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KVM: nVMX: Copy VMCS12 to processor-specific shadow vmcs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
ff2f6fe9
NHE		 359
360 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
361 struct list_head vmcs02_pool;
362 int vmcs02_num;
fe3ef05c 363 u64 vmcs01_tsc_offset;
644d711a
NHE		 364 /* L2 must run next, and mustn't decide to exit to L1. */
365 bool nested_run_pending;
fe3ef05c
NHE		 366 /*
367 * Guest pages referred to in vmcs02 with host-physical pointers, so
368 * we must keep them pinned while L2 runs.
369 */
370 struct page *apic_access_page;
ec378aee
NHE		 371};
372
01e439be
YZ		 373#define POSTED_INTR_ON 0
374/* Posted-Interrupt Descriptor */
375struct pi_desc {
376 u32 pir[8]; /* Posted interrupt requested */
377 u32 control; /* bit 0 of control is outstanding notification bit */
378 u32 rsvd[7];
379} __aligned(64);
380
a20ed54d
YZ		 381static bool pi_test_and_set_on(struct pi_desc *pi_desc)
382{
383 return test_and_set_bit(POSTED_INTR_ON,
384 (unsigned long *)&pi_desc->control);
385}
386
387static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
388{
389 return test_and_clear_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
394{
395 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
396}
397
a2fa3e9f 398struct vcpu_vmx {
fb3f0f51 399 struct kvm_vcpu vcpu;
313dbd49 400 unsigned long host_rsp;
29bd8a78 401 u8 fail;
69c73028 402 u8 cpl;
9d58b931 403 bool nmi_known_unmasked;
51aa01d1 404 u32 exit_intr_info;
1155f76a 405 u32 idt_vectoring_info;
6de12732 406 ulong rflags;
26bb0981 407 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 408 int nmsrs;
409 int save_nmsrs;
a547c6db 410 unsigned long host_idt_base;
a2fa3e9f 411#ifdef CONFIG_X86_64
44ea2b17
AK		 412 u64 msr_host_kernel_gs_base;
413 u64 msr_guest_kernel_gs_base;
a2fa3e9f 414#endif
d462b819
NHE		 415 /*
416 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
417 * non-nested (L1) guest, it always points to vmcs01. For a nested
418 * guest (L2), it points to a different VMCS.
419 */
420 struct loaded_vmcs vmcs01;
421 struct loaded_vmcs *loaded_vmcs;
422 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 423 struct msr_autoload {
424 unsigned nr;
425 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
426 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
427 } msr_autoload;
a2fa3e9f
GH		 428 struct {
429 int loaded;
430 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 431#ifdef CONFIG_X86_64
432 u16 ds_sel, es_sel;
433#endif
152d3f2f
LV		 434 int gs_ldt_reload_needed;
435 int fs_reload_needed;
d77c26fc 436 } host_state;
9c8cba37 437 struct {
7ffd92c5 438 int vm86_active;
78ac8b47 439 ulong save_rflags;
f5f7b2fe
AK		 440 struct kvm_segment segs[8];
441 } rmode;
442 struct {
443 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 444 struct kvm_save_segment {
445 u16 selector;
446 unsigned long base;
447 u32 limit;
448 u32 ar;
f5f7b2fe 449 } seg[8];
2fb92db1 450 } segment_cache;
2384d2b3 451 int vpid;
04fa4d32 452 bool emulation_required;
3b86cd99
JK		 453
454 /* Support for vnmi-less CPUs */
455 int soft_vnmi_blocked;
456 ktime_t entry_time;
457 s64 vnmi_blocked_time;
a0861c02 458 u32 exit_reason;
4e47c7a6
SY		 459
460 bool rdtscp_enabled;
ec378aee 461
01e439be
YZ		 462 /* Posted interrupt descriptor */
463 struct pi_desc pi_desc;
464
ec378aee
NHE		 465 /* Support for a guest hypervisor (nested VMX) */
466 struct nested_vmx nested;
a2fa3e9f
GH		 467};
468
2fb92db1
AK		 469enum segment_cache_field {
470 SEG_FIELD_SEL = 0,
471 SEG_FIELD_BASE = 1,
472 SEG_FIELD_LIMIT = 2,
473 SEG_FIELD_AR = 3,
474
475 SEG_FIELD_NR = 4
476};
477
a2fa3e9f
GH		 478static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
479{
fb3f0f51 480 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 481}
482
22bd0358
NHE		 483#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
484#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
485#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
486 [number##_HIGH] = VMCS12_OFFSET(name)+4
487
4607c2d7
AG		 488
489static const unsigned long shadow_read_only_fields[] = {
490 /*
491 * We do NOT shadow fields that are modified when L0
492 * traps and emulates any vmx instruction (e.g. VMPTRLD,
493 * VMXON...) executed by L1.
494 * For example, VM_INSTRUCTION_ERROR is read
495 * by L1 if a vmx instruction fails (part of the error path).
496 * Note the code assumes this logic. If for some reason
497 * we start shadowing these fields then we need to
498 * force a shadow sync when L0 emulates vmx instructions
499 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
500 * by nested_vmx_failValid)
501 */
502 VM_EXIT_REASON,
503 VM_EXIT_INTR_INFO,
504 VM_EXIT_INSTRUCTION_LEN,
505 IDT_VECTORING_INFO_FIELD,
506 IDT_VECTORING_ERROR_CODE,
507 VM_EXIT_INTR_ERROR_CODE,
508 EXIT_QUALIFICATION,
509 GUEST_LINEAR_ADDRESS,
510 GUEST_PHYSICAL_ADDRESS
511};
512static const int max_shadow_read_only_fields =
513 ARRAY_SIZE(shadow_read_only_fields);
514
515static const unsigned long shadow_read_write_fields[] = {
516 GUEST_RIP,
517 GUEST_RSP,
518 GUEST_CR0,
519 GUEST_CR3,
520 GUEST_CR4,
521 GUEST_INTERRUPTIBILITY_INFO,
522 GUEST_RFLAGS,
523 GUEST_CS_SELECTOR,
524 GUEST_CS_AR_BYTES,
525 GUEST_CS_LIMIT,
526 GUEST_CS_BASE,
527 GUEST_ES_BASE,
528 CR0_GUEST_HOST_MASK,
529 CR0_READ_SHADOW,
530 CR4_READ_SHADOW,
531 TSC_OFFSET,
532 EXCEPTION_BITMAP,
533 CPU_BASED_VM_EXEC_CONTROL,
534 VM_ENTRY_EXCEPTION_ERROR_CODE,
535 VM_ENTRY_INTR_INFO_FIELD,
536 VM_ENTRY_INSTRUCTION_LEN,
537 VM_ENTRY_EXCEPTION_ERROR_CODE,
538 HOST_FS_BASE,
539 HOST_GS_BASE,
540 HOST_FS_SELECTOR,
541 HOST_GS_SELECTOR
542};
543static const int max_shadow_read_write_fields =
544 ARRAY_SIZE(shadow_read_write_fields);
545
772e0318 546static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 547 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
548 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
549 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
550 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
551 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
552 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
553 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
554 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
555 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
556 FIELD(HOST_ES_SELECTOR, host_es_selector),
557 FIELD(HOST_CS_SELECTOR, host_cs_selector),
558 FIELD(HOST_SS_SELECTOR, host_ss_selector),
559 FIELD(HOST_DS_SELECTOR, host_ds_selector),
560 FIELD(HOST_FS_SELECTOR, host_fs_selector),
561 FIELD(HOST_GS_SELECTOR, host_gs_selector),
562 FIELD(HOST_TR_SELECTOR, host_tr_selector),
563 FIELD64(IO_BITMAP_A, io_bitmap_a),
564 FIELD64(IO_BITMAP_B, io_bitmap_b),
565 FIELD64(MSR_BITMAP, msr_bitmap),
566 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
567 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
568 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
569 FIELD64(TSC_OFFSET, tsc_offset),
570 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
571 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
572 FIELD64(EPT_POINTER, ept_pointer),
573 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
574 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
575 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
576 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
577 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
578 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
579 FIELD64(GUEST_PDPTR0, guest_pdptr0),
580 FIELD64(GUEST_PDPTR1, guest_pdptr1),
581 FIELD64(GUEST_PDPTR2, guest_pdptr2),
582 FIELD64(GUEST_PDPTR3, guest_pdptr3),
583 FIELD64(HOST_IA32_PAT, host_ia32_pat),
584 FIELD64(HOST_IA32_EFER, host_ia32_efer),
585 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
586 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
587 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
588 FIELD(EXCEPTION_BITMAP, exception_bitmap),
589 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
590 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
591 FIELD(CR3_TARGET_COUNT, cr3_target_count),
592 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
593 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
594 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
595 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
596 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
597 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
598 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
599 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
600 FIELD(TPR_THRESHOLD, tpr_threshold),
601 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
602 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
603 FIELD(VM_EXIT_REASON, vm_exit_reason),
604 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
605 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
606 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
607 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
608 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
609 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
610 FIELD(GUEST_ES_LIMIT, guest_es_limit),
611 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
612 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
613 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
614 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
615 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
616 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
617 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
618 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
619 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
620 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
621 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
622 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
623 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
624 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
625 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
626 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
627 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
628 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
629 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
630 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
631 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 632 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 633 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
634 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
635 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
636 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
637 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
638 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
639 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
640 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
641 FIELD(EXIT_QUALIFICATION, exit_qualification),
642 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
643 FIELD(GUEST_CR0, guest_cr0),
644 FIELD(GUEST_CR3, guest_cr3),
645 FIELD(GUEST_CR4, guest_cr4),
646 FIELD(GUEST_ES_BASE, guest_es_base),
647 FIELD(GUEST_CS_BASE, guest_cs_base),
648 FIELD(GUEST_SS_BASE, guest_ss_base),
649 FIELD(GUEST_DS_BASE, guest_ds_base),
650 FIELD(GUEST_FS_BASE, guest_fs_base),
651 FIELD(GUEST_GS_BASE, guest_gs_base),
652 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
653 FIELD(GUEST_TR_BASE, guest_tr_base),
654 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
655 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
656 FIELD(GUEST_DR7, guest_dr7),
657 FIELD(GUEST_RSP, guest_rsp),
658 FIELD(GUEST_RIP, guest_rip),
659 FIELD(GUEST_RFLAGS, guest_rflags),
660 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
661 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
662 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
663 FIELD(HOST_CR0, host_cr0),
664 FIELD(HOST_CR3, host_cr3),
665 FIELD(HOST_CR4, host_cr4),
666 FIELD(HOST_FS_BASE, host_fs_base),
667 FIELD(HOST_GS_BASE, host_gs_base),
668 FIELD(HOST_TR_BASE, host_tr_base),
669 FIELD(HOST_GDTR_BASE, host_gdtr_base),
670 FIELD(HOST_IDTR_BASE, host_idtr_base),
671 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
672 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
673 FIELD(HOST_RSP, host_rsp),
674 FIELD(HOST_RIP, host_rip),
675};
676static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
677
678static inline short vmcs_field_to_offset(unsigned long field)
679{
680 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
681 return -1;
682 return vmcs_field_to_offset_table[field];
683}
684
a9d30f33
NHE		 685static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
686{
687 return to_vmx(vcpu)->nested.current_vmcs12;
688}
689
690static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
691{
692 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 693 if (is_error_page(page))
a9d30f33 694 return NULL;
32cad84f 695
a9d30f33
NHE		 696 return page;
697}
698
699static void nested_release_page(struct page *page)
700{
701 kvm_release_page_dirty(page);
702}
703
704static void nested_release_page_clean(struct page *page)
705{
706 kvm_release_page_clean(page);
707}
708
4e1096d2 709static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 710static void kvm_cpu_vmxon(u64 addr);
711static void kvm_cpu_vmxoff(void);
aff48baa 712static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 713static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 714static void vmx_set_segment(struct kvm_vcpu *vcpu,
715 struct kvm_segment *var, int seg);
716static void vmx_get_segment(struct kvm_vcpu *vcpu,
717 struct kvm_segment *var, int seg);
d99e4152
GN		 718static bool guest_state_valid(struct kvm_vcpu *vcpu);
719static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 720static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 721static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 722static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 723
6aa8b732
AK		 724static DEFINE_PER_CPU(struct vmcs *, vmxarea);
725static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 726/*
727 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
728 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
729 */
730static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 731static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 732
3e7c73e9
AK		 733static unsigned long *vmx_io_bitmap_a;
734static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 735static unsigned long *vmx_msr_bitmap_legacy;
736static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 737static unsigned long *vmx_msr_bitmap_legacy_x2apic;
738static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 739static unsigned long *vmx_vmread_bitmap;
740static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 741
110312c8 742static bool cpu_has_load_ia32_efer;
8bf00a52 743static bool cpu_has_load_perf_global_ctrl;
110312c8 744
2384d2b3
SY		 745static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
746static DEFINE_SPINLOCK(vmx_vpid_lock);
747
1c3d14fe 748static struct vmcs_config {
6aa8b732
AK		 749 int size;
750 int order;
751 u32 revision_id;
1c3d14fe
YS		 752 u32 pin_based_exec_ctrl;
753 u32 cpu_based_exec_ctrl;
f78e0e2e 754 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 755 u32 vmexit_ctrl;
756 u32 vmentry_ctrl;
757} vmcs_config;
6aa8b732 758
efff9e53 759static struct vmx_capability {
d56f546d
SY		 760 u32 ept;
761 u32 vpid;
762} vmx_capability;
763
6aa8b732
AK		 764#define VMX_SEGMENT_FIELD(seg) \
765 [VCPU_SREG_##seg] = { \
766 .selector = GUEST_##seg##_SELECTOR, \
767 .base = GUEST_##seg##_BASE, \
768 .limit = GUEST_##seg##_LIMIT, \
769 .ar_bytes = GUEST_##seg##_AR_BYTES, \
770 }
771
772e0318 772static const struct kvm_vmx_segment_field {
6aa8b732
AK		 773 unsigned selector;
774 unsigned base;
775 unsigned limit;
776 unsigned ar_bytes;
777} kvm_vmx_segment_fields[] = {
778 VMX_SEGMENT_FIELD(CS),
779 VMX_SEGMENT_FIELD(DS),
780 VMX_SEGMENT_FIELD(ES),
781 VMX_SEGMENT_FIELD(FS),
782 VMX_SEGMENT_FIELD(GS),
783 VMX_SEGMENT_FIELD(SS),
784 VMX_SEGMENT_FIELD(TR),
785 VMX_SEGMENT_FIELD(LDTR),
786};
787
26bb0981
AK		 788static u64 host_efer;
789
6de4f3ad
AK		 790static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
791
4d56c8a7 792/*
8c06585d 793 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 794 * away by decrementing the array size.
795 */
6aa8b732 796static const u32 vmx_msr_index[] = {
05b3e0c2 797#ifdef CONFIG_X86_64
44ea2b17 798 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 799#endif
8c06585d 800 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 801};
9d8f549d 802#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 803
31299944 804static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 805{
806 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
807 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 808 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 809}
810
31299944 811static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 812{
813 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
814 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 815 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 816}
817
31299944 818static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 819{
820 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
821 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 822 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 823}
824
31299944 825static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 826{
827 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
828 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
829}
830
31299944 831static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
834 INTR_INFO_VALID_MASK)) ==
835 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
836}
837
31299944 838static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 839{
04547156 840 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 841}
842
31299944 843static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 844{
04547156 845 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 846}
847
31299944 848static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 849{
04547156 850 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 851}
852
31299944 853static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 854{
04547156
SY		 855 return vmcs_config.cpu_based_exec_ctrl &
856 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 857}
858
774ead3a 859static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_2nd_exec_ctrl &
862 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
863}
864
8d14695f
YZ		 865static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
866{
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
869}
870
83d4c286
YZ		 871static inline bool cpu_has_vmx_apic_register_virt(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_APIC_REGISTER_VIRT;
875}
876
c7c9c56c
YZ		 877static inline bool cpu_has_vmx_virtual_intr_delivery(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
881}
882
01e439be
YZ		 883static inline bool cpu_has_vmx_posted_intr(void)
884{
885 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
886}
887
888static inline bool cpu_has_vmx_apicv(void)
889{
890 return cpu_has_vmx_apic_register_virt() &&
891 cpu_has_vmx_virtual_intr_delivery() &&
892 cpu_has_vmx_posted_intr();
893}
894
04547156
SY		 895static inline bool cpu_has_vmx_flexpriority(void)
896{
897 return cpu_has_vmx_tpr_shadow() &&
898 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 899}
900
e799794e
MT		 901static inline bool cpu_has_vmx_ept_execute_only(void)
902{
31299944 903 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 904}
905
906static inline bool cpu_has_vmx_eptp_uncacheable(void)
907{
31299944 908 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 909}
910
911static inline bool cpu_has_vmx_eptp_writeback(void)
912{
31299944 913 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 914}
915
916static inline bool cpu_has_vmx_ept_2m_page(void)
917{
31299944 918 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 919}
920
878403b7
SY		 921static inline bool cpu_has_vmx_ept_1g_page(void)
922{
31299944 923 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 924}
925
4bc9b982
SY		 926static inline bool cpu_has_vmx_ept_4levels(void)
927{
928 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
929}
930
83c3a331
XH		 931static inline bool cpu_has_vmx_ept_ad_bits(void)
932{
933 return vmx_capability.ept & VMX_EPT_AD_BIT;
934}
935
31299944 936static inline bool cpu_has_vmx_invept_context(void)
d56f546d 937{
31299944 938 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 939}
940
31299944 941static inline bool cpu_has_vmx_invept_global(void)
d56f546d 942{
31299944 943 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 944}
945
518c8aee
GJ		 946static inline bool cpu_has_vmx_invvpid_single(void)
947{
948 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
949}
950
b9d762fa
GJ		 951static inline bool cpu_has_vmx_invvpid_global(void)
952{
953 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
954}
955
31299944 956static inline bool cpu_has_vmx_ept(void)
d56f546d 957{
04547156
SY		 958 return vmcs_config.cpu_based_2nd_exec_ctrl &
959 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 960}
961
31299944 962static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 963{
964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_UNRESTRICTED_GUEST;
966}
967
31299944 968static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
972}
973
31299944 974static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 975{
6d3e435e 976 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 977}
978
31299944 979static inline bool cpu_has_vmx_vpid(void)
2384d2b3 980{
04547156
SY		 981 return vmcs_config.cpu_based_2nd_exec_ctrl &
982 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 986{
987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_RDTSCP;
989}
990
ad756a16
MJ		 991static inline bool cpu_has_vmx_invpcid(void)
992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_ENABLE_INVPCID;
995}
996
31299944 997static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 998{
999 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1000}
1001
f5f48ee1
SY		 1002static inline bool cpu_has_vmx_wbinvd_exit(void)
1003{
1004 return vmcs_config.cpu_based_2nd_exec_ctrl &
1005 SECONDARY_EXEC_WBINVD_EXITING;
1006}
1007
abc4fc58
AG		 1008static inline bool cpu_has_vmx_shadow_vmcs(void)
1009{
1010 u64 vmx_msr;
1011 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1012 /* check if the cpu supports writing r/o exit information fields */
1013 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1014 return false;
1015
1016 return vmcs_config.cpu_based_2nd_exec_ctrl &
1017 SECONDARY_EXEC_SHADOW_VMCS;
1018}
1019
04547156
SY		 1020static inline bool report_flexpriority(void)
1021{
1022 return flexpriority_enabled;
1023}
1024
fe3ef05c
NHE		 1025static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1026{
1027 return vmcs12->cpu_based_vm_exec_control & bit;
1028}
1029
1030static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1031{
1032 return (vmcs12->cpu_based_vm_exec_control &
1033 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1034 (vmcs12->secondary_vm_exec_control & bit);
1035}
1036
644d711a
NHE		 1037static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1038 struct kvm_vcpu *vcpu)
1039{
1040 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1041}
1042
1043static inline bool is_exception(u32 intr_info)
1044{
1045 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1046 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1047}
1048
1049static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1050static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1051 struct vmcs12 *vmcs12,
1052 u32 reason, unsigned long qualification);
1053
8b9cf98c 1054static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1055{
1056 int i;
1057
a2fa3e9f 1058 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1059 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1060 return i;
1061 return -1;
1062}
1063
2384d2b3
SY		 1064static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1065{
1066 struct {
1067 u64 vpid : 16;
1068 u64 rsvd : 48;
1069 u64 gva;
1070 } operand = { vpid, 0, gva };
1071
4ecac3fd 1072 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1073 /* CF==1 or ZF==1 --> rc = -1 */
1074 "; ja 1f ; ud2 ; 1:"
1075 : : "a"(&operand), "c"(ext) : "cc", "memory");
1076}
1077
1439442c
SY		 1078static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1079{
1080 struct {
1081 u64 eptp, gpa;
1082 } operand = {eptp, gpa};
1083
4ecac3fd 1084 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1085 /* CF==1 or ZF==1 --> rc = -1 */
1086 "; ja 1f ; ud2 ; 1:\n"
1087 : : "a" (&operand), "c" (ext) : "cc", "memory");
1088}
1089
26bb0981 1090static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1091{
1092 int i;
1093
8b9cf98c 1094 i = __find_msr_index(vmx, msr);
a75beee6 1095 if (i >= 0)
a2fa3e9f 1096 return &vmx->guest_msrs[i];
8b6d44c7 1097 return NULL;
7725f0ba
AK		 1098}
1099
6aa8b732
AK		 1100static void vmcs_clear(struct vmcs *vmcs)
1101{
1102 u64 phys_addr = __pa(vmcs);
1103 u8 error;
1104
4ecac3fd 1105 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1106 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1107 : "cc", "memory");
1108 if (error)
1109 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1110 vmcs, phys_addr);
1111}
1112
d462b819
NHE		 1113static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1114{
1115 vmcs_clear(loaded_vmcs->vmcs);
1116 loaded_vmcs->cpu = -1;
1117 loaded_vmcs->launched = 0;
1118}
1119
7725b894
DX		 1120static void vmcs_load(struct vmcs *vmcs)
1121{
1122 u64 phys_addr = __pa(vmcs);
1123 u8 error;
1124
1125 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1126 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1127 : "cc", "memory");
1128 if (error)
2844d849 1129 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1130 vmcs, phys_addr);
1131}
1132
8f536b76
ZY		 1133#ifdef CONFIG_KEXEC
1134/*
1135 * This bitmap is used to indicate whether the vmclear
1136 * operation is enabled on all cpus. All disabled by
1137 * default.
1138 */
1139static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1140
1141static inline void crash_enable_local_vmclear(int cpu)
1142{
1143 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1144}
1145
1146static inline void crash_disable_local_vmclear(int cpu)
1147{
1148 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1149}
1150
1151static inline int crash_local_vmclear_enabled(int cpu)
1152{
1153 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static void crash_vmclear_local_loaded_vmcss(void)
1157{
1158 int cpu = raw_smp_processor_id();
1159 struct loaded_vmcs *v;
1160
1161 if (!crash_local_vmclear_enabled(cpu))
1162 return;
1163
1164 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1165 loaded_vmcss_on_cpu_link)
1166 vmcs_clear(v->vmcs);
1167}
1168#else
1169static inline void crash_enable_local_vmclear(int cpu) { }
1170static inline void crash_disable_local_vmclear(int cpu) { }
1171#endif /* CONFIG_KEXEC */
1172
d462b819 1173static void __loaded_vmcs_clear(void *arg)
6aa8b732 1174{
d462b819 1175 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1176 int cpu = raw_smp_processor_id();
6aa8b732 1177
d462b819
NHE		 1178 if (loaded_vmcs->cpu != cpu)
1179 return; /* vcpu migration can race with cpu offline */
1180 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1181 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1182 crash_disable_local_vmclear(cpu);
d462b819 1183 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1184
1185 /*
1186 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1187 * is before setting loaded_vmcs->vcpu to -1 which is done in
1188 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1189 * then adds the vmcs into percpu list before it is deleted.
1190 */
1191 smp_wmb();
1192
d462b819 1193 loaded_vmcs_init(loaded_vmcs);
8f536b76 1194 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1195}
1196
d462b819 1197static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1198{
e6c7d321
XG		 1199 int cpu = loaded_vmcs->cpu;
1200
1201 if (cpu != -1)
1202 smp_call_function_single(cpu,
1203 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1204}
1205
1760dd49 1206static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1207{
1208 if (vmx->vpid == 0)
1209 return;
1210
518c8aee
GJ		 1211 if (cpu_has_vmx_invvpid_single())
1212 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1213}
1214
b9d762fa
GJ		 1215static inline void vpid_sync_vcpu_global(void)
1216{
1217 if (cpu_has_vmx_invvpid_global())
1218 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1219}
1220
1221static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1222{
1223 if (cpu_has_vmx_invvpid_single())
1760dd49 1224 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1225 else
1226 vpid_sync_vcpu_global();
1227}
1228
1439442c
SY		 1229static inline void ept_sync_global(void)
1230{
1231 if (cpu_has_vmx_invept_global())
1232 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1233}
1234
1235static inline void ept_sync_context(u64 eptp)
1236{
089d034e 1237 if (enable_ept) {
1439442c
SY		 1238 if (cpu_has_vmx_invept_context())
1239 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1240 else
1241 ept_sync_global();
1242 }
1243}
1244
96304217 1245static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1246{
5e520e62 1247 unsigned long value;
6aa8b732 1248
5e520e62
AK		 1249 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1250 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1251 return value;
1252}
1253
96304217 1254static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1255{
1256 return vmcs_readl(field);
1257}
1258
96304217 1259static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1260{
1261 return vmcs_readl(field);
1262}
1263
96304217 1264static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1265{
05b3e0c2 1266#ifdef CONFIG_X86_64
6aa8b732
AK		 1267 return vmcs_readl(field);
1268#else
1269 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1270#endif
1271}
1272
e52de1b8
AK		 1273static noinline void vmwrite_error(unsigned long field, unsigned long value)
1274{
1275 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1276 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1277 dump_stack();
1278}
1279
6aa8b732
AK		 1280static void vmcs_writel(unsigned long field, unsigned long value)
1281{
1282 u8 error;
1283
4ecac3fd 1284 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1285 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1286 if (unlikely(error))
1287 vmwrite_error(field, value);
6aa8b732
AK		 1288}
1289
1290static void vmcs_write16(unsigned long field, u16 value)
1291{
1292 vmcs_writel(field, value);
1293}
1294
1295static void vmcs_write32(unsigned long field, u32 value)
1296{
1297 vmcs_writel(field, value);
1298}
1299
1300static void vmcs_write64(unsigned long field, u64 value)
1301{
6aa8b732 1302 vmcs_writel(field, value);
7682f2d0 1303#ifndef CONFIG_X86_64
6aa8b732
AK		 1304 asm volatile ("");
1305 vmcs_writel(field+1, value >> 32);
1306#endif
1307}
1308
2ab455cc
AL		 1309static void vmcs_clear_bits(unsigned long field, u32 mask)
1310{
1311 vmcs_writel(field, vmcs_readl(field) & ~mask);
1312}
1313
1314static void vmcs_set_bits(unsigned long field, u32 mask)
1315{
1316 vmcs_writel(field, vmcs_readl(field) | mask);
1317}
1318
2fb92db1
AK		 1319static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1320{
1321 vmx->segment_cache.bitmask = 0;
1322}
1323
1324static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1325 unsigned field)
1326{
1327 bool ret;
1328 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1329
1330 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1331 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1332 vmx->segment_cache.bitmask = 0;
1333 }
1334 ret = vmx->segment_cache.bitmask & mask;
1335 vmx->segment_cache.bitmask |= mask;
1336 return ret;
1337}
1338
1339static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1340{
1341 u16 *p = &vmx->segment_cache.seg[seg].selector;
1342
1343 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1344 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1345 return *p;
1346}
1347
1348static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1349{
1350 ulong *p = &vmx->segment_cache.seg[seg].base;
1351
1352 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1353 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1354 return *p;
1355}
1356
1357static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1358{
1359 u32 *p = &vmx->segment_cache.seg[seg].limit;
1360
1361 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1362 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1363 return *p;
1364}
1365
1366static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1367{
1368 u32 *p = &vmx->segment_cache.seg[seg].ar;
1369
1370 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1371 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1372 return *p;
1373}
1374
abd3f2d6
AK		 1375static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1376{
1377 u32 eb;
1378
fd7373cc
JK		 1379 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1380 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1381 if ((vcpu->guest_debug &
1382 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1383 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1384 eb |= 1u << BP_VECTOR;
7ffd92c5 1385 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1386 eb = ~0;
089d034e 1387 if (enable_ept)
1439442c 1388 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1389 if (vcpu->fpu_active)
1390 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1391
1392 /* When we are running a nested L2 guest and L1 specified for it a
1393 * certain exception bitmap, we must trap the same exceptions and pass
1394 * them to L1. When running L2, we will only handle the exceptions
1395 * specified above if L1 did not want them.
1396 */
1397 if (is_guest_mode(vcpu))
1398 eb |= get_vmcs12(vcpu)->exception_bitmap;
1399
abd3f2d6
AK		 1400 vmcs_write32(EXCEPTION_BITMAP, eb);
1401}
1402
8bf00a52
GN		 1403static void clear_atomic_switch_msr_special(unsigned long entry,
1404 unsigned long exit)
1405{
1406 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1407 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1408}
1409
61d2ef2c
AK		 1410static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1411{
1412 unsigned i;
1413 struct msr_autoload *m = &vmx->msr_autoload;
1414
8bf00a52
GN		 1415 switch (msr) {
1416 case MSR_EFER:
1417 if (cpu_has_load_ia32_efer) {
1418 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1419 VM_EXIT_LOAD_IA32_EFER);
1420 return;
1421 }
1422 break;
1423 case MSR_CORE_PERF_GLOBAL_CTRL:
1424 if (cpu_has_load_perf_global_ctrl) {
1425 clear_atomic_switch_msr_special(
1426 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1427 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1428 return;
1429 }
1430 break;
110312c8
AK		 1431 }
1432
61d2ef2c
AK		 1433 for (i = 0; i < m->nr; ++i)
1434 if (m->guest[i].index == msr)
1435 break;
1436
1437 if (i == m->nr)
1438 return;
1439 --m->nr;
1440 m->guest[i] = m->guest[m->nr];
1441 m->host[i] = m->host[m->nr];
1442 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1443 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1444}
1445
8bf00a52
GN		 1446static void add_atomic_switch_msr_special(unsigned long entry,
1447 unsigned long exit, unsigned long guest_val_vmcs,
1448 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1449{
1450 vmcs_write64(guest_val_vmcs, guest_val);
1451 vmcs_write64(host_val_vmcs, host_val);
1452 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1453 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1454}
1455
61d2ef2c
AK		 1456static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1457 u64 guest_val, u64 host_val)
1458{
1459 unsigned i;
1460 struct msr_autoload *m = &vmx->msr_autoload;
1461
8bf00a52
GN		 1462 switch (msr) {
1463 case MSR_EFER:
1464 if (cpu_has_load_ia32_efer) {
1465 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1466 VM_EXIT_LOAD_IA32_EFER,
1467 GUEST_IA32_EFER,
1468 HOST_IA32_EFER,
1469 guest_val, host_val);
1470 return;
1471 }
1472 break;
1473 case MSR_CORE_PERF_GLOBAL_CTRL:
1474 if (cpu_has_load_perf_global_ctrl) {
1475 add_atomic_switch_msr_special(
1476 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1477 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1478 GUEST_IA32_PERF_GLOBAL_CTRL,
1479 HOST_IA32_PERF_GLOBAL_CTRL,
1480 guest_val, host_val);
1481 return;
1482 }
1483 break;
110312c8
AK		 1484 }
1485
61d2ef2c
AK		 1486 for (i = 0; i < m->nr; ++i)
1487 if (m->guest[i].index == msr)
1488 break;
1489
e7fc6f93
GN		 1490 if (i == NR_AUTOLOAD_MSRS) {
1491 printk_once(KERN_WARNING"Not enough mst switch entries. "
1492 "Can't add msr %x\n", msr);
1493 return;
1494 } else if (i == m->nr) {
61d2ef2c
AK		 1495 ++m->nr;
1496 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1497 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1498 }
1499
1500 m->guest[i].index = msr;
1501 m->guest[i].value = guest_val;
1502 m->host[i].index = msr;
1503 m->host[i].value = host_val;
1504}
1505
33ed6329
AK		 1506static void reload_tss(void)
1507{
33ed6329
AK		 1508 /*
1509 * VT restores TR but not its size. Useless.
1510 */
d359192f 1511 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1512 struct desc_struct *descs;
33ed6329 1513
d359192f 1514 descs = (void *)gdt->address;
33ed6329
AK		 1515 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1516 load_TR_desc();
33ed6329
AK		 1517}
1518
92c0d900 1519static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1520{
3a34a881 1521 u64 guest_efer;
51c6cf66
AK		 1522 u64 ignore_bits;
1523
f6801dff 1524 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1525
51c6cf66 1526 /*
0fa06071 1527 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1528 * outside long mode
1529 */
1530 ignore_bits = EFER_NX | EFER_SCE;
1531#ifdef CONFIG_X86_64
1532 ignore_bits |= EFER_LMA | EFER_LME;
1533 /* SCE is meaningful only in long mode on Intel */
1534 if (guest_efer & EFER_LMA)
1535 ignore_bits &= ~(u64)EFER_SCE;
1536#endif
51c6cf66
AK		 1537 guest_efer &= ~ignore_bits;
1538 guest_efer |= host_efer & ignore_bits;
26bb0981 1539 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1540 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1541
1542 clear_atomic_switch_msr(vmx, MSR_EFER);
1543 /* On ept, can't emulate nx, and must switch nx atomically */
1544 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1545 guest_efer = vmx->vcpu.arch.efer;
1546 if (!(guest_efer & EFER_LMA))
1547 guest_efer &= ~EFER_LME;
1548 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1549 return false;
1550 }
1551
26bb0981 1552 return true;
51c6cf66
AK		 1553}
1554
2d49ec72
GN		 1555static unsigned long segment_base(u16 selector)
1556{
d359192f 1557 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1558 struct desc_struct *d;
1559 unsigned long table_base;
1560 unsigned long v;
1561
1562 if (!(selector & ~3))
1563 return 0;
1564
d359192f 1565 table_base = gdt->address;
2d49ec72
GN		 1566
1567 if (selector & 4) { /* from ldt */
1568 u16 ldt_selector = kvm_read_ldt();
1569
1570 if (!(ldt_selector & ~3))
1571 return 0;
1572
1573 table_base = segment_base(ldt_selector);
1574 }
1575 d = (struct desc_struct *)(table_base + (selector & ~7));
1576 v = get_desc_base(d);
1577#ifdef CONFIG_X86_64
1578 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1579 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1580#endif
1581 return v;
1582}
1583
1584static inline unsigned long kvm_read_tr_base(void)
1585{
1586 u16 tr;
1587 asm("str %0" : "=g"(tr));
1588 return segment_base(tr);
1589}
1590
04d2cc77 1591static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1592{
04d2cc77 1593 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1594 int i;
04d2cc77 1595
a2fa3e9f 1596 if (vmx->host_state.loaded)
33ed6329
AK		 1597 return;
1598
a2fa3e9f 1599 vmx->host_state.loaded = 1;
33ed6329
AK		 1600 /*
1601 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1602 * allow segment selectors with cpl > 0 or ti == 1.
1603 */
d6e88aec 1604 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1605 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1606 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1607 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1608 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1609 vmx->host_state.fs_reload_needed = 0;
1610 } else {
33ed6329 1611 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1612 vmx->host_state.fs_reload_needed = 1;
33ed6329 1613 }
9581d442 1614 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1615 if (!(vmx->host_state.gs_sel & 7))
1616 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1617 else {
1618 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1619 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1620 }
1621
b2da15ac
AK		 1622#ifdef CONFIG_X86_64
1623 savesegment(ds, vmx->host_state.ds_sel);
1624 savesegment(es, vmx->host_state.es_sel);
1625#endif
1626
33ed6329
AK		 1627#ifdef CONFIG_X86_64
1628 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1629 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1630#else
a2fa3e9f
GH		 1631 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1632 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1633#endif
707c0874
AK		 1634
1635#ifdef CONFIG_X86_64
c8770e7b
AK		 1636 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1637 if (is_long_mode(&vmx->vcpu))
44ea2b17 1638 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1639#endif
26bb0981
AK		 1640 for (i = 0; i < vmx->save_nmsrs; ++i)
1641 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1642 vmx->guest_msrs[i].data,
1643 vmx->guest_msrs[i].mask);
33ed6329
AK		 1644}
1645
a9b21b62 1646static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1647{
a2fa3e9f 1648 if (!vmx->host_state.loaded)
33ed6329
AK		 1649 return;
1650
e1beb1d3 1651 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1652 vmx->host_state.loaded = 0;
c8770e7b
AK		 1653#ifdef CONFIG_X86_64
1654 if (is_long_mode(&vmx->vcpu))
1655 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1656#endif
152d3f2f 1657 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1658 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1659#ifdef CONFIG_X86_64
9581d442 1660 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1661#else
1662 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1663#endif
33ed6329 1664 }
0a77fe4c
AK		 1665 if (vmx->host_state.fs_reload_needed)
1666 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1667#ifdef CONFIG_X86_64
1668 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1669 loadsegment(ds, vmx->host_state.ds_sel);
1670 loadsegment(es, vmx->host_state.es_sel);
1671 }
b2da15ac 1672#endif
152d3f2f 1673 reload_tss();
44ea2b17 1674#ifdef CONFIG_X86_64
c8770e7b 1675 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1676#endif
b1a74bf8
SS		 1677 /*
1678 * If the FPU is not active (through the host task or
1679 * the guest vcpu), then restore the cr0.TS bit.
1680 */
1681 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1682 stts();
3444d7da 1683 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1684}
1685
a9b21b62
AK		 1686static void vmx_load_host_state(struct vcpu_vmx *vmx)
1687{
1688 preempt_disable();
1689 __vmx_load_host_state(vmx);
1690 preempt_enable();
1691}
1692
6aa8b732
AK		 1693/*
1694 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1695 * vcpu mutex is already taken.
1696 */
15ad7146 1697static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1698{
a2fa3e9f 1699 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1700 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1701
4610c9cc
DX		 1702 if (!vmm_exclusive)
1703 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1704 else if (vmx->loaded_vmcs->cpu != cpu)
1705 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1706
d462b819
NHE		 1707 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1708 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1709 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1710 }
1711
d462b819 1712 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1713 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1714 unsigned long sysenter_esp;
1715
a8eeb04a 1716 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1717 local_irq_disable();
8f536b76 1718 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1719
1720 /*
1721 * Read loaded_vmcs->cpu should be before fetching
1722 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1723 * See the comments in __loaded_vmcs_clear().
1724 */
1725 smp_rmb();
1726
d462b819
NHE		 1727 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1728 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1729 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1730 local_irq_enable();
1731
6aa8b732
AK		 1732 /*
1733 * Linux uses per-cpu TSS and GDT, so set these when switching
1734 * processors.
1735 */
d6e88aec 1736 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1737 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1738
1739 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1740 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1741 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1742 }
6aa8b732
AK		 1743}
1744
1745static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1746{
a9b21b62 1747 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1748 if (!vmm_exclusive) {
d462b819
NHE		 1749 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1750 vcpu->cpu = -1;
4610c9cc
DX		 1751 kvm_cpu_vmxoff();
1752 }
6aa8b732
AK		 1753}
1754
5fd86fcf
AK		 1755static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1756{
81231c69
AK		 1757 ulong cr0;
1758
5fd86fcf
AK		 1759 if (vcpu->fpu_active)
1760 return;
1761 vcpu->fpu_active = 1;
81231c69
AK		 1762 cr0 = vmcs_readl(GUEST_CR0);
1763 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1764 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1765 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1766 update_exception_bitmap(vcpu);
edcafe3c 1767 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1768 if (is_guest_mode(vcpu))
1769 vcpu->arch.cr0_guest_owned_bits &=
1770 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1771 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1772}
1773
edcafe3c
AK		 1774static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1775
fe3ef05c
NHE		 1776/*
1777 * Return the cr0 value that a nested guest would read. This is a combination
1778 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1779 * its hypervisor (cr0_read_shadow).
1780 */
1781static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1782{
1783 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1784 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1785}
1786static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1787{
1788 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1789 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1790}
1791
5fd86fcf
AK		 1792static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1793{
36cf24e0
NHE		 1794 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1795 * set this *before* calling this function.
1796 */
edcafe3c 1797 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1798 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1799 update_exception_bitmap(vcpu);
edcafe3c
AK		 1800 vcpu->arch.cr0_guest_owned_bits = 0;
1801 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1802 if (is_guest_mode(vcpu)) {
1803 /*
1804 * L1's specified read shadow might not contain the TS bit,
1805 * so now that we turned on shadowing of this bit, we need to
1806 * set this bit of the shadow. Like in nested_vmx_run we need
1807 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1808 * up-to-date here because we just decached cr0.TS (and we'll
1809 * only update vmcs12->guest_cr0 on nested exit).
1810 */
1811 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1812 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1813 (vcpu->arch.cr0 & X86_CR0_TS);
1814 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1815 } else
1816 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1817}
1818
6aa8b732
AK		 1819static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1820{
78ac8b47 1821 unsigned long rflags, save_rflags;
345dcaa8 1822
6de12732
AK		 1823 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1824 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1825 rflags = vmcs_readl(GUEST_RFLAGS);
1826 if (to_vmx(vcpu)->rmode.vm86_active) {
1827 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1828 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1829 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1830 }
1831 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1832 }
6de12732 1833 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1834}
1835
1836static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1837{
6de12732
AK		 1838 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1839 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1840 if (to_vmx(vcpu)->rmode.vm86_active) {
1841 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1842 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1843 }
6aa8b732
AK		 1844 vmcs_writel(GUEST_RFLAGS, rflags);
1845}
1846
2809f5d2
GC		 1847static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1848{
1849 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1850 int ret = 0;
1851
1852 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1853 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1854 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1855 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1856
1857 return ret & mask;
1858}
1859
1860static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1861{
1862 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1863 u32 interruptibility = interruptibility_old;
1864
1865 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1866
48005f64 1867 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1868 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1869 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1870 interruptibility |= GUEST_INTR_STATE_STI;
1871
1872 if ((interruptibility != interruptibility_old))
1873 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1874}
1875
6aa8b732
AK		 1876static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1877{
1878 unsigned long rip;
6aa8b732 1879
5fdbf976 1880 rip = kvm_rip_read(vcpu);
6aa8b732 1881 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1882 kvm_rip_write(vcpu, rip);
6aa8b732 1883
2809f5d2
GC		 1884 /* skipping an emulated instruction also counts */
1885 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1886}
1887
0b6ac343
NHE		 1888/*
1889 * KVM wants to inject page-faults which it got to the guest. This function
1890 * checks whether in a nested guest, we need to inject them to L1 or L2.
1891 * This function assumes it is called with the exit reason in vmcs02 being
1892 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1893 * is running).
1894 */
1895static int nested_pf_handled(struct kvm_vcpu *vcpu)
1896{
1897 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1898
1899 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1900 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1901 return 0;
1902
1903 nested_vmx_vmexit(vcpu);
1904 return 1;
1905}
1906
298101da 1907static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1908 bool has_error_code, u32 error_code,
1909 bool reinject)
298101da 1910{
77ab6db0 1911 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1912 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1913
0b6ac343
NHE		 1914 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1915 nested_pf_handled(vcpu))
1916 return;
1917
8ab2d2e2 1918 if (has_error_code) {
77ab6db0 1919 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1920 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1921 }
77ab6db0 1922
7ffd92c5 1923 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1924 int inc_eip = 0;
1925 if (kvm_exception_is_soft(nr))
1926 inc_eip = vcpu->arch.event_exit_inst_len;
1927 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1928 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1929 return;
1930 }
1931
66fd3f7f
GN		 1932 if (kvm_exception_is_soft(nr)) {
1933 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1934 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1935 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1936 } else
1937 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1938
1939 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1940}
1941
4e47c7a6
SY		 1942static bool vmx_rdtscp_supported(void)
1943{
1944 return cpu_has_vmx_rdtscp();
1945}
1946
ad756a16
MJ		 1947static bool vmx_invpcid_supported(void)
1948{
1949 return cpu_has_vmx_invpcid() && enable_ept;
1950}
1951
a75beee6
ED		 1952/*
1953 * Swap MSR entry in host/guest MSR entry array.
1954 */
8b9cf98c 1955static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1956{
26bb0981 1957 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1958
1959 tmp = vmx->guest_msrs[to];
1960 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1961 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1962}
1963
8d14695f
YZ		 1964static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1965{
1966 unsigned long *msr_bitmap;
1967
1968 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1969 if (is_long_mode(vcpu))
1970 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1971 else
1972 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1973 } else {
1974 if (is_long_mode(vcpu))
1975 msr_bitmap = vmx_msr_bitmap_longmode;
1976 else
1977 msr_bitmap = vmx_msr_bitmap_legacy;
1978 }
1979
1980 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1981}
1982
e38aea3e
AK		 1983/*
1984 * Set up the vmcs to automatically save and restore system
1985 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1986 * mode, as fiddling with msrs is very expensive.
1987 */
8b9cf98c 1988static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1989{
26bb0981 1990 int save_nmsrs, index;
e38aea3e 1991
a75beee6
ED		 1992 save_nmsrs = 0;
1993#ifdef CONFIG_X86_64
8b9cf98c 1994 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1995 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1996 if (index >= 0)
8b9cf98c
RR		 1997 move_msr_up(vmx, index, save_nmsrs++);
1998 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1999 if (index >= 0)
8b9cf98c
RR		 2000 move_msr_up(vmx, index, save_nmsrs++);
2001 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2002 if (index >= 0)
8b9cf98c 2003 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2004 index = __find_msr_index(vmx, MSR_TSC_AUX);
2005 if (index >= 0 && vmx->rdtscp_enabled)
2006 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2007 /*
8c06585d 2008 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2009 * if efer.sce is enabled.
2010 */
8c06585d 2011 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2012 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2013 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2014 }
2015#endif
92c0d900
AK		 2016 index = __find_msr_index(vmx, MSR_EFER);
2017 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2018 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2019
26bb0981 2020 vmx->save_nmsrs = save_nmsrs;
5897297b 2021
8d14695f
YZ		 2022 if (cpu_has_vmx_msr_bitmap())
2023 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2024}
2025
6aa8b732
AK		 2026/*
2027 * reads and returns guest's timestamp counter "register"
2028 * guest_tsc = host_tsc + tsc_offset -- 21.3
2029 */
2030static u64 guest_read_tsc(void)
2031{
2032 u64 host_tsc, tsc_offset;
2033
2034 rdtscll(host_tsc);
2035 tsc_offset = vmcs_read64(TSC_OFFSET);
2036 return host_tsc + tsc_offset;
2037}
2038
d5c1785d
NHE		 2039/*
2040 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2041 * counter, even if a nested guest (L2) is currently running.
2042 */
886b470c 2043u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2044{
886b470c 2045 u64 tsc_offset;
d5c1785d 2046
d5c1785d
NHE		 2047 tsc_offset = is_guest_mode(vcpu) ?
2048 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2049 vmcs_read64(TSC_OFFSET);
2050 return host_tsc + tsc_offset;
2051}
2052
4051b188 2053/*
cc578287
ZA		 2054 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2055 * software catchup for faster rates on slower CPUs.
4051b188 2056 */
cc578287 2057static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2058{
cc578287
ZA		 2059 if (!scale)
2060 return;
2061
2062 if (user_tsc_khz > tsc_khz) {
2063 vcpu->arch.tsc_catchup = 1;
2064 vcpu->arch.tsc_always_catchup = 1;
2065 } else
2066 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2067}
2068
ba904635
WA		 2069static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2070{
2071 return vmcs_read64(TSC_OFFSET);
2072}
2073
6aa8b732 2074/*
99e3e30a 2075 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2076 */
99e3e30a 2077static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2078{
27fc51b2 2079 if (is_guest_mode(vcpu)) {
7991825b 2080 /*
27fc51b2
NHE		 2081 * We're here if L1 chose not to trap WRMSR to TSC. According
2082 * to the spec, this should set L1's TSC; The offset that L1
2083 * set for L2 remains unchanged, and still needs to be added
2084 * to the newly set TSC to get L2's TSC.
7991825b 2085 */
27fc51b2
NHE		 2086 struct vmcs12 *vmcs12;
2087 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2088 /* recalculate vmcs02.TSC_OFFSET: */
2089 vmcs12 = get_vmcs12(vcpu);
2090 vmcs_write64(TSC_OFFSET, offset +
2091 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2092 vmcs12->tsc_offset : 0));
2093 } else {
2094 vmcs_write64(TSC_OFFSET, offset);
2095 }
6aa8b732
AK		 2096}
2097
f1e2b260 2098static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2099{
2100 u64 offset = vmcs_read64(TSC_OFFSET);
2101 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2102 if (is_guest_mode(vcpu)) {
2103 /* Even when running L2, the adjustment needs to apply to L1 */
2104 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2105 }
e48672fa
ZA		 2106}
2107
857e4099
JR		 2108static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2109{
2110 return target_tsc - native_read_tsc();
2111}
2112
801d3424
NHE		 2113static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2114{
2115 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2116 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2117}
2118
2119/*
2120 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2121 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2122 * all guests if the "nested" module option is off, and can also be disabled
2123 * for a single guest by disabling its VMX cpuid bit.
2124 */
2125static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2126{
2127 return nested && guest_cpuid_has_vmx(vcpu);
2128}
2129
b87a51ae
NHE		 2130/*
2131 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2132 * returned for the various VMX controls MSRs when nested VMX is enabled.
2133 * The same values should also be used to verify that vmcs12 control fields are
2134 * valid during nested entry from L1 to L2.
2135 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2136 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2137 * bit in the high half is on if the corresponding bit in the control field
2138 * may be on. See also vmx_control_verify().
2139 * TODO: allow these variables to be modified (downgraded) by module options
2140 * or other means.
2141 */
2142static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2143static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2144static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2145static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2146static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2147static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2148static __init void nested_vmx_setup_ctls_msrs(void)
2149{
2150 /*
2151 * Note that as a general rule, the high half of the MSRs (bits in
2152 * the control fields which may be 1) should be initialized by the
2153 * intersection of the underlying hardware's MSR (i.e., features which
2154 * can be supported) and the list of features we want to expose -
2155 * because they are known to be properly supported in our code.
2156 * Also, usually, the low half of the MSRs (bits which must be 1) can
2157 * be set to 0, meaning that L1 may turn off any of these bits. The
2158 * reason is that if one of these bits is necessary, it will appear
2159 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2160 * fields of vmcs01 and vmcs02, will turn these bits off - and
2161 * nested_vmx_exit_handled() will not pass related exits to L1.
2162 * These rules have exceptions below.
2163 */
2164
2165 /* pin-based controls */
eabeaacc
JK		 2166 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2167 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2168 /*
2169 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2170 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2171 */
eabeaacc
JK		 2172 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2173 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2174 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2175 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2176 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2177
33fb20c3
JK		 2178 /*
2179 * Exit controls
2180 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2181 * 17 must be 1.
2182 */
2183 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2184 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2185#ifdef CONFIG_X86_64
2186 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2187#else
2188 nested_vmx_exit_ctls_high = 0;
2189#endif
33fb20c3 2190 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2191
2192 /* entry controls */
2193 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2194 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2195 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2196 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2197 nested_vmx_entry_ctls_high &=
2198 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2199 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2200
2201 /* cpu-based controls */
2202 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2203 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2204 nested_vmx_procbased_ctls_low = 0;
2205 nested_vmx_procbased_ctls_high &=
2206 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2207 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2208 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2209 CPU_BASED_CR3_STORE_EXITING |
2210#ifdef CONFIG_X86_64
2211 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2212#endif
2213 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2214 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2215 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2216 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2217 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2218 /*
2219 * We can allow some features even when not supported by the
2220 * hardware. For example, L1 can specify an MSR bitmap - and we
2221 * can use it to avoid exits to L1 - even when L0 runs L2
2222 * without MSR bitmaps.
2223 */
2224 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2225
2226 /* secondary cpu-based controls */
2227 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2228 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2229 nested_vmx_secondary_ctls_low = 0;
2230 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2231 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2232 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2233
2234 /* miscellaneous data */
2235 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2236 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2237 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2238 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2239}
2240
2241static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2242{
2243 /*
2244 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2245 */
2246 return ((control & high) | low) == control;
2247}
2248
2249static inline u64 vmx_control_msr(u32 low, u32 high)
2250{
2251 return low | ((u64)high << 32);
2252}
2253
2254/*
2255 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2256 * also let it use VMX-specific MSRs.
2257 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2258 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2259 * like all other MSRs).
2260 */
2261static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2262{
2263 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2264 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2265 /*
2266 * According to the spec, processors which do not support VMX
2267 * should throw a #GP(0) when VMX capability MSRs are read.
2268 */
2269 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2270 return 1;
2271 }
2272
2273 switch (msr_index) {
2274 case MSR_IA32_FEATURE_CONTROL:
2275 *pdata = 0;
2276 break;
2277 case MSR_IA32_VMX_BASIC:
2278 /*
2279 * This MSR reports some information about VMX support. We
2280 * should return information about the VMX we emulate for the
2281 * guest, and the VMCS structure we give it - not about the
2282 * VMX support of the underlying hardware.
2283 */
2284 *pdata = VMCS12_REVISION |
2285 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2286 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2287 break;
2288 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2289 case MSR_IA32_VMX_PINBASED_CTLS:
2290 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2291 nested_vmx_pinbased_ctls_high);
2292 break;
2293 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2294 case MSR_IA32_VMX_PROCBASED_CTLS:
2295 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2296 nested_vmx_procbased_ctls_high);
2297 break;
2298 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2299 case MSR_IA32_VMX_EXIT_CTLS:
2300 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2301 nested_vmx_exit_ctls_high);
2302 break;
2303 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2304 case MSR_IA32_VMX_ENTRY_CTLS:
2305 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2306 nested_vmx_entry_ctls_high);
2307 break;
2308 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2309 *pdata = vmx_control_msr(nested_vmx_misc_low,
2310 nested_vmx_misc_high);
b87a51ae
NHE		 2311 break;
2312 /*
2313 * These MSRs specify bits which the guest must keep fixed (on or off)
2314 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2315 * We picked the standard core2 setting.
2316 */
2317#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2318#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2319 case MSR_IA32_VMX_CR0_FIXED0:
2320 *pdata = VMXON_CR0_ALWAYSON;
2321 break;
2322 case MSR_IA32_VMX_CR0_FIXED1:
2323 *pdata = -1ULL;
2324 break;
2325 case MSR_IA32_VMX_CR4_FIXED0:
2326 *pdata = VMXON_CR4_ALWAYSON;
2327 break;
2328 case MSR_IA32_VMX_CR4_FIXED1:
2329 *pdata = -1ULL;
2330 break;
2331 case MSR_IA32_VMX_VMCS_ENUM:
2332 *pdata = 0x1f;
2333 break;
2334 case MSR_IA32_VMX_PROCBASED_CTLS2:
2335 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2336 nested_vmx_secondary_ctls_high);
2337 break;
2338 case MSR_IA32_VMX_EPT_VPID_CAP:
2339 /* Currently, no nested ept or nested vpid */
2340 *pdata = 0;
2341 break;
2342 default:
2343 return 0;
2344 }
2345
2346 return 1;
2347}
2348
2349static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2350{
2351 if (!nested_vmx_allowed(vcpu))
2352 return 0;
2353
2354 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2355 /* TODO: the right thing. */
2356 return 1;
2357 /*
2358 * No need to treat VMX capability MSRs specially: If we don't handle
2359 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2360 */
2361 return 0;
2362}
2363
6aa8b732
AK		 2364/*
2365 * Reads an msr value (of 'msr_index') into 'pdata'.
2366 * Returns 0 on success, non-0 otherwise.
2367 * Assumes vcpu_load() was already called.
2368 */
2369static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2370{
2371 u64 data;
26bb0981 2372 struct shared_msr_entry *msr;
6aa8b732
AK		 2373
2374 if (!pdata) {
2375 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2376 return -EINVAL;
2377 }
2378
2379 switch (msr_index) {
05b3e0c2 2380#ifdef CONFIG_X86_64
6aa8b732
AK		 2381 case MSR_FS_BASE:
2382 data = vmcs_readl(GUEST_FS_BASE);
2383 break;
2384 case MSR_GS_BASE:
2385 data = vmcs_readl(GUEST_GS_BASE);
2386 break;
44ea2b17
AK		 2387 case MSR_KERNEL_GS_BASE:
2388 vmx_load_host_state(to_vmx(vcpu));
2389 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2390 break;
26bb0981 2391#endif
6aa8b732 2392 case MSR_EFER:
3bab1f5d 2393 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2394 case MSR_IA32_TSC:
6aa8b732
AK		 2395 data = guest_read_tsc();
2396 break;
2397 case MSR_IA32_SYSENTER_CS:
2398 data = vmcs_read32(GUEST_SYSENTER_CS);
2399 break;
2400 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2401 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2402 break;
2403 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2404 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2405 break;
4e47c7a6
SY		 2406 case MSR_TSC_AUX:
2407 if (!to_vmx(vcpu)->rdtscp_enabled)
2408 return 1;
2409 /* Otherwise falls through */
6aa8b732 2410 default:
b87a51ae
NHE		 2411 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2412 return 0;
8b9cf98c 2413 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2414 if (msr) {
2415 data = msr->data;
2416 break;
6aa8b732 2417 }
3bab1f5d 2418 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2419 }
2420
2421 *pdata = data;
2422 return 0;
2423}
2424
2425/*
2426 * Writes msr value into into the appropriate "register".
2427 * Returns 0 on success, non-0 otherwise.
2428 * Assumes vcpu_load() was already called.
2429 */
8fe8ab46 2430static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2431{
a2fa3e9f 2432 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2433 struct shared_msr_entry *msr;
2cc51560 2434 int ret = 0;
8fe8ab46
WA		 2435 u32 msr_index = msr_info->index;
2436 u64 data = msr_info->data;
2cc51560 2437
6aa8b732 2438 switch (msr_index) {
3bab1f5d 2439 case MSR_EFER:
8fe8ab46 2440 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2441 break;
16175a79 2442#ifdef CONFIG_X86_64
6aa8b732 2443 case MSR_FS_BASE:
2fb92db1 2444 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2445 vmcs_writel(GUEST_FS_BASE, data);
2446 break;
2447 case MSR_GS_BASE:
2fb92db1 2448 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2449 vmcs_writel(GUEST_GS_BASE, data);
2450 break;
44ea2b17
AK		 2451 case MSR_KERNEL_GS_BASE:
2452 vmx_load_host_state(vmx);
2453 vmx->msr_guest_kernel_gs_base = data;
2454 break;
6aa8b732
AK		 2455#endif
2456 case MSR_IA32_SYSENTER_CS:
2457 vmcs_write32(GUEST_SYSENTER_CS, data);
2458 break;
2459 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2460 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2461 break;
2462 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2463 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2464 break;
af24a4e4 2465 case MSR_IA32_TSC:
8fe8ab46 2466 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2467 break;
468d472f
SY		 2468 case MSR_IA32_CR_PAT:
2469 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2470 vmcs_write64(GUEST_IA32_PAT, data);
2471 vcpu->arch.pat = data;
2472 break;
2473 }
8fe8ab46 2474 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2475 break;
ba904635
WA		 2476 case MSR_IA32_TSC_ADJUST:
2477 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2478 break;
2479 case MSR_TSC_AUX:
2480 if (!vmx->rdtscp_enabled)
2481 return 1;
2482 /* Check reserved bit, higher 32 bits should be zero */
2483 if ((data >> 32) != 0)
2484 return 1;
2485 /* Otherwise falls through */
6aa8b732 2486 default:
b87a51ae
NHE		 2487 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2488 break;
8b9cf98c 2489 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2490 if (msr) {
2491 msr->data = data;
2225fd56
AK		 2492 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2493 preempt_disable();
9ee73970
AK		 2494 kvm_set_shared_msr(msr->index, msr->data,
2495 msr->mask);
2225fd56
AK		 2496 preempt_enable();
2497 }
3bab1f5d 2498 break;
6aa8b732 2499 }
8fe8ab46 2500 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2501 }
2502
2cc51560 2503 return ret;
6aa8b732
AK		 2504}
2505
5fdbf976 2506static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2507{
5fdbf976
MT		 2508 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2509 switch (reg) {
2510 case VCPU_REGS_RSP:
2511 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2512 break;
2513 case VCPU_REGS_RIP:
2514 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2515 break;
6de4f3ad
AK		 2516 case VCPU_EXREG_PDPTR:
2517 if (enable_ept)
2518 ept_save_pdptrs(vcpu);
2519 break;
5fdbf976
MT		 2520 default:
2521 break;
2522 }
6aa8b732
AK		 2523}
2524
6aa8b732
AK		 2525static __init int cpu_has_kvm_support(void)
2526{
6210e37b 2527 return cpu_has_vmx();
6aa8b732
AK		 2528}
2529
2530static __init int vmx_disabled_by_bios(void)
2531{
2532 u64 msr;
2533
2534 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2535 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2536 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2537 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2538 && tboot_enabled())
2539 return 1;
23f3e991 2540 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2541 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2542 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2543 && !tboot_enabled()) {
2544 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2545 "activate TXT before enabling KVM\n");
cafd6659 2546 return 1;
f9335afe 2547 }
23f3e991
JC		 2548 /* launched w/o TXT and VMX disabled */
2549 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2550 && !tboot_enabled())
2551 return 1;
cafd6659
SW		 2552 }
2553
2554 return 0;
6aa8b732
AK		 2555}
2556
7725b894
DX		 2557static void kvm_cpu_vmxon(u64 addr)
2558{
2559 asm volatile (ASM_VMX_VMXON_RAX
2560 : : "a"(&addr), "m"(addr)
2561 : "memory", "cc");
2562}
2563
10474ae8 2564static int hardware_enable(void *garbage)
6aa8b732
AK		 2565{
2566 int cpu = raw_smp_processor_id();
2567 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2568 u64 old, test_bits;
6aa8b732 2569
10474ae8
AG		 2570 if (read_cr4() & X86_CR4_VMXE)
2571 return -EBUSY;
2572
d462b819 2573 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2574
2575 /*
2576 * Now we can enable the vmclear operation in kdump
2577 * since the loaded_vmcss_on_cpu list on this cpu
2578 * has been initialized.
2579 *
2580 * Though the cpu is not in VMX operation now, there
2581 * is no problem to enable the vmclear operation
2582 * for the loaded_vmcss_on_cpu list is empty!
2583 */
2584 crash_enable_local_vmclear(cpu);
2585
6aa8b732 2586 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2587
2588 test_bits = FEATURE_CONTROL_LOCKED;
2589 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2590 if (tboot_enabled())
2591 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2592
2593 if ((old & test_bits) != test_bits) {
6aa8b732 2594 /* enable and lock */
cafd6659
SW		 2595 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2596 }
66aee91a 2597 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2598
4610c9cc
DX		 2599 if (vmm_exclusive) {
2600 kvm_cpu_vmxon(phys_addr);
2601 ept_sync_global();
2602 }
10474ae8 2603
3444d7da
AK		 2604 store_gdt(&__get_cpu_var(host_gdt));
2605
10474ae8 2606 return 0;
6aa8b732
AK		 2607}
2608
d462b819 2609static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2610{
2611 int cpu = raw_smp_processor_id();
d462b819 2612 struct loaded_vmcs *v, *n;
543e4243 2613
d462b819
NHE		 2614 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2615 loaded_vmcss_on_cpu_link)
2616 __loaded_vmcs_clear(v);
543e4243
AK		 2617}
2618
710ff4a8
EH		 2619
2620/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2621 * tricks.
2622 */
2623static void kvm_cpu_vmxoff(void)
6aa8b732 2624{
4ecac3fd 2625 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2626}
2627
710ff4a8
EH		 2628static void hardware_disable(void *garbage)
2629{
4610c9cc 2630 if (vmm_exclusive) {
d462b819 2631 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2632 kvm_cpu_vmxoff();
2633 }
7725b894 2634 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2635}
2636
1c3d14fe 2637static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2638 u32 msr, u32 *result)
1c3d14fe
YS		 2639{
2640 u32 vmx_msr_low, vmx_msr_high;
2641 u32 ctl = ctl_min | ctl_opt;
2642
2643 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2644
2645 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2646 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2647
2648 /* Ensure minimum (required) set of control bits are supported. */
2649 if (ctl_min & ~ctl)
002c7f7c 2650 return -EIO;
1c3d14fe
YS		 2651
2652 *result = ctl;
2653 return 0;
2654}
2655
110312c8
AK		 2656static __init bool allow_1_setting(u32 msr, u32 ctl)
2657{
2658 u32 vmx_msr_low, vmx_msr_high;
2659
2660 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2661 return vmx_msr_high & ctl;
2662}
2663
002c7f7c 2664static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2665{
2666 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2667 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2668 u32 _pin_based_exec_control = 0;
2669 u32 _cpu_based_exec_control = 0;
f78e0e2e 2670 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2671 u32 _vmexit_control = 0;
2672 u32 _vmentry_control = 0;
2673
10166744 2674 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2675#ifdef CONFIG_X86_64
2676 CPU_BASED_CR8_LOAD_EXITING |
2677 CPU_BASED_CR8_STORE_EXITING |
2678#endif
d56f546d
SY		 2679 CPU_BASED_CR3_LOAD_EXITING |
2680 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2681 CPU_BASED_USE_IO_BITMAPS |
2682 CPU_BASED_MOV_DR_EXITING |
a7052897 2683 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2684 CPU_BASED_MWAIT_EXITING |
2685 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2686 CPU_BASED_INVLPG_EXITING |
2687 CPU_BASED_RDPMC_EXITING;
443381a8 2688
f78e0e2e 2689 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2690 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2691 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2692 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2693 &_cpu_based_exec_control) < 0)
002c7f7c 2694 return -EIO;
6e5d865c
YS		 2695#ifdef CONFIG_X86_64
2696 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2697 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2698 ~CPU_BASED_CR8_STORE_EXITING;
2699#endif
f78e0e2e 2700 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2701 min2 = 0;
2702 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2703 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2704 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2705 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2706 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2707 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2708 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2709 SECONDARY_EXEC_RDTSCP |
83d4c286 2710 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2711 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2712 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2713 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2714 if (adjust_vmx_controls(min2, opt2,
2715 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2716 &_cpu_based_2nd_exec_control) < 0)
2717 return -EIO;
2718 }
2719#ifndef CONFIG_X86_64
2720 if (!(_cpu_based_2nd_exec_control &
2721 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2722 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2723#endif
83d4c286
YZ		 2724
2725 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2726 _cpu_based_2nd_exec_control &= ~(
8d14695f 2727 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2728 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2729 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2730
d56f546d 2731 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2732 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2733 enabled */
5fff7d27
GN		 2734 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2735 CPU_BASED_CR3_STORE_EXITING |
2736 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2737 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2738 vmx_capability.ept, vmx_capability.vpid);
2739 }
1c3d14fe
YS		 2740
2741 min = 0;
2742#ifdef CONFIG_X86_64
2743 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2744#endif
a547c6db
YZ		 2745 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2746 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2747 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2748 &_vmexit_control) < 0)
002c7f7c 2749 return -EIO;
1c3d14fe 2750
01e439be
YZ		 2751 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2752 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2753 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2754 &_pin_based_exec_control) < 0)
2755 return -EIO;
2756
2757 if (!(_cpu_based_2nd_exec_control &
2758 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2759 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2760 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2761
468d472f
SY		 2762 min = 0;
2763 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2764 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2765 &_vmentry_control) < 0)
002c7f7c 2766 return -EIO;
6aa8b732 2767
c68876fd 2768 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2769
2770 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2771 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2772 return -EIO;
1c3d14fe
YS		 2773
2774#ifdef CONFIG_X86_64
2775 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2776 if (vmx_msr_high & (1u<<16))
002c7f7c 2777 return -EIO;
1c3d14fe
YS		 2778#endif
2779
2780 /* Require Write-Back (WB) memory type for VMCS accesses. */
2781 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2782 return -EIO;
1c3d14fe 2783
002c7f7c
YS		 2784 vmcs_conf->size = vmx_msr_high & 0x1fff;
2785 vmcs_conf->order = get_order(vmcs_config.size);
2786 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2787
002c7f7c
YS		 2788 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2789 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2790 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2791 vmcs_conf->vmexit_ctrl = _vmexit_control;
2792 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2793
110312c8
AK		 2794 cpu_has_load_ia32_efer =
2795 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2796 VM_ENTRY_LOAD_IA32_EFER)
2797 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2798 VM_EXIT_LOAD_IA32_EFER);
2799
8bf00a52
GN		 2800 cpu_has_load_perf_global_ctrl =
2801 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2802 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2803 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2804 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2805
2806 /*
2807 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2808 * but due to arrata below it can't be used. Workaround is to use
2809 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2810 *
2811 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2812 *
2813 * AAK155 (model 26)
2814 * AAP115 (model 30)
2815 * AAT100 (model 37)
2816 * BC86,AAY89,BD102 (model 44)
2817 * BA97 (model 46)
2818 *
2819 */
2820 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2821 switch (boot_cpu_data.x86_model) {
2822 case 26:
2823 case 30:
2824 case 37:
2825 case 44:
2826 case 46:
2827 cpu_has_load_perf_global_ctrl = false;
2828 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2829 "does not work properly. Using workaround\n");
2830 break;
2831 default:
2832 break;
2833 }
2834 }
2835
1c3d14fe 2836 return 0;
c68876fd 2837}
6aa8b732
AK		 2838
2839static struct vmcs *alloc_vmcs_cpu(int cpu)
2840{
2841 int node = cpu_to_node(cpu);
2842 struct page *pages;
2843 struct vmcs *vmcs;
2844
6484eb3e 2845 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2846 if (!pages)
2847 return NULL;
2848 vmcs = page_address(pages);
1c3d14fe
YS		 2849 memset(vmcs, 0, vmcs_config.size);
2850 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2851 return vmcs;
2852}
2853
2854static struct vmcs *alloc_vmcs(void)
2855{
d3b2c338 2856 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2857}
2858
2859static void free_vmcs(struct vmcs *vmcs)
2860{
1c3d14fe 2861 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2862}
2863
d462b819
NHE		 2864/*
2865 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2866 */
2867static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2868{
2869 if (!loaded_vmcs->vmcs)
2870 return;
2871 loaded_vmcs_clear(loaded_vmcs);
2872 free_vmcs(loaded_vmcs->vmcs);
2873 loaded_vmcs->vmcs = NULL;
2874}
2875
39959588 2876static void free_kvm_area(void)
6aa8b732
AK		 2877{
2878 int cpu;
2879
3230bb47 2880 for_each_possible_cpu(cpu) {
6aa8b732 2881 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2882 per_cpu(vmxarea, cpu) = NULL;
2883 }
6aa8b732
AK		 2884}
2885
6aa8b732
AK		 2886static __init int alloc_kvm_area(void)
2887{
2888 int cpu;
2889
3230bb47 2890 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2891 struct vmcs *vmcs;
2892
2893 vmcs = alloc_vmcs_cpu(cpu);
2894 if (!vmcs) {
2895 free_kvm_area();
2896 return -ENOMEM;
2897 }
2898
2899 per_cpu(vmxarea, cpu) = vmcs;
2900 }
2901 return 0;
2902}
2903
2904static __init int hardware_setup(void)
2905{
002c7f7c
YS		 2906 if (setup_vmcs_config(&vmcs_config) < 0)
2907 return -EIO;
50a37eb4
JR		 2908
2909 if (boot_cpu_has(X86_FEATURE_NX))
2910 kvm_enable_efer_bits(EFER_NX);
2911
93ba03c2
SY		 2912 if (!cpu_has_vmx_vpid())
2913 enable_vpid = 0;
abc4fc58
AG		 2914 if (!cpu_has_vmx_shadow_vmcs())
2915 enable_shadow_vmcs = 0;
93ba03c2 2916
4bc9b982
SY		 2917 if (!cpu_has_vmx_ept() ||
2918 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2919 enable_ept = 0;
3a624e29 2920 enable_unrestricted_guest = 0;
83c3a331 2921 enable_ept_ad_bits = 0;
3a624e29
NK		 2922 }
2923
83c3a331
XH		 2924 if (!cpu_has_vmx_ept_ad_bits())
2925 enable_ept_ad_bits = 0;
2926
3a624e29
NK		 2927 if (!cpu_has_vmx_unrestricted_guest())
2928 enable_unrestricted_guest = 0;
93ba03c2
SY		 2929
2930 if (!cpu_has_vmx_flexpriority())
2931 flexpriority_enabled = 0;
2932
95ba8273
GN		 2933 if (!cpu_has_vmx_tpr_shadow())
2934 kvm_x86_ops->update_cr8_intercept = NULL;
2935
54dee993
MT		 2936 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2937 kvm_disable_largepages();
2938
4b8d54f9
ZE		 2939 if (!cpu_has_vmx_ple())
2940 ple_gap = 0;
2941
01e439be
YZ		 2942 if (!cpu_has_vmx_apicv())
2943 enable_apicv = 0;
c7c9c56c 2944
01e439be 2945 if (enable_apicv)
c7c9c56c 2946 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2947 else {
c7c9c56c 2948 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2949 kvm_x86_ops->deliver_posted_interrupt = NULL;
2950 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2951 }
83d4c286 2952
b87a51ae
NHE		 2953 if (nested)
2954 nested_vmx_setup_ctls_msrs();
2955
6aa8b732
AK		 2956 return alloc_kvm_area();
2957}
2958
2959static __exit void hardware_unsetup(void)
2960{
2961 free_kvm_area();
2962}
2963
14168786
GN		 2964static bool emulation_required(struct kvm_vcpu *vcpu)
2965{
2966 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2967}
2968
91b0aa2c 2969static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2970 struct kvm_segment *save)
6aa8b732 2971{
d99e4152
GN		 2972 if (!emulate_invalid_guest_state) {
2973 /*
2974 * CS and SS RPL should be equal during guest entry according
2975 * to VMX spec, but in reality it is not always so. Since vcpu
2976 * is in the middle of the transition from real mode to
2977 * protected mode it is safe to assume that RPL 0 is a good
2978 * default value.
2979 */
2980 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2981 save->selector &= ~SELECTOR_RPL_MASK;
2982 save->dpl = save->selector & SELECTOR_RPL_MASK;
2983 save->s = 1;
6aa8b732 2984 }
d99e4152 2985 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2986}
2987
2988static void enter_pmode(struct kvm_vcpu *vcpu)
2989{
2990 unsigned long flags;
a89a8fb9 2991 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2992
d99e4152
GN		 2993 /*
2994 * Update real mode segment cache. It may be not up-to-date if sement
2995 * register was written while vcpu was in a guest mode.
2996 */
2997 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2998 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2999 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3000 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3001 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3002 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3003
7ffd92c5 3004 vmx->rmode.vm86_active = 0;
6aa8b732 3005
2fb92db1
AK		 3006 vmx_segment_cache_clear(vmx);
3007
f5f7b2fe 3008 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3009
3010 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3011 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3012 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3013 vmcs_writel(GUEST_RFLAGS, flags);
3014
66aee91a
RR		 3015 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3016 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3017
3018 update_exception_bitmap(vcpu);
3019
91b0aa2c
GN		 3020 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3021 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3022 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3023 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3024 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3025 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3026
3027 /* CPL is always 0 when CPU enters protected mode */
3028 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3029 vmx->cpl = 0;
6aa8b732
AK		 3030}
3031
f5f7b2fe 3032static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3033{
772e0318 3034 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3035 struct kvm_segment var = *save;
3036
3037 var.dpl = 0x3;
3038 if (seg == VCPU_SREG_CS)
3039 var.type = 0x3;
3040
3041 if (!emulate_invalid_guest_state) {
3042 var.selector = var.base >> 4;
3043 var.base = var.base & 0xffff0;
3044 var.limit = 0xffff;
3045 var.g = 0;
3046 var.db = 0;
3047 var.present = 1;
3048 var.s = 1;
3049 var.l = 0;
3050 var.unusable = 0;
3051 var.type = 0x3;
3052 var.avl = 0;
3053 if (save->base & 0xf)
3054 printk_once(KERN_WARNING "kvm: segment base is not "
3055 "paragraph aligned when entering "
3056 "protected mode (seg=%d)", seg);
3057 }
6aa8b732 3058
d99e4152
GN		 3059 vmcs_write16(sf->selector, var.selector);
3060 vmcs_write32(sf->base, var.base);
3061 vmcs_write32(sf->limit, var.limit);
3062 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3063}
3064
3065static void enter_rmode(struct kvm_vcpu *vcpu)
3066{
3067 unsigned long flags;
a89a8fb9 3068 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3069
f5f7b2fe
AK		 3070 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3071 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3072 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3073 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3074 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3075 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3076 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3077
7ffd92c5 3078 vmx->rmode.vm86_active = 1;
6aa8b732 3079
776e58ea
GN		 3080 /*
3081 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3082 * vcpu. Warn the user that an update is overdue.
776e58ea 3083 */
4918c6ca 3084 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3085 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3086 "called before entering vcpu\n");
776e58ea 3087
2fb92db1
AK		 3088 vmx_segment_cache_clear(vmx);
3089
4918c6ca 3090 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3091 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3092 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3093
3094 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3095 vmx->rmode.save_rflags = flags;
6aa8b732 3096
053de044 3097 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3098
3099 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3100 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3101 update_exception_bitmap(vcpu);
3102
d99e4152
GN		 3103 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3104 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3105 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3106 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3107 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3108 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3109
8668a3c4 3110 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3111}
3112
401d10de
AS		 3113static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3114{
3115 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3116 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3117
3118 if (!msr)
3119 return;
401d10de 3120
44ea2b17
AK		 3121 /*
3122 * Force kernel_gs_base reloading before EFER changes, as control
3123 * of this msr depends on is_long_mode().
3124 */
3125 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3126 vcpu->arch.efer = efer;
401d10de
AS		 3127 if (efer & EFER_LMA) {
3128 vmcs_write32(VM_ENTRY_CONTROLS,
3129 vmcs_read32(VM_ENTRY_CONTROLS) |
3130 VM_ENTRY_IA32E_MODE);
3131 msr->data = efer;
3132 } else {
3133 vmcs_write32(VM_ENTRY_CONTROLS,
3134 vmcs_read32(VM_ENTRY_CONTROLS) &
3135 ~VM_ENTRY_IA32E_MODE);
3136
3137 msr->data = efer & ~EFER_LME;
3138 }
3139 setup_msrs(vmx);
3140}
3141
05b3e0c2 3142#ifdef CONFIG_X86_64
6aa8b732
AK		 3143
3144static void enter_lmode(struct kvm_vcpu *vcpu)
3145{
3146 u32 guest_tr_ar;
3147
2fb92db1
AK		 3148 vmx_segment_cache_clear(to_vmx(vcpu));
3149
6aa8b732
AK		 3150 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3151 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3152 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3153 __func__);
6aa8b732
AK		 3154 vmcs_write32(GUEST_TR_AR_BYTES,
3155 (guest_tr_ar & ~AR_TYPE_MASK)
3156 | AR_TYPE_BUSY_64_TSS);
3157 }
da38f438 3158 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3159}
3160
3161static void exit_lmode(struct kvm_vcpu *vcpu)
3162{
6aa8b732
AK		 3163 vmcs_write32(VM_ENTRY_CONTROLS,
3164 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3165 & ~VM_ENTRY_IA32E_MODE);
da38f438 3166 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3167}
3168
3169#endif
3170
2384d2b3
SY		 3171static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3172{
b9d762fa 3173 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3174 if (enable_ept) {
3175 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3176 return;
4e1096d2 3177 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3178 }
2384d2b3
SY		 3179}
3180
e8467fda
AK		 3181static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3182{
3183 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3184
3185 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3186 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3187}
3188
aff48baa
AK		 3189static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3190{
3191 if (enable_ept && is_paging(vcpu))
3192 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3193 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3194}
3195
25c4c276 3196static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3197{
fc78f519
AK		 3198 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3199
3200 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3201 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3202}
3203
1439442c
SY		 3204static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3205{
6de4f3ad
AK		 3206 if (!test_bit(VCPU_EXREG_PDPTR,
3207 (unsigned long *)&vcpu->arch.regs_dirty))
3208 return;
3209
1439442c 3210 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3211 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3212 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3213 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3214 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3215 }
3216}
3217
8f5d549f
AK		 3218static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3219{
3220 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3221 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3222 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3223 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3224 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3225 }
6de4f3ad
AK		 3226
3227 __set_bit(VCPU_EXREG_PDPTR,
3228 (unsigned long *)&vcpu->arch.regs_avail);
3229 __set_bit(VCPU_EXREG_PDPTR,
3230 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3231}
3232
5e1746d6 3233static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3234
3235static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3236 unsigned long cr0,
3237 struct kvm_vcpu *vcpu)
3238{
5233dd51
MT		 3239 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3240 vmx_decache_cr3(vcpu);
1439442c
SY		 3241 if (!(cr0 & X86_CR0_PG)) {
3242 /* From paging/starting to nonpaging */
3243 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3244 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3245 (CPU_BASED_CR3_LOAD_EXITING |
3246 CPU_BASED_CR3_STORE_EXITING));
3247 vcpu->arch.cr0 = cr0;
fc78f519 3248 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3249 } else if (!is_paging(vcpu)) {
3250 /* From nonpaging to paging */
3251 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3252 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3253 ~(CPU_BASED_CR3_LOAD_EXITING |
3254 CPU_BASED_CR3_STORE_EXITING));
3255 vcpu->arch.cr0 = cr0;
fc78f519 3256 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3257 }
95eb84a7
SY		 3258
3259 if (!(cr0 & X86_CR0_WP))
3260 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3261}
3262
6aa8b732
AK		 3263static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3264{
7ffd92c5 3265 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3266 unsigned long hw_cr0;
3267
5037878e 3268 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3269 if (enable_unrestricted_guest)
5037878e 3270 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3271 else {
5037878e 3272 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3273
218e763f
GN		 3274 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3275 enter_pmode(vcpu);
6aa8b732 3276
218e763f
GN		 3277 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3278 enter_rmode(vcpu);
3279 }
6aa8b732 3280
05b3e0c2 3281#ifdef CONFIG_X86_64
f6801dff 3282 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3283 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3284 enter_lmode(vcpu);
707d92fa 3285 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3286 exit_lmode(vcpu);
3287 }
3288#endif
3289
089d034e 3290 if (enable_ept)
1439442c
SY		 3291 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3292
02daab21 3293 if (!vcpu->fpu_active)
81231c69 3294 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3295
6aa8b732 3296 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3297 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3298 vcpu->arch.cr0 = cr0;
14168786
GN		 3299
3300 /* depends on vcpu->arch.cr0 to be set to a new value */
3301 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3302}
3303
1439442c
SY		 3304static u64 construct_eptp(unsigned long root_hpa)
3305{
3306 u64 eptp;
3307
3308 /* TODO write the value reading from MSR */
3309 eptp = VMX_EPT_DEFAULT_MT |
3310 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3311 if (enable_ept_ad_bits)
3312 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3313 eptp |= (root_hpa & PAGE_MASK);
3314
3315 return eptp;
3316}
3317
6aa8b732
AK		 3318static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3319{
1439442c
SY		 3320 unsigned long guest_cr3;
3321 u64 eptp;
3322
3323 guest_cr3 = cr3;
089d034e 3324 if (enable_ept) {
1439442c
SY		 3325 eptp = construct_eptp(cr3);
3326 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3327 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3328 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3329 ept_load_pdptrs(vcpu);
1439442c
SY		 3330 }
3331
2384d2b3 3332 vmx_flush_tlb(vcpu);
1439442c 3333 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3334}
3335
5e1746d6 3336static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3337{
7ffd92c5 3338 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3339 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3340
5e1746d6
NHE		 3341 if (cr4 & X86_CR4_VMXE) {
3342 /*
3343 * To use VMXON (and later other VMX instructions), a guest
3344 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3345 * So basically the check on whether to allow nested VMX
3346 * is here.
3347 */
3348 if (!nested_vmx_allowed(vcpu))
3349 return 1;
1a0d74e6
JK		 3350 }
3351 if (to_vmx(vcpu)->nested.vmxon &&
3352 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3353 return 1;
3354
ad312c7c 3355 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3356 if (enable_ept) {
3357 if (!is_paging(vcpu)) {
3358 hw_cr4 &= ~X86_CR4_PAE;
3359 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3360 /*
3361 * SMEP is disabled if CPU is in non-paging mode in
3362 * hardware. However KVM always uses paging mode to
3363 * emulate guest non-paging mode with TDP.
3364 * To emulate this behavior, SMEP needs to be manually
3365 * disabled when guest switches to non-paging mode.
3366 */
3367 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3368 } else if (!(cr4 & X86_CR4_PAE)) {
3369 hw_cr4 &= ~X86_CR4_PAE;
3370 }
3371 }
1439442c
SY		 3372
3373 vmcs_writel(CR4_READ_SHADOW, cr4);
3374 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3375 return 0;
6aa8b732
AK		 3376}
3377
6aa8b732
AK		 3378static void vmx_get_segment(struct kvm_vcpu *vcpu,
3379 struct kvm_segment *var, int seg)
3380{
a9179499 3381 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3382 u32 ar;
3383
c6ad1153 3384 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3385 *var = vmx->rmode.segs[seg];
a9179499 3386 if (seg == VCPU_SREG_TR
2fb92db1 3387 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3388 return;
1390a28b
AK		 3389 var->base = vmx_read_guest_seg_base(vmx, seg);
3390 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3391 return;
a9179499 3392 }
2fb92db1
AK		 3393 var->base = vmx_read_guest_seg_base(vmx, seg);
3394 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3395 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3396 ar = vmx_read_guest_seg_ar(vmx, seg);
6aa8b732
AK		 3397 var->type = ar & 15;
3398 var->s = (ar >> 4) & 1;
3399 var->dpl = (ar >> 5) & 3;
3400 var->present = (ar >> 7) & 1;
3401 var->avl = (ar >> 12) & 1;
3402 var->l = (ar >> 13) & 1;
3403 var->db = (ar >> 14) & 1;
3404 var->g = (ar >> 15) & 1;
3405 var->unusable = (ar >> 16) & 1;
3406}
3407
a9179499
AK		 3408static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3409{
a9179499
AK		 3410 struct kvm_segment s;
3411
3412 if (to_vmx(vcpu)->rmode.vm86_active) {
3413 vmx_get_segment(vcpu, &s, seg);
3414 return s.base;
3415 }
2fb92db1 3416 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3417}
3418
b09408d0 3419static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3420{
b09408d0
MT		 3421 struct vcpu_vmx *vmx = to_vmx(vcpu);
3422
3eeb3288 3423 if (!is_protmode(vcpu))
2e4d2653
IE		 3424 return 0;
3425
f4c63e5d
AK		 3426 if (!is_long_mode(vcpu)
3427 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3428 return 3;
3429
69c73028
AK		 3430 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3431 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3432 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3433 }
d881e6f6
AK		 3434
3435 return vmx->cpl;
69c73028
AK		 3436}
3437
3438
653e3108 3439static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3440{
6aa8b732
AK		 3441 u32 ar;
3442
f0495f9b 3443 if (var->unusable || !var->present)
6aa8b732
AK		 3444 ar = 1 << 16;
3445 else {
3446 ar = var->type & 15;
3447 ar |= (var->s & 1) << 4;
3448 ar |= (var->dpl & 3) << 5;
3449 ar |= (var->present & 1) << 7;
3450 ar |= (var->avl & 1) << 12;
3451 ar |= (var->l & 1) << 13;
3452 ar |= (var->db & 1) << 14;
3453 ar |= (var->g & 1) << 15;
3454 }
653e3108
AK		 3455
3456 return ar;
3457}
3458
3459static void vmx_set_segment(struct kvm_vcpu *vcpu,
3460 struct kvm_segment *var, int seg)
3461{
7ffd92c5 3462 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3463 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3464
2fb92db1 3465 vmx_segment_cache_clear(vmx);
2f143240
GN		 3466 if (seg == VCPU_SREG_CS)
3467 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3468
1ecd50a9
GN		 3469 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3470 vmx->rmode.segs[seg] = *var;
3471 if (seg == VCPU_SREG_TR)
3472 vmcs_write16(sf->selector, var->selector);
3473 else if (var->s)
3474 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3475 goto out;
653e3108 3476 }
1ecd50a9 3477
653e3108
AK		 3478 vmcs_writel(sf->base, var->base);
3479 vmcs_write32(sf->limit, var->limit);
3480 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3481
3482 /*
3483 * Fix the "Accessed" bit in AR field of segment registers for older
3484 * qemu binaries.
3485 * IA32 arch specifies that at the time of processor reset the
3486 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3487 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3488 * state vmexit when "unrestricted guest" mode is turned on.
3489 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3490 * tree. Newer qemu binaries with that qemu fix would not need this
3491 * kvm hack.
3492 */
3493 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3494 var->type |= 0x1; /* Accessed */
3a624e29 3495
f924d66d 3496 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3497
3498out:
14168786 3499 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3500}
3501
6aa8b732
AK		 3502static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3503{
2fb92db1 3504 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3505
3506 *db = (ar >> 14) & 1;
3507 *l = (ar >> 13) & 1;
3508}
3509
89a27f4d 3510static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3511{
89a27f4d
GN		 3512 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3513 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3514}
3515
89a27f4d 3516static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3517{
89a27f4d
GN		 3518 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3519 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3520}
3521
89a27f4d 3522static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3523{
89a27f4d
GN		 3524 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3525 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3526}
3527
89a27f4d 3528static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3529{
89a27f4d
GN		 3530 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3531 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3532}
3533
648dfaa7
MG		 3534static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3535{
3536 struct kvm_segment var;
3537 u32 ar;
3538
3539 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3540 var.dpl = 0x3;
0647f4aa
GN		 3541 if (seg == VCPU_SREG_CS)
3542 var.type = 0x3;
648dfaa7
MG		 3543 ar = vmx_segment_access_rights(&var);
3544
3545 if (var.base != (var.selector << 4))
3546 return false;
89efbed0 3547 if (var.limit != 0xffff)
648dfaa7 3548 return false;
07f42f5f 3549 if (ar != 0xf3)
648dfaa7
MG		 3550 return false;
3551
3552 return true;
3553}
3554
3555static bool code_segment_valid(struct kvm_vcpu *vcpu)
3556{
3557 struct kvm_segment cs;
3558 unsigned int cs_rpl;
3559
3560 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3561 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3562
1872a3f4
AK		 3563 if (cs.unusable)
3564 return false;
648dfaa7
MG		 3565 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3566 return false;
3567 if (!cs.s)
3568 return false;
1872a3f4 3569 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3570 if (cs.dpl > cs_rpl)
3571 return false;
1872a3f4 3572 } else {
648dfaa7
MG		 3573 if (cs.dpl != cs_rpl)
3574 return false;
3575 }
3576 if (!cs.present)
3577 return false;
3578
3579 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3580 return true;
3581}
3582
3583static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3584{
3585 struct kvm_segment ss;
3586 unsigned int ss_rpl;
3587
3588 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3589 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3590
1872a3f4
AK		 3591 if (ss.unusable)
3592 return true;
3593 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3594 return false;
3595 if (!ss.s)
3596 return false;
3597 if (ss.dpl != ss_rpl) /* DPL != RPL */
3598 return false;
3599 if (!ss.present)
3600 return false;
3601
3602 return true;
3603}
3604
3605static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3606{
3607 struct kvm_segment var;
3608 unsigned int rpl;
3609
3610 vmx_get_segment(vcpu, &var, seg);
3611 rpl = var.selector & SELECTOR_RPL_MASK;
3612
1872a3f4
AK		 3613 if (var.unusable)
3614 return true;
648dfaa7
MG		 3615 if (!var.s)
3616 return false;
3617 if (!var.present)
3618 return false;
3619 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3620 if (var.dpl < rpl) /* DPL < RPL */
3621 return false;
3622 }
3623
3624 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3625 * rights flags
3626 */
3627 return true;
3628}
3629
3630static bool tr_valid(struct kvm_vcpu *vcpu)
3631{
3632 struct kvm_segment tr;
3633
3634 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3635
1872a3f4
AK		 3636 if (tr.unusable)
3637 return false;
648dfaa7
MG		 3638 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3639 return false;
1872a3f4 3640 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3641 return false;
3642 if (!tr.present)
3643 return false;
3644
3645 return true;
3646}
3647
3648static bool ldtr_valid(struct kvm_vcpu *vcpu)
3649{
3650 struct kvm_segment ldtr;
3651
3652 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3653
1872a3f4
AK		 3654 if (ldtr.unusable)
3655 return true;
648dfaa7
MG		 3656 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3657 return false;
3658 if (ldtr.type != 2)
3659 return false;
3660 if (!ldtr.present)
3661 return false;
3662
3663 return true;
3664}
3665
3666static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3667{
3668 struct kvm_segment cs, ss;
3669
3670 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3671 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3672
3673 return ((cs.selector & SELECTOR_RPL_MASK) ==
3674 (ss.selector & SELECTOR_RPL_MASK));
3675}
3676
3677/*
3678 * Check if guest state is valid. Returns true if valid, false if
3679 * not.
3680 * We assume that registers are always usable
3681 */
3682static bool guest_state_valid(struct kvm_vcpu *vcpu)
3683{
c5e97c80
GN		 3684 if (enable_unrestricted_guest)
3685 return true;
3686
648dfaa7 3687 /* real mode guest state checks */
f13882d8 3688 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3689 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3690 return false;
3691 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3692 return false;
3693 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3694 return false;
3695 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3696 return false;
3697 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3698 return false;
3699 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3700 return false;
3701 } else {
3702 /* protected mode guest state checks */
3703 if (!cs_ss_rpl_check(vcpu))
3704 return false;
3705 if (!code_segment_valid(vcpu))
3706 return false;
3707 if (!stack_segment_valid(vcpu))
3708 return false;
3709 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3710 return false;
3711 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3712 return false;
3713 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3714 return false;
3715 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3716 return false;
3717 if (!tr_valid(vcpu))
3718 return false;
3719 if (!ldtr_valid(vcpu))
3720 return false;
3721 }
3722 /* TODO:
3723 * - Add checks on RIP
3724 * - Add checks on RFLAGS
3725 */
3726
3727 return true;
3728}
3729
d77c26fc 3730static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3731{
40dcaa9f 3732 gfn_t fn;
195aefde 3733 u16 data = 0;
40dcaa9f 3734 int r, idx, ret = 0;
6aa8b732 3735
40dcaa9f 3736 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3737 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3738 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3739 if (r < 0)
10589a46 3740 goto out;
195aefde 3741 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3742 r = kvm_write_guest_page(kvm, fn++, &data,
3743 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3744 if (r < 0)
10589a46 3745 goto out;
195aefde
IE		 3746 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3747 if (r < 0)
10589a46 3748 goto out;
195aefde
IE		 3749 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3750 if (r < 0)
10589a46 3751 goto out;
195aefde 3752 data = ~0;
10589a46
MT		 3753 r = kvm_write_guest_page(kvm, fn, &data,
3754 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3755 sizeof(u8));
195aefde 3756 if (r < 0)
10589a46
MT		 3757 goto out;
3758
3759 ret = 1;
3760out:
40dcaa9f 3761 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3762 return ret;
6aa8b732
AK		 3763}
3764
b7ebfb05
SY		 3765static int init_rmode_identity_map(struct kvm *kvm)
3766{
40dcaa9f 3767 int i, idx, r, ret;
b7ebfb05
SY		 3768 pfn_t identity_map_pfn;
3769 u32 tmp;
3770
089d034e 3771 if (!enable_ept)
b7ebfb05
SY		 3772 return 1;
3773 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3774 printk(KERN_ERR "EPT: identity-mapping pagetable "
3775 "haven't been allocated!\n");
3776 return 0;
3777 }
3778 if (likely(kvm->arch.ept_identity_pagetable_done))
3779 return 1;
3780 ret = 0;
b927a3ce 3781 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3782 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3783 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3784 if (r < 0)
3785 goto out;
3786 /* Set up identity-mapping pagetable for EPT in real mode */
3787 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3788 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3789 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3790 r = kvm_write_guest_page(kvm, identity_map_pfn,
3791 &tmp, i * sizeof(tmp), sizeof(tmp));
3792 if (r < 0)
3793 goto out;
3794 }
3795 kvm->arch.ept_identity_pagetable_done = true;
3796 ret = 1;
3797out:
40dcaa9f 3798 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3799 return ret;
3800}
3801
6aa8b732
AK		 3802static void seg_setup(int seg)
3803{
772e0318 3804 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3805 unsigned int ar;
6aa8b732
AK		 3806
3807 vmcs_write16(sf->selector, 0);
3808 vmcs_writel(sf->base, 0);
3809 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3810 ar = 0x93;
3811 if (seg == VCPU_SREG_CS)
3812 ar |= 0x08; /* code segment */
3a624e29
NK		 3813
3814 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3815}
3816
f78e0e2e
SY		 3817static int alloc_apic_access_page(struct kvm *kvm)
3818{
4484141a 3819 struct page *page;
f78e0e2e
SY		 3820 struct kvm_userspace_memory_region kvm_userspace_mem;
3821 int r = 0;
3822
79fac95e 3823 mutex_lock(&kvm->slots_lock);
bfc6d222 3824 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3825 goto out;
3826 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3827 kvm_userspace_mem.flags = 0;
3828 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3829 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3830 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3831 if (r)
3832 goto out;
72dc67a6 3833
4484141a
XG		 3834 page = gfn_to_page(kvm, 0xfee00);
3835 if (is_error_page(page)) {
3836 r = -EFAULT;
3837 goto out;
3838 }
3839
3840 kvm->arch.apic_access_page = page;
f78e0e2e 3841out:
79fac95e 3842 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3843 return r;
3844}
3845
b7ebfb05
SY		 3846static int alloc_identity_pagetable(struct kvm *kvm)
3847{
4484141a 3848 struct page *page;
b7ebfb05
SY		 3849 struct kvm_userspace_memory_region kvm_userspace_mem;
3850 int r = 0;
3851
79fac95e 3852 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3853 if (kvm->arch.ept_identity_pagetable)
3854 goto out;
3855 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3856 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3857 kvm_userspace_mem.guest_phys_addr =
3858 kvm->arch.ept_identity_map_addr;
b7ebfb05 3859 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3860 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3861 if (r)
3862 goto out;
3863
4484141a
XG		 3864 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3865 if (is_error_page(page)) {
3866 r = -EFAULT;
3867 goto out;
3868 }
3869
3870 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3871out:
79fac95e 3872 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3873 return r;
3874}
3875
2384d2b3
SY		 3876static void allocate_vpid(struct vcpu_vmx *vmx)
3877{
3878 int vpid;
3879
3880 vmx->vpid = 0;
919818ab 3881 if (!enable_vpid)
2384d2b3
SY		 3882 return;
3883 spin_lock(&vmx_vpid_lock);
3884 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3885 if (vpid < VMX_NR_VPIDS) {
3886 vmx->vpid = vpid;
3887 __set_bit(vpid, vmx_vpid_bitmap);
3888 }
3889 spin_unlock(&vmx_vpid_lock);
3890}
3891
cdbecfc3
LJ		 3892static void free_vpid(struct vcpu_vmx *vmx)
3893{
3894 if (!enable_vpid)
3895 return;
3896 spin_lock(&vmx_vpid_lock);
3897 if (vmx->vpid != 0)
3898 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3899 spin_unlock(&vmx_vpid_lock);
3900}
3901
8d14695f
YZ		 3902#define MSR_TYPE_R 1
3903#define MSR_TYPE_W 2
3904static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3905 u32 msr, int type)
25c5f225 3906{
3e7c73e9 3907 int f = sizeof(unsigned long);
25c5f225
SY		 3908
3909 if (!cpu_has_vmx_msr_bitmap())
3910 return;
3911
3912 /*
3913 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3914 * have the write-low and read-high bitmap offsets the wrong way round.
3915 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3916 */
25c5f225 3917 if (msr <= 0x1fff) {
8d14695f
YZ		 3918 if (type & MSR_TYPE_R)
3919 /* read-low */
3920 __clear_bit(msr, msr_bitmap + 0x000 / f);
3921
3922 if (type & MSR_TYPE_W)
3923 /* write-low */
3924 __clear_bit(msr, msr_bitmap + 0x800 / f);
3925
25c5f225
SY		 3926 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3927 msr &= 0x1fff;
8d14695f
YZ		 3928 if (type & MSR_TYPE_R)
3929 /* read-high */
3930 __clear_bit(msr, msr_bitmap + 0x400 / f);
3931
3932 if (type & MSR_TYPE_W)
3933 /* write-high */
3934 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3935
3936 }
3937}
3938
3939static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3940 u32 msr, int type)
3941{
3942 int f = sizeof(unsigned long);
3943
3944 if (!cpu_has_vmx_msr_bitmap())
3945 return;
3946
3947 /*
3948 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3949 * have the write-low and read-high bitmap offsets the wrong way round.
3950 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3951 */
3952 if (msr <= 0x1fff) {
3953 if (type & MSR_TYPE_R)
3954 /* read-low */
3955 __set_bit(msr, msr_bitmap + 0x000 / f);
3956
3957 if (type & MSR_TYPE_W)
3958 /* write-low */
3959 __set_bit(msr, msr_bitmap + 0x800 / f);
3960
3961 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3962 msr &= 0x1fff;
3963 if (type & MSR_TYPE_R)
3964 /* read-high */
3965 __set_bit(msr, msr_bitmap + 0x400 / f);
3966
3967 if (type & MSR_TYPE_W)
3968 /* write-high */
3969 __set_bit(msr, msr_bitmap + 0xc00 / f);
3970
25c5f225 3971 }
25c5f225
SY		 3972}
3973
5897297b
AK		 3974static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3975{
3976 if (!longmode_only)
8d14695f
YZ		 3977 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3978 msr, MSR_TYPE_R | MSR_TYPE_W);
3979 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3980 msr, MSR_TYPE_R | MSR_TYPE_W);
3981}
3982
3983static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3984{
3985 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3986 msr, MSR_TYPE_R);
3987 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3988 msr, MSR_TYPE_R);
3989}
3990
3991static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3992{
3993 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3994 msr, MSR_TYPE_R);
3995 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3996 msr, MSR_TYPE_R);
3997}
3998
3999static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4000{
4001 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4002 msr, MSR_TYPE_W);
4003 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4004 msr, MSR_TYPE_W);
5897297b
AK		 4005}
4006
01e439be
YZ		 4007static int vmx_vm_has_apicv(struct kvm *kvm)
4008{
4009 return enable_apicv && irqchip_in_kernel(kvm);
4010}
4011
a20ed54d
YZ		 4012/*
4013 * Send interrupt to vcpu via posted interrupt way.
4014 * 1. If target vcpu is running(non-root mode), send posted interrupt
4015 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4016 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4017 * interrupt from PIR in next vmentry.
4018 */
4019static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4020{
4021 struct vcpu_vmx *vmx = to_vmx(vcpu);
4022 int r;
4023
4024 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4025 return;
4026
4027 r = pi_test_and_set_on(&vmx->pi_desc);
4028 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4029#ifdef CONFIG_SMP
a20ed54d
YZ		 4030 if (!r && (vcpu->mode == IN_GUEST_MODE))
4031 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4032 POSTED_INTR_VECTOR);
4033 else
6ffbbbba 4034#endif
a20ed54d
YZ		 4035 kvm_vcpu_kick(vcpu);
4036}
4037
4038static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4039{
4040 struct vcpu_vmx *vmx = to_vmx(vcpu);
4041
4042 if (!pi_test_and_clear_on(&vmx->pi_desc))
4043 return;
4044
4045 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4046}
4047
4048static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4049{
4050 return;
4051}
4052
a3a8ff8e
NHE		 4053/*
4054 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4055 * will not change in the lifetime of the guest.
4056 * Note that host-state that does change is set elsewhere. E.g., host-state
4057 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4058 */
a547c6db 4059static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4060{
4061 u32 low32, high32;
4062 unsigned long tmpl;
4063 struct desc_ptr dt;
4064
b1a74bf8 4065 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4066 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4067 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4068
4069 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4070#ifdef CONFIG_X86_64
4071 /*
4072 * Load null selectors, so we can avoid reloading them in
4073 * __vmx_load_host_state(), in case userspace uses the null selectors
4074 * too (the expected case).
4075 */
4076 vmcs_write16(HOST_DS_SELECTOR, 0);
4077 vmcs_write16(HOST_ES_SELECTOR, 0);
4078#else
a3a8ff8e
NHE		 4079 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4080 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4081#endif
a3a8ff8e
NHE		 4082 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4083 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4084
4085 native_store_idt(&dt);
4086 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4087 vmx->host_idt_base = dt.address;
a3a8ff8e 4088
83287ea4 4089 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4090
4091 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4092 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4093 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4094 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4095
4096 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4097 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4098 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4099 }
4100}
4101
bf8179a0
NHE		 4102static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4103{
4104 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4105 if (enable_ept)
4106 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4107 if (is_guest_mode(&vmx->vcpu))
4108 vmx->vcpu.arch.cr4_guest_owned_bits &=
4109 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4110 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4111}
4112
01e439be
YZ		 4113static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4114{
4115 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4116
4117 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4118 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4119 return pin_based_exec_ctrl;
4120}
4121
bf8179a0
NHE		 4122static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4123{
4124 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4125 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4126 exec_control &= ~CPU_BASED_TPR_SHADOW;
4127#ifdef CONFIG_X86_64
4128 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4129 CPU_BASED_CR8_LOAD_EXITING;
4130#endif
4131 }
4132 if (!enable_ept)
4133 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4134 CPU_BASED_CR3_LOAD_EXITING |
4135 CPU_BASED_INVLPG_EXITING;
4136 return exec_control;
4137}
4138
4139static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4140{
4141 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4142 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4143 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4144 if (vmx->vpid == 0)
4145 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4146 if (!enable_ept) {
4147 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4148 enable_unrestricted_guest = 0;
ad756a16
MJ		 4149 /* Enable INVPCID for non-ept guests may cause performance regression. */
4150 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4151 }
4152 if (!enable_unrestricted_guest)
4153 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4154 if (!ple_gap)
4155 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4156 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4157 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4158 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4159 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4160 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4161 (handle_vmptrld).
4162 We can NOT enable shadow_vmcs here because we don't have yet
4163 a current VMCS12
4164 */
4165 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4166 return exec_control;
4167}
4168
ce88decf
XG		 4169static void ept_set_mmio_spte_mask(void)
4170{
4171 /*
4172 * EPT Misconfigurations can be generated if the value of bits 2:0
4173 * of an EPT paging-structure entry is 110b (write/execute).
4174 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
4175 * spte.
4176 */
4177 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
4178}
4179
6aa8b732
AK		 4180/*
4181 * Sets up the vmcs for emulated real mode.
4182 */
8b9cf98c 4183static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4184{
2e4ce7f5 4185#ifdef CONFIG_X86_64
6aa8b732 4186 unsigned long a;
2e4ce7f5 4187#endif
6aa8b732 4188 int i;
6aa8b732 4189
6aa8b732 4190 /* I/O */
3e7c73e9
AK		 4191 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4192 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4193
4607c2d7
AG		 4194 if (enable_shadow_vmcs) {
4195 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4196 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4197 }
25c5f225 4198 if (cpu_has_vmx_msr_bitmap())
5897297b 4199 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4200
6aa8b732
AK		 4201 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4202
6aa8b732 4203 /* Control */
01e439be 4204 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4205
bf8179a0 4206 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4207
83ff3b9d 4208 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4209 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4210 vmx_secondary_exec_control(vmx));
83ff3b9d 4211 }
f78e0e2e 4212
01e439be 4213 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4214 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4215 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4216 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4217 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4218
4219 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4220
4221 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4222 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4223 }
4224
4b8d54f9
ZE		 4225 if (ple_gap) {
4226 vmcs_write32(PLE_GAP, ple_gap);
4227 vmcs_write32(PLE_WINDOW, ple_window);
4228 }
4229
c3707958
XG		 4230 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4231 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4232 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4233
9581d442
AK		 4234 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4235 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4236 vmx_set_constant_host_state(vmx);
05b3e0c2 4237#ifdef CONFIG_X86_64
6aa8b732
AK		 4238 rdmsrl(MSR_FS_BASE, a);
4239 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4240 rdmsrl(MSR_GS_BASE, a);
4241 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4242#else
4243 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4244 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4245#endif
4246
2cc51560
ED		 4247 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4248 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4249 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4250 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4251 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4252
468d472f 4253 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4254 u32 msr_low, msr_high;
4255 u64 host_pat;
468d472f
SY		 4256 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4257 host_pat = msr_low | ((u64) msr_high << 32);
4258 /* Write the default value follow host pat */
4259 vmcs_write64(GUEST_IA32_PAT, host_pat);
4260 /* Keep arch.pat sync with GUEST_IA32_PAT */
4261 vmx->vcpu.arch.pat = host_pat;
4262 }
4263
6aa8b732
AK		 4264 for (i = 0; i < NR_VMX_MSR; ++i) {
4265 u32 index = vmx_msr_index[i];
4266 u32 data_low, data_high;
a2fa3e9f 4267 int j = vmx->nmsrs;
6aa8b732
AK		 4268
4269 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4270 continue;
432bd6cb
AK		 4271 if (wrmsr_safe(index, data_low, data_high) < 0)
4272 continue;
26bb0981
AK		 4273 vmx->guest_msrs[j].index = i;
4274 vmx->guest_msrs[j].data = 0;
d5696725 4275 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4276 ++vmx->nmsrs;
6aa8b732 4277 }
6aa8b732 4278
1c3d14fe 4279 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4280
4281 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4282 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4283
e00c8cf2 4284 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4285 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4286
4287 return 0;
4288}
4289
57f252f2 4290static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4291{
4292 struct vcpu_vmx *vmx = to_vmx(vcpu);
4293 u64 msr;
e00c8cf2 4294
7ffd92c5 4295 vmx->rmode.vm86_active = 0;
e00c8cf2 4296
3b86cd99
JK		 4297 vmx->soft_vnmi_blocked = 0;
4298
ad312c7c 4299 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4300 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4301 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4302 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4303 msr |= MSR_IA32_APICBASE_BSP;
4304 kvm_set_apic_base(&vmx->vcpu, msr);
4305
2fb92db1
AK		 4306 vmx_segment_cache_clear(vmx);
4307
5706be0d 4308 seg_setup(VCPU_SREG_CS);
66450a21 4309 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4310 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4311
4312 seg_setup(VCPU_SREG_DS);
4313 seg_setup(VCPU_SREG_ES);
4314 seg_setup(VCPU_SREG_FS);
4315 seg_setup(VCPU_SREG_GS);
4316 seg_setup(VCPU_SREG_SS);
4317
4318 vmcs_write16(GUEST_TR_SELECTOR, 0);
4319 vmcs_writel(GUEST_TR_BASE, 0);
4320 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4321 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4322
4323 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4324 vmcs_writel(GUEST_LDTR_BASE, 0);
4325 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4326 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4327
4328 vmcs_write32(GUEST_SYSENTER_CS, 0);
4329 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4330 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4331
4332 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4333 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4334
e00c8cf2
AK		 4335 vmcs_writel(GUEST_GDTR_BASE, 0);
4336 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4337
4338 vmcs_writel(GUEST_IDTR_BASE, 0);
4339 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4340
443381a8 4341 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4342 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4343 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4344
e00c8cf2
AK		 4345 /* Special registers */
4346 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4347
4348 setup_msrs(vmx);
4349
6aa8b732
AK		 4350 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4351
f78e0e2e
SY		 4352 if (cpu_has_vmx_tpr_shadow()) {
4353 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4354 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4355 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4356 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4357 vmcs_write32(TPR_THRESHOLD, 0);
4358 }
4359
4360 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4361 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4362 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4363
01e439be
YZ		 4364 if (vmx_vm_has_apicv(vcpu->kvm))
4365 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4366
2384d2b3
SY		 4367 if (vmx->vpid != 0)
4368 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4369
fa40052c 4370 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4371 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4372 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4373 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4374 vmx_fpu_activate(&vmx->vcpu);
4375 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4376
b9d762fa 4377 vpid_sync_context(vmx);
6aa8b732
AK		 4378}
4379
b6f1250e
NHE		 4380/*
4381 * In nested virtualization, check if L1 asked to exit on external interrupts.
4382 * For most existing hypervisors, this will always return true.
4383 */
4384static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4385{
4386 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4387 PIN_BASED_EXT_INTR_MASK;
4388}
4389
3b86cd99
JK		 4390static void enable_irq_window(struct kvm_vcpu *vcpu)
4391{
4392 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4393 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4394 /*
4395 * We get here if vmx_interrupt_allowed() said we can't
4396 * inject to L1 now because L2 must run. Ask L2 to exit
4397 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4398 */
d6185f20 4399 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4400 return;
d6185f20 4401 }
3b86cd99
JK		 4402
4403 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4404 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4405 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4406}
4407
4408static void enable_nmi_window(struct kvm_vcpu *vcpu)
4409{
4410 u32 cpu_based_vm_exec_control;
4411
4412 if (!cpu_has_virtual_nmis()) {
4413 enable_irq_window(vcpu);
4414 return;
4415 }
4416
30bd0c4c
AK		 4417 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4418 enable_irq_window(vcpu);
4419 return;
4420 }
3b86cd99
JK		 4421 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4422 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4423 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4424}
4425
66fd3f7f 4426static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4427{
9c8cba37 4428 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4429 uint32_t intr;
4430 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4431
229456fc 4432 trace_kvm_inj_virq(irq);
2714d1d3 4433
fa89a817 4434 ++vcpu->stat.irq_injections;
7ffd92c5 4435 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4436 int inc_eip = 0;
4437 if (vcpu->arch.interrupt.soft)
4438 inc_eip = vcpu->arch.event_exit_inst_len;
4439 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4440 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4441 return;
4442 }
66fd3f7f
GN		 4443 intr = irq | INTR_INFO_VALID_MASK;
4444 if (vcpu->arch.interrupt.soft) {
4445 intr |= INTR_TYPE_SOFT_INTR;
4446 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4447 vmx->vcpu.arch.event_exit_inst_len);
4448 } else
4449 intr |= INTR_TYPE_EXT_INTR;
4450 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4451}
4452
f08864b4
SY		 4453static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4454{
66a5a347
JK		 4455 struct vcpu_vmx *vmx = to_vmx(vcpu);
4456
0b6ac343
NHE		 4457 if (is_guest_mode(vcpu))
4458 return;
4459
3b86cd99
JK		 4460 if (!cpu_has_virtual_nmis()) {
4461 /*
4462 * Tracking the NMI-blocked state in software is built upon
4463 * finding the next open IRQ window. This, in turn, depends on
4464 * well-behaving guests: They have to keep IRQs disabled at
4465 * least as long as the NMI handler runs. Otherwise we may
4466 * cause NMI nesting, maybe breaking the guest. But as this is
4467 * highly unlikely, we can live with the residual risk.
4468 */
4469 vmx->soft_vnmi_blocked = 1;
4470 vmx->vnmi_blocked_time = 0;
4471 }
4472
487b391d 4473 ++vcpu->stat.nmi_injections;
9d58b931 4474 vmx->nmi_known_unmasked = false;
7ffd92c5 4475 if (vmx->rmode.vm86_active) {
71f9833b 4476 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4477 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4478 return;
4479 }
f08864b4
SY		 4480 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4481 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4482}
4483
c4282df9 4484static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4485{
3b86cd99 4486 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4487 return 0;
33f089ca 4488
c4282df9 4489 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4490 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4491 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4492}
4493
3cfc3092
JK		 4494static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4495{
4496 if (!cpu_has_virtual_nmis())
4497 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4498 if (to_vmx(vcpu)->nmi_known_unmasked)
4499 return false;
c332c83a 4500 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4501}
4502
4503static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4504{
4505 struct vcpu_vmx *vmx = to_vmx(vcpu);
4506
4507 if (!cpu_has_virtual_nmis()) {
4508 if (vmx->soft_vnmi_blocked != masked) {
4509 vmx->soft_vnmi_blocked = masked;
4510 vmx->vnmi_blocked_time = 0;
4511 }
4512 } else {
9d58b931 4513 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4514 if (masked)
4515 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4516 GUEST_INTR_STATE_NMI);
4517 else
4518 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4519 GUEST_INTR_STATE_NMI);
4520 }
4521}
4522
78646121
GN		 4523static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4524{
e8457c67 4525 if (is_guest_mode(vcpu)) {
51cfe38e 4526 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4527
4528 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4529 return 0;
e8457c67
JK		 4530 if (nested_exit_on_intr(vcpu)) {
4531 nested_vmx_vmexit(vcpu);
4532 vmcs12->vm_exit_reason =
4533 EXIT_REASON_EXTERNAL_INTERRUPT;
4534 vmcs12->vm_exit_intr_info = 0;
4535 /*
4536 * fall through to normal code, but now in L1, not L2
4537 */
4538 }
b6f1250e
NHE		 4539 }
4540
c4282df9
GN		 4541 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4542 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4543 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4544}
4545
cbc94022
IE		 4546static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4547{
4548 int ret;
4549 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4550 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4551 .guest_phys_addr = addr,
4552 .memory_size = PAGE_SIZE * 3,
4553 .flags = 0,
4554 };
4555
47ae31e2 4556 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4557 if (ret)
4558 return ret;
bfc6d222 4559 kvm->arch.tss_addr = addr;
93ea5388
GN		 4560 if (!init_rmode_tss(kvm))
4561 return -ENOMEM;
4562
cbc94022
IE		 4563 return 0;
4564}
4565
0ca1b4f4 4566static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4567{
77ab6db0 4568 switch (vec) {
77ab6db0 4569 case BP_VECTOR:
c573cd22
JK		 4570 /*
4571 * Update instruction length as we may reinject the exception
4572 * from user space while in guest debugging mode.
4573 */
4574 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4575 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4576 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4577 return false;
4578 /* fall through */
4579 case DB_VECTOR:
4580 if (vcpu->guest_debug &
4581 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4582 return false;
d0bfb940
JK		 4583 /* fall through */
4584 case DE_VECTOR:
77ab6db0
JK		 4585 case OF_VECTOR:
4586 case BR_VECTOR:
4587 case UD_VECTOR:
4588 case DF_VECTOR:
4589 case SS_VECTOR:
4590 case GP_VECTOR:
4591 case MF_VECTOR:
0ca1b4f4
GN		 4592 return true;
4593 break;
77ab6db0 4594 }
0ca1b4f4
GN		 4595 return false;
4596}
4597
4598static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4599 int vec, u32 err_code)
4600{
4601 /*
4602 * Instruction with address size override prefix opcode 0x67
4603 * Cause the #SS fault with 0 error code in VM86 mode.
4604 */
4605 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4606 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4607 if (vcpu->arch.halt_request) {
4608 vcpu->arch.halt_request = 0;
4609 return kvm_emulate_halt(vcpu);
4610 }
4611 return 1;
4612 }
4613 return 0;
4614 }
4615
4616 /*
4617 * Forward all other exceptions that are valid in real mode.
4618 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4619 * the required debugging infrastructure rework.
4620 */
4621 kvm_queue_exception(vcpu, vec);
4622 return 1;
6aa8b732
AK		 4623}
4624
a0861c02
AK		 4625/*
4626 * Trigger machine check on the host. We assume all the MSRs are already set up
4627 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4628 * We pass a fake environment to the machine check handler because we want
4629 * the guest to be always treated like user space, no matter what context
4630 * it used internally.
4631 */
4632static void kvm_machine_check(void)
4633{
4634#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4635 struct pt_regs regs = {
4636 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4637 .flags = X86_EFLAGS_IF,
4638 };
4639
4640 do_machine_check(&regs, 0);
4641#endif
4642}
4643
851ba692 4644static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4645{
4646 /* already handled by vcpu_run */
4647 return 1;
4648}
4649
851ba692 4650static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4651{
1155f76a 4652 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4653 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4654 u32 intr_info, ex_no, error_code;
42dbaa5a 4655 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4656 u32 vect_info;
4657 enum emulation_result er;
4658
1155f76a 4659 vect_info = vmx->idt_vectoring_info;
88786475 4660 intr_info = vmx->exit_intr_info;
6aa8b732 4661
a0861c02 4662 if (is_machine_check(intr_info))
851ba692 4663 return handle_machine_check(vcpu);
a0861c02 4664
e4a41889 4665 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4666 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4667
4668 if (is_no_device(intr_info)) {
5fd86fcf 4669 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4670 return 1;
4671 }
4672
7aa81cc0 4673 if (is_invalid_opcode(intr_info)) {
51d8b661 4674 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4675 if (er != EMULATE_DONE)
7ee5d940 4676 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4677 return 1;
4678 }
4679
6aa8b732 4680 error_code = 0;
2e11384c 4681 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4682 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4683
4684 /*
4685 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4686 * MMIO, it is better to report an internal error.
4687 * See the comments in vmx_handle_exit.
4688 */
4689 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4690 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4691 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4692 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4693 vcpu->run->internal.ndata = 2;
4694 vcpu->run->internal.data[0] = vect_info;
4695 vcpu->run->internal.data[1] = intr_info;
4696 return 0;
4697 }
4698
6aa8b732 4699 if (is_page_fault(intr_info)) {
1439442c 4700 /* EPT won't cause page fault directly */
cf3ace79 4701 BUG_ON(enable_ept);
6aa8b732 4702 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4703 trace_kvm_page_fault(cr2, error_code);
4704
3298b75c 4705 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4706 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4707 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4708 }
4709
d0bfb940 4710 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4711
4712 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4713 return handle_rmode_exception(vcpu, ex_no, error_code);
4714
42dbaa5a
JK		 4715 switch (ex_no) {
4716 case DB_VECTOR:
4717 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4718 if (!(vcpu->guest_debug &
4719 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4720 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4721 kvm_queue_exception(vcpu, DB_VECTOR);
4722 return 1;
4723 }
4724 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4725 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4726 /* fall through */
4727 case BP_VECTOR:
c573cd22
JK		 4728 /*
4729 * Update instruction length as we may reinject #BP from
4730 * user space while in guest debugging mode. Reading it for
4731 * #DB as well causes no harm, it is not used in that case.
4732 */
4733 vmx->vcpu.arch.event_exit_inst_len =
4734 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4735 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4736 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4737 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4738 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4739 break;
4740 default:
d0bfb940
JK		 4741 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4742 kvm_run->ex.exception = ex_no;
4743 kvm_run->ex.error_code = error_code;
42dbaa5a 4744 break;
6aa8b732 4745 }
6aa8b732
AK		 4746 return 0;
4747}
4748
851ba692 4749static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4750{
1165f5fe 4751 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4752 return 1;
4753}
4754
851ba692 4755static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4756{
851ba692 4757 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4758 return 0;
4759}
6aa8b732 4760
851ba692 4761static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4762{
bfdaab09 4763 unsigned long exit_qualification;
34c33d16 4764 int size, in, string;
039576c0 4765 unsigned port;
6aa8b732 4766
bfdaab09 4767 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4768 string = (exit_qualification & 16) != 0;
cf8f70bf 4769 in = (exit_qualification & 8) != 0;
e70669ab 4770
cf8f70bf 4771 ++vcpu->stat.io_exits;
e70669ab 4772
cf8f70bf 4773 if (string || in)
51d8b661 4774 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4775
cf8f70bf
GN		 4776 port = exit_qualification >> 16;
4777 size = (exit_qualification & 7) + 1;
e93f36bc 4778 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4779
4780 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4781}
4782
102d8325
IM		 4783static void
4784vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4785{
4786 /*
4787 * Patch in the VMCALL instruction:
4788 */
4789 hypercall[0] = 0x0f;
4790 hypercall[1] = 0x01;
4791 hypercall[2] = 0xc1;
102d8325
IM		 4792}
4793
0fa06071 4794/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4795static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4796{
eeadf9e7 4797 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4798 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4799 unsigned long orig_val = val;
4800
eeadf9e7
NHE		 4801 /*
4802 * We get here when L2 changed cr0 in a way that did not change
4803 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4804 * but did change L0 shadowed bits. So we first calculate the
4805 * effective cr0 value that L1 would like to write into the
4806 * hardware. It consists of the L2-owned bits from the new
4807 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4808 */
1a0d74e6
JK		 4809 val = (val & ~vmcs12->cr0_guest_host_mask) |
4810 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4811
4812 /* TODO: will have to take unrestricted guest mode into
4813 * account */
4814 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4815 return 1;
1a0d74e6
JK		 4816
4817 if (kvm_set_cr0(vcpu, val))
4818 return 1;
4819 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4820 return 0;
1a0d74e6
JK		 4821 } else {
4822 if (to_vmx(vcpu)->nested.vmxon &&
4823 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4824 return 1;
eeadf9e7 4825 return kvm_set_cr0(vcpu, val);
1a0d74e6 4826 }
eeadf9e7
NHE		 4827}
4828
4829static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4830{
4831 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4832 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4833 unsigned long orig_val = val;
4834
4835 /* analogously to handle_set_cr0 */
4836 val = (val & ~vmcs12->cr4_guest_host_mask) |
4837 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4838 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4839 return 1;
1a0d74e6 4840 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4841 return 0;
4842 } else
4843 return kvm_set_cr4(vcpu, val);
4844}
4845
4846/* called to set cr0 as approriate for clts instruction exit. */
4847static void handle_clts(struct kvm_vcpu *vcpu)
4848{
4849 if (is_guest_mode(vcpu)) {
4850 /*
4851 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4852 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4853 * just pretend it's off (also in arch.cr0 for fpu_activate).
4854 */
4855 vmcs_writel(CR0_READ_SHADOW,
4856 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4857 vcpu->arch.cr0 &= ~X86_CR0_TS;
4858 } else
4859 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4860}
4861
851ba692 4862static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4863{
229456fc 4864 unsigned long exit_qualification, val;
6aa8b732
AK		 4865 int cr;
4866 int reg;
49a9b07e 4867 int err;
6aa8b732 4868
bfdaab09 4869 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4870 cr = exit_qualification & 15;
4871 reg = (exit_qualification >> 8) & 15;
4872 switch ((exit_qualification >> 4) & 3) {
4873 case 0: /* mov to cr */
229456fc
MT		 4874 val = kvm_register_read(vcpu, reg);
4875 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4876 switch (cr) {
4877 case 0:
eeadf9e7 4878 err = handle_set_cr0(vcpu, val);
db8fcefa 4879 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4880 return 1;
4881 case 3:
2390218b 4882 err = kvm_set_cr3(vcpu, val);
db8fcefa 4883 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4884 return 1;
4885 case 4:
eeadf9e7 4886 err = handle_set_cr4(vcpu, val);
db8fcefa 4887 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4888 return 1;
0a5fff19
GN		 4889 case 8: {
4890 u8 cr8_prev = kvm_get_cr8(vcpu);
4891 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4892 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4893 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4894 if (irqchip_in_kernel(vcpu->kvm))
4895 return 1;
4896 if (cr8_prev <= cr8)
4897 return 1;
851ba692 4898 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4899 return 0;
4900 }
4b8073e4 4901 }
6aa8b732 4902 break;
25c4c276 4903 case 2: /* clts */
eeadf9e7 4904 handle_clts(vcpu);
4d4ec087 4905 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4906 skip_emulated_instruction(vcpu);
6b52d186 4907 vmx_fpu_activate(vcpu);
25c4c276 4908 return 1;
6aa8b732
AK		 4909 case 1: /*mov from cr*/
4910 switch (cr) {
4911 case 3:
9f8fe504
AK		 4912 val = kvm_read_cr3(vcpu);
4913 kvm_register_write(vcpu, reg, val);
4914 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4915 skip_emulated_instruction(vcpu);
4916 return 1;
4917 case 8:
229456fc
MT		 4918 val = kvm_get_cr8(vcpu);
4919 kvm_register_write(vcpu, reg, val);
4920 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4921 skip_emulated_instruction(vcpu);
4922 return 1;
4923 }
4924 break;
4925 case 3: /* lmsw */
a1f83a74 4926 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4927 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4928 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4929
4930 skip_emulated_instruction(vcpu);
4931 return 1;
4932 default:
4933 break;
4934 }
851ba692 4935 vcpu->run->exit_reason = 0;
a737f256 4936 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4937 (int)(exit_qualification >> 4) & 3, cr);
4938 return 0;
4939}
4940
851ba692 4941static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4942{
bfdaab09 4943 unsigned long exit_qualification;
6aa8b732
AK		 4944 int dr, reg;
4945
f2483415 4946 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4947 if (!kvm_require_cpl(vcpu, 0))
4948 return 1;
42dbaa5a
JK		 4949 dr = vmcs_readl(GUEST_DR7);
4950 if (dr & DR7_GD) {
4951 /*
4952 * As the vm-exit takes precedence over the debug trap, we
4953 * need to emulate the latter, either for the host or the
4954 * guest debugging itself.
4955 */
4956 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4957 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4958 vcpu->run->debug.arch.dr7 = dr;
4959 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4960 vmcs_readl(GUEST_CS_BASE) +
4961 vmcs_readl(GUEST_RIP);
851ba692
AK		 4962 vcpu->run->debug.arch.exception = DB_VECTOR;
4963 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4964 return 0;
4965 } else {
4966 vcpu->arch.dr7 &= ~DR7_GD;
4967 vcpu->arch.dr6 |= DR6_BD;
4968 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4969 kvm_queue_exception(vcpu, DB_VECTOR);
4970 return 1;
4971 }
4972 }
4973
bfdaab09 4974 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4975 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4976 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4977 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4978 unsigned long val;
4979 if (!kvm_get_dr(vcpu, dr, &val))
4980 kvm_register_write(vcpu, reg, val);
4981 } else
4982 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4983 skip_emulated_instruction(vcpu);
4984 return 1;
4985}
4986
020df079
GN		 4987static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4988{
4989 vmcs_writel(GUEST_DR7, val);
4990}
4991
851ba692 4992static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4993{
06465c5a
AK		 4994 kvm_emulate_cpuid(vcpu);
4995 return 1;
6aa8b732
AK		 4996}
4997
851ba692 4998static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4999{
ad312c7c 5000 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5001 u64 data;
5002
5003 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5004 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5005 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5006 return 1;
5007 }
5008
229456fc 5009 trace_kvm_msr_read(ecx, data);
2714d1d3 5010
6aa8b732 5011 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5012 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5013 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5014 skip_emulated_instruction(vcpu);
5015 return 1;
5016}
5017
851ba692 5018static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5019{
8fe8ab46 5020 struct msr_data msr;
ad312c7c
ZX		 5021 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5022 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5023 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5024
8fe8ab46
WA		 5025 msr.data = data;
5026 msr.index = ecx;
5027 msr.host_initiated = false;
5028 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5029 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5030 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5031 return 1;
5032 }
5033
59200273 5034 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5035 skip_emulated_instruction(vcpu);
5036 return 1;
5037}
5038
851ba692 5039static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5040{
3842d135 5041 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5042 return 1;
5043}
5044
851ba692 5045static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5046{
85f455f7
ED		 5047 u32 cpu_based_vm_exec_control;
5048
5049 /* clear pending irq */
5050 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5051 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5052 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5053
3842d135
AK		 5054 kvm_make_request(KVM_REQ_EVENT, vcpu);
5055
a26bf12a 5056 ++vcpu->stat.irq_window_exits;
2714d1d3 5057
c1150d8c
DL		 5058 /*
5059 * If the user space waits to inject interrupts, exit as soon as
5060 * possible
5061 */
8061823a 5062 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5063 vcpu->run->request_interrupt_window &&
8061823a 5064 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5065 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5066 return 0;
5067 }
6aa8b732
AK		 5068 return 1;
5069}
5070
851ba692 5071static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5072{
5073 skip_emulated_instruction(vcpu);
d3bef15f 5074 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5075}
5076
851ba692 5077static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5078{
510043da 5079 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5080 kvm_emulate_hypercall(vcpu);
5081 return 1;
c21415e8
IM		 5082}
5083
ec25d5e6
GN		 5084static int handle_invd(struct kvm_vcpu *vcpu)
5085{
51d8b661 5086 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5087}
5088
851ba692 5089static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5090{
f9c617f6 5091 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5092
5093 kvm_mmu_invlpg(vcpu, exit_qualification);
5094 skip_emulated_instruction(vcpu);
5095 return 1;
5096}
5097
fee84b07
AK		 5098static int handle_rdpmc(struct kvm_vcpu *vcpu)
5099{
5100 int err;
5101
5102 err = kvm_rdpmc(vcpu);
5103 kvm_complete_insn_gp(vcpu, err);
5104
5105 return 1;
5106}
5107
851ba692 5108static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5109{
5110 skip_emulated_instruction(vcpu);
f5f48ee1 5111 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5112 return 1;
5113}
5114
2acf923e
DC		 5115static int handle_xsetbv(struct kvm_vcpu *vcpu)
5116{
5117 u64 new_bv = kvm_read_edx_eax(vcpu);
5118 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5119
5120 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5121 skip_emulated_instruction(vcpu);
5122 return 1;
5123}
5124
851ba692 5125static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5126{
58fbbf26
KT		 5127 if (likely(fasteoi)) {
5128 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5129 int access_type, offset;
5130
5131 access_type = exit_qualification & APIC_ACCESS_TYPE;
5132 offset = exit_qualification & APIC_ACCESS_OFFSET;
5133 /*
5134 * Sane guest uses MOV to write EOI, with written value
5135 * not cared. So make a short-circuit here by avoiding
5136 * heavy instruction emulation.
5137 */
5138 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5139 (offset == APIC_EOI)) {
5140 kvm_lapic_set_eoi(vcpu);
5141 skip_emulated_instruction(vcpu);
5142 return 1;
5143 }
5144 }
51d8b661 5145 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5146}
5147
c7c9c56c
YZ		 5148static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5149{
5150 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5151 int vector = exit_qualification & 0xff;
5152
5153 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5154 kvm_apic_set_eoi_accelerated(vcpu, vector);
5155 return 1;
5156}
5157
83d4c286
YZ		 5158static int handle_apic_write(struct kvm_vcpu *vcpu)
5159{
5160 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5161 u32 offset = exit_qualification & 0xfff;
5162
5163 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5164 kvm_apic_write_nodecode(vcpu, offset);
5165 return 1;
5166}
5167
851ba692 5168static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5169{
60637aac 5170 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5171 unsigned long exit_qualification;
e269fb21
JK		 5172 bool has_error_code = false;
5173 u32 error_code = 0;
37817f29 5174 u16 tss_selector;
7f3d35fd 5175 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5176
5177 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5178 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5179 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5180
5181 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5182
5183 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5184 if (reason == TASK_SWITCH_GATE && idt_v) {
5185 switch (type) {
5186 case INTR_TYPE_NMI_INTR:
5187 vcpu->arch.nmi_injected = false;
654f06fc 5188 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5189 break;
5190 case INTR_TYPE_EXT_INTR:
66fd3f7f 5191 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5192 kvm_clear_interrupt_queue(vcpu);
5193 break;
5194 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5195 if (vmx->idt_vectoring_info &
5196 VECTORING_INFO_DELIVER_CODE_MASK) {
5197 has_error_code = true;
5198 error_code =
5199 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5200 }
5201 /* fall through */
64a7ec06
GN		 5202 case INTR_TYPE_SOFT_EXCEPTION:
5203 kvm_clear_exception_queue(vcpu);
5204 break;
5205 default:
5206 break;
5207 }
60637aac 5208 }
37817f29
IE		 5209 tss_selector = exit_qualification;
5210
64a7ec06
GN		 5211 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5212 type != INTR_TYPE_EXT_INTR &&
5213 type != INTR_TYPE_NMI_INTR))
5214 skip_emulated_instruction(vcpu);
5215
7f3d35fd
KW		 5216 if (kvm_task_switch(vcpu, tss_selector,
5217 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5218 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5219 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5220 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5221 vcpu->run->internal.ndata = 0;
42dbaa5a 5222 return 0;
acb54517 5223 }
42dbaa5a
JK		 5224
5225 /* clear all local breakpoint enable flags */
5226 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5227
5228 /*
5229 * TODO: What about debug traps on tss switch?
5230 * Are we supposed to inject them and update dr6?
5231 */
5232
5233 return 1;
37817f29
IE		 5234}
5235
851ba692 5236static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5237{
f9c617f6 5238 unsigned long exit_qualification;
1439442c 5239 gpa_t gpa;
4f5982a5 5240 u32 error_code;
1439442c 5241 int gla_validity;
1439442c 5242
f9c617f6 5243 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5244
1439442c
SY		 5245 gla_validity = (exit_qualification >> 7) & 0x3;
5246 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5247 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5248 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5249 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5250 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5251 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5252 (long unsigned int)exit_qualification);
851ba692
AK		 5253 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5254 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5255 return 0;
1439442c
SY		 5256 }
5257
5258 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5259 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5260
5261 /* It is a write fault? */
5262 error_code = exit_qualification & (1U << 1);
5263 /* ept page table is present? */
5264 error_code |= (exit_qualification >> 3) & 0x1;
5265
5266 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5267}
5268
68f89400
MT		 5269static u64 ept_rsvd_mask(u64 spte, int level)
5270{
5271 int i;
5272 u64 mask = 0;
5273
5274 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5275 mask |= (1ULL << i);
5276
5277 if (level > 2)
5278 /* bits 7:3 reserved */
5279 mask |= 0xf8;
5280 else if (level == 2) {
5281 if (spte & (1ULL << 7))
5282 /* 2MB ref, bits 20:12 reserved */
5283 mask |= 0x1ff000;
5284 else
5285 /* bits 6:3 reserved */
5286 mask |= 0x78;
5287 }
5288
5289 return mask;
5290}
5291
5292static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5293 int level)
5294{
5295 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5296
5297 /* 010b (write-only) */
5298 WARN_ON((spte & 0x7) == 0x2);
5299
5300 /* 110b (write/execute) */
5301 WARN_ON((spte & 0x7) == 0x6);
5302
5303 /* 100b (execute-only) and value not supported by logical processor */
5304 if (!cpu_has_vmx_ept_execute_only())
5305 WARN_ON((spte & 0x7) == 0x4);
5306
5307 /* not 000b */
5308 if ((spte & 0x7)) {
5309 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5310
5311 if (rsvd_bits != 0) {
5312 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5313 __func__, rsvd_bits);
5314 WARN_ON(1);
5315 }
5316
5317 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5318 u64 ept_mem_type = (spte & 0x38) >> 3;
5319
5320 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5321 ept_mem_type == 7) {
5322 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5323 __func__, ept_mem_type);
5324 WARN_ON(1);
5325 }
5326 }
5327 }
5328}
5329
851ba692 5330static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5331{
5332 u64 sptes[4];
ce88decf 5333 int nr_sptes, i, ret;
68f89400
MT		 5334 gpa_t gpa;
5335
5336 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5337
ce88decf
XG		 5338 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5339 if (likely(ret == 1))
5340 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5341 EMULATE_DONE;
5342 if (unlikely(!ret))
5343 return 1;
5344
5345 /* It is the real ept misconfig */
68f89400
MT		 5346 printk(KERN_ERR "EPT: Misconfiguration.\n");
5347 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5348
5349 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5350
5351 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5352 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5353
851ba692
AK		 5354 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5355 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5356
5357 return 0;
5358}
5359
851ba692 5360static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5361{
5362 u32 cpu_based_vm_exec_control;
5363
5364 /* clear pending NMI */
5365 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5366 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5367 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5368 ++vcpu->stat.nmi_window_exits;
3842d135 5369 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5370
5371 return 1;
5372}
5373
80ced186 5374static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5375{
8b3079a5
AK		 5376 struct vcpu_vmx *vmx = to_vmx(vcpu);
5377 enum emulation_result err = EMULATE_DONE;
80ced186 5378 int ret = 1;
49e9d557
AK		 5379 u32 cpu_exec_ctrl;
5380 bool intr_window_requested;
b8405c18 5381 unsigned count = 130;
49e9d557
AK		 5382
5383 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5384 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5385
b8405c18 5386 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5387 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5388 return handle_interrupt_window(&vmx->vcpu);
5389
de87dcdd
AK		 5390 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5391 return 1;
5392
991eebf9 5393 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5394
80ced186
MG		 5395 if (err == EMULATE_DO_MMIO) {
5396 ret = 0;
5397 goto out;
5398 }
1d5a4d9b 5399
de5f70e0
AK		 5400 if (err != EMULATE_DONE) {
5401 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5402 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5403 vcpu->run->internal.ndata = 0;
6d77dbfc 5404 return 0;
de5f70e0 5405 }
ea953ef0
MG		 5406
5407 if (signal_pending(current))
80ced186 5408 goto out;
ea953ef0
MG		 5409 if (need_resched())
5410 schedule();
5411 }
5412
14168786 5413 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5414out:
5415 return ret;
ea953ef0
MG		 5416}
5417
4b8d54f9
ZE		 5418/*
5419 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5420 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5421 */
9fb41ba8 5422static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5423{
5424 skip_emulated_instruction(vcpu);
5425 kvm_vcpu_on_spin(vcpu);
5426
5427 return 1;
5428}
5429
59708670
SY		 5430static int handle_invalid_op(struct kvm_vcpu *vcpu)
5431{
5432 kvm_queue_exception(vcpu, UD_VECTOR);
5433 return 1;
5434}
5435
ff2f6fe9
NHE		 5436/*
5437 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5438 * We could reuse a single VMCS for all the L2 guests, but we also want the
5439 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5440 * allows keeping them loaded on the processor, and in the future will allow
5441 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5442 * every entry if they never change.
5443 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5444 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5445 *
5446 * The following functions allocate and free a vmcs02 in this pool.
5447 */
5448
5449/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5450static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5451{
5452 struct vmcs02_list *item;
5453 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5454 if (item->vmptr == vmx->nested.current_vmptr) {
5455 list_move(&item->list, &vmx->nested.vmcs02_pool);
5456 return &item->vmcs02;
5457 }
5458
5459 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5460 /* Recycle the least recently used VMCS. */
5461 item = list_entry(vmx->nested.vmcs02_pool.prev,
5462 struct vmcs02_list, list);
5463 item->vmptr = vmx->nested.current_vmptr;
5464 list_move(&item->list, &vmx->nested.vmcs02_pool);
5465 return &item->vmcs02;
5466 }
5467
5468 /* Create a new VMCS */
0fa24ce3 5469 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5470 if (!item)
5471 return NULL;
5472 item->vmcs02.vmcs = alloc_vmcs();
5473 if (!item->vmcs02.vmcs) {
5474 kfree(item);
5475 return NULL;
5476 }
5477 loaded_vmcs_init(&item->vmcs02);
5478 item->vmptr = vmx->nested.current_vmptr;
5479 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5480 vmx->nested.vmcs02_num++;
5481 return &item->vmcs02;
5482}
5483
5484/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5485static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5486{
5487 struct vmcs02_list *item;
5488 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5489 if (item->vmptr == vmptr) {
5490 free_loaded_vmcs(&item->vmcs02);
5491 list_del(&item->list);
5492 kfree(item);
5493 vmx->nested.vmcs02_num--;
5494 return;
5495 }
5496}
5497
5498/*
5499 * Free all VMCSs saved for this vcpu, except the one pointed by
5500 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5501 * currently used, if running L2), and vmcs01 when running L2.
5502 */
5503static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5504{
5505 struct vmcs02_list *item, *n;
5506 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5507 if (vmx->loaded_vmcs != &item->vmcs02)
5508 free_loaded_vmcs(&item->vmcs02);
5509 list_del(&item->list);
5510 kfree(item);
5511 }
5512 vmx->nested.vmcs02_num = 0;
5513
5514 if (vmx->loaded_vmcs != &vmx->vmcs01)
5515 free_loaded_vmcs(&vmx->vmcs01);
5516}
5517
145c28dd
AG		 5518static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5519 u32 vm_instruction_error);
5520
ec378aee
NHE		 5521/*
5522 * Emulate the VMXON instruction.
5523 * Currently, we just remember that VMX is active, and do not save or even
5524 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5525 * do not currently need to store anything in that guest-allocated memory
5526 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5527 * argument is different from the VMXON pointer (which the spec says they do).
5528 */
5529static int handle_vmon(struct kvm_vcpu *vcpu)
5530{
5531 struct kvm_segment cs;
5532 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5533 struct vmcs *shadow_vmcs;
ec378aee
NHE		 5534
5535 /* The Intel VMX Instruction Reference lists a bunch of bits that
5536 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5537 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5538 * Otherwise, we should fail with #UD. We test these now:
5539 */
5540 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5541 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5542 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5543 kvm_queue_exception(vcpu, UD_VECTOR);
5544 return 1;
5545 }
5546
5547 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5548 if (is_long_mode(vcpu) && !cs.l) {
5549 kvm_queue_exception(vcpu, UD_VECTOR);
5550 return 1;
5551 }
5552
5553 if (vmx_get_cpl(vcpu)) {
5554 kvm_inject_gp(vcpu, 0);
5555 return 1;
5556 }
145c28dd
AG		 5557 if (vmx->nested.vmxon) {
5558 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5559 skip_emulated_instruction(vcpu);
5560 return 1;
5561 }
8de48833
AG		 5562 if (enable_shadow_vmcs) {
5563 shadow_vmcs = alloc_vmcs();
5564 if (!shadow_vmcs)
5565 return -ENOMEM;
5566 /* mark vmcs as shadow */
5567 shadow_vmcs->revision_id |= (1u << 31);
5568 /* init shadow vmcs */
5569 vmcs_clear(shadow_vmcs);
5570 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5571 }
ec378aee 5572
ff2f6fe9
NHE		 5573 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5574 vmx->nested.vmcs02_num = 0;
5575
ec378aee
NHE		 5576 vmx->nested.vmxon = true;
5577
5578 skip_emulated_instruction(vcpu);
5579 return 1;
5580}
5581
5582/*
5583 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5584 * for running VMX instructions (except VMXON, whose prerequisites are
5585 * slightly different). It also specifies what exception to inject otherwise.
5586 */
5587static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5588{
5589 struct kvm_segment cs;
5590 struct vcpu_vmx *vmx = to_vmx(vcpu);
5591
5592 if (!vmx->nested.vmxon) {
5593 kvm_queue_exception(vcpu, UD_VECTOR);
5594 return 0;
5595 }
5596
5597 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5598 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5599 (is_long_mode(vcpu) && !cs.l)) {
5600 kvm_queue_exception(vcpu, UD_VECTOR);
5601 return 0;
5602 }
5603
5604 if (vmx_get_cpl(vcpu)) {
5605 kvm_inject_gp(vcpu, 0);
5606 return 0;
5607 }
5608
5609 return 1;
5610}
5611
e7953d7f
AG		 5612static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5613{
5614 kunmap(vmx->nested.current_vmcs12_page);
5615 nested_release_page(vmx->nested.current_vmcs12_page);
5616}
5617
ec378aee
NHE		 5618/*
5619 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5620 * just stops using VMX.
5621 */
5622static void free_nested(struct vcpu_vmx *vmx)
5623{
5624 if (!vmx->nested.vmxon)
5625 return;
5626 vmx->nested.vmxon = false;
a9d30f33 5627 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5628 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5629 vmx->nested.current_vmptr = -1ull;
5630 vmx->nested.current_vmcs12 = NULL;
5631 }
e7953d7f
AG		 5632 if (enable_shadow_vmcs)
5633 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5634 /* Unpin physical memory we referred to in current vmcs02 */
5635 if (vmx->nested.apic_access_page) {
5636 nested_release_page(vmx->nested.apic_access_page);
5637 vmx->nested.apic_access_page = 0;
5638 }
ff2f6fe9
NHE		 5639
5640 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5641}
5642
5643/* Emulate the VMXOFF instruction */
5644static int handle_vmoff(struct kvm_vcpu *vcpu)
5645{
5646 if (!nested_vmx_check_permission(vcpu))
5647 return 1;
5648 free_nested(to_vmx(vcpu));
5649 skip_emulated_instruction(vcpu);
5650 return 1;
5651}
5652
064aea77
NHE		 5653/*
5654 * Decode the memory-address operand of a vmx instruction, as recorded on an
5655 * exit caused by such an instruction (run by a guest hypervisor).
5656 * On success, returns 0. When the operand is invalid, returns 1 and throws
5657 * #UD or #GP.
5658 */
5659static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5660 unsigned long exit_qualification,
5661 u32 vmx_instruction_info, gva_t *ret)
5662{
5663 /*
5664 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5665 * Execution", on an exit, vmx_instruction_info holds most of the
5666 * addressing components of the operand. Only the displacement part
5667 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5668 * For how an actual address is calculated from all these components,
5669 * refer to Vol. 1, "Operand Addressing".
5670 */
5671 int scaling = vmx_instruction_info & 3;
5672 int addr_size = (vmx_instruction_info >> 7) & 7;
5673 bool is_reg = vmx_instruction_info & (1u << 10);
5674 int seg_reg = (vmx_instruction_info >> 15) & 7;
5675 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5676 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5677 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5678 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5679
5680 if (is_reg) {
5681 kvm_queue_exception(vcpu, UD_VECTOR);
5682 return 1;
5683 }
5684
5685 /* Addr = segment_base + offset */
5686 /* offset = base + [index * scale] + displacement */
5687 *ret = vmx_get_segment_base(vcpu, seg_reg);
5688 if (base_is_valid)
5689 *ret += kvm_register_read(vcpu, base_reg);
5690 if (index_is_valid)
5691 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5692 *ret += exit_qualification; /* holds the displacement */
5693
5694 if (addr_size == 1) /* 32 bit */
5695 *ret &= 0xffffffff;
5696
5697 /*
5698 * TODO: throw #GP (and return 1) in various cases that the VM*
5699 * instructions require it - e.g., offset beyond segment limit,
5700 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5701 * address, and so on. Currently these are not checked.
5702 */
5703 return 0;
5704}
5705
0140caea
NHE		 5706/*
5707 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5708 * set the success or error code of an emulated VMX instruction, as specified
5709 * by Vol 2B, VMX Instruction Reference, "Conventions".
5710 */
5711static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5712{
5713 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5714 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5715 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5716}
5717
5718static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5719{
5720 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5721 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5722 X86_EFLAGS_SF | X86_EFLAGS_OF))
5723 | X86_EFLAGS_CF);
5724}
5725
5726static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5727 u32 vm_instruction_error)
5728{
5729 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5730 /*
5731 * failValid writes the error number to the current VMCS, which
5732 * can't be done there isn't a current VMCS.
5733 */
5734 nested_vmx_failInvalid(vcpu);
5735 return;
5736 }
5737 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5738 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5739 X86_EFLAGS_SF | X86_EFLAGS_OF))
5740 | X86_EFLAGS_ZF);
5741 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5742}
5743
27d6c865
NHE		 5744/* Emulate the VMCLEAR instruction */
5745static int handle_vmclear(struct kvm_vcpu *vcpu)
5746{
5747 struct vcpu_vmx *vmx = to_vmx(vcpu);
5748 gva_t gva;
5749 gpa_t vmptr;
5750 struct vmcs12 *vmcs12;
5751 struct page *page;
5752 struct x86_exception e;
5753
5754 if (!nested_vmx_check_permission(vcpu))
5755 return 1;
5756
5757 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5758 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5759 return 1;
5760
5761 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5762 sizeof(vmptr), &e)) {
5763 kvm_inject_page_fault(vcpu, &e);
5764 return 1;
5765 }
5766
5767 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5768 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5769 skip_emulated_instruction(vcpu);
5770 return 1;
5771 }
5772
5773 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5774 nested_release_vmcs12(vmx);
27d6c865
NHE		 5775 vmx->nested.current_vmptr = -1ull;
5776 vmx->nested.current_vmcs12 = NULL;
5777 }
5778
5779 page = nested_get_page(vcpu, vmptr);
5780 if (page == NULL) {
5781 /*
5782 * For accurate processor emulation, VMCLEAR beyond available
5783 * physical memory should do nothing at all. However, it is
5784 * possible that a nested vmx bug, not a guest hypervisor bug,
5785 * resulted in this case, so let's shut down before doing any
5786 * more damage:
5787 */
5788 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5789 return 1;
5790 }
5791 vmcs12 = kmap(page);
5792 vmcs12->launch_state = 0;
5793 kunmap(page);
5794 nested_release_page(page);
5795
5796 nested_free_vmcs02(vmx, vmptr);
5797
5798 skip_emulated_instruction(vcpu);
5799 nested_vmx_succeed(vcpu);
5800 return 1;
5801}
5802
cd232ad0
NHE		 5803static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5804
5805/* Emulate the VMLAUNCH instruction */
5806static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5807{
5808 return nested_vmx_run(vcpu, true);
5809}
5810
5811/* Emulate the VMRESUME instruction */
5812static int handle_vmresume(struct kvm_vcpu *vcpu)
5813{
5814
5815 return nested_vmx_run(vcpu, false);
5816}
5817
49f705c5
NHE		 5818enum vmcs_field_type {
5819 VMCS_FIELD_TYPE_U16 = 0,
5820 VMCS_FIELD_TYPE_U64 = 1,
5821 VMCS_FIELD_TYPE_U32 = 2,
5822 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5823};
5824
5825static inline int vmcs_field_type(unsigned long field)
5826{
5827 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5828 return VMCS_FIELD_TYPE_U32;
5829 return (field >> 13) & 0x3 ;
5830}
5831
5832static inline int vmcs_field_readonly(unsigned long field)
5833{
5834 return (((field >> 10) & 0x3) == 1);
5835}
5836
5837/*
5838 * Read a vmcs12 field. Since these can have varying lengths and we return
5839 * one type, we chose the biggest type (u64) and zero-extend the return value
5840 * to that size. Note that the caller, handle_vmread, might need to use only
5841 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5842 * 64-bit fields are to be returned).
5843 */
5844static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5845 unsigned long field, u64 *ret)
5846{
5847 short offset = vmcs_field_to_offset(field);
5848 char *p;
5849
5850 if (offset < 0)
5851 return 0;
5852
5853 p = ((char *)(get_vmcs12(vcpu))) + offset;
5854
5855 switch (vmcs_field_type(field)) {
5856 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5857 *ret = *((natural_width *)p);
5858 return 1;
5859 case VMCS_FIELD_TYPE_U16:
5860 *ret = *((u16 *)p);
5861 return 1;
5862 case VMCS_FIELD_TYPE_U32:
5863 *ret = *((u32 *)p);
5864 return 1;
5865 case VMCS_FIELD_TYPE_U64:
5866 *ret = *((u64 *)p);
5867 return 1;
5868 default:
5869 return 0; /* can never happen. */
5870 }
5871}
5872
20b97fea
AG		 5873
5874static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5875 unsigned long field, u64 field_value){
5876 short offset = vmcs_field_to_offset(field);
5877 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5878 if (offset < 0)
5879 return false;
5880
5881 switch (vmcs_field_type(field)) {
5882 case VMCS_FIELD_TYPE_U16:
5883 *(u16 *)p = field_value;
5884 return true;
5885 case VMCS_FIELD_TYPE_U32:
5886 *(u32 *)p = field_value;
5887 return true;
5888 case VMCS_FIELD_TYPE_U64:
5889 *(u64 *)p = field_value;
5890 return true;
5891 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5892 *(natural_width *)p = field_value;
5893 return true;
5894 default:
5895 return false; /* can never happen. */
5896 }
5897
5898}
5899
16f5b903
AG		 5900static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5901{
5902 int i;
5903 unsigned long field;
5904 u64 field_value;
5905 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5906 unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5907 int num_fields = max_shadow_read_write_fields;
5908
5909 vmcs_load(shadow_vmcs);
5910
5911 for (i = 0; i < num_fields; i++) {
5912 field = fields[i];
5913 switch (vmcs_field_type(field)) {
5914 case VMCS_FIELD_TYPE_U16:
5915 field_value = vmcs_read16(field);
5916 break;
5917 case VMCS_FIELD_TYPE_U32:
5918 field_value = vmcs_read32(field);
5919 break;
5920 case VMCS_FIELD_TYPE_U64:
5921 field_value = vmcs_read64(field);
5922 break;
5923 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5924 field_value = vmcs_readl(field);
5925 break;
5926 }
5927 vmcs12_write_any(&vmx->vcpu, field, field_value);
5928 }
5929
5930 vmcs_clear(shadow_vmcs);
5931 vmcs_load(vmx->loaded_vmcs->vmcs);
5932}
5933
c3114420
AG		 5934static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
5935{
5936 unsigned long *fields[] = {
5937 (unsigned long *)shadow_read_write_fields,
5938 (unsigned long *)shadow_read_only_fields
5939 };
5940 int num_lists = ARRAY_SIZE(fields);
5941 int max_fields[] = {
5942 max_shadow_read_write_fields,
5943 max_shadow_read_only_fields
5944 };
5945 int i, q;
5946 unsigned long field;
5947 u64 field_value = 0;
5948 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5949
5950 vmcs_load(shadow_vmcs);
5951
5952 for (q = 0; q < num_lists; q++) {
5953 for (i = 0; i < max_fields[q]; i++) {
5954 field = fields[q][i];
5955 vmcs12_read_any(&vmx->vcpu, field, &field_value);
5956
5957 switch (vmcs_field_type(field)) {
5958 case VMCS_FIELD_TYPE_U16:
5959 vmcs_write16(field, (u16)field_value);
5960 break;
5961 case VMCS_FIELD_TYPE_U32:
5962 vmcs_write32(field, (u32)field_value);
5963 break;
5964 case VMCS_FIELD_TYPE_U64:
5965 vmcs_write64(field, (u64)field_value);
5966 break;
5967 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5968 vmcs_writel(field, (long)field_value);
5969 break;
5970 }
5971 }
5972 }
5973
5974 vmcs_clear(shadow_vmcs);
5975 vmcs_load(vmx->loaded_vmcs->vmcs);
5976}
5977
49f705c5
NHE		 5978/*
5979 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5980 * used before) all generate the same failure when it is missing.
5981 */
5982static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5983{
5984 struct vcpu_vmx *vmx = to_vmx(vcpu);
5985 if (vmx->nested.current_vmptr == -1ull) {
5986 nested_vmx_failInvalid(vcpu);
5987 skip_emulated_instruction(vcpu);
5988 return 0;
5989 }
5990 return 1;
5991}
5992
5993static int handle_vmread(struct kvm_vcpu *vcpu)
5994{
5995 unsigned long field;
5996 u64 field_value;
5997 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5998 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5999 gva_t gva = 0;
6000
6001 if (!nested_vmx_check_permission(vcpu) ||
6002 !nested_vmx_check_vmcs12(vcpu))
6003 return 1;
6004
6005 /* Decode instruction info and find the field to read */
6006 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6007 /* Read the field, zero-extended to a u64 field_value */
6008 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6009 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6010 skip_emulated_instruction(vcpu);
6011 return 1;
6012 }
6013 /*
6014 * Now copy part of this value to register or memory, as requested.
6015 * Note that the number of bits actually copied is 32 or 64 depending
6016 * on the guest's mode (32 or 64 bit), not on the given field's length.
6017 */
6018 if (vmx_instruction_info & (1u << 10)) {
6019 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6020 field_value);
6021 } else {
6022 if (get_vmx_mem_address(vcpu, exit_qualification,
6023 vmx_instruction_info, &gva))
6024 return 1;
6025 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6026 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6027 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6028 }
6029
6030 nested_vmx_succeed(vcpu);
6031 skip_emulated_instruction(vcpu);
6032 return 1;
6033}
6034
6035
6036static int handle_vmwrite(struct kvm_vcpu *vcpu)
6037{
6038 unsigned long field;
6039 gva_t gva;
6040 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6041 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6042 /* The value to write might be 32 or 64 bits, depending on L1's long
6043 * mode, and eventually we need to write that into a field of several
6044 * possible lengths. The code below first zero-extends the value to 64
6045 * bit (field_value), and then copies only the approriate number of
6046 * bits into the vmcs12 field.
6047 */
6048 u64 field_value = 0;
6049 struct x86_exception e;
6050
6051 if (!nested_vmx_check_permission(vcpu) ||
6052 !nested_vmx_check_vmcs12(vcpu))
6053 return 1;
6054
6055 if (vmx_instruction_info & (1u << 10))
6056 field_value = kvm_register_read(vcpu,
6057 (((vmx_instruction_info) >> 3) & 0xf));
6058 else {
6059 if (get_vmx_mem_address(vcpu, exit_qualification,
6060 vmx_instruction_info, &gva))
6061 return 1;
6062 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6063 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6064 kvm_inject_page_fault(vcpu, &e);
6065 return 1;
6066 }
6067 }
6068
6069
6070 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6071 if (vmcs_field_readonly(field)) {
6072 nested_vmx_failValid(vcpu,
6073 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6074 skip_emulated_instruction(vcpu);
6075 return 1;
6076 }
6077
20b97fea 6078 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6079 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6080 skip_emulated_instruction(vcpu);
6081 return 1;
6082 }
6083
6084 nested_vmx_succeed(vcpu);
6085 skip_emulated_instruction(vcpu);
6086 return 1;
6087}
6088
63846663
NHE		 6089/* Emulate the VMPTRLD instruction */
6090static int handle_vmptrld(struct kvm_vcpu *vcpu)
6091{
6092 struct vcpu_vmx *vmx = to_vmx(vcpu);
6093 gva_t gva;
6094 gpa_t vmptr;
6095 struct x86_exception e;
6096
6097 if (!nested_vmx_check_permission(vcpu))
6098 return 1;
6099
6100 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6101 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6102 return 1;
6103
6104 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6105 sizeof(vmptr), &e)) {
6106 kvm_inject_page_fault(vcpu, &e);
6107 return 1;
6108 }
6109
6110 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6111 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6112 skip_emulated_instruction(vcpu);
6113 return 1;
6114 }
6115
6116 if (vmx->nested.current_vmptr != vmptr) {
6117 struct vmcs12 *new_vmcs12;
6118 struct page *page;
6119 page = nested_get_page(vcpu, vmptr);
6120 if (page == NULL) {
6121 nested_vmx_failInvalid(vcpu);
6122 skip_emulated_instruction(vcpu);
6123 return 1;
6124 }
6125 new_vmcs12 = kmap(page);
6126 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6127 kunmap(page);
6128 nested_release_page_clean(page);
6129 nested_vmx_failValid(vcpu,
6130 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6131 skip_emulated_instruction(vcpu);
6132 return 1;
6133 }
e7953d7f
AG		 6134 if (vmx->nested.current_vmptr != -1ull)
6135 nested_release_vmcs12(vmx);
63846663
NHE		 6136
6137 vmx->nested.current_vmptr = vmptr;
6138 vmx->nested.current_vmcs12 = new_vmcs12;
6139 vmx->nested.current_vmcs12_page = page;
6140 }
6141
6142 nested_vmx_succeed(vcpu);
6143 skip_emulated_instruction(vcpu);
6144 return 1;
6145}
6146
6a4d7550
NHE		 6147/* Emulate the VMPTRST instruction */
6148static int handle_vmptrst(struct kvm_vcpu *vcpu)
6149{
6150 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6151 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6152 gva_t vmcs_gva;
6153 struct x86_exception e;
6154
6155 if (!nested_vmx_check_permission(vcpu))
6156 return 1;
6157
6158 if (get_vmx_mem_address(vcpu, exit_qualification,
6159 vmx_instruction_info, &vmcs_gva))
6160 return 1;
6161 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6162 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6163 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6164 sizeof(u64), &e)) {
6165 kvm_inject_page_fault(vcpu, &e);
6166 return 1;
6167 }
6168 nested_vmx_succeed(vcpu);
6169 skip_emulated_instruction(vcpu);
6170 return 1;
6171}
6172
6aa8b732
AK		 6173/*
6174 * The exit handlers return 1 if the exit was handled fully and guest execution
6175 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6176 * to be done to userspace and return 0.
6177 */
772e0318 6178static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6179 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6180 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6181 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6182 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6183 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6184 [EXIT_REASON_CR_ACCESS] = handle_cr,
6185 [EXIT_REASON_DR_ACCESS] = handle_dr,
6186 [EXIT_REASON_CPUID] = handle_cpuid,
6187 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6188 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6189 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6190 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6191 [EXIT_REASON_INVD] = handle_invd,
a7052897 6192 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6193 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6194 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6195 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6196 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6197 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6198 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6199 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6200 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6201 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6202 [EXIT_REASON_VMOFF] = handle_vmoff,
6203 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6204 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6205 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6206 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6207 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6208 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6209 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6210 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6211 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6212 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6213 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6214 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6215 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6216 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 6217};
6218
6219static const int kvm_vmx_max_exit_handlers =
50a3485c 6220 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6221
908a7bdd
JK		 6222static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6223 struct vmcs12 *vmcs12)
6224{
6225 unsigned long exit_qualification;
6226 gpa_t bitmap, last_bitmap;
6227 unsigned int port;
6228 int size;
6229 u8 b;
6230
6231 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6232 return 1;
6233
6234 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6235 return 0;
6236
6237 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6238
6239 port = exit_qualification >> 16;
6240 size = (exit_qualification & 7) + 1;
6241
6242 last_bitmap = (gpa_t)-1;
6243 b = -1;
6244
6245 while (size > 0) {
6246 if (port < 0x8000)
6247 bitmap = vmcs12->io_bitmap_a;
6248 else if (port < 0x10000)
6249 bitmap = vmcs12->io_bitmap_b;
6250 else
6251 return 1;
6252 bitmap += (port & 0x7fff) / 8;
6253
6254 if (last_bitmap != bitmap)
6255 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6256 return 1;
6257 if (b & (1 << (port & 7)))
6258 return 1;
6259
6260 port++;
6261 size--;
6262 last_bitmap = bitmap;
6263 }
6264
6265 return 0;
6266}
6267
644d711a
NHE		 6268/*
6269 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6270 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6271 * disinterest in the current event (read or write a specific MSR) by using an
6272 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6273 */
6274static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6275 struct vmcs12 *vmcs12, u32 exit_reason)
6276{
6277 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6278 gpa_t bitmap;
6279
cbd29cb6 6280 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6281 return 1;
6282
6283 /*
6284 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6285 * for the four combinations of read/write and low/high MSR numbers.
6286 * First we need to figure out which of the four to use:
6287 */
6288 bitmap = vmcs12->msr_bitmap;
6289 if (exit_reason == EXIT_REASON_MSR_WRITE)
6290 bitmap += 2048;
6291 if (msr_index >= 0xc0000000) {
6292 msr_index -= 0xc0000000;
6293 bitmap += 1024;
6294 }
6295
6296 /* Then read the msr_index'th bit from this bitmap: */
6297 if (msr_index < 1024*8) {
6298 unsigned char b;
bd31a7f5
JK		 6299 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6300 return 1;
644d711a
NHE		 6301 return 1 & (b >> (msr_index & 7));
6302 } else
6303 return 1; /* let L1 handle the wrong parameter */
6304}
6305
6306/*
6307 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6308 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6309 * intercept (via guest_host_mask etc.) the current event.
6310 */
6311static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6312 struct vmcs12 *vmcs12)
6313{
6314 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6315 int cr = exit_qualification & 15;
6316 int reg = (exit_qualification >> 8) & 15;
6317 unsigned long val = kvm_register_read(vcpu, reg);
6318
6319 switch ((exit_qualification >> 4) & 3) {
6320 case 0: /* mov to cr */
6321 switch (cr) {
6322 case 0:
6323 if (vmcs12->cr0_guest_host_mask &
6324 (val ^ vmcs12->cr0_read_shadow))
6325 return 1;
6326 break;
6327 case 3:
6328 if ((vmcs12->cr3_target_count >= 1 &&
6329 vmcs12->cr3_target_value0 == val) ||
6330 (vmcs12->cr3_target_count >= 2 &&
6331 vmcs12->cr3_target_value1 == val) ||
6332 (vmcs12->cr3_target_count >= 3 &&
6333 vmcs12->cr3_target_value2 == val) ||
6334 (vmcs12->cr3_target_count >= 4 &&
6335 vmcs12->cr3_target_value3 == val))
6336 return 0;
6337 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6338 return 1;
6339 break;
6340 case 4:
6341 if (vmcs12->cr4_guest_host_mask &
6342 (vmcs12->cr4_read_shadow ^ val))
6343 return 1;
6344 break;
6345 case 8:
6346 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6347 return 1;
6348 break;
6349 }
6350 break;
6351 case 2: /* clts */
6352 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6353 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6354 return 1;
6355 break;
6356 case 1: /* mov from cr */
6357 switch (cr) {
6358 case 3:
6359 if (vmcs12->cpu_based_vm_exec_control &
6360 CPU_BASED_CR3_STORE_EXITING)
6361 return 1;
6362 break;
6363 case 8:
6364 if (vmcs12->cpu_based_vm_exec_control &
6365 CPU_BASED_CR8_STORE_EXITING)
6366 return 1;
6367 break;
6368 }
6369 break;
6370 case 3: /* lmsw */
6371 /*
6372 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6373 * cr0. Other attempted changes are ignored, with no exit.
6374 */
6375 if (vmcs12->cr0_guest_host_mask & 0xe &
6376 (val ^ vmcs12->cr0_read_shadow))
6377 return 1;
6378 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6379 !(vmcs12->cr0_read_shadow & 0x1) &&
6380 (val & 0x1))
6381 return 1;
6382 break;
6383 }
6384 return 0;
6385}
6386
6387/*
6388 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6389 * should handle it ourselves in L0 (and then continue L2). Only call this
6390 * when in is_guest_mode (L2).
6391 */
6392static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6393{
644d711a
NHE		 6394 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6395 struct vcpu_vmx *vmx = to_vmx(vcpu);
6396 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6397 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6398
6399 if (vmx->nested.nested_run_pending)
6400 return 0;
6401
6402 if (unlikely(vmx->fail)) {
bd80158a
JK		 6403 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6404 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6405 return 1;
6406 }
6407
6408 switch (exit_reason) {
6409 case EXIT_REASON_EXCEPTION_NMI:
6410 if (!is_exception(intr_info))
6411 return 0;
6412 else if (is_page_fault(intr_info))
6413 return enable_ept;
6414 return vmcs12->exception_bitmap &
6415 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6416 case EXIT_REASON_EXTERNAL_INTERRUPT:
6417 return 0;
6418 case EXIT_REASON_TRIPLE_FAULT:
6419 return 1;
6420 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6421 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6422 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6423 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6424 case EXIT_REASON_TASK_SWITCH:
6425 return 1;
6426 case EXIT_REASON_CPUID:
6427 return 1;
6428 case EXIT_REASON_HLT:
6429 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6430 case EXIT_REASON_INVD:
6431 return 1;
6432 case EXIT_REASON_INVLPG:
6433 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6434 case EXIT_REASON_RDPMC:
6435 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6436 case EXIT_REASON_RDTSC:
6437 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6438 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6439 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6440 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6441 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6442 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6443 /*
6444 * VMX instructions trap unconditionally. This allows L1 to
6445 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6446 */
6447 return 1;
6448 case EXIT_REASON_CR_ACCESS:
6449 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6450 case EXIT_REASON_DR_ACCESS:
6451 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6452 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6453 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6454 case EXIT_REASON_MSR_READ:
6455 case EXIT_REASON_MSR_WRITE:
6456 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6457 case EXIT_REASON_INVALID_STATE:
6458 return 1;
6459 case EXIT_REASON_MWAIT_INSTRUCTION:
6460 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6461 case EXIT_REASON_MONITOR_INSTRUCTION:
6462 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6463 case EXIT_REASON_PAUSE_INSTRUCTION:
6464 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6465 nested_cpu_has2(vmcs12,
6466 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6467 case EXIT_REASON_MCE_DURING_VMENTRY:
6468 return 0;
6469 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6470 return 1;
6471 case EXIT_REASON_APIC_ACCESS:
6472 return nested_cpu_has2(vmcs12,
6473 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6474 case EXIT_REASON_EPT_VIOLATION:
6475 case EXIT_REASON_EPT_MISCONFIG:
6476 return 0;
0238ea91
JK		 6477 case EXIT_REASON_PREEMPTION_TIMER:
6478 return vmcs12->pin_based_vm_exec_control &
6479 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6480 case EXIT_REASON_WBINVD:
6481 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6482 case EXIT_REASON_XSETBV:
6483 return 1;
6484 default:
6485 return 1;
6486 }
6487}
6488
586f9607
AK		 6489static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6490{
6491 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6492 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6493}
6494
6aa8b732
AK		 6495/*
6496 * The guest has exited. See if we can fix it or if we need userspace
6497 * assistance.
6498 */
851ba692 6499static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6500{
29bd8a78 6501 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6502 u32 exit_reason = vmx->exit_reason;
1155f76a 6503 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6504
80ced186 6505 /* If guest state is invalid, start emulating */
14168786 6506 if (vmx->emulation_required)
80ced186 6507 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6508
b6f1250e
NHE		 6509 /*
6510 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6511 * we did not inject a still-pending event to L1 now because of
6512 * nested_run_pending, we need to re-enable this bit.
6513 */
6514 if (vmx->nested.nested_run_pending)
6515 kvm_make_request(KVM_REQ_EVENT, vcpu);
6516
509c75ea
NHE		 6517 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6518 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6519 vmx->nested.nested_run_pending = 1;
6520 else
6521 vmx->nested.nested_run_pending = 0;
6522
6523 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6524 nested_vmx_vmexit(vcpu);
6525 return 1;
6526 }
6527
5120702e
MG		 6528 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6529 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6530 vcpu->run->fail_entry.hardware_entry_failure_reason
6531 = exit_reason;
6532 return 0;
6533 }
6534
29bd8a78 6535 if (unlikely(vmx->fail)) {
851ba692
AK		 6536 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6537 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6538 = vmcs_read32(VM_INSTRUCTION_ERROR);
6539 return 0;
6540 }
6aa8b732 6541
b9bf6882
XG		 6542 /*
6543 * Note:
6544 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6545 * delivery event since it indicates guest is accessing MMIO.
6546 * The vm-exit can be triggered again after return to guest that
6547 * will cause infinite loop.
6548 */
d77c26fc 6549 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6550 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6551 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6552 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6553 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6554 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6555 vcpu->run->internal.ndata = 2;
6556 vcpu->run->internal.data[0] = vectoring_info;
6557 vcpu->run->internal.data[1] = exit_reason;
6558 return 0;
6559 }
3b86cd99 6560
644d711a
NHE		 6561 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6562 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6563 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6564 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6565 vmx->soft_vnmi_blocked = 0;
3b86cd99 6566 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6567 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6568 /*
6569 * This CPU don't support us in finding the end of an
6570 * NMI-blocked window if the guest runs with IRQs
6571 * disabled. So we pull the trigger after 1 s of
6572 * futile waiting, but inform the user about this.
6573 */
6574 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6575 "state on VCPU %d after 1 s timeout\n",
6576 __func__, vcpu->vcpu_id);
6577 vmx->soft_vnmi_blocked = 0;
3b86cd99 6578 }
3b86cd99
JK		 6579 }
6580
6aa8b732
AK		 6581 if (exit_reason < kvm_vmx_max_exit_handlers
6582 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6583 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6584 else {
851ba692
AK		 6585 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6586 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6587 }
6588 return 0;
6589}
6590
95ba8273 6591static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6592{
95ba8273 6593 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6594 vmcs_write32(TPR_THRESHOLD, 0);
6595 return;
6596 }
6597
95ba8273 6598 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6599}
6600
8d14695f
YZ		 6601static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6602{
6603 u32 sec_exec_control;
6604
6605 /*
6606 * There is not point to enable virtualize x2apic without enable
6607 * apicv
6608 */
c7c9c56c
YZ		 6609 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6610 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6611 return;
6612
6613 if (!vm_need_tpr_shadow(vcpu->kvm))
6614 return;
6615
6616 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6617
6618 if (set) {
6619 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6620 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6621 } else {
6622 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6623 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6624 }
6625 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6626
6627 vmx_set_msr_bitmap(vcpu);
6628}
6629
c7c9c56c
YZ		 6630static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6631{
6632 u16 status;
6633 u8 old;
6634
6635 if (!vmx_vm_has_apicv(kvm))
6636 return;
6637
6638 if (isr == -1)
6639 isr = 0;
6640
6641 status = vmcs_read16(GUEST_INTR_STATUS);
6642 old = status >> 8;
6643 if (isr != old) {
6644 status &= 0xff;
6645 status |= isr << 8;
6646 vmcs_write16(GUEST_INTR_STATUS, status);
6647 }
6648}
6649
6650static void vmx_set_rvi(int vector)
6651{
6652 u16 status;
6653 u8 old;
6654
6655 status = vmcs_read16(GUEST_INTR_STATUS);
6656 old = (u8)status & 0xff;
6657 if ((u8)vector != old) {
6658 status &= ~0xff;
6659 status |= (u8)vector;
6660 vmcs_write16(GUEST_INTR_STATUS, status);
6661 }
6662}
6663
6664static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6665{
6666 if (max_irr == -1)
6667 return;
6668
6669 vmx_set_rvi(max_irr);
6670}
6671
6672static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6673{
3d81bc7e
YZ		 6674 if (!vmx_vm_has_apicv(vcpu->kvm))
6675 return;
6676
c7c9c56c
YZ		 6677 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6678 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6679 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6680 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6681}
6682
51aa01d1 6683static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6684{
00eba012
AK		 6685 u32 exit_intr_info;
6686
6687 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6688 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6689 return;
6690
c5ca8e57 6691 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6692 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6693
6694 /* Handle machine checks before interrupts are enabled */
00eba012 6695 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6696 kvm_machine_check();
6697
20f65983 6698 /* We need to handle NMIs before interrupts are enabled */
00eba012 6699 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6700 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6701 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6702 asm("int $2");
ff9d07a0
ZY		 6703 kvm_after_handle_nmi(&vmx->vcpu);
6704 }
51aa01d1 6705}
20f65983 6706
a547c6db
YZ		 6707static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6708{
6709 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6710
6711 /*
6712 * If external interrupt exists, IF bit is set in rflags/eflags on the
6713 * interrupt stack frame, and interrupt will be enabled on a return
6714 * from interrupt handler.
6715 */
6716 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6717 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6718 unsigned int vector;
6719 unsigned long entry;
6720 gate_desc *desc;
6721 struct vcpu_vmx *vmx = to_vmx(vcpu);
6722#ifdef CONFIG_X86_64
6723 unsigned long tmp;
6724#endif
6725
6726 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6727 desc = (gate_desc *)vmx->host_idt_base + vector;
6728 entry = gate_offset(*desc);
6729 asm volatile(
6730#ifdef CONFIG_X86_64
6731 "mov %%" _ASM_SP ", %[sp]\n\t"
6732 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6733 "push $%c[ss]\n\t"
6734 "push %[sp]\n\t"
6735#endif
6736 "pushf\n\t"
6737 "orl $0x200, (%%" _ASM_SP ")\n\t"
6738 __ASM_SIZE(push) " $%c[cs]\n\t"
6739 "call *%[entry]\n\t"
6740 :
6741#ifdef CONFIG_X86_64
6742 [sp]"=&r"(tmp)
6743#endif
6744 :
6745 [entry]"r"(entry),
6746 [ss]"i"(__KERNEL_DS),
6747 [cs]"i"(__KERNEL_CS)
6748 );
6749 } else
6750 local_irq_enable();
6751}
6752
51aa01d1
AK		 6753static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6754{
c5ca8e57 6755 u32 exit_intr_info;
51aa01d1
AK		 6756 bool unblock_nmi;
6757 u8 vector;
6758 bool idtv_info_valid;
6759
6760 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6761
cf393f75 6762 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6763 if (vmx->nmi_known_unmasked)
6764 return;
c5ca8e57
AK		 6765 /*
6766 * Can't use vmx->exit_intr_info since we're not sure what
6767 * the exit reason is.
6768 */
6769 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6770 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6771 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6772 /*
7b4a25cb 6773 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6774 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6775 * a guest IRET fault.
7b4a25cb
GN		 6776 * SDM 3: 23.2.2 (September 2008)
6777 * Bit 12 is undefined in any of the following cases:
6778 * If the VM exit sets the valid bit in the IDT-vectoring
6779 * information field.
6780 * If the VM exit is due to a double fault.
cf393f75 6781 */
7b4a25cb
GN		 6782 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6783 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6784 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6785 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6786 else
6787 vmx->nmi_known_unmasked =
6788 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6789 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6790 } else if (unlikely(vmx->soft_vnmi_blocked))
6791 vmx->vnmi_blocked_time +=
6792 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6793}
6794
3ab66e8a 6795static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6796 u32 idt_vectoring_info,
6797 int instr_len_field,
6798 int error_code_field)
51aa01d1 6799{
51aa01d1
AK		 6800 u8 vector;
6801 int type;
6802 bool idtv_info_valid;
6803
6804 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6805
3ab66e8a
JK		 6806 vcpu->arch.nmi_injected = false;
6807 kvm_clear_exception_queue(vcpu);
6808 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6809
6810 if (!idtv_info_valid)
6811 return;
6812
3ab66e8a 6813 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6814
668f612f
AK		 6815 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6816 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6817
64a7ec06 6818 switch (type) {
37b96e98 6819 case INTR_TYPE_NMI_INTR:
3ab66e8a 6820 vcpu->arch.nmi_injected = true;
668f612f 6821 /*
7b4a25cb 6822 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6823 * Clear bit "block by NMI" before VM entry if a NMI
6824 * delivery faulted.
668f612f 6825 */
3ab66e8a 6826 vmx_set_nmi_mask(vcpu, false);
37b96e98 6827 break;
37b96e98 6828 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6829 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6830 /* fall through */
6831 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6832 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6833 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6834 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6835 } else
3ab66e8a 6836 kvm_queue_exception(vcpu, vector);
37b96e98 6837 break;
66fd3f7f 6838 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6839 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6840 /* fall through */
37b96e98 6841 case INTR_TYPE_EXT_INTR:
3ab66e8a 6842 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6843 break;
6844 default:
6845 break;
f7d9238f 6846 }
cf393f75
AK		 6847}
6848
83422e17
AK		 6849static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6850{
3ab66e8a 6851 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6852 VM_EXIT_INSTRUCTION_LEN,
6853 IDT_VECTORING_ERROR_CODE);
6854}
6855
b463a6f7
AK		 6856static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6857{
3ab66e8a 6858 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6859 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6860 VM_ENTRY_INSTRUCTION_LEN,
6861 VM_ENTRY_EXCEPTION_ERROR_CODE);
6862
6863 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6864}
6865
d7cd9796
GN		 6866static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6867{
6868 int i, nr_msrs;
6869 struct perf_guest_switch_msr *msrs;
6870
6871 msrs = perf_guest_get_msrs(&nr_msrs);
6872
6873 if (!msrs)
6874 return;
6875
6876 for (i = 0; i < nr_msrs; i++)
6877 if (msrs[i].host == msrs[i].guest)
6878 clear_atomic_switch_msr(vmx, msrs[i].msr);
6879 else
6880 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6881 msrs[i].host);
6882}
6883
a3b5ba49 6884static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6885{
a2fa3e9f 6886 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6887 unsigned long debugctlmsr;
104f226b
AK		 6888
6889 /* Record the guest's net vcpu time for enforced NMI injections. */
6890 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6891 vmx->entry_time = ktime_get();
6892
6893 /* Don't enter VMX if guest state is invalid, let the exit handler
6894 start emulation until we arrive back to a valid state */
14168786 6895 if (vmx->emulation_required)
104f226b
AK		 6896 return;
6897
6898 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6899 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6900 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6901 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6902
6903 /* When single-stepping over STI and MOV SS, we must clear the
6904 * corresponding interruptibility bits in the guest state. Otherwise
6905 * vmentry fails as it then expects bit 14 (BS) in pending debug
6906 * exceptions being set, but that's not correct for the guest debugging
6907 * case. */
6908 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6909 vmx_set_interrupt_shadow(vcpu, 0);
6910
d7cd9796 6911 atomic_switch_perf_msrs(vmx);
2a7921b7 6912 debugctlmsr = get_debugctlmsr();
d7cd9796 6913
d462b819 6914 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6915 asm(
6aa8b732 6916 /* Store host registers */
b188c81f
AK		 6917 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6918 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6919 "push %%" _ASM_CX " \n\t"
6920 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6921 "je 1f \n\t"
b188c81f 6922 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6923 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6924 "1: \n\t"
d3edefc0 6925 /* Reload cr2 if changed */
b188c81f
AK		 6926 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6927 "mov %%cr2, %%" _ASM_DX " \n\t"
6928 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6929 "je 2f \n\t"
b188c81f 6930 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6931 "2: \n\t"
6aa8b732 6932 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6933 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6934 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6935 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6936 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6937 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6938 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6939 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6940 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6941#ifdef CONFIG_X86_64
e08aa78a
AK		 6942 "mov %c[r8](%0), %%r8 \n\t"
6943 "mov %c[r9](%0), %%r9 \n\t"
6944 "mov %c[r10](%0), %%r10 \n\t"
6945 "mov %c[r11](%0), %%r11 \n\t"
6946 "mov %c[r12](%0), %%r12 \n\t"
6947 "mov %c[r13](%0), %%r13 \n\t"
6948 "mov %c[r14](%0), %%r14 \n\t"
6949 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6950#endif
b188c81f 6951 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6952
6aa8b732 6953 /* Enter guest mode */
83287ea4 6954 "jne 1f \n\t"
4ecac3fd 6955 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6956 "jmp 2f \n\t"
6957 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6958 "2: "
6aa8b732 6959 /* Save guest registers, load host registers, keep flags */
b188c81f 6960 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6961 "pop %0 \n\t"
b188c81f
AK		 6962 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6963 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6964 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6965 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6966 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6967 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6968 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6969#ifdef CONFIG_X86_64
e08aa78a
AK		 6970 "mov %%r8, %c[r8](%0) \n\t"
6971 "mov %%r9, %c[r9](%0) \n\t"
6972 "mov %%r10, %c[r10](%0) \n\t"
6973 "mov %%r11, %c[r11](%0) \n\t"
6974 "mov %%r12, %c[r12](%0) \n\t"
6975 "mov %%r13, %c[r13](%0) \n\t"
6976 "mov %%r14, %c[r14](%0) \n\t"
6977 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6978#endif
b188c81f
AK		 6979 "mov %%cr2, %%" _ASM_AX " \n\t"
6980 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6981
b188c81f 6982 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6983 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6984 ".pushsection .rodata \n\t"
6985 ".global vmx_return \n\t"
6986 "vmx_return: " _ASM_PTR " 2b \n\t"
6987 ".popsection"
e08aa78a 6988 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6989 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6990 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6991 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6992 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6993 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6994 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6995 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6996 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6997 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6998 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6999#ifdef CONFIG_X86_64
ad312c7c
ZX		 7000 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7001 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7002 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7003 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7004 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7005 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7006 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7007 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7008#endif
40712fae
AK		 7009 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7010 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7011 : "cc", "memory"
7012#ifdef CONFIG_X86_64
b188c81f 7013 , "rax", "rbx", "rdi", "rsi"
c2036300 7014 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7015#else
7016 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7017#endif
7018 );
6aa8b732 7019
2a7921b7
GN		 7020 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7021 if (debugctlmsr)
7022 update_debugctlmsr(debugctlmsr);
7023
aa67f609
AK		 7024#ifndef CONFIG_X86_64
7025 /*
7026 * The sysexit path does not restore ds/es, so we must set them to
7027 * a reasonable value ourselves.
7028 *
7029 * We can't defer this to vmx_load_host_state() since that function
7030 * may be executed in interrupt context, which saves and restore segments
7031 * around it, nullifying its effect.
7032 */
7033 loadsegment(ds, __USER_DS);
7034 loadsegment(es, __USER_DS);
7035#endif
7036
6de4f3ad 7037 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7038 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7039 | (1 << VCPU_EXREG_CPL)
aff48baa 7040 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7041 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7042 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7043 vcpu->arch.regs_dirty = 0;
7044
1155f76a
AK		 7045 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7046
d462b819 7047 vmx->loaded_vmcs->launched = 1;
1b6269db 7048
51aa01d1 7049 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7050 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7051
7052 vmx_complete_atomic_exit(vmx);
7053 vmx_recover_nmi_blocking(vmx);
cf393f75 7054 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7055}
7056
6aa8b732
AK		 7057static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7058{
fb3f0f51
RR		 7059 struct vcpu_vmx *vmx = to_vmx(vcpu);
7060
cdbecfc3 7061 free_vpid(vmx);
ec378aee 7062 free_nested(vmx);
d462b819 7063 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7064 kfree(vmx->guest_msrs);
7065 kvm_vcpu_uninit(vcpu);
a4770347 7066 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7067}
7068
fb3f0f51 7069static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7070{
fb3f0f51 7071 int err;
c16f862d 7072 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7073 int cpu;
6aa8b732 7074
a2fa3e9f 7075 if (!vmx)
fb3f0f51
RR		 7076 return ERR_PTR(-ENOMEM);
7077
2384d2b3
SY		 7078 allocate_vpid(vmx);
7079
fb3f0f51
RR		 7080 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7081 if (err)
7082 goto free_vcpu;
965b58a5 7083
a2fa3e9f 7084 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7085 err = -ENOMEM;
fb3f0f51 7086 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7087 goto uninit_vcpu;
7088 }
965b58a5 7089
d462b819
NHE		 7090 vmx->loaded_vmcs = &vmx->vmcs01;
7091 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7092 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7093 goto free_msrs;
d462b819
NHE		 7094 if (!vmm_exclusive)
7095 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7096 loaded_vmcs_init(vmx->loaded_vmcs);
7097 if (!vmm_exclusive)
7098 kvm_cpu_vmxoff();
a2fa3e9f 7099
15ad7146
AK		 7100 cpu = get_cpu();
7101 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7102 vmx->vcpu.cpu = cpu;
8b9cf98c 7103 err = vmx_vcpu_setup(vmx);
fb3f0f51 7104 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7105 put_cpu();
fb3f0f51
RR		 7106 if (err)
7107 goto free_vmcs;
a63cb560 7108 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7109 err = alloc_apic_access_page(kvm);
7110 if (err)
5e4a0b3c 7111 goto free_vmcs;
a63cb560 7112 }
fb3f0f51 7113
b927a3ce
SY		 7114 if (enable_ept) {
7115 if (!kvm->arch.ept_identity_map_addr)
7116 kvm->arch.ept_identity_map_addr =
7117 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7118 err = -ENOMEM;
b7ebfb05
SY		 7119 if (alloc_identity_pagetable(kvm) != 0)
7120 goto free_vmcs;
93ea5388
GN		 7121 if (!init_rmode_identity_map(kvm))
7122 goto free_vmcs;
b927a3ce 7123 }
b7ebfb05 7124
a9d30f33
NHE		 7125 vmx->nested.current_vmptr = -1ull;
7126 vmx->nested.current_vmcs12 = NULL;
7127
fb3f0f51
RR		 7128 return &vmx->vcpu;
7129
7130free_vmcs:
5f3fbc34 7131 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7132free_msrs:
fb3f0f51
RR		 7133 kfree(vmx->guest_msrs);
7134uninit_vcpu:
7135 kvm_vcpu_uninit(&vmx->vcpu);
7136free_vcpu:
cdbecfc3 7137 free_vpid(vmx);
a4770347 7138 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7139 return ERR_PTR(err);
6aa8b732
AK		 7140}
7141
002c7f7c
YS		 7142static void __init vmx_check_processor_compat(void *rtn)
7143{
7144 struct vmcs_config vmcs_conf;
7145
7146 *(int *)rtn = 0;
7147 if (setup_vmcs_config(&vmcs_conf) < 0)
7148 *(int *)rtn = -EIO;
7149 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7150 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7151 smp_processor_id());
7152 *(int *)rtn = -EIO;
7153 }
7154}
7155
67253af5
SY		 7156static int get_ept_level(void)
7157{
7158 return VMX_EPT_DEFAULT_GAW + 1;
7159}
7160
4b12f0de 7161static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7162{
4b12f0de
SY		 7163 u64 ret;
7164
522c68c4
SY		 7165 /* For VT-d and EPT combination
7166 * 1. MMIO: always map as UC
7167 * 2. EPT with VT-d:
7168 * a. VT-d without snooping control feature: can't guarantee the
7169 * result, try to trust guest.
7170 * b. VT-d with snooping control feature: snooping control feature of
7171 * VT-d engine can guarantee the cache correctness. Just set it
7172 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7173 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7174 * consistent with host MTRR
7175 */
4b12f0de
SY		 7176 if (is_mmio)
7177 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7178 else if (vcpu->kvm->arch.iommu_domain &&
7179 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7180 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7181 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7182 else
522c68c4 7183 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7184 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7185
7186 return ret;
64d4d521
SY		 7187}
7188
17cc3935 7189static int vmx_get_lpage_level(void)
344f414f 7190{
878403b7
SY		 7191 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7192 return PT_DIRECTORY_LEVEL;
7193 else
7194 /* For shadow and EPT supported 1GB page */
7195 return PT_PDPE_LEVEL;
344f414f
JR		 7196}
7197
0e851880
SY		 7198static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7199{
4e47c7a6
SY		 7200 struct kvm_cpuid_entry2 *best;
7201 struct vcpu_vmx *vmx = to_vmx(vcpu);
7202 u32 exec_control;
7203
7204 vmx->rdtscp_enabled = false;
7205 if (vmx_rdtscp_supported()) {
7206 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7207 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7208 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7209 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7210 vmx->rdtscp_enabled = true;
7211 else {
7212 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7213 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7214 exec_control);
7215 }
7216 }
7217 }
ad756a16 7218
ad756a16
MJ		 7219 /* Exposing INVPCID only when PCID is exposed */
7220 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7221 if (vmx_invpcid_supported() &&
4f977045 7222 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7223 guest_cpuid_has_pcid(vcpu)) {
29282fde 7224 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7225 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7226 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7227 exec_control);
7228 } else {
29282fde
TI		 7229 if (cpu_has_secondary_exec_ctrls()) {
7230 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7231 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7232 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7233 exec_control);
7234 }
ad756a16 7235 if (best)
4f977045 7236 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7237 }
0e851880
SY		 7238}
7239
d4330ef2
JR		 7240static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7241{
7b8050f5
NHE		 7242 if (func == 1 && nested)
7243 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7244}
7245
fe3ef05c
NHE		 7246/*
7247 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7248 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7249 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7250 * guest in a way that will both be appropriate to L1's requests, and our
7251 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7252 * function also has additional necessary side-effects, like setting various
7253 * vcpu->arch fields.
7254 */
7255static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7256{
7257 struct vcpu_vmx *vmx = to_vmx(vcpu);
7258 u32 exec_control;
7259
7260 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7261 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7262 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7263 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7264 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7265 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7266 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7267 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7268 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7269 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7270 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7271 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7272 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7273 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7274 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7275 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7276 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7277 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7278 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7279 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7280 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7281 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7282 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7283 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7284 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7285 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7286 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7287 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7288 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7289 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7290 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7291 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7292 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7293 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7294 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7295 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7296
7297 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7298 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7299 vmcs12->vm_entry_intr_info_field);
7300 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7301 vmcs12->vm_entry_exception_error_code);
7302 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7303 vmcs12->vm_entry_instruction_len);
7304 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7305 vmcs12->guest_interruptibility_info);
fe3ef05c 7306 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7307 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 7308 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7309 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7310 vmcs12->guest_pending_dbg_exceptions);
7311 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7312 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7313
7314 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7315
7316 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7317 (vmcs_config.pin_based_exec_ctrl |
7318 vmcs12->pin_based_vm_exec_control));
7319
0238ea91
JK		 7320 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7321 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7322 vmcs12->vmx_preemption_timer_value);
7323
fe3ef05c
NHE		 7324 /*
7325 * Whether page-faults are trapped is determined by a combination of
7326 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7327 * If enable_ept, L0 doesn't care about page faults and we should
7328 * set all of these to L1's desires. However, if !enable_ept, L0 does
7329 * care about (at least some) page faults, and because it is not easy
7330 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7331 * to exit on each and every L2 page fault. This is done by setting
7332 * MASK=MATCH=0 and (see below) EB.PF=1.
7333 * Note that below we don't need special code to set EB.PF beyond the
7334 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7335 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7336 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7337 *
7338 * A problem with this approach (when !enable_ept) is that L1 may be
7339 * injected with more page faults than it asked for. This could have
7340 * caused problems, but in practice existing hypervisors don't care.
7341 * To fix this, we will need to emulate the PFEC checking (on the L1
7342 * page tables), using walk_addr(), when injecting PFs to L1.
7343 */
7344 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7345 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7346 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7347 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7348
7349 if (cpu_has_secondary_exec_ctrls()) {
7350 u32 exec_control = vmx_secondary_exec_control(vmx);
7351 if (!vmx->rdtscp_enabled)
7352 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7353 /* Take the following fields only from vmcs12 */
7354 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7355 if (nested_cpu_has(vmcs12,
7356 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7357 exec_control |= vmcs12->secondary_vm_exec_control;
7358
7359 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7360 /*
7361 * Translate L1 physical address to host physical
7362 * address for vmcs02. Keep the page pinned, so this
7363 * physical address remains valid. We keep a reference
7364 * to it so we can release it later.
7365 */
7366 if (vmx->nested.apic_access_page) /* shouldn't happen */
7367 nested_release_page(vmx->nested.apic_access_page);
7368 vmx->nested.apic_access_page =
7369 nested_get_page(vcpu, vmcs12->apic_access_addr);
7370 /*
7371 * If translation failed, no matter: This feature asks
7372 * to exit when accessing the given address, and if it
7373 * can never be accessed, this feature won't do
7374 * anything anyway.
7375 */
7376 if (!vmx->nested.apic_access_page)
7377 exec_control &=
7378 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7379 else
7380 vmcs_write64(APIC_ACCESS_ADDR,
7381 page_to_phys(vmx->nested.apic_access_page));
7382 }
7383
7384 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7385 }
7386
7387
7388 /*
7389 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7390 * Some constant fields are set here by vmx_set_constant_host_state().
7391 * Other fields are different per CPU, and will be set later when
7392 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7393 */
a547c6db 7394 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7395
7396 /*
7397 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7398 * entry, but only if the current (host) sp changed from the value
7399 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7400 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7401 * here we just force the write to happen on entry.
7402 */
7403 vmx->host_rsp = 0;
7404
7405 exec_control = vmx_exec_control(vmx); /* L0's desires */
7406 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7407 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7408 exec_control &= ~CPU_BASED_TPR_SHADOW;
7409 exec_control |= vmcs12->cpu_based_vm_exec_control;
7410 /*
7411 * Merging of IO and MSR bitmaps not currently supported.
7412 * Rather, exit every time.
7413 */
7414 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7415 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7416 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7417
7418 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7419
7420 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7421 * bitwise-or of what L1 wants to trap for L2, and what we want to
7422 * trap. Note that CR0.TS also needs updating - we do this later.
7423 */
7424 update_exception_bitmap(vcpu);
7425 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7426 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7427
7428 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7429 vmcs_write32(VM_EXIT_CONTROLS,
7430 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7431 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7432 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7433
7434 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7435 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7436 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7437 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7438
7439
7440 set_cr4_guest_host_mask(vmx);
7441
27fc51b2
NHE		 7442 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7443 vmcs_write64(TSC_OFFSET,
7444 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7445 else
7446 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7447
7448 if (enable_vpid) {
7449 /*
7450 * Trivially support vpid by letting L2s share their parent
7451 * L1's vpid. TODO: move to a more elaborate solution, giving
7452 * each L2 its own vpid and exposing the vpid feature to L1.
7453 */
7454 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7455 vmx_flush_tlb(vcpu);
7456 }
7457
7458 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7459 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7460 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7461 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7462 else
7463 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7464 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7465 vmx_set_efer(vcpu, vcpu->arch.efer);
7466
7467 /*
7468 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7469 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7470 * The CR0_READ_SHADOW is what L2 should have expected to read given
7471 * the specifications by L1; It's not enough to take
7472 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7473 * have more bits than L1 expected.
7474 */
7475 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7476 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7477
7478 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7479 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7480
7481 /* shadow page tables on either EPT or shadow page tables */
7482 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7483 kvm_mmu_reset_context(vcpu);
7484
7485 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7486 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7487}
7488
cd232ad0
NHE		 7489/*
7490 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7491 * for running an L2 nested guest.
7492 */
7493static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7494{
7495 struct vmcs12 *vmcs12;
7496 struct vcpu_vmx *vmx = to_vmx(vcpu);
7497 int cpu;
7498 struct loaded_vmcs *vmcs02;
7499
7500 if (!nested_vmx_check_permission(vcpu) ||
7501 !nested_vmx_check_vmcs12(vcpu))
7502 return 1;
7503
7504 skip_emulated_instruction(vcpu);
7505 vmcs12 = get_vmcs12(vcpu);
7506
7c177938
NHE		 7507 /*
7508 * The nested entry process starts with enforcing various prerequisites
7509 * on vmcs12 as required by the Intel SDM, and act appropriately when
7510 * they fail: As the SDM explains, some conditions should cause the
7511 * instruction to fail, while others will cause the instruction to seem
7512 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7513 * To speed up the normal (success) code path, we should avoid checking
7514 * for misconfigurations which will anyway be caught by the processor
7515 * when using the merged vmcs02.
7516 */
7517 if (vmcs12->launch_state == launch) {
7518 nested_vmx_failValid(vcpu,
7519 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7520 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7521 return 1;
7522 }
7523
26539bd0
PB		 7524 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7525 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7526 return 1;
7527 }
7528
7c177938
NHE		 7529 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7530 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7531 /*TODO: Also verify bits beyond physical address width are 0*/
7532 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7533 return 1;
7534 }
7535
7536 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7537 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7538 /*TODO: Also verify bits beyond physical address width are 0*/
7539 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7540 return 1;
7541 }
7542
7543 if (vmcs12->vm_entry_msr_load_count > 0 ||
7544 vmcs12->vm_exit_msr_load_count > 0 ||
7545 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7546 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7547 __func__);
7c177938
NHE		 7548 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7549 return 1;
7550 }
7551
7552 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7553 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7554 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7555 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7556 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7557 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7558 !vmx_control_verify(vmcs12->vm_exit_controls,
7559 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7560 !vmx_control_verify(vmcs12->vm_entry_controls,
7561 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7562 {
7563 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7564 return 1;
7565 }
7566
7567 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7568 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7569 nested_vmx_failValid(vcpu,
7570 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7571 return 1;
7572 }
7573
7574 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7575 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7576 nested_vmx_entry_failure(vcpu, vmcs12,
7577 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7578 return 1;
7579 }
7580 if (vmcs12->vmcs_link_pointer != -1ull) {
7581 nested_vmx_entry_failure(vcpu, vmcs12,
7582 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7583 return 1;
7584 }
7585
7586 /*
7587 * We're finally done with prerequisite checking, and can start with
7588 * the nested entry.
7589 */
7590
cd232ad0
NHE		 7591 vmcs02 = nested_get_current_vmcs02(vmx);
7592 if (!vmcs02)
7593 return -ENOMEM;
7594
7595 enter_guest_mode(vcpu);
7596
7597 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7598
7599 cpu = get_cpu();
7600 vmx->loaded_vmcs = vmcs02;
7601 vmx_vcpu_put(vcpu);
7602 vmx_vcpu_load(vcpu, cpu);
7603 vcpu->cpu = cpu;
7604 put_cpu();
7605
36c3cc42
JK		 7606 vmx_segment_cache_clear(vmx);
7607
cd232ad0
NHE		 7608 vmcs12->launch_state = 1;
7609
7610 prepare_vmcs02(vcpu, vmcs12);
7611
7612 /*
7613 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7614 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7615 * returned as far as L1 is concerned. It will only return (and set
7616 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7617 */
7618 return 1;
7619}
7620
4704d0be
NHE		 7621/*
7622 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7623 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7624 * This function returns the new value we should put in vmcs12.guest_cr0.
7625 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7626 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7627 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7628 * didn't trap the bit, because if L1 did, so would L0).
7629 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7630 * been modified by L2, and L1 knows it. So just leave the old value of
7631 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7632 * isn't relevant, because if L0 traps this bit it can set it to anything.
7633 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7634 * changed these bits, and therefore they need to be updated, but L0
7635 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7636 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7637 */
7638static inline unsigned long
7639vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7640{
7641 return
7642 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7643 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7644 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7645 vcpu->arch.cr0_guest_owned_bits));
7646}
7647
7648static inline unsigned long
7649vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7650{
7651 return
7652 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7653 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7654 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7655 vcpu->arch.cr4_guest_owned_bits));
7656}
7657
5f3d5799
JK		 7658static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7659 struct vmcs12 *vmcs12)
7660{
7661 u32 idt_vectoring;
7662 unsigned int nr;
7663
7664 if (vcpu->arch.exception.pending) {
7665 nr = vcpu->arch.exception.nr;
7666 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7667
7668 if (kvm_exception_is_soft(nr)) {
7669 vmcs12->vm_exit_instruction_len =
7670 vcpu->arch.event_exit_inst_len;
7671 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7672 } else
7673 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7674
7675 if (vcpu->arch.exception.has_error_code) {
7676 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7677 vmcs12->idt_vectoring_error_code =
7678 vcpu->arch.exception.error_code;
7679 }
7680
7681 vmcs12->idt_vectoring_info_field = idt_vectoring;
7682 } else if (vcpu->arch.nmi_pending) {
7683 vmcs12->idt_vectoring_info_field =
7684 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7685 } else if (vcpu->arch.interrupt.pending) {
7686 nr = vcpu->arch.interrupt.nr;
7687 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7688
7689 if (vcpu->arch.interrupt.soft) {
7690 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7691 vmcs12->vm_entry_instruction_len =
7692 vcpu->arch.event_exit_inst_len;
7693 } else
7694 idt_vectoring |= INTR_TYPE_EXT_INTR;
7695
7696 vmcs12->idt_vectoring_info_field = idt_vectoring;
7697 }
7698}
7699
4704d0be
NHE		 7700/*
7701 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7702 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7703 * and this function updates it to reflect the changes to the guest state while
7704 * L2 was running (and perhaps made some exits which were handled directly by L0
7705 * without going back to L1), and to reflect the exit reason.
7706 * Note that we do not have to copy here all VMCS fields, just those that
7707 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7708 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7709 * which already writes to vmcs12 directly.
7710 */
733568f9 7711static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7712{
7713 /* update guest state fields: */
7714 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7715 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7716
7717 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7718 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7719 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7720 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7721
7722 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7723 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7724 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7725 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7726 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7727 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7728 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7729 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7730 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7731 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7732 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7733 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7734 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7735 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7736 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7737 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7738 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7739 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7740 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7741 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7742 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7743 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7744 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7745 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7746 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7747 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7748 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7749 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7750 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7751 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7752 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7753 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7754 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7755 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7756 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7757 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7758
4704d0be
NHE		 7759 vmcs12->guest_interruptibility_info =
7760 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7761 vmcs12->guest_pending_dbg_exceptions =
7762 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7763
c18911a2
JK		 7764 vmcs12->vm_entry_controls =
7765 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7766 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7767
4704d0be
NHE		 7768 /* TODO: These cannot have changed unless we have MSR bitmaps and
7769 * the relevant bit asks not to trap the change */
7770 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 7771 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 7772 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7773 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7774 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7775 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7776
7777 /* update exit information fields: */
7778
957c897e 7779 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7780 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7781
7782 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 7783 if ((vmcs12->vm_exit_intr_info &
7784 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7785 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7786 vmcs12->vm_exit_intr_error_code =
7787 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 7788 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 7789 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7790 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7791
5f3d5799
JK		 7792 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7793 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7794 * instead of reading the real value. */
4704d0be 7795 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 7796
7797 /*
7798 * Transfer the event that L0 or L1 may wanted to inject into
7799 * L2 to IDT_VECTORING_INFO_FIELD.
7800 */
7801 vmcs12_save_pending_event(vcpu, vmcs12);
7802 }
7803
7804 /*
7805 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7806 * preserved above and would only end up incorrectly in L1.
7807 */
7808 vcpu->arch.nmi_injected = false;
7809 kvm_clear_exception_queue(vcpu);
7810 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 7811}
7812
7813/*
7814 * A part of what we need to when the nested L2 guest exits and we want to
7815 * run its L1 parent, is to reset L1's guest state to the host state specified
7816 * in vmcs12.
7817 * This function is to be called not only on normal nested exit, but also on
7818 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7819 * Failures During or After Loading Guest State").
7820 * This function should be called when the active VMCS is L1's (vmcs01).
7821 */
733568f9
JK		 7822static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7823 struct vmcs12 *vmcs12)
4704d0be
NHE		 7824{
7825 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7826 vcpu->arch.efer = vmcs12->host_ia32_efer;
7827 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7828 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7829 else
7830 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7831 vmx_set_efer(vcpu, vcpu->arch.efer);
7832
7833 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7834 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
c4627c72 7835 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
4704d0be
NHE		 7836 /*
7837 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7838 * actually changed, because it depends on the current state of
7839 * fpu_active (which may have changed).
7840 * Note that vmx_set_cr0 refers to efer set above.
7841 */
7842 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7843 /*
7844 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7845 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7846 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7847 */
7848 update_exception_bitmap(vcpu);
7849 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7850 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7851
7852 /*
7853 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7854 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7855 */
7856 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7857 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7858
7859 /* shadow page tables on either EPT or shadow page tables */
7860 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7861 kvm_mmu_reset_context(vcpu);
7862
7863 if (enable_vpid) {
7864 /*
7865 * Trivially support vpid by letting L2s share their parent
7866 * L1's vpid. TODO: move to a more elaborate solution, giving
7867 * each L2 its own vpid and exposing the vpid feature to L1.
7868 */
7869 vmx_flush_tlb(vcpu);
7870 }
7871
7872
7873 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7874 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7875 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7876 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7877 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7878 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7879 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7880 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7881 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7882 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7883 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7884 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7885 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7886 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7887 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7888
7889 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7890 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7891 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7892 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7893 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 7894
7895 kvm_set_dr(vcpu, 7, 0x400);
7896 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 7897}
7898
7899/*
7900 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7901 * and modify vmcs12 to make it see what it would expect to see there if
7902 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7903 */
7904static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7905{
7906 struct vcpu_vmx *vmx = to_vmx(vcpu);
7907 int cpu;
7908 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7909
5f3d5799
JK		 7910 /* trying to cancel vmlaunch/vmresume is a bug */
7911 WARN_ON_ONCE(vmx->nested.nested_run_pending);
7912
4704d0be
NHE		 7913 leave_guest_mode(vcpu);
7914 prepare_vmcs12(vcpu, vmcs12);
7915
7916 cpu = get_cpu();
7917 vmx->loaded_vmcs = &vmx->vmcs01;
7918 vmx_vcpu_put(vcpu);
7919 vmx_vcpu_load(vcpu, cpu);
7920 vcpu->cpu = cpu;
7921 put_cpu();
7922
36c3cc42
JK		 7923 vmx_segment_cache_clear(vmx);
7924
4704d0be
NHE		 7925 /* if no vmcs02 cache requested, remove the one we used */
7926 if (VMCS02_POOL_SIZE == 0)
7927 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7928
7929 load_vmcs12_host_state(vcpu, vmcs12);
7930
27fc51b2 7931 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7932 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7933
7934 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7935 vmx->host_rsp = 0;
7936
7937 /* Unpin physical memory we referred to in vmcs02 */
7938 if (vmx->nested.apic_access_page) {
7939 nested_release_page(vmx->nested.apic_access_page);
7940 vmx->nested.apic_access_page = 0;
7941 }
7942
7943 /*
7944 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7945 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7946 * success or failure flag accordingly.
7947 */
7948 if (unlikely(vmx->fail)) {
7949 vmx->fail = 0;
7950 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7951 } else
7952 nested_vmx_succeed(vcpu);
7953}
7954
7c177938
NHE		 7955/*
7956 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7957 * 23.7 "VM-entry failures during or after loading guest state" (this also
7958 * lists the acceptable exit-reason and exit-qualification parameters).
7959 * It should only be called before L2 actually succeeded to run, and when
7960 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7961 */
7962static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7963 struct vmcs12 *vmcs12,
7964 u32 reason, unsigned long qualification)
7965{
7966 load_vmcs12_host_state(vcpu, vmcs12);
7967 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7968 vmcs12->exit_qualification = qualification;
7969 nested_vmx_succeed(vcpu);
7970}
7971
8a76d7f2
JR		 7972static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7973 struct x86_instruction_info *info,
7974 enum x86_intercept_stage stage)
7975{
7976 return X86EMUL_CONTINUE;
7977}
7978
cbdd1bea 7979static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7980 .cpu_has_kvm_support = cpu_has_kvm_support,
7981 .disabled_by_bios = vmx_disabled_by_bios,
7982 .hardware_setup = hardware_setup,
7983 .hardware_unsetup = hardware_unsetup,
002c7f7c 7984 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7985 .hardware_enable = hardware_enable,
7986 .hardware_disable = hardware_disable,
04547156 7987 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7988
7989 .vcpu_create = vmx_create_vcpu,
7990 .vcpu_free = vmx_free_vcpu,
04d2cc77 7991 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7992
04d2cc77 7993 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7994 .vcpu_load = vmx_vcpu_load,
7995 .vcpu_put = vmx_vcpu_put,
7996
c8639010 7997 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7998 .get_msr = vmx_get_msr,
7999 .set_msr = vmx_set_msr,
8000 .get_segment_base = vmx_get_segment_base,
8001 .get_segment = vmx_get_segment,
8002 .set_segment = vmx_set_segment,
2e4d2653 8003 .get_cpl = vmx_get_cpl,
6aa8b732 8004 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8005 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8006 .decache_cr3 = vmx_decache_cr3,
25c4c276 8007 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8008 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8009 .set_cr3 = vmx_set_cr3,
8010 .set_cr4 = vmx_set_cr4,
6aa8b732 8011 .set_efer = vmx_set_efer,
6aa8b732
AK		 8012 .get_idt = vmx_get_idt,
8013 .set_idt = vmx_set_idt,
8014 .get_gdt = vmx_get_gdt,
8015 .set_gdt = vmx_set_gdt,
020df079 8016 .set_dr7 = vmx_set_dr7,
5fdbf976 8017 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8018 .get_rflags = vmx_get_rflags,
8019 .set_rflags = vmx_set_rflags,
ebcbab4c 8020 .fpu_activate = vmx_fpu_activate,
02daab21 8021 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8022
8023 .tlb_flush = vmx_flush_tlb,
6aa8b732 8024
6aa8b732 8025 .run = vmx_vcpu_run,
6062d012 8026 .handle_exit = vmx_handle_exit,
6aa8b732 8027 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8028 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8029 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8030 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8031 .set_irq = vmx_inject_irq,
95ba8273 8032 .set_nmi = vmx_inject_nmi,
298101da 8033 .queue_exception = vmx_queue_exception,
b463a6f7 8034 .cancel_injection = vmx_cancel_injection,
78646121 8035 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8036 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8037 .get_nmi_mask = vmx_get_nmi_mask,
8038 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8039 .enable_nmi_window = enable_nmi_window,
8040 .enable_irq_window = enable_irq_window,
8041 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8042 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8043 .vm_has_apicv = vmx_vm_has_apicv,
8044 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8045 .hwapic_irr_update = vmx_hwapic_irr_update,
8046 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8047 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8048 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8049
cbc94022 8050 .set_tss_addr = vmx_set_tss_addr,
67253af5 8051 .get_tdp_level = get_ept_level,
4b12f0de 8052 .get_mt_mask = vmx_get_mt_mask,
229456fc 8053
586f9607 8054 .get_exit_info = vmx_get_exit_info,
586f9607 8055
17cc3935 8056 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8057
8058 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8059
8060 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8061 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8062
8063 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8064
8065 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8066
4051b188 8067 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8068 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8069 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8070 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8071 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8072 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8073
8074 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8075
8076 .check_intercept = vmx_check_intercept,
a547c6db 8077 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8078};
8079
8080static int __init vmx_init(void)
8081{
8d14695f 8082 int r, i, msr;
26bb0981
AK		 8083
8084 rdmsrl_safe(MSR_EFER, &host_efer);
8085
8086 for (i = 0; i < NR_VMX_MSR; ++i)
8087 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8088
3e7c73e9 8089 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8090 if (!vmx_io_bitmap_a)
8091 return -ENOMEM;
8092
2106a548
GC		 8093 r = -ENOMEM;
8094
3e7c73e9 8095 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8096 if (!vmx_io_bitmap_b)
fdef3ad1 8097 goto out;
fdef3ad1 8098
5897297b 8099 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8100 if (!vmx_msr_bitmap_legacy)
25c5f225 8101 goto out1;
2106a548 8102
8d14695f
YZ		 8103 vmx_msr_bitmap_legacy_x2apic =
8104 (unsigned long *)__get_free_page(GFP_KERNEL);
8105 if (!vmx_msr_bitmap_legacy_x2apic)
8106 goto out2;
25c5f225 8107
5897297b 8108 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8109 if (!vmx_msr_bitmap_longmode)
8d14695f 8110 goto out3;
2106a548 8111
8d14695f
YZ		 8112 vmx_msr_bitmap_longmode_x2apic =
8113 (unsigned long *)__get_free_page(GFP_KERNEL);
8114 if (!vmx_msr_bitmap_longmode_x2apic)
8115 goto out4;
4607c2d7
AG		 8116 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8117 if (!vmx_vmread_bitmap)
8118 goto out5;
8119
8120 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8121 if (!vmx_vmwrite_bitmap)
8122 goto out6;
8123
8124 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8125 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8126 /* shadowed read/write fields */
8127 for (i = 0; i < max_shadow_read_write_fields; i++) {
8128 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8129 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8130 }
8131 /* shadowed read only fields */
8132 for (i = 0; i < max_shadow_read_only_fields; i++)
8133 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8134
fdef3ad1
HQ		 8135 /*
8136 * Allow direct access to the PC debug port (it is often used for I/O
8137 * delays, but the vmexits simply slow things down).
8138 */
3e7c73e9
AK		 8139 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8140 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8141
3e7c73e9 8142 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8143
5897297b
AK		 8144 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8145 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8146
2384d2b3
SY		 8147 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8148
0ee75bea
AK		 8149 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8150 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8151 if (r)
4607c2d7 8152 goto out7;
25c5f225 8153
8f536b76
ZY		 8154#ifdef CONFIG_KEXEC
8155 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8156 crash_vmclear_local_loaded_vmcss);
8157#endif
8158
5897297b
AK		 8159 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8160 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8161 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8162 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8163 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8164 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8165 memcpy(vmx_msr_bitmap_legacy_x2apic,
8166 vmx_msr_bitmap_legacy, PAGE_SIZE);
8167 memcpy(vmx_msr_bitmap_longmode_x2apic,
8168 vmx_msr_bitmap_longmode, PAGE_SIZE);
8169
01e439be 8170 if (enable_apicv) {
8d14695f
YZ		 8171 for (msr = 0x800; msr <= 0x8ff; msr++)
8172 vmx_disable_intercept_msr_read_x2apic(msr);
8173
8174 /* According SDM, in x2apic mode, the whole id reg is used.
8175 * But in KVM, it only use the highest eight bits. Need to
8176 * intercept it */
8177 vmx_enable_intercept_msr_read_x2apic(0x802);
8178 /* TMCCT */
8179 vmx_enable_intercept_msr_read_x2apic(0x839);
8180 /* TPR */
8181 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8182 /* EOI */
8183 vmx_disable_intercept_msr_write_x2apic(0x80b);
8184 /* SELF-IPI */
8185 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8186 }
fdef3ad1 8187
089d034e 8188 if (enable_ept) {
3f6d8c8a
XH		 8189 kvm_mmu_set_mask_ptes(0ull,
8190 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8191 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8192 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8193 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8194 kvm_enable_tdp();
8195 } else
8196 kvm_disable_tdp();
1439442c 8197
fdef3ad1
HQ		 8198 return 0;
8199
4607c2d7
AG		 8200out7:
8201 free_page((unsigned long)vmx_vmwrite_bitmap);
8202out6:
8203 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8204out5:
8205 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8206out4:
5897297b 8207 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8208out3:
8209 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8210out2:
5897297b 8211 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8212out1:
3e7c73e9 8213 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8214out:
3e7c73e9 8215 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8216 return r;
6aa8b732
AK		 8217}
8218
8219static void __exit vmx_exit(void)
8220{
8d14695f
YZ		 8221 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8222 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8223 free_page((unsigned long)vmx_msr_bitmap_legacy);
8224 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8225 free_page((unsigned long)vmx_io_bitmap_b);
8226 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8227 free_page((unsigned long)vmx_vmwrite_bitmap);
8228 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8229
8f536b76
ZY		 8230#ifdef CONFIG_KEXEC
8231 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8232 synchronize_rcu();
8233#endif
8234
cb498ea2 8235 kvm_exit();
6aa8b732
AK		 8236}
8237
8238module_init(vmx_init)
8239module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)