projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86 emulator: convert a few freestanding emulations to fastop
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
801d3424
NHE		 87/*
88 * If nested=1, nested virtualization is supported, i.e., guests may use
89 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
90 * use VMX instructions.
91 */
476bc001 92static bool __read_mostly nested = 0;
801d3424
NHE		 93module_param(nested, bool, S_IRUGO);
94
cdc0e244
AK		 95#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
96 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
97#define KVM_GUEST_CR0_MASK \
98 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
99#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 100 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 101#define KVM_VM_CR0_ALWAYS_ON \
102 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 103#define KVM_CR4_GUEST_OWNED_BITS \
104 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
105 | X86_CR4_OSXMMEXCPT)
106
cdc0e244
AK		 107#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
108#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109
78ac8b47
AK		 110#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111
4b8d54f9
ZE		 112/*
113 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
114 * ple_gap: upper bound on the amount of time between two successive
115 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 116 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 117 * ple_window: upper bound on the amount of time a guest is allowed to execute
118 * in a PAUSE loop. Tests indicate that most spinlocks are held for
119 * less than 2^12 cycles
120 * Time is measured based on a counter that runs at the same rate as the TSC,
121 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 */
00c25bce 123#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 124#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
125static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
126module_param(ple_gap, int, S_IRUGO);
127
128static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
129module_param(ple_window, int, S_IRUGO);
130
83287ea4
AK		 131extern const ulong vmx_return;
132
8bf00a52 133#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 134#define VMCS02_POOL_SIZE 1
61d2ef2c 135
a2fa3e9f
GH		 136struct vmcs {
137 u32 revision_id;
138 u32 abort;
139 char data[0];
140};
141
d462b819
NHE		 142/*
143 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
144 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
145 * loaded on this CPU (so we can clear them if the CPU goes down).
146 */
147struct loaded_vmcs {
148 struct vmcs *vmcs;
149 int cpu;
150 int launched;
151 struct list_head loaded_vmcss_on_cpu_link;
152};
153
26bb0981
AK		 154struct shared_msr_entry {
155 unsigned index;
156 u64 data;
d5696725 157 u64 mask;
26bb0981
AK		 158};
159
a9d30f33
NHE		 160/*
161 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
162 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
163 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
164 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
165 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
166 * More than one of these structures may exist, if L1 runs multiple L2 guests.
167 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
168 * underlying hardware which will be used to run L2.
169 * This structure is packed to ensure that its layout is identical across
170 * machines (necessary for live migration).
171 * If there are changes in this struct, VMCS12_REVISION must be changed.
172 */
22bd0358 173typedef u64 natural_width;
a9d30f33
NHE		 174struct __packed vmcs12 {
175 /* According to the Intel spec, a VMCS region must start with the
176 * following two fields. Then follow implementation-specific data.
177 */
178 u32 revision_id;
179 u32 abort;
22bd0358 180
27d6c865
NHE		 181 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
182 u32 padding[7]; /* room for future expansion */
183
22bd0358
NHE		 184 u64 io_bitmap_a;
185 u64 io_bitmap_b;
186 u64 msr_bitmap;
187 u64 vm_exit_msr_store_addr;
188 u64 vm_exit_msr_load_addr;
189 u64 vm_entry_msr_load_addr;
190 u64 tsc_offset;
191 u64 virtual_apic_page_addr;
192 u64 apic_access_addr;
193 u64 ept_pointer;
194 u64 guest_physical_address;
195 u64 vmcs_link_pointer;
196 u64 guest_ia32_debugctl;
197 u64 guest_ia32_pat;
198 u64 guest_ia32_efer;
199 u64 guest_ia32_perf_global_ctrl;
200 u64 guest_pdptr0;
201 u64 guest_pdptr1;
202 u64 guest_pdptr2;
203 u64 guest_pdptr3;
204 u64 host_ia32_pat;
205 u64 host_ia32_efer;
206 u64 host_ia32_perf_global_ctrl;
207 u64 padding64[8]; /* room for future expansion */
208 /*
209 * To allow migration of L1 (complete with its L2 guests) between
210 * machines of different natural widths (32 or 64 bit), we cannot have
211 * unsigned long fields with no explict size. We use u64 (aliased
212 * natural_width) instead. Luckily, x86 is little-endian.
213 */
214 natural_width cr0_guest_host_mask;
215 natural_width cr4_guest_host_mask;
216 natural_width cr0_read_shadow;
217 natural_width cr4_read_shadow;
218 natural_width cr3_target_value0;
219 natural_width cr3_target_value1;
220 natural_width cr3_target_value2;
221 natural_width cr3_target_value3;
222 natural_width exit_qualification;
223 natural_width guest_linear_address;
224 natural_width guest_cr0;
225 natural_width guest_cr3;
226 natural_width guest_cr4;
227 natural_width guest_es_base;
228 natural_width guest_cs_base;
229 natural_width guest_ss_base;
230 natural_width guest_ds_base;
231 natural_width guest_fs_base;
232 natural_width guest_gs_base;
233 natural_width guest_ldtr_base;
234 natural_width guest_tr_base;
235 natural_width guest_gdtr_base;
236 natural_width guest_idtr_base;
237 natural_width guest_dr7;
238 natural_width guest_rsp;
239 natural_width guest_rip;
240 natural_width guest_rflags;
241 natural_width guest_pending_dbg_exceptions;
242 natural_width guest_sysenter_esp;
243 natural_width guest_sysenter_eip;
244 natural_width host_cr0;
245 natural_width host_cr3;
246 natural_width host_cr4;
247 natural_width host_fs_base;
248 natural_width host_gs_base;
249 natural_width host_tr_base;
250 natural_width host_gdtr_base;
251 natural_width host_idtr_base;
252 natural_width host_ia32_sysenter_esp;
253 natural_width host_ia32_sysenter_eip;
254 natural_width host_rsp;
255 natural_width host_rip;
256 natural_width paddingl[8]; /* room for future expansion */
257 u32 pin_based_vm_exec_control;
258 u32 cpu_based_vm_exec_control;
259 u32 exception_bitmap;
260 u32 page_fault_error_code_mask;
261 u32 page_fault_error_code_match;
262 u32 cr3_target_count;
263 u32 vm_exit_controls;
264 u32 vm_exit_msr_store_count;
265 u32 vm_exit_msr_load_count;
266 u32 vm_entry_controls;
267 u32 vm_entry_msr_load_count;
268 u32 vm_entry_intr_info_field;
269 u32 vm_entry_exception_error_code;
270 u32 vm_entry_instruction_len;
271 u32 tpr_threshold;
272 u32 secondary_vm_exec_control;
273 u32 vm_instruction_error;
274 u32 vm_exit_reason;
275 u32 vm_exit_intr_info;
276 u32 vm_exit_intr_error_code;
277 u32 idt_vectoring_info_field;
278 u32 idt_vectoring_error_code;
279 u32 vm_exit_instruction_len;
280 u32 vmx_instruction_info;
281 u32 guest_es_limit;
282 u32 guest_cs_limit;
283 u32 guest_ss_limit;
284 u32 guest_ds_limit;
285 u32 guest_fs_limit;
286 u32 guest_gs_limit;
287 u32 guest_ldtr_limit;
288 u32 guest_tr_limit;
289 u32 guest_gdtr_limit;
290 u32 guest_idtr_limit;
291 u32 guest_es_ar_bytes;
292 u32 guest_cs_ar_bytes;
293 u32 guest_ss_ar_bytes;
294 u32 guest_ds_ar_bytes;
295 u32 guest_fs_ar_bytes;
296 u32 guest_gs_ar_bytes;
297 u32 guest_ldtr_ar_bytes;
298 u32 guest_tr_ar_bytes;
299 u32 guest_interruptibility_info;
300 u32 guest_activity_state;
301 u32 guest_sysenter_cs;
302 u32 host_ia32_sysenter_cs;
303 u32 padding32[8]; /* room for future expansion */
304 u16 virtual_processor_id;
305 u16 guest_es_selector;
306 u16 guest_cs_selector;
307 u16 guest_ss_selector;
308 u16 guest_ds_selector;
309 u16 guest_fs_selector;
310 u16 guest_gs_selector;
311 u16 guest_ldtr_selector;
312 u16 guest_tr_selector;
313 u16 host_es_selector;
314 u16 host_cs_selector;
315 u16 host_ss_selector;
316 u16 host_ds_selector;
317 u16 host_fs_selector;
318 u16 host_gs_selector;
319 u16 host_tr_selector;
a9d30f33
NHE		 320};
321
322/*
323 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
324 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
325 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 */
327#define VMCS12_REVISION 0x11e57ed0
328
329/*
330 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
331 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
332 * current implementation, 4K are reserved to avoid future complications.
333 */
334#define VMCS12_SIZE 0x1000
335
ff2f6fe9
NHE		 336/* Used to remember the last vmcs02 used for some recently used vmcs12s */
337struct vmcs02_list {
338 struct list_head list;
339 gpa_t vmptr;
340 struct loaded_vmcs vmcs02;
341};
342
ec378aee
NHE		 343/*
344 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
345 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 */
347struct nested_vmx {
348 /* Has the level1 guest done vmxon? */
349 bool vmxon;
a9d30f33
NHE		 350
351 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 gpa_t current_vmptr;
353 /* The host-usable pointer to the above */
354 struct page *current_vmcs12_page;
355 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 356
357 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
358 struct list_head vmcs02_pool;
359 int vmcs02_num;
fe3ef05c 360 u64 vmcs01_tsc_offset;
644d711a
NHE		 361 /* L2 must run next, and mustn't decide to exit to L1. */
362 bool nested_run_pending;
fe3ef05c
NHE		 363 /*
364 * Guest pages referred to in vmcs02 with host-physical pointers, so
365 * we must keep them pinned while L2 runs.
366 */
367 struct page *apic_access_page;
ec378aee
NHE		 368};
369
a2fa3e9f 370struct vcpu_vmx {
fb3f0f51 371 struct kvm_vcpu vcpu;
313dbd49 372 unsigned long host_rsp;
29bd8a78 373 u8 fail;
69c73028 374 u8 cpl;
9d58b931 375 bool nmi_known_unmasked;
51aa01d1 376 u32 exit_intr_info;
1155f76a 377 u32 idt_vectoring_info;
6de12732 378 ulong rflags;
26bb0981 379 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 380 int nmsrs;
381 int save_nmsrs;
a2fa3e9f 382#ifdef CONFIG_X86_64
44ea2b17
AK		 383 u64 msr_host_kernel_gs_base;
384 u64 msr_guest_kernel_gs_base;
a2fa3e9f 385#endif
d462b819
NHE		 386 /*
387 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
388 * non-nested (L1) guest, it always points to vmcs01. For a nested
389 * guest (L2), it points to a different VMCS.
390 */
391 struct loaded_vmcs vmcs01;
392 struct loaded_vmcs *loaded_vmcs;
393 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 394 struct msr_autoload {
395 unsigned nr;
396 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
397 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
398 } msr_autoload;
a2fa3e9f
GH		 399 struct {
400 int loaded;
401 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 402#ifdef CONFIG_X86_64
403 u16 ds_sel, es_sel;
404#endif
152d3f2f
LV		 405 int gs_ldt_reload_needed;
406 int fs_reload_needed;
d77c26fc 407 } host_state;
9c8cba37 408 struct {
7ffd92c5 409 int vm86_active;
78ac8b47 410 ulong save_rflags;
f5f7b2fe
AK		 411 struct kvm_segment segs[8];
412 } rmode;
413 struct {
414 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 415 struct kvm_save_segment {
416 u16 selector;
417 unsigned long base;
418 u32 limit;
419 u32 ar;
f5f7b2fe 420 } seg[8];
2fb92db1 421 } segment_cache;
2384d2b3 422 int vpid;
04fa4d32 423 bool emulation_required;
3b86cd99
JK		 424
425 /* Support for vnmi-less CPUs */
426 int soft_vnmi_blocked;
427 ktime_t entry_time;
428 s64 vnmi_blocked_time;
a0861c02 429 u32 exit_reason;
4e47c7a6
SY		 430
431 bool rdtscp_enabled;
ec378aee
NHE		 432
433 /* Support for a guest hypervisor (nested VMX) */
434 struct nested_vmx nested;
a2fa3e9f
GH		 435};
436
2fb92db1
AK		 437enum segment_cache_field {
438 SEG_FIELD_SEL = 0,
439 SEG_FIELD_BASE = 1,
440 SEG_FIELD_LIMIT = 2,
441 SEG_FIELD_AR = 3,
442
443 SEG_FIELD_NR = 4
444};
445
a2fa3e9f
GH		 446static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
447{
fb3f0f51 448 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 449}
450
22bd0358
NHE		 451#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
452#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
453#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
454 [number##_HIGH] = VMCS12_OFFSET(name)+4
455
772e0318 456static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 457 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
458 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
459 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
460 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
461 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
462 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
463 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
464 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
465 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
466 FIELD(HOST_ES_SELECTOR, host_es_selector),
467 FIELD(HOST_CS_SELECTOR, host_cs_selector),
468 FIELD(HOST_SS_SELECTOR, host_ss_selector),
469 FIELD(HOST_DS_SELECTOR, host_ds_selector),
470 FIELD(HOST_FS_SELECTOR, host_fs_selector),
471 FIELD(HOST_GS_SELECTOR, host_gs_selector),
472 FIELD(HOST_TR_SELECTOR, host_tr_selector),
473 FIELD64(IO_BITMAP_A, io_bitmap_a),
474 FIELD64(IO_BITMAP_B, io_bitmap_b),
475 FIELD64(MSR_BITMAP, msr_bitmap),
476 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
477 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
478 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
479 FIELD64(TSC_OFFSET, tsc_offset),
480 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
481 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
482 FIELD64(EPT_POINTER, ept_pointer),
483 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
484 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
485 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
486 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
487 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
488 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
489 FIELD64(GUEST_PDPTR0, guest_pdptr0),
490 FIELD64(GUEST_PDPTR1, guest_pdptr1),
491 FIELD64(GUEST_PDPTR2, guest_pdptr2),
492 FIELD64(GUEST_PDPTR3, guest_pdptr3),
493 FIELD64(HOST_IA32_PAT, host_ia32_pat),
494 FIELD64(HOST_IA32_EFER, host_ia32_efer),
495 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
496 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
497 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
498 FIELD(EXCEPTION_BITMAP, exception_bitmap),
499 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
500 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
501 FIELD(CR3_TARGET_COUNT, cr3_target_count),
502 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
503 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
504 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
505 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
506 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
507 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
508 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
509 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
510 FIELD(TPR_THRESHOLD, tpr_threshold),
511 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
512 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
513 FIELD(VM_EXIT_REASON, vm_exit_reason),
514 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
515 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
516 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
517 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
518 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
519 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
520 FIELD(GUEST_ES_LIMIT, guest_es_limit),
521 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
522 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
523 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
524 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
525 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
526 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
527 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
528 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
529 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
530 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
531 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
532 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
533 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
534 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
535 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
536 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
537 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
538 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
539 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
540 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
541 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
542 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
543 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
544 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
545 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
546 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
547 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
548 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
549 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
550 FIELD(EXIT_QUALIFICATION, exit_qualification),
551 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
552 FIELD(GUEST_CR0, guest_cr0),
553 FIELD(GUEST_CR3, guest_cr3),
554 FIELD(GUEST_CR4, guest_cr4),
555 FIELD(GUEST_ES_BASE, guest_es_base),
556 FIELD(GUEST_CS_BASE, guest_cs_base),
557 FIELD(GUEST_SS_BASE, guest_ss_base),
558 FIELD(GUEST_DS_BASE, guest_ds_base),
559 FIELD(GUEST_FS_BASE, guest_fs_base),
560 FIELD(GUEST_GS_BASE, guest_gs_base),
561 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
562 FIELD(GUEST_TR_BASE, guest_tr_base),
563 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
564 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
565 FIELD(GUEST_DR7, guest_dr7),
566 FIELD(GUEST_RSP, guest_rsp),
567 FIELD(GUEST_RIP, guest_rip),
568 FIELD(GUEST_RFLAGS, guest_rflags),
569 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
570 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
571 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
572 FIELD(HOST_CR0, host_cr0),
573 FIELD(HOST_CR3, host_cr3),
574 FIELD(HOST_CR4, host_cr4),
575 FIELD(HOST_FS_BASE, host_fs_base),
576 FIELD(HOST_GS_BASE, host_gs_base),
577 FIELD(HOST_TR_BASE, host_tr_base),
578 FIELD(HOST_GDTR_BASE, host_gdtr_base),
579 FIELD(HOST_IDTR_BASE, host_idtr_base),
580 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
581 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
582 FIELD(HOST_RSP, host_rsp),
583 FIELD(HOST_RIP, host_rip),
584};
585static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
586
587static inline short vmcs_field_to_offset(unsigned long field)
588{
589 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
590 return -1;
591 return vmcs_field_to_offset_table[field];
592}
593
a9d30f33
NHE		 594static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
595{
596 return to_vmx(vcpu)->nested.current_vmcs12;
597}
598
599static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
600{
601 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 602 if (is_error_page(page))
a9d30f33 603 return NULL;
32cad84f 604
a9d30f33
NHE		 605 return page;
606}
607
608static void nested_release_page(struct page *page)
609{
610 kvm_release_page_dirty(page);
611}
612
613static void nested_release_page_clean(struct page *page)
614{
615 kvm_release_page_clean(page);
616}
617
4e1096d2 618static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 619static void kvm_cpu_vmxon(u64 addr);
620static void kvm_cpu_vmxoff(void);
aff48baa 621static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 622static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 623static void vmx_set_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
625static void vmx_get_segment(struct kvm_vcpu *vcpu,
626 struct kvm_segment *var, int seg);
d99e4152
GN		 627static bool guest_state_valid(struct kvm_vcpu *vcpu);
628static u32 vmx_segment_access_rights(struct kvm_segment *var);
75880a01 629
6aa8b732
AK		 630static DEFINE_PER_CPU(struct vmcs *, vmxarea);
631static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 632/*
633 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
634 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
635 */
636static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 637static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 638
3e7c73e9
AK		 639static unsigned long *vmx_io_bitmap_a;
640static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 641static unsigned long *vmx_msr_bitmap_legacy;
642static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 643
110312c8 644static bool cpu_has_load_ia32_efer;
8bf00a52 645static bool cpu_has_load_perf_global_ctrl;
110312c8 646
2384d2b3
SY		 647static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
648static DEFINE_SPINLOCK(vmx_vpid_lock);
649
1c3d14fe 650static struct vmcs_config {
6aa8b732
AK		 651 int size;
652 int order;
653 u32 revision_id;
1c3d14fe
YS		 654 u32 pin_based_exec_ctrl;
655 u32 cpu_based_exec_ctrl;
f78e0e2e 656 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 657 u32 vmexit_ctrl;
658 u32 vmentry_ctrl;
659} vmcs_config;
6aa8b732 660
efff9e53 661static struct vmx_capability {
d56f546d
SY		 662 u32 ept;
663 u32 vpid;
664} vmx_capability;
665
6aa8b732
AK		 666#define VMX_SEGMENT_FIELD(seg) \
667 [VCPU_SREG_##seg] = { \
668 .selector = GUEST_##seg##_SELECTOR, \
669 .base = GUEST_##seg##_BASE, \
670 .limit = GUEST_##seg##_LIMIT, \
671 .ar_bytes = GUEST_##seg##_AR_BYTES, \
672 }
673
772e0318 674static const struct kvm_vmx_segment_field {
6aa8b732
AK		 675 unsigned selector;
676 unsigned base;
677 unsigned limit;
678 unsigned ar_bytes;
679} kvm_vmx_segment_fields[] = {
680 VMX_SEGMENT_FIELD(CS),
681 VMX_SEGMENT_FIELD(DS),
682 VMX_SEGMENT_FIELD(ES),
683 VMX_SEGMENT_FIELD(FS),
684 VMX_SEGMENT_FIELD(GS),
685 VMX_SEGMENT_FIELD(SS),
686 VMX_SEGMENT_FIELD(TR),
687 VMX_SEGMENT_FIELD(LDTR),
688};
689
26bb0981
AK		 690static u64 host_efer;
691
6de4f3ad
AK		 692static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
693
4d56c8a7 694/*
8c06585d 695 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 696 * away by decrementing the array size.
697 */
6aa8b732 698static const u32 vmx_msr_index[] = {
05b3e0c2 699#ifdef CONFIG_X86_64
44ea2b17 700 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 701#endif
8c06585d 702 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 703};
9d8f549d 704#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 705
31299944 706static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
709 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 710 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 711}
712
31299944 713static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 714{
715 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
716 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 717 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 718}
719
31299944 720static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 721{
722 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
723 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 724 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 725}
726
31299944 727static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 728{
729 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
730 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
731}
732
31299944 733static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 734{
735 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
736 INTR_INFO_VALID_MASK)) ==
737 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
738}
739
31299944 740static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 741{
04547156 742 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 743}
744
31299944 745static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 746{
04547156 747 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 748}
749
31299944 750static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 751{
04547156 752 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 753}
754
31299944 755static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 756{
04547156
SY		 757 return vmcs_config.cpu_based_exec_ctrl &
758 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 759}
760
774ead3a 761static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 762{
04547156
SY		 763 return vmcs_config.cpu_based_2nd_exec_ctrl &
764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
765}
766
767static inline bool cpu_has_vmx_flexpriority(void)
768{
769 return cpu_has_vmx_tpr_shadow() &&
770 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 771}
772
e799794e
MT		 773static inline bool cpu_has_vmx_ept_execute_only(void)
774{
31299944 775 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 776}
777
778static inline bool cpu_has_vmx_eptp_uncacheable(void)
779{
31299944 780 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 781}
782
783static inline bool cpu_has_vmx_eptp_writeback(void)
784{
31299944 785 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 786}
787
788static inline bool cpu_has_vmx_ept_2m_page(void)
789{
31299944 790 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 791}
792
878403b7
SY		 793static inline bool cpu_has_vmx_ept_1g_page(void)
794{
31299944 795 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 796}
797
4bc9b982
SY		 798static inline bool cpu_has_vmx_ept_4levels(void)
799{
800 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
801}
802
83c3a331
XH		 803static inline bool cpu_has_vmx_ept_ad_bits(void)
804{
805 return vmx_capability.ept & VMX_EPT_AD_BIT;
806}
807
31299944 808static inline bool cpu_has_vmx_invept_context(void)
d56f546d 809{
31299944 810 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 811}
812
31299944 813static inline bool cpu_has_vmx_invept_global(void)
d56f546d 814{
31299944 815 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 816}
817
518c8aee
GJ		 818static inline bool cpu_has_vmx_invvpid_single(void)
819{
820 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
821}
822
b9d762fa
GJ		 823static inline bool cpu_has_vmx_invvpid_global(void)
824{
825 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
826}
827
31299944 828static inline bool cpu_has_vmx_ept(void)
d56f546d 829{
04547156
SY		 830 return vmcs_config.cpu_based_2nd_exec_ctrl &
831 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 832}
833
31299944 834static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 835{
836 return vmcs_config.cpu_based_2nd_exec_ctrl &
837 SECONDARY_EXEC_UNRESTRICTED_GUEST;
838}
839
31299944 840static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 841{
842 return vmcs_config.cpu_based_2nd_exec_ctrl &
843 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
844}
845
31299944 846static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 847{
6d3e435e 848 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_vpid(void)
2384d2b3 852{
04547156
SY		 853 return vmcs_config.cpu_based_2nd_exec_ctrl &
854 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 855}
856
31299944 857static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 858{
859 return vmcs_config.cpu_based_2nd_exec_ctrl &
860 SECONDARY_EXEC_RDTSCP;
861}
862
ad756a16
MJ		 863static inline bool cpu_has_vmx_invpcid(void)
864{
865 return vmcs_config.cpu_based_2nd_exec_ctrl &
866 SECONDARY_EXEC_ENABLE_INVPCID;
867}
868
31299944 869static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 870{
871 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
872}
873
f5f48ee1
SY		 874static inline bool cpu_has_vmx_wbinvd_exit(void)
875{
876 return vmcs_config.cpu_based_2nd_exec_ctrl &
877 SECONDARY_EXEC_WBINVD_EXITING;
878}
879
04547156
SY		 880static inline bool report_flexpriority(void)
881{
882 return flexpriority_enabled;
883}
884
fe3ef05c
NHE		 885static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
886{
887 return vmcs12->cpu_based_vm_exec_control & bit;
888}
889
890static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
891{
892 return (vmcs12->cpu_based_vm_exec_control &
893 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
894 (vmcs12->secondary_vm_exec_control & bit);
895}
896
644d711a
NHE		 897static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
898 struct kvm_vcpu *vcpu)
899{
900 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
901}
902
903static inline bool is_exception(u32 intr_info)
904{
905 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
906 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
907}
908
909static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 910static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
911 struct vmcs12 *vmcs12,
912 u32 reason, unsigned long qualification);
913
8b9cf98c 914static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 915{
916 int i;
917
a2fa3e9f 918 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 919 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 920 return i;
921 return -1;
922}
923
2384d2b3
SY		 924static inline void __invvpid(int ext, u16 vpid, gva_t gva)
925{
926 struct {
927 u64 vpid : 16;
928 u64 rsvd : 48;
929 u64 gva;
930 } operand = { vpid, 0, gva };
931
4ecac3fd 932 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 933 /* CF==1 or ZF==1 --> rc = -1 */
934 "; ja 1f ; ud2 ; 1:"
935 : : "a"(&operand), "c"(ext) : "cc", "memory");
936}
937
1439442c
SY		 938static inline void __invept(int ext, u64 eptp, gpa_t gpa)
939{
940 struct {
941 u64 eptp, gpa;
942 } operand = {eptp, gpa};
943
4ecac3fd 944 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 945 /* CF==1 or ZF==1 --> rc = -1 */
946 "; ja 1f ; ud2 ; 1:\n"
947 : : "a" (&operand), "c" (ext) : "cc", "memory");
948}
949
26bb0981 950static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 951{
952 int i;
953
8b9cf98c 954 i = __find_msr_index(vmx, msr);
a75beee6 955 if (i >= 0)
a2fa3e9f 956 return &vmx->guest_msrs[i];
8b6d44c7 957 return NULL;
7725f0ba
AK		 958}
959
6aa8b732
AK		 960static void vmcs_clear(struct vmcs *vmcs)
961{
962 u64 phys_addr = __pa(vmcs);
963 u8 error;
964
4ecac3fd 965 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 966 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 967 : "cc", "memory");
968 if (error)
969 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
970 vmcs, phys_addr);
971}
972
d462b819
NHE		 973static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
974{
975 vmcs_clear(loaded_vmcs->vmcs);
976 loaded_vmcs->cpu = -1;
977 loaded_vmcs->launched = 0;
978}
979
7725b894
DX		 980static void vmcs_load(struct vmcs *vmcs)
981{
982 u64 phys_addr = __pa(vmcs);
983 u8 error;
984
985 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 986 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 987 : "cc", "memory");
988 if (error)
2844d849 989 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 990 vmcs, phys_addr);
991}
992
8f536b76
ZY		 993#ifdef CONFIG_KEXEC
994/*
995 * This bitmap is used to indicate whether the vmclear
996 * operation is enabled on all cpus. All disabled by
997 * default.
998 */
999static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1000
1001static inline void crash_enable_local_vmclear(int cpu)
1002{
1003 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1004}
1005
1006static inline void crash_disable_local_vmclear(int cpu)
1007{
1008 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1009}
1010
1011static inline int crash_local_vmclear_enabled(int cpu)
1012{
1013 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1014}
1015
1016static void crash_vmclear_local_loaded_vmcss(void)
1017{
1018 int cpu = raw_smp_processor_id();
1019 struct loaded_vmcs *v;
1020
1021 if (!crash_local_vmclear_enabled(cpu))
1022 return;
1023
1024 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1025 loaded_vmcss_on_cpu_link)
1026 vmcs_clear(v->vmcs);
1027}
1028#else
1029static inline void crash_enable_local_vmclear(int cpu) { }
1030static inline void crash_disable_local_vmclear(int cpu) { }
1031#endif /* CONFIG_KEXEC */
1032
d462b819 1033static void __loaded_vmcs_clear(void *arg)
6aa8b732 1034{
d462b819 1035 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1036 int cpu = raw_smp_processor_id();
6aa8b732 1037
d462b819
NHE		 1038 if (loaded_vmcs->cpu != cpu)
1039 return; /* vcpu migration can race with cpu offline */
1040 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1041 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1042 crash_disable_local_vmclear(cpu);
d462b819 1043 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1044
1045 /*
1046 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1047 * is before setting loaded_vmcs->vcpu to -1 which is done in
1048 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1049 * then adds the vmcs into percpu list before it is deleted.
1050 */
1051 smp_wmb();
1052
d462b819 1053 loaded_vmcs_init(loaded_vmcs);
8f536b76 1054 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1055}
1056
d462b819 1057static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1058{
e6c7d321
XG		 1059 int cpu = loaded_vmcs->cpu;
1060
1061 if (cpu != -1)
1062 smp_call_function_single(cpu,
1063 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1064}
1065
1760dd49 1066static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1067{
1068 if (vmx->vpid == 0)
1069 return;
1070
518c8aee
GJ		 1071 if (cpu_has_vmx_invvpid_single())
1072 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1073}
1074
b9d762fa
GJ		 1075static inline void vpid_sync_vcpu_global(void)
1076{
1077 if (cpu_has_vmx_invvpid_global())
1078 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1079}
1080
1081static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1082{
1083 if (cpu_has_vmx_invvpid_single())
1760dd49 1084 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1085 else
1086 vpid_sync_vcpu_global();
1087}
1088
1439442c
SY		 1089static inline void ept_sync_global(void)
1090{
1091 if (cpu_has_vmx_invept_global())
1092 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1093}
1094
1095static inline void ept_sync_context(u64 eptp)
1096{
089d034e 1097 if (enable_ept) {
1439442c
SY		 1098 if (cpu_has_vmx_invept_context())
1099 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1100 else
1101 ept_sync_global();
1102 }
1103}
1104
96304217 1105static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1106{
5e520e62 1107 unsigned long value;
6aa8b732 1108
5e520e62
AK		 1109 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1110 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1111 return value;
1112}
1113
96304217 1114static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1115{
1116 return vmcs_readl(field);
1117}
1118
96304217 1119static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1120{
1121 return vmcs_readl(field);
1122}
1123
96304217 1124static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1125{
05b3e0c2 1126#ifdef CONFIG_X86_64
6aa8b732
AK		 1127 return vmcs_readl(field);
1128#else
1129 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1130#endif
1131}
1132
e52de1b8
AK		 1133static noinline void vmwrite_error(unsigned long field, unsigned long value)
1134{
1135 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1136 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1137 dump_stack();
1138}
1139
6aa8b732
AK		 1140static void vmcs_writel(unsigned long field, unsigned long value)
1141{
1142 u8 error;
1143
4ecac3fd 1144 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1145 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1146 if (unlikely(error))
1147 vmwrite_error(field, value);
6aa8b732
AK		 1148}
1149
1150static void vmcs_write16(unsigned long field, u16 value)
1151{
1152 vmcs_writel(field, value);
1153}
1154
1155static void vmcs_write32(unsigned long field, u32 value)
1156{
1157 vmcs_writel(field, value);
1158}
1159
1160static void vmcs_write64(unsigned long field, u64 value)
1161{
6aa8b732 1162 vmcs_writel(field, value);
7682f2d0 1163#ifndef CONFIG_X86_64
6aa8b732
AK		 1164 asm volatile ("");
1165 vmcs_writel(field+1, value >> 32);
1166#endif
1167}
1168
2ab455cc
AL		 1169static void vmcs_clear_bits(unsigned long field, u32 mask)
1170{
1171 vmcs_writel(field, vmcs_readl(field) & ~mask);
1172}
1173
1174static void vmcs_set_bits(unsigned long field, u32 mask)
1175{
1176 vmcs_writel(field, vmcs_readl(field) | mask);
1177}
1178
2fb92db1
AK		 1179static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1180{
1181 vmx->segment_cache.bitmask = 0;
1182}
1183
1184static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1185 unsigned field)
1186{
1187 bool ret;
1188 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1189
1190 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1191 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1192 vmx->segment_cache.bitmask = 0;
1193 }
1194 ret = vmx->segment_cache.bitmask & mask;
1195 vmx->segment_cache.bitmask |= mask;
1196 return ret;
1197}
1198
1199static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1200{
1201 u16 *p = &vmx->segment_cache.seg[seg].selector;
1202
1203 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1204 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1205 return *p;
1206}
1207
1208static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1209{
1210 ulong *p = &vmx->segment_cache.seg[seg].base;
1211
1212 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1213 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1214 return *p;
1215}
1216
1217static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1218{
1219 u32 *p = &vmx->segment_cache.seg[seg].limit;
1220
1221 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1222 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1223 return *p;
1224}
1225
1226static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1227{
1228 u32 *p = &vmx->segment_cache.seg[seg].ar;
1229
1230 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1231 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1232 return *p;
1233}
1234
abd3f2d6
AK		 1235static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1236{
1237 u32 eb;
1238
fd7373cc
JK		 1239 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1240 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1241 if ((vcpu->guest_debug &
1242 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1243 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1244 eb |= 1u << BP_VECTOR;
7ffd92c5 1245 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1246 eb = ~0;
089d034e 1247 if (enable_ept)
1439442c 1248 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1249 if (vcpu->fpu_active)
1250 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1251
1252 /* When we are running a nested L2 guest and L1 specified for it a
1253 * certain exception bitmap, we must trap the same exceptions and pass
1254 * them to L1. When running L2, we will only handle the exceptions
1255 * specified above if L1 did not want them.
1256 */
1257 if (is_guest_mode(vcpu))
1258 eb |= get_vmcs12(vcpu)->exception_bitmap;
1259
abd3f2d6
AK		 1260 vmcs_write32(EXCEPTION_BITMAP, eb);
1261}
1262
8bf00a52
GN		 1263static void clear_atomic_switch_msr_special(unsigned long entry,
1264 unsigned long exit)
1265{
1266 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1267 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1268}
1269
61d2ef2c
AK		 1270static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1271{
1272 unsigned i;
1273 struct msr_autoload *m = &vmx->msr_autoload;
1274
8bf00a52
GN		 1275 switch (msr) {
1276 case MSR_EFER:
1277 if (cpu_has_load_ia32_efer) {
1278 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1279 VM_EXIT_LOAD_IA32_EFER);
1280 return;
1281 }
1282 break;
1283 case MSR_CORE_PERF_GLOBAL_CTRL:
1284 if (cpu_has_load_perf_global_ctrl) {
1285 clear_atomic_switch_msr_special(
1286 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1287 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1288 return;
1289 }
1290 break;
110312c8
AK		 1291 }
1292
61d2ef2c
AK		 1293 for (i = 0; i < m->nr; ++i)
1294 if (m->guest[i].index == msr)
1295 break;
1296
1297 if (i == m->nr)
1298 return;
1299 --m->nr;
1300 m->guest[i] = m->guest[m->nr];
1301 m->host[i] = m->host[m->nr];
1302 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1303 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1304}
1305
8bf00a52
GN		 1306static void add_atomic_switch_msr_special(unsigned long entry,
1307 unsigned long exit, unsigned long guest_val_vmcs,
1308 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1309{
1310 vmcs_write64(guest_val_vmcs, guest_val);
1311 vmcs_write64(host_val_vmcs, host_val);
1312 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1313 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1314}
1315
61d2ef2c
AK		 1316static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1317 u64 guest_val, u64 host_val)
1318{
1319 unsigned i;
1320 struct msr_autoload *m = &vmx->msr_autoload;
1321
8bf00a52
GN		 1322 switch (msr) {
1323 case MSR_EFER:
1324 if (cpu_has_load_ia32_efer) {
1325 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1326 VM_EXIT_LOAD_IA32_EFER,
1327 GUEST_IA32_EFER,
1328 HOST_IA32_EFER,
1329 guest_val, host_val);
1330 return;
1331 }
1332 break;
1333 case MSR_CORE_PERF_GLOBAL_CTRL:
1334 if (cpu_has_load_perf_global_ctrl) {
1335 add_atomic_switch_msr_special(
1336 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1337 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1338 GUEST_IA32_PERF_GLOBAL_CTRL,
1339 HOST_IA32_PERF_GLOBAL_CTRL,
1340 guest_val, host_val);
1341 return;
1342 }
1343 break;
110312c8
AK		 1344 }
1345
61d2ef2c
AK		 1346 for (i = 0; i < m->nr; ++i)
1347 if (m->guest[i].index == msr)
1348 break;
1349
e7fc6f93
GN		 1350 if (i == NR_AUTOLOAD_MSRS) {
1351 printk_once(KERN_WARNING"Not enough mst switch entries. "
1352 "Can't add msr %x\n", msr);
1353 return;
1354 } else if (i == m->nr) {
61d2ef2c
AK		 1355 ++m->nr;
1356 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1357 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1358 }
1359
1360 m->guest[i].index = msr;
1361 m->guest[i].value = guest_val;
1362 m->host[i].index = msr;
1363 m->host[i].value = host_val;
1364}
1365
33ed6329
AK		 1366static void reload_tss(void)
1367{
33ed6329
AK		 1368 /*
1369 * VT restores TR but not its size. Useless.
1370 */
d359192f 1371 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1372 struct desc_struct *descs;
33ed6329 1373
d359192f 1374 descs = (void *)gdt->address;
33ed6329
AK		 1375 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1376 load_TR_desc();
33ed6329
AK		 1377}
1378
92c0d900 1379static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1380{
3a34a881 1381 u64 guest_efer;
51c6cf66
AK		 1382 u64 ignore_bits;
1383
f6801dff 1384 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1385
51c6cf66 1386 /*
0fa06071 1387 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1388 * outside long mode
1389 */
1390 ignore_bits = EFER_NX | EFER_SCE;
1391#ifdef CONFIG_X86_64
1392 ignore_bits |= EFER_LMA | EFER_LME;
1393 /* SCE is meaningful only in long mode on Intel */
1394 if (guest_efer & EFER_LMA)
1395 ignore_bits &= ~(u64)EFER_SCE;
1396#endif
51c6cf66
AK		 1397 guest_efer &= ~ignore_bits;
1398 guest_efer |= host_efer & ignore_bits;
26bb0981 1399 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1400 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1401
1402 clear_atomic_switch_msr(vmx, MSR_EFER);
1403 /* On ept, can't emulate nx, and must switch nx atomically */
1404 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1405 guest_efer = vmx->vcpu.arch.efer;
1406 if (!(guest_efer & EFER_LMA))
1407 guest_efer &= ~EFER_LME;
1408 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1409 return false;
1410 }
1411
26bb0981 1412 return true;
51c6cf66
AK		 1413}
1414
2d49ec72
GN		 1415static unsigned long segment_base(u16 selector)
1416{
d359192f 1417 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1418 struct desc_struct *d;
1419 unsigned long table_base;
1420 unsigned long v;
1421
1422 if (!(selector & ~3))
1423 return 0;
1424
d359192f 1425 table_base = gdt->address;
2d49ec72
GN		 1426
1427 if (selector & 4) { /* from ldt */
1428 u16 ldt_selector = kvm_read_ldt();
1429
1430 if (!(ldt_selector & ~3))
1431 return 0;
1432
1433 table_base = segment_base(ldt_selector);
1434 }
1435 d = (struct desc_struct *)(table_base + (selector & ~7));
1436 v = get_desc_base(d);
1437#ifdef CONFIG_X86_64
1438 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1439 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1440#endif
1441 return v;
1442}
1443
1444static inline unsigned long kvm_read_tr_base(void)
1445{
1446 u16 tr;
1447 asm("str %0" : "=g"(tr));
1448 return segment_base(tr);
1449}
1450
04d2cc77 1451static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1452{
04d2cc77 1453 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1454 int i;
04d2cc77 1455
a2fa3e9f 1456 if (vmx->host_state.loaded)
33ed6329
AK		 1457 return;
1458
a2fa3e9f 1459 vmx->host_state.loaded = 1;
33ed6329
AK		 1460 /*
1461 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1462 * allow segment selectors with cpl > 0 or ti == 1.
1463 */
d6e88aec 1464 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1465 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1466 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1467 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1468 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1469 vmx->host_state.fs_reload_needed = 0;
1470 } else {
33ed6329 1471 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1472 vmx->host_state.fs_reload_needed = 1;
33ed6329 1473 }
9581d442 1474 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1475 if (!(vmx->host_state.gs_sel & 7))
1476 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1477 else {
1478 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1479 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1480 }
1481
b2da15ac
AK		 1482#ifdef CONFIG_X86_64
1483 savesegment(ds, vmx->host_state.ds_sel);
1484 savesegment(es, vmx->host_state.es_sel);
1485#endif
1486
33ed6329
AK		 1487#ifdef CONFIG_X86_64
1488 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1489 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1490#else
a2fa3e9f
GH		 1491 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1492 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1493#endif
707c0874
AK		 1494
1495#ifdef CONFIG_X86_64
c8770e7b
AK		 1496 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1497 if (is_long_mode(&vmx->vcpu))
44ea2b17 1498 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1499#endif
26bb0981
AK		 1500 for (i = 0; i < vmx->save_nmsrs; ++i)
1501 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1502 vmx->guest_msrs[i].data,
1503 vmx->guest_msrs[i].mask);
33ed6329
AK		 1504}
1505
a9b21b62 1506static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1507{
a2fa3e9f 1508 if (!vmx->host_state.loaded)
33ed6329
AK		 1509 return;
1510
e1beb1d3 1511 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1512 vmx->host_state.loaded = 0;
c8770e7b
AK		 1513#ifdef CONFIG_X86_64
1514 if (is_long_mode(&vmx->vcpu))
1515 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1516#endif
152d3f2f 1517 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1518 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1519#ifdef CONFIG_X86_64
9581d442 1520 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1521#else
1522 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1523#endif
33ed6329 1524 }
0a77fe4c
AK		 1525 if (vmx->host_state.fs_reload_needed)
1526 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1527#ifdef CONFIG_X86_64
1528 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1529 loadsegment(ds, vmx->host_state.ds_sel);
1530 loadsegment(es, vmx->host_state.es_sel);
1531 }
b2da15ac 1532#endif
152d3f2f 1533 reload_tss();
44ea2b17 1534#ifdef CONFIG_X86_64
c8770e7b 1535 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1536#endif
b1a74bf8
SS		 1537 /*
1538 * If the FPU is not active (through the host task or
1539 * the guest vcpu), then restore the cr0.TS bit.
1540 */
1541 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1542 stts();
3444d7da 1543 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1544}
1545
a9b21b62
AK		 1546static void vmx_load_host_state(struct vcpu_vmx *vmx)
1547{
1548 preempt_disable();
1549 __vmx_load_host_state(vmx);
1550 preempt_enable();
1551}
1552
6aa8b732
AK		 1553/*
1554 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1555 * vcpu mutex is already taken.
1556 */
15ad7146 1557static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1558{
a2fa3e9f 1559 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1560 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1561
4610c9cc
DX		 1562 if (!vmm_exclusive)
1563 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1564 else if (vmx->loaded_vmcs->cpu != cpu)
1565 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1566
d462b819
NHE		 1567 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1568 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1569 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1570 }
1571
d462b819 1572 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1573 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1574 unsigned long sysenter_esp;
1575
a8eeb04a 1576 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1577 local_irq_disable();
8f536b76 1578 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1579
1580 /*
1581 * Read loaded_vmcs->cpu should be before fetching
1582 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1583 * See the comments in __loaded_vmcs_clear().
1584 */
1585 smp_rmb();
1586
d462b819
NHE		 1587 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1588 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1589 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1590 local_irq_enable();
1591
6aa8b732
AK		 1592 /*
1593 * Linux uses per-cpu TSS and GDT, so set these when switching
1594 * processors.
1595 */
d6e88aec 1596 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1597 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1598
1599 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1600 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1601 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1602 }
6aa8b732
AK		 1603}
1604
1605static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1606{
a9b21b62 1607 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1608 if (!vmm_exclusive) {
d462b819
NHE		 1609 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1610 vcpu->cpu = -1;
4610c9cc
DX		 1611 kvm_cpu_vmxoff();
1612 }
6aa8b732
AK		 1613}
1614
5fd86fcf
AK		 1615static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1616{
81231c69
AK		 1617 ulong cr0;
1618
5fd86fcf
AK		 1619 if (vcpu->fpu_active)
1620 return;
1621 vcpu->fpu_active = 1;
81231c69
AK		 1622 cr0 = vmcs_readl(GUEST_CR0);
1623 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1624 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1625 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1626 update_exception_bitmap(vcpu);
edcafe3c 1627 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1628 if (is_guest_mode(vcpu))
1629 vcpu->arch.cr0_guest_owned_bits &=
1630 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1631 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1632}
1633
edcafe3c
AK		 1634static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1635
fe3ef05c
NHE		 1636/*
1637 * Return the cr0 value that a nested guest would read. This is a combination
1638 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1639 * its hypervisor (cr0_read_shadow).
1640 */
1641static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1642{
1643 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1644 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1645}
1646static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1647{
1648 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1649 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1650}
1651
5fd86fcf
AK		 1652static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1653{
36cf24e0
NHE		 1654 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1655 * set this *before* calling this function.
1656 */
edcafe3c 1657 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1658 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1659 update_exception_bitmap(vcpu);
edcafe3c
AK		 1660 vcpu->arch.cr0_guest_owned_bits = 0;
1661 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1662 if (is_guest_mode(vcpu)) {
1663 /*
1664 * L1's specified read shadow might not contain the TS bit,
1665 * so now that we turned on shadowing of this bit, we need to
1666 * set this bit of the shadow. Like in nested_vmx_run we need
1667 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1668 * up-to-date here because we just decached cr0.TS (and we'll
1669 * only update vmcs12->guest_cr0 on nested exit).
1670 */
1671 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1672 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1673 (vcpu->arch.cr0 & X86_CR0_TS);
1674 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1675 } else
1676 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1677}
1678
6aa8b732
AK		 1679static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1680{
78ac8b47 1681 unsigned long rflags, save_rflags;
345dcaa8 1682
6de12732
AK		 1683 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1684 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1685 rflags = vmcs_readl(GUEST_RFLAGS);
1686 if (to_vmx(vcpu)->rmode.vm86_active) {
1687 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1688 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1689 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1690 }
1691 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1692 }
6de12732 1693 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1694}
1695
1696static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1697{
6de12732
AK		 1698 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1699 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1700 if (to_vmx(vcpu)->rmode.vm86_active) {
1701 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1702 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1703 }
6aa8b732
AK		 1704 vmcs_writel(GUEST_RFLAGS, rflags);
1705}
1706
2809f5d2
GC		 1707static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1708{
1709 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1710 int ret = 0;
1711
1712 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1713 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1714 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1715 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1716
1717 return ret & mask;
1718}
1719
1720static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1721{
1722 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1723 u32 interruptibility = interruptibility_old;
1724
1725 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1726
48005f64 1727 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1728 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1729 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1730 interruptibility |= GUEST_INTR_STATE_STI;
1731
1732 if ((interruptibility != interruptibility_old))
1733 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1734}
1735
6aa8b732
AK		 1736static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1737{
1738 unsigned long rip;
6aa8b732 1739
5fdbf976 1740 rip = kvm_rip_read(vcpu);
6aa8b732 1741 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1742 kvm_rip_write(vcpu, rip);
6aa8b732 1743
2809f5d2
GC		 1744 /* skipping an emulated instruction also counts */
1745 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1746}
1747
0b6ac343
NHE		 1748/*
1749 * KVM wants to inject page-faults which it got to the guest. This function
1750 * checks whether in a nested guest, we need to inject them to L1 or L2.
1751 * This function assumes it is called with the exit reason in vmcs02 being
1752 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1753 * is running).
1754 */
1755static int nested_pf_handled(struct kvm_vcpu *vcpu)
1756{
1757 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1758
1759 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1760 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1761 return 0;
1762
1763 nested_vmx_vmexit(vcpu);
1764 return 1;
1765}
1766
298101da 1767static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1768 bool has_error_code, u32 error_code,
1769 bool reinject)
298101da 1770{
77ab6db0 1771 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1772 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1773
0b6ac343
NHE		 1774 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1775 nested_pf_handled(vcpu))
1776 return;
1777
8ab2d2e2 1778 if (has_error_code) {
77ab6db0 1779 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1780 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1781 }
77ab6db0 1782
7ffd92c5 1783 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1784 int inc_eip = 0;
1785 if (kvm_exception_is_soft(nr))
1786 inc_eip = vcpu->arch.event_exit_inst_len;
1787 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1788 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1789 return;
1790 }
1791
66fd3f7f
GN		 1792 if (kvm_exception_is_soft(nr)) {
1793 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1794 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1795 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1796 } else
1797 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1798
1799 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1800}
1801
4e47c7a6
SY		 1802static bool vmx_rdtscp_supported(void)
1803{
1804 return cpu_has_vmx_rdtscp();
1805}
1806
ad756a16
MJ		 1807static bool vmx_invpcid_supported(void)
1808{
1809 return cpu_has_vmx_invpcid() && enable_ept;
1810}
1811
a75beee6
ED		 1812/*
1813 * Swap MSR entry in host/guest MSR entry array.
1814 */
8b9cf98c 1815static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1816{
26bb0981 1817 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1818
1819 tmp = vmx->guest_msrs[to];
1820 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1821 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1822}
1823
e38aea3e
AK		 1824/*
1825 * Set up the vmcs to automatically save and restore system
1826 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1827 * mode, as fiddling with msrs is very expensive.
1828 */
8b9cf98c 1829static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1830{
26bb0981 1831 int save_nmsrs, index;
5897297b 1832 unsigned long *msr_bitmap;
e38aea3e 1833
a75beee6
ED		 1834 save_nmsrs = 0;
1835#ifdef CONFIG_X86_64
8b9cf98c 1836 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1837 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1838 if (index >= 0)
8b9cf98c
RR		 1839 move_msr_up(vmx, index, save_nmsrs++);
1840 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1841 if (index >= 0)
8b9cf98c
RR		 1842 move_msr_up(vmx, index, save_nmsrs++);
1843 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1844 if (index >= 0)
8b9cf98c 1845 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1846 index = __find_msr_index(vmx, MSR_TSC_AUX);
1847 if (index >= 0 && vmx->rdtscp_enabled)
1848 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1849 /*
8c06585d 1850 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1851 * if efer.sce is enabled.
1852 */
8c06585d 1853 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1854 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1855 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1856 }
1857#endif
92c0d900
AK		 1858 index = __find_msr_index(vmx, MSR_EFER);
1859 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1860 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1861
26bb0981 1862 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1863
1864 if (cpu_has_vmx_msr_bitmap()) {
1865 if (is_long_mode(&vmx->vcpu))
1866 msr_bitmap = vmx_msr_bitmap_longmode;
1867 else
1868 msr_bitmap = vmx_msr_bitmap_legacy;
1869
1870 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1871 }
e38aea3e
AK		 1872}
1873
6aa8b732
AK		 1874/*
1875 * reads and returns guest's timestamp counter "register"
1876 * guest_tsc = host_tsc + tsc_offset -- 21.3
1877 */
1878static u64 guest_read_tsc(void)
1879{
1880 u64 host_tsc, tsc_offset;
1881
1882 rdtscll(host_tsc);
1883 tsc_offset = vmcs_read64(TSC_OFFSET);
1884 return host_tsc + tsc_offset;
1885}
1886
d5c1785d
NHE		 1887/*
1888 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1889 * counter, even if a nested guest (L2) is currently running.
1890 */
886b470c 1891u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1892{
886b470c 1893 u64 tsc_offset;
d5c1785d 1894
d5c1785d
NHE		 1895 tsc_offset = is_guest_mode(vcpu) ?
1896 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1897 vmcs_read64(TSC_OFFSET);
1898 return host_tsc + tsc_offset;
1899}
1900
4051b188 1901/*
cc578287
ZA		 1902 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1903 * software catchup for faster rates on slower CPUs.
4051b188 1904 */
cc578287 1905static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1906{
cc578287
ZA		 1907 if (!scale)
1908 return;
1909
1910 if (user_tsc_khz > tsc_khz) {
1911 vcpu->arch.tsc_catchup = 1;
1912 vcpu->arch.tsc_always_catchup = 1;
1913 } else
1914 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1915}
1916
ba904635
WA		 1917static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1918{
1919 return vmcs_read64(TSC_OFFSET);
1920}
1921
6aa8b732 1922/*
99e3e30a 1923 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1924 */
99e3e30a 1925static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1926{
27fc51b2 1927 if (is_guest_mode(vcpu)) {
7991825b 1928 /*
27fc51b2
NHE		 1929 * We're here if L1 chose not to trap WRMSR to TSC. According
1930 * to the spec, this should set L1's TSC; The offset that L1
1931 * set for L2 remains unchanged, and still needs to be added
1932 * to the newly set TSC to get L2's TSC.
7991825b 1933 */
27fc51b2
NHE		 1934 struct vmcs12 *vmcs12;
1935 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1936 /* recalculate vmcs02.TSC_OFFSET: */
1937 vmcs12 = get_vmcs12(vcpu);
1938 vmcs_write64(TSC_OFFSET, offset +
1939 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1940 vmcs12->tsc_offset : 0));
1941 } else {
1942 vmcs_write64(TSC_OFFSET, offset);
1943 }
6aa8b732
AK		 1944}
1945
f1e2b260 1946static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1947{
1948 u64 offset = vmcs_read64(TSC_OFFSET);
1949 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1950 if (is_guest_mode(vcpu)) {
1951 /* Even when running L2, the adjustment needs to apply to L1 */
1952 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1953 }
e48672fa
ZA		 1954}
1955
857e4099
JR		 1956static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1957{
1958 return target_tsc - native_read_tsc();
1959}
1960
801d3424
NHE		 1961static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1962{
1963 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1964 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1965}
1966
1967/*
1968 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1969 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1970 * all guests if the "nested" module option is off, and can also be disabled
1971 * for a single guest by disabling its VMX cpuid bit.
1972 */
1973static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1974{
1975 return nested && guest_cpuid_has_vmx(vcpu);
1976}
1977
b87a51ae
NHE		 1978/*
1979 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1980 * returned for the various VMX controls MSRs when nested VMX is enabled.
1981 * The same values should also be used to verify that vmcs12 control fields are
1982 * valid during nested entry from L1 to L2.
1983 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1984 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1985 * bit in the high half is on if the corresponding bit in the control field
1986 * may be on. See also vmx_control_verify().
1987 * TODO: allow these variables to be modified (downgraded) by module options
1988 * or other means.
1989 */
1990static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1991static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1992static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1993static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1994static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1995static __init void nested_vmx_setup_ctls_msrs(void)
1996{
1997 /*
1998 * Note that as a general rule, the high half of the MSRs (bits in
1999 * the control fields which may be 1) should be initialized by the
2000 * intersection of the underlying hardware's MSR (i.e., features which
2001 * can be supported) and the list of features we want to expose -
2002 * because they are known to be properly supported in our code.
2003 * Also, usually, the low half of the MSRs (bits which must be 1) can
2004 * be set to 0, meaning that L1 may turn off any of these bits. The
2005 * reason is that if one of these bits is necessary, it will appear
2006 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2007 * fields of vmcs01 and vmcs02, will turn these bits off - and
2008 * nested_vmx_exit_handled() will not pass related exits to L1.
2009 * These rules have exceptions below.
2010 */
2011
2012 /* pin-based controls */
2013 /*
2014 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2015 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2016 */
2017 nested_vmx_pinbased_ctls_low = 0x16 ;
2018 nested_vmx_pinbased_ctls_high = 0x16 |
2019 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2020 PIN_BASED_VIRTUAL_NMIS;
2021
2022 /* exit controls */
2023 nested_vmx_exit_ctls_low = 0;
b6f1250e 2024 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2025#ifdef CONFIG_X86_64
2026 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2027#else
2028 nested_vmx_exit_ctls_high = 0;
2029#endif
2030
2031 /* entry controls */
2032 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2033 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2034 nested_vmx_entry_ctls_low = 0;
2035 nested_vmx_entry_ctls_high &=
2036 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2037
2038 /* cpu-based controls */
2039 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2040 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2041 nested_vmx_procbased_ctls_low = 0;
2042 nested_vmx_procbased_ctls_high &=
2043 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2044 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2045 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2046 CPU_BASED_CR3_STORE_EXITING |
2047#ifdef CONFIG_X86_64
2048 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2049#endif
2050 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2051 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2052 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2053 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2054 /*
2055 * We can allow some features even when not supported by the
2056 * hardware. For example, L1 can specify an MSR bitmap - and we
2057 * can use it to avoid exits to L1 - even when L0 runs L2
2058 * without MSR bitmaps.
2059 */
2060 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2061
2062 /* secondary cpu-based controls */
2063 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2064 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2065 nested_vmx_secondary_ctls_low = 0;
2066 nested_vmx_secondary_ctls_high &=
2067 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2068}
2069
2070static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2071{
2072 /*
2073 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2074 */
2075 return ((control & high) | low) == control;
2076}
2077
2078static inline u64 vmx_control_msr(u32 low, u32 high)
2079{
2080 return low | ((u64)high << 32);
2081}
2082
2083/*
2084 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2085 * also let it use VMX-specific MSRs.
2086 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2087 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2088 * like all other MSRs).
2089 */
2090static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2091{
2092 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2093 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2094 /*
2095 * According to the spec, processors which do not support VMX
2096 * should throw a #GP(0) when VMX capability MSRs are read.
2097 */
2098 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2099 return 1;
2100 }
2101
2102 switch (msr_index) {
2103 case MSR_IA32_FEATURE_CONTROL:
2104 *pdata = 0;
2105 break;
2106 case MSR_IA32_VMX_BASIC:
2107 /*
2108 * This MSR reports some information about VMX support. We
2109 * should return information about the VMX we emulate for the
2110 * guest, and the VMCS structure we give it - not about the
2111 * VMX support of the underlying hardware.
2112 */
2113 *pdata = VMCS12_REVISION |
2114 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2115 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2116 break;
2117 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2118 case MSR_IA32_VMX_PINBASED_CTLS:
2119 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2120 nested_vmx_pinbased_ctls_high);
2121 break;
2122 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2123 case MSR_IA32_VMX_PROCBASED_CTLS:
2124 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2125 nested_vmx_procbased_ctls_high);
2126 break;
2127 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2128 case MSR_IA32_VMX_EXIT_CTLS:
2129 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2130 nested_vmx_exit_ctls_high);
2131 break;
2132 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2133 case MSR_IA32_VMX_ENTRY_CTLS:
2134 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2135 nested_vmx_entry_ctls_high);
2136 break;
2137 case MSR_IA32_VMX_MISC:
2138 *pdata = 0;
2139 break;
2140 /*
2141 * These MSRs specify bits which the guest must keep fixed (on or off)
2142 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2143 * We picked the standard core2 setting.
2144 */
2145#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2146#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2147 case MSR_IA32_VMX_CR0_FIXED0:
2148 *pdata = VMXON_CR0_ALWAYSON;
2149 break;
2150 case MSR_IA32_VMX_CR0_FIXED1:
2151 *pdata = -1ULL;
2152 break;
2153 case MSR_IA32_VMX_CR4_FIXED0:
2154 *pdata = VMXON_CR4_ALWAYSON;
2155 break;
2156 case MSR_IA32_VMX_CR4_FIXED1:
2157 *pdata = -1ULL;
2158 break;
2159 case MSR_IA32_VMX_VMCS_ENUM:
2160 *pdata = 0x1f;
2161 break;
2162 case MSR_IA32_VMX_PROCBASED_CTLS2:
2163 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2164 nested_vmx_secondary_ctls_high);
2165 break;
2166 case MSR_IA32_VMX_EPT_VPID_CAP:
2167 /* Currently, no nested ept or nested vpid */
2168 *pdata = 0;
2169 break;
2170 default:
2171 return 0;
2172 }
2173
2174 return 1;
2175}
2176
2177static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2178{
2179 if (!nested_vmx_allowed(vcpu))
2180 return 0;
2181
2182 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2183 /* TODO: the right thing. */
2184 return 1;
2185 /*
2186 * No need to treat VMX capability MSRs specially: If we don't handle
2187 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2188 */
2189 return 0;
2190}
2191
6aa8b732
AK		 2192/*
2193 * Reads an msr value (of 'msr_index') into 'pdata'.
2194 * Returns 0 on success, non-0 otherwise.
2195 * Assumes vcpu_load() was already called.
2196 */
2197static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2198{
2199 u64 data;
26bb0981 2200 struct shared_msr_entry *msr;
6aa8b732
AK		 2201
2202 if (!pdata) {
2203 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2204 return -EINVAL;
2205 }
2206
2207 switch (msr_index) {
05b3e0c2 2208#ifdef CONFIG_X86_64
6aa8b732
AK		 2209 case MSR_FS_BASE:
2210 data = vmcs_readl(GUEST_FS_BASE);
2211 break;
2212 case MSR_GS_BASE:
2213 data = vmcs_readl(GUEST_GS_BASE);
2214 break;
44ea2b17
AK		 2215 case MSR_KERNEL_GS_BASE:
2216 vmx_load_host_state(to_vmx(vcpu));
2217 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2218 break;
26bb0981 2219#endif
6aa8b732 2220 case MSR_EFER:
3bab1f5d 2221 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2222 case MSR_IA32_TSC:
6aa8b732
AK		 2223 data = guest_read_tsc();
2224 break;
2225 case MSR_IA32_SYSENTER_CS:
2226 data = vmcs_read32(GUEST_SYSENTER_CS);
2227 break;
2228 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2229 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2230 break;
2231 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2232 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2233 break;
4e47c7a6
SY		 2234 case MSR_TSC_AUX:
2235 if (!to_vmx(vcpu)->rdtscp_enabled)
2236 return 1;
2237 /* Otherwise falls through */
6aa8b732 2238 default:
b87a51ae
NHE		 2239 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2240 return 0;
8b9cf98c 2241 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2242 if (msr) {
2243 data = msr->data;
2244 break;
6aa8b732 2245 }
3bab1f5d 2246 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2247 }
2248
2249 *pdata = data;
2250 return 0;
2251}
2252
2253/*
2254 * Writes msr value into into the appropriate "register".
2255 * Returns 0 on success, non-0 otherwise.
2256 * Assumes vcpu_load() was already called.
2257 */
8fe8ab46 2258static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2259{
a2fa3e9f 2260 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2261 struct shared_msr_entry *msr;
2cc51560 2262 int ret = 0;
8fe8ab46
WA		 2263 u32 msr_index = msr_info->index;
2264 u64 data = msr_info->data;
2cc51560 2265
6aa8b732 2266 switch (msr_index) {
3bab1f5d 2267 case MSR_EFER:
8fe8ab46 2268 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2269 break;
16175a79 2270#ifdef CONFIG_X86_64
6aa8b732 2271 case MSR_FS_BASE:
2fb92db1 2272 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2273 vmcs_writel(GUEST_FS_BASE, data);
2274 break;
2275 case MSR_GS_BASE:
2fb92db1 2276 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2277 vmcs_writel(GUEST_GS_BASE, data);
2278 break;
44ea2b17
AK		 2279 case MSR_KERNEL_GS_BASE:
2280 vmx_load_host_state(vmx);
2281 vmx->msr_guest_kernel_gs_base = data;
2282 break;
6aa8b732
AK		 2283#endif
2284 case MSR_IA32_SYSENTER_CS:
2285 vmcs_write32(GUEST_SYSENTER_CS, data);
2286 break;
2287 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2288 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2289 break;
2290 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2291 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2292 break;
af24a4e4 2293 case MSR_IA32_TSC:
8fe8ab46 2294 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2295 break;
468d472f
SY		 2296 case MSR_IA32_CR_PAT:
2297 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2298 vmcs_write64(GUEST_IA32_PAT, data);
2299 vcpu->arch.pat = data;
2300 break;
2301 }
8fe8ab46 2302 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2303 break;
ba904635
WA		 2304 case MSR_IA32_TSC_ADJUST:
2305 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2306 break;
2307 case MSR_TSC_AUX:
2308 if (!vmx->rdtscp_enabled)
2309 return 1;
2310 /* Check reserved bit, higher 32 bits should be zero */
2311 if ((data >> 32) != 0)
2312 return 1;
2313 /* Otherwise falls through */
6aa8b732 2314 default:
b87a51ae
NHE		 2315 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2316 break;
8b9cf98c 2317 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2318 if (msr) {
2319 msr->data = data;
2225fd56
AK		 2320 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2321 preempt_disable();
9ee73970
AK		 2322 kvm_set_shared_msr(msr->index, msr->data,
2323 msr->mask);
2225fd56
AK		 2324 preempt_enable();
2325 }
3bab1f5d 2326 break;
6aa8b732 2327 }
8fe8ab46 2328 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2329 }
2330
2cc51560 2331 return ret;
6aa8b732
AK		 2332}
2333
5fdbf976 2334static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2335{
5fdbf976
MT		 2336 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2337 switch (reg) {
2338 case VCPU_REGS_RSP:
2339 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2340 break;
2341 case VCPU_REGS_RIP:
2342 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2343 break;
6de4f3ad
AK		 2344 case VCPU_EXREG_PDPTR:
2345 if (enable_ept)
2346 ept_save_pdptrs(vcpu);
2347 break;
5fdbf976
MT		 2348 default:
2349 break;
2350 }
6aa8b732
AK		 2351}
2352
6aa8b732
AK		 2353static __init int cpu_has_kvm_support(void)
2354{
6210e37b 2355 return cpu_has_vmx();
6aa8b732
AK		 2356}
2357
2358static __init int vmx_disabled_by_bios(void)
2359{
2360 u64 msr;
2361
2362 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2363 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2364 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2365 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2366 && tboot_enabled())
2367 return 1;
23f3e991 2368 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2369 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2370 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2371 && !tboot_enabled()) {
2372 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2373 "activate TXT before enabling KVM\n");
cafd6659 2374 return 1;
f9335afe 2375 }
23f3e991
JC		 2376 /* launched w/o TXT and VMX disabled */
2377 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2378 && !tboot_enabled())
2379 return 1;
cafd6659
SW		 2380 }
2381
2382 return 0;
6aa8b732
AK		 2383}
2384
7725b894
DX		 2385static void kvm_cpu_vmxon(u64 addr)
2386{
2387 asm volatile (ASM_VMX_VMXON_RAX
2388 : : "a"(&addr), "m"(addr)
2389 : "memory", "cc");
2390}
2391
10474ae8 2392static int hardware_enable(void *garbage)
6aa8b732
AK		 2393{
2394 int cpu = raw_smp_processor_id();
2395 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2396 u64 old, test_bits;
6aa8b732 2397
10474ae8
AG		 2398 if (read_cr4() & X86_CR4_VMXE)
2399 return -EBUSY;
2400
d462b819 2401 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2402
2403 /*
2404 * Now we can enable the vmclear operation in kdump
2405 * since the loaded_vmcss_on_cpu list on this cpu
2406 * has been initialized.
2407 *
2408 * Though the cpu is not in VMX operation now, there
2409 * is no problem to enable the vmclear operation
2410 * for the loaded_vmcss_on_cpu list is empty!
2411 */
2412 crash_enable_local_vmclear(cpu);
2413
6aa8b732 2414 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2415
2416 test_bits = FEATURE_CONTROL_LOCKED;
2417 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2418 if (tboot_enabled())
2419 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2420
2421 if ((old & test_bits) != test_bits) {
6aa8b732 2422 /* enable and lock */
cafd6659
SW		 2423 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2424 }
66aee91a 2425 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2426
4610c9cc
DX		 2427 if (vmm_exclusive) {
2428 kvm_cpu_vmxon(phys_addr);
2429 ept_sync_global();
2430 }
10474ae8 2431
3444d7da
AK		 2432 store_gdt(&__get_cpu_var(host_gdt));
2433
10474ae8 2434 return 0;
6aa8b732
AK		 2435}
2436
d462b819 2437static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2438{
2439 int cpu = raw_smp_processor_id();
d462b819 2440 struct loaded_vmcs *v, *n;
543e4243 2441
d462b819
NHE		 2442 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2443 loaded_vmcss_on_cpu_link)
2444 __loaded_vmcs_clear(v);
543e4243
AK		 2445}
2446
710ff4a8
EH		 2447
2448/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2449 * tricks.
2450 */
2451static void kvm_cpu_vmxoff(void)
6aa8b732 2452{
4ecac3fd 2453 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2454}
2455
710ff4a8
EH		 2456static void hardware_disable(void *garbage)
2457{
4610c9cc 2458 if (vmm_exclusive) {
d462b819 2459 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2460 kvm_cpu_vmxoff();
2461 }
7725b894 2462 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2463}
2464
1c3d14fe 2465static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2466 u32 msr, u32 *result)
1c3d14fe
YS		 2467{
2468 u32 vmx_msr_low, vmx_msr_high;
2469 u32 ctl = ctl_min | ctl_opt;
2470
2471 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2472
2473 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2474 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2475
2476 /* Ensure minimum (required) set of control bits are supported. */
2477 if (ctl_min & ~ctl)
002c7f7c 2478 return -EIO;
1c3d14fe
YS		 2479
2480 *result = ctl;
2481 return 0;
2482}
2483
110312c8
AK		 2484static __init bool allow_1_setting(u32 msr, u32 ctl)
2485{
2486 u32 vmx_msr_low, vmx_msr_high;
2487
2488 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2489 return vmx_msr_high & ctl;
2490}
2491
002c7f7c 2492static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2493{
2494 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2495 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2496 u32 _pin_based_exec_control = 0;
2497 u32 _cpu_based_exec_control = 0;
f78e0e2e 2498 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2499 u32 _vmexit_control = 0;
2500 u32 _vmentry_control = 0;
2501
2502 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2503 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2504 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2505 &_pin_based_exec_control) < 0)
002c7f7c 2506 return -EIO;
1c3d14fe 2507
10166744 2508 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2509#ifdef CONFIG_X86_64
2510 CPU_BASED_CR8_LOAD_EXITING |
2511 CPU_BASED_CR8_STORE_EXITING |
2512#endif
d56f546d
SY		 2513 CPU_BASED_CR3_LOAD_EXITING |
2514 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2515 CPU_BASED_USE_IO_BITMAPS |
2516 CPU_BASED_MOV_DR_EXITING |
a7052897 2517 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2518 CPU_BASED_MWAIT_EXITING |
2519 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2520 CPU_BASED_INVLPG_EXITING |
2521 CPU_BASED_RDPMC_EXITING;
443381a8 2522
f78e0e2e 2523 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2524 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2525 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2526 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2527 &_cpu_based_exec_control) < 0)
002c7f7c 2528 return -EIO;
6e5d865c
YS		 2529#ifdef CONFIG_X86_64
2530 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2531 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2532 ~CPU_BASED_CR8_STORE_EXITING;
2533#endif
f78e0e2e 2534 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2535 min2 = 0;
2536 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2537 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2538 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2539 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2540 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2541 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2542 SECONDARY_EXEC_RDTSCP |
2543 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2544 if (adjust_vmx_controls(min2, opt2,
2545 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2546 &_cpu_based_2nd_exec_control) < 0)
2547 return -EIO;
2548 }
2549#ifndef CONFIG_X86_64
2550 if (!(_cpu_based_2nd_exec_control &
2551 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2552 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2553#endif
d56f546d 2554 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2555 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2556 enabled */
5fff7d27
GN		 2557 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2558 CPU_BASED_CR3_STORE_EXITING |
2559 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2560 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2561 vmx_capability.ept, vmx_capability.vpid);
2562 }
1c3d14fe
YS		 2563
2564 min = 0;
2565#ifdef CONFIG_X86_64
2566 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2567#endif
468d472f 2568 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2569 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2570 &_vmexit_control) < 0)
002c7f7c 2571 return -EIO;
1c3d14fe 2572
468d472f
SY		 2573 min = 0;
2574 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2575 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2576 &_vmentry_control) < 0)
002c7f7c 2577 return -EIO;
6aa8b732 2578
c68876fd 2579 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2580
2581 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2582 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2583 return -EIO;
1c3d14fe
YS		 2584
2585#ifdef CONFIG_X86_64
2586 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2587 if (vmx_msr_high & (1u<<16))
002c7f7c 2588 return -EIO;
1c3d14fe
YS		 2589#endif
2590
2591 /* Require Write-Back (WB) memory type for VMCS accesses. */
2592 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2593 return -EIO;
1c3d14fe 2594
002c7f7c
YS		 2595 vmcs_conf->size = vmx_msr_high & 0x1fff;
2596 vmcs_conf->order = get_order(vmcs_config.size);
2597 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2598
002c7f7c
YS		 2599 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2600 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2601 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2602 vmcs_conf->vmexit_ctrl = _vmexit_control;
2603 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2604
110312c8
AK		 2605 cpu_has_load_ia32_efer =
2606 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2607 VM_ENTRY_LOAD_IA32_EFER)
2608 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2609 VM_EXIT_LOAD_IA32_EFER);
2610
8bf00a52
GN		 2611 cpu_has_load_perf_global_ctrl =
2612 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2613 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2614 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2615 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2616
2617 /*
2618 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2619 * but due to arrata below it can't be used. Workaround is to use
2620 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2621 *
2622 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2623 *
2624 * AAK155 (model 26)
2625 * AAP115 (model 30)
2626 * AAT100 (model 37)
2627 * BC86,AAY89,BD102 (model 44)
2628 * BA97 (model 46)
2629 *
2630 */
2631 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2632 switch (boot_cpu_data.x86_model) {
2633 case 26:
2634 case 30:
2635 case 37:
2636 case 44:
2637 case 46:
2638 cpu_has_load_perf_global_ctrl = false;
2639 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2640 "does not work properly. Using workaround\n");
2641 break;
2642 default:
2643 break;
2644 }
2645 }
2646
1c3d14fe 2647 return 0;
c68876fd 2648}
6aa8b732
AK		 2649
2650static struct vmcs *alloc_vmcs_cpu(int cpu)
2651{
2652 int node = cpu_to_node(cpu);
2653 struct page *pages;
2654 struct vmcs *vmcs;
2655
6484eb3e 2656 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2657 if (!pages)
2658 return NULL;
2659 vmcs = page_address(pages);
1c3d14fe
YS		 2660 memset(vmcs, 0, vmcs_config.size);
2661 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2662 return vmcs;
2663}
2664
2665static struct vmcs *alloc_vmcs(void)
2666{
d3b2c338 2667 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2668}
2669
2670static void free_vmcs(struct vmcs *vmcs)
2671{
1c3d14fe 2672 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2673}
2674
d462b819
NHE		 2675/*
2676 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2677 */
2678static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2679{
2680 if (!loaded_vmcs->vmcs)
2681 return;
2682 loaded_vmcs_clear(loaded_vmcs);
2683 free_vmcs(loaded_vmcs->vmcs);
2684 loaded_vmcs->vmcs = NULL;
2685}
2686
39959588 2687static void free_kvm_area(void)
6aa8b732
AK		 2688{
2689 int cpu;
2690
3230bb47 2691 for_each_possible_cpu(cpu) {
6aa8b732 2692 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2693 per_cpu(vmxarea, cpu) = NULL;
2694 }
6aa8b732
AK		 2695}
2696
6aa8b732
AK		 2697static __init int alloc_kvm_area(void)
2698{
2699 int cpu;
2700
3230bb47 2701 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2702 struct vmcs *vmcs;
2703
2704 vmcs = alloc_vmcs_cpu(cpu);
2705 if (!vmcs) {
2706 free_kvm_area();
2707 return -ENOMEM;
2708 }
2709
2710 per_cpu(vmxarea, cpu) = vmcs;
2711 }
2712 return 0;
2713}
2714
2715static __init int hardware_setup(void)
2716{
002c7f7c
YS		 2717 if (setup_vmcs_config(&vmcs_config) < 0)
2718 return -EIO;
50a37eb4
JR		 2719
2720 if (boot_cpu_has(X86_FEATURE_NX))
2721 kvm_enable_efer_bits(EFER_NX);
2722
93ba03c2
SY		 2723 if (!cpu_has_vmx_vpid())
2724 enable_vpid = 0;
2725
4bc9b982
SY		 2726 if (!cpu_has_vmx_ept() ||
2727 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2728 enable_ept = 0;
3a624e29 2729 enable_unrestricted_guest = 0;
83c3a331 2730 enable_ept_ad_bits = 0;
3a624e29
NK		 2731 }
2732
83c3a331
XH		 2733 if (!cpu_has_vmx_ept_ad_bits())
2734 enable_ept_ad_bits = 0;
2735
3a624e29
NK		 2736 if (!cpu_has_vmx_unrestricted_guest())
2737 enable_unrestricted_guest = 0;
93ba03c2
SY		 2738
2739 if (!cpu_has_vmx_flexpriority())
2740 flexpriority_enabled = 0;
2741
95ba8273
GN		 2742 if (!cpu_has_vmx_tpr_shadow())
2743 kvm_x86_ops->update_cr8_intercept = NULL;
2744
54dee993
MT		 2745 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2746 kvm_disable_largepages();
2747
4b8d54f9
ZE		 2748 if (!cpu_has_vmx_ple())
2749 ple_gap = 0;
2750
b87a51ae
NHE		 2751 if (nested)
2752 nested_vmx_setup_ctls_msrs();
2753
6aa8b732
AK		 2754 return alloc_kvm_area();
2755}
2756
2757static __exit void hardware_unsetup(void)
2758{
2759 free_kvm_area();
2760}
2761
d99e4152
GN		 2762static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg,
2763 struct kvm_segment *save)
6aa8b732 2764{
d99e4152
GN		 2765 if (!emulate_invalid_guest_state) {
2766 /*
2767 * CS and SS RPL should be equal during guest entry according
2768 * to VMX spec, but in reality it is not always so. Since vcpu
2769 * is in the middle of the transition from real mode to
2770 * protected mode it is safe to assume that RPL 0 is a good
2771 * default value.
2772 */
2773 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2774 save->selector &= ~SELECTOR_RPL_MASK;
2775 save->dpl = save->selector & SELECTOR_RPL_MASK;
2776 save->s = 1;
6aa8b732 2777 }
d99e4152 2778 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2779}
2780
2781static void enter_pmode(struct kvm_vcpu *vcpu)
2782{
2783 unsigned long flags;
a89a8fb9 2784 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2785
d99e4152
GN		 2786 /*
2787 * Update real mode segment cache. It may be not up-to-date if sement
2788 * register was written while vcpu was in a guest mode.
2789 */
2790 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2791 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2792 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2793 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2794 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2795 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2796
a89a8fb9 2797 vmx->emulation_required = 1;
7ffd92c5 2798 vmx->rmode.vm86_active = 0;
6aa8b732 2799
2fb92db1
AK		 2800 vmx_segment_cache_clear(vmx);
2801
f5f7b2fe 2802 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2803
2804 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2805 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2806 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2807 vmcs_writel(GUEST_RFLAGS, flags);
2808
66aee91a
RR		 2809 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2810 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2811
2812 update_exception_bitmap(vcpu);
2813
d99e4152
GN		 2814 fix_pmode_dataseg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2815 fix_pmode_dataseg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
f5f7b2fe
AK		 2816 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2817 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2818 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2819 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2820}
2821
d77c26fc 2822static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2823{
bfc6d222 2824 if (!kvm->arch.tss_addr) {
bc6678a3 2825 struct kvm_memslots *slots;
28a37544 2826 struct kvm_memory_slot *slot;
bc6678a3
MT		 2827 gfn_t base_gfn;
2828
90d83dc3 2829 slots = kvm_memslots(kvm);
28a37544
XG		 2830 slot = id_to_memslot(slots, 0);
2831 base_gfn = slot->base_gfn + slot->npages - 3;
2832
cbc94022
IE		 2833 return base_gfn << PAGE_SHIFT;
2834 }
bfc6d222 2835 return kvm->arch.tss_addr;
6aa8b732
AK		 2836}
2837
f5f7b2fe 2838static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2839{
772e0318 2840 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2841 struct kvm_segment var = *save;
2842
2843 var.dpl = 0x3;
2844 if (seg == VCPU_SREG_CS)
2845 var.type = 0x3;
2846
2847 if (!emulate_invalid_guest_state) {
2848 var.selector = var.base >> 4;
2849 var.base = var.base & 0xffff0;
2850 var.limit = 0xffff;
2851 var.g = 0;
2852 var.db = 0;
2853 var.present = 1;
2854 var.s = 1;
2855 var.l = 0;
2856 var.unusable = 0;
2857 var.type = 0x3;
2858 var.avl = 0;
2859 if (save->base & 0xf)
2860 printk_once(KERN_WARNING "kvm: segment base is not "
2861 "paragraph aligned when entering "
2862 "protected mode (seg=%d)", seg);
2863 }
6aa8b732 2864
d99e4152
GN		 2865 vmcs_write16(sf->selector, var.selector);
2866 vmcs_write32(sf->base, var.base);
2867 vmcs_write32(sf->limit, var.limit);
2868 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2869}
2870
2871static void enter_rmode(struct kvm_vcpu *vcpu)
2872{
2873 unsigned long flags;
a89a8fb9 2874 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2875
3a624e29
NK		 2876 if (enable_unrestricted_guest)
2877 return;
2878
f5f7b2fe
AK		 2879 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2880 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2881 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2882 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2883 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2884 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2885 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2886
a89a8fb9 2887 vmx->emulation_required = 1;
7ffd92c5 2888 vmx->rmode.vm86_active = 1;
6aa8b732 2889
776e58ea
GN		 2890 /*
2891 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2892 * vcpu. Call it here with phys address pointing 16M below 4G.
2893 */
2894 if (!vcpu->kvm->arch.tss_addr) {
2895 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2896 "called before entering vcpu\n");
2897 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2898 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2899 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2900 }
2901
2fb92db1
AK		 2902 vmx_segment_cache_clear(vmx);
2903
6aa8b732 2904 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2905 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2906 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2907
2908 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2909 vmx->rmode.save_rflags = flags;
6aa8b732 2910
053de044 2911 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2912
2913 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2914 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2915 update_exception_bitmap(vcpu);
2916
d99e4152
GN		 2917 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2918 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2919 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2920 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2921 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2922 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2923
8668a3c4 2924 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2925}
2926
401d10de
AS		 2927static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2928{
2929 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2930 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2931
2932 if (!msr)
2933 return;
401d10de 2934
44ea2b17
AK		 2935 /*
2936 * Force kernel_gs_base reloading before EFER changes, as control
2937 * of this msr depends on is_long_mode().
2938 */
2939 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2940 vcpu->arch.efer = efer;
401d10de
AS		 2941 if (efer & EFER_LMA) {
2942 vmcs_write32(VM_ENTRY_CONTROLS,
2943 vmcs_read32(VM_ENTRY_CONTROLS) |
2944 VM_ENTRY_IA32E_MODE);
2945 msr->data = efer;
2946 } else {
2947 vmcs_write32(VM_ENTRY_CONTROLS,
2948 vmcs_read32(VM_ENTRY_CONTROLS) &
2949 ~VM_ENTRY_IA32E_MODE);
2950
2951 msr->data = efer & ~EFER_LME;
2952 }
2953 setup_msrs(vmx);
2954}
2955
05b3e0c2 2956#ifdef CONFIG_X86_64
6aa8b732
AK		 2957
2958static void enter_lmode(struct kvm_vcpu *vcpu)
2959{
2960 u32 guest_tr_ar;
2961
2fb92db1
AK		 2962 vmx_segment_cache_clear(to_vmx(vcpu));
2963
6aa8b732
AK		 2964 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2965 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2966 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2967 __func__);
6aa8b732
AK		 2968 vmcs_write32(GUEST_TR_AR_BYTES,
2969 (guest_tr_ar & ~AR_TYPE_MASK)
2970 | AR_TYPE_BUSY_64_TSS);
2971 }
da38f438 2972 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2973}
2974
2975static void exit_lmode(struct kvm_vcpu *vcpu)
2976{
6aa8b732
AK		 2977 vmcs_write32(VM_ENTRY_CONTROLS,
2978 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2979 & ~VM_ENTRY_IA32E_MODE);
da38f438 2980 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2981}
2982
2983#endif
2984
2384d2b3
SY		 2985static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2986{
b9d762fa 2987 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2988 if (enable_ept) {
2989 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2990 return;
4e1096d2 2991 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2992 }
2384d2b3
SY		 2993}
2994
e8467fda
AK		 2995static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2996{
2997 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2998
2999 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3000 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3001}
3002
aff48baa
AK		 3003static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3004{
3005 if (enable_ept && is_paging(vcpu))
3006 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3007 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3008}
3009
25c4c276 3010static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3011{
fc78f519
AK		 3012 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3013
3014 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3015 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3016}
3017
1439442c
SY		 3018static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3019{
6de4f3ad
AK		 3020 if (!test_bit(VCPU_EXREG_PDPTR,
3021 (unsigned long *)&vcpu->arch.regs_dirty))
3022 return;
3023
1439442c 3024 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3025 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3026 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3027 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3028 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3029 }
3030}
3031
8f5d549f
AK		 3032static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3033{
3034 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3035 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3036 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3037 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3038 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3039 }
6de4f3ad
AK		 3040
3041 __set_bit(VCPU_EXREG_PDPTR,
3042 (unsigned long *)&vcpu->arch.regs_avail);
3043 __set_bit(VCPU_EXREG_PDPTR,
3044 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3045}
3046
5e1746d6 3047static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3048
3049static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3050 unsigned long cr0,
3051 struct kvm_vcpu *vcpu)
3052{
5233dd51
MT		 3053 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3054 vmx_decache_cr3(vcpu);
1439442c
SY		 3055 if (!(cr0 & X86_CR0_PG)) {
3056 /* From paging/starting to nonpaging */
3057 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3058 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3059 (CPU_BASED_CR3_LOAD_EXITING |
3060 CPU_BASED_CR3_STORE_EXITING));
3061 vcpu->arch.cr0 = cr0;
fc78f519 3062 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3063 } else if (!is_paging(vcpu)) {
3064 /* From nonpaging to paging */
3065 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3066 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3067 ~(CPU_BASED_CR3_LOAD_EXITING |
3068 CPU_BASED_CR3_STORE_EXITING));
3069 vcpu->arch.cr0 = cr0;
fc78f519 3070 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3071 }
95eb84a7
SY		 3072
3073 if (!(cr0 & X86_CR0_WP))
3074 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3075}
3076
6aa8b732
AK		 3077static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3078{
7ffd92c5 3079 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3080 unsigned long hw_cr0;
3081
3082 if (enable_unrestricted_guest)
3083 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3084 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3085 else
3086 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3087
7ffd92c5 3088 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3089 enter_pmode(vcpu);
3090
7ffd92c5 3091 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3092 enter_rmode(vcpu);
3093
05b3e0c2 3094#ifdef CONFIG_X86_64
f6801dff 3095 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3096 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3097 enter_lmode(vcpu);
707d92fa 3098 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3099 exit_lmode(vcpu);
3100 }
3101#endif
3102
089d034e 3103 if (enable_ept)
1439442c
SY		 3104 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3105
02daab21 3106 if (!vcpu->fpu_active)
81231c69 3107 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3108
6aa8b732 3109 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3110 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3111 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 3112}
3113
1439442c
SY		 3114static u64 construct_eptp(unsigned long root_hpa)
3115{
3116 u64 eptp;
3117
3118 /* TODO write the value reading from MSR */
3119 eptp = VMX_EPT_DEFAULT_MT |
3120 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3121 if (enable_ept_ad_bits)
3122 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3123 eptp |= (root_hpa & PAGE_MASK);
3124
3125 return eptp;
3126}
3127
6aa8b732
AK		 3128static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3129{
1439442c
SY		 3130 unsigned long guest_cr3;
3131 u64 eptp;
3132
3133 guest_cr3 = cr3;
089d034e 3134 if (enable_ept) {
1439442c
SY		 3135 eptp = construct_eptp(cr3);
3136 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3137 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3138 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3139 ept_load_pdptrs(vcpu);
1439442c
SY		 3140 }
3141
2384d2b3 3142 vmx_flush_tlb(vcpu);
1439442c 3143 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3144}
3145
5e1746d6 3146static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3147{
7ffd92c5 3148 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3149 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3150
5e1746d6
NHE		 3151 if (cr4 & X86_CR4_VMXE) {
3152 /*
3153 * To use VMXON (and later other VMX instructions), a guest
3154 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3155 * So basically the check on whether to allow nested VMX
3156 * is here.
3157 */
3158 if (!nested_vmx_allowed(vcpu))
3159 return 1;
3160 } else if (to_vmx(vcpu)->nested.vmxon)
3161 return 1;
3162
ad312c7c 3163 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3164 if (enable_ept) {
3165 if (!is_paging(vcpu)) {
3166 hw_cr4 &= ~X86_CR4_PAE;
3167 hw_cr4 |= X86_CR4_PSE;
3168 } else if (!(cr4 & X86_CR4_PAE)) {
3169 hw_cr4 &= ~X86_CR4_PAE;
3170 }
3171 }
1439442c
SY		 3172
3173 vmcs_writel(CR4_READ_SHADOW, cr4);
3174 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3175 return 0;
6aa8b732
AK		 3176}
3177
6aa8b732
AK		 3178static void vmx_get_segment(struct kvm_vcpu *vcpu,
3179 struct kvm_segment *var, int seg)
3180{
a9179499 3181 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3182 u32 ar;
3183
c6ad1153 3184 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3185 *var = vmx->rmode.segs[seg];
a9179499 3186 if (seg == VCPU_SREG_TR
2fb92db1 3187 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3188 return;
1390a28b
AK		 3189 var->base = vmx_read_guest_seg_base(vmx, seg);
3190 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3191 return;
a9179499 3192 }
2fb92db1
AK		 3193 var->base = vmx_read_guest_seg_base(vmx, seg);
3194 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3195 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3196 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3197 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3198 ar = 0;
3199 var->type = ar & 15;
3200 var->s = (ar >> 4) & 1;
3201 var->dpl = (ar >> 5) & 3;
3202 var->present = (ar >> 7) & 1;
3203 var->avl = (ar >> 12) & 1;
3204 var->l = (ar >> 13) & 1;
3205 var->db = (ar >> 14) & 1;
3206 var->g = (ar >> 15) & 1;
3207 var->unusable = (ar >> 16) & 1;
3208}
3209
a9179499
AK		 3210static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3211{
a9179499
AK		 3212 struct kvm_segment s;
3213
3214 if (to_vmx(vcpu)->rmode.vm86_active) {
3215 vmx_get_segment(vcpu, &s, seg);
3216 return s.base;
3217 }
2fb92db1 3218 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3219}
3220
b09408d0 3221static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3222{
b09408d0
MT		 3223 struct vcpu_vmx *vmx = to_vmx(vcpu);
3224
3eeb3288 3225 if (!is_protmode(vcpu))
2e4d2653
IE		 3226 return 0;
3227
f4c63e5d
AK		 3228 if (!is_long_mode(vcpu)
3229 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3230 return 3;
3231
d881e6f6
AK		 3232 /*
3233 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3234 * fail; use the cache instead.
3235 */
3236 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3237 return vmx->cpl;
3238 }
3239
69c73028
AK		 3240 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3241 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3242 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3243 }
d881e6f6
AK		 3244
3245 return vmx->cpl;
69c73028
AK		 3246}
3247
3248
653e3108 3249static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3250{
6aa8b732
AK		 3251 u32 ar;
3252
f0495f9b 3253 if (var->unusable || !var->present)
6aa8b732
AK		 3254 ar = 1 << 16;
3255 else {
3256 ar = var->type & 15;
3257 ar |= (var->s & 1) << 4;
3258 ar |= (var->dpl & 3) << 5;
3259 ar |= (var->present & 1) << 7;
3260 ar |= (var->avl & 1) << 12;
3261 ar |= (var->l & 1) << 13;
3262 ar |= (var->db & 1) << 14;
3263 ar |= (var->g & 1) << 15;
3264 }
653e3108
AK		 3265
3266 return ar;
3267}
3268
3269static void vmx_set_segment(struct kvm_vcpu *vcpu,
3270 struct kvm_segment *var, int seg)
3271{
7ffd92c5 3272 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3273 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3274
2fb92db1 3275 vmx_segment_cache_clear(vmx);
1ecd50a9 3276 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3277
1ecd50a9
GN		 3278 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3279 vmx->rmode.segs[seg] = *var;
3280 if (seg == VCPU_SREG_TR)
3281 vmcs_write16(sf->selector, var->selector);
3282 else if (var->s)
3283 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3284 goto out;
653e3108 3285 }
1ecd50a9 3286
653e3108
AK		 3287 vmcs_writel(sf->base, var->base);
3288 vmcs_write32(sf->limit, var->limit);
3289 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3290
3291 /*
3292 * Fix the "Accessed" bit in AR field of segment registers for older
3293 * qemu binaries.
3294 * IA32 arch specifies that at the time of processor reset the
3295 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3296 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3297 * state vmexit when "unrestricted guest" mode is turned on.
3298 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3299 * tree. Newer qemu binaries with that qemu fix would not need this
3300 * kvm hack.
3301 */
3302 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3303 var->type |= 0x1; /* Accessed */
3a624e29 3304
f924d66d 3305 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3306
3307out:
3308 if (!vmx->emulation_required)
3309 vmx->emulation_required = !guest_state_valid(vcpu);
6aa8b732
AK		 3310}
3311
6aa8b732
AK		 3312static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3313{
2fb92db1 3314 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3315
3316 *db = (ar >> 14) & 1;
3317 *l = (ar >> 13) & 1;
3318}
3319
89a27f4d 3320static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3321{
89a27f4d
GN		 3322 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3323 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3324}
3325
89a27f4d 3326static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3327{
89a27f4d
GN		 3328 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3329 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3330}
3331
89a27f4d 3332static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3333{
89a27f4d
GN		 3334 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3335 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3336}
3337
89a27f4d 3338static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3339{
89a27f4d
GN		 3340 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3341 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3342}
3343
648dfaa7
MG		 3344static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3345{
3346 struct kvm_segment var;
3347 u32 ar;
3348
3349 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3350 var.dpl = 0x3;
0647f4aa
GN		 3351 if (seg == VCPU_SREG_CS)
3352 var.type = 0x3;
648dfaa7
MG		 3353 ar = vmx_segment_access_rights(&var);
3354
3355 if (var.base != (var.selector << 4))
3356 return false;
89efbed0 3357 if (var.limit != 0xffff)
648dfaa7 3358 return false;
07f42f5f 3359 if (ar != 0xf3)
648dfaa7
MG		 3360 return false;
3361
3362 return true;
3363}
3364
3365static bool code_segment_valid(struct kvm_vcpu *vcpu)
3366{
3367 struct kvm_segment cs;
3368 unsigned int cs_rpl;
3369
3370 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3371 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3372
1872a3f4
AK		 3373 if (cs.unusable)
3374 return false;
648dfaa7
MG		 3375 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3376 return false;
3377 if (!cs.s)
3378 return false;
1872a3f4 3379 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3380 if (cs.dpl > cs_rpl)
3381 return false;
1872a3f4 3382 } else {
648dfaa7
MG		 3383 if (cs.dpl != cs_rpl)
3384 return false;
3385 }
3386 if (!cs.present)
3387 return false;
3388
3389 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3390 return true;
3391}
3392
3393static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3394{
3395 struct kvm_segment ss;
3396 unsigned int ss_rpl;
3397
3398 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3399 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3400
1872a3f4
AK		 3401 if (ss.unusable)
3402 return true;
3403 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3404 return false;
3405 if (!ss.s)
3406 return false;
3407 if (ss.dpl != ss_rpl) /* DPL != RPL */
3408 return false;
3409 if (!ss.present)
3410 return false;
3411
3412 return true;
3413}
3414
3415static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3416{
3417 struct kvm_segment var;
3418 unsigned int rpl;
3419
3420 vmx_get_segment(vcpu, &var, seg);
3421 rpl = var.selector & SELECTOR_RPL_MASK;
3422
1872a3f4
AK		 3423 if (var.unusable)
3424 return true;
648dfaa7
MG		 3425 if (!var.s)
3426 return false;
3427 if (!var.present)
3428 return false;
3429 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3430 if (var.dpl < rpl) /* DPL < RPL */
3431 return false;
3432 }
3433
3434 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3435 * rights flags
3436 */
3437 return true;
3438}
3439
3440static bool tr_valid(struct kvm_vcpu *vcpu)
3441{
3442 struct kvm_segment tr;
3443
3444 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3445
1872a3f4
AK		 3446 if (tr.unusable)
3447 return false;
648dfaa7
MG		 3448 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3449 return false;
1872a3f4 3450 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3451 return false;
3452 if (!tr.present)
3453 return false;
3454
3455 return true;
3456}
3457
3458static bool ldtr_valid(struct kvm_vcpu *vcpu)
3459{
3460 struct kvm_segment ldtr;
3461
3462 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3463
1872a3f4
AK		 3464 if (ldtr.unusable)
3465 return true;
648dfaa7
MG		 3466 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3467 return false;
3468 if (ldtr.type != 2)
3469 return false;
3470 if (!ldtr.present)
3471 return false;
3472
3473 return true;
3474}
3475
3476static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3477{
3478 struct kvm_segment cs, ss;
3479
3480 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3481 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3482
3483 return ((cs.selector & SELECTOR_RPL_MASK) ==
3484 (ss.selector & SELECTOR_RPL_MASK));
3485}
3486
3487/*
3488 * Check if guest state is valid. Returns true if valid, false if
3489 * not.
3490 * We assume that registers are always usable
3491 */
3492static bool guest_state_valid(struct kvm_vcpu *vcpu)
3493{
3494 /* real mode guest state checks */
3eeb3288 3495 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3496 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3497 return false;
3498 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3499 return false;
3500 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3501 return false;
3502 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3503 return false;
3504 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3505 return false;
3506 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3507 return false;
3508 } else {
3509 /* protected mode guest state checks */
3510 if (!cs_ss_rpl_check(vcpu))
3511 return false;
3512 if (!code_segment_valid(vcpu))
3513 return false;
3514 if (!stack_segment_valid(vcpu))
3515 return false;
3516 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3517 return false;
3518 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3519 return false;
3520 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3521 return false;
3522 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3523 return false;
3524 if (!tr_valid(vcpu))
3525 return false;
3526 if (!ldtr_valid(vcpu))
3527 return false;
3528 }
3529 /* TODO:
3530 * - Add checks on RIP
3531 * - Add checks on RFLAGS
3532 */
3533
3534 return true;
3535}
3536
d77c26fc 3537static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3538{
40dcaa9f 3539 gfn_t fn;
195aefde 3540 u16 data = 0;
40dcaa9f 3541 int r, idx, ret = 0;
6aa8b732 3542
40dcaa9f
XG		 3543 idx = srcu_read_lock(&kvm->srcu);
3544 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3545 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3546 if (r < 0)
10589a46 3547 goto out;
195aefde 3548 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3549 r = kvm_write_guest_page(kvm, fn++, &data,
3550 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3551 if (r < 0)
10589a46 3552 goto out;
195aefde
IE		 3553 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3554 if (r < 0)
10589a46 3555 goto out;
195aefde
IE		 3556 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3557 if (r < 0)
10589a46 3558 goto out;
195aefde 3559 data = ~0;
10589a46
MT		 3560 r = kvm_write_guest_page(kvm, fn, &data,
3561 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3562 sizeof(u8));
195aefde 3563 if (r < 0)
10589a46
MT		 3564 goto out;
3565
3566 ret = 1;
3567out:
40dcaa9f 3568 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3569 return ret;
6aa8b732
AK		 3570}
3571
b7ebfb05
SY		 3572static int init_rmode_identity_map(struct kvm *kvm)
3573{
40dcaa9f 3574 int i, idx, r, ret;
b7ebfb05
SY		 3575 pfn_t identity_map_pfn;
3576 u32 tmp;
3577
089d034e 3578 if (!enable_ept)
b7ebfb05
SY		 3579 return 1;
3580 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3581 printk(KERN_ERR "EPT: identity-mapping pagetable "
3582 "haven't been allocated!\n");
3583 return 0;
3584 }
3585 if (likely(kvm->arch.ept_identity_pagetable_done))
3586 return 1;
3587 ret = 0;
b927a3ce 3588 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3589 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3590 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3591 if (r < 0)
3592 goto out;
3593 /* Set up identity-mapping pagetable for EPT in real mode */
3594 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3595 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3596 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3597 r = kvm_write_guest_page(kvm, identity_map_pfn,
3598 &tmp, i * sizeof(tmp), sizeof(tmp));
3599 if (r < 0)
3600 goto out;
3601 }
3602 kvm->arch.ept_identity_pagetable_done = true;
3603 ret = 1;
3604out:
40dcaa9f 3605 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3606 return ret;
3607}
3608
6aa8b732
AK		 3609static void seg_setup(int seg)
3610{
772e0318 3611 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3612 unsigned int ar;
6aa8b732
AK		 3613
3614 vmcs_write16(sf->selector, 0);
3615 vmcs_writel(sf->base, 0);
3616 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3617 ar = 0x93;
3618 if (seg == VCPU_SREG_CS)
3619 ar |= 0x08; /* code segment */
3a624e29
NK		 3620
3621 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3622}
3623
f78e0e2e
SY		 3624static int alloc_apic_access_page(struct kvm *kvm)
3625{
4484141a 3626 struct page *page;
f78e0e2e
SY		 3627 struct kvm_userspace_memory_region kvm_userspace_mem;
3628 int r = 0;
3629
79fac95e 3630 mutex_lock(&kvm->slots_lock);
bfc6d222 3631 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3632 goto out;
3633 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3634 kvm_userspace_mem.flags = 0;
3635 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3636 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3637 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
f78e0e2e
SY		 3638 if (r)
3639 goto out;
72dc67a6 3640
4484141a
XG		 3641 page = gfn_to_page(kvm, 0xfee00);
3642 if (is_error_page(page)) {
3643 r = -EFAULT;
3644 goto out;
3645 }
3646
3647 kvm->arch.apic_access_page = page;
f78e0e2e 3648out:
79fac95e 3649 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3650 return r;
3651}
3652
b7ebfb05
SY		 3653static int alloc_identity_pagetable(struct kvm *kvm)
3654{
4484141a 3655 struct page *page;
b7ebfb05
SY		 3656 struct kvm_userspace_memory_region kvm_userspace_mem;
3657 int r = 0;
3658
79fac95e 3659 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3660 if (kvm->arch.ept_identity_pagetable)
3661 goto out;
3662 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3663 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3664 kvm_userspace_mem.guest_phys_addr =
3665 kvm->arch.ept_identity_map_addr;
b7ebfb05 3666 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3667 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
b7ebfb05
SY		 3668 if (r)
3669 goto out;
3670
4484141a
XG		 3671 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3672 if (is_error_page(page)) {
3673 r = -EFAULT;
3674 goto out;
3675 }
3676
3677 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3678out:
79fac95e 3679 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3680 return r;
3681}
3682
2384d2b3
SY		 3683static void allocate_vpid(struct vcpu_vmx *vmx)
3684{
3685 int vpid;
3686
3687 vmx->vpid = 0;
919818ab 3688 if (!enable_vpid)
2384d2b3
SY		 3689 return;
3690 spin_lock(&vmx_vpid_lock);
3691 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3692 if (vpid < VMX_NR_VPIDS) {
3693 vmx->vpid = vpid;
3694 __set_bit(vpid, vmx_vpid_bitmap);
3695 }
3696 spin_unlock(&vmx_vpid_lock);
3697}
3698
cdbecfc3
LJ		 3699static void free_vpid(struct vcpu_vmx *vmx)
3700{
3701 if (!enable_vpid)
3702 return;
3703 spin_lock(&vmx_vpid_lock);
3704 if (vmx->vpid != 0)
3705 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3706 spin_unlock(&vmx_vpid_lock);
3707}
3708
5897297b 3709static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3710{
3e7c73e9 3711 int f = sizeof(unsigned long);
25c5f225
SY		 3712
3713 if (!cpu_has_vmx_msr_bitmap())
3714 return;
3715
3716 /*
3717 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3718 * have the write-low and read-high bitmap offsets the wrong way round.
3719 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3720 */
25c5f225 3721 if (msr <= 0x1fff) {
3e7c73e9
AK		 3722 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3723 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3724 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3725 msr &= 0x1fff;
3e7c73e9
AK		 3726 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3727 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3728 }
25c5f225
SY		 3729}
3730
5897297b
AK		 3731static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3732{
3733 if (!longmode_only)
3734 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3735 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3736}
3737
a3a8ff8e
NHE		 3738/*
3739 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3740 * will not change in the lifetime of the guest.
3741 * Note that host-state that does change is set elsewhere. E.g., host-state
3742 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3743 */
3744static void vmx_set_constant_host_state(void)
3745{
3746 u32 low32, high32;
3747 unsigned long tmpl;
3748 struct desc_ptr dt;
3749
b1a74bf8 3750 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3751 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3752 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3753
3754 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3755#ifdef CONFIG_X86_64
3756 /*
3757 * Load null selectors, so we can avoid reloading them in
3758 * __vmx_load_host_state(), in case userspace uses the null selectors
3759 * too (the expected case).
3760 */
3761 vmcs_write16(HOST_DS_SELECTOR, 0);
3762 vmcs_write16(HOST_ES_SELECTOR, 0);
3763#else
a3a8ff8e
NHE		 3764 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3765 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3766#endif
a3a8ff8e
NHE		 3767 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3768 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3769
3770 native_store_idt(&dt);
3771 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3772
83287ea4 3773 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3774
3775 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3776 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3777 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3778 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3779
3780 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3781 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3782 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3783 }
3784}
3785
bf8179a0
NHE		 3786static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3787{
3788 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3789 if (enable_ept)
3790 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3791 if (is_guest_mode(&vmx->vcpu))
3792 vmx->vcpu.arch.cr4_guest_owned_bits &=
3793 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3794 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3795}
3796
3797static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3798{
3799 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3800 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3801 exec_control &= ~CPU_BASED_TPR_SHADOW;
3802#ifdef CONFIG_X86_64
3803 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3804 CPU_BASED_CR8_LOAD_EXITING;
3805#endif
3806 }
3807 if (!enable_ept)
3808 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3809 CPU_BASED_CR3_LOAD_EXITING |
3810 CPU_BASED_INVLPG_EXITING;
3811 return exec_control;
3812}
3813
3814static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3815{
3816 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3817 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3818 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3819 if (vmx->vpid == 0)
3820 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3821 if (!enable_ept) {
3822 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3823 enable_unrestricted_guest = 0;
ad756a16
MJ		 3824 /* Enable INVPCID for non-ept guests may cause performance regression. */
3825 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3826 }
3827 if (!enable_unrestricted_guest)
3828 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3829 if (!ple_gap)
3830 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3831 return exec_control;
3832}
3833
ce88decf
XG		 3834static void ept_set_mmio_spte_mask(void)
3835{
3836 /*
3837 * EPT Misconfigurations can be generated if the value of bits 2:0
3838 * of an EPT paging-structure entry is 110b (write/execute).
3839 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3840 * spte.
3841 */
3842 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3843}
3844
6aa8b732
AK		 3845/*
3846 * Sets up the vmcs for emulated real mode.
3847 */
8b9cf98c 3848static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3849{
2e4ce7f5 3850#ifdef CONFIG_X86_64
6aa8b732 3851 unsigned long a;
2e4ce7f5 3852#endif
6aa8b732 3853 int i;
6aa8b732 3854
6aa8b732 3855 /* I/O */
3e7c73e9
AK		 3856 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3857 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3858
25c5f225 3859 if (cpu_has_vmx_msr_bitmap())
5897297b 3860 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3861
6aa8b732
AK		 3862 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3863
6aa8b732 3864 /* Control */
1c3d14fe
YS		 3865 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3866 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3867
bf8179a0 3868 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3869
83ff3b9d 3870 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3871 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3872 vmx_secondary_exec_control(vmx));
83ff3b9d 3873 }
f78e0e2e 3874
4b8d54f9
ZE		 3875 if (ple_gap) {
3876 vmcs_write32(PLE_GAP, ple_gap);
3877 vmcs_write32(PLE_WINDOW, ple_window);
3878 }
3879
c3707958
XG		 3880 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3881 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3882 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3883
9581d442
AK		 3884 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3885 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3886 vmx_set_constant_host_state();
05b3e0c2 3887#ifdef CONFIG_X86_64
6aa8b732
AK		 3888 rdmsrl(MSR_FS_BASE, a);
3889 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3890 rdmsrl(MSR_GS_BASE, a);
3891 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3892#else
3893 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3894 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3895#endif
3896
2cc51560
ED		 3897 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3898 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3899 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3900 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3901 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3902
468d472f 3903 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3904 u32 msr_low, msr_high;
3905 u64 host_pat;
468d472f
SY		 3906 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3907 host_pat = msr_low | ((u64) msr_high << 32);
3908 /* Write the default value follow host pat */
3909 vmcs_write64(GUEST_IA32_PAT, host_pat);
3910 /* Keep arch.pat sync with GUEST_IA32_PAT */
3911 vmx->vcpu.arch.pat = host_pat;
3912 }
3913
6aa8b732
AK		 3914 for (i = 0; i < NR_VMX_MSR; ++i) {
3915 u32 index = vmx_msr_index[i];
3916 u32 data_low, data_high;
a2fa3e9f 3917 int j = vmx->nmsrs;
6aa8b732
AK		 3918
3919 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3920 continue;
432bd6cb
AK		 3921 if (wrmsr_safe(index, data_low, data_high) < 0)
3922 continue;
26bb0981
AK		 3923 vmx->guest_msrs[j].index = i;
3924 vmx->guest_msrs[j].data = 0;
d5696725 3925 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3926 ++vmx->nmsrs;
6aa8b732 3927 }
6aa8b732 3928
1c3d14fe 3929 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3930
3931 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3932 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3933
e00c8cf2 3934 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3935 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 3936
3937 return 0;
3938}
3939
3940static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3941{
3942 struct vcpu_vmx *vmx = to_vmx(vcpu);
3943 u64 msr;
4b9d3a04 3944 int ret;
e00c8cf2 3945
7ffd92c5 3946 vmx->rmode.vm86_active = 0;
e00c8cf2 3947
3b86cd99
JK		 3948 vmx->soft_vnmi_blocked = 0;
3949
ad312c7c 3950 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3951 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3952 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3953 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3954 msr |= MSR_IA32_APICBASE_BSP;
3955 kvm_set_apic_base(&vmx->vcpu, msr);
3956
2fb92db1
AK		 3957 vmx_segment_cache_clear(vmx);
3958
5706be0d 3959 seg_setup(VCPU_SREG_CS);
d54d07b2 3960 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2 3961 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
d54d07b2 3962 else {
ad312c7c
ZX		 3963 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3964 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3965 }
e00c8cf2
AK		 3966
3967 seg_setup(VCPU_SREG_DS);
3968 seg_setup(VCPU_SREG_ES);
3969 seg_setup(VCPU_SREG_FS);
3970 seg_setup(VCPU_SREG_GS);
3971 seg_setup(VCPU_SREG_SS);
3972
3973 vmcs_write16(GUEST_TR_SELECTOR, 0);
3974 vmcs_writel(GUEST_TR_BASE, 0);
3975 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3976 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3977
3978 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3979 vmcs_writel(GUEST_LDTR_BASE, 0);
3980 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3981 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3982
3983 vmcs_write32(GUEST_SYSENTER_CS, 0);
3984 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3985 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3986
3987 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3988 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3989 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3990 else
5fdbf976 3991 kvm_rip_write(vcpu, 0);
e00c8cf2 3992
e00c8cf2
AK		 3993 vmcs_writel(GUEST_GDTR_BASE, 0);
3994 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3995
3996 vmcs_writel(GUEST_IDTR_BASE, 0);
3997 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3998
443381a8 3999 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4000 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4001 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4002
e00c8cf2
AK		 4003 /* Special registers */
4004 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4005
4006 setup_msrs(vmx);
4007
6aa8b732
AK		 4008 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4009
f78e0e2e
SY		 4010 if (cpu_has_vmx_tpr_shadow()) {
4011 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4012 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4013 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4014 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4015 vmcs_write32(TPR_THRESHOLD, 0);
4016 }
4017
4018 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4019 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4020 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4021
2384d2b3
SY		 4022 if (vmx->vpid != 0)
4023 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4024
fa40052c 4025 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4026 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4027 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4028 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4029 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4030 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4031 vmx_fpu_activate(&vmx->vcpu);
4032 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4033
b9d762fa 4034 vpid_sync_context(vmx);
2384d2b3 4035
3200f405 4036 ret = 0;
6aa8b732 4037
a89a8fb9
MG		 4038 /* HACK: Don't enable emulation on guest boot/reset */
4039 vmx->emulation_required = 0;
4040
6aa8b732
AK		 4041 return ret;
4042}
4043
b6f1250e
NHE		 4044/*
4045 * In nested virtualization, check if L1 asked to exit on external interrupts.
4046 * For most existing hypervisors, this will always return true.
4047 */
4048static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4049{
4050 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4051 PIN_BASED_EXT_INTR_MASK;
4052}
4053
3b86cd99
JK		 4054static void enable_irq_window(struct kvm_vcpu *vcpu)
4055{
4056 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4057 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4058 /*
4059 * We get here if vmx_interrupt_allowed() said we can't
4060 * inject to L1 now because L2 must run. Ask L2 to exit
4061 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4062 */
d6185f20 4063 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4064 return;
d6185f20 4065 }
3b86cd99
JK		 4066
4067 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4068 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4069 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4070}
4071
4072static void enable_nmi_window(struct kvm_vcpu *vcpu)
4073{
4074 u32 cpu_based_vm_exec_control;
4075
4076 if (!cpu_has_virtual_nmis()) {
4077 enable_irq_window(vcpu);
4078 return;
4079 }
4080
30bd0c4c
AK		 4081 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4082 enable_irq_window(vcpu);
4083 return;
4084 }
3b86cd99
JK		 4085 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4086 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4087 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4088}
4089
66fd3f7f 4090static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4091{
9c8cba37 4092 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4093 uint32_t intr;
4094 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4095
229456fc 4096 trace_kvm_inj_virq(irq);
2714d1d3 4097
fa89a817 4098 ++vcpu->stat.irq_injections;
7ffd92c5 4099 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4100 int inc_eip = 0;
4101 if (vcpu->arch.interrupt.soft)
4102 inc_eip = vcpu->arch.event_exit_inst_len;
4103 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4104 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4105 return;
4106 }
66fd3f7f
GN		 4107 intr = irq | INTR_INFO_VALID_MASK;
4108 if (vcpu->arch.interrupt.soft) {
4109 intr |= INTR_TYPE_SOFT_INTR;
4110 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4111 vmx->vcpu.arch.event_exit_inst_len);
4112 } else
4113 intr |= INTR_TYPE_EXT_INTR;
4114 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4115}
4116
f08864b4
SY		 4117static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4118{
66a5a347
JK		 4119 struct vcpu_vmx *vmx = to_vmx(vcpu);
4120
0b6ac343
NHE		 4121 if (is_guest_mode(vcpu))
4122 return;
4123
3b86cd99
JK		 4124 if (!cpu_has_virtual_nmis()) {
4125 /*
4126 * Tracking the NMI-blocked state in software is built upon
4127 * finding the next open IRQ window. This, in turn, depends on
4128 * well-behaving guests: They have to keep IRQs disabled at
4129 * least as long as the NMI handler runs. Otherwise we may
4130 * cause NMI nesting, maybe breaking the guest. But as this is
4131 * highly unlikely, we can live with the residual risk.
4132 */
4133 vmx->soft_vnmi_blocked = 1;
4134 vmx->vnmi_blocked_time = 0;
4135 }
4136
487b391d 4137 ++vcpu->stat.nmi_injections;
9d58b931 4138 vmx->nmi_known_unmasked = false;
7ffd92c5 4139 if (vmx->rmode.vm86_active) {
71f9833b 4140 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4141 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4142 return;
4143 }
f08864b4
SY		 4144 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4145 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4146}
4147
c4282df9 4148static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4149{
3b86cd99 4150 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4151 return 0;
33f089ca 4152
c4282df9 4153 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4154 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4155 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4156}
4157
3cfc3092
JK		 4158static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4159{
4160 if (!cpu_has_virtual_nmis())
4161 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4162 if (to_vmx(vcpu)->nmi_known_unmasked)
4163 return false;
c332c83a 4164 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4165}
4166
4167static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4168{
4169 struct vcpu_vmx *vmx = to_vmx(vcpu);
4170
4171 if (!cpu_has_virtual_nmis()) {
4172 if (vmx->soft_vnmi_blocked != masked) {
4173 vmx->soft_vnmi_blocked = masked;
4174 vmx->vnmi_blocked_time = 0;
4175 }
4176 } else {
9d58b931 4177 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4178 if (masked)
4179 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4180 GUEST_INTR_STATE_NMI);
4181 else
4182 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4183 GUEST_INTR_STATE_NMI);
4184 }
4185}
4186
78646121
GN		 4187static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4188{
b6f1250e 4189 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4190 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4191 if (to_vmx(vcpu)->nested.nested_run_pending ||
4192 (vmcs12->idt_vectoring_info_field &
4193 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4194 return 0;
4195 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4196 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4197 vmcs12->vm_exit_intr_info = 0;
4198 /* fall through to normal code, but now in L1, not L2 */
4199 }
4200
c4282df9
GN		 4201 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4202 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4203 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4204}
4205
cbc94022
IE		 4206static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4207{
4208 int ret;
4209 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4210 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4211 .guest_phys_addr = addr,
4212 .memory_size = PAGE_SIZE * 3,
4213 .flags = 0,
4214 };
4215
f82a8cfe 4216 ret = kvm_set_memory_region(kvm, &tss_mem, false);
cbc94022
IE		 4217 if (ret)
4218 return ret;
bfc6d222 4219 kvm->arch.tss_addr = addr;
93ea5388
GN		 4220 if (!init_rmode_tss(kvm))
4221 return -ENOMEM;
4222
cbc94022
IE		 4223 return 0;
4224}
4225
0ca1b4f4 4226static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4227{
77ab6db0 4228 switch (vec) {
77ab6db0 4229 case BP_VECTOR:
c573cd22
JK		 4230 /*
4231 * Update instruction length as we may reinject the exception
4232 * from user space while in guest debugging mode.
4233 */
4234 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4235 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4236 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4237 return false;
4238 /* fall through */
4239 case DB_VECTOR:
4240 if (vcpu->guest_debug &
4241 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4242 return false;
d0bfb940
JK		 4243 /* fall through */
4244 case DE_VECTOR:
77ab6db0
JK		 4245 case OF_VECTOR:
4246 case BR_VECTOR:
4247 case UD_VECTOR:
4248 case DF_VECTOR:
4249 case SS_VECTOR:
4250 case GP_VECTOR:
4251 case MF_VECTOR:
0ca1b4f4
GN		 4252 return true;
4253 break;
77ab6db0 4254 }
0ca1b4f4
GN		 4255 return false;
4256}
4257
4258static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4259 int vec, u32 err_code)
4260{
4261 /*
4262 * Instruction with address size override prefix opcode 0x67
4263 * Cause the #SS fault with 0 error code in VM86 mode.
4264 */
4265 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4266 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4267 if (vcpu->arch.halt_request) {
4268 vcpu->arch.halt_request = 0;
4269 return kvm_emulate_halt(vcpu);
4270 }
4271 return 1;
4272 }
4273 return 0;
4274 }
4275
4276 /*
4277 * Forward all other exceptions that are valid in real mode.
4278 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4279 * the required debugging infrastructure rework.
4280 */
4281 kvm_queue_exception(vcpu, vec);
4282 return 1;
6aa8b732
AK		 4283}
4284
a0861c02
AK		 4285/*
4286 * Trigger machine check on the host. We assume all the MSRs are already set up
4287 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4288 * We pass a fake environment to the machine check handler because we want
4289 * the guest to be always treated like user space, no matter what context
4290 * it used internally.
4291 */
4292static void kvm_machine_check(void)
4293{
4294#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4295 struct pt_regs regs = {
4296 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4297 .flags = X86_EFLAGS_IF,
4298 };
4299
4300 do_machine_check(&regs, 0);
4301#endif
4302}
4303
851ba692 4304static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4305{
4306 /* already handled by vcpu_run */
4307 return 1;
4308}
4309
851ba692 4310static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4311{
1155f76a 4312 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4313 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4314 u32 intr_info, ex_no, error_code;
42dbaa5a 4315 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4316 u32 vect_info;
4317 enum emulation_result er;
4318
1155f76a 4319 vect_info = vmx->idt_vectoring_info;
88786475 4320 intr_info = vmx->exit_intr_info;
6aa8b732 4321
a0861c02 4322 if (is_machine_check(intr_info))
851ba692 4323 return handle_machine_check(vcpu);
a0861c02 4324
e4a41889 4325 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4326 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4327
4328 if (is_no_device(intr_info)) {
5fd86fcf 4329 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4330 return 1;
4331 }
4332
7aa81cc0 4333 if (is_invalid_opcode(intr_info)) {
51d8b661 4334 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4335 if (er != EMULATE_DONE)
7ee5d940 4336 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4337 return 1;
4338 }
4339
6aa8b732 4340 error_code = 0;
2e11384c 4341 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4342 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4343
4344 /*
4345 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4346 * MMIO, it is better to report an internal error.
4347 * See the comments in vmx_handle_exit.
4348 */
4349 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4350 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4351 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4352 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4353 vcpu->run->internal.ndata = 2;
4354 vcpu->run->internal.data[0] = vect_info;
4355 vcpu->run->internal.data[1] = intr_info;
4356 return 0;
4357 }
4358
6aa8b732 4359 if (is_page_fault(intr_info)) {
1439442c 4360 /* EPT won't cause page fault directly */
cf3ace79 4361 BUG_ON(enable_ept);
6aa8b732 4362 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4363 trace_kvm_page_fault(cr2, error_code);
4364
3298b75c 4365 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4366 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4367 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4368 }
4369
d0bfb940 4370 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4371
4372 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4373 return handle_rmode_exception(vcpu, ex_no, error_code);
4374
42dbaa5a
JK		 4375 switch (ex_no) {
4376 case DB_VECTOR:
4377 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4378 if (!(vcpu->guest_debug &
4379 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4380 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4381 kvm_queue_exception(vcpu, DB_VECTOR);
4382 return 1;
4383 }
4384 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4385 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4386 /* fall through */
4387 case BP_VECTOR:
c573cd22
JK		 4388 /*
4389 * Update instruction length as we may reinject #BP from
4390 * user space while in guest debugging mode. Reading it for
4391 * #DB as well causes no harm, it is not used in that case.
4392 */
4393 vmx->vcpu.arch.event_exit_inst_len =
4394 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4395 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4396 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4397 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4398 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4399 break;
4400 default:
d0bfb940
JK		 4401 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4402 kvm_run->ex.exception = ex_no;
4403 kvm_run->ex.error_code = error_code;
42dbaa5a 4404 break;
6aa8b732 4405 }
6aa8b732
AK		 4406 return 0;
4407}
4408
851ba692 4409static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4410{
1165f5fe 4411 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4412 return 1;
4413}
4414
851ba692 4415static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4416{
851ba692 4417 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4418 return 0;
4419}
6aa8b732 4420
851ba692 4421static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4422{
bfdaab09 4423 unsigned long exit_qualification;
34c33d16 4424 int size, in, string;
039576c0 4425 unsigned port;
6aa8b732 4426
bfdaab09 4427 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4428 string = (exit_qualification & 16) != 0;
cf8f70bf 4429 in = (exit_qualification & 8) != 0;
e70669ab 4430
cf8f70bf 4431 ++vcpu->stat.io_exits;
e70669ab 4432
cf8f70bf 4433 if (string || in)
51d8b661 4434 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4435
cf8f70bf
GN		 4436 port = exit_qualification >> 16;
4437 size = (exit_qualification & 7) + 1;
e93f36bc 4438 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4439
4440 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4441}
4442
102d8325
IM		 4443static void
4444vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4445{
4446 /*
4447 * Patch in the VMCALL instruction:
4448 */
4449 hypercall[0] = 0x0f;
4450 hypercall[1] = 0x01;
4451 hypercall[2] = 0xc1;
102d8325
IM		 4452}
4453
0fa06071 4454/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4455static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4456{
4457 if (to_vmx(vcpu)->nested.vmxon &&
4458 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4459 return 1;
4460
4461 if (is_guest_mode(vcpu)) {
4462 /*
4463 * We get here when L2 changed cr0 in a way that did not change
4464 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4465 * but did change L0 shadowed bits. This can currently happen
4466 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4467 * loading) while pretending to allow the guest to change it.
4468 */
4469 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4470 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4471 return 1;
4472 vmcs_writel(CR0_READ_SHADOW, val);
4473 return 0;
4474 } else
4475 return kvm_set_cr0(vcpu, val);
4476}
4477
4478static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4479{
4480 if (is_guest_mode(vcpu)) {
4481 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4482 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4483 return 1;
4484 vmcs_writel(CR4_READ_SHADOW, val);
4485 return 0;
4486 } else
4487 return kvm_set_cr4(vcpu, val);
4488}
4489
4490/* called to set cr0 as approriate for clts instruction exit. */
4491static void handle_clts(struct kvm_vcpu *vcpu)
4492{
4493 if (is_guest_mode(vcpu)) {
4494 /*
4495 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4496 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4497 * just pretend it's off (also in arch.cr0 for fpu_activate).
4498 */
4499 vmcs_writel(CR0_READ_SHADOW,
4500 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4501 vcpu->arch.cr0 &= ~X86_CR0_TS;
4502 } else
4503 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4504}
4505
851ba692 4506static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4507{
229456fc 4508 unsigned long exit_qualification, val;
6aa8b732
AK		 4509 int cr;
4510 int reg;
49a9b07e 4511 int err;
6aa8b732 4512
bfdaab09 4513 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4514 cr = exit_qualification & 15;
4515 reg = (exit_qualification >> 8) & 15;
4516 switch ((exit_qualification >> 4) & 3) {
4517 case 0: /* mov to cr */
229456fc
MT		 4518 val = kvm_register_read(vcpu, reg);
4519 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4520 switch (cr) {
4521 case 0:
eeadf9e7 4522 err = handle_set_cr0(vcpu, val);
db8fcefa 4523 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4524 return 1;
4525 case 3:
2390218b 4526 err = kvm_set_cr3(vcpu, val);
db8fcefa 4527 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4528 return 1;
4529 case 4:
eeadf9e7 4530 err = handle_set_cr4(vcpu, val);
db8fcefa 4531 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4532 return 1;
0a5fff19
GN		 4533 case 8: {
4534 u8 cr8_prev = kvm_get_cr8(vcpu);
4535 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4536 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4537 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4538 if (irqchip_in_kernel(vcpu->kvm))
4539 return 1;
4540 if (cr8_prev <= cr8)
4541 return 1;
851ba692 4542 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4543 return 0;
4544 }
4b8073e4 4545 }
6aa8b732 4546 break;
25c4c276 4547 case 2: /* clts */
eeadf9e7 4548 handle_clts(vcpu);
4d4ec087 4549 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4550 skip_emulated_instruction(vcpu);
6b52d186 4551 vmx_fpu_activate(vcpu);
25c4c276 4552 return 1;
6aa8b732
AK		 4553 case 1: /*mov from cr*/
4554 switch (cr) {
4555 case 3:
9f8fe504
AK		 4556 val = kvm_read_cr3(vcpu);
4557 kvm_register_write(vcpu, reg, val);
4558 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4559 skip_emulated_instruction(vcpu);
4560 return 1;
4561 case 8:
229456fc
MT		 4562 val = kvm_get_cr8(vcpu);
4563 kvm_register_write(vcpu, reg, val);
4564 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4565 skip_emulated_instruction(vcpu);
4566 return 1;
4567 }
4568 break;
4569 case 3: /* lmsw */
a1f83a74 4570 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4571 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4572 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4573
4574 skip_emulated_instruction(vcpu);
4575 return 1;
4576 default:
4577 break;
4578 }
851ba692 4579 vcpu->run->exit_reason = 0;
a737f256 4580 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4581 (int)(exit_qualification >> 4) & 3, cr);
4582 return 0;
4583}
4584
851ba692 4585static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4586{
bfdaab09 4587 unsigned long exit_qualification;
6aa8b732
AK		 4588 int dr, reg;
4589
f2483415 4590 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4591 if (!kvm_require_cpl(vcpu, 0))
4592 return 1;
42dbaa5a
JK		 4593 dr = vmcs_readl(GUEST_DR7);
4594 if (dr & DR7_GD) {
4595 /*
4596 * As the vm-exit takes precedence over the debug trap, we
4597 * need to emulate the latter, either for the host or the
4598 * guest debugging itself.
4599 */
4600 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4601 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4602 vcpu->run->debug.arch.dr7 = dr;
4603 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4604 vmcs_readl(GUEST_CS_BASE) +
4605 vmcs_readl(GUEST_RIP);
851ba692
AK		 4606 vcpu->run->debug.arch.exception = DB_VECTOR;
4607 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4608 return 0;
4609 } else {
4610 vcpu->arch.dr7 &= ~DR7_GD;
4611 vcpu->arch.dr6 |= DR6_BD;
4612 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4613 kvm_queue_exception(vcpu, DB_VECTOR);
4614 return 1;
4615 }
4616 }
4617
bfdaab09 4618 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4619 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4620 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4621 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4622 unsigned long val;
4623 if (!kvm_get_dr(vcpu, dr, &val))
4624 kvm_register_write(vcpu, reg, val);
4625 } else
4626 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4627 skip_emulated_instruction(vcpu);
4628 return 1;
4629}
4630
020df079
GN		 4631static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4632{
4633 vmcs_writel(GUEST_DR7, val);
4634}
4635
851ba692 4636static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4637{
06465c5a
AK		 4638 kvm_emulate_cpuid(vcpu);
4639 return 1;
6aa8b732
AK		 4640}
4641
851ba692 4642static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4643{
ad312c7c 4644 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4645 u64 data;
4646
4647 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4648 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4649 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4650 return 1;
4651 }
4652
229456fc 4653 trace_kvm_msr_read(ecx, data);
2714d1d3 4654
6aa8b732 4655 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4656 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4657 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4658 skip_emulated_instruction(vcpu);
4659 return 1;
4660}
4661
851ba692 4662static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4663{
8fe8ab46 4664 struct msr_data msr;
ad312c7c
ZX		 4665 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4666 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4667 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4668
8fe8ab46
WA		 4669 msr.data = data;
4670 msr.index = ecx;
4671 msr.host_initiated = false;
4672 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4673 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4674 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4675 return 1;
4676 }
4677
59200273 4678 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4679 skip_emulated_instruction(vcpu);
4680 return 1;
4681}
4682
851ba692 4683static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4684{
3842d135 4685 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4686 return 1;
4687}
4688
851ba692 4689static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4690{
85f455f7
ED		 4691 u32 cpu_based_vm_exec_control;
4692
4693 /* clear pending irq */
4694 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4695 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4696 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4697
3842d135
AK		 4698 kvm_make_request(KVM_REQ_EVENT, vcpu);
4699
a26bf12a 4700 ++vcpu->stat.irq_window_exits;
2714d1d3 4701
c1150d8c
DL		 4702 /*
4703 * If the user space waits to inject interrupts, exit as soon as
4704 * possible
4705 */
8061823a 4706 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4707 vcpu->run->request_interrupt_window &&
8061823a 4708 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4709 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4710 return 0;
4711 }
6aa8b732
AK		 4712 return 1;
4713}
4714
851ba692 4715static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4716{
4717 skip_emulated_instruction(vcpu);
d3bef15f 4718 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4719}
4720
851ba692 4721static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4722{
510043da 4723 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4724 kvm_emulate_hypercall(vcpu);
4725 return 1;
c21415e8
IM		 4726}
4727
ec25d5e6
GN		 4728static int handle_invd(struct kvm_vcpu *vcpu)
4729{
51d8b661 4730 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4731}
4732
851ba692 4733static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4734{
f9c617f6 4735 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4736
4737 kvm_mmu_invlpg(vcpu, exit_qualification);
4738 skip_emulated_instruction(vcpu);
4739 return 1;
4740}
4741
fee84b07
AK		 4742static int handle_rdpmc(struct kvm_vcpu *vcpu)
4743{
4744 int err;
4745
4746 err = kvm_rdpmc(vcpu);
4747 kvm_complete_insn_gp(vcpu, err);
4748
4749 return 1;
4750}
4751
851ba692 4752static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4753{
4754 skip_emulated_instruction(vcpu);
f5f48ee1 4755 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4756 return 1;
4757}
4758
2acf923e
DC		 4759static int handle_xsetbv(struct kvm_vcpu *vcpu)
4760{
4761 u64 new_bv = kvm_read_edx_eax(vcpu);
4762 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4763
4764 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4765 skip_emulated_instruction(vcpu);
4766 return 1;
4767}
4768
851ba692 4769static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4770{
58fbbf26
KT		 4771 if (likely(fasteoi)) {
4772 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4773 int access_type, offset;
4774
4775 access_type = exit_qualification & APIC_ACCESS_TYPE;
4776 offset = exit_qualification & APIC_ACCESS_OFFSET;
4777 /*
4778 * Sane guest uses MOV to write EOI, with written value
4779 * not cared. So make a short-circuit here by avoiding
4780 * heavy instruction emulation.
4781 */
4782 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4783 (offset == APIC_EOI)) {
4784 kvm_lapic_set_eoi(vcpu);
4785 skip_emulated_instruction(vcpu);
4786 return 1;
4787 }
4788 }
51d8b661 4789 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4790}
4791
851ba692 4792static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4793{
60637aac 4794 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4795 unsigned long exit_qualification;
e269fb21
JK		 4796 bool has_error_code = false;
4797 u32 error_code = 0;
37817f29 4798 u16 tss_selector;
7f3d35fd 4799 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4800
4801 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4802 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4803 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4804
4805 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4806
4807 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4808 if (reason == TASK_SWITCH_GATE && idt_v) {
4809 switch (type) {
4810 case INTR_TYPE_NMI_INTR:
4811 vcpu->arch.nmi_injected = false;
654f06fc 4812 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4813 break;
4814 case INTR_TYPE_EXT_INTR:
66fd3f7f 4815 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4816 kvm_clear_interrupt_queue(vcpu);
4817 break;
4818 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4819 if (vmx->idt_vectoring_info &
4820 VECTORING_INFO_DELIVER_CODE_MASK) {
4821 has_error_code = true;
4822 error_code =
4823 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4824 }
4825 /* fall through */
64a7ec06
GN		 4826 case INTR_TYPE_SOFT_EXCEPTION:
4827 kvm_clear_exception_queue(vcpu);
4828 break;
4829 default:
4830 break;
4831 }
60637aac 4832 }
37817f29
IE		 4833 tss_selector = exit_qualification;
4834
64a7ec06
GN		 4835 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4836 type != INTR_TYPE_EXT_INTR &&
4837 type != INTR_TYPE_NMI_INTR))
4838 skip_emulated_instruction(vcpu);
4839
7f3d35fd
KW		 4840 if (kvm_task_switch(vcpu, tss_selector,
4841 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4842 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4843 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4844 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4845 vcpu->run->internal.ndata = 0;
42dbaa5a 4846 return 0;
acb54517 4847 }
42dbaa5a
JK		 4848
4849 /* clear all local breakpoint enable flags */
4850 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4851
4852 /*
4853 * TODO: What about debug traps on tss switch?
4854 * Are we supposed to inject them and update dr6?
4855 */
4856
4857 return 1;
37817f29
IE		 4858}
4859
851ba692 4860static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4861{
f9c617f6 4862 unsigned long exit_qualification;
1439442c 4863 gpa_t gpa;
4f5982a5 4864 u32 error_code;
1439442c 4865 int gla_validity;
1439442c 4866
f9c617f6 4867 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 4868
1439442c
SY		 4869 gla_validity = (exit_qualification >> 7) & 0x3;
4870 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4871 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4872 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4873 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4874 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4875 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4876 (long unsigned int)exit_qualification);
851ba692
AK		 4877 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4878 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4879 return 0;
1439442c
SY		 4880 }
4881
4882 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4883 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4884
4885 /* It is a write fault? */
4886 error_code = exit_qualification & (1U << 1);
4887 /* ept page table is present? */
4888 error_code |= (exit_qualification >> 3) & 0x1;
4889
4890 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4891}
4892
68f89400
MT		 4893static u64 ept_rsvd_mask(u64 spte, int level)
4894{
4895 int i;
4896 u64 mask = 0;
4897
4898 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4899 mask |= (1ULL << i);
4900
4901 if (level > 2)
4902 /* bits 7:3 reserved */
4903 mask |= 0xf8;
4904 else if (level == 2) {
4905 if (spte & (1ULL << 7))
4906 /* 2MB ref, bits 20:12 reserved */
4907 mask |= 0x1ff000;
4908 else
4909 /* bits 6:3 reserved */
4910 mask |= 0x78;
4911 }
4912
4913 return mask;
4914}
4915
4916static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4917 int level)
4918{
4919 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4920
4921 /* 010b (write-only) */
4922 WARN_ON((spte & 0x7) == 0x2);
4923
4924 /* 110b (write/execute) */
4925 WARN_ON((spte & 0x7) == 0x6);
4926
4927 /* 100b (execute-only) and value not supported by logical processor */
4928 if (!cpu_has_vmx_ept_execute_only())
4929 WARN_ON((spte & 0x7) == 0x4);
4930
4931 /* not 000b */
4932 if ((spte & 0x7)) {
4933 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4934
4935 if (rsvd_bits != 0) {
4936 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4937 __func__, rsvd_bits);
4938 WARN_ON(1);
4939 }
4940
4941 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4942 u64 ept_mem_type = (spte & 0x38) >> 3;
4943
4944 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4945 ept_mem_type == 7) {
4946 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4947 __func__, ept_mem_type);
4948 WARN_ON(1);
4949 }
4950 }
4951 }
4952}
4953
851ba692 4954static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4955{
4956 u64 sptes[4];
ce88decf 4957 int nr_sptes, i, ret;
68f89400
MT		 4958 gpa_t gpa;
4959
4960 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4961
ce88decf
XG		 4962 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4963 if (likely(ret == 1))
4964 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4965 EMULATE_DONE;
4966 if (unlikely(!ret))
4967 return 1;
4968
4969 /* It is the real ept misconfig */
68f89400
MT		 4970 printk(KERN_ERR "EPT: Misconfiguration.\n");
4971 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4972
4973 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4974
4975 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4976 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4977
851ba692
AK		 4978 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4979 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4980
4981 return 0;
4982}
4983
851ba692 4984static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4985{
4986 u32 cpu_based_vm_exec_control;
4987
4988 /* clear pending NMI */
4989 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4990 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4991 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4992 ++vcpu->stat.nmi_window_exits;
3842d135 4993 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4994
4995 return 1;
4996}
4997
80ced186 4998static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4999{
8b3079a5
AK		 5000 struct vcpu_vmx *vmx = to_vmx(vcpu);
5001 enum emulation_result err = EMULATE_DONE;
80ced186 5002 int ret = 1;
49e9d557
AK		 5003 u32 cpu_exec_ctrl;
5004 bool intr_window_requested;
b8405c18 5005 unsigned count = 130;
49e9d557
AK		 5006
5007 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5008 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5009
b8405c18 5010 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5011 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5012 return handle_interrupt_window(&vmx->vcpu);
5013
de87dcdd
AK		 5014 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5015 return 1;
5016
51d8b661 5017 err = emulate_instruction(vcpu, 0);
ea953ef0 5018
80ced186
MG		 5019 if (err == EMULATE_DO_MMIO) {
5020 ret = 0;
5021 goto out;
5022 }
1d5a4d9b 5023
de5f70e0
AK		 5024 if (err != EMULATE_DONE) {
5025 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5026 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5027 vcpu->run->internal.ndata = 0;
6d77dbfc 5028 return 0;
de5f70e0 5029 }
ea953ef0
MG		 5030
5031 if (signal_pending(current))
80ced186 5032 goto out;
ea953ef0
MG		 5033 if (need_resched())
5034 schedule();
5035 }
5036
7c068e45 5037 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5038out:
5039 return ret;
ea953ef0
MG		 5040}
5041
4b8d54f9
ZE		 5042/*
5043 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5044 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5045 */
9fb41ba8 5046static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5047{
5048 skip_emulated_instruction(vcpu);
5049 kvm_vcpu_on_spin(vcpu);
5050
5051 return 1;
5052}
5053
59708670
SY		 5054static int handle_invalid_op(struct kvm_vcpu *vcpu)
5055{
5056 kvm_queue_exception(vcpu, UD_VECTOR);
5057 return 1;
5058}
5059
ff2f6fe9
NHE		 5060/*
5061 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5062 * We could reuse a single VMCS for all the L2 guests, but we also want the
5063 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5064 * allows keeping them loaded on the processor, and in the future will allow
5065 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5066 * every entry if they never change.
5067 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5068 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5069 *
5070 * The following functions allocate and free a vmcs02 in this pool.
5071 */
5072
5073/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5074static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5075{
5076 struct vmcs02_list *item;
5077 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5078 if (item->vmptr == vmx->nested.current_vmptr) {
5079 list_move(&item->list, &vmx->nested.vmcs02_pool);
5080 return &item->vmcs02;
5081 }
5082
5083 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5084 /* Recycle the least recently used VMCS. */
5085 item = list_entry(vmx->nested.vmcs02_pool.prev,
5086 struct vmcs02_list, list);
5087 item->vmptr = vmx->nested.current_vmptr;
5088 list_move(&item->list, &vmx->nested.vmcs02_pool);
5089 return &item->vmcs02;
5090 }
5091
5092 /* Create a new VMCS */
5093 item = (struct vmcs02_list *)
5094 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5095 if (!item)
5096 return NULL;
5097 item->vmcs02.vmcs = alloc_vmcs();
5098 if (!item->vmcs02.vmcs) {
5099 kfree(item);
5100 return NULL;
5101 }
5102 loaded_vmcs_init(&item->vmcs02);
5103 item->vmptr = vmx->nested.current_vmptr;
5104 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5105 vmx->nested.vmcs02_num++;
5106 return &item->vmcs02;
5107}
5108
5109/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5110static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5111{
5112 struct vmcs02_list *item;
5113 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5114 if (item->vmptr == vmptr) {
5115 free_loaded_vmcs(&item->vmcs02);
5116 list_del(&item->list);
5117 kfree(item);
5118 vmx->nested.vmcs02_num--;
5119 return;
5120 }
5121}
5122
5123/*
5124 * Free all VMCSs saved for this vcpu, except the one pointed by
5125 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5126 * currently used, if running L2), and vmcs01 when running L2.
5127 */
5128static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5129{
5130 struct vmcs02_list *item, *n;
5131 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5132 if (vmx->loaded_vmcs != &item->vmcs02)
5133 free_loaded_vmcs(&item->vmcs02);
5134 list_del(&item->list);
5135 kfree(item);
5136 }
5137 vmx->nested.vmcs02_num = 0;
5138
5139 if (vmx->loaded_vmcs != &vmx->vmcs01)
5140 free_loaded_vmcs(&vmx->vmcs01);
5141}
5142
ec378aee
NHE		 5143/*
5144 * Emulate the VMXON instruction.
5145 * Currently, we just remember that VMX is active, and do not save or even
5146 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5147 * do not currently need to store anything in that guest-allocated memory
5148 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5149 * argument is different from the VMXON pointer (which the spec says they do).
5150 */
5151static int handle_vmon(struct kvm_vcpu *vcpu)
5152{
5153 struct kvm_segment cs;
5154 struct vcpu_vmx *vmx = to_vmx(vcpu);
5155
5156 /* The Intel VMX Instruction Reference lists a bunch of bits that
5157 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5158 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5159 * Otherwise, we should fail with #UD. We test these now:
5160 */
5161 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5162 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5163 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5164 kvm_queue_exception(vcpu, UD_VECTOR);
5165 return 1;
5166 }
5167
5168 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5169 if (is_long_mode(vcpu) && !cs.l) {
5170 kvm_queue_exception(vcpu, UD_VECTOR);
5171 return 1;
5172 }
5173
5174 if (vmx_get_cpl(vcpu)) {
5175 kvm_inject_gp(vcpu, 0);
5176 return 1;
5177 }
5178
ff2f6fe9
NHE		 5179 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5180 vmx->nested.vmcs02_num = 0;
5181
ec378aee
NHE		 5182 vmx->nested.vmxon = true;
5183
5184 skip_emulated_instruction(vcpu);
5185 return 1;
5186}
5187
5188/*
5189 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5190 * for running VMX instructions (except VMXON, whose prerequisites are
5191 * slightly different). It also specifies what exception to inject otherwise.
5192 */
5193static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5194{
5195 struct kvm_segment cs;
5196 struct vcpu_vmx *vmx = to_vmx(vcpu);
5197
5198 if (!vmx->nested.vmxon) {
5199 kvm_queue_exception(vcpu, UD_VECTOR);
5200 return 0;
5201 }
5202
5203 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5204 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5205 (is_long_mode(vcpu) && !cs.l)) {
5206 kvm_queue_exception(vcpu, UD_VECTOR);
5207 return 0;
5208 }
5209
5210 if (vmx_get_cpl(vcpu)) {
5211 kvm_inject_gp(vcpu, 0);
5212 return 0;
5213 }
5214
5215 return 1;
5216}
5217
5218/*
5219 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5220 * just stops using VMX.
5221 */
5222static void free_nested(struct vcpu_vmx *vmx)
5223{
5224 if (!vmx->nested.vmxon)
5225 return;
5226 vmx->nested.vmxon = false;
a9d30f33
NHE		 5227 if (vmx->nested.current_vmptr != -1ull) {
5228 kunmap(vmx->nested.current_vmcs12_page);
5229 nested_release_page(vmx->nested.current_vmcs12_page);
5230 vmx->nested.current_vmptr = -1ull;
5231 vmx->nested.current_vmcs12 = NULL;
5232 }
fe3ef05c
NHE		 5233 /* Unpin physical memory we referred to in current vmcs02 */
5234 if (vmx->nested.apic_access_page) {
5235 nested_release_page(vmx->nested.apic_access_page);
5236 vmx->nested.apic_access_page = 0;
5237 }
ff2f6fe9
NHE		 5238
5239 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5240}
5241
5242/* Emulate the VMXOFF instruction */
5243static int handle_vmoff(struct kvm_vcpu *vcpu)
5244{
5245 if (!nested_vmx_check_permission(vcpu))
5246 return 1;
5247 free_nested(to_vmx(vcpu));
5248 skip_emulated_instruction(vcpu);
5249 return 1;
5250}
5251
064aea77
NHE		 5252/*
5253 * Decode the memory-address operand of a vmx instruction, as recorded on an
5254 * exit caused by such an instruction (run by a guest hypervisor).
5255 * On success, returns 0. When the operand is invalid, returns 1 and throws
5256 * #UD or #GP.
5257 */
5258static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5259 unsigned long exit_qualification,
5260 u32 vmx_instruction_info, gva_t *ret)
5261{
5262 /*
5263 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5264 * Execution", on an exit, vmx_instruction_info holds most of the
5265 * addressing components of the operand. Only the displacement part
5266 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5267 * For how an actual address is calculated from all these components,
5268 * refer to Vol. 1, "Operand Addressing".
5269 */
5270 int scaling = vmx_instruction_info & 3;
5271 int addr_size = (vmx_instruction_info >> 7) & 7;
5272 bool is_reg = vmx_instruction_info & (1u << 10);
5273 int seg_reg = (vmx_instruction_info >> 15) & 7;
5274 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5275 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5276 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5277 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5278
5279 if (is_reg) {
5280 kvm_queue_exception(vcpu, UD_VECTOR);
5281 return 1;
5282 }
5283
5284 /* Addr = segment_base + offset */
5285 /* offset = base + [index * scale] + displacement */
5286 *ret = vmx_get_segment_base(vcpu, seg_reg);
5287 if (base_is_valid)
5288 *ret += kvm_register_read(vcpu, base_reg);
5289 if (index_is_valid)
5290 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5291 *ret += exit_qualification; /* holds the displacement */
5292
5293 if (addr_size == 1) /* 32 bit */
5294 *ret &= 0xffffffff;
5295
5296 /*
5297 * TODO: throw #GP (and return 1) in various cases that the VM*
5298 * instructions require it - e.g., offset beyond segment limit,
5299 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5300 * address, and so on. Currently these are not checked.
5301 */
5302 return 0;
5303}
5304
0140caea
NHE		 5305/*
5306 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5307 * set the success or error code of an emulated VMX instruction, as specified
5308 * by Vol 2B, VMX Instruction Reference, "Conventions".
5309 */
5310static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5311{
5312 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5313 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5314 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5315}
5316
5317static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5318{
5319 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5320 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5321 X86_EFLAGS_SF | X86_EFLAGS_OF))
5322 | X86_EFLAGS_CF);
5323}
5324
5325static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5326 u32 vm_instruction_error)
5327{
5328 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5329 /*
5330 * failValid writes the error number to the current VMCS, which
5331 * can't be done there isn't a current VMCS.
5332 */
5333 nested_vmx_failInvalid(vcpu);
5334 return;
5335 }
5336 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5337 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5338 X86_EFLAGS_SF | X86_EFLAGS_OF))
5339 | X86_EFLAGS_ZF);
5340 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5341}
5342
27d6c865
NHE		 5343/* Emulate the VMCLEAR instruction */
5344static int handle_vmclear(struct kvm_vcpu *vcpu)
5345{
5346 struct vcpu_vmx *vmx = to_vmx(vcpu);
5347 gva_t gva;
5348 gpa_t vmptr;
5349 struct vmcs12 *vmcs12;
5350 struct page *page;
5351 struct x86_exception e;
5352
5353 if (!nested_vmx_check_permission(vcpu))
5354 return 1;
5355
5356 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5357 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5358 return 1;
5359
5360 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5361 sizeof(vmptr), &e)) {
5362 kvm_inject_page_fault(vcpu, &e);
5363 return 1;
5364 }
5365
5366 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5367 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5368 skip_emulated_instruction(vcpu);
5369 return 1;
5370 }
5371
5372 if (vmptr == vmx->nested.current_vmptr) {
5373 kunmap(vmx->nested.current_vmcs12_page);
5374 nested_release_page(vmx->nested.current_vmcs12_page);
5375 vmx->nested.current_vmptr = -1ull;
5376 vmx->nested.current_vmcs12 = NULL;
5377 }
5378
5379 page = nested_get_page(vcpu, vmptr);
5380 if (page == NULL) {
5381 /*
5382 * For accurate processor emulation, VMCLEAR beyond available
5383 * physical memory should do nothing at all. However, it is
5384 * possible that a nested vmx bug, not a guest hypervisor bug,
5385 * resulted in this case, so let's shut down before doing any
5386 * more damage:
5387 */
5388 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5389 return 1;
5390 }
5391 vmcs12 = kmap(page);
5392 vmcs12->launch_state = 0;
5393 kunmap(page);
5394 nested_release_page(page);
5395
5396 nested_free_vmcs02(vmx, vmptr);
5397
5398 skip_emulated_instruction(vcpu);
5399 nested_vmx_succeed(vcpu);
5400 return 1;
5401}
5402
cd232ad0
NHE		 5403static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5404
5405/* Emulate the VMLAUNCH instruction */
5406static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5407{
5408 return nested_vmx_run(vcpu, true);
5409}
5410
5411/* Emulate the VMRESUME instruction */
5412static int handle_vmresume(struct kvm_vcpu *vcpu)
5413{
5414
5415 return nested_vmx_run(vcpu, false);
5416}
5417
49f705c5
NHE		 5418enum vmcs_field_type {
5419 VMCS_FIELD_TYPE_U16 = 0,
5420 VMCS_FIELD_TYPE_U64 = 1,
5421 VMCS_FIELD_TYPE_U32 = 2,
5422 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5423};
5424
5425static inline int vmcs_field_type(unsigned long field)
5426{
5427 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5428 return VMCS_FIELD_TYPE_U32;
5429 return (field >> 13) & 0x3 ;
5430}
5431
5432static inline int vmcs_field_readonly(unsigned long field)
5433{
5434 return (((field >> 10) & 0x3) == 1);
5435}
5436
5437/*
5438 * Read a vmcs12 field. Since these can have varying lengths and we return
5439 * one type, we chose the biggest type (u64) and zero-extend the return value
5440 * to that size. Note that the caller, handle_vmread, might need to use only
5441 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5442 * 64-bit fields are to be returned).
5443 */
5444static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5445 unsigned long field, u64 *ret)
5446{
5447 short offset = vmcs_field_to_offset(field);
5448 char *p;
5449
5450 if (offset < 0)
5451 return 0;
5452
5453 p = ((char *)(get_vmcs12(vcpu))) + offset;
5454
5455 switch (vmcs_field_type(field)) {
5456 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5457 *ret = *((natural_width *)p);
5458 return 1;
5459 case VMCS_FIELD_TYPE_U16:
5460 *ret = *((u16 *)p);
5461 return 1;
5462 case VMCS_FIELD_TYPE_U32:
5463 *ret = *((u32 *)p);
5464 return 1;
5465 case VMCS_FIELD_TYPE_U64:
5466 *ret = *((u64 *)p);
5467 return 1;
5468 default:
5469 return 0; /* can never happen. */
5470 }
5471}
5472
5473/*
5474 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5475 * used before) all generate the same failure when it is missing.
5476 */
5477static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5478{
5479 struct vcpu_vmx *vmx = to_vmx(vcpu);
5480 if (vmx->nested.current_vmptr == -1ull) {
5481 nested_vmx_failInvalid(vcpu);
5482 skip_emulated_instruction(vcpu);
5483 return 0;
5484 }
5485 return 1;
5486}
5487
5488static int handle_vmread(struct kvm_vcpu *vcpu)
5489{
5490 unsigned long field;
5491 u64 field_value;
5492 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5493 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5494 gva_t gva = 0;
5495
5496 if (!nested_vmx_check_permission(vcpu) ||
5497 !nested_vmx_check_vmcs12(vcpu))
5498 return 1;
5499
5500 /* Decode instruction info and find the field to read */
5501 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5502 /* Read the field, zero-extended to a u64 field_value */
5503 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5504 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5505 skip_emulated_instruction(vcpu);
5506 return 1;
5507 }
5508 /*
5509 * Now copy part of this value to register or memory, as requested.
5510 * Note that the number of bits actually copied is 32 or 64 depending
5511 * on the guest's mode (32 or 64 bit), not on the given field's length.
5512 */
5513 if (vmx_instruction_info & (1u << 10)) {
5514 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5515 field_value);
5516 } else {
5517 if (get_vmx_mem_address(vcpu, exit_qualification,
5518 vmx_instruction_info, &gva))
5519 return 1;
5520 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5521 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5522 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5523 }
5524
5525 nested_vmx_succeed(vcpu);
5526 skip_emulated_instruction(vcpu);
5527 return 1;
5528}
5529
5530
5531static int handle_vmwrite(struct kvm_vcpu *vcpu)
5532{
5533 unsigned long field;
5534 gva_t gva;
5535 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5536 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5537 char *p;
5538 short offset;
5539 /* The value to write might be 32 or 64 bits, depending on L1's long
5540 * mode, and eventually we need to write that into a field of several
5541 * possible lengths. The code below first zero-extends the value to 64
5542 * bit (field_value), and then copies only the approriate number of
5543 * bits into the vmcs12 field.
5544 */
5545 u64 field_value = 0;
5546 struct x86_exception e;
5547
5548 if (!nested_vmx_check_permission(vcpu) ||
5549 !nested_vmx_check_vmcs12(vcpu))
5550 return 1;
5551
5552 if (vmx_instruction_info & (1u << 10))
5553 field_value = kvm_register_read(vcpu,
5554 (((vmx_instruction_info) >> 3) & 0xf));
5555 else {
5556 if (get_vmx_mem_address(vcpu, exit_qualification,
5557 vmx_instruction_info, &gva))
5558 return 1;
5559 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5560 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5561 kvm_inject_page_fault(vcpu, &e);
5562 return 1;
5563 }
5564 }
5565
5566
5567 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5568 if (vmcs_field_readonly(field)) {
5569 nested_vmx_failValid(vcpu,
5570 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5571 skip_emulated_instruction(vcpu);
5572 return 1;
5573 }
5574
5575 offset = vmcs_field_to_offset(field);
5576 if (offset < 0) {
5577 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5578 skip_emulated_instruction(vcpu);
5579 return 1;
5580 }
5581 p = ((char *) get_vmcs12(vcpu)) + offset;
5582
5583 switch (vmcs_field_type(field)) {
5584 case VMCS_FIELD_TYPE_U16:
5585 *(u16 *)p = field_value;
5586 break;
5587 case VMCS_FIELD_TYPE_U32:
5588 *(u32 *)p = field_value;
5589 break;
5590 case VMCS_FIELD_TYPE_U64:
5591 *(u64 *)p = field_value;
5592 break;
5593 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5594 *(natural_width *)p = field_value;
5595 break;
5596 default:
5597 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5598 skip_emulated_instruction(vcpu);
5599 return 1;
5600 }
5601
5602 nested_vmx_succeed(vcpu);
5603 skip_emulated_instruction(vcpu);
5604 return 1;
5605}
5606
63846663
NHE		 5607/* Emulate the VMPTRLD instruction */
5608static int handle_vmptrld(struct kvm_vcpu *vcpu)
5609{
5610 struct vcpu_vmx *vmx = to_vmx(vcpu);
5611 gva_t gva;
5612 gpa_t vmptr;
5613 struct x86_exception e;
5614
5615 if (!nested_vmx_check_permission(vcpu))
5616 return 1;
5617
5618 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5619 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5620 return 1;
5621
5622 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5623 sizeof(vmptr), &e)) {
5624 kvm_inject_page_fault(vcpu, &e);
5625 return 1;
5626 }
5627
5628 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5629 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5630 skip_emulated_instruction(vcpu);
5631 return 1;
5632 }
5633
5634 if (vmx->nested.current_vmptr != vmptr) {
5635 struct vmcs12 *new_vmcs12;
5636 struct page *page;
5637 page = nested_get_page(vcpu, vmptr);
5638 if (page == NULL) {
5639 nested_vmx_failInvalid(vcpu);
5640 skip_emulated_instruction(vcpu);
5641 return 1;
5642 }
5643 new_vmcs12 = kmap(page);
5644 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5645 kunmap(page);
5646 nested_release_page_clean(page);
5647 nested_vmx_failValid(vcpu,
5648 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5649 skip_emulated_instruction(vcpu);
5650 return 1;
5651 }
5652 if (vmx->nested.current_vmptr != -1ull) {
5653 kunmap(vmx->nested.current_vmcs12_page);
5654 nested_release_page(vmx->nested.current_vmcs12_page);
5655 }
5656
5657 vmx->nested.current_vmptr = vmptr;
5658 vmx->nested.current_vmcs12 = new_vmcs12;
5659 vmx->nested.current_vmcs12_page = page;
5660 }
5661
5662 nested_vmx_succeed(vcpu);
5663 skip_emulated_instruction(vcpu);
5664 return 1;
5665}
5666
6a4d7550
NHE		 5667/* Emulate the VMPTRST instruction */
5668static int handle_vmptrst(struct kvm_vcpu *vcpu)
5669{
5670 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5671 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5672 gva_t vmcs_gva;
5673 struct x86_exception e;
5674
5675 if (!nested_vmx_check_permission(vcpu))
5676 return 1;
5677
5678 if (get_vmx_mem_address(vcpu, exit_qualification,
5679 vmx_instruction_info, &vmcs_gva))
5680 return 1;
5681 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5682 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5683 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5684 sizeof(u64), &e)) {
5685 kvm_inject_page_fault(vcpu, &e);
5686 return 1;
5687 }
5688 nested_vmx_succeed(vcpu);
5689 skip_emulated_instruction(vcpu);
5690 return 1;
5691}
5692
6aa8b732
AK		 5693/*
5694 * The exit handlers return 1 if the exit was handled fully and guest execution
5695 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5696 * to be done to userspace and return 0.
5697 */
772e0318 5698static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5699 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5700 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5701 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5702 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5703 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5704 [EXIT_REASON_CR_ACCESS] = handle_cr,
5705 [EXIT_REASON_DR_ACCESS] = handle_dr,
5706 [EXIT_REASON_CPUID] = handle_cpuid,
5707 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5708 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5709 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5710 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5711 [EXIT_REASON_INVD] = handle_invd,
a7052897 5712 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5713 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5714 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5715 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5716 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5717 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5718 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5719 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5720 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5721 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5722 [EXIT_REASON_VMOFF] = handle_vmoff,
5723 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5724 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5725 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5726 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5727 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5728 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5729 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5730 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5731 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5732 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5733 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5734 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5735};
5736
5737static const int kvm_vmx_max_exit_handlers =
50a3485c 5738 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5739
644d711a
NHE		 5740/*
5741 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5742 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5743 * disinterest in the current event (read or write a specific MSR) by using an
5744 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5745 */
5746static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5747 struct vmcs12 *vmcs12, u32 exit_reason)
5748{
5749 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5750 gpa_t bitmap;
5751
5752 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5753 return 1;
5754
5755 /*
5756 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5757 * for the four combinations of read/write and low/high MSR numbers.
5758 * First we need to figure out which of the four to use:
5759 */
5760 bitmap = vmcs12->msr_bitmap;
5761 if (exit_reason == EXIT_REASON_MSR_WRITE)
5762 bitmap += 2048;
5763 if (msr_index >= 0xc0000000) {
5764 msr_index -= 0xc0000000;
5765 bitmap += 1024;
5766 }
5767
5768 /* Then read the msr_index'th bit from this bitmap: */
5769 if (msr_index < 1024*8) {
5770 unsigned char b;
5771 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5772 return 1 & (b >> (msr_index & 7));
5773 } else
5774 return 1; /* let L1 handle the wrong parameter */
5775}
5776
5777/*
5778 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5779 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5780 * intercept (via guest_host_mask etc.) the current event.
5781 */
5782static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5783 struct vmcs12 *vmcs12)
5784{
5785 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5786 int cr = exit_qualification & 15;
5787 int reg = (exit_qualification >> 8) & 15;
5788 unsigned long val = kvm_register_read(vcpu, reg);
5789
5790 switch ((exit_qualification >> 4) & 3) {
5791 case 0: /* mov to cr */
5792 switch (cr) {
5793 case 0:
5794 if (vmcs12->cr0_guest_host_mask &
5795 (val ^ vmcs12->cr0_read_shadow))
5796 return 1;
5797 break;
5798 case 3:
5799 if ((vmcs12->cr3_target_count >= 1 &&
5800 vmcs12->cr3_target_value0 == val) ||
5801 (vmcs12->cr3_target_count >= 2 &&
5802 vmcs12->cr3_target_value1 == val) ||
5803 (vmcs12->cr3_target_count >= 3 &&
5804 vmcs12->cr3_target_value2 == val) ||
5805 (vmcs12->cr3_target_count >= 4 &&
5806 vmcs12->cr3_target_value3 == val))
5807 return 0;
5808 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5809 return 1;
5810 break;
5811 case 4:
5812 if (vmcs12->cr4_guest_host_mask &
5813 (vmcs12->cr4_read_shadow ^ val))
5814 return 1;
5815 break;
5816 case 8:
5817 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5818 return 1;
5819 break;
5820 }
5821 break;
5822 case 2: /* clts */
5823 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5824 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5825 return 1;
5826 break;
5827 case 1: /* mov from cr */
5828 switch (cr) {
5829 case 3:
5830 if (vmcs12->cpu_based_vm_exec_control &
5831 CPU_BASED_CR3_STORE_EXITING)
5832 return 1;
5833 break;
5834 case 8:
5835 if (vmcs12->cpu_based_vm_exec_control &
5836 CPU_BASED_CR8_STORE_EXITING)
5837 return 1;
5838 break;
5839 }
5840 break;
5841 case 3: /* lmsw */
5842 /*
5843 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5844 * cr0. Other attempted changes are ignored, with no exit.
5845 */
5846 if (vmcs12->cr0_guest_host_mask & 0xe &
5847 (val ^ vmcs12->cr0_read_shadow))
5848 return 1;
5849 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5850 !(vmcs12->cr0_read_shadow & 0x1) &&
5851 (val & 0x1))
5852 return 1;
5853 break;
5854 }
5855 return 0;
5856}
5857
5858/*
5859 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5860 * should handle it ourselves in L0 (and then continue L2). Only call this
5861 * when in is_guest_mode (L2).
5862 */
5863static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5864{
5865 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5866 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5867 struct vcpu_vmx *vmx = to_vmx(vcpu);
5868 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5869
5870 if (vmx->nested.nested_run_pending)
5871 return 0;
5872
5873 if (unlikely(vmx->fail)) {
bd80158a
JK		 5874 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5875 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5876 return 1;
5877 }
5878
5879 switch (exit_reason) {
5880 case EXIT_REASON_EXCEPTION_NMI:
5881 if (!is_exception(intr_info))
5882 return 0;
5883 else if (is_page_fault(intr_info))
5884 return enable_ept;
5885 return vmcs12->exception_bitmap &
5886 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5887 case EXIT_REASON_EXTERNAL_INTERRUPT:
5888 return 0;
5889 case EXIT_REASON_TRIPLE_FAULT:
5890 return 1;
5891 case EXIT_REASON_PENDING_INTERRUPT:
5892 case EXIT_REASON_NMI_WINDOW:
5893 /*
5894 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5895 * (aka Interrupt Window Exiting) only when L1 turned it on,
5896 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5897 * Same for NMI Window Exiting.
5898 */
5899 return 1;
5900 case EXIT_REASON_TASK_SWITCH:
5901 return 1;
5902 case EXIT_REASON_CPUID:
5903 return 1;
5904 case EXIT_REASON_HLT:
5905 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5906 case EXIT_REASON_INVD:
5907 return 1;
5908 case EXIT_REASON_INVLPG:
5909 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5910 case EXIT_REASON_RDPMC:
5911 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5912 case EXIT_REASON_RDTSC:
5913 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5914 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5915 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5916 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5917 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5918 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5919 /*
5920 * VMX instructions trap unconditionally. This allows L1 to
5921 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5922 */
5923 return 1;
5924 case EXIT_REASON_CR_ACCESS:
5925 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5926 case EXIT_REASON_DR_ACCESS:
5927 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5928 case EXIT_REASON_IO_INSTRUCTION:
5929 /* TODO: support IO bitmaps */
5930 return 1;
5931 case EXIT_REASON_MSR_READ:
5932 case EXIT_REASON_MSR_WRITE:
5933 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5934 case EXIT_REASON_INVALID_STATE:
5935 return 1;
5936 case EXIT_REASON_MWAIT_INSTRUCTION:
5937 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5938 case EXIT_REASON_MONITOR_INSTRUCTION:
5939 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5940 case EXIT_REASON_PAUSE_INSTRUCTION:
5941 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5942 nested_cpu_has2(vmcs12,
5943 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5944 case EXIT_REASON_MCE_DURING_VMENTRY:
5945 return 0;
5946 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5947 return 1;
5948 case EXIT_REASON_APIC_ACCESS:
5949 return nested_cpu_has2(vmcs12,
5950 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5951 case EXIT_REASON_EPT_VIOLATION:
5952 case EXIT_REASON_EPT_MISCONFIG:
5953 return 0;
5954 case EXIT_REASON_WBINVD:
5955 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5956 case EXIT_REASON_XSETBV:
5957 return 1;
5958 default:
5959 return 1;
5960 }
5961}
5962
586f9607
AK		 5963static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5964{
5965 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5966 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5967}
5968
6aa8b732
AK		 5969/*
5970 * The guest has exited. See if we can fix it or if we need userspace
5971 * assistance.
5972 */
851ba692 5973static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5974{
29bd8a78 5975 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5976 u32 exit_reason = vmx->exit_reason;
1155f76a 5977 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5978
80ced186
MG		 5979 /* If guest state is invalid, start emulating */
5980 if (vmx->emulation_required && emulate_invalid_guest_state)
5981 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5982
b6f1250e
NHE		 5983 /*
5984 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5985 * we did not inject a still-pending event to L1 now because of
5986 * nested_run_pending, we need to re-enable this bit.
5987 */
5988 if (vmx->nested.nested_run_pending)
5989 kvm_make_request(KVM_REQ_EVENT, vcpu);
5990
509c75ea
NHE		 5991 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5992 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5993 vmx->nested.nested_run_pending = 1;
5994 else
5995 vmx->nested.nested_run_pending = 0;
5996
5997 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5998 nested_vmx_vmexit(vcpu);
5999 return 1;
6000 }
6001
5120702e
MG		 6002 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6003 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6004 vcpu->run->fail_entry.hardware_entry_failure_reason
6005 = exit_reason;
6006 return 0;
6007 }
6008
29bd8a78 6009 if (unlikely(vmx->fail)) {
851ba692
AK		 6010 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6011 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6012 = vmcs_read32(VM_INSTRUCTION_ERROR);
6013 return 0;
6014 }
6aa8b732 6015
b9bf6882
XG		 6016 /*
6017 * Note:
6018 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6019 * delivery event since it indicates guest is accessing MMIO.
6020 * The vm-exit can be triggered again after return to guest that
6021 * will cause infinite loop.
6022 */
d77c26fc 6023 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6024 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6025 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6026 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6027 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6028 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6029 vcpu->run->internal.ndata = 2;
6030 vcpu->run->internal.data[0] = vectoring_info;
6031 vcpu->run->internal.data[1] = exit_reason;
6032 return 0;
6033 }
3b86cd99 6034
644d711a
NHE		 6035 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6036 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6037 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6038 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6039 vmx->soft_vnmi_blocked = 0;
3b86cd99 6040 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6041 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6042 /*
6043 * This CPU don't support us in finding the end of an
6044 * NMI-blocked window if the guest runs with IRQs
6045 * disabled. So we pull the trigger after 1 s of
6046 * futile waiting, but inform the user about this.
6047 */
6048 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6049 "state on VCPU %d after 1 s timeout\n",
6050 __func__, vcpu->vcpu_id);
6051 vmx->soft_vnmi_blocked = 0;
3b86cd99 6052 }
3b86cd99
JK		 6053 }
6054
6aa8b732
AK		 6055 if (exit_reason < kvm_vmx_max_exit_handlers
6056 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6057 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6058 else {
851ba692
AK		 6059 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6060 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6061 }
6062 return 0;
6063}
6064
95ba8273 6065static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6066{
95ba8273 6067 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6068 vmcs_write32(TPR_THRESHOLD, 0);
6069 return;
6070 }
6071
95ba8273 6072 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6073}
6074
51aa01d1 6075static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6076{
00eba012
AK		 6077 u32 exit_intr_info;
6078
6079 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6080 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6081 return;
6082
c5ca8e57 6083 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6084 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6085
6086 /* Handle machine checks before interrupts are enabled */
00eba012 6087 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6088 kvm_machine_check();
6089
20f65983 6090 /* We need to handle NMIs before interrupts are enabled */
00eba012 6091 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6092 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6093 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6094 asm("int $2");
ff9d07a0
ZY		 6095 kvm_after_handle_nmi(&vmx->vcpu);
6096 }
51aa01d1 6097}
20f65983 6098
51aa01d1
AK		 6099static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6100{
c5ca8e57 6101 u32 exit_intr_info;
51aa01d1
AK		 6102 bool unblock_nmi;
6103 u8 vector;
6104 bool idtv_info_valid;
6105
6106 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6107
cf393f75 6108 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6109 if (vmx->nmi_known_unmasked)
6110 return;
c5ca8e57
AK		 6111 /*
6112 * Can't use vmx->exit_intr_info since we're not sure what
6113 * the exit reason is.
6114 */
6115 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6116 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6117 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6118 /*
7b4a25cb 6119 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6120 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6121 * a guest IRET fault.
7b4a25cb
GN		 6122 * SDM 3: 23.2.2 (September 2008)
6123 * Bit 12 is undefined in any of the following cases:
6124 * If the VM exit sets the valid bit in the IDT-vectoring
6125 * information field.
6126 * If the VM exit is due to a double fault.
cf393f75 6127 */
7b4a25cb
GN		 6128 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6129 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6130 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6131 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6132 else
6133 vmx->nmi_known_unmasked =
6134 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6135 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6136 } else if (unlikely(vmx->soft_vnmi_blocked))
6137 vmx->vnmi_blocked_time +=
6138 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6139}
6140
83422e17
AK		 6141static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6142 u32 idt_vectoring_info,
6143 int instr_len_field,
6144 int error_code_field)
51aa01d1 6145{
51aa01d1
AK		 6146 u8 vector;
6147 int type;
6148 bool idtv_info_valid;
6149
6150 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6151
37b96e98
GN		 6152 vmx->vcpu.arch.nmi_injected = false;
6153 kvm_clear_exception_queue(&vmx->vcpu);
6154 kvm_clear_interrupt_queue(&vmx->vcpu);
6155
6156 if (!idtv_info_valid)
6157 return;
6158
3842d135
AK		 6159 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6160
668f612f
AK		 6161 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6162 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6163
64a7ec06 6164 switch (type) {
37b96e98
GN		 6165 case INTR_TYPE_NMI_INTR:
6166 vmx->vcpu.arch.nmi_injected = true;
668f612f 6167 /*
7b4a25cb 6168 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6169 * Clear bit "block by NMI" before VM entry if a NMI
6170 * delivery faulted.
668f612f 6171 */
654f06fc 6172 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6173 break;
37b96e98 6174 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6175 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6176 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6177 /* fall through */
6178 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6179 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6180 u32 err = vmcs_read32(error_code_field);
37b96e98 6181 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6182 } else
6183 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6184 break;
66fd3f7f
GN		 6185 case INTR_TYPE_SOFT_INTR:
6186 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6187 vmcs_read32(instr_len_field);
66fd3f7f 6188 /* fall through */
37b96e98 6189 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6190 kvm_queue_interrupt(&vmx->vcpu, vector,
6191 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6192 break;
6193 default:
6194 break;
f7d9238f 6195 }
cf393f75
AK		 6196}
6197
83422e17
AK		 6198static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6199{
66c78ae4
NHE		 6200 if (is_guest_mode(&vmx->vcpu))
6201 return;
83422e17
AK		 6202 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6203 VM_EXIT_INSTRUCTION_LEN,
6204 IDT_VECTORING_ERROR_CODE);
6205}
6206
b463a6f7
AK		 6207static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6208{
66c78ae4
NHE		 6209 if (is_guest_mode(vcpu))
6210 return;
b463a6f7
AK		 6211 __vmx_complete_interrupts(to_vmx(vcpu),
6212 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6213 VM_ENTRY_INSTRUCTION_LEN,
6214 VM_ENTRY_EXCEPTION_ERROR_CODE);
6215
6216 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6217}
6218
d7cd9796
GN		 6219static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6220{
6221 int i, nr_msrs;
6222 struct perf_guest_switch_msr *msrs;
6223
6224 msrs = perf_guest_get_msrs(&nr_msrs);
6225
6226 if (!msrs)
6227 return;
6228
6229 for (i = 0; i < nr_msrs; i++)
6230 if (msrs[i].host == msrs[i].guest)
6231 clear_atomic_switch_msr(vmx, msrs[i].msr);
6232 else
6233 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6234 msrs[i].host);
6235}
6236
a3b5ba49 6237static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6238{
a2fa3e9f 6239 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6240 unsigned long debugctlmsr;
104f226b 6241
66c78ae4
NHE		 6242 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6243 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6244 if (vmcs12->idt_vectoring_info_field &
6245 VECTORING_INFO_VALID_MASK) {
6246 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6247 vmcs12->idt_vectoring_info_field);
6248 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6249 vmcs12->vm_exit_instruction_len);
6250 if (vmcs12->idt_vectoring_info_field &
6251 VECTORING_INFO_DELIVER_CODE_MASK)
6252 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6253 vmcs12->idt_vectoring_error_code);
6254 }
6255 }
6256
104f226b
AK		 6257 /* Record the guest's net vcpu time for enforced NMI injections. */
6258 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6259 vmx->entry_time = ktime_get();
6260
6261 /* Don't enter VMX if guest state is invalid, let the exit handler
6262 start emulation until we arrive back to a valid state */
6263 if (vmx->emulation_required && emulate_invalid_guest_state)
6264 return;
6265
6266 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6267 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6268 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6269 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6270
6271 /* When single-stepping over STI and MOV SS, we must clear the
6272 * corresponding interruptibility bits in the guest state. Otherwise
6273 * vmentry fails as it then expects bit 14 (BS) in pending debug
6274 * exceptions being set, but that's not correct for the guest debugging
6275 * case. */
6276 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6277 vmx_set_interrupt_shadow(vcpu, 0);
6278
d7cd9796 6279 atomic_switch_perf_msrs(vmx);
2a7921b7 6280 debugctlmsr = get_debugctlmsr();
d7cd9796 6281
d462b819 6282 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6283 asm(
6aa8b732 6284 /* Store host registers */
b188c81f
AK		 6285 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6286 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6287 "push %%" _ASM_CX " \n\t"
6288 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6289 "je 1f \n\t"
b188c81f 6290 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6291 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6292 "1: \n\t"
d3edefc0 6293 /* Reload cr2 if changed */
b188c81f
AK		 6294 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6295 "mov %%cr2, %%" _ASM_DX " \n\t"
6296 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6297 "je 2f \n\t"
b188c81f 6298 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6299 "2: \n\t"
6aa8b732 6300 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6301 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6302 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6303 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6304 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6305 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6306 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6307 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6308 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6309#ifdef CONFIG_X86_64
e08aa78a
AK		 6310 "mov %c[r8](%0), %%r8 \n\t"
6311 "mov %c[r9](%0), %%r9 \n\t"
6312 "mov %c[r10](%0), %%r10 \n\t"
6313 "mov %c[r11](%0), %%r11 \n\t"
6314 "mov %c[r12](%0), %%r12 \n\t"
6315 "mov %c[r13](%0), %%r13 \n\t"
6316 "mov %c[r14](%0), %%r14 \n\t"
6317 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6318#endif
b188c81f 6319 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6320
6aa8b732 6321 /* Enter guest mode */
83287ea4 6322 "jne 1f \n\t"
4ecac3fd 6323 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6324 "jmp 2f \n\t"
6325 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6326 "2: "
6aa8b732 6327 /* Save guest registers, load host registers, keep flags */
b188c81f 6328 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6329 "pop %0 \n\t"
b188c81f
AK		 6330 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6331 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6332 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6333 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6334 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6335 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6336 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6337#ifdef CONFIG_X86_64
e08aa78a
AK		 6338 "mov %%r8, %c[r8](%0) \n\t"
6339 "mov %%r9, %c[r9](%0) \n\t"
6340 "mov %%r10, %c[r10](%0) \n\t"
6341 "mov %%r11, %c[r11](%0) \n\t"
6342 "mov %%r12, %c[r12](%0) \n\t"
6343 "mov %%r13, %c[r13](%0) \n\t"
6344 "mov %%r14, %c[r14](%0) \n\t"
6345 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6346#endif
b188c81f
AK		 6347 "mov %%cr2, %%" _ASM_AX " \n\t"
6348 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6349
b188c81f 6350 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6351 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6352 ".pushsection .rodata \n\t"
6353 ".global vmx_return \n\t"
6354 "vmx_return: " _ASM_PTR " 2b \n\t"
6355 ".popsection"
e08aa78a 6356 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6357 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6358 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6359 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6360 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6361 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6362 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6363 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6364 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6365 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6366 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6367#ifdef CONFIG_X86_64
ad312c7c
ZX		 6368 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6369 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6370 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6371 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6372 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6373 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6374 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6375 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6376#endif
40712fae
AK		 6377 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6378 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6379 : "cc", "memory"
6380#ifdef CONFIG_X86_64
b188c81f 6381 , "rax", "rbx", "rdi", "rsi"
c2036300 6382 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6383#else
6384 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6385#endif
6386 );
6aa8b732 6387
2a7921b7
GN		 6388 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6389 if (debugctlmsr)
6390 update_debugctlmsr(debugctlmsr);
6391
aa67f609
AK		 6392#ifndef CONFIG_X86_64
6393 /*
6394 * The sysexit path does not restore ds/es, so we must set them to
6395 * a reasonable value ourselves.
6396 *
6397 * We can't defer this to vmx_load_host_state() since that function
6398 * may be executed in interrupt context, which saves and restore segments
6399 * around it, nullifying its effect.
6400 */
6401 loadsegment(ds, __USER_DS);
6402 loadsegment(es, __USER_DS);
6403#endif
6404
6de4f3ad 6405 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6406 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6407 | (1 << VCPU_EXREG_CPL)
aff48baa 6408 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6409 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6410 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6411 vcpu->arch.regs_dirty = 0;
6412
1155f76a
AK		 6413 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6414
66c78ae4
NHE		 6415 if (is_guest_mode(vcpu)) {
6416 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6417 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6418 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6419 vmcs12->idt_vectoring_error_code =
6420 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6421 vmcs12->vm_exit_instruction_len =
6422 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6423 }
6424 }
6425
d462b819 6426 vmx->loaded_vmcs->launched = 1;
1b6269db 6427
51aa01d1 6428 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6429 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6430
6431 vmx_complete_atomic_exit(vmx);
6432 vmx_recover_nmi_blocking(vmx);
cf393f75 6433 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6434}
6435
6aa8b732
AK		 6436static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6437{
fb3f0f51
RR		 6438 struct vcpu_vmx *vmx = to_vmx(vcpu);
6439
cdbecfc3 6440 free_vpid(vmx);
ec378aee 6441 free_nested(vmx);
d462b819 6442 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6443 kfree(vmx->guest_msrs);
6444 kvm_vcpu_uninit(vcpu);
a4770347 6445 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6446}
6447
fb3f0f51 6448static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6449{
fb3f0f51 6450 int err;
c16f862d 6451 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6452 int cpu;
6aa8b732 6453
a2fa3e9f 6454 if (!vmx)
fb3f0f51
RR		 6455 return ERR_PTR(-ENOMEM);
6456
2384d2b3
SY		 6457 allocate_vpid(vmx);
6458
fb3f0f51
RR		 6459 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6460 if (err)
6461 goto free_vcpu;
965b58a5 6462
a2fa3e9f 6463 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6464 err = -ENOMEM;
fb3f0f51 6465 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6466 goto uninit_vcpu;
6467 }
965b58a5 6468
d462b819
NHE		 6469 vmx->loaded_vmcs = &vmx->vmcs01;
6470 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6471 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6472 goto free_msrs;
d462b819
NHE		 6473 if (!vmm_exclusive)
6474 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6475 loaded_vmcs_init(vmx->loaded_vmcs);
6476 if (!vmm_exclusive)
6477 kvm_cpu_vmxoff();
a2fa3e9f 6478
15ad7146
AK		 6479 cpu = get_cpu();
6480 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6481 vmx->vcpu.cpu = cpu;
8b9cf98c 6482 err = vmx_vcpu_setup(vmx);
fb3f0f51 6483 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6484 put_cpu();
fb3f0f51
RR		 6485 if (err)
6486 goto free_vmcs;
5e4a0b3c 6487 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6488 err = alloc_apic_access_page(kvm);
6489 if (err)
5e4a0b3c 6490 goto free_vmcs;
fb3f0f51 6491
b927a3ce
SY		 6492 if (enable_ept) {
6493 if (!kvm->arch.ept_identity_map_addr)
6494 kvm->arch.ept_identity_map_addr =
6495 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6496 err = -ENOMEM;
b7ebfb05
SY		 6497 if (alloc_identity_pagetable(kvm) != 0)
6498 goto free_vmcs;
93ea5388
GN		 6499 if (!init_rmode_identity_map(kvm))
6500 goto free_vmcs;
b927a3ce 6501 }
b7ebfb05 6502
a9d30f33
NHE		 6503 vmx->nested.current_vmptr = -1ull;
6504 vmx->nested.current_vmcs12 = NULL;
6505
fb3f0f51
RR		 6506 return &vmx->vcpu;
6507
6508free_vmcs:
5f3fbc34 6509 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6510free_msrs:
fb3f0f51
RR		 6511 kfree(vmx->guest_msrs);
6512uninit_vcpu:
6513 kvm_vcpu_uninit(&vmx->vcpu);
6514free_vcpu:
cdbecfc3 6515 free_vpid(vmx);
a4770347 6516 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6517 return ERR_PTR(err);
6aa8b732
AK		 6518}
6519
002c7f7c
YS		 6520static void __init vmx_check_processor_compat(void *rtn)
6521{
6522 struct vmcs_config vmcs_conf;
6523
6524 *(int *)rtn = 0;
6525 if (setup_vmcs_config(&vmcs_conf) < 0)
6526 *(int *)rtn = -EIO;
6527 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6528 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6529 smp_processor_id());
6530 *(int *)rtn = -EIO;
6531 }
6532}
6533
67253af5
SY		 6534static int get_ept_level(void)
6535{
6536 return VMX_EPT_DEFAULT_GAW + 1;
6537}
6538
4b12f0de 6539static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6540{
4b12f0de
SY		 6541 u64 ret;
6542
522c68c4
SY		 6543 /* For VT-d and EPT combination
6544 * 1. MMIO: always map as UC
6545 * 2. EPT with VT-d:
6546 * a. VT-d without snooping control feature: can't guarantee the
6547 * result, try to trust guest.
6548 * b. VT-d with snooping control feature: snooping control feature of
6549 * VT-d engine can guarantee the cache correctness. Just set it
6550 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6551 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6552 * consistent with host MTRR
6553 */
4b12f0de
SY		 6554 if (is_mmio)
6555 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6556 else if (vcpu->kvm->arch.iommu_domain &&
6557 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6558 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6559 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6560 else
522c68c4 6561 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6562 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6563
6564 return ret;
64d4d521
SY		 6565}
6566
17cc3935 6567static int vmx_get_lpage_level(void)
344f414f 6568{
878403b7
SY		 6569 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6570 return PT_DIRECTORY_LEVEL;
6571 else
6572 /* For shadow and EPT supported 1GB page */
6573 return PT_PDPE_LEVEL;
344f414f
JR		 6574}
6575
0e851880
SY		 6576static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6577{
4e47c7a6
SY		 6578 struct kvm_cpuid_entry2 *best;
6579 struct vcpu_vmx *vmx = to_vmx(vcpu);
6580 u32 exec_control;
6581
6582 vmx->rdtscp_enabled = false;
6583 if (vmx_rdtscp_supported()) {
6584 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6585 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6586 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6587 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6588 vmx->rdtscp_enabled = true;
6589 else {
6590 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6591 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6592 exec_control);
6593 }
6594 }
6595 }
ad756a16 6596
ad756a16
MJ		 6597 /* Exposing INVPCID only when PCID is exposed */
6598 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6599 if (vmx_invpcid_supported() &&
4f977045 6600 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6601 guest_cpuid_has_pcid(vcpu)) {
29282fde 6602 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 6603 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6604 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6605 exec_control);
6606 } else {
29282fde
TI		 6607 if (cpu_has_secondary_exec_ctrls()) {
6608 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6609 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6610 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6611 exec_control);
6612 }
ad756a16 6613 if (best)
4f977045 6614 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6615 }
0e851880
SY		 6616}
6617
d4330ef2
JR		 6618static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6619{
7b8050f5
NHE		 6620 if (func == 1 && nested)
6621 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6622}
6623
fe3ef05c
NHE		 6624/*
6625 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6626 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6627 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6628 * guest in a way that will both be appropriate to L1's requests, and our
6629 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6630 * function also has additional necessary side-effects, like setting various
6631 * vcpu->arch fields.
6632 */
6633static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6634{
6635 struct vcpu_vmx *vmx = to_vmx(vcpu);
6636 u32 exec_control;
6637
6638 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6639 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6640 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6641 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6642 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6643 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6644 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6645 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6646 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6647 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6648 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6649 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6650 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6651 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6652 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6653 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6654 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6655 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6656 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6657 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6658 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6659 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6660 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6661 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6662 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6663 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6664 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6665 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6666 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6667 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6668 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6669 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6670 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6671 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6672 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6673 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6674
6675 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6676 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6677 vmcs12->vm_entry_intr_info_field);
6678 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6679 vmcs12->vm_entry_exception_error_code);
6680 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6681 vmcs12->vm_entry_instruction_len);
6682 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6683 vmcs12->guest_interruptibility_info);
6684 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6685 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6686 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6687 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6688 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6689 vmcs12->guest_pending_dbg_exceptions);
6690 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6691 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6692
6693 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6694
6695 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6696 (vmcs_config.pin_based_exec_ctrl |
6697 vmcs12->pin_based_vm_exec_control));
6698
6699 /*
6700 * Whether page-faults are trapped is determined by a combination of
6701 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6702 * If enable_ept, L0 doesn't care about page faults and we should
6703 * set all of these to L1's desires. However, if !enable_ept, L0 does
6704 * care about (at least some) page faults, and because it is not easy
6705 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6706 * to exit on each and every L2 page fault. This is done by setting
6707 * MASK=MATCH=0 and (see below) EB.PF=1.
6708 * Note that below we don't need special code to set EB.PF beyond the
6709 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6710 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6711 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6712 *
6713 * A problem with this approach (when !enable_ept) is that L1 may be
6714 * injected with more page faults than it asked for. This could have
6715 * caused problems, but in practice existing hypervisors don't care.
6716 * To fix this, we will need to emulate the PFEC checking (on the L1
6717 * page tables), using walk_addr(), when injecting PFs to L1.
6718 */
6719 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6720 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6721 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6722 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6723
6724 if (cpu_has_secondary_exec_ctrls()) {
6725 u32 exec_control = vmx_secondary_exec_control(vmx);
6726 if (!vmx->rdtscp_enabled)
6727 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6728 /* Take the following fields only from vmcs12 */
6729 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6730 if (nested_cpu_has(vmcs12,
6731 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6732 exec_control |= vmcs12->secondary_vm_exec_control;
6733
6734 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6735 /*
6736 * Translate L1 physical address to host physical
6737 * address for vmcs02. Keep the page pinned, so this
6738 * physical address remains valid. We keep a reference
6739 * to it so we can release it later.
6740 */
6741 if (vmx->nested.apic_access_page) /* shouldn't happen */
6742 nested_release_page(vmx->nested.apic_access_page);
6743 vmx->nested.apic_access_page =
6744 nested_get_page(vcpu, vmcs12->apic_access_addr);
6745 /*
6746 * If translation failed, no matter: This feature asks
6747 * to exit when accessing the given address, and if it
6748 * can never be accessed, this feature won't do
6749 * anything anyway.
6750 */
6751 if (!vmx->nested.apic_access_page)
6752 exec_control &=
6753 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6754 else
6755 vmcs_write64(APIC_ACCESS_ADDR,
6756 page_to_phys(vmx->nested.apic_access_page));
6757 }
6758
6759 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6760 }
6761
6762
6763 /*
6764 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6765 * Some constant fields are set here by vmx_set_constant_host_state().
6766 * Other fields are different per CPU, and will be set later when
6767 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6768 */
6769 vmx_set_constant_host_state();
6770
6771 /*
6772 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6773 * entry, but only if the current (host) sp changed from the value
6774 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6775 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6776 * here we just force the write to happen on entry.
6777 */
6778 vmx->host_rsp = 0;
6779
6780 exec_control = vmx_exec_control(vmx); /* L0's desires */
6781 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6782 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6783 exec_control &= ~CPU_BASED_TPR_SHADOW;
6784 exec_control |= vmcs12->cpu_based_vm_exec_control;
6785 /*
6786 * Merging of IO and MSR bitmaps not currently supported.
6787 * Rather, exit every time.
6788 */
6789 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6790 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6791 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6792
6793 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6794
6795 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6796 * bitwise-or of what L1 wants to trap for L2, and what we want to
6797 * trap. Note that CR0.TS also needs updating - we do this later.
6798 */
6799 update_exception_bitmap(vcpu);
6800 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6801 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6802
6803 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6804 vmcs_write32(VM_EXIT_CONTROLS,
6805 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6806 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6807 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6808
6809 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6810 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6811 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6812 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6813
6814
6815 set_cr4_guest_host_mask(vmx);
6816
27fc51b2
NHE		 6817 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6818 vmcs_write64(TSC_OFFSET,
6819 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6820 else
6821 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6822
6823 if (enable_vpid) {
6824 /*
6825 * Trivially support vpid by letting L2s share their parent
6826 * L1's vpid. TODO: move to a more elaborate solution, giving
6827 * each L2 its own vpid and exposing the vpid feature to L1.
6828 */
6829 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6830 vmx_flush_tlb(vcpu);
6831 }
6832
6833 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6834 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6835 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6836 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6837 else
6838 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6839 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6840 vmx_set_efer(vcpu, vcpu->arch.efer);
6841
6842 /*
6843 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6844 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6845 * The CR0_READ_SHADOW is what L2 should have expected to read given
6846 * the specifications by L1; It's not enough to take
6847 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6848 * have more bits than L1 expected.
6849 */
6850 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6851 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6852
6853 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6854 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6855
6856 /* shadow page tables on either EPT or shadow page tables */
6857 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6858 kvm_mmu_reset_context(vcpu);
6859
6860 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6861 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6862}
6863
cd232ad0
NHE		 6864/*
6865 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6866 * for running an L2 nested guest.
6867 */
6868static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6869{
6870 struct vmcs12 *vmcs12;
6871 struct vcpu_vmx *vmx = to_vmx(vcpu);
6872 int cpu;
6873 struct loaded_vmcs *vmcs02;
6874
6875 if (!nested_vmx_check_permission(vcpu) ||
6876 !nested_vmx_check_vmcs12(vcpu))
6877 return 1;
6878
6879 skip_emulated_instruction(vcpu);
6880 vmcs12 = get_vmcs12(vcpu);
6881
7c177938
NHE		 6882 /*
6883 * The nested entry process starts with enforcing various prerequisites
6884 * on vmcs12 as required by the Intel SDM, and act appropriately when
6885 * they fail: As the SDM explains, some conditions should cause the
6886 * instruction to fail, while others will cause the instruction to seem
6887 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6888 * To speed up the normal (success) code path, we should avoid checking
6889 * for misconfigurations which will anyway be caught by the processor
6890 * when using the merged vmcs02.
6891 */
6892 if (vmcs12->launch_state == launch) {
6893 nested_vmx_failValid(vcpu,
6894 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6895 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6896 return 1;
6897 }
6898
6899 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6900 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6901 /*TODO: Also verify bits beyond physical address width are 0*/
6902 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6903 return 1;
6904 }
6905
6906 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6907 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6908 /*TODO: Also verify bits beyond physical address width are 0*/
6909 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6910 return 1;
6911 }
6912
6913 if (vmcs12->vm_entry_msr_load_count > 0 ||
6914 vmcs12->vm_exit_msr_load_count > 0 ||
6915 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6916 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6917 __func__);
7c177938
NHE		 6918 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6919 return 1;
6920 }
6921
6922 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6923 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6924 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6925 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6926 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6927 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6928 !vmx_control_verify(vmcs12->vm_exit_controls,
6929 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6930 !vmx_control_verify(vmcs12->vm_entry_controls,
6931 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6932 {
6933 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6934 return 1;
6935 }
6936
6937 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6938 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6939 nested_vmx_failValid(vcpu,
6940 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6941 return 1;
6942 }
6943
6944 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6945 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6946 nested_vmx_entry_failure(vcpu, vmcs12,
6947 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6948 return 1;
6949 }
6950 if (vmcs12->vmcs_link_pointer != -1ull) {
6951 nested_vmx_entry_failure(vcpu, vmcs12,
6952 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6953 return 1;
6954 }
6955
6956 /*
6957 * We're finally done with prerequisite checking, and can start with
6958 * the nested entry.
6959 */
6960
cd232ad0
NHE		 6961 vmcs02 = nested_get_current_vmcs02(vmx);
6962 if (!vmcs02)
6963 return -ENOMEM;
6964
6965 enter_guest_mode(vcpu);
6966
6967 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6968
6969 cpu = get_cpu();
6970 vmx->loaded_vmcs = vmcs02;
6971 vmx_vcpu_put(vcpu);
6972 vmx_vcpu_load(vcpu, cpu);
6973 vcpu->cpu = cpu;
6974 put_cpu();
6975
6976 vmcs12->launch_state = 1;
6977
6978 prepare_vmcs02(vcpu, vmcs12);
6979
6980 /*
6981 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6982 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6983 * returned as far as L1 is concerned. It will only return (and set
6984 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6985 */
6986 return 1;
6987}
6988
4704d0be
NHE		 6989/*
6990 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6991 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6992 * This function returns the new value we should put in vmcs12.guest_cr0.
6993 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6994 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6995 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6996 * didn't trap the bit, because if L1 did, so would L0).
6997 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6998 * been modified by L2, and L1 knows it. So just leave the old value of
6999 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7000 * isn't relevant, because if L0 traps this bit it can set it to anything.
7001 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7002 * changed these bits, and therefore they need to be updated, but L0
7003 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7004 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7005 */
7006static inline unsigned long
7007vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7008{
7009 return
7010 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7011 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7012 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7013 vcpu->arch.cr0_guest_owned_bits));
7014}
7015
7016static inline unsigned long
7017vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7018{
7019 return
7020 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7021 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7022 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7023 vcpu->arch.cr4_guest_owned_bits));
7024}
7025
7026/*
7027 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7028 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7029 * and this function updates it to reflect the changes to the guest state while
7030 * L2 was running (and perhaps made some exits which were handled directly by L0
7031 * without going back to L1), and to reflect the exit reason.
7032 * Note that we do not have to copy here all VMCS fields, just those that
7033 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7034 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7035 * which already writes to vmcs12 directly.
7036 */
7037void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7038{
7039 /* update guest state fields: */
7040 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7041 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7042
7043 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7044 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7045 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7046 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7047
7048 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7049 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7050 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7051 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7052 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7053 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7054 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7055 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7056 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7057 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7058 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7059 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7060 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7061 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7062 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7063 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7064 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7065 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7066 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7067 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7068 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7069 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7070 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7071 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7072 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7073 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7074 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7075 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7076 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7077 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7078 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7079 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7080 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7081 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7082 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7083 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7084
7085 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7086 vmcs12->guest_interruptibility_info =
7087 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7088 vmcs12->guest_pending_dbg_exceptions =
7089 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7090
7091 /* TODO: These cannot have changed unless we have MSR bitmaps and
7092 * the relevant bit asks not to trap the change */
7093 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7094 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7095 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7096 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7097 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7098 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7099
7100 /* update exit information fields: */
7101
7102 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7103 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7104
7105 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7106 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7107 vmcs12->idt_vectoring_info_field =
7108 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7109 vmcs12->idt_vectoring_error_code =
7110 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7111 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7112 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7113
7114 /* clear vm-entry fields which are to be cleared on exit */
7115 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7116 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7117}
7118
7119/*
7120 * A part of what we need to when the nested L2 guest exits and we want to
7121 * run its L1 parent, is to reset L1's guest state to the host state specified
7122 * in vmcs12.
7123 * This function is to be called not only on normal nested exit, but also on
7124 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7125 * Failures During or After Loading Guest State").
7126 * This function should be called when the active VMCS is L1's (vmcs01).
7127 */
7128void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7129{
7130 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7131 vcpu->arch.efer = vmcs12->host_ia32_efer;
7132 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7133 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7134 else
7135 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7136 vmx_set_efer(vcpu, vcpu->arch.efer);
7137
7138 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7139 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7140 /*
7141 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7142 * actually changed, because it depends on the current state of
7143 * fpu_active (which may have changed).
7144 * Note that vmx_set_cr0 refers to efer set above.
7145 */
7146 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7147 /*
7148 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7149 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7150 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7151 */
7152 update_exception_bitmap(vcpu);
7153 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7154 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7155
7156 /*
7157 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7158 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7159 */
7160 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7161 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7162
7163 /* shadow page tables on either EPT or shadow page tables */
7164 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7165 kvm_mmu_reset_context(vcpu);
7166
7167 if (enable_vpid) {
7168 /*
7169 * Trivially support vpid by letting L2s share their parent
7170 * L1's vpid. TODO: move to a more elaborate solution, giving
7171 * each L2 its own vpid and exposing the vpid feature to L1.
7172 */
7173 vmx_flush_tlb(vcpu);
7174 }
7175
7176
7177 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7178 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7179 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7180 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7181 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7182 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7183 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7184 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7185 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7186 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7187 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7188 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7189 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7190 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7191 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7192
7193 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7194 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7195 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7196 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7197 vmcs12->host_ia32_perf_global_ctrl);
7198}
7199
7200/*
7201 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7202 * and modify vmcs12 to make it see what it would expect to see there if
7203 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7204 */
7205static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7206{
7207 struct vcpu_vmx *vmx = to_vmx(vcpu);
7208 int cpu;
7209 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7210
7211 leave_guest_mode(vcpu);
7212 prepare_vmcs12(vcpu, vmcs12);
7213
7214 cpu = get_cpu();
7215 vmx->loaded_vmcs = &vmx->vmcs01;
7216 vmx_vcpu_put(vcpu);
7217 vmx_vcpu_load(vcpu, cpu);
7218 vcpu->cpu = cpu;
7219 put_cpu();
7220
7221 /* if no vmcs02 cache requested, remove the one we used */
7222 if (VMCS02_POOL_SIZE == 0)
7223 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7224
7225 load_vmcs12_host_state(vcpu, vmcs12);
7226
27fc51b2 7227 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7228 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7229
7230 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7231 vmx->host_rsp = 0;
7232
7233 /* Unpin physical memory we referred to in vmcs02 */
7234 if (vmx->nested.apic_access_page) {
7235 nested_release_page(vmx->nested.apic_access_page);
7236 vmx->nested.apic_access_page = 0;
7237 }
7238
7239 /*
7240 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7241 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7242 * success or failure flag accordingly.
7243 */
7244 if (unlikely(vmx->fail)) {
7245 vmx->fail = 0;
7246 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7247 } else
7248 nested_vmx_succeed(vcpu);
7249}
7250
7c177938
NHE		 7251/*
7252 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7253 * 23.7 "VM-entry failures during or after loading guest state" (this also
7254 * lists the acceptable exit-reason and exit-qualification parameters).
7255 * It should only be called before L2 actually succeeded to run, and when
7256 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7257 */
7258static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7259 struct vmcs12 *vmcs12,
7260 u32 reason, unsigned long qualification)
7261{
7262 load_vmcs12_host_state(vcpu, vmcs12);
7263 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7264 vmcs12->exit_qualification = qualification;
7265 nested_vmx_succeed(vcpu);
7266}
7267
8a76d7f2
JR		 7268static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7269 struct x86_instruction_info *info,
7270 enum x86_intercept_stage stage)
7271{
7272 return X86EMUL_CONTINUE;
7273}
7274
cbdd1bea 7275static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7276 .cpu_has_kvm_support = cpu_has_kvm_support,
7277 .disabled_by_bios = vmx_disabled_by_bios,
7278 .hardware_setup = hardware_setup,
7279 .hardware_unsetup = hardware_unsetup,
002c7f7c 7280 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7281 .hardware_enable = hardware_enable,
7282 .hardware_disable = hardware_disable,
04547156 7283 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7284
7285 .vcpu_create = vmx_create_vcpu,
7286 .vcpu_free = vmx_free_vcpu,
04d2cc77 7287 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7288
04d2cc77 7289 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7290 .vcpu_load = vmx_vcpu_load,
7291 .vcpu_put = vmx_vcpu_put,
7292
c8639010 7293 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7294 .get_msr = vmx_get_msr,
7295 .set_msr = vmx_set_msr,
7296 .get_segment_base = vmx_get_segment_base,
7297 .get_segment = vmx_get_segment,
7298 .set_segment = vmx_set_segment,
2e4d2653 7299 .get_cpl = vmx_get_cpl,
6aa8b732 7300 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7301 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7302 .decache_cr3 = vmx_decache_cr3,
25c4c276 7303 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7304 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7305 .set_cr3 = vmx_set_cr3,
7306 .set_cr4 = vmx_set_cr4,
6aa8b732 7307 .set_efer = vmx_set_efer,
6aa8b732
AK		 7308 .get_idt = vmx_get_idt,
7309 .set_idt = vmx_set_idt,
7310 .get_gdt = vmx_get_gdt,
7311 .set_gdt = vmx_set_gdt,
020df079 7312 .set_dr7 = vmx_set_dr7,
5fdbf976 7313 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7314 .get_rflags = vmx_get_rflags,
7315 .set_rflags = vmx_set_rflags,
ebcbab4c 7316 .fpu_activate = vmx_fpu_activate,
02daab21 7317 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7318
7319 .tlb_flush = vmx_flush_tlb,
6aa8b732 7320
6aa8b732 7321 .run = vmx_vcpu_run,
6062d012 7322 .handle_exit = vmx_handle_exit,
6aa8b732 7323 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7324 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7325 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7326 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7327 .set_irq = vmx_inject_irq,
95ba8273 7328 .set_nmi = vmx_inject_nmi,
298101da 7329 .queue_exception = vmx_queue_exception,
b463a6f7 7330 .cancel_injection = vmx_cancel_injection,
78646121 7331 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7332 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7333 .get_nmi_mask = vmx_get_nmi_mask,
7334 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7335 .enable_nmi_window = enable_nmi_window,
7336 .enable_irq_window = enable_irq_window,
7337 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7338
cbc94022 7339 .set_tss_addr = vmx_set_tss_addr,
67253af5 7340 .get_tdp_level = get_ept_level,
4b12f0de 7341 .get_mt_mask = vmx_get_mt_mask,
229456fc 7342
586f9607 7343 .get_exit_info = vmx_get_exit_info,
586f9607 7344
17cc3935 7345 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7346
7347 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7348
7349 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7350 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7351
7352 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7353
7354 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7355
4051b188 7356 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7357 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7358 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7359 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7360 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7361 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7362
7363 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7364
7365 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7366};
7367
7368static int __init vmx_init(void)
7369{
26bb0981
AK		 7370 int r, i;
7371
7372 rdmsrl_safe(MSR_EFER, &host_efer);
7373
7374 for (i = 0; i < NR_VMX_MSR; ++i)
7375 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7376
3e7c73e9 7377 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7378 if (!vmx_io_bitmap_a)
7379 return -ENOMEM;
7380
2106a548
GC		 7381 r = -ENOMEM;
7382
3e7c73e9 7383 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7384 if (!vmx_io_bitmap_b)
fdef3ad1 7385 goto out;
fdef3ad1 7386
5897297b 7387 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7388 if (!vmx_msr_bitmap_legacy)
25c5f225 7389 goto out1;
2106a548 7390
25c5f225 7391
5897297b 7392 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7393 if (!vmx_msr_bitmap_longmode)
5897297b 7394 goto out2;
2106a548 7395
5897297b 7396
fdef3ad1
HQ		 7397 /*
7398 * Allow direct access to the PC debug port (it is often used for I/O
7399 * delays, but the vmexits simply slow things down).
7400 */
3e7c73e9
AK		 7401 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7402 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7403
3e7c73e9 7404 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7405
5897297b
AK		 7406 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7407 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7408
2384d2b3
SY		 7409 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7410
0ee75bea
AK		 7411 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7412 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7413 if (r)
5897297b 7414 goto out3;
25c5f225 7415
8f536b76
ZY		 7416#ifdef CONFIG_KEXEC
7417 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7418 crash_vmclear_local_loaded_vmcss);
7419#endif
7420
5897297b
AK		 7421 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7422 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7423 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7424 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7425 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7426 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7427
089d034e 7428 if (enable_ept) {
3f6d8c8a
XH		 7429 kvm_mmu_set_mask_ptes(0ull,
7430 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7431 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7432 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7433 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7434 kvm_enable_tdp();
7435 } else
7436 kvm_disable_tdp();
1439442c 7437
fdef3ad1
HQ		 7438 return 0;
7439
5897297b
AK		 7440out3:
7441 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7442out2:
5897297b 7443 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7444out1:
3e7c73e9 7445 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7446out:
3e7c73e9 7447 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7448 return r;
6aa8b732
AK		 7449}
7450
7451static void __exit vmx_exit(void)
7452{
5897297b
AK		 7453 free_page((unsigned long)vmx_msr_bitmap_legacy);
7454 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7455 free_page((unsigned long)vmx_io_bitmap_b);
7456 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7457
8f536b76
ZY		 7458#ifdef CONFIG_KEXEC
7459 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7460 synchronize_rcu();
7461#endif
7462
cb498ea2 7463 kvm_exit();
6aa8b732
AK		 7464}
7465
7466module_init(vmx_init)
7467module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)