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KVM: VMX: cleanup rmode_segment_valid()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
801d3424
NHE		 87/*
88 * If nested=1, nested virtualization is supported, i.e., guests may use
89 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
90 * use VMX instructions.
91 */
476bc001 92static bool __read_mostly nested = 0;
801d3424
NHE		 93module_param(nested, bool, S_IRUGO);
94
cdc0e244
AK		 95#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
96 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
97#define KVM_GUEST_CR0_MASK \
98 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
99#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 100 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 101#define KVM_VM_CR0_ALWAYS_ON \
102 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 103#define KVM_CR4_GUEST_OWNED_BITS \
104 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
105 | X86_CR4_OSXMMEXCPT)
106
cdc0e244
AK		 107#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
108#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109
78ac8b47
AK		 110#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111
4b8d54f9
ZE		 112/*
113 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
114 * ple_gap: upper bound on the amount of time between two successive
115 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 116 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 117 * ple_window: upper bound on the amount of time a guest is allowed to execute
118 * in a PAUSE loop. Tests indicate that most spinlocks are held for
119 * less than 2^12 cycles
120 * Time is measured based on a counter that runs at the same rate as the TSC,
121 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 */
00c25bce 123#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 124#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
125static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
126module_param(ple_gap, int, S_IRUGO);
127
128static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
129module_param(ple_window, int, S_IRUGO);
130
83287ea4
AK		 131extern const ulong vmx_return;
132
8bf00a52 133#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 134#define VMCS02_POOL_SIZE 1
61d2ef2c 135
a2fa3e9f
GH		 136struct vmcs {
137 u32 revision_id;
138 u32 abort;
139 char data[0];
140};
141
d462b819
NHE		 142/*
143 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
144 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
145 * loaded on this CPU (so we can clear them if the CPU goes down).
146 */
147struct loaded_vmcs {
148 struct vmcs *vmcs;
149 int cpu;
150 int launched;
151 struct list_head loaded_vmcss_on_cpu_link;
152};
153
26bb0981
AK		 154struct shared_msr_entry {
155 unsigned index;
156 u64 data;
d5696725 157 u64 mask;
26bb0981
AK		 158};
159
a9d30f33
NHE		 160/*
161 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
162 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
163 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
164 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
165 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
166 * More than one of these structures may exist, if L1 runs multiple L2 guests.
167 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
168 * underlying hardware which will be used to run L2.
169 * This structure is packed to ensure that its layout is identical across
170 * machines (necessary for live migration).
171 * If there are changes in this struct, VMCS12_REVISION must be changed.
172 */
22bd0358 173typedef u64 natural_width;
a9d30f33
NHE		 174struct __packed vmcs12 {
175 /* According to the Intel spec, a VMCS region must start with the
176 * following two fields. Then follow implementation-specific data.
177 */
178 u32 revision_id;
179 u32 abort;
22bd0358 180
27d6c865
NHE		 181 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
182 u32 padding[7]; /* room for future expansion */
183
22bd0358
NHE		 184 u64 io_bitmap_a;
185 u64 io_bitmap_b;
186 u64 msr_bitmap;
187 u64 vm_exit_msr_store_addr;
188 u64 vm_exit_msr_load_addr;
189 u64 vm_entry_msr_load_addr;
190 u64 tsc_offset;
191 u64 virtual_apic_page_addr;
192 u64 apic_access_addr;
193 u64 ept_pointer;
194 u64 guest_physical_address;
195 u64 vmcs_link_pointer;
196 u64 guest_ia32_debugctl;
197 u64 guest_ia32_pat;
198 u64 guest_ia32_efer;
199 u64 guest_ia32_perf_global_ctrl;
200 u64 guest_pdptr0;
201 u64 guest_pdptr1;
202 u64 guest_pdptr2;
203 u64 guest_pdptr3;
204 u64 host_ia32_pat;
205 u64 host_ia32_efer;
206 u64 host_ia32_perf_global_ctrl;
207 u64 padding64[8]; /* room for future expansion */
208 /*
209 * To allow migration of L1 (complete with its L2 guests) between
210 * machines of different natural widths (32 or 64 bit), we cannot have
211 * unsigned long fields with no explict size. We use u64 (aliased
212 * natural_width) instead. Luckily, x86 is little-endian.
213 */
214 natural_width cr0_guest_host_mask;
215 natural_width cr4_guest_host_mask;
216 natural_width cr0_read_shadow;
217 natural_width cr4_read_shadow;
218 natural_width cr3_target_value0;
219 natural_width cr3_target_value1;
220 natural_width cr3_target_value2;
221 natural_width cr3_target_value3;
222 natural_width exit_qualification;
223 natural_width guest_linear_address;
224 natural_width guest_cr0;
225 natural_width guest_cr3;
226 natural_width guest_cr4;
227 natural_width guest_es_base;
228 natural_width guest_cs_base;
229 natural_width guest_ss_base;
230 natural_width guest_ds_base;
231 natural_width guest_fs_base;
232 natural_width guest_gs_base;
233 natural_width guest_ldtr_base;
234 natural_width guest_tr_base;
235 natural_width guest_gdtr_base;
236 natural_width guest_idtr_base;
237 natural_width guest_dr7;
238 natural_width guest_rsp;
239 natural_width guest_rip;
240 natural_width guest_rflags;
241 natural_width guest_pending_dbg_exceptions;
242 natural_width guest_sysenter_esp;
243 natural_width guest_sysenter_eip;
244 natural_width host_cr0;
245 natural_width host_cr3;
246 natural_width host_cr4;
247 natural_width host_fs_base;
248 natural_width host_gs_base;
249 natural_width host_tr_base;
250 natural_width host_gdtr_base;
251 natural_width host_idtr_base;
252 natural_width host_ia32_sysenter_esp;
253 natural_width host_ia32_sysenter_eip;
254 natural_width host_rsp;
255 natural_width host_rip;
256 natural_width paddingl[8]; /* room for future expansion */
257 u32 pin_based_vm_exec_control;
258 u32 cpu_based_vm_exec_control;
259 u32 exception_bitmap;
260 u32 page_fault_error_code_mask;
261 u32 page_fault_error_code_match;
262 u32 cr3_target_count;
263 u32 vm_exit_controls;
264 u32 vm_exit_msr_store_count;
265 u32 vm_exit_msr_load_count;
266 u32 vm_entry_controls;
267 u32 vm_entry_msr_load_count;
268 u32 vm_entry_intr_info_field;
269 u32 vm_entry_exception_error_code;
270 u32 vm_entry_instruction_len;
271 u32 tpr_threshold;
272 u32 secondary_vm_exec_control;
273 u32 vm_instruction_error;
274 u32 vm_exit_reason;
275 u32 vm_exit_intr_info;
276 u32 vm_exit_intr_error_code;
277 u32 idt_vectoring_info_field;
278 u32 idt_vectoring_error_code;
279 u32 vm_exit_instruction_len;
280 u32 vmx_instruction_info;
281 u32 guest_es_limit;
282 u32 guest_cs_limit;
283 u32 guest_ss_limit;
284 u32 guest_ds_limit;
285 u32 guest_fs_limit;
286 u32 guest_gs_limit;
287 u32 guest_ldtr_limit;
288 u32 guest_tr_limit;
289 u32 guest_gdtr_limit;
290 u32 guest_idtr_limit;
291 u32 guest_es_ar_bytes;
292 u32 guest_cs_ar_bytes;
293 u32 guest_ss_ar_bytes;
294 u32 guest_ds_ar_bytes;
295 u32 guest_fs_ar_bytes;
296 u32 guest_gs_ar_bytes;
297 u32 guest_ldtr_ar_bytes;
298 u32 guest_tr_ar_bytes;
299 u32 guest_interruptibility_info;
300 u32 guest_activity_state;
301 u32 guest_sysenter_cs;
302 u32 host_ia32_sysenter_cs;
303 u32 padding32[8]; /* room for future expansion */
304 u16 virtual_processor_id;
305 u16 guest_es_selector;
306 u16 guest_cs_selector;
307 u16 guest_ss_selector;
308 u16 guest_ds_selector;
309 u16 guest_fs_selector;
310 u16 guest_gs_selector;
311 u16 guest_ldtr_selector;
312 u16 guest_tr_selector;
313 u16 host_es_selector;
314 u16 host_cs_selector;
315 u16 host_ss_selector;
316 u16 host_ds_selector;
317 u16 host_fs_selector;
318 u16 host_gs_selector;
319 u16 host_tr_selector;
a9d30f33
NHE		 320};
321
322/*
323 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
324 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
325 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 */
327#define VMCS12_REVISION 0x11e57ed0
328
329/*
330 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
331 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
332 * current implementation, 4K are reserved to avoid future complications.
333 */
334#define VMCS12_SIZE 0x1000
335
ff2f6fe9
NHE		 336/* Used to remember the last vmcs02 used for some recently used vmcs12s */
337struct vmcs02_list {
338 struct list_head list;
339 gpa_t vmptr;
340 struct loaded_vmcs vmcs02;
341};
342
ec378aee
NHE		 343/*
344 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
345 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 */
347struct nested_vmx {
348 /* Has the level1 guest done vmxon? */
349 bool vmxon;
a9d30f33
NHE		 350
351 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 gpa_t current_vmptr;
353 /* The host-usable pointer to the above */
354 struct page *current_vmcs12_page;
355 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 356
357 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
358 struct list_head vmcs02_pool;
359 int vmcs02_num;
fe3ef05c 360 u64 vmcs01_tsc_offset;
644d711a
NHE		 361 /* L2 must run next, and mustn't decide to exit to L1. */
362 bool nested_run_pending;
fe3ef05c
NHE		 363 /*
364 * Guest pages referred to in vmcs02 with host-physical pointers, so
365 * we must keep them pinned while L2 runs.
366 */
367 struct page *apic_access_page;
ec378aee
NHE		 368};
369
a2fa3e9f 370struct vcpu_vmx {
fb3f0f51 371 struct kvm_vcpu vcpu;
313dbd49 372 unsigned long host_rsp;
29bd8a78 373 u8 fail;
69c73028 374 u8 cpl;
9d58b931 375 bool nmi_known_unmasked;
51aa01d1 376 u32 exit_intr_info;
1155f76a 377 u32 idt_vectoring_info;
6de12732 378 ulong rflags;
26bb0981 379 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 380 int nmsrs;
381 int save_nmsrs;
a2fa3e9f 382#ifdef CONFIG_X86_64
44ea2b17
AK		 383 u64 msr_host_kernel_gs_base;
384 u64 msr_guest_kernel_gs_base;
a2fa3e9f 385#endif
d462b819
NHE		 386 /*
387 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
388 * non-nested (L1) guest, it always points to vmcs01. For a nested
389 * guest (L2), it points to a different VMCS.
390 */
391 struct loaded_vmcs vmcs01;
392 struct loaded_vmcs *loaded_vmcs;
393 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 394 struct msr_autoload {
395 unsigned nr;
396 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
397 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
398 } msr_autoload;
a2fa3e9f
GH		 399 struct {
400 int loaded;
401 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 402#ifdef CONFIG_X86_64
403 u16 ds_sel, es_sel;
404#endif
152d3f2f
LV		 405 int gs_ldt_reload_needed;
406 int fs_reload_needed;
d77c26fc 407 } host_state;
9c8cba37 408 struct {
7ffd92c5 409 int vm86_active;
78ac8b47 410 ulong save_rflags;
f5f7b2fe
AK		 411 struct kvm_segment segs[8];
412 } rmode;
413 struct {
414 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 415 struct kvm_save_segment {
416 u16 selector;
417 unsigned long base;
418 u32 limit;
419 u32 ar;
f5f7b2fe 420 } seg[8];
2fb92db1 421 } segment_cache;
2384d2b3 422 int vpid;
04fa4d32 423 bool emulation_required;
3b86cd99
JK		 424
425 /* Support for vnmi-less CPUs */
426 int soft_vnmi_blocked;
427 ktime_t entry_time;
428 s64 vnmi_blocked_time;
a0861c02 429 u32 exit_reason;
4e47c7a6
SY		 430
431 bool rdtscp_enabled;
ec378aee
NHE		 432
433 /* Support for a guest hypervisor (nested VMX) */
434 struct nested_vmx nested;
a2fa3e9f
GH		 435};
436
2fb92db1
AK		 437enum segment_cache_field {
438 SEG_FIELD_SEL = 0,
439 SEG_FIELD_BASE = 1,
440 SEG_FIELD_LIMIT = 2,
441 SEG_FIELD_AR = 3,
442
443 SEG_FIELD_NR = 4
444};
445
a2fa3e9f
GH		 446static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
447{
fb3f0f51 448 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 449}
450
22bd0358
NHE		 451#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
452#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
453#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
454 [number##_HIGH] = VMCS12_OFFSET(name)+4
455
772e0318 456static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 457 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
458 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
459 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
460 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
461 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
462 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
463 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
464 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
465 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
466 FIELD(HOST_ES_SELECTOR, host_es_selector),
467 FIELD(HOST_CS_SELECTOR, host_cs_selector),
468 FIELD(HOST_SS_SELECTOR, host_ss_selector),
469 FIELD(HOST_DS_SELECTOR, host_ds_selector),
470 FIELD(HOST_FS_SELECTOR, host_fs_selector),
471 FIELD(HOST_GS_SELECTOR, host_gs_selector),
472 FIELD(HOST_TR_SELECTOR, host_tr_selector),
473 FIELD64(IO_BITMAP_A, io_bitmap_a),
474 FIELD64(IO_BITMAP_B, io_bitmap_b),
475 FIELD64(MSR_BITMAP, msr_bitmap),
476 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
477 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
478 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
479 FIELD64(TSC_OFFSET, tsc_offset),
480 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
481 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
482 FIELD64(EPT_POINTER, ept_pointer),
483 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
484 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
485 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
486 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
487 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
488 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
489 FIELD64(GUEST_PDPTR0, guest_pdptr0),
490 FIELD64(GUEST_PDPTR1, guest_pdptr1),
491 FIELD64(GUEST_PDPTR2, guest_pdptr2),
492 FIELD64(GUEST_PDPTR3, guest_pdptr3),
493 FIELD64(HOST_IA32_PAT, host_ia32_pat),
494 FIELD64(HOST_IA32_EFER, host_ia32_efer),
495 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
496 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
497 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
498 FIELD(EXCEPTION_BITMAP, exception_bitmap),
499 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
500 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
501 FIELD(CR3_TARGET_COUNT, cr3_target_count),
502 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
503 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
504 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
505 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
506 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
507 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
508 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
509 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
510 FIELD(TPR_THRESHOLD, tpr_threshold),
511 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
512 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
513 FIELD(VM_EXIT_REASON, vm_exit_reason),
514 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
515 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
516 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
517 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
518 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
519 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
520 FIELD(GUEST_ES_LIMIT, guest_es_limit),
521 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
522 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
523 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
524 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
525 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
526 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
527 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
528 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
529 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
530 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
531 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
532 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
533 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
534 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
535 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
536 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
537 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
538 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
539 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
540 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
541 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
542 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
543 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
544 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
545 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
546 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
547 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
548 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
549 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
550 FIELD(EXIT_QUALIFICATION, exit_qualification),
551 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
552 FIELD(GUEST_CR0, guest_cr0),
553 FIELD(GUEST_CR3, guest_cr3),
554 FIELD(GUEST_CR4, guest_cr4),
555 FIELD(GUEST_ES_BASE, guest_es_base),
556 FIELD(GUEST_CS_BASE, guest_cs_base),
557 FIELD(GUEST_SS_BASE, guest_ss_base),
558 FIELD(GUEST_DS_BASE, guest_ds_base),
559 FIELD(GUEST_FS_BASE, guest_fs_base),
560 FIELD(GUEST_GS_BASE, guest_gs_base),
561 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
562 FIELD(GUEST_TR_BASE, guest_tr_base),
563 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
564 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
565 FIELD(GUEST_DR7, guest_dr7),
566 FIELD(GUEST_RSP, guest_rsp),
567 FIELD(GUEST_RIP, guest_rip),
568 FIELD(GUEST_RFLAGS, guest_rflags),
569 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
570 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
571 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
572 FIELD(HOST_CR0, host_cr0),
573 FIELD(HOST_CR3, host_cr3),
574 FIELD(HOST_CR4, host_cr4),
575 FIELD(HOST_FS_BASE, host_fs_base),
576 FIELD(HOST_GS_BASE, host_gs_base),
577 FIELD(HOST_TR_BASE, host_tr_base),
578 FIELD(HOST_GDTR_BASE, host_gdtr_base),
579 FIELD(HOST_IDTR_BASE, host_idtr_base),
580 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
581 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
582 FIELD(HOST_RSP, host_rsp),
583 FIELD(HOST_RIP, host_rip),
584};
585static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
586
587static inline short vmcs_field_to_offset(unsigned long field)
588{
589 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
590 return -1;
591 return vmcs_field_to_offset_table[field];
592}
593
a9d30f33
NHE		 594static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
595{
596 return to_vmx(vcpu)->nested.current_vmcs12;
597}
598
599static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
600{
601 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 602 if (is_error_page(page))
a9d30f33 603 return NULL;
32cad84f 604
a9d30f33
NHE		 605 return page;
606}
607
608static void nested_release_page(struct page *page)
609{
610 kvm_release_page_dirty(page);
611}
612
613static void nested_release_page_clean(struct page *page)
614{
615 kvm_release_page_clean(page);
616}
617
4e1096d2 618static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 619static void kvm_cpu_vmxon(u64 addr);
620static void kvm_cpu_vmxoff(void);
aff48baa 621static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 622static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 623static void vmx_set_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
625static void vmx_get_segment(struct kvm_vcpu *vcpu,
626 struct kvm_segment *var, int seg);
75880a01 627
6aa8b732
AK		 628static DEFINE_PER_CPU(struct vmcs *, vmxarea);
629static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 630/*
631 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
632 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
633 */
634static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 635static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 636
3e7c73e9
AK		 637static unsigned long *vmx_io_bitmap_a;
638static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 639static unsigned long *vmx_msr_bitmap_legacy;
640static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 641
110312c8 642static bool cpu_has_load_ia32_efer;
8bf00a52 643static bool cpu_has_load_perf_global_ctrl;
110312c8 644
2384d2b3
SY		 645static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
646static DEFINE_SPINLOCK(vmx_vpid_lock);
647
1c3d14fe 648static struct vmcs_config {
6aa8b732
AK		 649 int size;
650 int order;
651 u32 revision_id;
1c3d14fe
YS		 652 u32 pin_based_exec_ctrl;
653 u32 cpu_based_exec_ctrl;
f78e0e2e 654 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 655 u32 vmexit_ctrl;
656 u32 vmentry_ctrl;
657} vmcs_config;
6aa8b732 658
efff9e53 659static struct vmx_capability {
d56f546d
SY		 660 u32 ept;
661 u32 vpid;
662} vmx_capability;
663
6aa8b732
AK		 664#define VMX_SEGMENT_FIELD(seg) \
665 [VCPU_SREG_##seg] = { \
666 .selector = GUEST_##seg##_SELECTOR, \
667 .base = GUEST_##seg##_BASE, \
668 .limit = GUEST_##seg##_LIMIT, \
669 .ar_bytes = GUEST_##seg##_AR_BYTES, \
670 }
671
772e0318 672static const struct kvm_vmx_segment_field {
6aa8b732
AK		 673 unsigned selector;
674 unsigned base;
675 unsigned limit;
676 unsigned ar_bytes;
677} kvm_vmx_segment_fields[] = {
678 VMX_SEGMENT_FIELD(CS),
679 VMX_SEGMENT_FIELD(DS),
680 VMX_SEGMENT_FIELD(ES),
681 VMX_SEGMENT_FIELD(FS),
682 VMX_SEGMENT_FIELD(GS),
683 VMX_SEGMENT_FIELD(SS),
684 VMX_SEGMENT_FIELD(TR),
685 VMX_SEGMENT_FIELD(LDTR),
686};
687
26bb0981
AK		 688static u64 host_efer;
689
6de4f3ad
AK		 690static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
691
4d56c8a7 692/*
8c06585d 693 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 694 * away by decrementing the array size.
695 */
6aa8b732 696static const u32 vmx_msr_index[] = {
05b3e0c2 697#ifdef CONFIG_X86_64
44ea2b17 698 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 699#endif
8c06585d 700 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 701};
9d8f549d 702#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 703
31299944 704static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 705{
706 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
707 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 708 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 709}
710
31299944 711static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 712{
713 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
714 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 715 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 716}
717
31299944 718static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 719{
720 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
721 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 722 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 723}
724
31299944 725static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 726{
727 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
728 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
729}
730
31299944 731static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 732{
733 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
734 INTR_INFO_VALID_MASK)) ==
735 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
736}
737
31299944 738static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 739{
04547156 740 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 741}
742
31299944 743static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 744{
04547156 745 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 746}
747
31299944 748static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 749{
04547156 750 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 751}
752
31299944 753static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 754{
04547156
SY		 755 return vmcs_config.cpu_based_exec_ctrl &
756 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 757}
758
774ead3a 759static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 760{
04547156
SY		 761 return vmcs_config.cpu_based_2nd_exec_ctrl &
762 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
763}
764
765static inline bool cpu_has_vmx_flexpriority(void)
766{
767 return cpu_has_vmx_tpr_shadow() &&
768 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 769}
770
e799794e
MT		 771static inline bool cpu_has_vmx_ept_execute_only(void)
772{
31299944 773 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 774}
775
776static inline bool cpu_has_vmx_eptp_uncacheable(void)
777{
31299944 778 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 779}
780
781static inline bool cpu_has_vmx_eptp_writeback(void)
782{
31299944 783 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 784}
785
786static inline bool cpu_has_vmx_ept_2m_page(void)
787{
31299944 788 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 789}
790
878403b7
SY		 791static inline bool cpu_has_vmx_ept_1g_page(void)
792{
31299944 793 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 794}
795
4bc9b982
SY		 796static inline bool cpu_has_vmx_ept_4levels(void)
797{
798 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
799}
800
83c3a331
XH		 801static inline bool cpu_has_vmx_ept_ad_bits(void)
802{
803 return vmx_capability.ept & VMX_EPT_AD_BIT;
804}
805
31299944 806static inline bool cpu_has_vmx_invept_context(void)
d56f546d 807{
31299944 808 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 809}
810
31299944 811static inline bool cpu_has_vmx_invept_global(void)
d56f546d 812{
31299944 813 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 814}
815
518c8aee
GJ		 816static inline bool cpu_has_vmx_invvpid_single(void)
817{
818 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
819}
820
b9d762fa
GJ		 821static inline bool cpu_has_vmx_invvpid_global(void)
822{
823 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
824}
825
31299944 826static inline bool cpu_has_vmx_ept(void)
d56f546d 827{
04547156
SY		 828 return vmcs_config.cpu_based_2nd_exec_ctrl &
829 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 830}
831
31299944 832static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 833{
834 return vmcs_config.cpu_based_2nd_exec_ctrl &
835 SECONDARY_EXEC_UNRESTRICTED_GUEST;
836}
837
31299944 838static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 839{
840 return vmcs_config.cpu_based_2nd_exec_ctrl &
841 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
842}
843
31299944 844static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 845{
6d3e435e 846 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_vpid(void)
2384d2b3 850{
04547156
SY		 851 return vmcs_config.cpu_based_2nd_exec_ctrl &
852 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 853}
854
31299944 855static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 856{
857 return vmcs_config.cpu_based_2nd_exec_ctrl &
858 SECONDARY_EXEC_RDTSCP;
859}
860
ad756a16
MJ		 861static inline bool cpu_has_vmx_invpcid(void)
862{
863 return vmcs_config.cpu_based_2nd_exec_ctrl &
864 SECONDARY_EXEC_ENABLE_INVPCID;
865}
866
31299944 867static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 868{
869 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
870}
871
f5f48ee1
SY		 872static inline bool cpu_has_vmx_wbinvd_exit(void)
873{
874 return vmcs_config.cpu_based_2nd_exec_ctrl &
875 SECONDARY_EXEC_WBINVD_EXITING;
876}
877
04547156
SY		 878static inline bool report_flexpriority(void)
879{
880 return flexpriority_enabled;
881}
882
fe3ef05c
NHE		 883static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
884{
885 return vmcs12->cpu_based_vm_exec_control & bit;
886}
887
888static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
889{
890 return (vmcs12->cpu_based_vm_exec_control &
891 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
892 (vmcs12->secondary_vm_exec_control & bit);
893}
894
644d711a
NHE		 895static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
896 struct kvm_vcpu *vcpu)
897{
898 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
899}
900
901static inline bool is_exception(u32 intr_info)
902{
903 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
904 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
905}
906
907static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 908static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
909 struct vmcs12 *vmcs12,
910 u32 reason, unsigned long qualification);
911
8b9cf98c 912static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 913{
914 int i;
915
a2fa3e9f 916 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 917 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 918 return i;
919 return -1;
920}
921
2384d2b3
SY		 922static inline void __invvpid(int ext, u16 vpid, gva_t gva)
923{
924 struct {
925 u64 vpid : 16;
926 u64 rsvd : 48;
927 u64 gva;
928 } operand = { vpid, 0, gva };
929
4ecac3fd 930 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 931 /* CF==1 or ZF==1 --> rc = -1 */
932 "; ja 1f ; ud2 ; 1:"
933 : : "a"(&operand), "c"(ext) : "cc", "memory");
934}
935
1439442c
SY		 936static inline void __invept(int ext, u64 eptp, gpa_t gpa)
937{
938 struct {
939 u64 eptp, gpa;
940 } operand = {eptp, gpa};
941
4ecac3fd 942 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 943 /* CF==1 or ZF==1 --> rc = -1 */
944 "; ja 1f ; ud2 ; 1:\n"
945 : : "a" (&operand), "c" (ext) : "cc", "memory");
946}
947
26bb0981 948static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 949{
950 int i;
951
8b9cf98c 952 i = __find_msr_index(vmx, msr);
a75beee6 953 if (i >= 0)
a2fa3e9f 954 return &vmx->guest_msrs[i];
8b6d44c7 955 return NULL;
7725f0ba
AK		 956}
957
6aa8b732
AK		 958static void vmcs_clear(struct vmcs *vmcs)
959{
960 u64 phys_addr = __pa(vmcs);
961 u8 error;
962
4ecac3fd 963 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 964 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 965 : "cc", "memory");
966 if (error)
967 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
968 vmcs, phys_addr);
969}
970
d462b819
NHE		 971static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
972{
973 vmcs_clear(loaded_vmcs->vmcs);
974 loaded_vmcs->cpu = -1;
975 loaded_vmcs->launched = 0;
976}
977
7725b894
DX		 978static void vmcs_load(struct vmcs *vmcs)
979{
980 u64 phys_addr = __pa(vmcs);
981 u8 error;
982
983 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 984 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 985 : "cc", "memory");
986 if (error)
2844d849 987 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 988 vmcs, phys_addr);
989}
990
8f536b76
ZY		 991#ifdef CONFIG_KEXEC
992/*
993 * This bitmap is used to indicate whether the vmclear
994 * operation is enabled on all cpus. All disabled by
995 * default.
996 */
997static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
998
999static inline void crash_enable_local_vmclear(int cpu)
1000{
1001 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1002}
1003
1004static inline void crash_disable_local_vmclear(int cpu)
1005{
1006 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1007}
1008
1009static inline int crash_local_vmclear_enabled(int cpu)
1010{
1011 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1012}
1013
1014static void crash_vmclear_local_loaded_vmcss(void)
1015{
1016 int cpu = raw_smp_processor_id();
1017 struct loaded_vmcs *v;
1018
1019 if (!crash_local_vmclear_enabled(cpu))
1020 return;
1021
1022 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1023 loaded_vmcss_on_cpu_link)
1024 vmcs_clear(v->vmcs);
1025}
1026#else
1027static inline void crash_enable_local_vmclear(int cpu) { }
1028static inline void crash_disable_local_vmclear(int cpu) { }
1029#endif /* CONFIG_KEXEC */
1030
d462b819 1031static void __loaded_vmcs_clear(void *arg)
6aa8b732 1032{
d462b819 1033 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1034 int cpu = raw_smp_processor_id();
6aa8b732 1035
d462b819
NHE		 1036 if (loaded_vmcs->cpu != cpu)
1037 return; /* vcpu migration can race with cpu offline */
1038 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1039 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1040 crash_disable_local_vmclear(cpu);
d462b819 1041 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1042
1043 /*
1044 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1045 * is before setting loaded_vmcs->vcpu to -1 which is done in
1046 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1047 * then adds the vmcs into percpu list before it is deleted.
1048 */
1049 smp_wmb();
1050
d462b819 1051 loaded_vmcs_init(loaded_vmcs);
8f536b76 1052 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1053}
1054
d462b819 1055static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1056{
e6c7d321
XG		 1057 int cpu = loaded_vmcs->cpu;
1058
1059 if (cpu != -1)
1060 smp_call_function_single(cpu,
1061 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1062}
1063
1760dd49 1064static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1065{
1066 if (vmx->vpid == 0)
1067 return;
1068
518c8aee
GJ		 1069 if (cpu_has_vmx_invvpid_single())
1070 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1071}
1072
b9d762fa
GJ		 1073static inline void vpid_sync_vcpu_global(void)
1074{
1075 if (cpu_has_vmx_invvpid_global())
1076 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1077}
1078
1079static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1080{
1081 if (cpu_has_vmx_invvpid_single())
1760dd49 1082 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1083 else
1084 vpid_sync_vcpu_global();
1085}
1086
1439442c
SY		 1087static inline void ept_sync_global(void)
1088{
1089 if (cpu_has_vmx_invept_global())
1090 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1091}
1092
1093static inline void ept_sync_context(u64 eptp)
1094{
089d034e 1095 if (enable_ept) {
1439442c
SY		 1096 if (cpu_has_vmx_invept_context())
1097 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1098 else
1099 ept_sync_global();
1100 }
1101}
1102
96304217 1103static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1104{
5e520e62 1105 unsigned long value;
6aa8b732 1106
5e520e62
AK		 1107 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1108 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1109 return value;
1110}
1111
96304217 1112static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1113{
1114 return vmcs_readl(field);
1115}
1116
96304217 1117static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1118{
1119 return vmcs_readl(field);
1120}
1121
96304217 1122static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1123{
05b3e0c2 1124#ifdef CONFIG_X86_64
6aa8b732
AK		 1125 return vmcs_readl(field);
1126#else
1127 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1128#endif
1129}
1130
e52de1b8
AK		 1131static noinline void vmwrite_error(unsigned long field, unsigned long value)
1132{
1133 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1134 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1135 dump_stack();
1136}
1137
6aa8b732
AK		 1138static void vmcs_writel(unsigned long field, unsigned long value)
1139{
1140 u8 error;
1141
4ecac3fd 1142 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1143 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1144 if (unlikely(error))
1145 vmwrite_error(field, value);
6aa8b732
AK		 1146}
1147
1148static void vmcs_write16(unsigned long field, u16 value)
1149{
1150 vmcs_writel(field, value);
1151}
1152
1153static void vmcs_write32(unsigned long field, u32 value)
1154{
1155 vmcs_writel(field, value);
1156}
1157
1158static void vmcs_write64(unsigned long field, u64 value)
1159{
6aa8b732 1160 vmcs_writel(field, value);
7682f2d0 1161#ifndef CONFIG_X86_64
6aa8b732
AK		 1162 asm volatile ("");
1163 vmcs_writel(field+1, value >> 32);
1164#endif
1165}
1166
2ab455cc
AL		 1167static void vmcs_clear_bits(unsigned long field, u32 mask)
1168{
1169 vmcs_writel(field, vmcs_readl(field) & ~mask);
1170}
1171
1172static void vmcs_set_bits(unsigned long field, u32 mask)
1173{
1174 vmcs_writel(field, vmcs_readl(field) | mask);
1175}
1176
2fb92db1
AK		 1177static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1178{
1179 vmx->segment_cache.bitmask = 0;
1180}
1181
1182static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1183 unsigned field)
1184{
1185 bool ret;
1186 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1187
1188 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1189 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1190 vmx->segment_cache.bitmask = 0;
1191 }
1192 ret = vmx->segment_cache.bitmask & mask;
1193 vmx->segment_cache.bitmask |= mask;
1194 return ret;
1195}
1196
1197static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1198{
1199 u16 *p = &vmx->segment_cache.seg[seg].selector;
1200
1201 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1202 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1203 return *p;
1204}
1205
1206static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1207{
1208 ulong *p = &vmx->segment_cache.seg[seg].base;
1209
1210 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1211 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1212 return *p;
1213}
1214
1215static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1216{
1217 u32 *p = &vmx->segment_cache.seg[seg].limit;
1218
1219 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1220 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1221 return *p;
1222}
1223
1224static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1225{
1226 u32 *p = &vmx->segment_cache.seg[seg].ar;
1227
1228 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1229 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1230 return *p;
1231}
1232
abd3f2d6
AK		 1233static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1234{
1235 u32 eb;
1236
fd7373cc
JK		 1237 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1238 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1239 if ((vcpu->guest_debug &
1240 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1241 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1242 eb |= 1u << BP_VECTOR;
7ffd92c5 1243 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1244 eb = ~0;
089d034e 1245 if (enable_ept)
1439442c 1246 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1247 if (vcpu->fpu_active)
1248 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1249
1250 /* When we are running a nested L2 guest and L1 specified for it a
1251 * certain exception bitmap, we must trap the same exceptions and pass
1252 * them to L1. When running L2, we will only handle the exceptions
1253 * specified above if L1 did not want them.
1254 */
1255 if (is_guest_mode(vcpu))
1256 eb |= get_vmcs12(vcpu)->exception_bitmap;
1257
abd3f2d6
AK		 1258 vmcs_write32(EXCEPTION_BITMAP, eb);
1259}
1260
8bf00a52
GN		 1261static void clear_atomic_switch_msr_special(unsigned long entry,
1262 unsigned long exit)
1263{
1264 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1265 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1266}
1267
61d2ef2c
AK		 1268static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1269{
1270 unsigned i;
1271 struct msr_autoload *m = &vmx->msr_autoload;
1272
8bf00a52
GN		 1273 switch (msr) {
1274 case MSR_EFER:
1275 if (cpu_has_load_ia32_efer) {
1276 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1277 VM_EXIT_LOAD_IA32_EFER);
1278 return;
1279 }
1280 break;
1281 case MSR_CORE_PERF_GLOBAL_CTRL:
1282 if (cpu_has_load_perf_global_ctrl) {
1283 clear_atomic_switch_msr_special(
1284 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1285 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1286 return;
1287 }
1288 break;
110312c8
AK		 1289 }
1290
61d2ef2c
AK		 1291 for (i = 0; i < m->nr; ++i)
1292 if (m->guest[i].index == msr)
1293 break;
1294
1295 if (i == m->nr)
1296 return;
1297 --m->nr;
1298 m->guest[i] = m->guest[m->nr];
1299 m->host[i] = m->host[m->nr];
1300 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1301 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1302}
1303
8bf00a52
GN		 1304static void add_atomic_switch_msr_special(unsigned long entry,
1305 unsigned long exit, unsigned long guest_val_vmcs,
1306 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1307{
1308 vmcs_write64(guest_val_vmcs, guest_val);
1309 vmcs_write64(host_val_vmcs, host_val);
1310 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1311 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1312}
1313
61d2ef2c
AK		 1314static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1315 u64 guest_val, u64 host_val)
1316{
1317 unsigned i;
1318 struct msr_autoload *m = &vmx->msr_autoload;
1319
8bf00a52
GN		 1320 switch (msr) {
1321 case MSR_EFER:
1322 if (cpu_has_load_ia32_efer) {
1323 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1324 VM_EXIT_LOAD_IA32_EFER,
1325 GUEST_IA32_EFER,
1326 HOST_IA32_EFER,
1327 guest_val, host_val);
1328 return;
1329 }
1330 break;
1331 case MSR_CORE_PERF_GLOBAL_CTRL:
1332 if (cpu_has_load_perf_global_ctrl) {
1333 add_atomic_switch_msr_special(
1334 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1335 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1336 GUEST_IA32_PERF_GLOBAL_CTRL,
1337 HOST_IA32_PERF_GLOBAL_CTRL,
1338 guest_val, host_val);
1339 return;
1340 }
1341 break;
110312c8
AK		 1342 }
1343
61d2ef2c
AK		 1344 for (i = 0; i < m->nr; ++i)
1345 if (m->guest[i].index == msr)
1346 break;
1347
e7fc6f93
GN		 1348 if (i == NR_AUTOLOAD_MSRS) {
1349 printk_once(KERN_WARNING"Not enough mst switch entries. "
1350 "Can't add msr %x\n", msr);
1351 return;
1352 } else if (i == m->nr) {
61d2ef2c
AK		 1353 ++m->nr;
1354 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1355 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1356 }
1357
1358 m->guest[i].index = msr;
1359 m->guest[i].value = guest_val;
1360 m->host[i].index = msr;
1361 m->host[i].value = host_val;
1362}
1363
33ed6329
AK		 1364static void reload_tss(void)
1365{
33ed6329
AK		 1366 /*
1367 * VT restores TR but not its size. Useless.
1368 */
d359192f 1369 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1370 struct desc_struct *descs;
33ed6329 1371
d359192f 1372 descs = (void *)gdt->address;
33ed6329
AK		 1373 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1374 load_TR_desc();
33ed6329
AK		 1375}
1376
92c0d900 1377static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1378{
3a34a881 1379 u64 guest_efer;
51c6cf66
AK		 1380 u64 ignore_bits;
1381
f6801dff 1382 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1383
51c6cf66 1384 /*
0fa06071 1385 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1386 * outside long mode
1387 */
1388 ignore_bits = EFER_NX | EFER_SCE;
1389#ifdef CONFIG_X86_64
1390 ignore_bits |= EFER_LMA | EFER_LME;
1391 /* SCE is meaningful only in long mode on Intel */
1392 if (guest_efer & EFER_LMA)
1393 ignore_bits &= ~(u64)EFER_SCE;
1394#endif
51c6cf66
AK		 1395 guest_efer &= ~ignore_bits;
1396 guest_efer |= host_efer & ignore_bits;
26bb0981 1397 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1398 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1399
1400 clear_atomic_switch_msr(vmx, MSR_EFER);
1401 /* On ept, can't emulate nx, and must switch nx atomically */
1402 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1403 guest_efer = vmx->vcpu.arch.efer;
1404 if (!(guest_efer & EFER_LMA))
1405 guest_efer &= ~EFER_LME;
1406 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1407 return false;
1408 }
1409
26bb0981 1410 return true;
51c6cf66
AK		 1411}
1412
2d49ec72
GN		 1413static unsigned long segment_base(u16 selector)
1414{
d359192f 1415 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1416 struct desc_struct *d;
1417 unsigned long table_base;
1418 unsigned long v;
1419
1420 if (!(selector & ~3))
1421 return 0;
1422
d359192f 1423 table_base = gdt->address;
2d49ec72
GN		 1424
1425 if (selector & 4) { /* from ldt */
1426 u16 ldt_selector = kvm_read_ldt();
1427
1428 if (!(ldt_selector & ~3))
1429 return 0;
1430
1431 table_base = segment_base(ldt_selector);
1432 }
1433 d = (struct desc_struct *)(table_base + (selector & ~7));
1434 v = get_desc_base(d);
1435#ifdef CONFIG_X86_64
1436 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1437 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1438#endif
1439 return v;
1440}
1441
1442static inline unsigned long kvm_read_tr_base(void)
1443{
1444 u16 tr;
1445 asm("str %0" : "=g"(tr));
1446 return segment_base(tr);
1447}
1448
04d2cc77 1449static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1450{
04d2cc77 1451 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1452 int i;
04d2cc77 1453
a2fa3e9f 1454 if (vmx->host_state.loaded)
33ed6329
AK		 1455 return;
1456
a2fa3e9f 1457 vmx->host_state.loaded = 1;
33ed6329
AK		 1458 /*
1459 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1460 * allow segment selectors with cpl > 0 or ti == 1.
1461 */
d6e88aec 1462 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1463 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1464 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1465 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1466 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1467 vmx->host_state.fs_reload_needed = 0;
1468 } else {
33ed6329 1469 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1470 vmx->host_state.fs_reload_needed = 1;
33ed6329 1471 }
9581d442 1472 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1473 if (!(vmx->host_state.gs_sel & 7))
1474 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1475 else {
1476 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1477 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1478 }
1479
b2da15ac
AK		 1480#ifdef CONFIG_X86_64
1481 savesegment(ds, vmx->host_state.ds_sel);
1482 savesegment(es, vmx->host_state.es_sel);
1483#endif
1484
33ed6329
AK		 1485#ifdef CONFIG_X86_64
1486 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1487 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1488#else
a2fa3e9f
GH		 1489 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1490 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1491#endif
707c0874
AK		 1492
1493#ifdef CONFIG_X86_64
c8770e7b
AK		 1494 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1495 if (is_long_mode(&vmx->vcpu))
44ea2b17 1496 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1497#endif
26bb0981
AK		 1498 for (i = 0; i < vmx->save_nmsrs; ++i)
1499 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1500 vmx->guest_msrs[i].data,
1501 vmx->guest_msrs[i].mask);
33ed6329
AK		 1502}
1503
a9b21b62 1504static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1505{
a2fa3e9f 1506 if (!vmx->host_state.loaded)
33ed6329
AK		 1507 return;
1508
e1beb1d3 1509 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1510 vmx->host_state.loaded = 0;
c8770e7b
AK		 1511#ifdef CONFIG_X86_64
1512 if (is_long_mode(&vmx->vcpu))
1513 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1514#endif
152d3f2f 1515 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1516 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1517#ifdef CONFIG_X86_64
9581d442 1518 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1519#else
1520 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1521#endif
33ed6329 1522 }
0a77fe4c
AK		 1523 if (vmx->host_state.fs_reload_needed)
1524 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1525#ifdef CONFIG_X86_64
1526 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1527 loadsegment(ds, vmx->host_state.ds_sel);
1528 loadsegment(es, vmx->host_state.es_sel);
1529 }
b2da15ac 1530#endif
152d3f2f 1531 reload_tss();
44ea2b17 1532#ifdef CONFIG_X86_64
c8770e7b 1533 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1534#endif
b1a74bf8
SS		 1535 /*
1536 * If the FPU is not active (through the host task or
1537 * the guest vcpu), then restore the cr0.TS bit.
1538 */
1539 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1540 stts();
3444d7da 1541 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1542}
1543
a9b21b62
AK		 1544static void vmx_load_host_state(struct vcpu_vmx *vmx)
1545{
1546 preempt_disable();
1547 __vmx_load_host_state(vmx);
1548 preempt_enable();
1549}
1550
6aa8b732
AK		 1551/*
1552 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1553 * vcpu mutex is already taken.
1554 */
15ad7146 1555static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1556{
a2fa3e9f 1557 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1558 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1559
4610c9cc
DX		 1560 if (!vmm_exclusive)
1561 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1562 else if (vmx->loaded_vmcs->cpu != cpu)
1563 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1564
d462b819
NHE		 1565 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1566 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1567 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1568 }
1569
d462b819 1570 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1571 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1572 unsigned long sysenter_esp;
1573
a8eeb04a 1574 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1575 local_irq_disable();
8f536b76 1576 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1577
1578 /*
1579 * Read loaded_vmcs->cpu should be before fetching
1580 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1581 * See the comments in __loaded_vmcs_clear().
1582 */
1583 smp_rmb();
1584
d462b819
NHE		 1585 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1586 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1587 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1588 local_irq_enable();
1589
6aa8b732
AK		 1590 /*
1591 * Linux uses per-cpu TSS and GDT, so set these when switching
1592 * processors.
1593 */
d6e88aec 1594 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1595 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1596
1597 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1598 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1599 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1600 }
6aa8b732
AK		 1601}
1602
1603static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1604{
a9b21b62 1605 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1606 if (!vmm_exclusive) {
d462b819
NHE		 1607 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1608 vcpu->cpu = -1;
4610c9cc
DX		 1609 kvm_cpu_vmxoff();
1610 }
6aa8b732
AK		 1611}
1612
5fd86fcf
AK		 1613static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1614{
81231c69
AK		 1615 ulong cr0;
1616
5fd86fcf
AK		 1617 if (vcpu->fpu_active)
1618 return;
1619 vcpu->fpu_active = 1;
81231c69
AK		 1620 cr0 = vmcs_readl(GUEST_CR0);
1621 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1622 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1623 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1624 update_exception_bitmap(vcpu);
edcafe3c 1625 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1626 if (is_guest_mode(vcpu))
1627 vcpu->arch.cr0_guest_owned_bits &=
1628 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1629 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1630}
1631
edcafe3c
AK		 1632static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1633
fe3ef05c
NHE		 1634/*
1635 * Return the cr0 value that a nested guest would read. This is a combination
1636 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1637 * its hypervisor (cr0_read_shadow).
1638 */
1639static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1640{
1641 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1642 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1643}
1644static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1645{
1646 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1647 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1648}
1649
5fd86fcf
AK		 1650static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1651{
36cf24e0
NHE		 1652 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1653 * set this *before* calling this function.
1654 */
edcafe3c 1655 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1656 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1657 update_exception_bitmap(vcpu);
edcafe3c
AK		 1658 vcpu->arch.cr0_guest_owned_bits = 0;
1659 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1660 if (is_guest_mode(vcpu)) {
1661 /*
1662 * L1's specified read shadow might not contain the TS bit,
1663 * so now that we turned on shadowing of this bit, we need to
1664 * set this bit of the shadow. Like in nested_vmx_run we need
1665 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1666 * up-to-date here because we just decached cr0.TS (and we'll
1667 * only update vmcs12->guest_cr0 on nested exit).
1668 */
1669 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1670 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1671 (vcpu->arch.cr0 & X86_CR0_TS);
1672 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1673 } else
1674 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1675}
1676
6aa8b732
AK		 1677static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1678{
78ac8b47 1679 unsigned long rflags, save_rflags;
345dcaa8 1680
6de12732
AK		 1681 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1682 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1683 rflags = vmcs_readl(GUEST_RFLAGS);
1684 if (to_vmx(vcpu)->rmode.vm86_active) {
1685 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1686 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1687 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1688 }
1689 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1690 }
6de12732 1691 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1692}
1693
1694static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1695{
6de12732 1696 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1697 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1698 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1699 if (to_vmx(vcpu)->rmode.vm86_active) {
1700 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1701 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1702 }
6aa8b732
AK		 1703 vmcs_writel(GUEST_RFLAGS, rflags);
1704}
1705
2809f5d2
GC		 1706static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1707{
1708 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1709 int ret = 0;
1710
1711 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1712 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1713 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1714 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1715
1716 return ret & mask;
1717}
1718
1719static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1720{
1721 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1722 u32 interruptibility = interruptibility_old;
1723
1724 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1725
48005f64 1726 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1727 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1728 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1729 interruptibility |= GUEST_INTR_STATE_STI;
1730
1731 if ((interruptibility != interruptibility_old))
1732 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1733}
1734
6aa8b732
AK		 1735static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1736{
1737 unsigned long rip;
6aa8b732 1738
5fdbf976 1739 rip = kvm_rip_read(vcpu);
6aa8b732 1740 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1741 kvm_rip_write(vcpu, rip);
6aa8b732 1742
2809f5d2
GC		 1743 /* skipping an emulated instruction also counts */
1744 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1745}
1746
0b6ac343
NHE		 1747/*
1748 * KVM wants to inject page-faults which it got to the guest. This function
1749 * checks whether in a nested guest, we need to inject them to L1 or L2.
1750 * This function assumes it is called with the exit reason in vmcs02 being
1751 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1752 * is running).
1753 */
1754static int nested_pf_handled(struct kvm_vcpu *vcpu)
1755{
1756 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1757
1758 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1759 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1760 return 0;
1761
1762 nested_vmx_vmexit(vcpu);
1763 return 1;
1764}
1765
298101da 1766static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1767 bool has_error_code, u32 error_code,
1768 bool reinject)
298101da 1769{
77ab6db0 1770 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1771 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1772
0b6ac343
NHE		 1773 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1774 nested_pf_handled(vcpu))
1775 return;
1776
8ab2d2e2 1777 if (has_error_code) {
77ab6db0 1778 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1779 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1780 }
77ab6db0 1781
7ffd92c5 1782 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1783 int inc_eip = 0;
1784 if (kvm_exception_is_soft(nr))
1785 inc_eip = vcpu->arch.event_exit_inst_len;
1786 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1787 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1788 return;
1789 }
1790
66fd3f7f
GN		 1791 if (kvm_exception_is_soft(nr)) {
1792 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1793 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1794 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1795 } else
1796 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1797
1798 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1799}
1800
4e47c7a6
SY		 1801static bool vmx_rdtscp_supported(void)
1802{
1803 return cpu_has_vmx_rdtscp();
1804}
1805
ad756a16
MJ		 1806static bool vmx_invpcid_supported(void)
1807{
1808 return cpu_has_vmx_invpcid() && enable_ept;
1809}
1810
a75beee6
ED		 1811/*
1812 * Swap MSR entry in host/guest MSR entry array.
1813 */
8b9cf98c 1814static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1815{
26bb0981 1816 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1817
1818 tmp = vmx->guest_msrs[to];
1819 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1820 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1821}
1822
e38aea3e
AK		 1823/*
1824 * Set up the vmcs to automatically save and restore system
1825 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1826 * mode, as fiddling with msrs is very expensive.
1827 */
8b9cf98c 1828static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1829{
26bb0981 1830 int save_nmsrs, index;
5897297b 1831 unsigned long *msr_bitmap;
e38aea3e 1832
a75beee6
ED		 1833 save_nmsrs = 0;
1834#ifdef CONFIG_X86_64
8b9cf98c 1835 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1836 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1837 if (index >= 0)
8b9cf98c
RR		 1838 move_msr_up(vmx, index, save_nmsrs++);
1839 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1840 if (index >= 0)
8b9cf98c
RR		 1841 move_msr_up(vmx, index, save_nmsrs++);
1842 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1843 if (index >= 0)
8b9cf98c 1844 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1845 index = __find_msr_index(vmx, MSR_TSC_AUX);
1846 if (index >= 0 && vmx->rdtscp_enabled)
1847 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1848 /*
8c06585d 1849 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1850 * if efer.sce is enabled.
1851 */
8c06585d 1852 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1853 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1854 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1855 }
1856#endif
92c0d900
AK		 1857 index = __find_msr_index(vmx, MSR_EFER);
1858 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1859 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1860
26bb0981 1861 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1862
1863 if (cpu_has_vmx_msr_bitmap()) {
1864 if (is_long_mode(&vmx->vcpu))
1865 msr_bitmap = vmx_msr_bitmap_longmode;
1866 else
1867 msr_bitmap = vmx_msr_bitmap_legacy;
1868
1869 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1870 }
e38aea3e
AK		 1871}
1872
6aa8b732
AK		 1873/*
1874 * reads and returns guest's timestamp counter "register"
1875 * guest_tsc = host_tsc + tsc_offset -- 21.3
1876 */
1877static u64 guest_read_tsc(void)
1878{
1879 u64 host_tsc, tsc_offset;
1880
1881 rdtscll(host_tsc);
1882 tsc_offset = vmcs_read64(TSC_OFFSET);
1883 return host_tsc + tsc_offset;
1884}
1885
d5c1785d
NHE		 1886/*
1887 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1888 * counter, even if a nested guest (L2) is currently running.
1889 */
886b470c 1890u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1891{
886b470c 1892 u64 tsc_offset;
d5c1785d 1893
d5c1785d
NHE		 1894 tsc_offset = is_guest_mode(vcpu) ?
1895 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1896 vmcs_read64(TSC_OFFSET);
1897 return host_tsc + tsc_offset;
1898}
1899
4051b188 1900/*
cc578287
ZA		 1901 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1902 * software catchup for faster rates on slower CPUs.
4051b188 1903 */
cc578287 1904static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1905{
cc578287
ZA		 1906 if (!scale)
1907 return;
1908
1909 if (user_tsc_khz > tsc_khz) {
1910 vcpu->arch.tsc_catchup = 1;
1911 vcpu->arch.tsc_always_catchup = 1;
1912 } else
1913 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1914}
1915
ba904635
WA		 1916static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1917{
1918 return vmcs_read64(TSC_OFFSET);
1919}
1920
6aa8b732 1921/*
99e3e30a 1922 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1923 */
99e3e30a 1924static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1925{
27fc51b2 1926 if (is_guest_mode(vcpu)) {
7991825b 1927 /*
27fc51b2
NHE		 1928 * We're here if L1 chose not to trap WRMSR to TSC. According
1929 * to the spec, this should set L1's TSC; The offset that L1
1930 * set for L2 remains unchanged, and still needs to be added
1931 * to the newly set TSC to get L2's TSC.
7991825b 1932 */
27fc51b2
NHE		 1933 struct vmcs12 *vmcs12;
1934 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1935 /* recalculate vmcs02.TSC_OFFSET: */
1936 vmcs12 = get_vmcs12(vcpu);
1937 vmcs_write64(TSC_OFFSET, offset +
1938 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1939 vmcs12->tsc_offset : 0));
1940 } else {
1941 vmcs_write64(TSC_OFFSET, offset);
1942 }
6aa8b732
AK		 1943}
1944
f1e2b260 1945static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1946{
1947 u64 offset = vmcs_read64(TSC_OFFSET);
1948 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1949 if (is_guest_mode(vcpu)) {
1950 /* Even when running L2, the adjustment needs to apply to L1 */
1951 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1952 }
e48672fa
ZA		 1953}
1954
857e4099
JR		 1955static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1956{
1957 return target_tsc - native_read_tsc();
1958}
1959
801d3424
NHE		 1960static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1961{
1962 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1963 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1964}
1965
1966/*
1967 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1968 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1969 * all guests if the "nested" module option is off, and can also be disabled
1970 * for a single guest by disabling its VMX cpuid bit.
1971 */
1972static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1973{
1974 return nested && guest_cpuid_has_vmx(vcpu);
1975}
1976
b87a51ae
NHE		 1977/*
1978 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1979 * returned for the various VMX controls MSRs when nested VMX is enabled.
1980 * The same values should also be used to verify that vmcs12 control fields are
1981 * valid during nested entry from L1 to L2.
1982 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1983 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1984 * bit in the high half is on if the corresponding bit in the control field
1985 * may be on. See also vmx_control_verify().
1986 * TODO: allow these variables to be modified (downgraded) by module options
1987 * or other means.
1988 */
1989static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1990static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1991static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1992static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1993static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1994static __init void nested_vmx_setup_ctls_msrs(void)
1995{
1996 /*
1997 * Note that as a general rule, the high half of the MSRs (bits in
1998 * the control fields which may be 1) should be initialized by the
1999 * intersection of the underlying hardware's MSR (i.e., features which
2000 * can be supported) and the list of features we want to expose -
2001 * because they are known to be properly supported in our code.
2002 * Also, usually, the low half of the MSRs (bits which must be 1) can
2003 * be set to 0, meaning that L1 may turn off any of these bits. The
2004 * reason is that if one of these bits is necessary, it will appear
2005 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2006 * fields of vmcs01 and vmcs02, will turn these bits off - and
2007 * nested_vmx_exit_handled() will not pass related exits to L1.
2008 * These rules have exceptions below.
2009 */
2010
2011 /* pin-based controls */
2012 /*
2013 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2014 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2015 */
2016 nested_vmx_pinbased_ctls_low = 0x16 ;
2017 nested_vmx_pinbased_ctls_high = 0x16 |
2018 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2019 PIN_BASED_VIRTUAL_NMIS;
2020
2021 /* exit controls */
2022 nested_vmx_exit_ctls_low = 0;
b6f1250e 2023 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2024#ifdef CONFIG_X86_64
2025 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2026#else
2027 nested_vmx_exit_ctls_high = 0;
2028#endif
2029
2030 /* entry controls */
2031 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2032 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2033 nested_vmx_entry_ctls_low = 0;
2034 nested_vmx_entry_ctls_high &=
2035 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2036
2037 /* cpu-based controls */
2038 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2039 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2040 nested_vmx_procbased_ctls_low = 0;
2041 nested_vmx_procbased_ctls_high &=
2042 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2043 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2044 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2045 CPU_BASED_CR3_STORE_EXITING |
2046#ifdef CONFIG_X86_64
2047 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2048#endif
2049 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2050 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2051 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2052 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2053 /*
2054 * We can allow some features even when not supported by the
2055 * hardware. For example, L1 can specify an MSR bitmap - and we
2056 * can use it to avoid exits to L1 - even when L0 runs L2
2057 * without MSR bitmaps.
2058 */
2059 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2060
2061 /* secondary cpu-based controls */
2062 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2063 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2064 nested_vmx_secondary_ctls_low = 0;
2065 nested_vmx_secondary_ctls_high &=
2066 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2067}
2068
2069static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2070{
2071 /*
2072 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2073 */
2074 return ((control & high) | low) == control;
2075}
2076
2077static inline u64 vmx_control_msr(u32 low, u32 high)
2078{
2079 return low | ((u64)high << 32);
2080}
2081
2082/*
2083 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2084 * also let it use VMX-specific MSRs.
2085 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2086 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2087 * like all other MSRs).
2088 */
2089static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2090{
2091 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2092 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2093 /*
2094 * According to the spec, processors which do not support VMX
2095 * should throw a #GP(0) when VMX capability MSRs are read.
2096 */
2097 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2098 return 1;
2099 }
2100
2101 switch (msr_index) {
2102 case MSR_IA32_FEATURE_CONTROL:
2103 *pdata = 0;
2104 break;
2105 case MSR_IA32_VMX_BASIC:
2106 /*
2107 * This MSR reports some information about VMX support. We
2108 * should return information about the VMX we emulate for the
2109 * guest, and the VMCS structure we give it - not about the
2110 * VMX support of the underlying hardware.
2111 */
2112 *pdata = VMCS12_REVISION |
2113 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2114 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2115 break;
2116 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2117 case MSR_IA32_VMX_PINBASED_CTLS:
2118 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2119 nested_vmx_pinbased_ctls_high);
2120 break;
2121 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2122 case MSR_IA32_VMX_PROCBASED_CTLS:
2123 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2124 nested_vmx_procbased_ctls_high);
2125 break;
2126 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2127 case MSR_IA32_VMX_EXIT_CTLS:
2128 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2129 nested_vmx_exit_ctls_high);
2130 break;
2131 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2132 case MSR_IA32_VMX_ENTRY_CTLS:
2133 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2134 nested_vmx_entry_ctls_high);
2135 break;
2136 case MSR_IA32_VMX_MISC:
2137 *pdata = 0;
2138 break;
2139 /*
2140 * These MSRs specify bits which the guest must keep fixed (on or off)
2141 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2142 * We picked the standard core2 setting.
2143 */
2144#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2145#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2146 case MSR_IA32_VMX_CR0_FIXED0:
2147 *pdata = VMXON_CR0_ALWAYSON;
2148 break;
2149 case MSR_IA32_VMX_CR0_FIXED1:
2150 *pdata = -1ULL;
2151 break;
2152 case MSR_IA32_VMX_CR4_FIXED0:
2153 *pdata = VMXON_CR4_ALWAYSON;
2154 break;
2155 case MSR_IA32_VMX_CR4_FIXED1:
2156 *pdata = -1ULL;
2157 break;
2158 case MSR_IA32_VMX_VMCS_ENUM:
2159 *pdata = 0x1f;
2160 break;
2161 case MSR_IA32_VMX_PROCBASED_CTLS2:
2162 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2163 nested_vmx_secondary_ctls_high);
2164 break;
2165 case MSR_IA32_VMX_EPT_VPID_CAP:
2166 /* Currently, no nested ept or nested vpid */
2167 *pdata = 0;
2168 break;
2169 default:
2170 return 0;
2171 }
2172
2173 return 1;
2174}
2175
2176static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2177{
2178 if (!nested_vmx_allowed(vcpu))
2179 return 0;
2180
2181 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2182 /* TODO: the right thing. */
2183 return 1;
2184 /*
2185 * No need to treat VMX capability MSRs specially: If we don't handle
2186 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2187 */
2188 return 0;
2189}
2190
6aa8b732
AK		 2191/*
2192 * Reads an msr value (of 'msr_index') into 'pdata'.
2193 * Returns 0 on success, non-0 otherwise.
2194 * Assumes vcpu_load() was already called.
2195 */
2196static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2197{
2198 u64 data;
26bb0981 2199 struct shared_msr_entry *msr;
6aa8b732
AK		 2200
2201 if (!pdata) {
2202 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2203 return -EINVAL;
2204 }
2205
2206 switch (msr_index) {
05b3e0c2 2207#ifdef CONFIG_X86_64
6aa8b732
AK		 2208 case MSR_FS_BASE:
2209 data = vmcs_readl(GUEST_FS_BASE);
2210 break;
2211 case MSR_GS_BASE:
2212 data = vmcs_readl(GUEST_GS_BASE);
2213 break;
44ea2b17
AK		 2214 case MSR_KERNEL_GS_BASE:
2215 vmx_load_host_state(to_vmx(vcpu));
2216 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2217 break;
26bb0981 2218#endif
6aa8b732 2219 case MSR_EFER:
3bab1f5d 2220 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2221 case MSR_IA32_TSC:
6aa8b732
AK		 2222 data = guest_read_tsc();
2223 break;
2224 case MSR_IA32_SYSENTER_CS:
2225 data = vmcs_read32(GUEST_SYSENTER_CS);
2226 break;
2227 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2228 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2229 break;
2230 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2231 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2232 break;
4e47c7a6
SY		 2233 case MSR_TSC_AUX:
2234 if (!to_vmx(vcpu)->rdtscp_enabled)
2235 return 1;
2236 /* Otherwise falls through */
6aa8b732 2237 default:
b87a51ae
NHE		 2238 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2239 return 0;
8b9cf98c 2240 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2241 if (msr) {
2242 data = msr->data;
2243 break;
6aa8b732 2244 }
3bab1f5d 2245 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2246 }
2247
2248 *pdata = data;
2249 return 0;
2250}
2251
2252/*
2253 * Writes msr value into into the appropriate "register".
2254 * Returns 0 on success, non-0 otherwise.
2255 * Assumes vcpu_load() was already called.
2256 */
8fe8ab46 2257static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2258{
a2fa3e9f 2259 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2260 struct shared_msr_entry *msr;
2cc51560 2261 int ret = 0;
8fe8ab46
WA		 2262 u32 msr_index = msr_info->index;
2263 u64 data = msr_info->data;
2cc51560 2264
6aa8b732 2265 switch (msr_index) {
3bab1f5d 2266 case MSR_EFER:
8fe8ab46 2267 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2268 break;
16175a79 2269#ifdef CONFIG_X86_64
6aa8b732 2270 case MSR_FS_BASE:
2fb92db1 2271 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2272 vmcs_writel(GUEST_FS_BASE, data);
2273 break;
2274 case MSR_GS_BASE:
2fb92db1 2275 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2276 vmcs_writel(GUEST_GS_BASE, data);
2277 break;
44ea2b17
AK		 2278 case MSR_KERNEL_GS_BASE:
2279 vmx_load_host_state(vmx);
2280 vmx->msr_guest_kernel_gs_base = data;
2281 break;
6aa8b732
AK		 2282#endif
2283 case MSR_IA32_SYSENTER_CS:
2284 vmcs_write32(GUEST_SYSENTER_CS, data);
2285 break;
2286 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2287 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2288 break;
2289 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2290 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2291 break;
af24a4e4 2292 case MSR_IA32_TSC:
8fe8ab46 2293 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2294 break;
468d472f
SY		 2295 case MSR_IA32_CR_PAT:
2296 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2297 vmcs_write64(GUEST_IA32_PAT, data);
2298 vcpu->arch.pat = data;
2299 break;
2300 }
8fe8ab46 2301 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2302 break;
ba904635
WA		 2303 case MSR_IA32_TSC_ADJUST:
2304 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2305 break;
2306 case MSR_TSC_AUX:
2307 if (!vmx->rdtscp_enabled)
2308 return 1;
2309 /* Check reserved bit, higher 32 bits should be zero */
2310 if ((data >> 32) != 0)
2311 return 1;
2312 /* Otherwise falls through */
6aa8b732 2313 default:
b87a51ae
NHE		 2314 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2315 break;
8b9cf98c 2316 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2317 if (msr) {
2318 msr->data = data;
2225fd56
AK		 2319 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2320 preempt_disable();
9ee73970
AK		 2321 kvm_set_shared_msr(msr->index, msr->data,
2322 msr->mask);
2225fd56
AK		 2323 preempt_enable();
2324 }
3bab1f5d 2325 break;
6aa8b732 2326 }
8fe8ab46 2327 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2328 }
2329
2cc51560 2330 return ret;
6aa8b732
AK		 2331}
2332
5fdbf976 2333static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2334{
5fdbf976
MT		 2335 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2336 switch (reg) {
2337 case VCPU_REGS_RSP:
2338 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2339 break;
2340 case VCPU_REGS_RIP:
2341 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2342 break;
6de4f3ad
AK		 2343 case VCPU_EXREG_PDPTR:
2344 if (enable_ept)
2345 ept_save_pdptrs(vcpu);
2346 break;
5fdbf976
MT		 2347 default:
2348 break;
2349 }
6aa8b732
AK		 2350}
2351
6aa8b732
AK		 2352static __init int cpu_has_kvm_support(void)
2353{
6210e37b 2354 return cpu_has_vmx();
6aa8b732
AK		 2355}
2356
2357static __init int vmx_disabled_by_bios(void)
2358{
2359 u64 msr;
2360
2361 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2362 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2363 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2364 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2365 && tboot_enabled())
2366 return 1;
23f3e991 2367 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2368 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2369 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2370 && !tboot_enabled()) {
2371 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2372 "activate TXT before enabling KVM\n");
cafd6659 2373 return 1;
f9335afe 2374 }
23f3e991
JC		 2375 /* launched w/o TXT and VMX disabled */
2376 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2377 && !tboot_enabled())
2378 return 1;
cafd6659
SW		 2379 }
2380
2381 return 0;
6aa8b732
AK		 2382}
2383
7725b894
DX		 2384static void kvm_cpu_vmxon(u64 addr)
2385{
2386 asm volatile (ASM_VMX_VMXON_RAX
2387 : : "a"(&addr), "m"(addr)
2388 : "memory", "cc");
2389}
2390
10474ae8 2391static int hardware_enable(void *garbage)
6aa8b732
AK		 2392{
2393 int cpu = raw_smp_processor_id();
2394 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2395 u64 old, test_bits;
6aa8b732 2396
10474ae8
AG		 2397 if (read_cr4() & X86_CR4_VMXE)
2398 return -EBUSY;
2399
d462b819 2400 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2401
2402 /*
2403 * Now we can enable the vmclear operation in kdump
2404 * since the loaded_vmcss_on_cpu list on this cpu
2405 * has been initialized.
2406 *
2407 * Though the cpu is not in VMX operation now, there
2408 * is no problem to enable the vmclear operation
2409 * for the loaded_vmcss_on_cpu list is empty!
2410 */
2411 crash_enable_local_vmclear(cpu);
2412
6aa8b732 2413 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2414
2415 test_bits = FEATURE_CONTROL_LOCKED;
2416 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2417 if (tboot_enabled())
2418 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2419
2420 if ((old & test_bits) != test_bits) {
6aa8b732 2421 /* enable and lock */
cafd6659
SW		 2422 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2423 }
66aee91a 2424 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2425
4610c9cc
DX		 2426 if (vmm_exclusive) {
2427 kvm_cpu_vmxon(phys_addr);
2428 ept_sync_global();
2429 }
10474ae8 2430
3444d7da
AK		 2431 store_gdt(&__get_cpu_var(host_gdt));
2432
10474ae8 2433 return 0;
6aa8b732
AK		 2434}
2435
d462b819 2436static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2437{
2438 int cpu = raw_smp_processor_id();
d462b819 2439 struct loaded_vmcs *v, *n;
543e4243 2440
d462b819
NHE		 2441 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2442 loaded_vmcss_on_cpu_link)
2443 __loaded_vmcs_clear(v);
543e4243
AK		 2444}
2445
710ff4a8
EH		 2446
2447/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2448 * tricks.
2449 */
2450static void kvm_cpu_vmxoff(void)
6aa8b732 2451{
4ecac3fd 2452 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2453}
2454
710ff4a8
EH		 2455static void hardware_disable(void *garbage)
2456{
4610c9cc 2457 if (vmm_exclusive) {
d462b819 2458 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2459 kvm_cpu_vmxoff();
2460 }
7725b894 2461 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2462}
2463
1c3d14fe 2464static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2465 u32 msr, u32 *result)
1c3d14fe
YS		 2466{
2467 u32 vmx_msr_low, vmx_msr_high;
2468 u32 ctl = ctl_min | ctl_opt;
2469
2470 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2471
2472 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2473 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2474
2475 /* Ensure minimum (required) set of control bits are supported. */
2476 if (ctl_min & ~ctl)
002c7f7c 2477 return -EIO;
1c3d14fe
YS		 2478
2479 *result = ctl;
2480 return 0;
2481}
2482
110312c8
AK		 2483static __init bool allow_1_setting(u32 msr, u32 ctl)
2484{
2485 u32 vmx_msr_low, vmx_msr_high;
2486
2487 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2488 return vmx_msr_high & ctl;
2489}
2490
002c7f7c 2491static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2492{
2493 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2494 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2495 u32 _pin_based_exec_control = 0;
2496 u32 _cpu_based_exec_control = 0;
f78e0e2e 2497 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2498 u32 _vmexit_control = 0;
2499 u32 _vmentry_control = 0;
2500
2501 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2502 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2503 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2504 &_pin_based_exec_control) < 0)
002c7f7c 2505 return -EIO;
1c3d14fe 2506
10166744 2507 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2508#ifdef CONFIG_X86_64
2509 CPU_BASED_CR8_LOAD_EXITING |
2510 CPU_BASED_CR8_STORE_EXITING |
2511#endif
d56f546d
SY		 2512 CPU_BASED_CR3_LOAD_EXITING |
2513 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2514 CPU_BASED_USE_IO_BITMAPS |
2515 CPU_BASED_MOV_DR_EXITING |
a7052897 2516 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2517 CPU_BASED_MWAIT_EXITING |
2518 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2519 CPU_BASED_INVLPG_EXITING |
2520 CPU_BASED_RDPMC_EXITING;
443381a8 2521
f78e0e2e 2522 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2523 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2524 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2525 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2526 &_cpu_based_exec_control) < 0)
002c7f7c 2527 return -EIO;
6e5d865c
YS		 2528#ifdef CONFIG_X86_64
2529 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2530 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2531 ~CPU_BASED_CR8_STORE_EXITING;
2532#endif
f78e0e2e 2533 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2534 min2 = 0;
2535 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2536 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2537 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2538 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2539 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2540 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2541 SECONDARY_EXEC_RDTSCP |
2542 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2543 if (adjust_vmx_controls(min2, opt2,
2544 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2545 &_cpu_based_2nd_exec_control) < 0)
2546 return -EIO;
2547 }
2548#ifndef CONFIG_X86_64
2549 if (!(_cpu_based_2nd_exec_control &
2550 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2551 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2552#endif
d56f546d 2553 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2554 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2555 enabled */
5fff7d27
GN		 2556 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2557 CPU_BASED_CR3_STORE_EXITING |
2558 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2559 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2560 vmx_capability.ept, vmx_capability.vpid);
2561 }
1c3d14fe
YS		 2562
2563 min = 0;
2564#ifdef CONFIG_X86_64
2565 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2566#endif
468d472f 2567 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2568 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2569 &_vmexit_control) < 0)
002c7f7c 2570 return -EIO;
1c3d14fe 2571
468d472f
SY		 2572 min = 0;
2573 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2574 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2575 &_vmentry_control) < 0)
002c7f7c 2576 return -EIO;
6aa8b732 2577
c68876fd 2578 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2579
2580 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2581 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2582 return -EIO;
1c3d14fe
YS		 2583
2584#ifdef CONFIG_X86_64
2585 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2586 if (vmx_msr_high & (1u<<16))
002c7f7c 2587 return -EIO;
1c3d14fe
YS		 2588#endif
2589
2590 /* Require Write-Back (WB) memory type for VMCS accesses. */
2591 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2592 return -EIO;
1c3d14fe 2593
002c7f7c
YS		 2594 vmcs_conf->size = vmx_msr_high & 0x1fff;
2595 vmcs_conf->order = get_order(vmcs_config.size);
2596 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2597
002c7f7c
YS		 2598 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2599 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2600 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2601 vmcs_conf->vmexit_ctrl = _vmexit_control;
2602 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2603
110312c8
AK		 2604 cpu_has_load_ia32_efer =
2605 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2606 VM_ENTRY_LOAD_IA32_EFER)
2607 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2608 VM_EXIT_LOAD_IA32_EFER);
2609
8bf00a52
GN		 2610 cpu_has_load_perf_global_ctrl =
2611 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2612 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2613 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2614 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2615
2616 /*
2617 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2618 * but due to arrata below it can't be used. Workaround is to use
2619 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2620 *
2621 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2622 *
2623 * AAK155 (model 26)
2624 * AAP115 (model 30)
2625 * AAT100 (model 37)
2626 * BC86,AAY89,BD102 (model 44)
2627 * BA97 (model 46)
2628 *
2629 */
2630 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2631 switch (boot_cpu_data.x86_model) {
2632 case 26:
2633 case 30:
2634 case 37:
2635 case 44:
2636 case 46:
2637 cpu_has_load_perf_global_ctrl = false;
2638 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2639 "does not work properly. Using workaround\n");
2640 break;
2641 default:
2642 break;
2643 }
2644 }
2645
1c3d14fe 2646 return 0;
c68876fd 2647}
6aa8b732
AK		 2648
2649static struct vmcs *alloc_vmcs_cpu(int cpu)
2650{
2651 int node = cpu_to_node(cpu);
2652 struct page *pages;
2653 struct vmcs *vmcs;
2654
6484eb3e 2655 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2656 if (!pages)
2657 return NULL;
2658 vmcs = page_address(pages);
1c3d14fe
YS		 2659 memset(vmcs, 0, vmcs_config.size);
2660 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2661 return vmcs;
2662}
2663
2664static struct vmcs *alloc_vmcs(void)
2665{
d3b2c338 2666 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2667}
2668
2669static void free_vmcs(struct vmcs *vmcs)
2670{
1c3d14fe 2671 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2672}
2673
d462b819
NHE		 2674/*
2675 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2676 */
2677static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2678{
2679 if (!loaded_vmcs->vmcs)
2680 return;
2681 loaded_vmcs_clear(loaded_vmcs);
2682 free_vmcs(loaded_vmcs->vmcs);
2683 loaded_vmcs->vmcs = NULL;
2684}
2685
39959588 2686static void free_kvm_area(void)
6aa8b732
AK		 2687{
2688 int cpu;
2689
3230bb47 2690 for_each_possible_cpu(cpu) {
6aa8b732 2691 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2692 per_cpu(vmxarea, cpu) = NULL;
2693 }
6aa8b732
AK		 2694}
2695
6aa8b732
AK		 2696static __init int alloc_kvm_area(void)
2697{
2698 int cpu;
2699
3230bb47 2700 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2701 struct vmcs *vmcs;
2702
2703 vmcs = alloc_vmcs_cpu(cpu);
2704 if (!vmcs) {
2705 free_kvm_area();
2706 return -ENOMEM;
2707 }
2708
2709 per_cpu(vmxarea, cpu) = vmcs;
2710 }
2711 return 0;
2712}
2713
2714static __init int hardware_setup(void)
2715{
002c7f7c
YS		 2716 if (setup_vmcs_config(&vmcs_config) < 0)
2717 return -EIO;
50a37eb4
JR		 2718
2719 if (boot_cpu_has(X86_FEATURE_NX))
2720 kvm_enable_efer_bits(EFER_NX);
2721
93ba03c2
SY		 2722 if (!cpu_has_vmx_vpid())
2723 enable_vpid = 0;
2724
4bc9b982
SY		 2725 if (!cpu_has_vmx_ept() ||
2726 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2727 enable_ept = 0;
3a624e29 2728 enable_unrestricted_guest = 0;
83c3a331 2729 enable_ept_ad_bits = 0;
3a624e29
NK		 2730 }
2731
83c3a331
XH		 2732 if (!cpu_has_vmx_ept_ad_bits())
2733 enable_ept_ad_bits = 0;
2734
3a624e29
NK		 2735 if (!cpu_has_vmx_unrestricted_guest())
2736 enable_unrestricted_guest = 0;
93ba03c2
SY		 2737
2738 if (!cpu_has_vmx_flexpriority())
2739 flexpriority_enabled = 0;
2740
95ba8273
GN		 2741 if (!cpu_has_vmx_tpr_shadow())
2742 kvm_x86_ops->update_cr8_intercept = NULL;
2743
54dee993
MT		 2744 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2745 kvm_disable_largepages();
2746
4b8d54f9
ZE		 2747 if (!cpu_has_vmx_ple())
2748 ple_gap = 0;
2749
b87a51ae
NHE		 2750 if (nested)
2751 nested_vmx_setup_ctls_msrs();
2752
6aa8b732
AK		 2753 return alloc_kvm_area();
2754}
2755
2756static __exit void hardware_unsetup(void)
2757{
2758 free_kvm_area();
2759}
2760
f5f7b2fe 2761static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
6aa8b732 2762{
772e0318 2763 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
c865c43d 2764 struct kvm_segment tmp = *save;
6aa8b732 2765
c865c43d
AK		 2766 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2767 tmp.base = vmcs_readl(sf->base);
2768 tmp.selector = vmcs_read16(sf->selector);
a4d3326c 2769 tmp.dpl = tmp.selector & SELECTOR_RPL_MASK;
c865c43d 2770 tmp.s = 1;
6aa8b732 2771 }
c865c43d 2772 vmx_set_segment(vcpu, &tmp, seg);
6aa8b732
AK		 2773}
2774
2775static void enter_pmode(struct kvm_vcpu *vcpu)
2776{
2777 unsigned long flags;
a89a8fb9 2778 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2779
a89a8fb9 2780 vmx->emulation_required = 1;
7ffd92c5 2781 vmx->rmode.vm86_active = 0;
6aa8b732 2782
2fb92db1
AK		 2783 vmx_segment_cache_clear(vmx);
2784
f5f7b2fe 2785 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2786
2787 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2788 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2789 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2790 vmcs_writel(GUEST_RFLAGS, flags);
2791
66aee91a
RR		 2792 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2793 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2794
2795 update_exception_bitmap(vcpu);
2796
a89a8fb9
MG		 2797 if (emulate_invalid_guest_state)
2798 return;
2799
f5f7b2fe
AK		 2800 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2801 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2802 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2803 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732 2804
2fb92db1
AK		 2805 vmx_segment_cache_clear(vmx);
2806
6aa8b732
AK		 2807 vmcs_write16(GUEST_SS_SELECTOR, 0);
2808 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2809
2810 vmcs_write16(GUEST_CS_SELECTOR,
2811 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2812 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2813}
2814
d77c26fc 2815static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2816{
bfc6d222 2817 if (!kvm->arch.tss_addr) {
bc6678a3 2818 struct kvm_memslots *slots;
28a37544 2819 struct kvm_memory_slot *slot;
bc6678a3
MT		 2820 gfn_t base_gfn;
2821
90d83dc3 2822 slots = kvm_memslots(kvm);
28a37544
XG		 2823 slot = id_to_memslot(slots, 0);
2824 base_gfn = slot->base_gfn + slot->npages - 3;
2825
cbc94022
IE		 2826 return base_gfn << PAGE_SHIFT;
2827 }
bfc6d222 2828 return kvm->arch.tss_addr;
6aa8b732
AK		 2829}
2830
f5f7b2fe 2831static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2832{
772e0318 2833 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
6aa8b732 2834
15b00f32 2835 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2836 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2837 vmcs_write32(sf->limit, 0xffff);
2838 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2839 if (save->base & 0xf)
2840 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2841 " aligned when entering protected mode (seg=%d)",
2842 seg);
6aa8b732
AK		 2843}
2844
2845static void enter_rmode(struct kvm_vcpu *vcpu)
2846{
2847 unsigned long flags;
a89a8fb9 2848 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2849 struct kvm_segment var;
6aa8b732 2850
3a624e29
NK		 2851 if (enable_unrestricted_guest)
2852 return;
2853
f5f7b2fe
AK		 2854 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2855 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2856 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2857 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2858 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2859
a89a8fb9 2860 vmx->emulation_required = 1;
7ffd92c5 2861 vmx->rmode.vm86_active = 1;
6aa8b732 2862
baa7e81e 2863
776e58ea
GN		 2864 /*
2865 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2866 * vcpu. Call it here with phys address pointing 16M below 4G.
2867 */
2868 if (!vcpu->kvm->arch.tss_addr) {
2869 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2870 "called before entering vcpu\n");
2871 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2872 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2873 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2874 }
2875
2fb92db1
AK		 2876 vmx_segment_cache_clear(vmx);
2877
6aa8b732 2878 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2879 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2880 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2881
2882 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2883 vmx->rmode.save_rflags = flags;
6aa8b732 2884
053de044 2885 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2886
2887 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2888 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2889 update_exception_bitmap(vcpu);
2890
a89a8fb9
MG		 2891 if (emulate_invalid_guest_state)
2892 goto continue_rmode;
2893
b246dd5d
OW		 2894 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2895 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2896
2897 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2898 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2899
2900 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2901 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2902
2903 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2904 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2905
b246dd5d
OW		 2906 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2907 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2908
b246dd5d
OW		 2909 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2910 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2911
a89a8fb9 2912continue_rmode:
8668a3c4 2913 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2914}
2915
401d10de
AS		 2916static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2917{
2918 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2919 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2920
2921 if (!msr)
2922 return;
401d10de 2923
44ea2b17
AK		 2924 /*
2925 * Force kernel_gs_base reloading before EFER changes, as control
2926 * of this msr depends on is_long_mode().
2927 */
2928 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2929 vcpu->arch.efer = efer;
401d10de
AS		 2930 if (efer & EFER_LMA) {
2931 vmcs_write32(VM_ENTRY_CONTROLS,
2932 vmcs_read32(VM_ENTRY_CONTROLS) |
2933 VM_ENTRY_IA32E_MODE);
2934 msr->data = efer;
2935 } else {
2936 vmcs_write32(VM_ENTRY_CONTROLS,
2937 vmcs_read32(VM_ENTRY_CONTROLS) &
2938 ~VM_ENTRY_IA32E_MODE);
2939
2940 msr->data = efer & ~EFER_LME;
2941 }
2942 setup_msrs(vmx);
2943}
2944
05b3e0c2 2945#ifdef CONFIG_X86_64
6aa8b732
AK		 2946
2947static void enter_lmode(struct kvm_vcpu *vcpu)
2948{
2949 u32 guest_tr_ar;
2950
2fb92db1
AK		 2951 vmx_segment_cache_clear(to_vmx(vcpu));
2952
6aa8b732
AK		 2953 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2954 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2955 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2956 __func__);
6aa8b732
AK		 2957 vmcs_write32(GUEST_TR_AR_BYTES,
2958 (guest_tr_ar & ~AR_TYPE_MASK)
2959 | AR_TYPE_BUSY_64_TSS);
2960 }
da38f438 2961 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2962}
2963
2964static void exit_lmode(struct kvm_vcpu *vcpu)
2965{
6aa8b732
AK		 2966 vmcs_write32(VM_ENTRY_CONTROLS,
2967 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2968 & ~VM_ENTRY_IA32E_MODE);
da38f438 2969 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2970}
2971
2972#endif
2973
2384d2b3
SY		 2974static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2975{
b9d762fa 2976 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2977 if (enable_ept) {
2978 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2979 return;
4e1096d2 2980 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2981 }
2384d2b3
SY		 2982}
2983
e8467fda
AK		 2984static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2985{
2986 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2987
2988 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2989 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2990}
2991
aff48baa
AK		 2992static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2993{
2994 if (enable_ept && is_paging(vcpu))
2995 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2996 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2997}
2998
25c4c276 2999static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3000{
fc78f519
AK		 3001 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3002
3003 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3004 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3005}
3006
1439442c
SY		 3007static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3008{
6de4f3ad
AK		 3009 if (!test_bit(VCPU_EXREG_PDPTR,
3010 (unsigned long *)&vcpu->arch.regs_dirty))
3011 return;
3012
1439442c 3013 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3014 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3015 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3016 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3017 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3018 }
3019}
3020
8f5d549f
AK		 3021static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3022{
3023 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3024 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3025 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3026 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3027 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3028 }
6de4f3ad
AK		 3029
3030 __set_bit(VCPU_EXREG_PDPTR,
3031 (unsigned long *)&vcpu->arch.regs_avail);
3032 __set_bit(VCPU_EXREG_PDPTR,
3033 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3034}
3035
5e1746d6 3036static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3037
3038static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3039 unsigned long cr0,
3040 struct kvm_vcpu *vcpu)
3041{
5233dd51
MT		 3042 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3043 vmx_decache_cr3(vcpu);
1439442c
SY		 3044 if (!(cr0 & X86_CR0_PG)) {
3045 /* From paging/starting to nonpaging */
3046 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3047 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3048 (CPU_BASED_CR3_LOAD_EXITING |
3049 CPU_BASED_CR3_STORE_EXITING));
3050 vcpu->arch.cr0 = cr0;
fc78f519 3051 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3052 } else if (!is_paging(vcpu)) {
3053 /* From nonpaging to paging */
3054 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3055 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3056 ~(CPU_BASED_CR3_LOAD_EXITING |
3057 CPU_BASED_CR3_STORE_EXITING));
3058 vcpu->arch.cr0 = cr0;
fc78f519 3059 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3060 }
95eb84a7
SY		 3061
3062 if (!(cr0 & X86_CR0_WP))
3063 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3064}
3065
6aa8b732
AK		 3066static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3067{
7ffd92c5 3068 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3069 unsigned long hw_cr0;
3070
3071 if (enable_unrestricted_guest)
3072 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3073 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3074 else
3075 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3076
7ffd92c5 3077 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3078 enter_pmode(vcpu);
3079
7ffd92c5 3080 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3081 enter_rmode(vcpu);
3082
05b3e0c2 3083#ifdef CONFIG_X86_64
f6801dff 3084 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3085 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3086 enter_lmode(vcpu);
707d92fa 3087 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3088 exit_lmode(vcpu);
3089 }
3090#endif
3091
089d034e 3092 if (enable_ept)
1439442c
SY		 3093 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3094
02daab21 3095 if (!vcpu->fpu_active)
81231c69 3096 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3097
6aa8b732 3098 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3099 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3100 vcpu->arch.cr0 = cr0;
69c73028 3101 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3102}
3103
1439442c
SY		 3104static u64 construct_eptp(unsigned long root_hpa)
3105{
3106 u64 eptp;
3107
3108 /* TODO write the value reading from MSR */
3109 eptp = VMX_EPT_DEFAULT_MT |
3110 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3111 if (enable_ept_ad_bits)
3112 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3113 eptp |= (root_hpa & PAGE_MASK);
3114
3115 return eptp;
3116}
3117
6aa8b732
AK		 3118static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3119{
1439442c
SY		 3120 unsigned long guest_cr3;
3121 u64 eptp;
3122
3123 guest_cr3 = cr3;
089d034e 3124 if (enable_ept) {
1439442c
SY		 3125 eptp = construct_eptp(cr3);
3126 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3127 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3128 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3129 ept_load_pdptrs(vcpu);
1439442c
SY		 3130 }
3131
2384d2b3 3132 vmx_flush_tlb(vcpu);
1439442c 3133 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3134}
3135
5e1746d6 3136static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3137{
7ffd92c5 3138 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3139 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3140
5e1746d6
NHE		 3141 if (cr4 & X86_CR4_VMXE) {
3142 /*
3143 * To use VMXON (and later other VMX instructions), a guest
3144 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3145 * So basically the check on whether to allow nested VMX
3146 * is here.
3147 */
3148 if (!nested_vmx_allowed(vcpu))
3149 return 1;
3150 } else if (to_vmx(vcpu)->nested.vmxon)
3151 return 1;
3152
ad312c7c 3153 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3154 if (enable_ept) {
3155 if (!is_paging(vcpu)) {
3156 hw_cr4 &= ~X86_CR4_PAE;
3157 hw_cr4 |= X86_CR4_PSE;
3158 } else if (!(cr4 & X86_CR4_PAE)) {
3159 hw_cr4 &= ~X86_CR4_PAE;
3160 }
3161 }
1439442c
SY		 3162
3163 vmcs_writel(CR4_READ_SHADOW, cr4);
3164 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3165 return 0;
6aa8b732
AK		 3166}
3167
6aa8b732
AK		 3168static void vmx_get_segment(struct kvm_vcpu *vcpu,
3169 struct kvm_segment *var, int seg)
3170{
a9179499 3171 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3172 u32 ar;
3173
a9179499
AK		 3174 if (vmx->rmode.vm86_active
3175 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3176 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
72636420 3177 || seg == VCPU_SREG_GS)) {
f5f7b2fe 3178 *var = vmx->rmode.segs[seg];
a9179499 3179 if (seg == VCPU_SREG_TR
2fb92db1 3180 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3181 return;
1390a28b
AK		 3182 var->base = vmx_read_guest_seg_base(vmx, seg);
3183 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3184 return;
a9179499 3185 }
2fb92db1
AK		 3186 var->base = vmx_read_guest_seg_base(vmx, seg);
3187 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3188 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3189 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3190 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3191 ar = 0;
3192 var->type = ar & 15;
3193 var->s = (ar >> 4) & 1;
3194 var->dpl = (ar >> 5) & 3;
3195 var->present = (ar >> 7) & 1;
3196 var->avl = (ar >> 12) & 1;
3197 var->l = (ar >> 13) & 1;
3198 var->db = (ar >> 14) & 1;
3199 var->g = (ar >> 15) & 1;
3200 var->unusable = (ar >> 16) & 1;
3201}
3202
a9179499
AK		 3203static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3204{
a9179499
AK		 3205 struct kvm_segment s;
3206
3207 if (to_vmx(vcpu)->rmode.vm86_active) {
3208 vmx_get_segment(vcpu, &s, seg);
3209 return s.base;
3210 }
2fb92db1 3211 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3212}
3213
69c73028 3214static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3215{
3eeb3288 3216 if (!is_protmode(vcpu))
2e4d2653
IE		 3217 return 0;
3218
f4c63e5d
AK		 3219 if (!is_long_mode(vcpu)
3220 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3221 return 3;
3222
2fb92db1 3223 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3224}
3225
69c73028
AK		 3226static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3227{
d881e6f6
AK		 3228 struct vcpu_vmx *vmx = to_vmx(vcpu);
3229
3230 /*
3231 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3232 * fail; use the cache instead.
3233 */
3234 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3235 return vmx->cpl;
3236 }
3237
69c73028
AK		 3238 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3239 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3240 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3241 }
d881e6f6
AK		 3242
3243 return vmx->cpl;
69c73028
AK		 3244}
3245
3246
653e3108 3247static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3248{
6aa8b732
AK		 3249 u32 ar;
3250
f0495f9b 3251 if (var->unusable || !var->present)
6aa8b732
AK		 3252 ar = 1 << 16;
3253 else {
3254 ar = var->type & 15;
3255 ar |= (var->s & 1) << 4;
3256 ar |= (var->dpl & 3) << 5;
3257 ar |= (var->present & 1) << 7;
3258 ar |= (var->avl & 1) << 12;
3259 ar |= (var->l & 1) << 13;
3260 ar |= (var->db & 1) << 14;
3261 ar |= (var->g & 1) << 15;
3262 }
653e3108
AK		 3263
3264 return ar;
3265}
3266
3267static void vmx_set_segment(struct kvm_vcpu *vcpu,
3268 struct kvm_segment *var, int seg)
3269{
7ffd92c5 3270 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3271 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108
AK		 3272 u32 ar;
3273
2fb92db1
AK		 3274 vmx_segment_cache_clear(vmx);
3275
7ffd92c5 3276 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3277 vmcs_write16(sf->selector, var->selector);
f5f7b2fe 3278 vmx->rmode.segs[VCPU_SREG_TR] = *var;
653e3108
AK		 3279 return;
3280 }
3281 vmcs_writel(sf->base, var->base);
3282 vmcs_write32(sf->limit, var->limit);
3283 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3284 if (vmx->rmode.vm86_active && var->s) {
ce566803 3285 vmx->rmode.segs[seg] = *var;
653e3108
AK		 3286 /*
3287 * Hack real-mode segments into vm86 compatibility.
3288 */
3289 if (var->base == 0xffff0000 && var->selector == 0xf000)
3290 vmcs_writel(sf->base, 0xf0000);
3291 ar = 0xf3;
3292 } else
3293 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3294
3295 /*
3296 * Fix the "Accessed" bit in AR field of segment registers for older
3297 * qemu binaries.
3298 * IA32 arch specifies that at the time of processor reset the
3299 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3300 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3301 * state vmexit when "unrestricted guest" mode is turned on.
3302 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3303 * tree. Newer qemu binaries with that qemu fix would not need this
3304 * kvm hack.
3305 */
3306 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3307 ar |= 0x1; /* Accessed */
3308
6aa8b732 3309 vmcs_write32(sf->ar_bytes, ar);
69c73028 3310 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3311
3312 /*
3313 * Fix segments for real mode guest in hosts that don't have
3314 * "unrestricted_mode" or it was disabled.
3315 * This is done to allow migration of the guests from hosts with
3316 * unrestricted guest like Westmere to older host that don't have
3317 * unrestricted guest like Nehelem.
3318 */
0b26b588 3319 if (vmx->rmode.vm86_active) {
b246dd5d
OW		 3320 switch (seg) {
3321 case VCPU_SREG_CS:
3322 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3323 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3324 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3325 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3326 vmcs_write16(GUEST_CS_SELECTOR,
3327 vmcs_readl(GUEST_CS_BASE) >> 4);
3328 break;
3329 case VCPU_SREG_ES:
b246dd5d 3330 case VCPU_SREG_DS:
b246dd5d 3331 case VCPU_SREG_GS:
b246dd5d 3332 case VCPU_SREG_FS:
f5f7b2fe 3333 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
b246dd5d
OW		 3334 break;
3335 case VCPU_SREG_SS:
3336 vmcs_write16(GUEST_SS_SELECTOR,
3337 vmcs_readl(GUEST_SS_BASE) >> 4);
3338 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3339 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3340 break;
3341 }
3342 }
6aa8b732
AK		 3343}
3344
6aa8b732
AK		 3345static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3346{
2fb92db1 3347 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3348
3349 *db = (ar >> 14) & 1;
3350 *l = (ar >> 13) & 1;
3351}
3352
89a27f4d 3353static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3354{
89a27f4d
GN		 3355 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3356 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3357}
3358
89a27f4d 3359static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3360{
89a27f4d
GN		 3361 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3362 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3363}
3364
89a27f4d 3365static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3366{
89a27f4d
GN		 3367 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3368 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3369}
3370
89a27f4d 3371static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3372{
89a27f4d
GN		 3373 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3374 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3375}
3376
648dfaa7
MG		 3377static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3378{
3379 struct kvm_segment var;
3380 u32 ar;
3381
3382 vmx_get_segment(vcpu, &var, seg);
07f42f5f
GN		 3383 var.dpl = 0x3;
3384 var.g = 0;
3385 var.db = 0;
648dfaa7
MG		 3386 ar = vmx_segment_access_rights(&var);
3387
3388 if (var.base != (var.selector << 4))
3389 return false;
e2a610d7 3390 if (var.limit < 0xffff)
648dfaa7 3391 return false;
07f42f5f 3392 if (ar != 0xf3)
648dfaa7
MG		 3393 return false;
3394
3395 return true;
3396}
3397
3398static bool code_segment_valid(struct kvm_vcpu *vcpu)
3399{
3400 struct kvm_segment cs;
3401 unsigned int cs_rpl;
3402
3403 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3404 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3405
1872a3f4
AK		 3406 if (cs.unusable)
3407 return false;
648dfaa7
MG		 3408 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3409 return false;
3410 if (!cs.s)
3411 return false;
1872a3f4 3412 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3413 if (cs.dpl > cs_rpl)
3414 return false;
1872a3f4 3415 } else {
648dfaa7
MG		 3416 if (cs.dpl != cs_rpl)
3417 return false;
3418 }
3419 if (!cs.present)
3420 return false;
3421
3422 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3423 return true;
3424}
3425
3426static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3427{
3428 struct kvm_segment ss;
3429 unsigned int ss_rpl;
3430
3431 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3432 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3433
1872a3f4
AK		 3434 if (ss.unusable)
3435 return true;
3436 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3437 return false;
3438 if (!ss.s)
3439 return false;
3440 if (ss.dpl != ss_rpl) /* DPL != RPL */
3441 return false;
3442 if (!ss.present)
3443 return false;
3444
3445 return true;
3446}
3447
3448static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3449{
3450 struct kvm_segment var;
3451 unsigned int rpl;
3452
3453 vmx_get_segment(vcpu, &var, seg);
3454 rpl = var.selector & SELECTOR_RPL_MASK;
3455
1872a3f4
AK		 3456 if (var.unusable)
3457 return true;
648dfaa7
MG		 3458 if (!var.s)
3459 return false;
3460 if (!var.present)
3461 return false;
3462 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3463 if (var.dpl < rpl) /* DPL < RPL */
3464 return false;
3465 }
3466
3467 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3468 * rights flags
3469 */
3470 return true;
3471}
3472
3473static bool tr_valid(struct kvm_vcpu *vcpu)
3474{
3475 struct kvm_segment tr;
3476
3477 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3478
1872a3f4
AK		 3479 if (tr.unusable)
3480 return false;
648dfaa7
MG		 3481 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3482 return false;
1872a3f4 3483 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3484 return false;
3485 if (!tr.present)
3486 return false;
3487
3488 return true;
3489}
3490
3491static bool ldtr_valid(struct kvm_vcpu *vcpu)
3492{
3493 struct kvm_segment ldtr;
3494
3495 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3496
1872a3f4
AK		 3497 if (ldtr.unusable)
3498 return true;
648dfaa7
MG		 3499 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3500 return false;
3501 if (ldtr.type != 2)
3502 return false;
3503 if (!ldtr.present)
3504 return false;
3505
3506 return true;
3507}
3508
3509static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3510{
3511 struct kvm_segment cs, ss;
3512
3513 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3514 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3515
3516 return ((cs.selector & SELECTOR_RPL_MASK) ==
3517 (ss.selector & SELECTOR_RPL_MASK));
3518}
3519
3520/*
3521 * Check if guest state is valid. Returns true if valid, false if
3522 * not.
3523 * We assume that registers are always usable
3524 */
3525static bool guest_state_valid(struct kvm_vcpu *vcpu)
3526{
3527 /* real mode guest state checks */
3eeb3288 3528 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3529 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3530 return false;
3531 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3532 return false;
3533 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3534 return false;
3535 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3536 return false;
3537 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3538 return false;
3539 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3540 return false;
3541 } else {
3542 /* protected mode guest state checks */
3543 if (!cs_ss_rpl_check(vcpu))
3544 return false;
3545 if (!code_segment_valid(vcpu))
3546 return false;
3547 if (!stack_segment_valid(vcpu))
3548 return false;
3549 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3550 return false;
3551 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3552 return false;
3553 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3554 return false;
3555 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3556 return false;
3557 if (!tr_valid(vcpu))
3558 return false;
3559 if (!ldtr_valid(vcpu))
3560 return false;
3561 }
3562 /* TODO:
3563 * - Add checks on RIP
3564 * - Add checks on RFLAGS
3565 */
3566
3567 return true;
3568}
3569
d77c26fc 3570static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3571{
40dcaa9f 3572 gfn_t fn;
195aefde 3573 u16 data = 0;
40dcaa9f 3574 int r, idx, ret = 0;
6aa8b732 3575
40dcaa9f
XG		 3576 idx = srcu_read_lock(&kvm->srcu);
3577 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3578 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3579 if (r < 0)
10589a46 3580 goto out;
195aefde 3581 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3582 r = kvm_write_guest_page(kvm, fn++, &data,
3583 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3584 if (r < 0)
10589a46 3585 goto out;
195aefde
IE		 3586 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3587 if (r < 0)
10589a46 3588 goto out;
195aefde
IE		 3589 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3590 if (r < 0)
10589a46 3591 goto out;
195aefde 3592 data = ~0;
10589a46
MT		 3593 r = kvm_write_guest_page(kvm, fn, &data,
3594 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3595 sizeof(u8));
195aefde 3596 if (r < 0)
10589a46
MT		 3597 goto out;
3598
3599 ret = 1;
3600out:
40dcaa9f 3601 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3602 return ret;
6aa8b732
AK		 3603}
3604
b7ebfb05
SY		 3605static int init_rmode_identity_map(struct kvm *kvm)
3606{
40dcaa9f 3607 int i, idx, r, ret;
b7ebfb05
SY		 3608 pfn_t identity_map_pfn;
3609 u32 tmp;
3610
089d034e 3611 if (!enable_ept)
b7ebfb05
SY		 3612 return 1;
3613 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3614 printk(KERN_ERR "EPT: identity-mapping pagetable "
3615 "haven't been allocated!\n");
3616 return 0;
3617 }
3618 if (likely(kvm->arch.ept_identity_pagetable_done))
3619 return 1;
3620 ret = 0;
b927a3ce 3621 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3622 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3623 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3624 if (r < 0)
3625 goto out;
3626 /* Set up identity-mapping pagetable for EPT in real mode */
3627 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3628 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3629 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3630 r = kvm_write_guest_page(kvm, identity_map_pfn,
3631 &tmp, i * sizeof(tmp), sizeof(tmp));
3632 if (r < 0)
3633 goto out;
3634 }
3635 kvm->arch.ept_identity_pagetable_done = true;
3636 ret = 1;
3637out:
40dcaa9f 3638 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3639 return ret;
3640}
3641
6aa8b732
AK		 3642static void seg_setup(int seg)
3643{
772e0318 3644 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3645 unsigned int ar;
6aa8b732
AK		 3646
3647 vmcs_write16(sf->selector, 0);
3648 vmcs_writel(sf->base, 0);
3649 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3650 if (enable_unrestricted_guest) {
3651 ar = 0x93;
3652 if (seg == VCPU_SREG_CS)
3653 ar |= 0x08; /* code segment */
3654 } else
3655 ar = 0xf3;
3656
3657 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3658}
3659
f78e0e2e
SY		 3660static int alloc_apic_access_page(struct kvm *kvm)
3661{
4484141a 3662 struct page *page;
f78e0e2e
SY		 3663 struct kvm_userspace_memory_region kvm_userspace_mem;
3664 int r = 0;
3665
79fac95e 3666 mutex_lock(&kvm->slots_lock);
bfc6d222 3667 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3668 goto out;
3669 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3670 kvm_userspace_mem.flags = 0;
3671 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3672 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3673 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
f78e0e2e
SY		 3674 if (r)
3675 goto out;
72dc67a6 3676
4484141a
XG		 3677 page = gfn_to_page(kvm, 0xfee00);
3678 if (is_error_page(page)) {
3679 r = -EFAULT;
3680 goto out;
3681 }
3682
3683 kvm->arch.apic_access_page = page;
f78e0e2e 3684out:
79fac95e 3685 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3686 return r;
3687}
3688
b7ebfb05
SY		 3689static int alloc_identity_pagetable(struct kvm *kvm)
3690{
4484141a 3691 struct page *page;
b7ebfb05
SY		 3692 struct kvm_userspace_memory_region kvm_userspace_mem;
3693 int r = 0;
3694
79fac95e 3695 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3696 if (kvm->arch.ept_identity_pagetable)
3697 goto out;
3698 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3699 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3700 kvm_userspace_mem.guest_phys_addr =
3701 kvm->arch.ept_identity_map_addr;
b7ebfb05 3702 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3703 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
b7ebfb05
SY		 3704 if (r)
3705 goto out;
3706
4484141a
XG		 3707 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3708 if (is_error_page(page)) {
3709 r = -EFAULT;
3710 goto out;
3711 }
3712
3713 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3714out:
79fac95e 3715 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3716 return r;
3717}
3718
2384d2b3
SY		 3719static void allocate_vpid(struct vcpu_vmx *vmx)
3720{
3721 int vpid;
3722
3723 vmx->vpid = 0;
919818ab 3724 if (!enable_vpid)
2384d2b3
SY		 3725 return;
3726 spin_lock(&vmx_vpid_lock);
3727 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3728 if (vpid < VMX_NR_VPIDS) {
3729 vmx->vpid = vpid;
3730 __set_bit(vpid, vmx_vpid_bitmap);
3731 }
3732 spin_unlock(&vmx_vpid_lock);
3733}
3734
cdbecfc3
LJ		 3735static void free_vpid(struct vcpu_vmx *vmx)
3736{
3737 if (!enable_vpid)
3738 return;
3739 spin_lock(&vmx_vpid_lock);
3740 if (vmx->vpid != 0)
3741 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3742 spin_unlock(&vmx_vpid_lock);
3743}
3744
5897297b 3745static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3746{
3e7c73e9 3747 int f = sizeof(unsigned long);
25c5f225
SY		 3748
3749 if (!cpu_has_vmx_msr_bitmap())
3750 return;
3751
3752 /*
3753 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3754 * have the write-low and read-high bitmap offsets the wrong way round.
3755 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3756 */
25c5f225 3757 if (msr <= 0x1fff) {
3e7c73e9
AK		 3758 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3759 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3760 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3761 msr &= 0x1fff;
3e7c73e9
AK		 3762 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3763 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3764 }
25c5f225
SY		 3765}
3766
5897297b
AK		 3767static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3768{
3769 if (!longmode_only)
3770 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3771 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3772}
3773
a3a8ff8e
NHE		 3774/*
3775 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3776 * will not change in the lifetime of the guest.
3777 * Note that host-state that does change is set elsewhere. E.g., host-state
3778 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3779 */
3780static void vmx_set_constant_host_state(void)
3781{
3782 u32 low32, high32;
3783 unsigned long tmpl;
3784 struct desc_ptr dt;
3785
b1a74bf8 3786 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3787 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3788 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3789
3790 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3791#ifdef CONFIG_X86_64
3792 /*
3793 * Load null selectors, so we can avoid reloading them in
3794 * __vmx_load_host_state(), in case userspace uses the null selectors
3795 * too (the expected case).
3796 */
3797 vmcs_write16(HOST_DS_SELECTOR, 0);
3798 vmcs_write16(HOST_ES_SELECTOR, 0);
3799#else
a3a8ff8e
NHE		 3800 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3801 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3802#endif
a3a8ff8e
NHE		 3803 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3804 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3805
3806 native_store_idt(&dt);
3807 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3808
83287ea4 3809 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3810
3811 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3812 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3813 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3814 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3815
3816 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3817 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3818 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3819 }
3820}
3821
bf8179a0
NHE		 3822static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3823{
3824 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3825 if (enable_ept)
3826 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3827 if (is_guest_mode(&vmx->vcpu))
3828 vmx->vcpu.arch.cr4_guest_owned_bits &=
3829 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3830 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3831}
3832
3833static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3834{
3835 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3836 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3837 exec_control &= ~CPU_BASED_TPR_SHADOW;
3838#ifdef CONFIG_X86_64
3839 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3840 CPU_BASED_CR8_LOAD_EXITING;
3841#endif
3842 }
3843 if (!enable_ept)
3844 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3845 CPU_BASED_CR3_LOAD_EXITING |
3846 CPU_BASED_INVLPG_EXITING;
3847 return exec_control;
3848}
3849
3850static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3851{
3852 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3853 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3854 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3855 if (vmx->vpid == 0)
3856 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3857 if (!enable_ept) {
3858 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3859 enable_unrestricted_guest = 0;
ad756a16
MJ		 3860 /* Enable INVPCID for non-ept guests may cause performance regression. */
3861 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3862 }
3863 if (!enable_unrestricted_guest)
3864 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3865 if (!ple_gap)
3866 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3867 return exec_control;
3868}
3869
ce88decf
XG		 3870static void ept_set_mmio_spte_mask(void)
3871{
3872 /*
3873 * EPT Misconfigurations can be generated if the value of bits 2:0
3874 * of an EPT paging-structure entry is 110b (write/execute).
3875 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3876 * spte.
3877 */
3878 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3879}
3880
6aa8b732
AK		 3881/*
3882 * Sets up the vmcs for emulated real mode.
3883 */
8b9cf98c 3884static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3885{
2e4ce7f5 3886#ifdef CONFIG_X86_64
6aa8b732 3887 unsigned long a;
2e4ce7f5 3888#endif
6aa8b732 3889 int i;
6aa8b732 3890
6aa8b732 3891 /* I/O */
3e7c73e9
AK		 3892 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3893 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3894
25c5f225 3895 if (cpu_has_vmx_msr_bitmap())
5897297b 3896 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3897
6aa8b732
AK		 3898 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3899
6aa8b732 3900 /* Control */
1c3d14fe
YS		 3901 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3902 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3903
bf8179a0 3904 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3905
83ff3b9d 3906 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3907 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3908 vmx_secondary_exec_control(vmx));
83ff3b9d 3909 }
f78e0e2e 3910
4b8d54f9
ZE		 3911 if (ple_gap) {
3912 vmcs_write32(PLE_GAP, ple_gap);
3913 vmcs_write32(PLE_WINDOW, ple_window);
3914 }
3915
c3707958
XG		 3916 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3917 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3918 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3919
9581d442
AK		 3920 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3921 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3922 vmx_set_constant_host_state();
05b3e0c2 3923#ifdef CONFIG_X86_64
6aa8b732
AK		 3924 rdmsrl(MSR_FS_BASE, a);
3925 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3926 rdmsrl(MSR_GS_BASE, a);
3927 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3928#else
3929 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3930 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3931#endif
3932
2cc51560
ED		 3933 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3934 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3935 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3936 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3937 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3938
468d472f 3939 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3940 u32 msr_low, msr_high;
3941 u64 host_pat;
468d472f
SY		 3942 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3943 host_pat = msr_low | ((u64) msr_high << 32);
3944 /* Write the default value follow host pat */
3945 vmcs_write64(GUEST_IA32_PAT, host_pat);
3946 /* Keep arch.pat sync with GUEST_IA32_PAT */
3947 vmx->vcpu.arch.pat = host_pat;
3948 }
3949
6aa8b732
AK		 3950 for (i = 0; i < NR_VMX_MSR; ++i) {
3951 u32 index = vmx_msr_index[i];
3952 u32 data_low, data_high;
a2fa3e9f 3953 int j = vmx->nmsrs;
6aa8b732
AK		 3954
3955 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3956 continue;
432bd6cb
AK		 3957 if (wrmsr_safe(index, data_low, data_high) < 0)
3958 continue;
26bb0981
AK		 3959 vmx->guest_msrs[j].index = i;
3960 vmx->guest_msrs[j].data = 0;
d5696725 3961 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3962 ++vmx->nmsrs;
6aa8b732 3963 }
6aa8b732 3964
1c3d14fe 3965 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3966
3967 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3968 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3969
e00c8cf2 3970 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3971 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 3972
3973 return 0;
3974}
3975
3976static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3977{
3978 struct vcpu_vmx *vmx = to_vmx(vcpu);
3979 u64 msr;
4b9d3a04 3980 int ret;
e00c8cf2 3981
7ffd92c5 3982 vmx->rmode.vm86_active = 0;
e00c8cf2 3983
3b86cd99
JK		 3984 vmx->soft_vnmi_blocked = 0;
3985
ad312c7c 3986 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3987 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3988 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3989 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3990 msr |= MSR_IA32_APICBASE_BSP;
3991 kvm_set_apic_base(&vmx->vcpu, msr);
3992
2fb92db1
AK		 3993 vmx_segment_cache_clear(vmx);
3994
5706be0d 3995 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3996 /*
3997 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3998 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3999 */
c5af89b6 4000 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 4001 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4002 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
4003 } else {
ad312c7c
ZX		 4004 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
4005 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 4006 }
e00c8cf2
AK		 4007
4008 seg_setup(VCPU_SREG_DS);
4009 seg_setup(VCPU_SREG_ES);
4010 seg_setup(VCPU_SREG_FS);
4011 seg_setup(VCPU_SREG_GS);
4012 seg_setup(VCPU_SREG_SS);
4013
4014 vmcs_write16(GUEST_TR_SELECTOR, 0);
4015 vmcs_writel(GUEST_TR_BASE, 0);
4016 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4017 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4018
4019 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4020 vmcs_writel(GUEST_LDTR_BASE, 0);
4021 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4022 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4023
4024 vmcs_write32(GUEST_SYSENTER_CS, 0);
4025 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4026 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4027
4028 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 4029 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 4030 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4031 else
5fdbf976 4032 kvm_rip_write(vcpu, 0);
e00c8cf2 4033
e00c8cf2
AK		 4034 vmcs_writel(GUEST_GDTR_BASE, 0);
4035 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4036
4037 vmcs_writel(GUEST_IDTR_BASE, 0);
4038 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4039
443381a8 4040 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4041 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4042 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4043
e00c8cf2
AK		 4044 /* Special registers */
4045 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4046
4047 setup_msrs(vmx);
4048
6aa8b732
AK		 4049 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4050
f78e0e2e
SY		 4051 if (cpu_has_vmx_tpr_shadow()) {
4052 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4053 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4054 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4055 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4056 vmcs_write32(TPR_THRESHOLD, 0);
4057 }
4058
4059 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4060 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4061 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4062
2384d2b3
SY		 4063 if (vmx->vpid != 0)
4064 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4065
fa40052c 4066 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4067 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4068 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4069 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4070 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4071 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4072 vmx_fpu_activate(&vmx->vcpu);
4073 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4074
b9d762fa 4075 vpid_sync_context(vmx);
2384d2b3 4076
3200f405 4077 ret = 0;
6aa8b732 4078
a89a8fb9
MG		 4079 /* HACK: Don't enable emulation on guest boot/reset */
4080 vmx->emulation_required = 0;
4081
6aa8b732
AK		 4082 return ret;
4083}
4084
b6f1250e
NHE		 4085/*
4086 * In nested virtualization, check if L1 asked to exit on external interrupts.
4087 * For most existing hypervisors, this will always return true.
4088 */
4089static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4090{
4091 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4092 PIN_BASED_EXT_INTR_MASK;
4093}
4094
3b86cd99
JK		 4095static void enable_irq_window(struct kvm_vcpu *vcpu)
4096{
4097 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4098 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4099 /*
4100 * We get here if vmx_interrupt_allowed() said we can't
4101 * inject to L1 now because L2 must run. Ask L2 to exit
4102 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4103 */
d6185f20 4104 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4105 return;
d6185f20 4106 }
3b86cd99
JK		 4107
4108 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4109 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4110 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4111}
4112
4113static void enable_nmi_window(struct kvm_vcpu *vcpu)
4114{
4115 u32 cpu_based_vm_exec_control;
4116
4117 if (!cpu_has_virtual_nmis()) {
4118 enable_irq_window(vcpu);
4119 return;
4120 }
4121
30bd0c4c
AK		 4122 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4123 enable_irq_window(vcpu);
4124 return;
4125 }
3b86cd99
JK		 4126 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4127 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4128 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4129}
4130
66fd3f7f 4131static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4132{
9c8cba37 4133 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4134 uint32_t intr;
4135 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4136
229456fc 4137 trace_kvm_inj_virq(irq);
2714d1d3 4138
fa89a817 4139 ++vcpu->stat.irq_injections;
7ffd92c5 4140 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4141 int inc_eip = 0;
4142 if (vcpu->arch.interrupt.soft)
4143 inc_eip = vcpu->arch.event_exit_inst_len;
4144 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4145 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4146 return;
4147 }
66fd3f7f
GN		 4148 intr = irq | INTR_INFO_VALID_MASK;
4149 if (vcpu->arch.interrupt.soft) {
4150 intr |= INTR_TYPE_SOFT_INTR;
4151 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4152 vmx->vcpu.arch.event_exit_inst_len);
4153 } else
4154 intr |= INTR_TYPE_EXT_INTR;
4155 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4156}
4157
f08864b4
SY		 4158static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4159{
66a5a347
JK		 4160 struct vcpu_vmx *vmx = to_vmx(vcpu);
4161
0b6ac343
NHE		 4162 if (is_guest_mode(vcpu))
4163 return;
4164
3b86cd99
JK		 4165 if (!cpu_has_virtual_nmis()) {
4166 /*
4167 * Tracking the NMI-blocked state in software is built upon
4168 * finding the next open IRQ window. This, in turn, depends on
4169 * well-behaving guests: They have to keep IRQs disabled at
4170 * least as long as the NMI handler runs. Otherwise we may
4171 * cause NMI nesting, maybe breaking the guest. But as this is
4172 * highly unlikely, we can live with the residual risk.
4173 */
4174 vmx->soft_vnmi_blocked = 1;
4175 vmx->vnmi_blocked_time = 0;
4176 }
4177
487b391d 4178 ++vcpu->stat.nmi_injections;
9d58b931 4179 vmx->nmi_known_unmasked = false;
7ffd92c5 4180 if (vmx->rmode.vm86_active) {
71f9833b 4181 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4182 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4183 return;
4184 }
f08864b4
SY		 4185 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4186 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4187}
4188
c4282df9 4189static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4190{
3b86cd99 4191 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4192 return 0;
33f089ca 4193
c4282df9 4194 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4195 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4196 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4197}
4198
3cfc3092
JK		 4199static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4200{
4201 if (!cpu_has_virtual_nmis())
4202 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4203 if (to_vmx(vcpu)->nmi_known_unmasked)
4204 return false;
c332c83a 4205 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4206}
4207
4208static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4209{
4210 struct vcpu_vmx *vmx = to_vmx(vcpu);
4211
4212 if (!cpu_has_virtual_nmis()) {
4213 if (vmx->soft_vnmi_blocked != masked) {
4214 vmx->soft_vnmi_blocked = masked;
4215 vmx->vnmi_blocked_time = 0;
4216 }
4217 } else {
9d58b931 4218 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4219 if (masked)
4220 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4221 GUEST_INTR_STATE_NMI);
4222 else
4223 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4224 GUEST_INTR_STATE_NMI);
4225 }
4226}
4227
78646121
GN		 4228static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4229{
b6f1250e 4230 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4231 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4232 if (to_vmx(vcpu)->nested.nested_run_pending ||
4233 (vmcs12->idt_vectoring_info_field &
4234 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4235 return 0;
4236 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4237 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4238 vmcs12->vm_exit_intr_info = 0;
4239 /* fall through to normal code, but now in L1, not L2 */
4240 }
4241
c4282df9
GN		 4242 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4243 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4244 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4245}
4246
cbc94022
IE		 4247static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4248{
4249 int ret;
4250 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4251 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4252 .guest_phys_addr = addr,
4253 .memory_size = PAGE_SIZE * 3,
4254 .flags = 0,
4255 };
4256
f82a8cfe 4257 ret = kvm_set_memory_region(kvm, &tss_mem, false);
cbc94022
IE		 4258 if (ret)
4259 return ret;
bfc6d222 4260 kvm->arch.tss_addr = addr;
93ea5388
GN		 4261 if (!init_rmode_tss(kvm))
4262 return -ENOMEM;
4263
cbc94022
IE		 4264 return 0;
4265}
4266
6aa8b732
AK		 4267static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4268 int vec, u32 err_code)
4269{
b3f37707
NK		 4270 /*
4271 * Instruction with address size override prefix opcode 0x67
4272 * Cause the #SS fault with 0 error code in VM86 mode.
4273 */
4274 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4275 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4276 return 1;
77ab6db0
JK		 4277 /*
4278 * Forward all other exceptions that are valid in real mode.
4279 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4280 * the required debugging infrastructure rework.
4281 */
4282 switch (vec) {
77ab6db0 4283 case DB_VECTOR:
d0bfb940
JK		 4284 if (vcpu->guest_debug &
4285 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4286 return 0;
4287 kvm_queue_exception(vcpu, vec);
4288 return 1;
77ab6db0 4289 case BP_VECTOR:
c573cd22
JK		 4290 /*
4291 * Update instruction length as we may reinject the exception
4292 * from user space while in guest debugging mode.
4293 */
4294 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4295 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4296 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4297 return 0;
4298 /* fall through */
4299 case DE_VECTOR:
77ab6db0
JK		 4300 case OF_VECTOR:
4301 case BR_VECTOR:
4302 case UD_VECTOR:
4303 case DF_VECTOR:
4304 case SS_VECTOR:
4305 case GP_VECTOR:
4306 case MF_VECTOR:
4307 kvm_queue_exception(vcpu, vec);
4308 return 1;
4309 }
6aa8b732
AK		 4310 return 0;
4311}
4312
a0861c02
AK		 4313/*
4314 * Trigger machine check on the host. We assume all the MSRs are already set up
4315 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4316 * We pass a fake environment to the machine check handler because we want
4317 * the guest to be always treated like user space, no matter what context
4318 * it used internally.
4319 */
4320static void kvm_machine_check(void)
4321{
4322#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4323 struct pt_regs regs = {
4324 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4325 .flags = X86_EFLAGS_IF,
4326 };
4327
4328 do_machine_check(&regs, 0);
4329#endif
4330}
4331
851ba692 4332static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4333{
4334 /* already handled by vcpu_run */
4335 return 1;
4336}
4337
851ba692 4338static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4339{
1155f76a 4340 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4341 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4342 u32 intr_info, ex_no, error_code;
42dbaa5a 4343 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4344 u32 vect_info;
4345 enum emulation_result er;
4346
1155f76a 4347 vect_info = vmx->idt_vectoring_info;
88786475 4348 intr_info = vmx->exit_intr_info;
6aa8b732 4349
a0861c02 4350 if (is_machine_check(intr_info))
851ba692 4351 return handle_machine_check(vcpu);
a0861c02 4352
e4a41889 4353 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4354 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4355
4356 if (is_no_device(intr_info)) {
5fd86fcf 4357 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4358 return 1;
4359 }
4360
7aa81cc0 4361 if (is_invalid_opcode(intr_info)) {
51d8b661 4362 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4363 if (er != EMULATE_DONE)
7ee5d940 4364 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4365 return 1;
4366 }
4367
6aa8b732 4368 error_code = 0;
2e11384c 4369 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4370 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4371
4372 /*
4373 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4374 * MMIO, it is better to report an internal error.
4375 * See the comments in vmx_handle_exit.
4376 */
4377 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4378 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4379 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4380 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4381 vcpu->run->internal.ndata = 2;
4382 vcpu->run->internal.data[0] = vect_info;
4383 vcpu->run->internal.data[1] = intr_info;
4384 return 0;
4385 }
4386
6aa8b732 4387 if (is_page_fault(intr_info)) {
1439442c 4388 /* EPT won't cause page fault directly */
cf3ace79 4389 BUG_ON(enable_ept);
6aa8b732 4390 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4391 trace_kvm_page_fault(cr2, error_code);
4392
3298b75c 4393 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4394 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4395 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4396 }
4397
7ffd92c5 4398 if (vmx->rmode.vm86_active &&
6aa8b732 4399 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4400 error_code)) {
ad312c7c
ZX		 4401 if (vcpu->arch.halt_request) {
4402 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4403 return kvm_emulate_halt(vcpu);
4404 }
6aa8b732 4405 return 1;
72d6e5a0 4406 }
6aa8b732 4407
d0bfb940 4408 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4409 switch (ex_no) {
4410 case DB_VECTOR:
4411 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4412 if (!(vcpu->guest_debug &
4413 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4414 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4415 kvm_queue_exception(vcpu, DB_VECTOR);
4416 return 1;
4417 }
4418 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4419 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4420 /* fall through */
4421 case BP_VECTOR:
c573cd22
JK		 4422 /*
4423 * Update instruction length as we may reinject #BP from
4424 * user space while in guest debugging mode. Reading it for
4425 * #DB as well causes no harm, it is not used in that case.
4426 */
4427 vmx->vcpu.arch.event_exit_inst_len =
4428 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4429 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4430 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4431 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4432 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4433 break;
4434 default:
d0bfb940
JK		 4435 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4436 kvm_run->ex.exception = ex_no;
4437 kvm_run->ex.error_code = error_code;
42dbaa5a 4438 break;
6aa8b732 4439 }
6aa8b732
AK		 4440 return 0;
4441}
4442
851ba692 4443static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4444{
1165f5fe 4445 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4446 return 1;
4447}
4448
851ba692 4449static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4450{
851ba692 4451 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4452 return 0;
4453}
6aa8b732 4454
851ba692 4455static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4456{
bfdaab09 4457 unsigned long exit_qualification;
34c33d16 4458 int size, in, string;
039576c0 4459 unsigned port;
6aa8b732 4460
bfdaab09 4461 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4462 string = (exit_qualification & 16) != 0;
cf8f70bf 4463 in = (exit_qualification & 8) != 0;
e70669ab 4464
cf8f70bf 4465 ++vcpu->stat.io_exits;
e70669ab 4466
cf8f70bf 4467 if (string || in)
51d8b661 4468 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4469
cf8f70bf
GN		 4470 port = exit_qualification >> 16;
4471 size = (exit_qualification & 7) + 1;
e93f36bc 4472 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4473
4474 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4475}
4476
102d8325
IM		 4477static void
4478vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4479{
4480 /*
4481 * Patch in the VMCALL instruction:
4482 */
4483 hypercall[0] = 0x0f;
4484 hypercall[1] = 0x01;
4485 hypercall[2] = 0xc1;
102d8325
IM		 4486}
4487
0fa06071 4488/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4489static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4490{
4491 if (to_vmx(vcpu)->nested.vmxon &&
4492 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4493 return 1;
4494
4495 if (is_guest_mode(vcpu)) {
4496 /*
4497 * We get here when L2 changed cr0 in a way that did not change
4498 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4499 * but did change L0 shadowed bits. This can currently happen
4500 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4501 * loading) while pretending to allow the guest to change it.
4502 */
4503 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4504 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4505 return 1;
4506 vmcs_writel(CR0_READ_SHADOW, val);
4507 return 0;
4508 } else
4509 return kvm_set_cr0(vcpu, val);
4510}
4511
4512static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4513{
4514 if (is_guest_mode(vcpu)) {
4515 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4516 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4517 return 1;
4518 vmcs_writel(CR4_READ_SHADOW, val);
4519 return 0;
4520 } else
4521 return kvm_set_cr4(vcpu, val);
4522}
4523
4524/* called to set cr0 as approriate for clts instruction exit. */
4525static void handle_clts(struct kvm_vcpu *vcpu)
4526{
4527 if (is_guest_mode(vcpu)) {
4528 /*
4529 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4530 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4531 * just pretend it's off (also in arch.cr0 for fpu_activate).
4532 */
4533 vmcs_writel(CR0_READ_SHADOW,
4534 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4535 vcpu->arch.cr0 &= ~X86_CR0_TS;
4536 } else
4537 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4538}
4539
851ba692 4540static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4541{
229456fc 4542 unsigned long exit_qualification, val;
6aa8b732
AK		 4543 int cr;
4544 int reg;
49a9b07e 4545 int err;
6aa8b732 4546
bfdaab09 4547 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4548 cr = exit_qualification & 15;
4549 reg = (exit_qualification >> 8) & 15;
4550 switch ((exit_qualification >> 4) & 3) {
4551 case 0: /* mov to cr */
229456fc
MT		 4552 val = kvm_register_read(vcpu, reg);
4553 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4554 switch (cr) {
4555 case 0:
eeadf9e7 4556 err = handle_set_cr0(vcpu, val);
db8fcefa 4557 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4558 return 1;
4559 case 3:
2390218b 4560 err = kvm_set_cr3(vcpu, val);
db8fcefa 4561 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4562 return 1;
4563 case 4:
eeadf9e7 4564 err = handle_set_cr4(vcpu, val);
db8fcefa 4565 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4566 return 1;
0a5fff19
GN		 4567 case 8: {
4568 u8 cr8_prev = kvm_get_cr8(vcpu);
4569 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4570 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4571 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4572 if (irqchip_in_kernel(vcpu->kvm))
4573 return 1;
4574 if (cr8_prev <= cr8)
4575 return 1;
851ba692 4576 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4577 return 0;
4578 }
4b8073e4 4579 }
6aa8b732 4580 break;
25c4c276 4581 case 2: /* clts */
eeadf9e7 4582 handle_clts(vcpu);
4d4ec087 4583 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4584 skip_emulated_instruction(vcpu);
6b52d186 4585 vmx_fpu_activate(vcpu);
25c4c276 4586 return 1;
6aa8b732
AK		 4587 case 1: /*mov from cr*/
4588 switch (cr) {
4589 case 3:
9f8fe504
AK		 4590 val = kvm_read_cr3(vcpu);
4591 kvm_register_write(vcpu, reg, val);
4592 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4593 skip_emulated_instruction(vcpu);
4594 return 1;
4595 case 8:
229456fc
MT		 4596 val = kvm_get_cr8(vcpu);
4597 kvm_register_write(vcpu, reg, val);
4598 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4599 skip_emulated_instruction(vcpu);
4600 return 1;
4601 }
4602 break;
4603 case 3: /* lmsw */
a1f83a74 4604 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4605 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4606 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4607
4608 skip_emulated_instruction(vcpu);
4609 return 1;
4610 default:
4611 break;
4612 }
851ba692 4613 vcpu->run->exit_reason = 0;
a737f256 4614 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4615 (int)(exit_qualification >> 4) & 3, cr);
4616 return 0;
4617}
4618
851ba692 4619static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4620{
bfdaab09 4621 unsigned long exit_qualification;
6aa8b732
AK		 4622 int dr, reg;
4623
f2483415 4624 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4625 if (!kvm_require_cpl(vcpu, 0))
4626 return 1;
42dbaa5a
JK		 4627 dr = vmcs_readl(GUEST_DR7);
4628 if (dr & DR7_GD) {
4629 /*
4630 * As the vm-exit takes precedence over the debug trap, we
4631 * need to emulate the latter, either for the host or the
4632 * guest debugging itself.
4633 */
4634 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4635 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4636 vcpu->run->debug.arch.dr7 = dr;
4637 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4638 vmcs_readl(GUEST_CS_BASE) +
4639 vmcs_readl(GUEST_RIP);
851ba692
AK		 4640 vcpu->run->debug.arch.exception = DB_VECTOR;
4641 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4642 return 0;
4643 } else {
4644 vcpu->arch.dr7 &= ~DR7_GD;
4645 vcpu->arch.dr6 |= DR6_BD;
4646 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4647 kvm_queue_exception(vcpu, DB_VECTOR);
4648 return 1;
4649 }
4650 }
4651
bfdaab09 4652 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4653 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4654 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4655 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4656 unsigned long val;
4657 if (!kvm_get_dr(vcpu, dr, &val))
4658 kvm_register_write(vcpu, reg, val);
4659 } else
4660 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4661 skip_emulated_instruction(vcpu);
4662 return 1;
4663}
4664
020df079
GN		 4665static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4666{
4667 vmcs_writel(GUEST_DR7, val);
4668}
4669
851ba692 4670static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4671{
06465c5a
AK		 4672 kvm_emulate_cpuid(vcpu);
4673 return 1;
6aa8b732
AK		 4674}
4675
851ba692 4676static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4677{
ad312c7c 4678 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4679 u64 data;
4680
4681 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4682 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4683 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4684 return 1;
4685 }
4686
229456fc 4687 trace_kvm_msr_read(ecx, data);
2714d1d3 4688
6aa8b732 4689 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4690 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4691 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4692 skip_emulated_instruction(vcpu);
4693 return 1;
4694}
4695
851ba692 4696static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4697{
8fe8ab46 4698 struct msr_data msr;
ad312c7c
ZX		 4699 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4700 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4701 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4702
8fe8ab46
WA		 4703 msr.data = data;
4704 msr.index = ecx;
4705 msr.host_initiated = false;
4706 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4707 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4708 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4709 return 1;
4710 }
4711
59200273 4712 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4713 skip_emulated_instruction(vcpu);
4714 return 1;
4715}
4716
851ba692 4717static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4718{
3842d135 4719 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4720 return 1;
4721}
4722
851ba692 4723static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4724{
85f455f7
ED		 4725 u32 cpu_based_vm_exec_control;
4726
4727 /* clear pending irq */
4728 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4729 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4730 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4731
3842d135
AK		 4732 kvm_make_request(KVM_REQ_EVENT, vcpu);
4733
a26bf12a 4734 ++vcpu->stat.irq_window_exits;
2714d1d3 4735
c1150d8c
DL		 4736 /*
4737 * If the user space waits to inject interrupts, exit as soon as
4738 * possible
4739 */
8061823a 4740 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4741 vcpu->run->request_interrupt_window &&
8061823a 4742 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4743 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4744 return 0;
4745 }
6aa8b732
AK		 4746 return 1;
4747}
4748
851ba692 4749static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4750{
4751 skip_emulated_instruction(vcpu);
d3bef15f 4752 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4753}
4754
851ba692 4755static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4756{
510043da 4757 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4758 kvm_emulate_hypercall(vcpu);
4759 return 1;
c21415e8
IM		 4760}
4761
ec25d5e6
GN		 4762static int handle_invd(struct kvm_vcpu *vcpu)
4763{
51d8b661 4764 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4765}
4766
851ba692 4767static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4768{
f9c617f6 4769 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4770
4771 kvm_mmu_invlpg(vcpu, exit_qualification);
4772 skip_emulated_instruction(vcpu);
4773 return 1;
4774}
4775
fee84b07
AK		 4776static int handle_rdpmc(struct kvm_vcpu *vcpu)
4777{
4778 int err;
4779
4780 err = kvm_rdpmc(vcpu);
4781 kvm_complete_insn_gp(vcpu, err);
4782
4783 return 1;
4784}
4785
851ba692 4786static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4787{
4788 skip_emulated_instruction(vcpu);
f5f48ee1 4789 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4790 return 1;
4791}
4792
2acf923e
DC		 4793static int handle_xsetbv(struct kvm_vcpu *vcpu)
4794{
4795 u64 new_bv = kvm_read_edx_eax(vcpu);
4796 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4797
4798 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4799 skip_emulated_instruction(vcpu);
4800 return 1;
4801}
4802
851ba692 4803static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4804{
58fbbf26
KT		 4805 if (likely(fasteoi)) {
4806 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4807 int access_type, offset;
4808
4809 access_type = exit_qualification & APIC_ACCESS_TYPE;
4810 offset = exit_qualification & APIC_ACCESS_OFFSET;
4811 /*
4812 * Sane guest uses MOV to write EOI, with written value
4813 * not cared. So make a short-circuit here by avoiding
4814 * heavy instruction emulation.
4815 */
4816 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4817 (offset == APIC_EOI)) {
4818 kvm_lapic_set_eoi(vcpu);
4819 skip_emulated_instruction(vcpu);
4820 return 1;
4821 }
4822 }
51d8b661 4823 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4824}
4825
851ba692 4826static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4827{
60637aac 4828 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4829 unsigned long exit_qualification;
e269fb21
JK		 4830 bool has_error_code = false;
4831 u32 error_code = 0;
37817f29 4832 u16 tss_selector;
7f3d35fd 4833 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4834
4835 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4836 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4837 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4838
4839 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4840
4841 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4842 if (reason == TASK_SWITCH_GATE && idt_v) {
4843 switch (type) {
4844 case INTR_TYPE_NMI_INTR:
4845 vcpu->arch.nmi_injected = false;
654f06fc 4846 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4847 break;
4848 case INTR_TYPE_EXT_INTR:
66fd3f7f 4849 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4850 kvm_clear_interrupt_queue(vcpu);
4851 break;
4852 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4853 if (vmx->idt_vectoring_info &
4854 VECTORING_INFO_DELIVER_CODE_MASK) {
4855 has_error_code = true;
4856 error_code =
4857 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4858 }
4859 /* fall through */
64a7ec06
GN		 4860 case INTR_TYPE_SOFT_EXCEPTION:
4861 kvm_clear_exception_queue(vcpu);
4862 break;
4863 default:
4864 break;
4865 }
60637aac 4866 }
37817f29
IE		 4867 tss_selector = exit_qualification;
4868
64a7ec06
GN		 4869 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4870 type != INTR_TYPE_EXT_INTR &&
4871 type != INTR_TYPE_NMI_INTR))
4872 skip_emulated_instruction(vcpu);
4873
7f3d35fd
KW		 4874 if (kvm_task_switch(vcpu, tss_selector,
4875 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4876 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4877 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4878 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4879 vcpu->run->internal.ndata = 0;
42dbaa5a 4880 return 0;
acb54517 4881 }
42dbaa5a
JK		 4882
4883 /* clear all local breakpoint enable flags */
4884 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4885
4886 /*
4887 * TODO: What about debug traps on tss switch?
4888 * Are we supposed to inject them and update dr6?
4889 */
4890
4891 return 1;
37817f29
IE		 4892}
4893
851ba692 4894static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4895{
f9c617f6 4896 unsigned long exit_qualification;
1439442c 4897 gpa_t gpa;
4f5982a5 4898 u32 error_code;
1439442c 4899 int gla_validity;
1439442c 4900
f9c617f6 4901 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 4902
1439442c
SY		 4903 gla_validity = (exit_qualification >> 7) & 0x3;
4904 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4905 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4906 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4907 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4908 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4909 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4910 (long unsigned int)exit_qualification);
851ba692
AK		 4911 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4912 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4913 return 0;
1439442c
SY		 4914 }
4915
4916 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4917 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4918
4919 /* It is a write fault? */
4920 error_code = exit_qualification & (1U << 1);
4921 /* ept page table is present? */
4922 error_code |= (exit_qualification >> 3) & 0x1;
4923
4924 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4925}
4926
68f89400
MT		 4927static u64 ept_rsvd_mask(u64 spte, int level)
4928{
4929 int i;
4930 u64 mask = 0;
4931
4932 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4933 mask |= (1ULL << i);
4934
4935 if (level > 2)
4936 /* bits 7:3 reserved */
4937 mask |= 0xf8;
4938 else if (level == 2) {
4939 if (spte & (1ULL << 7))
4940 /* 2MB ref, bits 20:12 reserved */
4941 mask |= 0x1ff000;
4942 else
4943 /* bits 6:3 reserved */
4944 mask |= 0x78;
4945 }
4946
4947 return mask;
4948}
4949
4950static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4951 int level)
4952{
4953 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4954
4955 /* 010b (write-only) */
4956 WARN_ON((spte & 0x7) == 0x2);
4957
4958 /* 110b (write/execute) */
4959 WARN_ON((spte & 0x7) == 0x6);
4960
4961 /* 100b (execute-only) and value not supported by logical processor */
4962 if (!cpu_has_vmx_ept_execute_only())
4963 WARN_ON((spte & 0x7) == 0x4);
4964
4965 /* not 000b */
4966 if ((spte & 0x7)) {
4967 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4968
4969 if (rsvd_bits != 0) {
4970 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4971 __func__, rsvd_bits);
4972 WARN_ON(1);
4973 }
4974
4975 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4976 u64 ept_mem_type = (spte & 0x38) >> 3;
4977
4978 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4979 ept_mem_type == 7) {
4980 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4981 __func__, ept_mem_type);
4982 WARN_ON(1);
4983 }
4984 }
4985 }
4986}
4987
851ba692 4988static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4989{
4990 u64 sptes[4];
ce88decf 4991 int nr_sptes, i, ret;
68f89400
MT		 4992 gpa_t gpa;
4993
4994 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4995
ce88decf
XG		 4996 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4997 if (likely(ret == 1))
4998 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4999 EMULATE_DONE;
5000 if (unlikely(!ret))
5001 return 1;
5002
5003 /* It is the real ept misconfig */
68f89400
MT		 5004 printk(KERN_ERR "EPT: Misconfiguration.\n");
5005 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5006
5007 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5008
5009 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5010 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5011
851ba692
AK		 5012 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5013 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5014
5015 return 0;
5016}
5017
851ba692 5018static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5019{
5020 u32 cpu_based_vm_exec_control;
5021
5022 /* clear pending NMI */
5023 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5024 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5025 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5026 ++vcpu->stat.nmi_window_exits;
3842d135 5027 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5028
5029 return 1;
5030}
5031
80ced186 5032static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5033{
8b3079a5
AK		 5034 struct vcpu_vmx *vmx = to_vmx(vcpu);
5035 enum emulation_result err = EMULATE_DONE;
80ced186 5036 int ret = 1;
49e9d557
AK		 5037 u32 cpu_exec_ctrl;
5038 bool intr_window_requested;
b8405c18 5039 unsigned count = 130;
49e9d557
AK		 5040
5041 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5042 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5043
b8405c18 5044 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5045 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5046 return handle_interrupt_window(&vmx->vcpu);
5047
de87dcdd
AK		 5048 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5049 return 1;
5050
51d8b661 5051 err = emulate_instruction(vcpu, 0);
ea953ef0 5052
80ced186
MG		 5053 if (err == EMULATE_DO_MMIO) {
5054 ret = 0;
5055 goto out;
5056 }
1d5a4d9b 5057
de5f70e0
AK		 5058 if (err != EMULATE_DONE) {
5059 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5060 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5061 vcpu->run->internal.ndata = 0;
6d77dbfc 5062 return 0;
de5f70e0 5063 }
ea953ef0
MG		 5064
5065 if (signal_pending(current))
80ced186 5066 goto out;
ea953ef0
MG		 5067 if (need_resched())
5068 schedule();
5069 }
5070
7c068e45 5071 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5072out:
5073 return ret;
ea953ef0
MG		 5074}
5075
4b8d54f9
ZE		 5076/*
5077 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5078 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5079 */
9fb41ba8 5080static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5081{
5082 skip_emulated_instruction(vcpu);
5083 kvm_vcpu_on_spin(vcpu);
5084
5085 return 1;
5086}
5087
59708670
SY		 5088static int handle_invalid_op(struct kvm_vcpu *vcpu)
5089{
5090 kvm_queue_exception(vcpu, UD_VECTOR);
5091 return 1;
5092}
5093
ff2f6fe9
NHE		 5094/*
5095 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5096 * We could reuse a single VMCS for all the L2 guests, but we also want the
5097 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5098 * allows keeping them loaded on the processor, and in the future will allow
5099 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5100 * every entry if they never change.
5101 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5102 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5103 *
5104 * The following functions allocate and free a vmcs02 in this pool.
5105 */
5106
5107/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5108static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5109{
5110 struct vmcs02_list *item;
5111 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5112 if (item->vmptr == vmx->nested.current_vmptr) {
5113 list_move(&item->list, &vmx->nested.vmcs02_pool);
5114 return &item->vmcs02;
5115 }
5116
5117 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5118 /* Recycle the least recently used VMCS. */
5119 item = list_entry(vmx->nested.vmcs02_pool.prev,
5120 struct vmcs02_list, list);
5121 item->vmptr = vmx->nested.current_vmptr;
5122 list_move(&item->list, &vmx->nested.vmcs02_pool);
5123 return &item->vmcs02;
5124 }
5125
5126 /* Create a new VMCS */
5127 item = (struct vmcs02_list *)
5128 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5129 if (!item)
5130 return NULL;
5131 item->vmcs02.vmcs = alloc_vmcs();
5132 if (!item->vmcs02.vmcs) {
5133 kfree(item);
5134 return NULL;
5135 }
5136 loaded_vmcs_init(&item->vmcs02);
5137 item->vmptr = vmx->nested.current_vmptr;
5138 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5139 vmx->nested.vmcs02_num++;
5140 return &item->vmcs02;
5141}
5142
5143/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5144static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5145{
5146 struct vmcs02_list *item;
5147 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5148 if (item->vmptr == vmptr) {
5149 free_loaded_vmcs(&item->vmcs02);
5150 list_del(&item->list);
5151 kfree(item);
5152 vmx->nested.vmcs02_num--;
5153 return;
5154 }
5155}
5156
5157/*
5158 * Free all VMCSs saved for this vcpu, except the one pointed by
5159 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5160 * currently used, if running L2), and vmcs01 when running L2.
5161 */
5162static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5163{
5164 struct vmcs02_list *item, *n;
5165 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5166 if (vmx->loaded_vmcs != &item->vmcs02)
5167 free_loaded_vmcs(&item->vmcs02);
5168 list_del(&item->list);
5169 kfree(item);
5170 }
5171 vmx->nested.vmcs02_num = 0;
5172
5173 if (vmx->loaded_vmcs != &vmx->vmcs01)
5174 free_loaded_vmcs(&vmx->vmcs01);
5175}
5176
ec378aee
NHE		 5177/*
5178 * Emulate the VMXON instruction.
5179 * Currently, we just remember that VMX is active, and do not save or even
5180 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5181 * do not currently need to store anything in that guest-allocated memory
5182 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5183 * argument is different from the VMXON pointer (which the spec says they do).
5184 */
5185static int handle_vmon(struct kvm_vcpu *vcpu)
5186{
5187 struct kvm_segment cs;
5188 struct vcpu_vmx *vmx = to_vmx(vcpu);
5189
5190 /* The Intel VMX Instruction Reference lists a bunch of bits that
5191 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5192 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5193 * Otherwise, we should fail with #UD. We test these now:
5194 */
5195 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5196 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5197 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5198 kvm_queue_exception(vcpu, UD_VECTOR);
5199 return 1;
5200 }
5201
5202 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5203 if (is_long_mode(vcpu) && !cs.l) {
5204 kvm_queue_exception(vcpu, UD_VECTOR);
5205 return 1;
5206 }
5207
5208 if (vmx_get_cpl(vcpu)) {
5209 kvm_inject_gp(vcpu, 0);
5210 return 1;
5211 }
5212
ff2f6fe9
NHE		 5213 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5214 vmx->nested.vmcs02_num = 0;
5215
ec378aee
NHE		 5216 vmx->nested.vmxon = true;
5217
5218 skip_emulated_instruction(vcpu);
5219 return 1;
5220}
5221
5222/*
5223 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5224 * for running VMX instructions (except VMXON, whose prerequisites are
5225 * slightly different). It also specifies what exception to inject otherwise.
5226 */
5227static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5228{
5229 struct kvm_segment cs;
5230 struct vcpu_vmx *vmx = to_vmx(vcpu);
5231
5232 if (!vmx->nested.vmxon) {
5233 kvm_queue_exception(vcpu, UD_VECTOR);
5234 return 0;
5235 }
5236
5237 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5238 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5239 (is_long_mode(vcpu) && !cs.l)) {
5240 kvm_queue_exception(vcpu, UD_VECTOR);
5241 return 0;
5242 }
5243
5244 if (vmx_get_cpl(vcpu)) {
5245 kvm_inject_gp(vcpu, 0);
5246 return 0;
5247 }
5248
5249 return 1;
5250}
5251
5252/*
5253 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5254 * just stops using VMX.
5255 */
5256static void free_nested(struct vcpu_vmx *vmx)
5257{
5258 if (!vmx->nested.vmxon)
5259 return;
5260 vmx->nested.vmxon = false;
a9d30f33
NHE		 5261 if (vmx->nested.current_vmptr != -1ull) {
5262 kunmap(vmx->nested.current_vmcs12_page);
5263 nested_release_page(vmx->nested.current_vmcs12_page);
5264 vmx->nested.current_vmptr = -1ull;
5265 vmx->nested.current_vmcs12 = NULL;
5266 }
fe3ef05c
NHE		 5267 /* Unpin physical memory we referred to in current vmcs02 */
5268 if (vmx->nested.apic_access_page) {
5269 nested_release_page(vmx->nested.apic_access_page);
5270 vmx->nested.apic_access_page = 0;
5271 }
ff2f6fe9
NHE		 5272
5273 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5274}
5275
5276/* Emulate the VMXOFF instruction */
5277static int handle_vmoff(struct kvm_vcpu *vcpu)
5278{
5279 if (!nested_vmx_check_permission(vcpu))
5280 return 1;
5281 free_nested(to_vmx(vcpu));
5282 skip_emulated_instruction(vcpu);
5283 return 1;
5284}
5285
064aea77
NHE		 5286/*
5287 * Decode the memory-address operand of a vmx instruction, as recorded on an
5288 * exit caused by such an instruction (run by a guest hypervisor).
5289 * On success, returns 0. When the operand is invalid, returns 1 and throws
5290 * #UD or #GP.
5291 */
5292static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5293 unsigned long exit_qualification,
5294 u32 vmx_instruction_info, gva_t *ret)
5295{
5296 /*
5297 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5298 * Execution", on an exit, vmx_instruction_info holds most of the
5299 * addressing components of the operand. Only the displacement part
5300 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5301 * For how an actual address is calculated from all these components,
5302 * refer to Vol. 1, "Operand Addressing".
5303 */
5304 int scaling = vmx_instruction_info & 3;
5305 int addr_size = (vmx_instruction_info >> 7) & 7;
5306 bool is_reg = vmx_instruction_info & (1u << 10);
5307 int seg_reg = (vmx_instruction_info >> 15) & 7;
5308 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5309 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5310 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5311 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5312
5313 if (is_reg) {
5314 kvm_queue_exception(vcpu, UD_VECTOR);
5315 return 1;
5316 }
5317
5318 /* Addr = segment_base + offset */
5319 /* offset = base + [index * scale] + displacement */
5320 *ret = vmx_get_segment_base(vcpu, seg_reg);
5321 if (base_is_valid)
5322 *ret += kvm_register_read(vcpu, base_reg);
5323 if (index_is_valid)
5324 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5325 *ret += exit_qualification; /* holds the displacement */
5326
5327 if (addr_size == 1) /* 32 bit */
5328 *ret &= 0xffffffff;
5329
5330 /*
5331 * TODO: throw #GP (and return 1) in various cases that the VM*
5332 * instructions require it - e.g., offset beyond segment limit,
5333 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5334 * address, and so on. Currently these are not checked.
5335 */
5336 return 0;
5337}
5338
0140caea
NHE		 5339/*
5340 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5341 * set the success or error code of an emulated VMX instruction, as specified
5342 * by Vol 2B, VMX Instruction Reference, "Conventions".
5343 */
5344static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5345{
5346 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5347 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5348 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5349}
5350
5351static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5352{
5353 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5354 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5355 X86_EFLAGS_SF | X86_EFLAGS_OF))
5356 | X86_EFLAGS_CF);
5357}
5358
5359static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5360 u32 vm_instruction_error)
5361{
5362 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5363 /*
5364 * failValid writes the error number to the current VMCS, which
5365 * can't be done there isn't a current VMCS.
5366 */
5367 nested_vmx_failInvalid(vcpu);
5368 return;
5369 }
5370 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5371 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5372 X86_EFLAGS_SF | X86_EFLAGS_OF))
5373 | X86_EFLAGS_ZF);
5374 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5375}
5376
27d6c865
NHE		 5377/* Emulate the VMCLEAR instruction */
5378static int handle_vmclear(struct kvm_vcpu *vcpu)
5379{
5380 struct vcpu_vmx *vmx = to_vmx(vcpu);
5381 gva_t gva;
5382 gpa_t vmptr;
5383 struct vmcs12 *vmcs12;
5384 struct page *page;
5385 struct x86_exception e;
5386
5387 if (!nested_vmx_check_permission(vcpu))
5388 return 1;
5389
5390 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5391 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5392 return 1;
5393
5394 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5395 sizeof(vmptr), &e)) {
5396 kvm_inject_page_fault(vcpu, &e);
5397 return 1;
5398 }
5399
5400 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5401 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5402 skip_emulated_instruction(vcpu);
5403 return 1;
5404 }
5405
5406 if (vmptr == vmx->nested.current_vmptr) {
5407 kunmap(vmx->nested.current_vmcs12_page);
5408 nested_release_page(vmx->nested.current_vmcs12_page);
5409 vmx->nested.current_vmptr = -1ull;
5410 vmx->nested.current_vmcs12 = NULL;
5411 }
5412
5413 page = nested_get_page(vcpu, vmptr);
5414 if (page == NULL) {
5415 /*
5416 * For accurate processor emulation, VMCLEAR beyond available
5417 * physical memory should do nothing at all. However, it is
5418 * possible that a nested vmx bug, not a guest hypervisor bug,
5419 * resulted in this case, so let's shut down before doing any
5420 * more damage:
5421 */
5422 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5423 return 1;
5424 }
5425 vmcs12 = kmap(page);
5426 vmcs12->launch_state = 0;
5427 kunmap(page);
5428 nested_release_page(page);
5429
5430 nested_free_vmcs02(vmx, vmptr);
5431
5432 skip_emulated_instruction(vcpu);
5433 nested_vmx_succeed(vcpu);
5434 return 1;
5435}
5436
cd232ad0
NHE		 5437static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5438
5439/* Emulate the VMLAUNCH instruction */
5440static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5441{
5442 return nested_vmx_run(vcpu, true);
5443}
5444
5445/* Emulate the VMRESUME instruction */
5446static int handle_vmresume(struct kvm_vcpu *vcpu)
5447{
5448
5449 return nested_vmx_run(vcpu, false);
5450}
5451
49f705c5
NHE		 5452enum vmcs_field_type {
5453 VMCS_FIELD_TYPE_U16 = 0,
5454 VMCS_FIELD_TYPE_U64 = 1,
5455 VMCS_FIELD_TYPE_U32 = 2,
5456 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5457};
5458
5459static inline int vmcs_field_type(unsigned long field)
5460{
5461 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5462 return VMCS_FIELD_TYPE_U32;
5463 return (field >> 13) & 0x3 ;
5464}
5465
5466static inline int vmcs_field_readonly(unsigned long field)
5467{
5468 return (((field >> 10) & 0x3) == 1);
5469}
5470
5471/*
5472 * Read a vmcs12 field. Since these can have varying lengths and we return
5473 * one type, we chose the biggest type (u64) and zero-extend the return value
5474 * to that size. Note that the caller, handle_vmread, might need to use only
5475 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5476 * 64-bit fields are to be returned).
5477 */
5478static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5479 unsigned long field, u64 *ret)
5480{
5481 short offset = vmcs_field_to_offset(field);
5482 char *p;
5483
5484 if (offset < 0)
5485 return 0;
5486
5487 p = ((char *)(get_vmcs12(vcpu))) + offset;
5488
5489 switch (vmcs_field_type(field)) {
5490 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5491 *ret = *((natural_width *)p);
5492 return 1;
5493 case VMCS_FIELD_TYPE_U16:
5494 *ret = *((u16 *)p);
5495 return 1;
5496 case VMCS_FIELD_TYPE_U32:
5497 *ret = *((u32 *)p);
5498 return 1;
5499 case VMCS_FIELD_TYPE_U64:
5500 *ret = *((u64 *)p);
5501 return 1;
5502 default:
5503 return 0; /* can never happen. */
5504 }
5505}
5506
5507/*
5508 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5509 * used before) all generate the same failure when it is missing.
5510 */
5511static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5512{
5513 struct vcpu_vmx *vmx = to_vmx(vcpu);
5514 if (vmx->nested.current_vmptr == -1ull) {
5515 nested_vmx_failInvalid(vcpu);
5516 skip_emulated_instruction(vcpu);
5517 return 0;
5518 }
5519 return 1;
5520}
5521
5522static int handle_vmread(struct kvm_vcpu *vcpu)
5523{
5524 unsigned long field;
5525 u64 field_value;
5526 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5527 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5528 gva_t gva = 0;
5529
5530 if (!nested_vmx_check_permission(vcpu) ||
5531 !nested_vmx_check_vmcs12(vcpu))
5532 return 1;
5533
5534 /* Decode instruction info and find the field to read */
5535 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5536 /* Read the field, zero-extended to a u64 field_value */
5537 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5538 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5539 skip_emulated_instruction(vcpu);
5540 return 1;
5541 }
5542 /*
5543 * Now copy part of this value to register or memory, as requested.
5544 * Note that the number of bits actually copied is 32 or 64 depending
5545 * on the guest's mode (32 or 64 bit), not on the given field's length.
5546 */
5547 if (vmx_instruction_info & (1u << 10)) {
5548 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5549 field_value);
5550 } else {
5551 if (get_vmx_mem_address(vcpu, exit_qualification,
5552 vmx_instruction_info, &gva))
5553 return 1;
5554 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5555 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5556 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5557 }
5558
5559 nested_vmx_succeed(vcpu);
5560 skip_emulated_instruction(vcpu);
5561 return 1;
5562}
5563
5564
5565static int handle_vmwrite(struct kvm_vcpu *vcpu)
5566{
5567 unsigned long field;
5568 gva_t gva;
5569 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5570 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5571 char *p;
5572 short offset;
5573 /* The value to write might be 32 or 64 bits, depending on L1's long
5574 * mode, and eventually we need to write that into a field of several
5575 * possible lengths. The code below first zero-extends the value to 64
5576 * bit (field_value), and then copies only the approriate number of
5577 * bits into the vmcs12 field.
5578 */
5579 u64 field_value = 0;
5580 struct x86_exception e;
5581
5582 if (!nested_vmx_check_permission(vcpu) ||
5583 !nested_vmx_check_vmcs12(vcpu))
5584 return 1;
5585
5586 if (vmx_instruction_info & (1u << 10))
5587 field_value = kvm_register_read(vcpu,
5588 (((vmx_instruction_info) >> 3) & 0xf));
5589 else {
5590 if (get_vmx_mem_address(vcpu, exit_qualification,
5591 vmx_instruction_info, &gva))
5592 return 1;
5593 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5594 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5595 kvm_inject_page_fault(vcpu, &e);
5596 return 1;
5597 }
5598 }
5599
5600
5601 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5602 if (vmcs_field_readonly(field)) {
5603 nested_vmx_failValid(vcpu,
5604 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5605 skip_emulated_instruction(vcpu);
5606 return 1;
5607 }
5608
5609 offset = vmcs_field_to_offset(field);
5610 if (offset < 0) {
5611 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5612 skip_emulated_instruction(vcpu);
5613 return 1;
5614 }
5615 p = ((char *) get_vmcs12(vcpu)) + offset;
5616
5617 switch (vmcs_field_type(field)) {
5618 case VMCS_FIELD_TYPE_U16:
5619 *(u16 *)p = field_value;
5620 break;
5621 case VMCS_FIELD_TYPE_U32:
5622 *(u32 *)p = field_value;
5623 break;
5624 case VMCS_FIELD_TYPE_U64:
5625 *(u64 *)p = field_value;
5626 break;
5627 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5628 *(natural_width *)p = field_value;
5629 break;
5630 default:
5631 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5632 skip_emulated_instruction(vcpu);
5633 return 1;
5634 }
5635
5636 nested_vmx_succeed(vcpu);
5637 skip_emulated_instruction(vcpu);
5638 return 1;
5639}
5640
63846663
NHE		 5641/* Emulate the VMPTRLD instruction */
5642static int handle_vmptrld(struct kvm_vcpu *vcpu)
5643{
5644 struct vcpu_vmx *vmx = to_vmx(vcpu);
5645 gva_t gva;
5646 gpa_t vmptr;
5647 struct x86_exception e;
5648
5649 if (!nested_vmx_check_permission(vcpu))
5650 return 1;
5651
5652 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5653 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5654 return 1;
5655
5656 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5657 sizeof(vmptr), &e)) {
5658 kvm_inject_page_fault(vcpu, &e);
5659 return 1;
5660 }
5661
5662 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5663 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5664 skip_emulated_instruction(vcpu);
5665 return 1;
5666 }
5667
5668 if (vmx->nested.current_vmptr != vmptr) {
5669 struct vmcs12 *new_vmcs12;
5670 struct page *page;
5671 page = nested_get_page(vcpu, vmptr);
5672 if (page == NULL) {
5673 nested_vmx_failInvalid(vcpu);
5674 skip_emulated_instruction(vcpu);
5675 return 1;
5676 }
5677 new_vmcs12 = kmap(page);
5678 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5679 kunmap(page);
5680 nested_release_page_clean(page);
5681 nested_vmx_failValid(vcpu,
5682 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5683 skip_emulated_instruction(vcpu);
5684 return 1;
5685 }
5686 if (vmx->nested.current_vmptr != -1ull) {
5687 kunmap(vmx->nested.current_vmcs12_page);
5688 nested_release_page(vmx->nested.current_vmcs12_page);
5689 }
5690
5691 vmx->nested.current_vmptr = vmptr;
5692 vmx->nested.current_vmcs12 = new_vmcs12;
5693 vmx->nested.current_vmcs12_page = page;
5694 }
5695
5696 nested_vmx_succeed(vcpu);
5697 skip_emulated_instruction(vcpu);
5698 return 1;
5699}
5700
6a4d7550
NHE		 5701/* Emulate the VMPTRST instruction */
5702static int handle_vmptrst(struct kvm_vcpu *vcpu)
5703{
5704 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5705 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5706 gva_t vmcs_gva;
5707 struct x86_exception e;
5708
5709 if (!nested_vmx_check_permission(vcpu))
5710 return 1;
5711
5712 if (get_vmx_mem_address(vcpu, exit_qualification,
5713 vmx_instruction_info, &vmcs_gva))
5714 return 1;
5715 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5716 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5717 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5718 sizeof(u64), &e)) {
5719 kvm_inject_page_fault(vcpu, &e);
5720 return 1;
5721 }
5722 nested_vmx_succeed(vcpu);
5723 skip_emulated_instruction(vcpu);
5724 return 1;
5725}
5726
6aa8b732
AK		 5727/*
5728 * The exit handlers return 1 if the exit was handled fully and guest execution
5729 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5730 * to be done to userspace and return 0.
5731 */
772e0318 5732static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5733 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5734 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5735 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5736 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5737 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5738 [EXIT_REASON_CR_ACCESS] = handle_cr,
5739 [EXIT_REASON_DR_ACCESS] = handle_dr,
5740 [EXIT_REASON_CPUID] = handle_cpuid,
5741 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5742 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5743 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5744 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5745 [EXIT_REASON_INVD] = handle_invd,
a7052897 5746 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5747 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5748 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5749 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5750 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5751 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5752 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5753 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5754 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5755 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5756 [EXIT_REASON_VMOFF] = handle_vmoff,
5757 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5758 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5759 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5760 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5761 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5762 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5763 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5764 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5765 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5766 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5767 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5768 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5769};
5770
5771static const int kvm_vmx_max_exit_handlers =
50a3485c 5772 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5773
644d711a
NHE		 5774/*
5775 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5776 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5777 * disinterest in the current event (read or write a specific MSR) by using an
5778 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5779 */
5780static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5781 struct vmcs12 *vmcs12, u32 exit_reason)
5782{
5783 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5784 gpa_t bitmap;
5785
5786 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5787 return 1;
5788
5789 /*
5790 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5791 * for the four combinations of read/write and low/high MSR numbers.
5792 * First we need to figure out which of the four to use:
5793 */
5794 bitmap = vmcs12->msr_bitmap;
5795 if (exit_reason == EXIT_REASON_MSR_WRITE)
5796 bitmap += 2048;
5797 if (msr_index >= 0xc0000000) {
5798 msr_index -= 0xc0000000;
5799 bitmap += 1024;
5800 }
5801
5802 /* Then read the msr_index'th bit from this bitmap: */
5803 if (msr_index < 1024*8) {
5804 unsigned char b;
5805 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5806 return 1 & (b >> (msr_index & 7));
5807 } else
5808 return 1; /* let L1 handle the wrong parameter */
5809}
5810
5811/*
5812 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5813 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5814 * intercept (via guest_host_mask etc.) the current event.
5815 */
5816static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5817 struct vmcs12 *vmcs12)
5818{
5819 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5820 int cr = exit_qualification & 15;
5821 int reg = (exit_qualification >> 8) & 15;
5822 unsigned long val = kvm_register_read(vcpu, reg);
5823
5824 switch ((exit_qualification >> 4) & 3) {
5825 case 0: /* mov to cr */
5826 switch (cr) {
5827 case 0:
5828 if (vmcs12->cr0_guest_host_mask &
5829 (val ^ vmcs12->cr0_read_shadow))
5830 return 1;
5831 break;
5832 case 3:
5833 if ((vmcs12->cr3_target_count >= 1 &&
5834 vmcs12->cr3_target_value0 == val) ||
5835 (vmcs12->cr3_target_count >= 2 &&
5836 vmcs12->cr3_target_value1 == val) ||
5837 (vmcs12->cr3_target_count >= 3 &&
5838 vmcs12->cr3_target_value2 == val) ||
5839 (vmcs12->cr3_target_count >= 4 &&
5840 vmcs12->cr3_target_value3 == val))
5841 return 0;
5842 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5843 return 1;
5844 break;
5845 case 4:
5846 if (vmcs12->cr4_guest_host_mask &
5847 (vmcs12->cr4_read_shadow ^ val))
5848 return 1;
5849 break;
5850 case 8:
5851 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5852 return 1;
5853 break;
5854 }
5855 break;
5856 case 2: /* clts */
5857 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5858 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5859 return 1;
5860 break;
5861 case 1: /* mov from cr */
5862 switch (cr) {
5863 case 3:
5864 if (vmcs12->cpu_based_vm_exec_control &
5865 CPU_BASED_CR3_STORE_EXITING)
5866 return 1;
5867 break;
5868 case 8:
5869 if (vmcs12->cpu_based_vm_exec_control &
5870 CPU_BASED_CR8_STORE_EXITING)
5871 return 1;
5872 break;
5873 }
5874 break;
5875 case 3: /* lmsw */
5876 /*
5877 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5878 * cr0. Other attempted changes are ignored, with no exit.
5879 */
5880 if (vmcs12->cr0_guest_host_mask & 0xe &
5881 (val ^ vmcs12->cr0_read_shadow))
5882 return 1;
5883 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5884 !(vmcs12->cr0_read_shadow & 0x1) &&
5885 (val & 0x1))
5886 return 1;
5887 break;
5888 }
5889 return 0;
5890}
5891
5892/*
5893 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5894 * should handle it ourselves in L0 (and then continue L2). Only call this
5895 * when in is_guest_mode (L2).
5896 */
5897static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5898{
5899 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5900 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5901 struct vcpu_vmx *vmx = to_vmx(vcpu);
5902 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5903
5904 if (vmx->nested.nested_run_pending)
5905 return 0;
5906
5907 if (unlikely(vmx->fail)) {
bd80158a
JK		 5908 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5909 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5910 return 1;
5911 }
5912
5913 switch (exit_reason) {
5914 case EXIT_REASON_EXCEPTION_NMI:
5915 if (!is_exception(intr_info))
5916 return 0;
5917 else if (is_page_fault(intr_info))
5918 return enable_ept;
5919 return vmcs12->exception_bitmap &
5920 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5921 case EXIT_REASON_EXTERNAL_INTERRUPT:
5922 return 0;
5923 case EXIT_REASON_TRIPLE_FAULT:
5924 return 1;
5925 case EXIT_REASON_PENDING_INTERRUPT:
5926 case EXIT_REASON_NMI_WINDOW:
5927 /*
5928 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5929 * (aka Interrupt Window Exiting) only when L1 turned it on,
5930 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5931 * Same for NMI Window Exiting.
5932 */
5933 return 1;
5934 case EXIT_REASON_TASK_SWITCH:
5935 return 1;
5936 case EXIT_REASON_CPUID:
5937 return 1;
5938 case EXIT_REASON_HLT:
5939 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5940 case EXIT_REASON_INVD:
5941 return 1;
5942 case EXIT_REASON_INVLPG:
5943 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5944 case EXIT_REASON_RDPMC:
5945 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5946 case EXIT_REASON_RDTSC:
5947 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5948 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5949 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5950 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5951 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5952 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5953 /*
5954 * VMX instructions trap unconditionally. This allows L1 to
5955 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5956 */
5957 return 1;
5958 case EXIT_REASON_CR_ACCESS:
5959 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5960 case EXIT_REASON_DR_ACCESS:
5961 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5962 case EXIT_REASON_IO_INSTRUCTION:
5963 /* TODO: support IO bitmaps */
5964 return 1;
5965 case EXIT_REASON_MSR_READ:
5966 case EXIT_REASON_MSR_WRITE:
5967 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5968 case EXIT_REASON_INVALID_STATE:
5969 return 1;
5970 case EXIT_REASON_MWAIT_INSTRUCTION:
5971 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5972 case EXIT_REASON_MONITOR_INSTRUCTION:
5973 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5974 case EXIT_REASON_PAUSE_INSTRUCTION:
5975 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5976 nested_cpu_has2(vmcs12,
5977 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5978 case EXIT_REASON_MCE_DURING_VMENTRY:
5979 return 0;
5980 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5981 return 1;
5982 case EXIT_REASON_APIC_ACCESS:
5983 return nested_cpu_has2(vmcs12,
5984 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5985 case EXIT_REASON_EPT_VIOLATION:
5986 case EXIT_REASON_EPT_MISCONFIG:
5987 return 0;
5988 case EXIT_REASON_WBINVD:
5989 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5990 case EXIT_REASON_XSETBV:
5991 return 1;
5992 default:
5993 return 1;
5994 }
5995}
5996
586f9607
AK		 5997static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5998{
5999 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6000 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6001}
6002
6aa8b732
AK		 6003/*
6004 * The guest has exited. See if we can fix it or if we need userspace
6005 * assistance.
6006 */
851ba692 6007static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6008{
29bd8a78 6009 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6010 u32 exit_reason = vmx->exit_reason;
1155f76a 6011 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6012
80ced186
MG		 6013 /* If guest state is invalid, start emulating */
6014 if (vmx->emulation_required && emulate_invalid_guest_state)
6015 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6016
b6f1250e
NHE		 6017 /*
6018 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6019 * we did not inject a still-pending event to L1 now because of
6020 * nested_run_pending, we need to re-enable this bit.
6021 */
6022 if (vmx->nested.nested_run_pending)
6023 kvm_make_request(KVM_REQ_EVENT, vcpu);
6024
509c75ea
NHE		 6025 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6026 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6027 vmx->nested.nested_run_pending = 1;
6028 else
6029 vmx->nested.nested_run_pending = 0;
6030
6031 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6032 nested_vmx_vmexit(vcpu);
6033 return 1;
6034 }
6035
5120702e
MG		 6036 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6037 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6038 vcpu->run->fail_entry.hardware_entry_failure_reason
6039 = exit_reason;
6040 return 0;
6041 }
6042
29bd8a78 6043 if (unlikely(vmx->fail)) {
851ba692
AK		 6044 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6045 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6046 = vmcs_read32(VM_INSTRUCTION_ERROR);
6047 return 0;
6048 }
6aa8b732 6049
b9bf6882
XG		 6050 /*
6051 * Note:
6052 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6053 * delivery event since it indicates guest is accessing MMIO.
6054 * The vm-exit can be triggered again after return to guest that
6055 * will cause infinite loop.
6056 */
d77c26fc 6057 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6058 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6059 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6060 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6061 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6062 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6063 vcpu->run->internal.ndata = 2;
6064 vcpu->run->internal.data[0] = vectoring_info;
6065 vcpu->run->internal.data[1] = exit_reason;
6066 return 0;
6067 }
3b86cd99 6068
644d711a
NHE		 6069 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6070 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6071 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6072 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6073 vmx->soft_vnmi_blocked = 0;
3b86cd99 6074 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6075 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6076 /*
6077 * This CPU don't support us in finding the end of an
6078 * NMI-blocked window if the guest runs with IRQs
6079 * disabled. So we pull the trigger after 1 s of
6080 * futile waiting, but inform the user about this.
6081 */
6082 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6083 "state on VCPU %d after 1 s timeout\n",
6084 __func__, vcpu->vcpu_id);
6085 vmx->soft_vnmi_blocked = 0;
3b86cd99 6086 }
3b86cd99
JK		 6087 }
6088
6aa8b732
AK		 6089 if (exit_reason < kvm_vmx_max_exit_handlers
6090 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6091 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6092 else {
851ba692
AK		 6093 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6094 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6095 }
6096 return 0;
6097}
6098
95ba8273 6099static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6100{
95ba8273 6101 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6102 vmcs_write32(TPR_THRESHOLD, 0);
6103 return;
6104 }
6105
95ba8273 6106 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6107}
6108
51aa01d1 6109static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6110{
00eba012
AK		 6111 u32 exit_intr_info;
6112
6113 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6114 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6115 return;
6116
c5ca8e57 6117 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6118 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6119
6120 /* Handle machine checks before interrupts are enabled */
00eba012 6121 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6122 kvm_machine_check();
6123
20f65983 6124 /* We need to handle NMIs before interrupts are enabled */
00eba012 6125 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6126 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6127 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6128 asm("int $2");
ff9d07a0
ZY		 6129 kvm_after_handle_nmi(&vmx->vcpu);
6130 }
51aa01d1 6131}
20f65983 6132
51aa01d1
AK		 6133static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6134{
c5ca8e57 6135 u32 exit_intr_info;
51aa01d1
AK		 6136 bool unblock_nmi;
6137 u8 vector;
6138 bool idtv_info_valid;
6139
6140 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6141
cf393f75 6142 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6143 if (vmx->nmi_known_unmasked)
6144 return;
c5ca8e57
AK		 6145 /*
6146 * Can't use vmx->exit_intr_info since we're not sure what
6147 * the exit reason is.
6148 */
6149 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6150 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6151 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6152 /*
7b4a25cb 6153 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6154 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6155 * a guest IRET fault.
7b4a25cb
GN		 6156 * SDM 3: 23.2.2 (September 2008)
6157 * Bit 12 is undefined in any of the following cases:
6158 * If the VM exit sets the valid bit in the IDT-vectoring
6159 * information field.
6160 * If the VM exit is due to a double fault.
cf393f75 6161 */
7b4a25cb
GN		 6162 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6163 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6164 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6165 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6166 else
6167 vmx->nmi_known_unmasked =
6168 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6169 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6170 } else if (unlikely(vmx->soft_vnmi_blocked))
6171 vmx->vnmi_blocked_time +=
6172 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6173}
6174
83422e17
AK		 6175static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6176 u32 idt_vectoring_info,
6177 int instr_len_field,
6178 int error_code_field)
51aa01d1 6179{
51aa01d1
AK		 6180 u8 vector;
6181 int type;
6182 bool idtv_info_valid;
6183
6184 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6185
37b96e98
GN		 6186 vmx->vcpu.arch.nmi_injected = false;
6187 kvm_clear_exception_queue(&vmx->vcpu);
6188 kvm_clear_interrupt_queue(&vmx->vcpu);
6189
6190 if (!idtv_info_valid)
6191 return;
6192
3842d135
AK		 6193 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6194
668f612f
AK		 6195 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6196 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6197
64a7ec06 6198 switch (type) {
37b96e98
GN		 6199 case INTR_TYPE_NMI_INTR:
6200 vmx->vcpu.arch.nmi_injected = true;
668f612f 6201 /*
7b4a25cb 6202 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6203 * Clear bit "block by NMI" before VM entry if a NMI
6204 * delivery faulted.
668f612f 6205 */
654f06fc 6206 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6207 break;
37b96e98 6208 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6209 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6210 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6211 /* fall through */
6212 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6213 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6214 u32 err = vmcs_read32(error_code_field);
37b96e98 6215 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6216 } else
6217 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6218 break;
66fd3f7f
GN		 6219 case INTR_TYPE_SOFT_INTR:
6220 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6221 vmcs_read32(instr_len_field);
66fd3f7f 6222 /* fall through */
37b96e98 6223 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6224 kvm_queue_interrupt(&vmx->vcpu, vector,
6225 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6226 break;
6227 default:
6228 break;
f7d9238f 6229 }
cf393f75
AK		 6230}
6231
83422e17
AK		 6232static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6233{
66c78ae4
NHE		 6234 if (is_guest_mode(&vmx->vcpu))
6235 return;
83422e17
AK		 6236 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6237 VM_EXIT_INSTRUCTION_LEN,
6238 IDT_VECTORING_ERROR_CODE);
6239}
6240
b463a6f7
AK		 6241static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6242{
66c78ae4
NHE		 6243 if (is_guest_mode(vcpu))
6244 return;
b463a6f7
AK		 6245 __vmx_complete_interrupts(to_vmx(vcpu),
6246 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6247 VM_ENTRY_INSTRUCTION_LEN,
6248 VM_ENTRY_EXCEPTION_ERROR_CODE);
6249
6250 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6251}
6252
d7cd9796
GN		 6253static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6254{
6255 int i, nr_msrs;
6256 struct perf_guest_switch_msr *msrs;
6257
6258 msrs = perf_guest_get_msrs(&nr_msrs);
6259
6260 if (!msrs)
6261 return;
6262
6263 for (i = 0; i < nr_msrs; i++)
6264 if (msrs[i].host == msrs[i].guest)
6265 clear_atomic_switch_msr(vmx, msrs[i].msr);
6266 else
6267 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6268 msrs[i].host);
6269}
6270
a3b5ba49 6271static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6272{
a2fa3e9f 6273 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6274 unsigned long debugctlmsr;
104f226b 6275
66c78ae4
NHE		 6276 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6277 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6278 if (vmcs12->idt_vectoring_info_field &
6279 VECTORING_INFO_VALID_MASK) {
6280 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6281 vmcs12->idt_vectoring_info_field);
6282 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6283 vmcs12->vm_exit_instruction_len);
6284 if (vmcs12->idt_vectoring_info_field &
6285 VECTORING_INFO_DELIVER_CODE_MASK)
6286 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6287 vmcs12->idt_vectoring_error_code);
6288 }
6289 }
6290
104f226b
AK		 6291 /* Record the guest's net vcpu time for enforced NMI injections. */
6292 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6293 vmx->entry_time = ktime_get();
6294
6295 /* Don't enter VMX if guest state is invalid, let the exit handler
6296 start emulation until we arrive back to a valid state */
6297 if (vmx->emulation_required && emulate_invalid_guest_state)
6298 return;
6299
6300 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6301 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6302 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6303 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6304
6305 /* When single-stepping over STI and MOV SS, we must clear the
6306 * corresponding interruptibility bits in the guest state. Otherwise
6307 * vmentry fails as it then expects bit 14 (BS) in pending debug
6308 * exceptions being set, but that's not correct for the guest debugging
6309 * case. */
6310 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6311 vmx_set_interrupt_shadow(vcpu, 0);
6312
d7cd9796 6313 atomic_switch_perf_msrs(vmx);
2a7921b7 6314 debugctlmsr = get_debugctlmsr();
d7cd9796 6315
d462b819 6316 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6317 asm(
6aa8b732 6318 /* Store host registers */
b188c81f
AK		 6319 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6320 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6321 "push %%" _ASM_CX " \n\t"
6322 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6323 "je 1f \n\t"
b188c81f 6324 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6325 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6326 "1: \n\t"
d3edefc0 6327 /* Reload cr2 if changed */
b188c81f
AK		 6328 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6329 "mov %%cr2, %%" _ASM_DX " \n\t"
6330 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6331 "je 2f \n\t"
b188c81f 6332 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6333 "2: \n\t"
6aa8b732 6334 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6335 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6336 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6337 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6338 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6339 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6340 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6341 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6342 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6343#ifdef CONFIG_X86_64
e08aa78a
AK		 6344 "mov %c[r8](%0), %%r8 \n\t"
6345 "mov %c[r9](%0), %%r9 \n\t"
6346 "mov %c[r10](%0), %%r10 \n\t"
6347 "mov %c[r11](%0), %%r11 \n\t"
6348 "mov %c[r12](%0), %%r12 \n\t"
6349 "mov %c[r13](%0), %%r13 \n\t"
6350 "mov %c[r14](%0), %%r14 \n\t"
6351 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6352#endif
b188c81f 6353 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6354
6aa8b732 6355 /* Enter guest mode */
83287ea4 6356 "jne 1f \n\t"
4ecac3fd 6357 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6358 "jmp 2f \n\t"
6359 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6360 "2: "
6aa8b732 6361 /* Save guest registers, load host registers, keep flags */
b188c81f 6362 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6363 "pop %0 \n\t"
b188c81f
AK		 6364 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6365 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6366 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6367 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6368 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6369 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6370 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6371#ifdef CONFIG_X86_64
e08aa78a
AK		 6372 "mov %%r8, %c[r8](%0) \n\t"
6373 "mov %%r9, %c[r9](%0) \n\t"
6374 "mov %%r10, %c[r10](%0) \n\t"
6375 "mov %%r11, %c[r11](%0) \n\t"
6376 "mov %%r12, %c[r12](%0) \n\t"
6377 "mov %%r13, %c[r13](%0) \n\t"
6378 "mov %%r14, %c[r14](%0) \n\t"
6379 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6380#endif
b188c81f
AK		 6381 "mov %%cr2, %%" _ASM_AX " \n\t"
6382 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6383
b188c81f 6384 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6385 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6386 ".pushsection .rodata \n\t"
6387 ".global vmx_return \n\t"
6388 "vmx_return: " _ASM_PTR " 2b \n\t"
6389 ".popsection"
e08aa78a 6390 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6391 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6392 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6393 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6394 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6395 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6396 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6397 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6398 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6399 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6400 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6401#ifdef CONFIG_X86_64
ad312c7c
ZX		 6402 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6403 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6404 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6405 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6406 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6407 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6408 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6409 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6410#endif
40712fae
AK		 6411 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6412 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6413 : "cc", "memory"
6414#ifdef CONFIG_X86_64
b188c81f 6415 , "rax", "rbx", "rdi", "rsi"
c2036300 6416 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6417#else
6418 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6419#endif
6420 );
6aa8b732 6421
2a7921b7
GN		 6422 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6423 if (debugctlmsr)
6424 update_debugctlmsr(debugctlmsr);
6425
aa67f609
AK		 6426#ifndef CONFIG_X86_64
6427 /*
6428 * The sysexit path does not restore ds/es, so we must set them to
6429 * a reasonable value ourselves.
6430 *
6431 * We can't defer this to vmx_load_host_state() since that function
6432 * may be executed in interrupt context, which saves and restore segments
6433 * around it, nullifying its effect.
6434 */
6435 loadsegment(ds, __USER_DS);
6436 loadsegment(es, __USER_DS);
6437#endif
6438
6de4f3ad 6439 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6440 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6441 | (1 << VCPU_EXREG_CPL)
aff48baa 6442 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6443 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6444 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6445 vcpu->arch.regs_dirty = 0;
6446
1155f76a
AK		 6447 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6448
66c78ae4
NHE		 6449 if (is_guest_mode(vcpu)) {
6450 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6451 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6452 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6453 vmcs12->idt_vectoring_error_code =
6454 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6455 vmcs12->vm_exit_instruction_len =
6456 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6457 }
6458 }
6459
d462b819 6460 vmx->loaded_vmcs->launched = 1;
1b6269db 6461
51aa01d1 6462 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6463 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6464
6465 vmx_complete_atomic_exit(vmx);
6466 vmx_recover_nmi_blocking(vmx);
cf393f75 6467 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6468}
6469
6aa8b732
AK		 6470static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6471{
fb3f0f51
RR		 6472 struct vcpu_vmx *vmx = to_vmx(vcpu);
6473
cdbecfc3 6474 free_vpid(vmx);
ec378aee 6475 free_nested(vmx);
d462b819 6476 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6477 kfree(vmx->guest_msrs);
6478 kvm_vcpu_uninit(vcpu);
a4770347 6479 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6480}
6481
fb3f0f51 6482static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6483{
fb3f0f51 6484 int err;
c16f862d 6485 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6486 int cpu;
6aa8b732 6487
a2fa3e9f 6488 if (!vmx)
fb3f0f51
RR		 6489 return ERR_PTR(-ENOMEM);
6490
2384d2b3
SY		 6491 allocate_vpid(vmx);
6492
fb3f0f51
RR		 6493 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6494 if (err)
6495 goto free_vcpu;
965b58a5 6496
a2fa3e9f 6497 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6498 err = -ENOMEM;
fb3f0f51 6499 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6500 goto uninit_vcpu;
6501 }
965b58a5 6502
d462b819
NHE		 6503 vmx->loaded_vmcs = &vmx->vmcs01;
6504 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6505 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6506 goto free_msrs;
d462b819
NHE		 6507 if (!vmm_exclusive)
6508 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6509 loaded_vmcs_init(vmx->loaded_vmcs);
6510 if (!vmm_exclusive)
6511 kvm_cpu_vmxoff();
a2fa3e9f 6512
15ad7146
AK		 6513 cpu = get_cpu();
6514 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6515 vmx->vcpu.cpu = cpu;
8b9cf98c 6516 err = vmx_vcpu_setup(vmx);
fb3f0f51 6517 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6518 put_cpu();
fb3f0f51
RR		 6519 if (err)
6520 goto free_vmcs;
5e4a0b3c 6521 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6522 err = alloc_apic_access_page(kvm);
6523 if (err)
5e4a0b3c 6524 goto free_vmcs;
fb3f0f51 6525
b927a3ce
SY		 6526 if (enable_ept) {
6527 if (!kvm->arch.ept_identity_map_addr)
6528 kvm->arch.ept_identity_map_addr =
6529 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6530 err = -ENOMEM;
b7ebfb05
SY		 6531 if (alloc_identity_pagetable(kvm) != 0)
6532 goto free_vmcs;
93ea5388
GN		 6533 if (!init_rmode_identity_map(kvm))
6534 goto free_vmcs;
b927a3ce 6535 }
b7ebfb05 6536
a9d30f33
NHE		 6537 vmx->nested.current_vmptr = -1ull;
6538 vmx->nested.current_vmcs12 = NULL;
6539
fb3f0f51
RR		 6540 return &vmx->vcpu;
6541
6542free_vmcs:
5f3fbc34 6543 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6544free_msrs:
fb3f0f51
RR		 6545 kfree(vmx->guest_msrs);
6546uninit_vcpu:
6547 kvm_vcpu_uninit(&vmx->vcpu);
6548free_vcpu:
cdbecfc3 6549 free_vpid(vmx);
a4770347 6550 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6551 return ERR_PTR(err);
6aa8b732
AK		 6552}
6553
002c7f7c
YS		 6554static void __init vmx_check_processor_compat(void *rtn)
6555{
6556 struct vmcs_config vmcs_conf;
6557
6558 *(int *)rtn = 0;
6559 if (setup_vmcs_config(&vmcs_conf) < 0)
6560 *(int *)rtn = -EIO;
6561 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6562 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6563 smp_processor_id());
6564 *(int *)rtn = -EIO;
6565 }
6566}
6567
67253af5
SY		 6568static int get_ept_level(void)
6569{
6570 return VMX_EPT_DEFAULT_GAW + 1;
6571}
6572
4b12f0de 6573static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6574{
4b12f0de
SY		 6575 u64 ret;
6576
522c68c4
SY		 6577 /* For VT-d and EPT combination
6578 * 1. MMIO: always map as UC
6579 * 2. EPT with VT-d:
6580 * a. VT-d without snooping control feature: can't guarantee the
6581 * result, try to trust guest.
6582 * b. VT-d with snooping control feature: snooping control feature of
6583 * VT-d engine can guarantee the cache correctness. Just set it
6584 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6585 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6586 * consistent with host MTRR
6587 */
4b12f0de
SY		 6588 if (is_mmio)
6589 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6590 else if (vcpu->kvm->arch.iommu_domain &&
6591 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6592 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6593 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6594 else
522c68c4 6595 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6596 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6597
6598 return ret;
64d4d521
SY		 6599}
6600
17cc3935 6601static int vmx_get_lpage_level(void)
344f414f 6602{
878403b7
SY		 6603 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6604 return PT_DIRECTORY_LEVEL;
6605 else
6606 /* For shadow and EPT supported 1GB page */
6607 return PT_PDPE_LEVEL;
344f414f
JR		 6608}
6609
0e851880
SY		 6610static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6611{
4e47c7a6
SY		 6612 struct kvm_cpuid_entry2 *best;
6613 struct vcpu_vmx *vmx = to_vmx(vcpu);
6614 u32 exec_control;
6615
6616 vmx->rdtscp_enabled = false;
6617 if (vmx_rdtscp_supported()) {
6618 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6619 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6620 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6621 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6622 vmx->rdtscp_enabled = true;
6623 else {
6624 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6625 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6626 exec_control);
6627 }
6628 }
6629 }
ad756a16 6630
ad756a16
MJ		 6631 /* Exposing INVPCID only when PCID is exposed */
6632 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6633 if (vmx_invpcid_supported() &&
4f977045 6634 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6635 guest_cpuid_has_pcid(vcpu)) {
29282fde 6636 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 6637 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6638 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6639 exec_control);
6640 } else {
29282fde
TI		 6641 if (cpu_has_secondary_exec_ctrls()) {
6642 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6643 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6644 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6645 exec_control);
6646 }
ad756a16 6647 if (best)
4f977045 6648 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6649 }
0e851880
SY		 6650}
6651
d4330ef2
JR		 6652static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6653{
7b8050f5
NHE		 6654 if (func == 1 && nested)
6655 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6656}
6657
fe3ef05c
NHE		 6658/*
6659 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6660 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6661 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6662 * guest in a way that will both be appropriate to L1's requests, and our
6663 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6664 * function also has additional necessary side-effects, like setting various
6665 * vcpu->arch fields.
6666 */
6667static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6668{
6669 struct vcpu_vmx *vmx = to_vmx(vcpu);
6670 u32 exec_control;
6671
6672 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6673 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6674 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6675 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6676 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6677 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6678 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6679 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6680 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6681 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6682 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6683 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6684 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6685 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6686 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6687 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6688 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6689 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6690 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6691 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6692 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6693 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6694 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6695 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6696 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6697 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6698 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6699 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6700 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6701 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6702 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6703 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6704 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6705 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6706 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6707 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6708
6709 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6710 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6711 vmcs12->vm_entry_intr_info_field);
6712 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6713 vmcs12->vm_entry_exception_error_code);
6714 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6715 vmcs12->vm_entry_instruction_len);
6716 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6717 vmcs12->guest_interruptibility_info);
6718 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6719 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6720 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6721 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6722 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6723 vmcs12->guest_pending_dbg_exceptions);
6724 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6725 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6726
6727 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6728
6729 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6730 (vmcs_config.pin_based_exec_ctrl |
6731 vmcs12->pin_based_vm_exec_control));
6732
6733 /*
6734 * Whether page-faults are trapped is determined by a combination of
6735 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6736 * If enable_ept, L0 doesn't care about page faults and we should
6737 * set all of these to L1's desires. However, if !enable_ept, L0 does
6738 * care about (at least some) page faults, and because it is not easy
6739 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6740 * to exit on each and every L2 page fault. This is done by setting
6741 * MASK=MATCH=0 and (see below) EB.PF=1.
6742 * Note that below we don't need special code to set EB.PF beyond the
6743 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6744 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6745 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6746 *
6747 * A problem with this approach (when !enable_ept) is that L1 may be
6748 * injected with more page faults than it asked for. This could have
6749 * caused problems, but in practice existing hypervisors don't care.
6750 * To fix this, we will need to emulate the PFEC checking (on the L1
6751 * page tables), using walk_addr(), when injecting PFs to L1.
6752 */
6753 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6754 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6755 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6756 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6757
6758 if (cpu_has_secondary_exec_ctrls()) {
6759 u32 exec_control = vmx_secondary_exec_control(vmx);
6760 if (!vmx->rdtscp_enabled)
6761 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6762 /* Take the following fields only from vmcs12 */
6763 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6764 if (nested_cpu_has(vmcs12,
6765 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6766 exec_control |= vmcs12->secondary_vm_exec_control;
6767
6768 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6769 /*
6770 * Translate L1 physical address to host physical
6771 * address for vmcs02. Keep the page pinned, so this
6772 * physical address remains valid. We keep a reference
6773 * to it so we can release it later.
6774 */
6775 if (vmx->nested.apic_access_page) /* shouldn't happen */
6776 nested_release_page(vmx->nested.apic_access_page);
6777 vmx->nested.apic_access_page =
6778 nested_get_page(vcpu, vmcs12->apic_access_addr);
6779 /*
6780 * If translation failed, no matter: This feature asks
6781 * to exit when accessing the given address, and if it
6782 * can never be accessed, this feature won't do
6783 * anything anyway.
6784 */
6785 if (!vmx->nested.apic_access_page)
6786 exec_control &=
6787 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6788 else
6789 vmcs_write64(APIC_ACCESS_ADDR,
6790 page_to_phys(vmx->nested.apic_access_page));
6791 }
6792
6793 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6794 }
6795
6796
6797 /*
6798 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6799 * Some constant fields are set here by vmx_set_constant_host_state().
6800 * Other fields are different per CPU, and will be set later when
6801 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6802 */
6803 vmx_set_constant_host_state();
6804
6805 /*
6806 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6807 * entry, but only if the current (host) sp changed from the value
6808 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6809 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6810 * here we just force the write to happen on entry.
6811 */
6812 vmx->host_rsp = 0;
6813
6814 exec_control = vmx_exec_control(vmx); /* L0's desires */
6815 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6816 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6817 exec_control &= ~CPU_BASED_TPR_SHADOW;
6818 exec_control |= vmcs12->cpu_based_vm_exec_control;
6819 /*
6820 * Merging of IO and MSR bitmaps not currently supported.
6821 * Rather, exit every time.
6822 */
6823 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6824 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6825 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6826
6827 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6828
6829 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6830 * bitwise-or of what L1 wants to trap for L2, and what we want to
6831 * trap. Note that CR0.TS also needs updating - we do this later.
6832 */
6833 update_exception_bitmap(vcpu);
6834 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6835 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6836
6837 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6838 vmcs_write32(VM_EXIT_CONTROLS,
6839 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6840 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6841 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6842
6843 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6844 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6845 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6846 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6847
6848
6849 set_cr4_guest_host_mask(vmx);
6850
27fc51b2
NHE		 6851 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6852 vmcs_write64(TSC_OFFSET,
6853 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6854 else
6855 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6856
6857 if (enable_vpid) {
6858 /*
6859 * Trivially support vpid by letting L2s share their parent
6860 * L1's vpid. TODO: move to a more elaborate solution, giving
6861 * each L2 its own vpid and exposing the vpid feature to L1.
6862 */
6863 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6864 vmx_flush_tlb(vcpu);
6865 }
6866
6867 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6868 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6869 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6870 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6871 else
6872 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6873 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6874 vmx_set_efer(vcpu, vcpu->arch.efer);
6875
6876 /*
6877 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6878 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6879 * The CR0_READ_SHADOW is what L2 should have expected to read given
6880 * the specifications by L1; It's not enough to take
6881 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6882 * have more bits than L1 expected.
6883 */
6884 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6885 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6886
6887 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6888 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6889
6890 /* shadow page tables on either EPT or shadow page tables */
6891 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6892 kvm_mmu_reset_context(vcpu);
6893
6894 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6895 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6896}
6897
cd232ad0
NHE		 6898/*
6899 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6900 * for running an L2 nested guest.
6901 */
6902static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6903{
6904 struct vmcs12 *vmcs12;
6905 struct vcpu_vmx *vmx = to_vmx(vcpu);
6906 int cpu;
6907 struct loaded_vmcs *vmcs02;
6908
6909 if (!nested_vmx_check_permission(vcpu) ||
6910 !nested_vmx_check_vmcs12(vcpu))
6911 return 1;
6912
6913 skip_emulated_instruction(vcpu);
6914 vmcs12 = get_vmcs12(vcpu);
6915
7c177938
NHE		 6916 /*
6917 * The nested entry process starts with enforcing various prerequisites
6918 * on vmcs12 as required by the Intel SDM, and act appropriately when
6919 * they fail: As the SDM explains, some conditions should cause the
6920 * instruction to fail, while others will cause the instruction to seem
6921 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6922 * To speed up the normal (success) code path, we should avoid checking
6923 * for misconfigurations which will anyway be caught by the processor
6924 * when using the merged vmcs02.
6925 */
6926 if (vmcs12->launch_state == launch) {
6927 nested_vmx_failValid(vcpu,
6928 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6929 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6930 return 1;
6931 }
6932
6933 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6934 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6935 /*TODO: Also verify bits beyond physical address width are 0*/
6936 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6937 return 1;
6938 }
6939
6940 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6941 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6942 /*TODO: Also verify bits beyond physical address width are 0*/
6943 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6944 return 1;
6945 }
6946
6947 if (vmcs12->vm_entry_msr_load_count > 0 ||
6948 vmcs12->vm_exit_msr_load_count > 0 ||
6949 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6950 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6951 __func__);
7c177938
NHE		 6952 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6953 return 1;
6954 }
6955
6956 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6957 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6958 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6959 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6960 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6961 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6962 !vmx_control_verify(vmcs12->vm_exit_controls,
6963 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6964 !vmx_control_verify(vmcs12->vm_entry_controls,
6965 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6966 {
6967 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6968 return 1;
6969 }
6970
6971 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6972 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6973 nested_vmx_failValid(vcpu,
6974 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6975 return 1;
6976 }
6977
6978 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6979 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6980 nested_vmx_entry_failure(vcpu, vmcs12,
6981 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6982 return 1;
6983 }
6984 if (vmcs12->vmcs_link_pointer != -1ull) {
6985 nested_vmx_entry_failure(vcpu, vmcs12,
6986 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6987 return 1;
6988 }
6989
6990 /*
6991 * We're finally done with prerequisite checking, and can start with
6992 * the nested entry.
6993 */
6994
cd232ad0
NHE		 6995 vmcs02 = nested_get_current_vmcs02(vmx);
6996 if (!vmcs02)
6997 return -ENOMEM;
6998
6999 enter_guest_mode(vcpu);
7000
7001 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7002
7003 cpu = get_cpu();
7004 vmx->loaded_vmcs = vmcs02;
7005 vmx_vcpu_put(vcpu);
7006 vmx_vcpu_load(vcpu, cpu);
7007 vcpu->cpu = cpu;
7008 put_cpu();
7009
7010 vmcs12->launch_state = 1;
7011
7012 prepare_vmcs02(vcpu, vmcs12);
7013
7014 /*
7015 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7016 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7017 * returned as far as L1 is concerned. It will only return (and set
7018 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7019 */
7020 return 1;
7021}
7022
4704d0be
NHE		 7023/*
7024 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7025 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7026 * This function returns the new value we should put in vmcs12.guest_cr0.
7027 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7028 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7029 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7030 * didn't trap the bit, because if L1 did, so would L0).
7031 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7032 * been modified by L2, and L1 knows it. So just leave the old value of
7033 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7034 * isn't relevant, because if L0 traps this bit it can set it to anything.
7035 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7036 * changed these bits, and therefore they need to be updated, but L0
7037 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7038 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7039 */
7040static inline unsigned long
7041vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7042{
7043 return
7044 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7045 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7046 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7047 vcpu->arch.cr0_guest_owned_bits));
7048}
7049
7050static inline unsigned long
7051vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7052{
7053 return
7054 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7055 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7056 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7057 vcpu->arch.cr4_guest_owned_bits));
7058}
7059
7060/*
7061 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7062 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7063 * and this function updates it to reflect the changes to the guest state while
7064 * L2 was running (and perhaps made some exits which were handled directly by L0
7065 * without going back to L1), and to reflect the exit reason.
7066 * Note that we do not have to copy here all VMCS fields, just those that
7067 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7068 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7069 * which already writes to vmcs12 directly.
7070 */
7071void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7072{
7073 /* update guest state fields: */
7074 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7075 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7076
7077 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7078 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7079 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7080 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7081
7082 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7083 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7084 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7085 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7086 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7087 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7088 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7089 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7090 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7091 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7092 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7093 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7094 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7095 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7096 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7097 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7098 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7099 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7100 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7101 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7102 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7103 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7104 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7105 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7106 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7107 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7108 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7109 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7110 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7111 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7112 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7113 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7114 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7115 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7116 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7117 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7118
7119 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7120 vmcs12->guest_interruptibility_info =
7121 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7122 vmcs12->guest_pending_dbg_exceptions =
7123 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7124
7125 /* TODO: These cannot have changed unless we have MSR bitmaps and
7126 * the relevant bit asks not to trap the change */
7127 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7128 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7129 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7130 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7131 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7132 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7133
7134 /* update exit information fields: */
7135
7136 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7137 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7138
7139 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7140 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7141 vmcs12->idt_vectoring_info_field =
7142 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7143 vmcs12->idt_vectoring_error_code =
7144 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7145 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7146 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7147
7148 /* clear vm-entry fields which are to be cleared on exit */
7149 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7150 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7151}
7152
7153/*
7154 * A part of what we need to when the nested L2 guest exits and we want to
7155 * run its L1 parent, is to reset L1's guest state to the host state specified
7156 * in vmcs12.
7157 * This function is to be called not only on normal nested exit, but also on
7158 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7159 * Failures During or After Loading Guest State").
7160 * This function should be called when the active VMCS is L1's (vmcs01).
7161 */
7162void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7163{
7164 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7165 vcpu->arch.efer = vmcs12->host_ia32_efer;
7166 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7167 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7168 else
7169 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7170 vmx_set_efer(vcpu, vcpu->arch.efer);
7171
7172 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7173 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7174 /*
7175 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7176 * actually changed, because it depends on the current state of
7177 * fpu_active (which may have changed).
7178 * Note that vmx_set_cr0 refers to efer set above.
7179 */
7180 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7181 /*
7182 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7183 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7184 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7185 */
7186 update_exception_bitmap(vcpu);
7187 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7188 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7189
7190 /*
7191 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7192 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7193 */
7194 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7195 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7196
7197 /* shadow page tables on either EPT or shadow page tables */
7198 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7199 kvm_mmu_reset_context(vcpu);
7200
7201 if (enable_vpid) {
7202 /*
7203 * Trivially support vpid by letting L2s share their parent
7204 * L1's vpid. TODO: move to a more elaborate solution, giving
7205 * each L2 its own vpid and exposing the vpid feature to L1.
7206 */
7207 vmx_flush_tlb(vcpu);
7208 }
7209
7210
7211 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7212 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7213 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7214 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7215 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7216 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7217 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7218 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7219 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7220 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7221 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7222 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7223 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7224 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7225 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7226
7227 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7228 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7229 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7230 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7231 vmcs12->host_ia32_perf_global_ctrl);
7232}
7233
7234/*
7235 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7236 * and modify vmcs12 to make it see what it would expect to see there if
7237 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7238 */
7239static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7240{
7241 struct vcpu_vmx *vmx = to_vmx(vcpu);
7242 int cpu;
7243 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7244
7245 leave_guest_mode(vcpu);
7246 prepare_vmcs12(vcpu, vmcs12);
7247
7248 cpu = get_cpu();
7249 vmx->loaded_vmcs = &vmx->vmcs01;
7250 vmx_vcpu_put(vcpu);
7251 vmx_vcpu_load(vcpu, cpu);
7252 vcpu->cpu = cpu;
7253 put_cpu();
7254
7255 /* if no vmcs02 cache requested, remove the one we used */
7256 if (VMCS02_POOL_SIZE == 0)
7257 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7258
7259 load_vmcs12_host_state(vcpu, vmcs12);
7260
27fc51b2 7261 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7262 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7263
7264 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7265 vmx->host_rsp = 0;
7266
7267 /* Unpin physical memory we referred to in vmcs02 */
7268 if (vmx->nested.apic_access_page) {
7269 nested_release_page(vmx->nested.apic_access_page);
7270 vmx->nested.apic_access_page = 0;
7271 }
7272
7273 /*
7274 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7275 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7276 * success or failure flag accordingly.
7277 */
7278 if (unlikely(vmx->fail)) {
7279 vmx->fail = 0;
7280 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7281 } else
7282 nested_vmx_succeed(vcpu);
7283}
7284
7c177938
NHE		 7285/*
7286 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7287 * 23.7 "VM-entry failures during or after loading guest state" (this also
7288 * lists the acceptable exit-reason and exit-qualification parameters).
7289 * It should only be called before L2 actually succeeded to run, and when
7290 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7291 */
7292static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7293 struct vmcs12 *vmcs12,
7294 u32 reason, unsigned long qualification)
7295{
7296 load_vmcs12_host_state(vcpu, vmcs12);
7297 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7298 vmcs12->exit_qualification = qualification;
7299 nested_vmx_succeed(vcpu);
7300}
7301
8a76d7f2
JR		 7302static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7303 struct x86_instruction_info *info,
7304 enum x86_intercept_stage stage)
7305{
7306 return X86EMUL_CONTINUE;
7307}
7308
cbdd1bea 7309static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7310 .cpu_has_kvm_support = cpu_has_kvm_support,
7311 .disabled_by_bios = vmx_disabled_by_bios,
7312 .hardware_setup = hardware_setup,
7313 .hardware_unsetup = hardware_unsetup,
002c7f7c 7314 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7315 .hardware_enable = hardware_enable,
7316 .hardware_disable = hardware_disable,
04547156 7317 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7318
7319 .vcpu_create = vmx_create_vcpu,
7320 .vcpu_free = vmx_free_vcpu,
04d2cc77 7321 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7322
04d2cc77 7323 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7324 .vcpu_load = vmx_vcpu_load,
7325 .vcpu_put = vmx_vcpu_put,
7326
c8639010 7327 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7328 .get_msr = vmx_get_msr,
7329 .set_msr = vmx_set_msr,
7330 .get_segment_base = vmx_get_segment_base,
7331 .get_segment = vmx_get_segment,
7332 .set_segment = vmx_set_segment,
2e4d2653 7333 .get_cpl = vmx_get_cpl,
6aa8b732 7334 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7335 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7336 .decache_cr3 = vmx_decache_cr3,
25c4c276 7337 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7338 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7339 .set_cr3 = vmx_set_cr3,
7340 .set_cr4 = vmx_set_cr4,
6aa8b732 7341 .set_efer = vmx_set_efer,
6aa8b732
AK		 7342 .get_idt = vmx_get_idt,
7343 .set_idt = vmx_set_idt,
7344 .get_gdt = vmx_get_gdt,
7345 .set_gdt = vmx_set_gdt,
020df079 7346 .set_dr7 = vmx_set_dr7,
5fdbf976 7347 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7348 .get_rflags = vmx_get_rflags,
7349 .set_rflags = vmx_set_rflags,
ebcbab4c 7350 .fpu_activate = vmx_fpu_activate,
02daab21 7351 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7352
7353 .tlb_flush = vmx_flush_tlb,
6aa8b732 7354
6aa8b732 7355 .run = vmx_vcpu_run,
6062d012 7356 .handle_exit = vmx_handle_exit,
6aa8b732 7357 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7358 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7359 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7360 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7361 .set_irq = vmx_inject_irq,
95ba8273 7362 .set_nmi = vmx_inject_nmi,
298101da 7363 .queue_exception = vmx_queue_exception,
b463a6f7 7364 .cancel_injection = vmx_cancel_injection,
78646121 7365 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7366 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7367 .get_nmi_mask = vmx_get_nmi_mask,
7368 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7369 .enable_nmi_window = enable_nmi_window,
7370 .enable_irq_window = enable_irq_window,
7371 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7372
cbc94022 7373 .set_tss_addr = vmx_set_tss_addr,
67253af5 7374 .get_tdp_level = get_ept_level,
4b12f0de 7375 .get_mt_mask = vmx_get_mt_mask,
229456fc 7376
586f9607 7377 .get_exit_info = vmx_get_exit_info,
586f9607 7378
17cc3935 7379 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7380
7381 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7382
7383 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7384 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7385
7386 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7387
7388 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7389
4051b188 7390 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7391 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7392 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7393 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7394 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7395 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7396
7397 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7398
7399 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7400};
7401
7402static int __init vmx_init(void)
7403{
26bb0981
AK		 7404 int r, i;
7405
7406 rdmsrl_safe(MSR_EFER, &host_efer);
7407
7408 for (i = 0; i < NR_VMX_MSR; ++i)
7409 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7410
3e7c73e9 7411 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7412 if (!vmx_io_bitmap_a)
7413 return -ENOMEM;
7414
2106a548
GC		 7415 r = -ENOMEM;
7416
3e7c73e9 7417 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7418 if (!vmx_io_bitmap_b)
fdef3ad1 7419 goto out;
fdef3ad1 7420
5897297b 7421 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7422 if (!vmx_msr_bitmap_legacy)
25c5f225 7423 goto out1;
2106a548 7424
25c5f225 7425
5897297b 7426 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7427 if (!vmx_msr_bitmap_longmode)
5897297b 7428 goto out2;
2106a548 7429
5897297b 7430
fdef3ad1
HQ		 7431 /*
7432 * Allow direct access to the PC debug port (it is often used for I/O
7433 * delays, but the vmexits simply slow things down).
7434 */
3e7c73e9
AK		 7435 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7436 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7437
3e7c73e9 7438 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7439
5897297b
AK		 7440 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7441 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7442
2384d2b3
SY		 7443 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7444
0ee75bea
AK		 7445 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7446 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7447 if (r)
5897297b 7448 goto out3;
25c5f225 7449
8f536b76
ZY		 7450#ifdef CONFIG_KEXEC
7451 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7452 crash_vmclear_local_loaded_vmcss);
7453#endif
7454
5897297b
AK		 7455 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7456 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7457 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7458 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7459 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7460 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7461
089d034e 7462 if (enable_ept) {
3f6d8c8a
XH		 7463 kvm_mmu_set_mask_ptes(0ull,
7464 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7465 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7466 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7467 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7468 kvm_enable_tdp();
7469 } else
7470 kvm_disable_tdp();
1439442c 7471
fdef3ad1
HQ		 7472 return 0;
7473
5897297b
AK		 7474out3:
7475 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7476out2:
5897297b 7477 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7478out1:
3e7c73e9 7479 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7480out:
3e7c73e9 7481 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7482 return r;
6aa8b732
AK		 7483}
7484
7485static void __exit vmx_exit(void)
7486{
5897297b
AK		 7487 free_page((unsigned long)vmx_msr_bitmap_legacy);
7488 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7489 free_page((unsigned long)vmx_io_bitmap_b);
7490 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7491
8f536b76
ZY		 7492#ifdef CONFIG_KEXEC
7493 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7494 synchronize_rcu();
7495#endif
7496
cb498ea2 7497 kvm_exit();
6aa8b732
AK		 7498}
7499
7500module_init(vmx_init)
7501module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)