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x86: vdso: pvclock gettime support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
a27685c3 77static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
83287ea4
AK		 130extern const ulong vmx_return;
131
8bf00a52 132#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 133#define VMCS02_POOL_SIZE 1
61d2ef2c 134
a2fa3e9f
GH		 135struct vmcs {
136 u32 revision_id;
137 u32 abort;
138 char data[0];
139};
140
d462b819
NHE		 141/*
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
145 */
146struct loaded_vmcs {
147 struct vmcs *vmcs;
148 int cpu;
149 int launched;
150 struct list_head loaded_vmcss_on_cpu_link;
151};
152
26bb0981
AK		 153struct shared_msr_entry {
154 unsigned index;
155 u64 data;
d5696725 156 u64 mask;
26bb0981
AK		 157};
158
a9d30f33
NHE		 159/*
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 */
22bd0358 172typedef u64 natural_width;
a9d30f33
NHE		 173struct __packed vmcs12 {
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
176 */
177 u32 revision_id;
178 u32 abort;
22bd0358 179
27d6c865
NHE		 180 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding[7]; /* room for future expansion */
182
22bd0358
NHE		 183 u64 io_bitmap_a;
184 u64 io_bitmap_b;
185 u64 msr_bitmap;
186 u64 vm_exit_msr_store_addr;
187 u64 vm_exit_msr_load_addr;
188 u64 vm_entry_msr_load_addr;
189 u64 tsc_offset;
190 u64 virtual_apic_page_addr;
191 u64 apic_access_addr;
192 u64 ept_pointer;
193 u64 guest_physical_address;
194 u64 vmcs_link_pointer;
195 u64 guest_ia32_debugctl;
196 u64 guest_ia32_pat;
197 u64 guest_ia32_efer;
198 u64 guest_ia32_perf_global_ctrl;
199 u64 guest_pdptr0;
200 u64 guest_pdptr1;
201 u64 guest_pdptr2;
202 u64 guest_pdptr3;
203 u64 host_ia32_pat;
204 u64 host_ia32_efer;
205 u64 host_ia32_perf_global_ctrl;
206 u64 padding64[8]; /* room for future expansion */
207 /*
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
212 */
213 natural_width cr0_guest_host_mask;
214 natural_width cr4_guest_host_mask;
215 natural_width cr0_read_shadow;
216 natural_width cr4_read_shadow;
217 natural_width cr3_target_value0;
218 natural_width cr3_target_value1;
219 natural_width cr3_target_value2;
220 natural_width cr3_target_value3;
221 natural_width exit_qualification;
222 natural_width guest_linear_address;
223 natural_width guest_cr0;
224 natural_width guest_cr3;
225 natural_width guest_cr4;
226 natural_width guest_es_base;
227 natural_width guest_cs_base;
228 natural_width guest_ss_base;
229 natural_width guest_ds_base;
230 natural_width guest_fs_base;
231 natural_width guest_gs_base;
232 natural_width guest_ldtr_base;
233 natural_width guest_tr_base;
234 natural_width guest_gdtr_base;
235 natural_width guest_idtr_base;
236 natural_width guest_dr7;
237 natural_width guest_rsp;
238 natural_width guest_rip;
239 natural_width guest_rflags;
240 natural_width guest_pending_dbg_exceptions;
241 natural_width guest_sysenter_esp;
242 natural_width guest_sysenter_eip;
243 natural_width host_cr0;
244 natural_width host_cr3;
245 natural_width host_cr4;
246 natural_width host_fs_base;
247 natural_width host_gs_base;
248 natural_width host_tr_base;
249 natural_width host_gdtr_base;
250 natural_width host_idtr_base;
251 natural_width host_ia32_sysenter_esp;
252 natural_width host_ia32_sysenter_eip;
253 natural_width host_rsp;
254 natural_width host_rip;
255 natural_width paddingl[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control;
257 u32 cpu_based_vm_exec_control;
258 u32 exception_bitmap;
259 u32 page_fault_error_code_mask;
260 u32 page_fault_error_code_match;
261 u32 cr3_target_count;
262 u32 vm_exit_controls;
263 u32 vm_exit_msr_store_count;
264 u32 vm_exit_msr_load_count;
265 u32 vm_entry_controls;
266 u32 vm_entry_msr_load_count;
267 u32 vm_entry_intr_info_field;
268 u32 vm_entry_exception_error_code;
269 u32 vm_entry_instruction_len;
270 u32 tpr_threshold;
271 u32 secondary_vm_exec_control;
272 u32 vm_instruction_error;
273 u32 vm_exit_reason;
274 u32 vm_exit_intr_info;
275 u32 vm_exit_intr_error_code;
276 u32 idt_vectoring_info_field;
277 u32 idt_vectoring_error_code;
278 u32 vm_exit_instruction_len;
279 u32 vmx_instruction_info;
280 u32 guest_es_limit;
281 u32 guest_cs_limit;
282 u32 guest_ss_limit;
283 u32 guest_ds_limit;
284 u32 guest_fs_limit;
285 u32 guest_gs_limit;
286 u32 guest_ldtr_limit;
287 u32 guest_tr_limit;
288 u32 guest_gdtr_limit;
289 u32 guest_idtr_limit;
290 u32 guest_es_ar_bytes;
291 u32 guest_cs_ar_bytes;
292 u32 guest_ss_ar_bytes;
293 u32 guest_ds_ar_bytes;
294 u32 guest_fs_ar_bytes;
295 u32 guest_gs_ar_bytes;
296 u32 guest_ldtr_ar_bytes;
297 u32 guest_tr_ar_bytes;
298 u32 guest_interruptibility_info;
299 u32 guest_activity_state;
300 u32 guest_sysenter_cs;
301 u32 host_ia32_sysenter_cs;
302 u32 padding32[8]; /* room for future expansion */
303 u16 virtual_processor_id;
304 u16 guest_es_selector;
305 u16 guest_cs_selector;
306 u16 guest_ss_selector;
307 u16 guest_ds_selector;
308 u16 guest_fs_selector;
309 u16 guest_gs_selector;
310 u16 guest_ldtr_selector;
311 u16 guest_tr_selector;
312 u16 host_es_selector;
313 u16 host_cs_selector;
314 u16 host_ss_selector;
315 u16 host_ds_selector;
316 u16 host_fs_selector;
317 u16 host_gs_selector;
318 u16 host_tr_selector;
a9d30f33
NHE		 319};
320
321/*
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 */
326#define VMCS12_REVISION 0x11e57ed0
327
328/*
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
332 */
333#define VMCS12_SIZE 0x1000
334
ff2f6fe9
NHE		 335/* Used to remember the last vmcs02 used for some recently used vmcs12s */
336struct vmcs02_list {
337 struct list_head list;
338 gpa_t vmptr;
339 struct loaded_vmcs vmcs02;
340};
341
ec378aee
NHE		 342/*
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 */
346struct nested_vmx {
347 /* Has the level1 guest done vmxon? */
348 bool vmxon;
a9d30f33
NHE		 349
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 gpa_t current_vmptr;
352 /* The host-usable pointer to the above */
353 struct page *current_vmcs12_page;
354 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 355
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool;
358 int vmcs02_num;
fe3ef05c 359 u64 vmcs01_tsc_offset;
644d711a
NHE		 360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending;
fe3ef05c
NHE		 362 /*
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
365 */
366 struct page *apic_access_page;
ec378aee
NHE		 367};
368
a2fa3e9f 369struct vcpu_vmx {
fb3f0f51 370 struct kvm_vcpu vcpu;
313dbd49 371 unsigned long host_rsp;
29bd8a78 372 u8 fail;
69c73028 373 u8 cpl;
9d58b931 374 bool nmi_known_unmasked;
51aa01d1 375 u32 exit_intr_info;
1155f76a 376 u32 idt_vectoring_info;
6de12732 377 ulong rflags;
26bb0981 378 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 379 int nmsrs;
380 int save_nmsrs;
a2fa3e9f 381#ifdef CONFIG_X86_64
44ea2b17
AK		 382 u64 msr_host_kernel_gs_base;
383 u64 msr_guest_kernel_gs_base;
a2fa3e9f 384#endif
d462b819
NHE		 385 /*
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
389 */
390 struct loaded_vmcs vmcs01;
391 struct loaded_vmcs *loaded_vmcs;
392 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 393 struct msr_autoload {
394 unsigned nr;
395 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
396 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
397 } msr_autoload;
a2fa3e9f
GH		 398 struct {
399 int loaded;
400 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 401#ifdef CONFIG_X86_64
402 u16 ds_sel, es_sel;
403#endif
152d3f2f
LV		 404 int gs_ldt_reload_needed;
405 int fs_reload_needed;
d77c26fc 406 } host_state;
9c8cba37 407 struct {
7ffd92c5 408 int vm86_active;
78ac8b47 409 ulong save_rflags;
f5f7b2fe
AK		 410 struct kvm_segment segs[8];
411 } rmode;
412 struct {
413 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 414 struct kvm_save_segment {
415 u16 selector;
416 unsigned long base;
417 u32 limit;
418 u32 ar;
f5f7b2fe 419 } seg[8];
2fb92db1 420 } segment_cache;
2384d2b3 421 int vpid;
04fa4d32 422 bool emulation_required;
3b86cd99
JK		 423
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked;
426 ktime_t entry_time;
427 s64 vnmi_blocked_time;
a0861c02 428 u32 exit_reason;
4e47c7a6
SY		 429
430 bool rdtscp_enabled;
ec378aee
NHE		 431
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested;
a2fa3e9f
GH		 434};
435
2fb92db1
AK		 436enum segment_cache_field {
437 SEG_FIELD_SEL = 0,
438 SEG_FIELD_BASE = 1,
439 SEG_FIELD_LIMIT = 2,
440 SEG_FIELD_AR = 3,
441
442 SEG_FIELD_NR = 4
443};
444
a2fa3e9f
GH		 445static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
446{
fb3f0f51 447 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 448}
449
22bd0358
NHE		 450#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
454
772e0318 455static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 456 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
457 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
458 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
459 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
460 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
461 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
462 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
463 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
464 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
465 FIELD(HOST_ES_SELECTOR, host_es_selector),
466 FIELD(HOST_CS_SELECTOR, host_cs_selector),
467 FIELD(HOST_SS_SELECTOR, host_ss_selector),
468 FIELD(HOST_DS_SELECTOR, host_ds_selector),
469 FIELD(HOST_FS_SELECTOR, host_fs_selector),
470 FIELD(HOST_GS_SELECTOR, host_gs_selector),
471 FIELD(HOST_TR_SELECTOR, host_tr_selector),
472 FIELD64(IO_BITMAP_A, io_bitmap_a),
473 FIELD64(IO_BITMAP_B, io_bitmap_b),
474 FIELD64(MSR_BITMAP, msr_bitmap),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
478 FIELD64(TSC_OFFSET, tsc_offset),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
480 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
481 FIELD64(EPT_POINTER, ept_pointer),
482 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
483 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
484 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
485 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
486 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
488 FIELD64(GUEST_PDPTR0, guest_pdptr0),
489 FIELD64(GUEST_PDPTR1, guest_pdptr1),
490 FIELD64(GUEST_PDPTR2, guest_pdptr2),
491 FIELD64(GUEST_PDPTR3, guest_pdptr3),
492 FIELD64(HOST_IA32_PAT, host_ia32_pat),
493 FIELD64(HOST_IA32_EFER, host_ia32_efer),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
497 FIELD(EXCEPTION_BITMAP, exception_bitmap),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
500 FIELD(CR3_TARGET_COUNT, cr3_target_count),
501 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
502 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
504 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
509 FIELD(TPR_THRESHOLD, tpr_threshold),
510 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
511 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
512 FIELD(VM_EXIT_REASON, vm_exit_reason),
513 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
514 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
515 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
516 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
517 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
518 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
519 FIELD(GUEST_ES_LIMIT, guest_es_limit),
520 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
521 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
522 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
523 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
524 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
525 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
526 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
527 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
528 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
529 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
530 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
531 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
532 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
533 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
534 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
535 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
536 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
538 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
539 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
540 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
541 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
542 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
543 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
544 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
545 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
546 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
547 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
548 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
549 FIELD(EXIT_QUALIFICATION, exit_qualification),
550 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
551 FIELD(GUEST_CR0, guest_cr0),
552 FIELD(GUEST_CR3, guest_cr3),
553 FIELD(GUEST_CR4, guest_cr4),
554 FIELD(GUEST_ES_BASE, guest_es_base),
555 FIELD(GUEST_CS_BASE, guest_cs_base),
556 FIELD(GUEST_SS_BASE, guest_ss_base),
557 FIELD(GUEST_DS_BASE, guest_ds_base),
558 FIELD(GUEST_FS_BASE, guest_fs_base),
559 FIELD(GUEST_GS_BASE, guest_gs_base),
560 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
561 FIELD(GUEST_TR_BASE, guest_tr_base),
562 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
563 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
564 FIELD(GUEST_DR7, guest_dr7),
565 FIELD(GUEST_RSP, guest_rsp),
566 FIELD(GUEST_RIP, guest_rip),
567 FIELD(GUEST_RFLAGS, guest_rflags),
568 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
569 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
570 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
571 FIELD(HOST_CR0, host_cr0),
572 FIELD(HOST_CR3, host_cr3),
573 FIELD(HOST_CR4, host_cr4),
574 FIELD(HOST_FS_BASE, host_fs_base),
575 FIELD(HOST_GS_BASE, host_gs_base),
576 FIELD(HOST_TR_BASE, host_tr_base),
577 FIELD(HOST_GDTR_BASE, host_gdtr_base),
578 FIELD(HOST_IDTR_BASE, host_idtr_base),
579 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
580 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
581 FIELD(HOST_RSP, host_rsp),
582 FIELD(HOST_RIP, host_rip),
583};
584static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
585
586static inline short vmcs_field_to_offset(unsigned long field)
587{
588 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
589 return -1;
590 return vmcs_field_to_offset_table[field];
591}
592
a9d30f33
NHE		 593static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
594{
595 return to_vmx(vcpu)->nested.current_vmcs12;
596}
597
598static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
599{
600 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 601 if (is_error_page(page))
a9d30f33 602 return NULL;
32cad84f 603
a9d30f33
NHE		 604 return page;
605}
606
607static void nested_release_page(struct page *page)
608{
609 kvm_release_page_dirty(page);
610}
611
612static void nested_release_page_clean(struct page *page)
613{
614 kvm_release_page_clean(page);
615}
616
4e1096d2 617static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 618static void kvm_cpu_vmxon(u64 addr);
619static void kvm_cpu_vmxoff(void);
aff48baa 620static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 621static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 622static void vmx_set_segment(struct kvm_vcpu *vcpu,
623 struct kvm_segment *var, int seg);
624static void vmx_get_segment(struct kvm_vcpu *vcpu,
625 struct kvm_segment *var, int seg);
75880a01 626
6aa8b732
AK		 627static DEFINE_PER_CPU(struct vmcs *, vmxarea);
628static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 629/*
630 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
631 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 */
633static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 634static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 635
3e7c73e9
AK		 636static unsigned long *vmx_io_bitmap_a;
637static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 638static unsigned long *vmx_msr_bitmap_legacy;
639static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 640
110312c8 641static bool cpu_has_load_ia32_efer;
8bf00a52 642static bool cpu_has_load_perf_global_ctrl;
110312c8 643
2384d2b3
SY		 644static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
645static DEFINE_SPINLOCK(vmx_vpid_lock);
646
1c3d14fe 647static struct vmcs_config {
6aa8b732
AK		 648 int size;
649 int order;
650 u32 revision_id;
1c3d14fe
YS		 651 u32 pin_based_exec_ctrl;
652 u32 cpu_based_exec_ctrl;
f78e0e2e 653 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 654 u32 vmexit_ctrl;
655 u32 vmentry_ctrl;
656} vmcs_config;
6aa8b732 657
efff9e53 658static struct vmx_capability {
d56f546d
SY		 659 u32 ept;
660 u32 vpid;
661} vmx_capability;
662
6aa8b732
AK		 663#define VMX_SEGMENT_FIELD(seg) \
664 [VCPU_SREG_##seg] = { \
665 .selector = GUEST_##seg##_SELECTOR, \
666 .base = GUEST_##seg##_BASE, \
667 .limit = GUEST_##seg##_LIMIT, \
668 .ar_bytes = GUEST_##seg##_AR_BYTES, \
669 }
670
772e0318 671static const struct kvm_vmx_segment_field {
6aa8b732
AK		 672 unsigned selector;
673 unsigned base;
674 unsigned limit;
675 unsigned ar_bytes;
676} kvm_vmx_segment_fields[] = {
677 VMX_SEGMENT_FIELD(CS),
678 VMX_SEGMENT_FIELD(DS),
679 VMX_SEGMENT_FIELD(ES),
680 VMX_SEGMENT_FIELD(FS),
681 VMX_SEGMENT_FIELD(GS),
682 VMX_SEGMENT_FIELD(SS),
683 VMX_SEGMENT_FIELD(TR),
684 VMX_SEGMENT_FIELD(LDTR),
685};
686
26bb0981
AK		 687static u64 host_efer;
688
6de4f3ad
AK		 689static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
690
4d56c8a7 691/*
8c06585d 692 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 693 * away by decrementing the array size.
694 */
6aa8b732 695static const u32 vmx_msr_index[] = {
05b3e0c2 696#ifdef CONFIG_X86_64
44ea2b17 697 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 698#endif
8c06585d 699 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 700};
9d8f549d 701#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 702
31299944 703static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 704{
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
706 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 707 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 708}
709
31299944 710static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 711{
712 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
713 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 714 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 715}
716
31299944 717static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 718{
719 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
720 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 721 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 722}
723
31299944 724static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 725{
726 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
727 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
728}
729
31299944 730static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 731{
732 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
733 INTR_INFO_VALID_MASK)) ==
734 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
735}
736
31299944 737static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 738{
04547156 739 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 740}
741
31299944 742static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 743{
04547156 744 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 745}
746
31299944 747static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 748{
04547156 749 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 750}
751
31299944 752static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 753{
04547156
SY		 754 return vmcs_config.cpu_based_exec_ctrl &
755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 756}
757
774ead3a 758static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 759{
04547156
SY		 760 return vmcs_config.cpu_based_2nd_exec_ctrl &
761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
762}
763
764static inline bool cpu_has_vmx_flexpriority(void)
765{
766 return cpu_has_vmx_tpr_shadow() &&
767 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 768}
769
e799794e
MT		 770static inline bool cpu_has_vmx_ept_execute_only(void)
771{
31299944 772 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 773}
774
775static inline bool cpu_has_vmx_eptp_uncacheable(void)
776{
31299944 777 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 778}
779
780static inline bool cpu_has_vmx_eptp_writeback(void)
781{
31299944 782 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 783}
784
785static inline bool cpu_has_vmx_ept_2m_page(void)
786{
31299944 787 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 788}
789
878403b7
SY		 790static inline bool cpu_has_vmx_ept_1g_page(void)
791{
31299944 792 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 793}
794
4bc9b982
SY		 795static inline bool cpu_has_vmx_ept_4levels(void)
796{
797 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
798}
799
83c3a331
XH		 800static inline bool cpu_has_vmx_ept_ad_bits(void)
801{
802 return vmx_capability.ept & VMX_EPT_AD_BIT;
803}
804
31299944 805static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 806{
31299944 807 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 808}
809
31299944 810static inline bool cpu_has_vmx_invept_context(void)
d56f546d 811{
31299944 812 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 813}
814
31299944 815static inline bool cpu_has_vmx_invept_global(void)
d56f546d 816{
31299944 817 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 818}
819
518c8aee
GJ		 820static inline bool cpu_has_vmx_invvpid_single(void)
821{
822 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
823}
824
b9d762fa
GJ		 825static inline bool cpu_has_vmx_invvpid_global(void)
826{
827 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
828}
829
31299944 830static inline bool cpu_has_vmx_ept(void)
d56f546d 831{
04547156
SY		 832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 834}
835
31299944 836static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 837{
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_UNRESTRICTED_GUEST;
840}
841
31299944 842static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 843{
844 return vmcs_config.cpu_based_2nd_exec_ctrl &
845 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
846}
847
31299944 848static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 849{
6d3e435e 850 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 851}
852
31299944 853static inline bool cpu_has_vmx_vpid(void)
2384d2b3 854{
04547156
SY		 855 return vmcs_config.cpu_based_2nd_exec_ctrl &
856 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 857}
858
31299944 859static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 860{
861 return vmcs_config.cpu_based_2nd_exec_ctrl &
862 SECONDARY_EXEC_RDTSCP;
863}
864
ad756a16
MJ		 865static inline bool cpu_has_vmx_invpcid(void)
866{
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_ENABLE_INVPCID;
869}
870
31299944 871static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 872{
873 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
874}
875
f5f48ee1
SY		 876static inline bool cpu_has_vmx_wbinvd_exit(void)
877{
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_WBINVD_EXITING;
880}
881
04547156
SY		 882static inline bool report_flexpriority(void)
883{
884 return flexpriority_enabled;
885}
886
fe3ef05c
NHE		 887static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
888{
889 return vmcs12->cpu_based_vm_exec_control & bit;
890}
891
892static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
893{
894 return (vmcs12->cpu_based_vm_exec_control &
895 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
896 (vmcs12->secondary_vm_exec_control & bit);
897}
898
644d711a
NHE		 899static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
900 struct kvm_vcpu *vcpu)
901{
902 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
903}
904
905static inline bool is_exception(u32 intr_info)
906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
908 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
909}
910
911static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 912static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
913 struct vmcs12 *vmcs12,
914 u32 reason, unsigned long qualification);
915
8b9cf98c 916static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 917{
918 int i;
919
a2fa3e9f 920 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 921 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 922 return i;
923 return -1;
924}
925
2384d2b3
SY		 926static inline void __invvpid(int ext, u16 vpid, gva_t gva)
927{
928 struct {
929 u64 vpid : 16;
930 u64 rsvd : 48;
931 u64 gva;
932 } operand = { vpid, 0, gva };
933
4ecac3fd 934 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 935 /* CF==1 or ZF==1 --> rc = -1 */
936 "; ja 1f ; ud2 ; 1:"
937 : : "a"(&operand), "c"(ext) : "cc", "memory");
938}
939
1439442c
SY		 940static inline void __invept(int ext, u64 eptp, gpa_t gpa)
941{
942 struct {
943 u64 eptp, gpa;
944 } operand = {eptp, gpa};
945
4ecac3fd 946 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 947 /* CF==1 or ZF==1 --> rc = -1 */
948 "; ja 1f ; ud2 ; 1:\n"
949 : : "a" (&operand), "c" (ext) : "cc", "memory");
950}
951
26bb0981 952static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 953{
954 int i;
955
8b9cf98c 956 i = __find_msr_index(vmx, msr);
a75beee6 957 if (i >= 0)
a2fa3e9f 958 return &vmx->guest_msrs[i];
8b6d44c7 959 return NULL;
7725f0ba
AK		 960}
961
6aa8b732
AK		 962static void vmcs_clear(struct vmcs *vmcs)
963{
964 u64 phys_addr = __pa(vmcs);
965 u8 error;
966
4ecac3fd 967 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 968 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 969 : "cc", "memory");
970 if (error)
971 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
972 vmcs, phys_addr);
973}
974
d462b819
NHE		 975static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
976{
977 vmcs_clear(loaded_vmcs->vmcs);
978 loaded_vmcs->cpu = -1;
979 loaded_vmcs->launched = 0;
980}
981
7725b894
DX		 982static void vmcs_load(struct vmcs *vmcs)
983{
984 u64 phys_addr = __pa(vmcs);
985 u8 error;
986
987 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 988 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 989 : "cc", "memory");
990 if (error)
2844d849 991 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 992 vmcs, phys_addr);
993}
994
d462b819 995static void __loaded_vmcs_clear(void *arg)
6aa8b732 996{
d462b819 997 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 998 int cpu = raw_smp_processor_id();
6aa8b732 999
d462b819
NHE		 1000 if (loaded_vmcs->cpu != cpu)
1001 return; /* vcpu migration can race with cpu offline */
1002 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1003 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 1004 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1005 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 1006}
1007
d462b819 1008static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1009{
d462b819
NHE		 1010 if (loaded_vmcs->cpu != -1)
1011 smp_call_function_single(
1012 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1013}
1014
1760dd49 1015static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1016{
1017 if (vmx->vpid == 0)
1018 return;
1019
518c8aee
GJ		 1020 if (cpu_has_vmx_invvpid_single())
1021 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1022}
1023
b9d762fa
GJ		 1024static inline void vpid_sync_vcpu_global(void)
1025{
1026 if (cpu_has_vmx_invvpid_global())
1027 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1028}
1029
1030static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1031{
1032 if (cpu_has_vmx_invvpid_single())
1760dd49 1033 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1034 else
1035 vpid_sync_vcpu_global();
1036}
1037
1439442c
SY		 1038static inline void ept_sync_global(void)
1039{
1040 if (cpu_has_vmx_invept_global())
1041 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1042}
1043
1044static inline void ept_sync_context(u64 eptp)
1045{
089d034e 1046 if (enable_ept) {
1439442c
SY		 1047 if (cpu_has_vmx_invept_context())
1048 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1049 else
1050 ept_sync_global();
1051 }
1052}
1053
1054static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1055{
089d034e 1056 if (enable_ept) {
1439442c
SY		 1057 if (cpu_has_vmx_invept_individual_addr())
1058 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1059 eptp, gpa);
1060 else
1061 ept_sync_context(eptp);
1062 }
1063}
1064
96304217 1065static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1066{
5e520e62 1067 unsigned long value;
6aa8b732 1068
5e520e62
AK		 1069 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1070 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1071 return value;
1072}
1073
96304217 1074static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1075{
1076 return vmcs_readl(field);
1077}
1078
96304217 1079static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1080{
1081 return vmcs_readl(field);
1082}
1083
96304217 1084static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1085{
05b3e0c2 1086#ifdef CONFIG_X86_64
6aa8b732
AK		 1087 return vmcs_readl(field);
1088#else
1089 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1090#endif
1091}
1092
e52de1b8
AK		 1093static noinline void vmwrite_error(unsigned long field, unsigned long value)
1094{
1095 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1096 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1097 dump_stack();
1098}
1099
6aa8b732
AK		 1100static void vmcs_writel(unsigned long field, unsigned long value)
1101{
1102 u8 error;
1103
4ecac3fd 1104 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1105 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1106 if (unlikely(error))
1107 vmwrite_error(field, value);
6aa8b732
AK		 1108}
1109
1110static void vmcs_write16(unsigned long field, u16 value)
1111{
1112 vmcs_writel(field, value);
1113}
1114
1115static void vmcs_write32(unsigned long field, u32 value)
1116{
1117 vmcs_writel(field, value);
1118}
1119
1120static void vmcs_write64(unsigned long field, u64 value)
1121{
6aa8b732 1122 vmcs_writel(field, value);
7682f2d0 1123#ifndef CONFIG_X86_64
6aa8b732
AK		 1124 asm volatile ("");
1125 vmcs_writel(field+1, value >> 32);
1126#endif
1127}
1128
2ab455cc
AL		 1129static void vmcs_clear_bits(unsigned long field, u32 mask)
1130{
1131 vmcs_writel(field, vmcs_readl(field) & ~mask);
1132}
1133
1134static void vmcs_set_bits(unsigned long field, u32 mask)
1135{
1136 vmcs_writel(field, vmcs_readl(field) | mask);
1137}
1138
2fb92db1
AK		 1139static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1140{
1141 vmx->segment_cache.bitmask = 0;
1142}
1143
1144static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1145 unsigned field)
1146{
1147 bool ret;
1148 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1149
1150 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1151 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1152 vmx->segment_cache.bitmask = 0;
1153 }
1154 ret = vmx->segment_cache.bitmask & mask;
1155 vmx->segment_cache.bitmask |= mask;
1156 return ret;
1157}
1158
1159static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1160{
1161 u16 *p = &vmx->segment_cache.seg[seg].selector;
1162
1163 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1164 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1165 return *p;
1166}
1167
1168static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1169{
1170 ulong *p = &vmx->segment_cache.seg[seg].base;
1171
1172 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1173 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1174 return *p;
1175}
1176
1177static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1178{
1179 u32 *p = &vmx->segment_cache.seg[seg].limit;
1180
1181 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1182 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1183 return *p;
1184}
1185
1186static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1187{
1188 u32 *p = &vmx->segment_cache.seg[seg].ar;
1189
1190 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1191 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1192 return *p;
1193}
1194
abd3f2d6
AK		 1195static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1196{
1197 u32 eb;
1198
fd7373cc
JK		 1199 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1200 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1201 if ((vcpu->guest_debug &
1202 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1203 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1204 eb |= 1u << BP_VECTOR;
7ffd92c5 1205 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1206 eb = ~0;
089d034e 1207 if (enable_ept)
1439442c 1208 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1209 if (vcpu->fpu_active)
1210 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1211
1212 /* When we are running a nested L2 guest and L1 specified for it a
1213 * certain exception bitmap, we must trap the same exceptions and pass
1214 * them to L1. When running L2, we will only handle the exceptions
1215 * specified above if L1 did not want them.
1216 */
1217 if (is_guest_mode(vcpu))
1218 eb |= get_vmcs12(vcpu)->exception_bitmap;
1219
abd3f2d6
AK		 1220 vmcs_write32(EXCEPTION_BITMAP, eb);
1221}
1222
8bf00a52
GN		 1223static void clear_atomic_switch_msr_special(unsigned long entry,
1224 unsigned long exit)
1225{
1226 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1227 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1228}
1229
61d2ef2c
AK		 1230static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1231{
1232 unsigned i;
1233 struct msr_autoload *m = &vmx->msr_autoload;
1234
8bf00a52
GN		 1235 switch (msr) {
1236 case MSR_EFER:
1237 if (cpu_has_load_ia32_efer) {
1238 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1239 VM_EXIT_LOAD_IA32_EFER);
1240 return;
1241 }
1242 break;
1243 case MSR_CORE_PERF_GLOBAL_CTRL:
1244 if (cpu_has_load_perf_global_ctrl) {
1245 clear_atomic_switch_msr_special(
1246 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1247 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1248 return;
1249 }
1250 break;
110312c8
AK		 1251 }
1252
61d2ef2c
AK		 1253 for (i = 0; i < m->nr; ++i)
1254 if (m->guest[i].index == msr)
1255 break;
1256
1257 if (i == m->nr)
1258 return;
1259 --m->nr;
1260 m->guest[i] = m->guest[m->nr];
1261 m->host[i] = m->host[m->nr];
1262 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1263 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1264}
1265
8bf00a52
GN		 1266static void add_atomic_switch_msr_special(unsigned long entry,
1267 unsigned long exit, unsigned long guest_val_vmcs,
1268 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1269{
1270 vmcs_write64(guest_val_vmcs, guest_val);
1271 vmcs_write64(host_val_vmcs, host_val);
1272 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1273 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1274}
1275
61d2ef2c
AK		 1276static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1277 u64 guest_val, u64 host_val)
1278{
1279 unsigned i;
1280 struct msr_autoload *m = &vmx->msr_autoload;
1281
8bf00a52
GN		 1282 switch (msr) {
1283 case MSR_EFER:
1284 if (cpu_has_load_ia32_efer) {
1285 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1286 VM_EXIT_LOAD_IA32_EFER,
1287 GUEST_IA32_EFER,
1288 HOST_IA32_EFER,
1289 guest_val, host_val);
1290 return;
1291 }
1292 break;
1293 case MSR_CORE_PERF_GLOBAL_CTRL:
1294 if (cpu_has_load_perf_global_ctrl) {
1295 add_atomic_switch_msr_special(
1296 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1297 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1298 GUEST_IA32_PERF_GLOBAL_CTRL,
1299 HOST_IA32_PERF_GLOBAL_CTRL,
1300 guest_val, host_val);
1301 return;
1302 }
1303 break;
110312c8
AK		 1304 }
1305
61d2ef2c
AK		 1306 for (i = 0; i < m->nr; ++i)
1307 if (m->guest[i].index == msr)
1308 break;
1309
e7fc6f93
GN		 1310 if (i == NR_AUTOLOAD_MSRS) {
1311 printk_once(KERN_WARNING"Not enough mst switch entries. "
1312 "Can't add msr %x\n", msr);
1313 return;
1314 } else if (i == m->nr) {
61d2ef2c
AK		 1315 ++m->nr;
1316 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1317 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1318 }
1319
1320 m->guest[i].index = msr;
1321 m->guest[i].value = guest_val;
1322 m->host[i].index = msr;
1323 m->host[i].value = host_val;
1324}
1325
33ed6329
AK		 1326static void reload_tss(void)
1327{
33ed6329
AK		 1328 /*
1329 * VT restores TR but not its size. Useless.
1330 */
d359192f 1331 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1332 struct desc_struct *descs;
33ed6329 1333
d359192f 1334 descs = (void *)gdt->address;
33ed6329
AK		 1335 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1336 load_TR_desc();
33ed6329
AK		 1337}
1338
92c0d900 1339static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1340{
3a34a881 1341 u64 guest_efer;
51c6cf66
AK		 1342 u64 ignore_bits;
1343
f6801dff 1344 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1345
51c6cf66 1346 /*
0fa06071 1347 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1348 * outside long mode
1349 */
1350 ignore_bits = EFER_NX | EFER_SCE;
1351#ifdef CONFIG_X86_64
1352 ignore_bits |= EFER_LMA | EFER_LME;
1353 /* SCE is meaningful only in long mode on Intel */
1354 if (guest_efer & EFER_LMA)
1355 ignore_bits &= ~(u64)EFER_SCE;
1356#endif
51c6cf66
AK		 1357 guest_efer &= ~ignore_bits;
1358 guest_efer |= host_efer & ignore_bits;
26bb0981 1359 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1360 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1361
1362 clear_atomic_switch_msr(vmx, MSR_EFER);
1363 /* On ept, can't emulate nx, and must switch nx atomically */
1364 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1365 guest_efer = vmx->vcpu.arch.efer;
1366 if (!(guest_efer & EFER_LMA))
1367 guest_efer &= ~EFER_LME;
1368 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1369 return false;
1370 }
1371
26bb0981 1372 return true;
51c6cf66
AK		 1373}
1374
2d49ec72
GN		 1375static unsigned long segment_base(u16 selector)
1376{
d359192f 1377 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1378 struct desc_struct *d;
1379 unsigned long table_base;
1380 unsigned long v;
1381
1382 if (!(selector & ~3))
1383 return 0;
1384
d359192f 1385 table_base = gdt->address;
2d49ec72
GN		 1386
1387 if (selector & 4) { /* from ldt */
1388 u16 ldt_selector = kvm_read_ldt();
1389
1390 if (!(ldt_selector & ~3))
1391 return 0;
1392
1393 table_base = segment_base(ldt_selector);
1394 }
1395 d = (struct desc_struct *)(table_base + (selector & ~7));
1396 v = get_desc_base(d);
1397#ifdef CONFIG_X86_64
1398 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1399 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1400#endif
1401 return v;
1402}
1403
1404static inline unsigned long kvm_read_tr_base(void)
1405{
1406 u16 tr;
1407 asm("str %0" : "=g"(tr));
1408 return segment_base(tr);
1409}
1410
04d2cc77 1411static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1412{
04d2cc77 1413 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1414 int i;
04d2cc77 1415
a2fa3e9f 1416 if (vmx->host_state.loaded)
33ed6329
AK		 1417 return;
1418
a2fa3e9f 1419 vmx->host_state.loaded = 1;
33ed6329
AK		 1420 /*
1421 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1422 * allow segment selectors with cpl > 0 or ti == 1.
1423 */
d6e88aec 1424 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1425 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1426 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1427 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1428 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1429 vmx->host_state.fs_reload_needed = 0;
1430 } else {
33ed6329 1431 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1432 vmx->host_state.fs_reload_needed = 1;
33ed6329 1433 }
9581d442 1434 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1435 if (!(vmx->host_state.gs_sel & 7))
1436 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1437 else {
1438 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1439 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1440 }
1441
b2da15ac
AK		 1442#ifdef CONFIG_X86_64
1443 savesegment(ds, vmx->host_state.ds_sel);
1444 savesegment(es, vmx->host_state.es_sel);
1445#endif
1446
33ed6329
AK		 1447#ifdef CONFIG_X86_64
1448 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1449 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1450#else
a2fa3e9f
GH		 1451 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1452 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1453#endif
707c0874
AK		 1454
1455#ifdef CONFIG_X86_64
c8770e7b
AK		 1456 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1457 if (is_long_mode(&vmx->vcpu))
44ea2b17 1458 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1459#endif
26bb0981
AK		 1460 for (i = 0; i < vmx->save_nmsrs; ++i)
1461 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1462 vmx->guest_msrs[i].data,
1463 vmx->guest_msrs[i].mask);
33ed6329
AK		 1464}
1465
a9b21b62 1466static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1467{
a2fa3e9f 1468 if (!vmx->host_state.loaded)
33ed6329
AK		 1469 return;
1470
e1beb1d3 1471 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1472 vmx->host_state.loaded = 0;
c8770e7b
AK		 1473#ifdef CONFIG_X86_64
1474 if (is_long_mode(&vmx->vcpu))
1475 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1476#endif
152d3f2f 1477 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1478 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1479#ifdef CONFIG_X86_64
9581d442 1480 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1481#else
1482 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1483#endif
33ed6329 1484 }
0a77fe4c
AK		 1485 if (vmx->host_state.fs_reload_needed)
1486 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1487#ifdef CONFIG_X86_64
1488 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1489 loadsegment(ds, vmx->host_state.ds_sel);
1490 loadsegment(es, vmx->host_state.es_sel);
1491 }
b2da15ac 1492#endif
152d3f2f 1493 reload_tss();
44ea2b17 1494#ifdef CONFIG_X86_64
c8770e7b 1495 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1496#endif
b1a74bf8
SS		 1497 /*
1498 * If the FPU is not active (through the host task or
1499 * the guest vcpu), then restore the cr0.TS bit.
1500 */
1501 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1502 stts();
3444d7da 1503 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1504}
1505
a9b21b62
AK		 1506static void vmx_load_host_state(struct vcpu_vmx *vmx)
1507{
1508 preempt_disable();
1509 __vmx_load_host_state(vmx);
1510 preempt_enable();
1511}
1512
6aa8b732
AK		 1513/*
1514 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1515 * vcpu mutex is already taken.
1516 */
15ad7146 1517static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1518{
a2fa3e9f 1519 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1520 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1521
4610c9cc
DX		 1522 if (!vmm_exclusive)
1523 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1524 else if (vmx->loaded_vmcs->cpu != cpu)
1525 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1526
d462b819
NHE		 1527 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1528 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1529 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1530 }
1531
d462b819 1532 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1533 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1534 unsigned long sysenter_esp;
1535
a8eeb04a 1536 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1537 local_irq_disable();
d462b819
NHE		 1538 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1539 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1540 local_irq_enable();
1541
6aa8b732
AK		 1542 /*
1543 * Linux uses per-cpu TSS and GDT, so set these when switching
1544 * processors.
1545 */
d6e88aec 1546 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1547 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1548
1549 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1550 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1551 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1552 }
6aa8b732
AK		 1553}
1554
1555static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1556{
a9b21b62 1557 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1558 if (!vmm_exclusive) {
d462b819
NHE		 1559 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1560 vcpu->cpu = -1;
4610c9cc
DX		 1561 kvm_cpu_vmxoff();
1562 }
6aa8b732
AK		 1563}
1564
5fd86fcf
AK		 1565static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1566{
81231c69
AK		 1567 ulong cr0;
1568
5fd86fcf
AK		 1569 if (vcpu->fpu_active)
1570 return;
1571 vcpu->fpu_active = 1;
81231c69
AK		 1572 cr0 = vmcs_readl(GUEST_CR0);
1573 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1574 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1575 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1576 update_exception_bitmap(vcpu);
edcafe3c 1577 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1578 if (is_guest_mode(vcpu))
1579 vcpu->arch.cr0_guest_owned_bits &=
1580 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1581 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1582}
1583
edcafe3c
AK		 1584static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1585
fe3ef05c
NHE		 1586/*
1587 * Return the cr0 value that a nested guest would read. This is a combination
1588 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1589 * its hypervisor (cr0_read_shadow).
1590 */
1591static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1592{
1593 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1594 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1595}
1596static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1597{
1598 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1599 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1600}
1601
5fd86fcf
AK		 1602static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1603{
36cf24e0
NHE		 1604 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1605 * set this *before* calling this function.
1606 */
edcafe3c 1607 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1608 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1609 update_exception_bitmap(vcpu);
edcafe3c
AK		 1610 vcpu->arch.cr0_guest_owned_bits = 0;
1611 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1612 if (is_guest_mode(vcpu)) {
1613 /*
1614 * L1's specified read shadow might not contain the TS bit,
1615 * so now that we turned on shadowing of this bit, we need to
1616 * set this bit of the shadow. Like in nested_vmx_run we need
1617 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1618 * up-to-date here because we just decached cr0.TS (and we'll
1619 * only update vmcs12->guest_cr0 on nested exit).
1620 */
1621 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1622 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1623 (vcpu->arch.cr0 & X86_CR0_TS);
1624 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1625 } else
1626 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1627}
1628
6aa8b732
AK		 1629static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1630{
78ac8b47 1631 unsigned long rflags, save_rflags;
345dcaa8 1632
6de12732
AK		 1633 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1634 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1635 rflags = vmcs_readl(GUEST_RFLAGS);
1636 if (to_vmx(vcpu)->rmode.vm86_active) {
1637 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1638 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1639 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1640 }
1641 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1642 }
6de12732 1643 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1644}
1645
1646static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1647{
6de12732 1648 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1649 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1650 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1651 if (to_vmx(vcpu)->rmode.vm86_active) {
1652 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1653 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1654 }
6aa8b732
AK		 1655 vmcs_writel(GUEST_RFLAGS, rflags);
1656}
1657
2809f5d2
GC		 1658static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1659{
1660 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1661 int ret = 0;
1662
1663 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1664 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1665 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1666 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1667
1668 return ret & mask;
1669}
1670
1671static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1672{
1673 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1674 u32 interruptibility = interruptibility_old;
1675
1676 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1677
48005f64 1678 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1679 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1680 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1681 interruptibility |= GUEST_INTR_STATE_STI;
1682
1683 if ((interruptibility != interruptibility_old))
1684 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1685}
1686
6aa8b732
AK		 1687static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1688{
1689 unsigned long rip;
6aa8b732 1690
5fdbf976 1691 rip = kvm_rip_read(vcpu);
6aa8b732 1692 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1693 kvm_rip_write(vcpu, rip);
6aa8b732 1694
2809f5d2
GC		 1695 /* skipping an emulated instruction also counts */
1696 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1697}
1698
0b6ac343
NHE		 1699/*
1700 * KVM wants to inject page-faults which it got to the guest. This function
1701 * checks whether in a nested guest, we need to inject them to L1 or L2.
1702 * This function assumes it is called with the exit reason in vmcs02 being
1703 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1704 * is running).
1705 */
1706static int nested_pf_handled(struct kvm_vcpu *vcpu)
1707{
1708 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1709
1710 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1711 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1712 return 0;
1713
1714 nested_vmx_vmexit(vcpu);
1715 return 1;
1716}
1717
298101da 1718static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1719 bool has_error_code, u32 error_code,
1720 bool reinject)
298101da 1721{
77ab6db0 1722 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1723 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1724
0b6ac343
NHE		 1725 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1726 nested_pf_handled(vcpu))
1727 return;
1728
8ab2d2e2 1729 if (has_error_code) {
77ab6db0 1730 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1731 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1732 }
77ab6db0 1733
7ffd92c5 1734 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1735 int inc_eip = 0;
1736 if (kvm_exception_is_soft(nr))
1737 inc_eip = vcpu->arch.event_exit_inst_len;
1738 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1739 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1740 return;
1741 }
1742
66fd3f7f
GN		 1743 if (kvm_exception_is_soft(nr)) {
1744 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1745 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1746 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1747 } else
1748 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1749
1750 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1751}
1752
4e47c7a6
SY		 1753static bool vmx_rdtscp_supported(void)
1754{
1755 return cpu_has_vmx_rdtscp();
1756}
1757
ad756a16
MJ		 1758static bool vmx_invpcid_supported(void)
1759{
1760 return cpu_has_vmx_invpcid() && enable_ept;
1761}
1762
a75beee6
ED		 1763/*
1764 * Swap MSR entry in host/guest MSR entry array.
1765 */
8b9cf98c 1766static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1767{
26bb0981 1768 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1769
1770 tmp = vmx->guest_msrs[to];
1771 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1772 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1773}
1774
e38aea3e
AK		 1775/*
1776 * Set up the vmcs to automatically save and restore system
1777 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1778 * mode, as fiddling with msrs is very expensive.
1779 */
8b9cf98c 1780static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1781{
26bb0981 1782 int save_nmsrs, index;
5897297b 1783 unsigned long *msr_bitmap;
e38aea3e 1784
a75beee6
ED		 1785 save_nmsrs = 0;
1786#ifdef CONFIG_X86_64
8b9cf98c 1787 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1788 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1789 if (index >= 0)
8b9cf98c
RR		 1790 move_msr_up(vmx, index, save_nmsrs++);
1791 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1792 if (index >= 0)
8b9cf98c
RR		 1793 move_msr_up(vmx, index, save_nmsrs++);
1794 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1795 if (index >= 0)
8b9cf98c 1796 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1797 index = __find_msr_index(vmx, MSR_TSC_AUX);
1798 if (index >= 0 && vmx->rdtscp_enabled)
1799 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1800 /*
8c06585d 1801 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1802 * if efer.sce is enabled.
1803 */
8c06585d 1804 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1805 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1806 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1807 }
1808#endif
92c0d900
AK		 1809 index = __find_msr_index(vmx, MSR_EFER);
1810 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1811 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1812
26bb0981 1813 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1814
1815 if (cpu_has_vmx_msr_bitmap()) {
1816 if (is_long_mode(&vmx->vcpu))
1817 msr_bitmap = vmx_msr_bitmap_longmode;
1818 else
1819 msr_bitmap = vmx_msr_bitmap_legacy;
1820
1821 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1822 }
e38aea3e
AK		 1823}
1824
6aa8b732
AK		 1825/*
1826 * reads and returns guest's timestamp counter "register"
1827 * guest_tsc = host_tsc + tsc_offset -- 21.3
1828 */
1829static u64 guest_read_tsc(void)
1830{
1831 u64 host_tsc, tsc_offset;
1832
1833 rdtscll(host_tsc);
1834 tsc_offset = vmcs_read64(TSC_OFFSET);
1835 return host_tsc + tsc_offset;
1836}
1837
d5c1785d
NHE		 1838/*
1839 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1840 * counter, even if a nested guest (L2) is currently running.
1841 */
1842u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1843{
1844 u64 host_tsc, tsc_offset;
1845
1846 rdtscll(host_tsc);
1847 tsc_offset = is_guest_mode(vcpu) ?
1848 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1849 vmcs_read64(TSC_OFFSET);
1850 return host_tsc + tsc_offset;
1851}
1852
4051b188 1853/*
cc578287
ZA		 1854 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1855 * software catchup for faster rates on slower CPUs.
4051b188 1856 */
cc578287 1857static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1858{
cc578287
ZA		 1859 if (!scale)
1860 return;
1861
1862 if (user_tsc_khz > tsc_khz) {
1863 vcpu->arch.tsc_catchup = 1;
1864 vcpu->arch.tsc_always_catchup = 1;
1865 } else
1866 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1867}
1868
6aa8b732 1869/*
99e3e30a 1870 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1871 */
99e3e30a 1872static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1873{
27fc51b2 1874 if (is_guest_mode(vcpu)) {
7991825b 1875 /*
27fc51b2
NHE		 1876 * We're here if L1 chose not to trap WRMSR to TSC. According
1877 * to the spec, this should set L1's TSC; The offset that L1
1878 * set for L2 remains unchanged, and still needs to be added
1879 * to the newly set TSC to get L2's TSC.
7991825b 1880 */
27fc51b2
NHE		 1881 struct vmcs12 *vmcs12;
1882 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1883 /* recalculate vmcs02.TSC_OFFSET: */
1884 vmcs12 = get_vmcs12(vcpu);
1885 vmcs_write64(TSC_OFFSET, offset +
1886 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1887 vmcs12->tsc_offset : 0));
1888 } else {
1889 vmcs_write64(TSC_OFFSET, offset);
1890 }
6aa8b732
AK		 1891}
1892
f1e2b260 1893static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1894{
1895 u64 offset = vmcs_read64(TSC_OFFSET);
1896 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1897 if (is_guest_mode(vcpu)) {
1898 /* Even when running L2, the adjustment needs to apply to L1 */
1899 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1900 }
e48672fa
ZA		 1901}
1902
857e4099
JR		 1903static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1904{
1905 return target_tsc - native_read_tsc();
1906}
1907
801d3424
NHE		 1908static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1909{
1910 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1911 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1912}
1913
1914/*
1915 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1916 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1917 * all guests if the "nested" module option is off, and can also be disabled
1918 * for a single guest by disabling its VMX cpuid bit.
1919 */
1920static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1921{
1922 return nested && guest_cpuid_has_vmx(vcpu);
1923}
1924
b87a51ae
NHE		 1925/*
1926 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1927 * returned for the various VMX controls MSRs when nested VMX is enabled.
1928 * The same values should also be used to verify that vmcs12 control fields are
1929 * valid during nested entry from L1 to L2.
1930 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1931 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1932 * bit in the high half is on if the corresponding bit in the control field
1933 * may be on. See also vmx_control_verify().
1934 * TODO: allow these variables to be modified (downgraded) by module options
1935 * or other means.
1936 */
1937static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1938static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1939static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1940static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1941static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1942static __init void nested_vmx_setup_ctls_msrs(void)
1943{
1944 /*
1945 * Note that as a general rule, the high half of the MSRs (bits in
1946 * the control fields which may be 1) should be initialized by the
1947 * intersection of the underlying hardware's MSR (i.e., features which
1948 * can be supported) and the list of features we want to expose -
1949 * because they are known to be properly supported in our code.
1950 * Also, usually, the low half of the MSRs (bits which must be 1) can
1951 * be set to 0, meaning that L1 may turn off any of these bits. The
1952 * reason is that if one of these bits is necessary, it will appear
1953 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1954 * fields of vmcs01 and vmcs02, will turn these bits off - and
1955 * nested_vmx_exit_handled() will not pass related exits to L1.
1956 * These rules have exceptions below.
1957 */
1958
1959 /* pin-based controls */
1960 /*
1961 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1962 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1963 */
1964 nested_vmx_pinbased_ctls_low = 0x16 ;
1965 nested_vmx_pinbased_ctls_high = 0x16 |
1966 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1967 PIN_BASED_VIRTUAL_NMIS;
1968
1969 /* exit controls */
1970 nested_vmx_exit_ctls_low = 0;
b6f1250e 1971 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1972#ifdef CONFIG_X86_64
1973 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1974#else
1975 nested_vmx_exit_ctls_high = 0;
1976#endif
1977
1978 /* entry controls */
1979 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1980 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1981 nested_vmx_entry_ctls_low = 0;
1982 nested_vmx_entry_ctls_high &=
1983 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1984
1985 /* cpu-based controls */
1986 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1987 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1988 nested_vmx_procbased_ctls_low = 0;
1989 nested_vmx_procbased_ctls_high &=
1990 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1991 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1992 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1993 CPU_BASED_CR3_STORE_EXITING |
1994#ifdef CONFIG_X86_64
1995 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1996#endif
1997 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1998 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 1999 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2000 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2001 /*
2002 * We can allow some features even when not supported by the
2003 * hardware. For example, L1 can specify an MSR bitmap - and we
2004 * can use it to avoid exits to L1 - even when L0 runs L2
2005 * without MSR bitmaps.
2006 */
2007 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2008
2009 /* secondary cpu-based controls */
2010 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2011 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2012 nested_vmx_secondary_ctls_low = 0;
2013 nested_vmx_secondary_ctls_high &=
2014 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2015}
2016
2017static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2018{
2019 /*
2020 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2021 */
2022 return ((control & high) | low) == control;
2023}
2024
2025static inline u64 vmx_control_msr(u32 low, u32 high)
2026{
2027 return low | ((u64)high << 32);
2028}
2029
2030/*
2031 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2032 * also let it use VMX-specific MSRs.
2033 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2034 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2035 * like all other MSRs).
2036 */
2037static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2038{
2039 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2040 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2041 /*
2042 * According to the spec, processors which do not support VMX
2043 * should throw a #GP(0) when VMX capability MSRs are read.
2044 */
2045 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2046 return 1;
2047 }
2048
2049 switch (msr_index) {
2050 case MSR_IA32_FEATURE_CONTROL:
2051 *pdata = 0;
2052 break;
2053 case MSR_IA32_VMX_BASIC:
2054 /*
2055 * This MSR reports some information about VMX support. We
2056 * should return information about the VMX we emulate for the
2057 * guest, and the VMCS structure we give it - not about the
2058 * VMX support of the underlying hardware.
2059 */
2060 *pdata = VMCS12_REVISION |
2061 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2062 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2063 break;
2064 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2065 case MSR_IA32_VMX_PINBASED_CTLS:
2066 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2067 nested_vmx_pinbased_ctls_high);
2068 break;
2069 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2070 case MSR_IA32_VMX_PROCBASED_CTLS:
2071 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2072 nested_vmx_procbased_ctls_high);
2073 break;
2074 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2075 case MSR_IA32_VMX_EXIT_CTLS:
2076 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2077 nested_vmx_exit_ctls_high);
2078 break;
2079 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2080 case MSR_IA32_VMX_ENTRY_CTLS:
2081 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2082 nested_vmx_entry_ctls_high);
2083 break;
2084 case MSR_IA32_VMX_MISC:
2085 *pdata = 0;
2086 break;
2087 /*
2088 * These MSRs specify bits which the guest must keep fixed (on or off)
2089 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2090 * We picked the standard core2 setting.
2091 */
2092#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2093#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2094 case MSR_IA32_VMX_CR0_FIXED0:
2095 *pdata = VMXON_CR0_ALWAYSON;
2096 break;
2097 case MSR_IA32_VMX_CR0_FIXED1:
2098 *pdata = -1ULL;
2099 break;
2100 case MSR_IA32_VMX_CR4_FIXED0:
2101 *pdata = VMXON_CR4_ALWAYSON;
2102 break;
2103 case MSR_IA32_VMX_CR4_FIXED1:
2104 *pdata = -1ULL;
2105 break;
2106 case MSR_IA32_VMX_VMCS_ENUM:
2107 *pdata = 0x1f;
2108 break;
2109 case MSR_IA32_VMX_PROCBASED_CTLS2:
2110 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2111 nested_vmx_secondary_ctls_high);
2112 break;
2113 case MSR_IA32_VMX_EPT_VPID_CAP:
2114 /* Currently, no nested ept or nested vpid */
2115 *pdata = 0;
2116 break;
2117 default:
2118 return 0;
2119 }
2120
2121 return 1;
2122}
2123
2124static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2125{
2126 if (!nested_vmx_allowed(vcpu))
2127 return 0;
2128
2129 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2130 /* TODO: the right thing. */
2131 return 1;
2132 /*
2133 * No need to treat VMX capability MSRs specially: If we don't handle
2134 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2135 */
2136 return 0;
2137}
2138
6aa8b732
AK		 2139/*
2140 * Reads an msr value (of 'msr_index') into 'pdata'.
2141 * Returns 0 on success, non-0 otherwise.
2142 * Assumes vcpu_load() was already called.
2143 */
2144static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2145{
2146 u64 data;
26bb0981 2147 struct shared_msr_entry *msr;
6aa8b732
AK		 2148
2149 if (!pdata) {
2150 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2151 return -EINVAL;
2152 }
2153
2154 switch (msr_index) {
05b3e0c2 2155#ifdef CONFIG_X86_64
6aa8b732
AK		 2156 case MSR_FS_BASE:
2157 data = vmcs_readl(GUEST_FS_BASE);
2158 break;
2159 case MSR_GS_BASE:
2160 data = vmcs_readl(GUEST_GS_BASE);
2161 break;
44ea2b17
AK		 2162 case MSR_KERNEL_GS_BASE:
2163 vmx_load_host_state(to_vmx(vcpu));
2164 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2165 break;
26bb0981 2166#endif
6aa8b732 2167 case MSR_EFER:
3bab1f5d 2168 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2169 case MSR_IA32_TSC:
6aa8b732
AK		 2170 data = guest_read_tsc();
2171 break;
2172 case MSR_IA32_SYSENTER_CS:
2173 data = vmcs_read32(GUEST_SYSENTER_CS);
2174 break;
2175 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2176 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2177 break;
2178 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2179 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2180 break;
4e47c7a6
SY		 2181 case MSR_TSC_AUX:
2182 if (!to_vmx(vcpu)->rdtscp_enabled)
2183 return 1;
2184 /* Otherwise falls through */
6aa8b732 2185 default:
b87a51ae
NHE		 2186 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2187 return 0;
8b9cf98c 2188 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2189 if (msr) {
2190 data = msr->data;
2191 break;
6aa8b732 2192 }
3bab1f5d 2193 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2194 }
2195
2196 *pdata = data;
2197 return 0;
2198}
2199
2200/*
2201 * Writes msr value into into the appropriate "register".
2202 * Returns 0 on success, non-0 otherwise.
2203 * Assumes vcpu_load() was already called.
2204 */
2205static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2206{
a2fa3e9f 2207 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2208 struct shared_msr_entry *msr;
2cc51560
ED		 2209 int ret = 0;
2210
6aa8b732 2211 switch (msr_index) {
3bab1f5d 2212 case MSR_EFER:
2cc51560 2213 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2214 break;
16175a79 2215#ifdef CONFIG_X86_64
6aa8b732 2216 case MSR_FS_BASE:
2fb92db1 2217 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2218 vmcs_writel(GUEST_FS_BASE, data);
2219 break;
2220 case MSR_GS_BASE:
2fb92db1 2221 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2222 vmcs_writel(GUEST_GS_BASE, data);
2223 break;
44ea2b17
AK		 2224 case MSR_KERNEL_GS_BASE:
2225 vmx_load_host_state(vmx);
2226 vmx->msr_guest_kernel_gs_base = data;
2227 break;
6aa8b732
AK		 2228#endif
2229 case MSR_IA32_SYSENTER_CS:
2230 vmcs_write32(GUEST_SYSENTER_CS, data);
2231 break;
2232 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2233 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2234 break;
2235 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2236 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2237 break;
af24a4e4 2238 case MSR_IA32_TSC:
99e3e30a 2239 kvm_write_tsc(vcpu, data);
6aa8b732 2240 break;
468d472f
SY		 2241 case MSR_IA32_CR_PAT:
2242 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2243 vmcs_write64(GUEST_IA32_PAT, data);
2244 vcpu->arch.pat = data;
2245 break;
2246 }
4e47c7a6
SY		 2247 ret = kvm_set_msr_common(vcpu, msr_index, data);
2248 break;
2249 case MSR_TSC_AUX:
2250 if (!vmx->rdtscp_enabled)
2251 return 1;
2252 /* Check reserved bit, higher 32 bits should be zero */
2253 if ((data >> 32) != 0)
2254 return 1;
2255 /* Otherwise falls through */
6aa8b732 2256 default:
b87a51ae
NHE		 2257 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2258 break;
8b9cf98c 2259 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2260 if (msr) {
2261 msr->data = data;
2225fd56
AK		 2262 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2263 preempt_disable();
9ee73970
AK		 2264 kvm_set_shared_msr(msr->index, msr->data,
2265 msr->mask);
2225fd56
AK		 2266 preempt_enable();
2267 }
3bab1f5d 2268 break;
6aa8b732 2269 }
2cc51560 2270 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2271 }
2272
2cc51560 2273 return ret;
6aa8b732
AK		 2274}
2275
5fdbf976 2276static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2277{
5fdbf976
MT		 2278 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2279 switch (reg) {
2280 case VCPU_REGS_RSP:
2281 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2282 break;
2283 case VCPU_REGS_RIP:
2284 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2285 break;
6de4f3ad
AK		 2286 case VCPU_EXREG_PDPTR:
2287 if (enable_ept)
2288 ept_save_pdptrs(vcpu);
2289 break;
5fdbf976
MT		 2290 default:
2291 break;
2292 }
6aa8b732
AK		 2293}
2294
6aa8b732
AK		 2295static __init int cpu_has_kvm_support(void)
2296{
6210e37b 2297 return cpu_has_vmx();
6aa8b732
AK		 2298}
2299
2300static __init int vmx_disabled_by_bios(void)
2301{
2302 u64 msr;
2303
2304 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2305 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2306 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2307 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2308 && tboot_enabled())
2309 return 1;
23f3e991 2310 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2311 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2312 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2313 && !tboot_enabled()) {
2314 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2315 "activate TXT before enabling KVM\n");
cafd6659 2316 return 1;
f9335afe 2317 }
23f3e991
JC		 2318 /* launched w/o TXT and VMX disabled */
2319 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2320 && !tboot_enabled())
2321 return 1;
cafd6659
SW		 2322 }
2323
2324 return 0;
6aa8b732
AK		 2325}
2326
7725b894
DX		 2327static void kvm_cpu_vmxon(u64 addr)
2328{
2329 asm volatile (ASM_VMX_VMXON_RAX
2330 : : "a"(&addr), "m"(addr)
2331 : "memory", "cc");
2332}
2333
10474ae8 2334static int hardware_enable(void *garbage)
6aa8b732
AK		 2335{
2336 int cpu = raw_smp_processor_id();
2337 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2338 u64 old, test_bits;
6aa8b732 2339
10474ae8
AG		 2340 if (read_cr4() & X86_CR4_VMXE)
2341 return -EBUSY;
2342
d462b819 2343 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2344 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2345
2346 test_bits = FEATURE_CONTROL_LOCKED;
2347 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2348 if (tboot_enabled())
2349 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2350
2351 if ((old & test_bits) != test_bits) {
6aa8b732 2352 /* enable and lock */
cafd6659
SW		 2353 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2354 }
66aee91a 2355 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2356
4610c9cc
DX		 2357 if (vmm_exclusive) {
2358 kvm_cpu_vmxon(phys_addr);
2359 ept_sync_global();
2360 }
10474ae8 2361
3444d7da
AK		 2362 store_gdt(&__get_cpu_var(host_gdt));
2363
10474ae8 2364 return 0;
6aa8b732
AK		 2365}
2366
d462b819 2367static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2368{
2369 int cpu = raw_smp_processor_id();
d462b819 2370 struct loaded_vmcs *v, *n;
543e4243 2371
d462b819
NHE		 2372 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2373 loaded_vmcss_on_cpu_link)
2374 __loaded_vmcs_clear(v);
543e4243
AK		 2375}
2376
710ff4a8
EH		 2377
2378/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2379 * tricks.
2380 */
2381static void kvm_cpu_vmxoff(void)
6aa8b732 2382{
4ecac3fd 2383 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2384}
2385
710ff4a8
EH		 2386static void hardware_disable(void *garbage)
2387{
4610c9cc 2388 if (vmm_exclusive) {
d462b819 2389 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2390 kvm_cpu_vmxoff();
2391 }
7725b894 2392 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2393}
2394
1c3d14fe 2395static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2396 u32 msr, u32 *result)
1c3d14fe
YS		 2397{
2398 u32 vmx_msr_low, vmx_msr_high;
2399 u32 ctl = ctl_min | ctl_opt;
2400
2401 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2402
2403 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2404 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2405
2406 /* Ensure minimum (required) set of control bits are supported. */
2407 if (ctl_min & ~ctl)
002c7f7c 2408 return -EIO;
1c3d14fe
YS		 2409
2410 *result = ctl;
2411 return 0;
2412}
2413
110312c8
AK		 2414static __init bool allow_1_setting(u32 msr, u32 ctl)
2415{
2416 u32 vmx_msr_low, vmx_msr_high;
2417
2418 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2419 return vmx_msr_high & ctl;
2420}
2421
002c7f7c 2422static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2423{
2424 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2425 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2426 u32 _pin_based_exec_control = 0;
2427 u32 _cpu_based_exec_control = 0;
f78e0e2e 2428 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2429 u32 _vmexit_control = 0;
2430 u32 _vmentry_control = 0;
2431
2432 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2433 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2434 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2435 &_pin_based_exec_control) < 0)
002c7f7c 2436 return -EIO;
1c3d14fe 2437
10166744 2438 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2439#ifdef CONFIG_X86_64
2440 CPU_BASED_CR8_LOAD_EXITING |
2441 CPU_BASED_CR8_STORE_EXITING |
2442#endif
d56f546d
SY		 2443 CPU_BASED_CR3_LOAD_EXITING |
2444 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2445 CPU_BASED_USE_IO_BITMAPS |
2446 CPU_BASED_MOV_DR_EXITING |
a7052897 2447 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2448 CPU_BASED_MWAIT_EXITING |
2449 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2450 CPU_BASED_INVLPG_EXITING |
2451 CPU_BASED_RDPMC_EXITING;
443381a8 2452
f78e0e2e 2453 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2454 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2455 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2456 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2457 &_cpu_based_exec_control) < 0)
002c7f7c 2458 return -EIO;
6e5d865c
YS		 2459#ifdef CONFIG_X86_64
2460 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2461 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2462 ~CPU_BASED_CR8_STORE_EXITING;
2463#endif
f78e0e2e 2464 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2465 min2 = 0;
2466 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2467 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2468 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2469 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2470 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2471 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2472 SECONDARY_EXEC_RDTSCP |
2473 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2474 if (adjust_vmx_controls(min2, opt2,
2475 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2476 &_cpu_based_2nd_exec_control) < 0)
2477 return -EIO;
2478 }
2479#ifndef CONFIG_X86_64
2480 if (!(_cpu_based_2nd_exec_control &
2481 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2482 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2483#endif
d56f546d 2484 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2485 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2486 enabled */
5fff7d27
GN		 2487 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2488 CPU_BASED_CR3_STORE_EXITING |
2489 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2490 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2491 vmx_capability.ept, vmx_capability.vpid);
2492 }
1c3d14fe
YS		 2493
2494 min = 0;
2495#ifdef CONFIG_X86_64
2496 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2497#endif
468d472f 2498 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2499 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500 &_vmexit_control) < 0)
002c7f7c 2501 return -EIO;
1c3d14fe 2502
468d472f
SY		 2503 min = 0;
2504 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2505 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2506 &_vmentry_control) < 0)
002c7f7c 2507 return -EIO;
6aa8b732 2508
c68876fd 2509 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2510
2511 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2512 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2513 return -EIO;
1c3d14fe
YS		 2514
2515#ifdef CONFIG_X86_64
2516 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2517 if (vmx_msr_high & (1u<<16))
002c7f7c 2518 return -EIO;
1c3d14fe
YS		 2519#endif
2520
2521 /* Require Write-Back (WB) memory type for VMCS accesses. */
2522 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2523 return -EIO;
1c3d14fe 2524
002c7f7c
YS		 2525 vmcs_conf->size = vmx_msr_high & 0x1fff;
2526 vmcs_conf->order = get_order(vmcs_config.size);
2527 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2528
002c7f7c
YS		 2529 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2530 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2531 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2532 vmcs_conf->vmexit_ctrl = _vmexit_control;
2533 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2534
110312c8
AK		 2535 cpu_has_load_ia32_efer =
2536 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2537 VM_ENTRY_LOAD_IA32_EFER)
2538 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2539 VM_EXIT_LOAD_IA32_EFER);
2540
8bf00a52
GN		 2541 cpu_has_load_perf_global_ctrl =
2542 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2543 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2544 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2545 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2546
2547 /*
2548 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2549 * but due to arrata below it can't be used. Workaround is to use
2550 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2551 *
2552 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2553 *
2554 * AAK155 (model 26)
2555 * AAP115 (model 30)
2556 * AAT100 (model 37)
2557 * BC86,AAY89,BD102 (model 44)
2558 * BA97 (model 46)
2559 *
2560 */
2561 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2562 switch (boot_cpu_data.x86_model) {
2563 case 26:
2564 case 30:
2565 case 37:
2566 case 44:
2567 case 46:
2568 cpu_has_load_perf_global_ctrl = false;
2569 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2570 "does not work properly. Using workaround\n");
2571 break;
2572 default:
2573 break;
2574 }
2575 }
2576
1c3d14fe 2577 return 0;
c68876fd 2578}
6aa8b732
AK		 2579
2580static struct vmcs *alloc_vmcs_cpu(int cpu)
2581{
2582 int node = cpu_to_node(cpu);
2583 struct page *pages;
2584 struct vmcs *vmcs;
2585
6484eb3e 2586 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2587 if (!pages)
2588 return NULL;
2589 vmcs = page_address(pages);
1c3d14fe
YS		 2590 memset(vmcs, 0, vmcs_config.size);
2591 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2592 return vmcs;
2593}
2594
2595static struct vmcs *alloc_vmcs(void)
2596{
d3b2c338 2597 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2598}
2599
2600static void free_vmcs(struct vmcs *vmcs)
2601{
1c3d14fe 2602 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2603}
2604
d462b819
NHE		 2605/*
2606 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2607 */
2608static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2609{
2610 if (!loaded_vmcs->vmcs)
2611 return;
2612 loaded_vmcs_clear(loaded_vmcs);
2613 free_vmcs(loaded_vmcs->vmcs);
2614 loaded_vmcs->vmcs = NULL;
2615}
2616
39959588 2617static void free_kvm_area(void)
6aa8b732
AK		 2618{
2619 int cpu;
2620
3230bb47 2621 for_each_possible_cpu(cpu) {
6aa8b732 2622 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2623 per_cpu(vmxarea, cpu) = NULL;
2624 }
6aa8b732
AK		 2625}
2626
6aa8b732
AK		 2627static __init int alloc_kvm_area(void)
2628{
2629 int cpu;
2630
3230bb47 2631 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2632 struct vmcs *vmcs;
2633
2634 vmcs = alloc_vmcs_cpu(cpu);
2635 if (!vmcs) {
2636 free_kvm_area();
2637 return -ENOMEM;
2638 }
2639
2640 per_cpu(vmxarea, cpu) = vmcs;
2641 }
2642 return 0;
2643}
2644
2645static __init int hardware_setup(void)
2646{
002c7f7c
YS		 2647 if (setup_vmcs_config(&vmcs_config) < 0)
2648 return -EIO;
50a37eb4
JR		 2649
2650 if (boot_cpu_has(X86_FEATURE_NX))
2651 kvm_enable_efer_bits(EFER_NX);
2652
93ba03c2
SY		 2653 if (!cpu_has_vmx_vpid())
2654 enable_vpid = 0;
2655
4bc9b982
SY		 2656 if (!cpu_has_vmx_ept() ||
2657 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2658 enable_ept = 0;
3a624e29 2659 enable_unrestricted_guest = 0;
83c3a331 2660 enable_ept_ad_bits = 0;
3a624e29
NK		 2661 }
2662
83c3a331
XH		 2663 if (!cpu_has_vmx_ept_ad_bits())
2664 enable_ept_ad_bits = 0;
2665
3a624e29
NK		 2666 if (!cpu_has_vmx_unrestricted_guest())
2667 enable_unrestricted_guest = 0;
93ba03c2
SY		 2668
2669 if (!cpu_has_vmx_flexpriority())
2670 flexpriority_enabled = 0;
2671
95ba8273
GN		 2672 if (!cpu_has_vmx_tpr_shadow())
2673 kvm_x86_ops->update_cr8_intercept = NULL;
2674
54dee993
MT		 2675 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2676 kvm_disable_largepages();
2677
4b8d54f9
ZE		 2678 if (!cpu_has_vmx_ple())
2679 ple_gap = 0;
2680
b87a51ae
NHE		 2681 if (nested)
2682 nested_vmx_setup_ctls_msrs();
2683
6aa8b732
AK		 2684 return alloc_kvm_area();
2685}
2686
2687static __exit void hardware_unsetup(void)
2688{
2689 free_kvm_area();
2690}
2691
f5f7b2fe 2692static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
6aa8b732 2693{
772e0318 2694 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
c865c43d 2695 struct kvm_segment tmp = *save;
6aa8b732 2696
c865c43d
AK		 2697 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2698 tmp.base = vmcs_readl(sf->base);
2699 tmp.selector = vmcs_read16(sf->selector);
2700 tmp.s = 1;
6aa8b732 2701 }
c865c43d 2702 vmx_set_segment(vcpu, &tmp, seg);
6aa8b732
AK		 2703}
2704
2705static void enter_pmode(struct kvm_vcpu *vcpu)
2706{
2707 unsigned long flags;
a89a8fb9 2708 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2709
a89a8fb9 2710 vmx->emulation_required = 1;
7ffd92c5 2711 vmx->rmode.vm86_active = 0;
6aa8b732 2712
2fb92db1
AK		 2713 vmx_segment_cache_clear(vmx);
2714
f5f7b2fe 2715 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2716
2717 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2718 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2719 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2720 vmcs_writel(GUEST_RFLAGS, flags);
2721
66aee91a
RR		 2722 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2723 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2724
2725 update_exception_bitmap(vcpu);
2726
a89a8fb9
MG		 2727 if (emulate_invalid_guest_state)
2728 return;
2729
f5f7b2fe
AK		 2730 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2731 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2732 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2733 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732 2734
2fb92db1
AK		 2735 vmx_segment_cache_clear(vmx);
2736
6aa8b732
AK		 2737 vmcs_write16(GUEST_SS_SELECTOR, 0);
2738 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2739
2740 vmcs_write16(GUEST_CS_SELECTOR,
2741 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2742 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2743}
2744
d77c26fc 2745static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2746{
bfc6d222 2747 if (!kvm->arch.tss_addr) {
bc6678a3 2748 struct kvm_memslots *slots;
28a37544 2749 struct kvm_memory_slot *slot;
bc6678a3
MT		 2750 gfn_t base_gfn;
2751
90d83dc3 2752 slots = kvm_memslots(kvm);
28a37544
XG		 2753 slot = id_to_memslot(slots, 0);
2754 base_gfn = slot->base_gfn + slot->npages - 3;
2755
cbc94022
IE		 2756 return base_gfn << PAGE_SHIFT;
2757 }
bfc6d222 2758 return kvm->arch.tss_addr;
6aa8b732
AK		 2759}
2760
f5f7b2fe 2761static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2762{
772e0318 2763 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
6aa8b732 2764
15b00f32 2765 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2766 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2767 vmcs_write32(sf->limit, 0xffff);
2768 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2769 if (save->base & 0xf)
2770 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2771 " aligned when entering protected mode (seg=%d)",
2772 seg);
6aa8b732
AK		 2773}
2774
2775static void enter_rmode(struct kvm_vcpu *vcpu)
2776{
2777 unsigned long flags;
a89a8fb9 2778 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2779 struct kvm_segment var;
6aa8b732 2780
3a624e29
NK		 2781 if (enable_unrestricted_guest)
2782 return;
2783
f5f7b2fe
AK		 2784 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2785 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2786 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2787 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2788 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2789
a89a8fb9 2790 vmx->emulation_required = 1;
7ffd92c5 2791 vmx->rmode.vm86_active = 1;
6aa8b732 2792
baa7e81e 2793
776e58ea
GN		 2794 /*
2795 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2796 * vcpu. Call it here with phys address pointing 16M below 4G.
2797 */
2798 if (!vcpu->kvm->arch.tss_addr) {
2799 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2800 "called before entering vcpu\n");
2801 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2802 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2803 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2804 }
2805
2fb92db1
AK		 2806 vmx_segment_cache_clear(vmx);
2807
6aa8b732 2808 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2809 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2810 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2811
2812 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2813 vmx->rmode.save_rflags = flags;
6aa8b732 2814
053de044 2815 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2816
2817 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2818 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2819 update_exception_bitmap(vcpu);
2820
a89a8fb9
MG		 2821 if (emulate_invalid_guest_state)
2822 goto continue_rmode;
2823
b246dd5d
OW		 2824 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2825 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2826
2827 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2828 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2829
2830 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2831 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2832
2833 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2834 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2835
b246dd5d
OW		 2836 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2837 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2838
b246dd5d
OW		 2839 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2840 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2841
a89a8fb9 2842continue_rmode:
8668a3c4 2843 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2844}
2845
401d10de
AS		 2846static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2847{
2848 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2849 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2850
2851 if (!msr)
2852 return;
401d10de 2853
44ea2b17
AK		 2854 /*
2855 * Force kernel_gs_base reloading before EFER changes, as control
2856 * of this msr depends on is_long_mode().
2857 */
2858 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2859 vcpu->arch.efer = efer;
401d10de
AS		 2860 if (efer & EFER_LMA) {
2861 vmcs_write32(VM_ENTRY_CONTROLS,
2862 vmcs_read32(VM_ENTRY_CONTROLS) |
2863 VM_ENTRY_IA32E_MODE);
2864 msr->data = efer;
2865 } else {
2866 vmcs_write32(VM_ENTRY_CONTROLS,
2867 vmcs_read32(VM_ENTRY_CONTROLS) &
2868 ~VM_ENTRY_IA32E_MODE);
2869
2870 msr->data = efer & ~EFER_LME;
2871 }
2872 setup_msrs(vmx);
2873}
2874
05b3e0c2 2875#ifdef CONFIG_X86_64
6aa8b732
AK		 2876
2877static void enter_lmode(struct kvm_vcpu *vcpu)
2878{
2879 u32 guest_tr_ar;
2880
2fb92db1
AK		 2881 vmx_segment_cache_clear(to_vmx(vcpu));
2882
6aa8b732
AK		 2883 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2884 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2885 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2886 __func__);
6aa8b732
AK		 2887 vmcs_write32(GUEST_TR_AR_BYTES,
2888 (guest_tr_ar & ~AR_TYPE_MASK)
2889 | AR_TYPE_BUSY_64_TSS);
2890 }
da38f438 2891 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2892}
2893
2894static void exit_lmode(struct kvm_vcpu *vcpu)
2895{
6aa8b732
AK		 2896 vmcs_write32(VM_ENTRY_CONTROLS,
2897 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2898 & ~VM_ENTRY_IA32E_MODE);
da38f438 2899 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2900}
2901
2902#endif
2903
2384d2b3
SY		 2904static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2905{
b9d762fa 2906 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2907 if (enable_ept) {
2908 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2909 return;
4e1096d2 2910 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2911 }
2384d2b3
SY		 2912}
2913
e8467fda
AK		 2914static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2915{
2916 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2917
2918 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2919 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2920}
2921
aff48baa
AK		 2922static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2923{
2924 if (enable_ept && is_paging(vcpu))
2925 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2926 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2927}
2928
25c4c276 2929static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2930{
fc78f519
AK		 2931 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2932
2933 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2934 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2935}
2936
1439442c
SY		 2937static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2938{
6de4f3ad
AK		 2939 if (!test_bit(VCPU_EXREG_PDPTR,
2940 (unsigned long *)&vcpu->arch.regs_dirty))
2941 return;
2942
1439442c 2943 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2944 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2945 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2946 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2947 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2948 }
2949}
2950
8f5d549f
AK		 2951static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2952{
2953 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2954 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2955 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2956 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2957 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2958 }
6de4f3ad
AK		 2959
2960 __set_bit(VCPU_EXREG_PDPTR,
2961 (unsigned long *)&vcpu->arch.regs_avail);
2962 __set_bit(VCPU_EXREG_PDPTR,
2963 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2964}
2965
5e1746d6 2966static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2967
2968static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2969 unsigned long cr0,
2970 struct kvm_vcpu *vcpu)
2971{
5233dd51
MT		 2972 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2973 vmx_decache_cr3(vcpu);
1439442c
SY		 2974 if (!(cr0 & X86_CR0_PG)) {
2975 /* From paging/starting to nonpaging */
2976 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2977 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2978 (CPU_BASED_CR3_LOAD_EXITING |
2979 CPU_BASED_CR3_STORE_EXITING));
2980 vcpu->arch.cr0 = cr0;
fc78f519 2981 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2982 } else if (!is_paging(vcpu)) {
2983 /* From nonpaging to paging */
2984 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2985 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2986 ~(CPU_BASED_CR3_LOAD_EXITING |
2987 CPU_BASED_CR3_STORE_EXITING));
2988 vcpu->arch.cr0 = cr0;
fc78f519 2989 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2990 }
95eb84a7
SY		 2991
2992 if (!(cr0 & X86_CR0_WP))
2993 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2994}
2995
6aa8b732
AK		 2996static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2997{
7ffd92c5 2998 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2999 unsigned long hw_cr0;
3000
3001 if (enable_unrestricted_guest)
3002 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3003 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3004 else
3005 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3006
7ffd92c5 3007 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3008 enter_pmode(vcpu);
3009
7ffd92c5 3010 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3011 enter_rmode(vcpu);
3012
05b3e0c2 3013#ifdef CONFIG_X86_64
f6801dff 3014 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3015 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3016 enter_lmode(vcpu);
707d92fa 3017 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3018 exit_lmode(vcpu);
3019 }
3020#endif
3021
089d034e 3022 if (enable_ept)
1439442c
SY		 3023 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3024
02daab21 3025 if (!vcpu->fpu_active)
81231c69 3026 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3027
6aa8b732 3028 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3029 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3030 vcpu->arch.cr0 = cr0;
69c73028 3031 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3032}
3033
1439442c
SY		 3034static u64 construct_eptp(unsigned long root_hpa)
3035{
3036 u64 eptp;
3037
3038 /* TODO write the value reading from MSR */
3039 eptp = VMX_EPT_DEFAULT_MT |
3040 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3041 if (enable_ept_ad_bits)
3042 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3043 eptp |= (root_hpa & PAGE_MASK);
3044
3045 return eptp;
3046}
3047
6aa8b732
AK		 3048static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3049{
1439442c
SY		 3050 unsigned long guest_cr3;
3051 u64 eptp;
3052
3053 guest_cr3 = cr3;
089d034e 3054 if (enable_ept) {
1439442c
SY		 3055 eptp = construct_eptp(cr3);
3056 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3057 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3058 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3059 ept_load_pdptrs(vcpu);
1439442c
SY		 3060 }
3061
2384d2b3 3062 vmx_flush_tlb(vcpu);
1439442c 3063 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3064}
3065
5e1746d6 3066static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3067{
7ffd92c5 3068 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3069 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3070
5e1746d6
NHE		 3071 if (cr4 & X86_CR4_VMXE) {
3072 /*
3073 * To use VMXON (and later other VMX instructions), a guest
3074 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3075 * So basically the check on whether to allow nested VMX
3076 * is here.
3077 */
3078 if (!nested_vmx_allowed(vcpu))
3079 return 1;
3080 } else if (to_vmx(vcpu)->nested.vmxon)
3081 return 1;
3082
ad312c7c 3083 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3084 if (enable_ept) {
3085 if (!is_paging(vcpu)) {
3086 hw_cr4 &= ~X86_CR4_PAE;
3087 hw_cr4 |= X86_CR4_PSE;
3088 } else if (!(cr4 & X86_CR4_PAE)) {
3089 hw_cr4 &= ~X86_CR4_PAE;
3090 }
3091 }
1439442c
SY		 3092
3093 vmcs_writel(CR4_READ_SHADOW, cr4);
3094 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3095 return 0;
6aa8b732
AK		 3096}
3097
6aa8b732
AK		 3098static void vmx_get_segment(struct kvm_vcpu *vcpu,
3099 struct kvm_segment *var, int seg)
3100{
a9179499 3101 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3102 u32 ar;
3103
a9179499
AK		 3104 if (vmx->rmode.vm86_active
3105 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3106 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
72636420 3107 || seg == VCPU_SREG_GS)) {
f5f7b2fe 3108 *var = vmx->rmode.segs[seg];
a9179499 3109 if (seg == VCPU_SREG_TR
2fb92db1 3110 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3111 return;
1390a28b
AK		 3112 var->base = vmx_read_guest_seg_base(vmx, seg);
3113 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3114 return;
a9179499 3115 }
2fb92db1
AK		 3116 var->base = vmx_read_guest_seg_base(vmx, seg);
3117 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3118 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3119 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3120 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3121 ar = 0;
3122 var->type = ar & 15;
3123 var->s = (ar >> 4) & 1;
3124 var->dpl = (ar >> 5) & 3;
3125 var->present = (ar >> 7) & 1;
3126 var->avl = (ar >> 12) & 1;
3127 var->l = (ar >> 13) & 1;
3128 var->db = (ar >> 14) & 1;
3129 var->g = (ar >> 15) & 1;
3130 var->unusable = (ar >> 16) & 1;
3131}
3132
a9179499
AK		 3133static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3134{
a9179499
AK		 3135 struct kvm_segment s;
3136
3137 if (to_vmx(vcpu)->rmode.vm86_active) {
3138 vmx_get_segment(vcpu, &s, seg);
3139 return s.base;
3140 }
2fb92db1 3141 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3142}
3143
69c73028 3144static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3145{
3eeb3288 3146 if (!is_protmode(vcpu))
2e4d2653
IE		 3147 return 0;
3148
f4c63e5d
AK		 3149 if (!is_long_mode(vcpu)
3150 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3151 return 3;
3152
2fb92db1 3153 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3154}
3155
69c73028
AK		 3156static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3157{
d881e6f6
AK		 3158 struct vcpu_vmx *vmx = to_vmx(vcpu);
3159
3160 /*
3161 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3162 * fail; use the cache instead.
3163 */
3164 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3165 return vmx->cpl;
3166 }
3167
69c73028
AK		 3168 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3169 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3170 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3171 }
d881e6f6
AK		 3172
3173 return vmx->cpl;
69c73028
AK		 3174}
3175
3176
653e3108 3177static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3178{
6aa8b732
AK		 3179 u32 ar;
3180
f0495f9b 3181 if (var->unusable || !var->present)
6aa8b732
AK		 3182 ar = 1 << 16;
3183 else {
3184 ar = var->type & 15;
3185 ar |= (var->s & 1) << 4;
3186 ar |= (var->dpl & 3) << 5;
3187 ar |= (var->present & 1) << 7;
3188 ar |= (var->avl & 1) << 12;
3189 ar |= (var->l & 1) << 13;
3190 ar |= (var->db & 1) << 14;
3191 ar |= (var->g & 1) << 15;
3192 }
653e3108
AK		 3193
3194 return ar;
3195}
3196
3197static void vmx_set_segment(struct kvm_vcpu *vcpu,
3198 struct kvm_segment *var, int seg)
3199{
7ffd92c5 3200 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3201 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108
AK		 3202 u32 ar;
3203
2fb92db1
AK		 3204 vmx_segment_cache_clear(vmx);
3205
7ffd92c5 3206 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3207 vmcs_write16(sf->selector, var->selector);
f5f7b2fe 3208 vmx->rmode.segs[VCPU_SREG_TR] = *var;
653e3108
AK		 3209 return;
3210 }
3211 vmcs_writel(sf->base, var->base);
3212 vmcs_write32(sf->limit, var->limit);
3213 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3214 if (vmx->rmode.vm86_active && var->s) {
ce566803 3215 vmx->rmode.segs[seg] = *var;
653e3108
AK		 3216 /*
3217 * Hack real-mode segments into vm86 compatibility.
3218 */
3219 if (var->base == 0xffff0000 && var->selector == 0xf000)
3220 vmcs_writel(sf->base, 0xf0000);
3221 ar = 0xf3;
3222 } else
3223 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3224
3225 /*
3226 * Fix the "Accessed" bit in AR field of segment registers for older
3227 * qemu binaries.
3228 * IA32 arch specifies that at the time of processor reset the
3229 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3230 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3231 * state vmexit when "unrestricted guest" mode is turned on.
3232 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3233 * tree. Newer qemu binaries with that qemu fix would not need this
3234 * kvm hack.
3235 */
3236 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3237 ar |= 0x1; /* Accessed */
3238
6aa8b732 3239 vmcs_write32(sf->ar_bytes, ar);
69c73028 3240 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3241
3242 /*
3243 * Fix segments for real mode guest in hosts that don't have
3244 * "unrestricted_mode" or it was disabled.
3245 * This is done to allow migration of the guests from hosts with
3246 * unrestricted guest like Westmere to older host that don't have
3247 * unrestricted guest like Nehelem.
3248 */
3249 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3250 switch (seg) {
3251 case VCPU_SREG_CS:
3252 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3253 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3254 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3255 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3256 vmcs_write16(GUEST_CS_SELECTOR,
3257 vmcs_readl(GUEST_CS_BASE) >> 4);
3258 break;
3259 case VCPU_SREG_ES:
b246dd5d 3260 case VCPU_SREG_DS:
b246dd5d 3261 case VCPU_SREG_GS:
b246dd5d 3262 case VCPU_SREG_FS:
f5f7b2fe 3263 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
b246dd5d
OW		 3264 break;
3265 case VCPU_SREG_SS:
3266 vmcs_write16(GUEST_SS_SELECTOR,
3267 vmcs_readl(GUEST_SS_BASE) >> 4);
3268 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3269 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3270 break;
3271 }
3272 }
6aa8b732
AK		 3273}
3274
6aa8b732
AK		 3275static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3276{
2fb92db1 3277 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3278
3279 *db = (ar >> 14) & 1;
3280 *l = (ar >> 13) & 1;
3281}
3282
89a27f4d 3283static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3284{
89a27f4d
GN		 3285 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3286 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3287}
3288
89a27f4d 3289static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3290{
89a27f4d
GN		 3291 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3292 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3293}
3294
89a27f4d 3295static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3296{
89a27f4d
GN		 3297 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3298 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3299}
3300
89a27f4d 3301static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3302{
89a27f4d
GN		 3303 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3304 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3305}
3306
648dfaa7
MG		 3307static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3308{
3309 struct kvm_segment var;
3310 u32 ar;
3311
3312 vmx_get_segment(vcpu, &var, seg);
3313 ar = vmx_segment_access_rights(&var);
3314
3315 if (var.base != (var.selector << 4))
3316 return false;
e2a610d7 3317 if (var.limit < 0xffff)
648dfaa7 3318 return false;
a81aba14 3319 if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
648dfaa7
MG		 3320 return false;
3321
3322 return true;
3323}
3324
3325static bool code_segment_valid(struct kvm_vcpu *vcpu)
3326{
3327 struct kvm_segment cs;
3328 unsigned int cs_rpl;
3329
3330 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3331 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3332
1872a3f4
AK		 3333 if (cs.unusable)
3334 return false;
648dfaa7
MG		 3335 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3336 return false;
3337 if (!cs.s)
3338 return false;
1872a3f4 3339 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3340 if (cs.dpl > cs_rpl)
3341 return false;
1872a3f4 3342 } else {
648dfaa7
MG		 3343 if (cs.dpl != cs_rpl)
3344 return false;
3345 }
3346 if (!cs.present)
3347 return false;
3348
3349 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3350 return true;
3351}
3352
3353static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3354{
3355 struct kvm_segment ss;
3356 unsigned int ss_rpl;
3357
3358 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3359 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3360
1872a3f4
AK		 3361 if (ss.unusable)
3362 return true;
3363 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3364 return false;
3365 if (!ss.s)
3366 return false;
3367 if (ss.dpl != ss_rpl) /* DPL != RPL */
3368 return false;
3369 if (!ss.present)
3370 return false;
3371
3372 return true;
3373}
3374
3375static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3376{
3377 struct kvm_segment var;
3378 unsigned int rpl;
3379
3380 vmx_get_segment(vcpu, &var, seg);
3381 rpl = var.selector & SELECTOR_RPL_MASK;
3382
1872a3f4
AK		 3383 if (var.unusable)
3384 return true;
648dfaa7
MG		 3385 if (!var.s)
3386 return false;
3387 if (!var.present)
3388 return false;
3389 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3390 if (var.dpl < rpl) /* DPL < RPL */
3391 return false;
3392 }
3393
3394 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3395 * rights flags
3396 */
3397 return true;
3398}
3399
3400static bool tr_valid(struct kvm_vcpu *vcpu)
3401{
3402 struct kvm_segment tr;
3403
3404 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3405
1872a3f4
AK		 3406 if (tr.unusable)
3407 return false;
648dfaa7
MG		 3408 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3409 return false;
1872a3f4 3410 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3411 return false;
3412 if (!tr.present)
3413 return false;
3414
3415 return true;
3416}
3417
3418static bool ldtr_valid(struct kvm_vcpu *vcpu)
3419{
3420 struct kvm_segment ldtr;
3421
3422 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3423
1872a3f4
AK		 3424 if (ldtr.unusable)
3425 return true;
648dfaa7
MG		 3426 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3427 return false;
3428 if (ldtr.type != 2)
3429 return false;
3430 if (!ldtr.present)
3431 return false;
3432
3433 return true;
3434}
3435
3436static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3437{
3438 struct kvm_segment cs, ss;
3439
3440 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3441 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3442
3443 return ((cs.selector & SELECTOR_RPL_MASK) ==
3444 (ss.selector & SELECTOR_RPL_MASK));
3445}
3446
3447/*
3448 * Check if guest state is valid. Returns true if valid, false if
3449 * not.
3450 * We assume that registers are always usable
3451 */
3452static bool guest_state_valid(struct kvm_vcpu *vcpu)
3453{
3454 /* real mode guest state checks */
3eeb3288 3455 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3456 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3457 return false;
3458 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3459 return false;
3460 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3461 return false;
3462 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3463 return false;
3464 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3465 return false;
3466 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3467 return false;
3468 } else {
3469 /* protected mode guest state checks */
3470 if (!cs_ss_rpl_check(vcpu))
3471 return false;
3472 if (!code_segment_valid(vcpu))
3473 return false;
3474 if (!stack_segment_valid(vcpu))
3475 return false;
3476 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3477 return false;
3478 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3479 return false;
3480 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3481 return false;
3482 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3483 return false;
3484 if (!tr_valid(vcpu))
3485 return false;
3486 if (!ldtr_valid(vcpu))
3487 return false;
3488 }
3489 /* TODO:
3490 * - Add checks on RIP
3491 * - Add checks on RFLAGS
3492 */
3493
3494 return true;
3495}
3496
d77c26fc 3497static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3498{
40dcaa9f 3499 gfn_t fn;
195aefde 3500 u16 data = 0;
40dcaa9f 3501 int r, idx, ret = 0;
6aa8b732 3502
40dcaa9f
XG		 3503 idx = srcu_read_lock(&kvm->srcu);
3504 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3505 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3506 if (r < 0)
10589a46 3507 goto out;
195aefde 3508 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3509 r = kvm_write_guest_page(kvm, fn++, &data,
3510 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3511 if (r < 0)
10589a46 3512 goto out;
195aefde
IE		 3513 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3514 if (r < 0)
10589a46 3515 goto out;
195aefde
IE		 3516 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3517 if (r < 0)
10589a46 3518 goto out;
195aefde 3519 data = ~0;
10589a46
MT		 3520 r = kvm_write_guest_page(kvm, fn, &data,
3521 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3522 sizeof(u8));
195aefde 3523 if (r < 0)
10589a46
MT		 3524 goto out;
3525
3526 ret = 1;
3527out:
40dcaa9f 3528 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3529 return ret;
6aa8b732
AK		 3530}
3531
b7ebfb05
SY		 3532static int init_rmode_identity_map(struct kvm *kvm)
3533{
40dcaa9f 3534 int i, idx, r, ret;
b7ebfb05
SY		 3535 pfn_t identity_map_pfn;
3536 u32 tmp;
3537
089d034e 3538 if (!enable_ept)
b7ebfb05
SY		 3539 return 1;
3540 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3541 printk(KERN_ERR "EPT: identity-mapping pagetable "
3542 "haven't been allocated!\n");
3543 return 0;
3544 }
3545 if (likely(kvm->arch.ept_identity_pagetable_done))
3546 return 1;
3547 ret = 0;
b927a3ce 3548 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3549 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3550 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3551 if (r < 0)
3552 goto out;
3553 /* Set up identity-mapping pagetable for EPT in real mode */
3554 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3555 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3556 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3557 r = kvm_write_guest_page(kvm, identity_map_pfn,
3558 &tmp, i * sizeof(tmp), sizeof(tmp));
3559 if (r < 0)
3560 goto out;
3561 }
3562 kvm->arch.ept_identity_pagetable_done = true;
3563 ret = 1;
3564out:
40dcaa9f 3565 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3566 return ret;
3567}
3568
6aa8b732
AK		 3569static void seg_setup(int seg)
3570{
772e0318 3571 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3572 unsigned int ar;
6aa8b732
AK		 3573
3574 vmcs_write16(sf->selector, 0);
3575 vmcs_writel(sf->base, 0);
3576 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3577 if (enable_unrestricted_guest) {
3578 ar = 0x93;
3579 if (seg == VCPU_SREG_CS)
3580 ar |= 0x08; /* code segment */
3581 } else
3582 ar = 0xf3;
3583
3584 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3585}
3586
f78e0e2e
SY		 3587static int alloc_apic_access_page(struct kvm *kvm)
3588{
4484141a 3589 struct page *page;
f78e0e2e
SY		 3590 struct kvm_userspace_memory_region kvm_userspace_mem;
3591 int r = 0;
3592
79fac95e 3593 mutex_lock(&kvm->slots_lock);
bfc6d222 3594 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3595 goto out;
3596 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3597 kvm_userspace_mem.flags = 0;
3598 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3599 kvm_userspace_mem.memory_size = PAGE_SIZE;
3600 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3601 if (r)
3602 goto out;
72dc67a6 3603
4484141a
XG		 3604 page = gfn_to_page(kvm, 0xfee00);
3605 if (is_error_page(page)) {
3606 r = -EFAULT;
3607 goto out;
3608 }
3609
3610 kvm->arch.apic_access_page = page;
f78e0e2e 3611out:
79fac95e 3612 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3613 return r;
3614}
3615
b7ebfb05
SY		 3616static int alloc_identity_pagetable(struct kvm *kvm)
3617{
4484141a 3618 struct page *page;
b7ebfb05
SY		 3619 struct kvm_userspace_memory_region kvm_userspace_mem;
3620 int r = 0;
3621
79fac95e 3622 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3623 if (kvm->arch.ept_identity_pagetable)
3624 goto out;
3625 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3626 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3627 kvm_userspace_mem.guest_phys_addr =
3628 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3629 kvm_userspace_mem.memory_size = PAGE_SIZE;
3630 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3631 if (r)
3632 goto out;
3633
4484141a
XG		 3634 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3635 if (is_error_page(page)) {
3636 r = -EFAULT;
3637 goto out;
3638 }
3639
3640 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3641out:
79fac95e 3642 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3643 return r;
3644}
3645
2384d2b3
SY		 3646static void allocate_vpid(struct vcpu_vmx *vmx)
3647{
3648 int vpid;
3649
3650 vmx->vpid = 0;
919818ab 3651 if (!enable_vpid)
2384d2b3
SY		 3652 return;
3653 spin_lock(&vmx_vpid_lock);
3654 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3655 if (vpid < VMX_NR_VPIDS) {
3656 vmx->vpid = vpid;
3657 __set_bit(vpid, vmx_vpid_bitmap);
3658 }
3659 spin_unlock(&vmx_vpid_lock);
3660}
3661
cdbecfc3
LJ		 3662static void free_vpid(struct vcpu_vmx *vmx)
3663{
3664 if (!enable_vpid)
3665 return;
3666 spin_lock(&vmx_vpid_lock);
3667 if (vmx->vpid != 0)
3668 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3669 spin_unlock(&vmx_vpid_lock);
3670}
3671
5897297b 3672static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3673{
3e7c73e9 3674 int f = sizeof(unsigned long);
25c5f225
SY		 3675
3676 if (!cpu_has_vmx_msr_bitmap())
3677 return;
3678
3679 /*
3680 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3681 * have the write-low and read-high bitmap offsets the wrong way round.
3682 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3683 */
25c5f225 3684 if (msr <= 0x1fff) {
3e7c73e9
AK		 3685 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3686 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3687 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3688 msr &= 0x1fff;
3e7c73e9
AK		 3689 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3690 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3691 }
25c5f225
SY		 3692}
3693
5897297b
AK		 3694static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3695{
3696 if (!longmode_only)
3697 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3698 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3699}
3700
a3a8ff8e
NHE		 3701/*
3702 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3703 * will not change in the lifetime of the guest.
3704 * Note that host-state that does change is set elsewhere. E.g., host-state
3705 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3706 */
3707static void vmx_set_constant_host_state(void)
3708{
3709 u32 low32, high32;
3710 unsigned long tmpl;
3711 struct desc_ptr dt;
3712
b1a74bf8 3713 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3714 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3715 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3716
3717 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3718#ifdef CONFIG_X86_64
3719 /*
3720 * Load null selectors, so we can avoid reloading them in
3721 * __vmx_load_host_state(), in case userspace uses the null selectors
3722 * too (the expected case).
3723 */
3724 vmcs_write16(HOST_DS_SELECTOR, 0);
3725 vmcs_write16(HOST_ES_SELECTOR, 0);
3726#else
a3a8ff8e
NHE		 3727 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3728 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3729#endif
a3a8ff8e
NHE		 3730 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3731 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3732
3733 native_store_idt(&dt);
3734 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3735
83287ea4 3736 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3737
3738 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3739 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3740 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3741 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3742
3743 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3744 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3745 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3746 }
3747}
3748
bf8179a0
NHE		 3749static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3750{
3751 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3752 if (enable_ept)
3753 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3754 if (is_guest_mode(&vmx->vcpu))
3755 vmx->vcpu.arch.cr4_guest_owned_bits &=
3756 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3757 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3758}
3759
3760static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3761{
3762 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3763 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3764 exec_control &= ~CPU_BASED_TPR_SHADOW;
3765#ifdef CONFIG_X86_64
3766 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3767 CPU_BASED_CR8_LOAD_EXITING;
3768#endif
3769 }
3770 if (!enable_ept)
3771 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3772 CPU_BASED_CR3_LOAD_EXITING |
3773 CPU_BASED_INVLPG_EXITING;
3774 return exec_control;
3775}
3776
3777static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3778{
3779 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3780 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3781 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3782 if (vmx->vpid == 0)
3783 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3784 if (!enable_ept) {
3785 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3786 enable_unrestricted_guest = 0;
ad756a16
MJ		 3787 /* Enable INVPCID for non-ept guests may cause performance regression. */
3788 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3789 }
3790 if (!enable_unrestricted_guest)
3791 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3792 if (!ple_gap)
3793 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3794 return exec_control;
3795}
3796
ce88decf
XG		 3797static void ept_set_mmio_spte_mask(void)
3798{
3799 /*
3800 * EPT Misconfigurations can be generated if the value of bits 2:0
3801 * of an EPT paging-structure entry is 110b (write/execute).
3802 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3803 * spte.
3804 */
3805 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3806}
3807
6aa8b732
AK		 3808/*
3809 * Sets up the vmcs for emulated real mode.
3810 */
8b9cf98c 3811static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3812{
2e4ce7f5 3813#ifdef CONFIG_X86_64
6aa8b732 3814 unsigned long a;
2e4ce7f5 3815#endif
6aa8b732 3816 int i;
6aa8b732 3817
6aa8b732 3818 /* I/O */
3e7c73e9
AK		 3819 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3820 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3821
25c5f225 3822 if (cpu_has_vmx_msr_bitmap())
5897297b 3823 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3824
6aa8b732
AK		 3825 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3826
6aa8b732 3827 /* Control */
1c3d14fe
YS		 3828 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3829 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3830
bf8179a0 3831 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3832
83ff3b9d 3833 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3834 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3835 vmx_secondary_exec_control(vmx));
83ff3b9d 3836 }
f78e0e2e 3837
4b8d54f9
ZE		 3838 if (ple_gap) {
3839 vmcs_write32(PLE_GAP, ple_gap);
3840 vmcs_write32(PLE_WINDOW, ple_window);
3841 }
3842
c3707958
XG		 3843 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3844 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3845 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3846
9581d442
AK		 3847 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3848 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3849 vmx_set_constant_host_state();
05b3e0c2 3850#ifdef CONFIG_X86_64
6aa8b732
AK		 3851 rdmsrl(MSR_FS_BASE, a);
3852 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3853 rdmsrl(MSR_GS_BASE, a);
3854 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3855#else
3856 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3857 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3858#endif
3859
2cc51560
ED		 3860 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3861 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3862 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3863 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3864 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3865
468d472f 3866 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3867 u32 msr_low, msr_high;
3868 u64 host_pat;
468d472f
SY		 3869 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3870 host_pat = msr_low | ((u64) msr_high << 32);
3871 /* Write the default value follow host pat */
3872 vmcs_write64(GUEST_IA32_PAT, host_pat);
3873 /* Keep arch.pat sync with GUEST_IA32_PAT */
3874 vmx->vcpu.arch.pat = host_pat;
3875 }
3876
6aa8b732
AK		 3877 for (i = 0; i < NR_VMX_MSR; ++i) {
3878 u32 index = vmx_msr_index[i];
3879 u32 data_low, data_high;
a2fa3e9f 3880 int j = vmx->nmsrs;
6aa8b732
AK		 3881
3882 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3883 continue;
432bd6cb
AK		 3884 if (wrmsr_safe(index, data_low, data_high) < 0)
3885 continue;
26bb0981
AK		 3886 vmx->guest_msrs[j].index = i;
3887 vmx->guest_msrs[j].data = 0;
d5696725 3888 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3889 ++vmx->nmsrs;
6aa8b732 3890 }
6aa8b732 3891
1c3d14fe 3892 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3893
3894 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3895 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3896
e00c8cf2 3897 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3898 set_cr4_guest_host_mask(vmx);
e00c8cf2 3899
99e3e30a 3900 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3901
e00c8cf2
AK		 3902 return 0;
3903}
3904
3905static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3906{
3907 struct vcpu_vmx *vmx = to_vmx(vcpu);
3908 u64 msr;
4b9d3a04 3909 int ret;
e00c8cf2 3910
5fdbf976 3911 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3912
7ffd92c5 3913 vmx->rmode.vm86_active = 0;
e00c8cf2 3914
3b86cd99
JK		 3915 vmx->soft_vnmi_blocked = 0;
3916
ad312c7c 3917 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3918 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3919 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3920 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3921 msr |= MSR_IA32_APICBASE_BSP;
3922 kvm_set_apic_base(&vmx->vcpu, msr);
3923
10ab25cd
JK		 3924 ret = fx_init(&vmx->vcpu);
3925 if (ret != 0)
3926 goto out;
e00c8cf2 3927
2fb92db1
AK		 3928 vmx_segment_cache_clear(vmx);
3929
5706be0d 3930 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3931 /*
3932 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3933 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3934 */
c5af89b6 3935 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3936 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3937 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3938 } else {
ad312c7c
ZX		 3939 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3940 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3941 }
e00c8cf2
AK		 3942
3943 seg_setup(VCPU_SREG_DS);
3944 seg_setup(VCPU_SREG_ES);
3945 seg_setup(VCPU_SREG_FS);
3946 seg_setup(VCPU_SREG_GS);
3947 seg_setup(VCPU_SREG_SS);
3948
3949 vmcs_write16(GUEST_TR_SELECTOR, 0);
3950 vmcs_writel(GUEST_TR_BASE, 0);
3951 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3952 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3953
3954 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3955 vmcs_writel(GUEST_LDTR_BASE, 0);
3956 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3957 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3958
3959 vmcs_write32(GUEST_SYSENTER_CS, 0);
3960 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3961 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3962
3963 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3964 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3965 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3966 else
5fdbf976
MT		 3967 kvm_rip_write(vcpu, 0);
3968 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3969
e00c8cf2
AK		 3970 vmcs_writel(GUEST_GDTR_BASE, 0);
3971 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3972
3973 vmcs_writel(GUEST_IDTR_BASE, 0);
3974 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3975
443381a8 3976 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3977 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3978 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3979
e00c8cf2
AK		 3980 /* Special registers */
3981 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3982
3983 setup_msrs(vmx);
3984
6aa8b732
AK		 3985 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3986
f78e0e2e
SY		 3987 if (cpu_has_vmx_tpr_shadow()) {
3988 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3989 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3990 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3991 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3992 vmcs_write32(TPR_THRESHOLD, 0);
3993 }
3994
3995 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3996 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3997 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3998
2384d2b3
SY		 3999 if (vmx->vpid != 0)
4000 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4001
fa40052c 4002 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4003 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4004 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4005 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4006 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4007 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4008 vmx_fpu_activate(&vmx->vcpu);
4009 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4010
b9d762fa 4011 vpid_sync_context(vmx);
2384d2b3 4012
3200f405 4013 ret = 0;
6aa8b732 4014
a89a8fb9
MG		 4015 /* HACK: Don't enable emulation on guest boot/reset */
4016 vmx->emulation_required = 0;
4017
6aa8b732
AK		 4018out:
4019 return ret;
4020}
4021
b6f1250e
NHE		 4022/*
4023 * In nested virtualization, check if L1 asked to exit on external interrupts.
4024 * For most existing hypervisors, this will always return true.
4025 */
4026static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4027{
4028 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4029 PIN_BASED_EXT_INTR_MASK;
4030}
4031
3b86cd99
JK		 4032static void enable_irq_window(struct kvm_vcpu *vcpu)
4033{
4034 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4035 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4036 /*
4037 * We get here if vmx_interrupt_allowed() said we can't
4038 * inject to L1 now because L2 must run. Ask L2 to exit
4039 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4040 */
d6185f20 4041 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4042 return;
d6185f20 4043 }
3b86cd99
JK		 4044
4045 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4046 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4047 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4048}
4049
4050static void enable_nmi_window(struct kvm_vcpu *vcpu)
4051{
4052 u32 cpu_based_vm_exec_control;
4053
4054 if (!cpu_has_virtual_nmis()) {
4055 enable_irq_window(vcpu);
4056 return;
4057 }
4058
30bd0c4c
AK		 4059 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4060 enable_irq_window(vcpu);
4061 return;
4062 }
3b86cd99
JK		 4063 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4064 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4065 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4066}
4067
66fd3f7f 4068static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4069{
9c8cba37 4070 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4071 uint32_t intr;
4072 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4073
229456fc 4074 trace_kvm_inj_virq(irq);
2714d1d3 4075
fa89a817 4076 ++vcpu->stat.irq_injections;
7ffd92c5 4077 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4078 int inc_eip = 0;
4079 if (vcpu->arch.interrupt.soft)
4080 inc_eip = vcpu->arch.event_exit_inst_len;
4081 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4082 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4083 return;
4084 }
66fd3f7f
GN		 4085 intr = irq | INTR_INFO_VALID_MASK;
4086 if (vcpu->arch.interrupt.soft) {
4087 intr |= INTR_TYPE_SOFT_INTR;
4088 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4089 vmx->vcpu.arch.event_exit_inst_len);
4090 } else
4091 intr |= INTR_TYPE_EXT_INTR;
4092 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4093}
4094
f08864b4
SY		 4095static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4096{
66a5a347
JK		 4097 struct vcpu_vmx *vmx = to_vmx(vcpu);
4098
0b6ac343
NHE		 4099 if (is_guest_mode(vcpu))
4100 return;
4101
3b86cd99
JK		 4102 if (!cpu_has_virtual_nmis()) {
4103 /*
4104 * Tracking the NMI-blocked state in software is built upon
4105 * finding the next open IRQ window. This, in turn, depends on
4106 * well-behaving guests: They have to keep IRQs disabled at
4107 * least as long as the NMI handler runs. Otherwise we may
4108 * cause NMI nesting, maybe breaking the guest. But as this is
4109 * highly unlikely, we can live with the residual risk.
4110 */
4111 vmx->soft_vnmi_blocked = 1;
4112 vmx->vnmi_blocked_time = 0;
4113 }
4114
487b391d 4115 ++vcpu->stat.nmi_injections;
9d58b931 4116 vmx->nmi_known_unmasked = false;
7ffd92c5 4117 if (vmx->rmode.vm86_active) {
71f9833b 4118 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4119 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4120 return;
4121 }
f08864b4
SY		 4122 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4123 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4124}
4125
c4282df9 4126static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4127{
3b86cd99 4128 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4129 return 0;
33f089ca 4130
c4282df9 4131 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4132 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4133 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4134}
4135
3cfc3092
JK		 4136static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4137{
4138 if (!cpu_has_virtual_nmis())
4139 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4140 if (to_vmx(vcpu)->nmi_known_unmasked)
4141 return false;
c332c83a 4142 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4143}
4144
4145static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4146{
4147 struct vcpu_vmx *vmx = to_vmx(vcpu);
4148
4149 if (!cpu_has_virtual_nmis()) {
4150 if (vmx->soft_vnmi_blocked != masked) {
4151 vmx->soft_vnmi_blocked = masked;
4152 vmx->vnmi_blocked_time = 0;
4153 }
4154 } else {
9d58b931 4155 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4156 if (masked)
4157 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4158 GUEST_INTR_STATE_NMI);
4159 else
4160 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4161 GUEST_INTR_STATE_NMI);
4162 }
4163}
4164
78646121
GN		 4165static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4166{
b6f1250e 4167 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4168 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4169 if (to_vmx(vcpu)->nested.nested_run_pending ||
4170 (vmcs12->idt_vectoring_info_field &
4171 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4172 return 0;
4173 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4174 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4175 vmcs12->vm_exit_intr_info = 0;
4176 /* fall through to normal code, but now in L1, not L2 */
4177 }
4178
c4282df9
GN		 4179 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4180 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4181 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4182}
4183
cbc94022
IE		 4184static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4185{
4186 int ret;
4187 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4188 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4189 .guest_phys_addr = addr,
4190 .memory_size = PAGE_SIZE * 3,
4191 .flags = 0,
4192 };
4193
4194 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4195 if (ret)
4196 return ret;
bfc6d222 4197 kvm->arch.tss_addr = addr;
93ea5388
GN		 4198 if (!init_rmode_tss(kvm))
4199 return -ENOMEM;
4200
cbc94022
IE		 4201 return 0;
4202}
4203
6aa8b732
AK		 4204static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4205 int vec, u32 err_code)
4206{
b3f37707
NK		 4207 /*
4208 * Instruction with address size override prefix opcode 0x67
4209 * Cause the #SS fault with 0 error code in VM86 mode.
4210 */
4211 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4212 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4213 return 1;
77ab6db0
JK		 4214 /*
4215 * Forward all other exceptions that are valid in real mode.
4216 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4217 * the required debugging infrastructure rework.
4218 */
4219 switch (vec) {
77ab6db0 4220 case DB_VECTOR:
d0bfb940
JK		 4221 if (vcpu->guest_debug &
4222 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4223 return 0;
4224 kvm_queue_exception(vcpu, vec);
4225 return 1;
77ab6db0 4226 case BP_VECTOR:
c573cd22
JK		 4227 /*
4228 * Update instruction length as we may reinject the exception
4229 * from user space while in guest debugging mode.
4230 */
4231 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4232 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4233 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4234 return 0;
4235 /* fall through */
4236 case DE_VECTOR:
77ab6db0
JK		 4237 case OF_VECTOR:
4238 case BR_VECTOR:
4239 case UD_VECTOR:
4240 case DF_VECTOR:
4241 case SS_VECTOR:
4242 case GP_VECTOR:
4243 case MF_VECTOR:
4244 kvm_queue_exception(vcpu, vec);
4245 return 1;
4246 }
6aa8b732
AK		 4247 return 0;
4248}
4249
a0861c02
AK		 4250/*
4251 * Trigger machine check on the host. We assume all the MSRs are already set up
4252 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4253 * We pass a fake environment to the machine check handler because we want
4254 * the guest to be always treated like user space, no matter what context
4255 * it used internally.
4256 */
4257static void kvm_machine_check(void)
4258{
4259#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4260 struct pt_regs regs = {
4261 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4262 .flags = X86_EFLAGS_IF,
4263 };
4264
4265 do_machine_check(&regs, 0);
4266#endif
4267}
4268
851ba692 4269static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4270{
4271 /* already handled by vcpu_run */
4272 return 1;
4273}
4274
851ba692 4275static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4276{
1155f76a 4277 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4278 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4279 u32 intr_info, ex_no, error_code;
42dbaa5a 4280 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4281 u32 vect_info;
4282 enum emulation_result er;
4283
1155f76a 4284 vect_info = vmx->idt_vectoring_info;
88786475 4285 intr_info = vmx->exit_intr_info;
6aa8b732 4286
a0861c02 4287 if (is_machine_check(intr_info))
851ba692 4288 return handle_machine_check(vcpu);
a0861c02 4289
e4a41889 4290 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4291 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4292
4293 if (is_no_device(intr_info)) {
5fd86fcf 4294 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4295 return 1;
4296 }
4297
7aa81cc0 4298 if (is_invalid_opcode(intr_info)) {
51d8b661 4299 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4300 if (er != EMULATE_DONE)
7ee5d940 4301 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4302 return 1;
4303 }
4304
6aa8b732 4305 error_code = 0;
2e11384c 4306 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4307 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4308
4309 /*
4310 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4311 * MMIO, it is better to report an internal error.
4312 * See the comments in vmx_handle_exit.
4313 */
4314 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4315 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4316 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4317 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4318 vcpu->run->internal.ndata = 2;
4319 vcpu->run->internal.data[0] = vect_info;
4320 vcpu->run->internal.data[1] = intr_info;
4321 return 0;
4322 }
4323
6aa8b732 4324 if (is_page_fault(intr_info)) {
1439442c 4325 /* EPT won't cause page fault directly */
cf3ace79 4326 BUG_ON(enable_ept);
6aa8b732 4327 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4328 trace_kvm_page_fault(cr2, error_code);
4329
3298b75c 4330 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4331 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4332 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4333 }
4334
7ffd92c5 4335 if (vmx->rmode.vm86_active &&
6aa8b732 4336 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4337 error_code)) {
ad312c7c
ZX		 4338 if (vcpu->arch.halt_request) {
4339 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4340 return kvm_emulate_halt(vcpu);
4341 }
6aa8b732 4342 return 1;
72d6e5a0 4343 }
6aa8b732 4344
d0bfb940 4345 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4346 switch (ex_no) {
4347 case DB_VECTOR:
4348 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4349 if (!(vcpu->guest_debug &
4350 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4351 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4352 kvm_queue_exception(vcpu, DB_VECTOR);
4353 return 1;
4354 }
4355 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4356 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4357 /* fall through */
4358 case BP_VECTOR:
c573cd22
JK		 4359 /*
4360 * Update instruction length as we may reinject #BP from
4361 * user space while in guest debugging mode. Reading it for
4362 * #DB as well causes no harm, it is not used in that case.
4363 */
4364 vmx->vcpu.arch.event_exit_inst_len =
4365 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4366 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4367 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4368 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4369 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4370 break;
4371 default:
d0bfb940
JK		 4372 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4373 kvm_run->ex.exception = ex_no;
4374 kvm_run->ex.error_code = error_code;
42dbaa5a 4375 break;
6aa8b732 4376 }
6aa8b732
AK		 4377 return 0;
4378}
4379
851ba692 4380static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4381{
1165f5fe 4382 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4383 return 1;
4384}
4385
851ba692 4386static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4387{
851ba692 4388 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4389 return 0;
4390}
6aa8b732 4391
851ba692 4392static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4393{
bfdaab09 4394 unsigned long exit_qualification;
34c33d16 4395 int size, in, string;
039576c0 4396 unsigned port;
6aa8b732 4397
bfdaab09 4398 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4399 string = (exit_qualification & 16) != 0;
cf8f70bf 4400 in = (exit_qualification & 8) != 0;
e70669ab 4401
cf8f70bf 4402 ++vcpu->stat.io_exits;
e70669ab 4403
cf8f70bf 4404 if (string || in)
51d8b661 4405 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4406
cf8f70bf
GN		 4407 port = exit_qualification >> 16;
4408 size = (exit_qualification & 7) + 1;
e93f36bc 4409 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4410
4411 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4412}
4413
102d8325
IM		 4414static void
4415vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4416{
4417 /*
4418 * Patch in the VMCALL instruction:
4419 */
4420 hypercall[0] = 0x0f;
4421 hypercall[1] = 0x01;
4422 hypercall[2] = 0xc1;
102d8325
IM		 4423}
4424
0fa06071 4425/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4426static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4427{
4428 if (to_vmx(vcpu)->nested.vmxon &&
4429 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4430 return 1;
4431
4432 if (is_guest_mode(vcpu)) {
4433 /*
4434 * We get here when L2 changed cr0 in a way that did not change
4435 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4436 * but did change L0 shadowed bits. This can currently happen
4437 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4438 * loading) while pretending to allow the guest to change it.
4439 */
4440 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4441 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4442 return 1;
4443 vmcs_writel(CR0_READ_SHADOW, val);
4444 return 0;
4445 } else
4446 return kvm_set_cr0(vcpu, val);
4447}
4448
4449static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4450{
4451 if (is_guest_mode(vcpu)) {
4452 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4453 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4454 return 1;
4455 vmcs_writel(CR4_READ_SHADOW, val);
4456 return 0;
4457 } else
4458 return kvm_set_cr4(vcpu, val);
4459}
4460
4461/* called to set cr0 as approriate for clts instruction exit. */
4462static void handle_clts(struct kvm_vcpu *vcpu)
4463{
4464 if (is_guest_mode(vcpu)) {
4465 /*
4466 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4467 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4468 * just pretend it's off (also in arch.cr0 for fpu_activate).
4469 */
4470 vmcs_writel(CR0_READ_SHADOW,
4471 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4472 vcpu->arch.cr0 &= ~X86_CR0_TS;
4473 } else
4474 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4475}
4476
851ba692 4477static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4478{
229456fc 4479 unsigned long exit_qualification, val;
6aa8b732
AK		 4480 int cr;
4481 int reg;
49a9b07e 4482 int err;
6aa8b732 4483
bfdaab09 4484 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4485 cr = exit_qualification & 15;
4486 reg = (exit_qualification >> 8) & 15;
4487 switch ((exit_qualification >> 4) & 3) {
4488 case 0: /* mov to cr */
229456fc
MT		 4489 val = kvm_register_read(vcpu, reg);
4490 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4491 switch (cr) {
4492 case 0:
eeadf9e7 4493 err = handle_set_cr0(vcpu, val);
db8fcefa 4494 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4495 return 1;
4496 case 3:
2390218b 4497 err = kvm_set_cr3(vcpu, val);
db8fcefa 4498 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4499 return 1;
4500 case 4:
eeadf9e7 4501 err = handle_set_cr4(vcpu, val);
db8fcefa 4502 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4503 return 1;
0a5fff19
GN		 4504 case 8: {
4505 u8 cr8_prev = kvm_get_cr8(vcpu);
4506 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4507 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4508 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4509 if (irqchip_in_kernel(vcpu->kvm))
4510 return 1;
4511 if (cr8_prev <= cr8)
4512 return 1;
851ba692 4513 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4514 return 0;
4515 }
4b8073e4 4516 }
6aa8b732 4517 break;
25c4c276 4518 case 2: /* clts */
eeadf9e7 4519 handle_clts(vcpu);
4d4ec087 4520 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4521 skip_emulated_instruction(vcpu);
6b52d186 4522 vmx_fpu_activate(vcpu);
25c4c276 4523 return 1;
6aa8b732
AK		 4524 case 1: /*mov from cr*/
4525 switch (cr) {
4526 case 3:
9f8fe504
AK		 4527 val = kvm_read_cr3(vcpu);
4528 kvm_register_write(vcpu, reg, val);
4529 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4530 skip_emulated_instruction(vcpu);
4531 return 1;
4532 case 8:
229456fc
MT		 4533 val = kvm_get_cr8(vcpu);
4534 kvm_register_write(vcpu, reg, val);
4535 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4536 skip_emulated_instruction(vcpu);
4537 return 1;
4538 }
4539 break;
4540 case 3: /* lmsw */
a1f83a74 4541 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4542 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4543 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4544
4545 skip_emulated_instruction(vcpu);
4546 return 1;
4547 default:
4548 break;
4549 }
851ba692 4550 vcpu->run->exit_reason = 0;
a737f256 4551 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4552 (int)(exit_qualification >> 4) & 3, cr);
4553 return 0;
4554}
4555
851ba692 4556static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4557{
bfdaab09 4558 unsigned long exit_qualification;
6aa8b732
AK		 4559 int dr, reg;
4560
f2483415 4561 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4562 if (!kvm_require_cpl(vcpu, 0))
4563 return 1;
42dbaa5a
JK		 4564 dr = vmcs_readl(GUEST_DR7);
4565 if (dr & DR7_GD) {
4566 /*
4567 * As the vm-exit takes precedence over the debug trap, we
4568 * need to emulate the latter, either for the host or the
4569 * guest debugging itself.
4570 */
4571 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4572 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4573 vcpu->run->debug.arch.dr7 = dr;
4574 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4575 vmcs_readl(GUEST_CS_BASE) +
4576 vmcs_readl(GUEST_RIP);
851ba692
AK		 4577 vcpu->run->debug.arch.exception = DB_VECTOR;
4578 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4579 return 0;
4580 } else {
4581 vcpu->arch.dr7 &= ~DR7_GD;
4582 vcpu->arch.dr6 |= DR6_BD;
4583 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4584 kvm_queue_exception(vcpu, DB_VECTOR);
4585 return 1;
4586 }
4587 }
4588
bfdaab09 4589 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4590 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4591 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4592 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4593 unsigned long val;
4594 if (!kvm_get_dr(vcpu, dr, &val))
4595 kvm_register_write(vcpu, reg, val);
4596 } else
4597 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4598 skip_emulated_instruction(vcpu);
4599 return 1;
4600}
4601
020df079
GN		 4602static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4603{
4604 vmcs_writel(GUEST_DR7, val);
4605}
4606
851ba692 4607static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4608{
06465c5a
AK		 4609 kvm_emulate_cpuid(vcpu);
4610 return 1;
6aa8b732
AK		 4611}
4612
851ba692 4613static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4614{
ad312c7c 4615 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4616 u64 data;
4617
4618 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4619 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4620 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4621 return 1;
4622 }
4623
229456fc 4624 trace_kvm_msr_read(ecx, data);
2714d1d3 4625
6aa8b732 4626 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4627 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4628 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4629 skip_emulated_instruction(vcpu);
4630 return 1;
4631}
4632
851ba692 4633static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4634{
ad312c7c
ZX		 4635 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4636 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4637 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4638
4639 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4640 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4641 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4642 return 1;
4643 }
4644
59200273 4645 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4646 skip_emulated_instruction(vcpu);
4647 return 1;
4648}
4649
851ba692 4650static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4651{
3842d135 4652 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4653 return 1;
4654}
4655
851ba692 4656static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4657{
85f455f7
ED		 4658 u32 cpu_based_vm_exec_control;
4659
4660 /* clear pending irq */
4661 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4662 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4663 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4664
3842d135
AK		 4665 kvm_make_request(KVM_REQ_EVENT, vcpu);
4666
a26bf12a 4667 ++vcpu->stat.irq_window_exits;
2714d1d3 4668
c1150d8c
DL		 4669 /*
4670 * If the user space waits to inject interrupts, exit as soon as
4671 * possible
4672 */
8061823a 4673 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4674 vcpu->run->request_interrupt_window &&
8061823a 4675 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4676 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4677 return 0;
4678 }
6aa8b732
AK		 4679 return 1;
4680}
4681
851ba692 4682static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4683{
4684 skip_emulated_instruction(vcpu);
d3bef15f 4685 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4686}
4687
851ba692 4688static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4689{
510043da 4690 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4691 kvm_emulate_hypercall(vcpu);
4692 return 1;
c21415e8
IM		 4693}
4694
ec25d5e6
GN		 4695static int handle_invd(struct kvm_vcpu *vcpu)
4696{
51d8b661 4697 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4698}
4699
851ba692 4700static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4701{
f9c617f6 4702 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4703
4704 kvm_mmu_invlpg(vcpu, exit_qualification);
4705 skip_emulated_instruction(vcpu);
4706 return 1;
4707}
4708
fee84b07
AK		 4709static int handle_rdpmc(struct kvm_vcpu *vcpu)
4710{
4711 int err;
4712
4713 err = kvm_rdpmc(vcpu);
4714 kvm_complete_insn_gp(vcpu, err);
4715
4716 return 1;
4717}
4718
851ba692 4719static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4720{
4721 skip_emulated_instruction(vcpu);
f5f48ee1 4722 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4723 return 1;
4724}
4725
2acf923e
DC		 4726static int handle_xsetbv(struct kvm_vcpu *vcpu)
4727{
4728 u64 new_bv = kvm_read_edx_eax(vcpu);
4729 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4730
4731 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4732 skip_emulated_instruction(vcpu);
4733 return 1;
4734}
4735
851ba692 4736static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4737{
58fbbf26
KT		 4738 if (likely(fasteoi)) {
4739 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4740 int access_type, offset;
4741
4742 access_type = exit_qualification & APIC_ACCESS_TYPE;
4743 offset = exit_qualification & APIC_ACCESS_OFFSET;
4744 /*
4745 * Sane guest uses MOV to write EOI, with written value
4746 * not cared. So make a short-circuit here by avoiding
4747 * heavy instruction emulation.
4748 */
4749 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4750 (offset == APIC_EOI)) {
4751 kvm_lapic_set_eoi(vcpu);
4752 skip_emulated_instruction(vcpu);
4753 return 1;
4754 }
4755 }
51d8b661 4756 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4757}
4758
851ba692 4759static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4760{
60637aac 4761 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4762 unsigned long exit_qualification;
e269fb21
JK		 4763 bool has_error_code = false;
4764 u32 error_code = 0;
37817f29 4765 u16 tss_selector;
7f3d35fd 4766 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4767
4768 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4769 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4770 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4771
4772 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4773
4774 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4775 if (reason == TASK_SWITCH_GATE && idt_v) {
4776 switch (type) {
4777 case INTR_TYPE_NMI_INTR:
4778 vcpu->arch.nmi_injected = false;
654f06fc 4779 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4780 break;
4781 case INTR_TYPE_EXT_INTR:
66fd3f7f 4782 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4783 kvm_clear_interrupt_queue(vcpu);
4784 break;
4785 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4786 if (vmx->idt_vectoring_info &
4787 VECTORING_INFO_DELIVER_CODE_MASK) {
4788 has_error_code = true;
4789 error_code =
4790 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4791 }
4792 /* fall through */
64a7ec06
GN		 4793 case INTR_TYPE_SOFT_EXCEPTION:
4794 kvm_clear_exception_queue(vcpu);
4795 break;
4796 default:
4797 break;
4798 }
60637aac 4799 }
37817f29
IE		 4800 tss_selector = exit_qualification;
4801
64a7ec06
GN		 4802 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4803 type != INTR_TYPE_EXT_INTR &&
4804 type != INTR_TYPE_NMI_INTR))
4805 skip_emulated_instruction(vcpu);
4806
7f3d35fd
KW		 4807 if (kvm_task_switch(vcpu, tss_selector,
4808 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4809 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4810 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4811 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4812 vcpu->run->internal.ndata = 0;
42dbaa5a 4813 return 0;
acb54517 4814 }
42dbaa5a
JK		 4815
4816 /* clear all local breakpoint enable flags */
4817 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4818
4819 /*
4820 * TODO: What about debug traps on tss switch?
4821 * Are we supposed to inject them and update dr6?
4822 */
4823
4824 return 1;
37817f29
IE		 4825}
4826
851ba692 4827static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4828{
f9c617f6 4829 unsigned long exit_qualification;
1439442c 4830 gpa_t gpa;
4f5982a5 4831 u32 error_code;
1439442c 4832 int gla_validity;
1439442c 4833
f9c617f6 4834 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4835
4836 if (exit_qualification & (1 << 6)) {
4837 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4838 return -EINVAL;
1439442c
SY		 4839 }
4840
4841 gla_validity = (exit_qualification >> 7) & 0x3;
4842 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4843 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4844 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4845 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4846 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4847 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4848 (long unsigned int)exit_qualification);
851ba692
AK		 4849 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4850 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4851 return 0;
1439442c
SY		 4852 }
4853
4854 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4855 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4856
4857 /* It is a write fault? */
4858 error_code = exit_qualification & (1U << 1);
4859 /* ept page table is present? */
4860 error_code |= (exit_qualification >> 3) & 0x1;
4861
4862 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4863}
4864
68f89400
MT		 4865static u64 ept_rsvd_mask(u64 spte, int level)
4866{
4867 int i;
4868 u64 mask = 0;
4869
4870 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4871 mask |= (1ULL << i);
4872
4873 if (level > 2)
4874 /* bits 7:3 reserved */
4875 mask |= 0xf8;
4876 else if (level == 2) {
4877 if (spte & (1ULL << 7))
4878 /* 2MB ref, bits 20:12 reserved */
4879 mask |= 0x1ff000;
4880 else
4881 /* bits 6:3 reserved */
4882 mask |= 0x78;
4883 }
4884
4885 return mask;
4886}
4887
4888static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4889 int level)
4890{
4891 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4892
4893 /* 010b (write-only) */
4894 WARN_ON((spte & 0x7) == 0x2);
4895
4896 /* 110b (write/execute) */
4897 WARN_ON((spte & 0x7) == 0x6);
4898
4899 /* 100b (execute-only) and value not supported by logical processor */
4900 if (!cpu_has_vmx_ept_execute_only())
4901 WARN_ON((spte & 0x7) == 0x4);
4902
4903 /* not 000b */
4904 if ((spte & 0x7)) {
4905 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4906
4907 if (rsvd_bits != 0) {
4908 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4909 __func__, rsvd_bits);
4910 WARN_ON(1);
4911 }
4912
4913 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4914 u64 ept_mem_type = (spte & 0x38) >> 3;
4915
4916 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4917 ept_mem_type == 7) {
4918 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4919 __func__, ept_mem_type);
4920 WARN_ON(1);
4921 }
4922 }
4923 }
4924}
4925
851ba692 4926static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4927{
4928 u64 sptes[4];
ce88decf 4929 int nr_sptes, i, ret;
68f89400
MT		 4930 gpa_t gpa;
4931
4932 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4933
ce88decf
XG		 4934 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4935 if (likely(ret == 1))
4936 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4937 EMULATE_DONE;
4938 if (unlikely(!ret))
4939 return 1;
4940
4941 /* It is the real ept misconfig */
68f89400
MT		 4942 printk(KERN_ERR "EPT: Misconfiguration.\n");
4943 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4944
4945 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4946
4947 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4948 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4949
851ba692
AK		 4950 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4951 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4952
4953 return 0;
4954}
4955
851ba692 4956static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4957{
4958 u32 cpu_based_vm_exec_control;
4959
4960 /* clear pending NMI */
4961 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4962 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4963 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4964 ++vcpu->stat.nmi_window_exits;
3842d135 4965 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4966
4967 return 1;
4968}
4969
80ced186 4970static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4971{
8b3079a5
AK		 4972 struct vcpu_vmx *vmx = to_vmx(vcpu);
4973 enum emulation_result err = EMULATE_DONE;
80ced186 4974 int ret = 1;
49e9d557
AK		 4975 u32 cpu_exec_ctrl;
4976 bool intr_window_requested;
b8405c18 4977 unsigned count = 130;
49e9d557
AK		 4978
4979 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4980 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 4981
b8405c18 4982 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 4983 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 4984 return handle_interrupt_window(&vmx->vcpu);
4985
de87dcdd
AK		 4986 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
4987 return 1;
4988
51d8b661 4989 err = emulate_instruction(vcpu, 0);
ea953ef0 4990
80ced186
MG		 4991 if (err == EMULATE_DO_MMIO) {
4992 ret = 0;
4993 goto out;
4994 }
1d5a4d9b 4995
de5f70e0
AK		 4996 if (err != EMULATE_DONE) {
4997 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4998 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4999 vcpu->run->internal.ndata = 0;
6d77dbfc 5000 return 0;
de5f70e0 5001 }
ea953ef0
MG		 5002
5003 if (signal_pending(current))
80ced186 5004 goto out;
ea953ef0
MG		 5005 if (need_resched())
5006 schedule();
5007 }
5008
7c068e45 5009 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5010out:
5011 return ret;
ea953ef0
MG		 5012}
5013
4b8d54f9
ZE		 5014/*
5015 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5016 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5017 */
9fb41ba8 5018static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5019{
5020 skip_emulated_instruction(vcpu);
5021 kvm_vcpu_on_spin(vcpu);
5022
5023 return 1;
5024}
5025
59708670
SY		 5026static int handle_invalid_op(struct kvm_vcpu *vcpu)
5027{
5028 kvm_queue_exception(vcpu, UD_VECTOR);
5029 return 1;
5030}
5031
ff2f6fe9
NHE		 5032/*
5033 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5034 * We could reuse a single VMCS for all the L2 guests, but we also want the
5035 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5036 * allows keeping them loaded on the processor, and in the future will allow
5037 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5038 * every entry if they never change.
5039 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5040 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5041 *
5042 * The following functions allocate and free a vmcs02 in this pool.
5043 */
5044
5045/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5046static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5047{
5048 struct vmcs02_list *item;
5049 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5050 if (item->vmptr == vmx->nested.current_vmptr) {
5051 list_move(&item->list, &vmx->nested.vmcs02_pool);
5052 return &item->vmcs02;
5053 }
5054
5055 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5056 /* Recycle the least recently used VMCS. */
5057 item = list_entry(vmx->nested.vmcs02_pool.prev,
5058 struct vmcs02_list, list);
5059 item->vmptr = vmx->nested.current_vmptr;
5060 list_move(&item->list, &vmx->nested.vmcs02_pool);
5061 return &item->vmcs02;
5062 }
5063
5064 /* Create a new VMCS */
5065 item = (struct vmcs02_list *)
5066 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5067 if (!item)
5068 return NULL;
5069 item->vmcs02.vmcs = alloc_vmcs();
5070 if (!item->vmcs02.vmcs) {
5071 kfree(item);
5072 return NULL;
5073 }
5074 loaded_vmcs_init(&item->vmcs02);
5075 item->vmptr = vmx->nested.current_vmptr;
5076 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5077 vmx->nested.vmcs02_num++;
5078 return &item->vmcs02;
5079}
5080
5081/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5082static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5083{
5084 struct vmcs02_list *item;
5085 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5086 if (item->vmptr == vmptr) {
5087 free_loaded_vmcs(&item->vmcs02);
5088 list_del(&item->list);
5089 kfree(item);
5090 vmx->nested.vmcs02_num--;
5091 return;
5092 }
5093}
5094
5095/*
5096 * Free all VMCSs saved for this vcpu, except the one pointed by
5097 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5098 * currently used, if running L2), and vmcs01 when running L2.
5099 */
5100static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5101{
5102 struct vmcs02_list *item, *n;
5103 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5104 if (vmx->loaded_vmcs != &item->vmcs02)
5105 free_loaded_vmcs(&item->vmcs02);
5106 list_del(&item->list);
5107 kfree(item);
5108 }
5109 vmx->nested.vmcs02_num = 0;
5110
5111 if (vmx->loaded_vmcs != &vmx->vmcs01)
5112 free_loaded_vmcs(&vmx->vmcs01);
5113}
5114
ec378aee
NHE		 5115/*
5116 * Emulate the VMXON instruction.
5117 * Currently, we just remember that VMX is active, and do not save or even
5118 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5119 * do not currently need to store anything in that guest-allocated memory
5120 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5121 * argument is different from the VMXON pointer (which the spec says they do).
5122 */
5123static int handle_vmon(struct kvm_vcpu *vcpu)
5124{
5125 struct kvm_segment cs;
5126 struct vcpu_vmx *vmx = to_vmx(vcpu);
5127
5128 /* The Intel VMX Instruction Reference lists a bunch of bits that
5129 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5130 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5131 * Otherwise, we should fail with #UD. We test these now:
5132 */
5133 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5134 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5135 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5136 kvm_queue_exception(vcpu, UD_VECTOR);
5137 return 1;
5138 }
5139
5140 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5141 if (is_long_mode(vcpu) && !cs.l) {
5142 kvm_queue_exception(vcpu, UD_VECTOR);
5143 return 1;
5144 }
5145
5146 if (vmx_get_cpl(vcpu)) {
5147 kvm_inject_gp(vcpu, 0);
5148 return 1;
5149 }
5150
ff2f6fe9
NHE		 5151 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5152 vmx->nested.vmcs02_num = 0;
5153
ec378aee
NHE		 5154 vmx->nested.vmxon = true;
5155
5156 skip_emulated_instruction(vcpu);
5157 return 1;
5158}
5159
5160/*
5161 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5162 * for running VMX instructions (except VMXON, whose prerequisites are
5163 * slightly different). It also specifies what exception to inject otherwise.
5164 */
5165static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5166{
5167 struct kvm_segment cs;
5168 struct vcpu_vmx *vmx = to_vmx(vcpu);
5169
5170 if (!vmx->nested.vmxon) {
5171 kvm_queue_exception(vcpu, UD_VECTOR);
5172 return 0;
5173 }
5174
5175 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5176 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5177 (is_long_mode(vcpu) && !cs.l)) {
5178 kvm_queue_exception(vcpu, UD_VECTOR);
5179 return 0;
5180 }
5181
5182 if (vmx_get_cpl(vcpu)) {
5183 kvm_inject_gp(vcpu, 0);
5184 return 0;
5185 }
5186
5187 return 1;
5188}
5189
5190/*
5191 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5192 * just stops using VMX.
5193 */
5194static void free_nested(struct vcpu_vmx *vmx)
5195{
5196 if (!vmx->nested.vmxon)
5197 return;
5198 vmx->nested.vmxon = false;
a9d30f33
NHE		 5199 if (vmx->nested.current_vmptr != -1ull) {
5200 kunmap(vmx->nested.current_vmcs12_page);
5201 nested_release_page(vmx->nested.current_vmcs12_page);
5202 vmx->nested.current_vmptr = -1ull;
5203 vmx->nested.current_vmcs12 = NULL;
5204 }
fe3ef05c
NHE		 5205 /* Unpin physical memory we referred to in current vmcs02 */
5206 if (vmx->nested.apic_access_page) {
5207 nested_release_page(vmx->nested.apic_access_page);
5208 vmx->nested.apic_access_page = 0;
5209 }
ff2f6fe9
NHE		 5210
5211 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5212}
5213
5214/* Emulate the VMXOFF instruction */
5215static int handle_vmoff(struct kvm_vcpu *vcpu)
5216{
5217 if (!nested_vmx_check_permission(vcpu))
5218 return 1;
5219 free_nested(to_vmx(vcpu));
5220 skip_emulated_instruction(vcpu);
5221 return 1;
5222}
5223
064aea77
NHE		 5224/*
5225 * Decode the memory-address operand of a vmx instruction, as recorded on an
5226 * exit caused by such an instruction (run by a guest hypervisor).
5227 * On success, returns 0. When the operand is invalid, returns 1 and throws
5228 * #UD or #GP.
5229 */
5230static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5231 unsigned long exit_qualification,
5232 u32 vmx_instruction_info, gva_t *ret)
5233{
5234 /*
5235 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5236 * Execution", on an exit, vmx_instruction_info holds most of the
5237 * addressing components of the operand. Only the displacement part
5238 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5239 * For how an actual address is calculated from all these components,
5240 * refer to Vol. 1, "Operand Addressing".
5241 */
5242 int scaling = vmx_instruction_info & 3;
5243 int addr_size = (vmx_instruction_info >> 7) & 7;
5244 bool is_reg = vmx_instruction_info & (1u << 10);
5245 int seg_reg = (vmx_instruction_info >> 15) & 7;
5246 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5247 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5248 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5249 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5250
5251 if (is_reg) {
5252 kvm_queue_exception(vcpu, UD_VECTOR);
5253 return 1;
5254 }
5255
5256 /* Addr = segment_base + offset */
5257 /* offset = base + [index * scale] + displacement */
5258 *ret = vmx_get_segment_base(vcpu, seg_reg);
5259 if (base_is_valid)
5260 *ret += kvm_register_read(vcpu, base_reg);
5261 if (index_is_valid)
5262 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5263 *ret += exit_qualification; /* holds the displacement */
5264
5265 if (addr_size == 1) /* 32 bit */
5266 *ret &= 0xffffffff;
5267
5268 /*
5269 * TODO: throw #GP (and return 1) in various cases that the VM*
5270 * instructions require it - e.g., offset beyond segment limit,
5271 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5272 * address, and so on. Currently these are not checked.
5273 */
5274 return 0;
5275}
5276
0140caea
NHE		 5277/*
5278 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5279 * set the success or error code of an emulated VMX instruction, as specified
5280 * by Vol 2B, VMX Instruction Reference, "Conventions".
5281 */
5282static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5283{
5284 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5285 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5286 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5287}
5288
5289static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5290{
5291 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5292 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5293 X86_EFLAGS_SF | X86_EFLAGS_OF))
5294 | X86_EFLAGS_CF);
5295}
5296
5297static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5298 u32 vm_instruction_error)
5299{
5300 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5301 /*
5302 * failValid writes the error number to the current VMCS, which
5303 * can't be done there isn't a current VMCS.
5304 */
5305 nested_vmx_failInvalid(vcpu);
5306 return;
5307 }
5308 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5309 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5310 X86_EFLAGS_SF | X86_EFLAGS_OF))
5311 | X86_EFLAGS_ZF);
5312 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5313}
5314
27d6c865
NHE		 5315/* Emulate the VMCLEAR instruction */
5316static int handle_vmclear(struct kvm_vcpu *vcpu)
5317{
5318 struct vcpu_vmx *vmx = to_vmx(vcpu);
5319 gva_t gva;
5320 gpa_t vmptr;
5321 struct vmcs12 *vmcs12;
5322 struct page *page;
5323 struct x86_exception e;
5324
5325 if (!nested_vmx_check_permission(vcpu))
5326 return 1;
5327
5328 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5329 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5330 return 1;
5331
5332 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5333 sizeof(vmptr), &e)) {
5334 kvm_inject_page_fault(vcpu, &e);
5335 return 1;
5336 }
5337
5338 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5339 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5340 skip_emulated_instruction(vcpu);
5341 return 1;
5342 }
5343
5344 if (vmptr == vmx->nested.current_vmptr) {
5345 kunmap(vmx->nested.current_vmcs12_page);
5346 nested_release_page(vmx->nested.current_vmcs12_page);
5347 vmx->nested.current_vmptr = -1ull;
5348 vmx->nested.current_vmcs12 = NULL;
5349 }
5350
5351 page = nested_get_page(vcpu, vmptr);
5352 if (page == NULL) {
5353 /*
5354 * For accurate processor emulation, VMCLEAR beyond available
5355 * physical memory should do nothing at all. However, it is
5356 * possible that a nested vmx bug, not a guest hypervisor bug,
5357 * resulted in this case, so let's shut down before doing any
5358 * more damage:
5359 */
5360 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5361 return 1;
5362 }
5363 vmcs12 = kmap(page);
5364 vmcs12->launch_state = 0;
5365 kunmap(page);
5366 nested_release_page(page);
5367
5368 nested_free_vmcs02(vmx, vmptr);
5369
5370 skip_emulated_instruction(vcpu);
5371 nested_vmx_succeed(vcpu);
5372 return 1;
5373}
5374
cd232ad0
NHE		 5375static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5376
5377/* Emulate the VMLAUNCH instruction */
5378static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5379{
5380 return nested_vmx_run(vcpu, true);
5381}
5382
5383/* Emulate the VMRESUME instruction */
5384static int handle_vmresume(struct kvm_vcpu *vcpu)
5385{
5386
5387 return nested_vmx_run(vcpu, false);
5388}
5389
49f705c5
NHE		 5390enum vmcs_field_type {
5391 VMCS_FIELD_TYPE_U16 = 0,
5392 VMCS_FIELD_TYPE_U64 = 1,
5393 VMCS_FIELD_TYPE_U32 = 2,
5394 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5395};
5396
5397static inline int vmcs_field_type(unsigned long field)
5398{
5399 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5400 return VMCS_FIELD_TYPE_U32;
5401 return (field >> 13) & 0x3 ;
5402}
5403
5404static inline int vmcs_field_readonly(unsigned long field)
5405{
5406 return (((field >> 10) & 0x3) == 1);
5407}
5408
5409/*
5410 * Read a vmcs12 field. Since these can have varying lengths and we return
5411 * one type, we chose the biggest type (u64) and zero-extend the return value
5412 * to that size. Note that the caller, handle_vmread, might need to use only
5413 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5414 * 64-bit fields are to be returned).
5415 */
5416static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5417 unsigned long field, u64 *ret)
5418{
5419 short offset = vmcs_field_to_offset(field);
5420 char *p;
5421
5422 if (offset < 0)
5423 return 0;
5424
5425 p = ((char *)(get_vmcs12(vcpu))) + offset;
5426
5427 switch (vmcs_field_type(field)) {
5428 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5429 *ret = *((natural_width *)p);
5430 return 1;
5431 case VMCS_FIELD_TYPE_U16:
5432 *ret = *((u16 *)p);
5433 return 1;
5434 case VMCS_FIELD_TYPE_U32:
5435 *ret = *((u32 *)p);
5436 return 1;
5437 case VMCS_FIELD_TYPE_U64:
5438 *ret = *((u64 *)p);
5439 return 1;
5440 default:
5441 return 0; /* can never happen. */
5442 }
5443}
5444
5445/*
5446 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5447 * used before) all generate the same failure when it is missing.
5448 */
5449static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5450{
5451 struct vcpu_vmx *vmx = to_vmx(vcpu);
5452 if (vmx->nested.current_vmptr == -1ull) {
5453 nested_vmx_failInvalid(vcpu);
5454 skip_emulated_instruction(vcpu);
5455 return 0;
5456 }
5457 return 1;
5458}
5459
5460static int handle_vmread(struct kvm_vcpu *vcpu)
5461{
5462 unsigned long field;
5463 u64 field_value;
5464 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5465 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5466 gva_t gva = 0;
5467
5468 if (!nested_vmx_check_permission(vcpu) ||
5469 !nested_vmx_check_vmcs12(vcpu))
5470 return 1;
5471
5472 /* Decode instruction info and find the field to read */
5473 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5474 /* Read the field, zero-extended to a u64 field_value */
5475 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5476 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5477 skip_emulated_instruction(vcpu);
5478 return 1;
5479 }
5480 /*
5481 * Now copy part of this value to register or memory, as requested.
5482 * Note that the number of bits actually copied is 32 or 64 depending
5483 * on the guest's mode (32 or 64 bit), not on the given field's length.
5484 */
5485 if (vmx_instruction_info & (1u << 10)) {
5486 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5487 field_value);
5488 } else {
5489 if (get_vmx_mem_address(vcpu, exit_qualification,
5490 vmx_instruction_info, &gva))
5491 return 1;
5492 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5493 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5494 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5495 }
5496
5497 nested_vmx_succeed(vcpu);
5498 skip_emulated_instruction(vcpu);
5499 return 1;
5500}
5501
5502
5503static int handle_vmwrite(struct kvm_vcpu *vcpu)
5504{
5505 unsigned long field;
5506 gva_t gva;
5507 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5508 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5509 char *p;
5510 short offset;
5511 /* The value to write might be 32 or 64 bits, depending on L1's long
5512 * mode, and eventually we need to write that into a field of several
5513 * possible lengths. The code below first zero-extends the value to 64
5514 * bit (field_value), and then copies only the approriate number of
5515 * bits into the vmcs12 field.
5516 */
5517 u64 field_value = 0;
5518 struct x86_exception e;
5519
5520 if (!nested_vmx_check_permission(vcpu) ||
5521 !nested_vmx_check_vmcs12(vcpu))
5522 return 1;
5523
5524 if (vmx_instruction_info & (1u << 10))
5525 field_value = kvm_register_read(vcpu,
5526 (((vmx_instruction_info) >> 3) & 0xf));
5527 else {
5528 if (get_vmx_mem_address(vcpu, exit_qualification,
5529 vmx_instruction_info, &gva))
5530 return 1;
5531 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5532 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5533 kvm_inject_page_fault(vcpu, &e);
5534 return 1;
5535 }
5536 }
5537
5538
5539 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5540 if (vmcs_field_readonly(field)) {
5541 nested_vmx_failValid(vcpu,
5542 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5543 skip_emulated_instruction(vcpu);
5544 return 1;
5545 }
5546
5547 offset = vmcs_field_to_offset(field);
5548 if (offset < 0) {
5549 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5550 skip_emulated_instruction(vcpu);
5551 return 1;
5552 }
5553 p = ((char *) get_vmcs12(vcpu)) + offset;
5554
5555 switch (vmcs_field_type(field)) {
5556 case VMCS_FIELD_TYPE_U16:
5557 *(u16 *)p = field_value;
5558 break;
5559 case VMCS_FIELD_TYPE_U32:
5560 *(u32 *)p = field_value;
5561 break;
5562 case VMCS_FIELD_TYPE_U64:
5563 *(u64 *)p = field_value;
5564 break;
5565 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5566 *(natural_width *)p = field_value;
5567 break;
5568 default:
5569 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5570 skip_emulated_instruction(vcpu);
5571 return 1;
5572 }
5573
5574 nested_vmx_succeed(vcpu);
5575 skip_emulated_instruction(vcpu);
5576 return 1;
5577}
5578
63846663
NHE		 5579/* Emulate the VMPTRLD instruction */
5580static int handle_vmptrld(struct kvm_vcpu *vcpu)
5581{
5582 struct vcpu_vmx *vmx = to_vmx(vcpu);
5583 gva_t gva;
5584 gpa_t vmptr;
5585 struct x86_exception e;
5586
5587 if (!nested_vmx_check_permission(vcpu))
5588 return 1;
5589
5590 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5591 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5592 return 1;
5593
5594 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5595 sizeof(vmptr), &e)) {
5596 kvm_inject_page_fault(vcpu, &e);
5597 return 1;
5598 }
5599
5600 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5601 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5602 skip_emulated_instruction(vcpu);
5603 return 1;
5604 }
5605
5606 if (vmx->nested.current_vmptr != vmptr) {
5607 struct vmcs12 *new_vmcs12;
5608 struct page *page;
5609 page = nested_get_page(vcpu, vmptr);
5610 if (page == NULL) {
5611 nested_vmx_failInvalid(vcpu);
5612 skip_emulated_instruction(vcpu);
5613 return 1;
5614 }
5615 new_vmcs12 = kmap(page);
5616 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5617 kunmap(page);
5618 nested_release_page_clean(page);
5619 nested_vmx_failValid(vcpu,
5620 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5621 skip_emulated_instruction(vcpu);
5622 return 1;
5623 }
5624 if (vmx->nested.current_vmptr != -1ull) {
5625 kunmap(vmx->nested.current_vmcs12_page);
5626 nested_release_page(vmx->nested.current_vmcs12_page);
5627 }
5628
5629 vmx->nested.current_vmptr = vmptr;
5630 vmx->nested.current_vmcs12 = new_vmcs12;
5631 vmx->nested.current_vmcs12_page = page;
5632 }
5633
5634 nested_vmx_succeed(vcpu);
5635 skip_emulated_instruction(vcpu);
5636 return 1;
5637}
5638
6a4d7550
NHE		 5639/* Emulate the VMPTRST instruction */
5640static int handle_vmptrst(struct kvm_vcpu *vcpu)
5641{
5642 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5643 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5644 gva_t vmcs_gva;
5645 struct x86_exception e;
5646
5647 if (!nested_vmx_check_permission(vcpu))
5648 return 1;
5649
5650 if (get_vmx_mem_address(vcpu, exit_qualification,
5651 vmx_instruction_info, &vmcs_gva))
5652 return 1;
5653 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5654 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5655 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5656 sizeof(u64), &e)) {
5657 kvm_inject_page_fault(vcpu, &e);
5658 return 1;
5659 }
5660 nested_vmx_succeed(vcpu);
5661 skip_emulated_instruction(vcpu);
5662 return 1;
5663}
5664
6aa8b732
AK		 5665/*
5666 * The exit handlers return 1 if the exit was handled fully and guest execution
5667 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5668 * to be done to userspace and return 0.
5669 */
772e0318 5670static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5671 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5672 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5673 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5674 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5675 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5676 [EXIT_REASON_CR_ACCESS] = handle_cr,
5677 [EXIT_REASON_DR_ACCESS] = handle_dr,
5678 [EXIT_REASON_CPUID] = handle_cpuid,
5679 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5680 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5681 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5682 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5683 [EXIT_REASON_INVD] = handle_invd,
a7052897 5684 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5685 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5686 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5687 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5688 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5689 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5690 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5691 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5692 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5693 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5694 [EXIT_REASON_VMOFF] = handle_vmoff,
5695 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5696 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5697 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5698 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5699 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5700 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5701 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5702 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5703 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5704 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5705 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5706 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5707};
5708
5709static const int kvm_vmx_max_exit_handlers =
50a3485c 5710 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5711
644d711a
NHE		 5712/*
5713 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5714 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5715 * disinterest in the current event (read or write a specific MSR) by using an
5716 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5717 */
5718static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5719 struct vmcs12 *vmcs12, u32 exit_reason)
5720{
5721 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5722 gpa_t bitmap;
5723
5724 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5725 return 1;
5726
5727 /*
5728 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5729 * for the four combinations of read/write and low/high MSR numbers.
5730 * First we need to figure out which of the four to use:
5731 */
5732 bitmap = vmcs12->msr_bitmap;
5733 if (exit_reason == EXIT_REASON_MSR_WRITE)
5734 bitmap += 2048;
5735 if (msr_index >= 0xc0000000) {
5736 msr_index -= 0xc0000000;
5737 bitmap += 1024;
5738 }
5739
5740 /* Then read the msr_index'th bit from this bitmap: */
5741 if (msr_index < 1024*8) {
5742 unsigned char b;
5743 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5744 return 1 & (b >> (msr_index & 7));
5745 } else
5746 return 1; /* let L1 handle the wrong parameter */
5747}
5748
5749/*
5750 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5751 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5752 * intercept (via guest_host_mask etc.) the current event.
5753 */
5754static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5755 struct vmcs12 *vmcs12)
5756{
5757 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5758 int cr = exit_qualification & 15;
5759 int reg = (exit_qualification >> 8) & 15;
5760 unsigned long val = kvm_register_read(vcpu, reg);
5761
5762 switch ((exit_qualification >> 4) & 3) {
5763 case 0: /* mov to cr */
5764 switch (cr) {
5765 case 0:
5766 if (vmcs12->cr0_guest_host_mask &
5767 (val ^ vmcs12->cr0_read_shadow))
5768 return 1;
5769 break;
5770 case 3:
5771 if ((vmcs12->cr3_target_count >= 1 &&
5772 vmcs12->cr3_target_value0 == val) ||
5773 (vmcs12->cr3_target_count >= 2 &&
5774 vmcs12->cr3_target_value1 == val) ||
5775 (vmcs12->cr3_target_count >= 3 &&
5776 vmcs12->cr3_target_value2 == val) ||
5777 (vmcs12->cr3_target_count >= 4 &&
5778 vmcs12->cr3_target_value3 == val))
5779 return 0;
5780 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5781 return 1;
5782 break;
5783 case 4:
5784 if (vmcs12->cr4_guest_host_mask &
5785 (vmcs12->cr4_read_shadow ^ val))
5786 return 1;
5787 break;
5788 case 8:
5789 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5790 return 1;
5791 break;
5792 }
5793 break;
5794 case 2: /* clts */
5795 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5796 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5797 return 1;
5798 break;
5799 case 1: /* mov from cr */
5800 switch (cr) {
5801 case 3:
5802 if (vmcs12->cpu_based_vm_exec_control &
5803 CPU_BASED_CR3_STORE_EXITING)
5804 return 1;
5805 break;
5806 case 8:
5807 if (vmcs12->cpu_based_vm_exec_control &
5808 CPU_BASED_CR8_STORE_EXITING)
5809 return 1;
5810 break;
5811 }
5812 break;
5813 case 3: /* lmsw */
5814 /*
5815 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5816 * cr0. Other attempted changes are ignored, with no exit.
5817 */
5818 if (vmcs12->cr0_guest_host_mask & 0xe &
5819 (val ^ vmcs12->cr0_read_shadow))
5820 return 1;
5821 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5822 !(vmcs12->cr0_read_shadow & 0x1) &&
5823 (val & 0x1))
5824 return 1;
5825 break;
5826 }
5827 return 0;
5828}
5829
5830/*
5831 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5832 * should handle it ourselves in L0 (and then continue L2). Only call this
5833 * when in is_guest_mode (L2).
5834 */
5835static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5836{
5837 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5838 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5839 struct vcpu_vmx *vmx = to_vmx(vcpu);
5840 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5841
5842 if (vmx->nested.nested_run_pending)
5843 return 0;
5844
5845 if (unlikely(vmx->fail)) {
bd80158a
JK		 5846 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5847 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5848 return 1;
5849 }
5850
5851 switch (exit_reason) {
5852 case EXIT_REASON_EXCEPTION_NMI:
5853 if (!is_exception(intr_info))
5854 return 0;
5855 else if (is_page_fault(intr_info))
5856 return enable_ept;
5857 return vmcs12->exception_bitmap &
5858 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5859 case EXIT_REASON_EXTERNAL_INTERRUPT:
5860 return 0;
5861 case EXIT_REASON_TRIPLE_FAULT:
5862 return 1;
5863 case EXIT_REASON_PENDING_INTERRUPT:
5864 case EXIT_REASON_NMI_WINDOW:
5865 /*
5866 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5867 * (aka Interrupt Window Exiting) only when L1 turned it on,
5868 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5869 * Same for NMI Window Exiting.
5870 */
5871 return 1;
5872 case EXIT_REASON_TASK_SWITCH:
5873 return 1;
5874 case EXIT_REASON_CPUID:
5875 return 1;
5876 case EXIT_REASON_HLT:
5877 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5878 case EXIT_REASON_INVD:
5879 return 1;
5880 case EXIT_REASON_INVLPG:
5881 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5882 case EXIT_REASON_RDPMC:
5883 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5884 case EXIT_REASON_RDTSC:
5885 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5886 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5887 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5888 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5889 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5890 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5891 /*
5892 * VMX instructions trap unconditionally. This allows L1 to
5893 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5894 */
5895 return 1;
5896 case EXIT_REASON_CR_ACCESS:
5897 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5898 case EXIT_REASON_DR_ACCESS:
5899 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5900 case EXIT_REASON_IO_INSTRUCTION:
5901 /* TODO: support IO bitmaps */
5902 return 1;
5903 case EXIT_REASON_MSR_READ:
5904 case EXIT_REASON_MSR_WRITE:
5905 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5906 case EXIT_REASON_INVALID_STATE:
5907 return 1;
5908 case EXIT_REASON_MWAIT_INSTRUCTION:
5909 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5910 case EXIT_REASON_MONITOR_INSTRUCTION:
5911 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5912 case EXIT_REASON_PAUSE_INSTRUCTION:
5913 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5914 nested_cpu_has2(vmcs12,
5915 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5916 case EXIT_REASON_MCE_DURING_VMENTRY:
5917 return 0;
5918 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5919 return 1;
5920 case EXIT_REASON_APIC_ACCESS:
5921 return nested_cpu_has2(vmcs12,
5922 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5923 case EXIT_REASON_EPT_VIOLATION:
5924 case EXIT_REASON_EPT_MISCONFIG:
5925 return 0;
5926 case EXIT_REASON_WBINVD:
5927 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5928 case EXIT_REASON_XSETBV:
5929 return 1;
5930 default:
5931 return 1;
5932 }
5933}
5934
586f9607
AK		 5935static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5936{
5937 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5938 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5939}
5940
6aa8b732
AK		 5941/*
5942 * The guest has exited. See if we can fix it or if we need userspace
5943 * assistance.
5944 */
851ba692 5945static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5946{
29bd8a78 5947 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5948 u32 exit_reason = vmx->exit_reason;
1155f76a 5949 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5950
80ced186
MG		 5951 /* If guest state is invalid, start emulating */
5952 if (vmx->emulation_required && emulate_invalid_guest_state)
5953 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5954
b6f1250e
NHE		 5955 /*
5956 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5957 * we did not inject a still-pending event to L1 now because of
5958 * nested_run_pending, we need to re-enable this bit.
5959 */
5960 if (vmx->nested.nested_run_pending)
5961 kvm_make_request(KVM_REQ_EVENT, vcpu);
5962
509c75ea
NHE		 5963 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5964 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5965 vmx->nested.nested_run_pending = 1;
5966 else
5967 vmx->nested.nested_run_pending = 0;
5968
5969 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5970 nested_vmx_vmexit(vcpu);
5971 return 1;
5972 }
5973
5120702e
MG		 5974 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5975 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5976 vcpu->run->fail_entry.hardware_entry_failure_reason
5977 = exit_reason;
5978 return 0;
5979 }
5980
29bd8a78 5981 if (unlikely(vmx->fail)) {
851ba692
AK		 5982 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5983 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5984 = vmcs_read32(VM_INSTRUCTION_ERROR);
5985 return 0;
5986 }
6aa8b732 5987
b9bf6882
XG		 5988 /*
5989 * Note:
5990 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5991 * delivery event since it indicates guest is accessing MMIO.
5992 * The vm-exit can be triggered again after return to guest that
5993 * will cause infinite loop.
5994 */
d77c26fc 5995 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5996 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 5997 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 5998 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5999 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6000 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6001 vcpu->run->internal.ndata = 2;
6002 vcpu->run->internal.data[0] = vectoring_info;
6003 vcpu->run->internal.data[1] = exit_reason;
6004 return 0;
6005 }
3b86cd99 6006
644d711a
NHE		 6007 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6008 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6009 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6010 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6011 vmx->soft_vnmi_blocked = 0;
3b86cd99 6012 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6013 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6014 /*
6015 * This CPU don't support us in finding the end of an
6016 * NMI-blocked window if the guest runs with IRQs
6017 * disabled. So we pull the trigger after 1 s of
6018 * futile waiting, but inform the user about this.
6019 */
6020 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6021 "state on VCPU %d after 1 s timeout\n",
6022 __func__, vcpu->vcpu_id);
6023 vmx->soft_vnmi_blocked = 0;
3b86cd99 6024 }
3b86cd99
JK		 6025 }
6026
6aa8b732
AK		 6027 if (exit_reason < kvm_vmx_max_exit_handlers
6028 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6029 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6030 else {
851ba692
AK		 6031 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6032 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6033 }
6034 return 0;
6035}
6036
95ba8273 6037static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6038{
95ba8273 6039 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6040 vmcs_write32(TPR_THRESHOLD, 0);
6041 return;
6042 }
6043
95ba8273 6044 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6045}
6046
51aa01d1 6047static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6048{
00eba012
AK		 6049 u32 exit_intr_info;
6050
6051 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6052 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6053 return;
6054
c5ca8e57 6055 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6056 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6057
6058 /* Handle machine checks before interrupts are enabled */
00eba012 6059 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6060 kvm_machine_check();
6061
20f65983 6062 /* We need to handle NMIs before interrupts are enabled */
00eba012 6063 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6064 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6065 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6066 asm("int $2");
ff9d07a0
ZY		 6067 kvm_after_handle_nmi(&vmx->vcpu);
6068 }
51aa01d1 6069}
20f65983 6070
51aa01d1
AK		 6071static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6072{
c5ca8e57 6073 u32 exit_intr_info;
51aa01d1
AK		 6074 bool unblock_nmi;
6075 u8 vector;
6076 bool idtv_info_valid;
6077
6078 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6079
cf393f75 6080 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6081 if (vmx->nmi_known_unmasked)
6082 return;
c5ca8e57
AK		 6083 /*
6084 * Can't use vmx->exit_intr_info since we're not sure what
6085 * the exit reason is.
6086 */
6087 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6088 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6089 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6090 /*
7b4a25cb 6091 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6092 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6093 * a guest IRET fault.
7b4a25cb
GN		 6094 * SDM 3: 23.2.2 (September 2008)
6095 * Bit 12 is undefined in any of the following cases:
6096 * If the VM exit sets the valid bit in the IDT-vectoring
6097 * information field.
6098 * If the VM exit is due to a double fault.
cf393f75 6099 */
7b4a25cb
GN		 6100 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6101 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6102 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6103 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6104 else
6105 vmx->nmi_known_unmasked =
6106 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6107 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6108 } else if (unlikely(vmx->soft_vnmi_blocked))
6109 vmx->vnmi_blocked_time +=
6110 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6111}
6112
83422e17
AK		 6113static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6114 u32 idt_vectoring_info,
6115 int instr_len_field,
6116 int error_code_field)
51aa01d1 6117{
51aa01d1
AK		 6118 u8 vector;
6119 int type;
6120 bool idtv_info_valid;
6121
6122 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6123
37b96e98
GN		 6124 vmx->vcpu.arch.nmi_injected = false;
6125 kvm_clear_exception_queue(&vmx->vcpu);
6126 kvm_clear_interrupt_queue(&vmx->vcpu);
6127
6128 if (!idtv_info_valid)
6129 return;
6130
3842d135
AK		 6131 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6132
668f612f
AK		 6133 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6134 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6135
64a7ec06 6136 switch (type) {
37b96e98
GN		 6137 case INTR_TYPE_NMI_INTR:
6138 vmx->vcpu.arch.nmi_injected = true;
668f612f 6139 /*
7b4a25cb 6140 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6141 * Clear bit "block by NMI" before VM entry if a NMI
6142 * delivery faulted.
668f612f 6143 */
654f06fc 6144 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6145 break;
37b96e98 6146 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6147 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6148 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6149 /* fall through */
6150 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6151 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6152 u32 err = vmcs_read32(error_code_field);
37b96e98 6153 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6154 } else
6155 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6156 break;
66fd3f7f
GN		 6157 case INTR_TYPE_SOFT_INTR:
6158 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6159 vmcs_read32(instr_len_field);
66fd3f7f 6160 /* fall through */
37b96e98 6161 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6162 kvm_queue_interrupt(&vmx->vcpu, vector,
6163 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6164 break;
6165 default:
6166 break;
f7d9238f 6167 }
cf393f75
AK		 6168}
6169
83422e17
AK		 6170static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6171{
66c78ae4
NHE		 6172 if (is_guest_mode(&vmx->vcpu))
6173 return;
83422e17
AK		 6174 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6175 VM_EXIT_INSTRUCTION_LEN,
6176 IDT_VECTORING_ERROR_CODE);
6177}
6178
b463a6f7
AK		 6179static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6180{
66c78ae4
NHE		 6181 if (is_guest_mode(vcpu))
6182 return;
b463a6f7
AK		 6183 __vmx_complete_interrupts(to_vmx(vcpu),
6184 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6185 VM_ENTRY_INSTRUCTION_LEN,
6186 VM_ENTRY_EXCEPTION_ERROR_CODE);
6187
6188 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6189}
6190
d7cd9796
GN		 6191static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6192{
6193 int i, nr_msrs;
6194 struct perf_guest_switch_msr *msrs;
6195
6196 msrs = perf_guest_get_msrs(&nr_msrs);
6197
6198 if (!msrs)
6199 return;
6200
6201 for (i = 0; i < nr_msrs; i++)
6202 if (msrs[i].host == msrs[i].guest)
6203 clear_atomic_switch_msr(vmx, msrs[i].msr);
6204 else
6205 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6206 msrs[i].host);
6207}
6208
a3b5ba49 6209static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6210{
a2fa3e9f 6211 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6212 unsigned long debugctlmsr;
104f226b 6213
66c78ae4
NHE		 6214 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6215 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6216 if (vmcs12->idt_vectoring_info_field &
6217 VECTORING_INFO_VALID_MASK) {
6218 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6219 vmcs12->idt_vectoring_info_field);
6220 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6221 vmcs12->vm_exit_instruction_len);
6222 if (vmcs12->idt_vectoring_info_field &
6223 VECTORING_INFO_DELIVER_CODE_MASK)
6224 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6225 vmcs12->idt_vectoring_error_code);
6226 }
6227 }
6228
104f226b
AK		 6229 /* Record the guest's net vcpu time for enforced NMI injections. */
6230 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6231 vmx->entry_time = ktime_get();
6232
6233 /* Don't enter VMX if guest state is invalid, let the exit handler
6234 start emulation until we arrive back to a valid state */
6235 if (vmx->emulation_required && emulate_invalid_guest_state)
6236 return;
6237
6238 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6239 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6240 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6241 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6242
6243 /* When single-stepping over STI and MOV SS, we must clear the
6244 * corresponding interruptibility bits in the guest state. Otherwise
6245 * vmentry fails as it then expects bit 14 (BS) in pending debug
6246 * exceptions being set, but that's not correct for the guest debugging
6247 * case. */
6248 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6249 vmx_set_interrupt_shadow(vcpu, 0);
6250
d7cd9796 6251 atomic_switch_perf_msrs(vmx);
2a7921b7 6252 debugctlmsr = get_debugctlmsr();
d7cd9796 6253
d462b819 6254 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6255 asm(
6aa8b732 6256 /* Store host registers */
b188c81f
AK		 6257 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6258 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6259 "push %%" _ASM_CX " \n\t"
6260 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6261 "je 1f \n\t"
b188c81f 6262 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6263 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6264 "1: \n\t"
d3edefc0 6265 /* Reload cr2 if changed */
b188c81f
AK		 6266 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6267 "mov %%cr2, %%" _ASM_DX " \n\t"
6268 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6269 "je 2f \n\t"
b188c81f 6270 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6271 "2: \n\t"
6aa8b732 6272 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6273 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6274 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6275 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6276 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6277 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6278 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6279 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6280 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6281#ifdef CONFIG_X86_64
e08aa78a
AK		 6282 "mov %c[r8](%0), %%r8 \n\t"
6283 "mov %c[r9](%0), %%r9 \n\t"
6284 "mov %c[r10](%0), %%r10 \n\t"
6285 "mov %c[r11](%0), %%r11 \n\t"
6286 "mov %c[r12](%0), %%r12 \n\t"
6287 "mov %c[r13](%0), %%r13 \n\t"
6288 "mov %c[r14](%0), %%r14 \n\t"
6289 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6290#endif
b188c81f 6291 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6292
6aa8b732 6293 /* Enter guest mode */
83287ea4 6294 "jne 1f \n\t"
4ecac3fd 6295 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6296 "jmp 2f \n\t"
6297 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6298 "2: "
6aa8b732 6299 /* Save guest registers, load host registers, keep flags */
b188c81f 6300 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6301 "pop %0 \n\t"
b188c81f
AK		 6302 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6303 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6304 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6305 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6306 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6307 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6308 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6309#ifdef CONFIG_X86_64
e08aa78a
AK		 6310 "mov %%r8, %c[r8](%0) \n\t"
6311 "mov %%r9, %c[r9](%0) \n\t"
6312 "mov %%r10, %c[r10](%0) \n\t"
6313 "mov %%r11, %c[r11](%0) \n\t"
6314 "mov %%r12, %c[r12](%0) \n\t"
6315 "mov %%r13, %c[r13](%0) \n\t"
6316 "mov %%r14, %c[r14](%0) \n\t"
6317 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6318#endif
b188c81f
AK		 6319 "mov %%cr2, %%" _ASM_AX " \n\t"
6320 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6321
b188c81f 6322 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6323 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6324 ".pushsection .rodata \n\t"
6325 ".global vmx_return \n\t"
6326 "vmx_return: " _ASM_PTR " 2b \n\t"
6327 ".popsection"
e08aa78a 6328 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6329 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6330 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6331 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6332 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6333 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6334 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6335 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6336 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6337 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6338 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6339#ifdef CONFIG_X86_64
ad312c7c
ZX		 6340 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6341 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6342 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6343 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6344 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6345 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6346 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6347 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6348#endif
40712fae
AK		 6349 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6350 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6351 : "cc", "memory"
6352#ifdef CONFIG_X86_64
b188c81f 6353 , "rax", "rbx", "rdi", "rsi"
c2036300 6354 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6355#else
6356 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6357#endif
6358 );
6aa8b732 6359
2a7921b7
GN		 6360 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6361 if (debugctlmsr)
6362 update_debugctlmsr(debugctlmsr);
6363
aa67f609
AK		 6364#ifndef CONFIG_X86_64
6365 /*
6366 * The sysexit path does not restore ds/es, so we must set them to
6367 * a reasonable value ourselves.
6368 *
6369 * We can't defer this to vmx_load_host_state() since that function
6370 * may be executed in interrupt context, which saves and restore segments
6371 * around it, nullifying its effect.
6372 */
6373 loadsegment(ds, __USER_DS);
6374 loadsegment(es, __USER_DS);
6375#endif
6376
6de4f3ad 6377 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6378 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6379 | (1 << VCPU_EXREG_CPL)
aff48baa 6380 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6381 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6382 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6383 vcpu->arch.regs_dirty = 0;
6384
1155f76a
AK		 6385 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6386
66c78ae4
NHE		 6387 if (is_guest_mode(vcpu)) {
6388 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6389 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6390 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6391 vmcs12->idt_vectoring_error_code =
6392 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6393 vmcs12->vm_exit_instruction_len =
6394 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6395 }
6396 }
6397
d462b819 6398 vmx->loaded_vmcs->launched = 1;
1b6269db 6399
51aa01d1 6400 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6401 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6402
6403 vmx_complete_atomic_exit(vmx);
6404 vmx_recover_nmi_blocking(vmx);
cf393f75 6405 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6406}
6407
6aa8b732
AK		 6408static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6409{
fb3f0f51
RR		 6410 struct vcpu_vmx *vmx = to_vmx(vcpu);
6411
cdbecfc3 6412 free_vpid(vmx);
ec378aee 6413 free_nested(vmx);
d462b819 6414 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6415 kfree(vmx->guest_msrs);
6416 kvm_vcpu_uninit(vcpu);
a4770347 6417 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6418}
6419
fb3f0f51 6420static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6421{
fb3f0f51 6422 int err;
c16f862d 6423 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6424 int cpu;
6aa8b732 6425
a2fa3e9f 6426 if (!vmx)
fb3f0f51
RR		 6427 return ERR_PTR(-ENOMEM);
6428
2384d2b3
SY		 6429 allocate_vpid(vmx);
6430
fb3f0f51
RR		 6431 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6432 if (err)
6433 goto free_vcpu;
965b58a5 6434
a2fa3e9f 6435 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6436 err = -ENOMEM;
fb3f0f51 6437 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6438 goto uninit_vcpu;
6439 }
965b58a5 6440
d462b819
NHE		 6441 vmx->loaded_vmcs = &vmx->vmcs01;
6442 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6443 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6444 goto free_msrs;
d462b819
NHE		 6445 if (!vmm_exclusive)
6446 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6447 loaded_vmcs_init(vmx->loaded_vmcs);
6448 if (!vmm_exclusive)
6449 kvm_cpu_vmxoff();
a2fa3e9f 6450
15ad7146
AK		 6451 cpu = get_cpu();
6452 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6453 vmx->vcpu.cpu = cpu;
8b9cf98c 6454 err = vmx_vcpu_setup(vmx);
fb3f0f51 6455 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6456 put_cpu();
fb3f0f51
RR		 6457 if (err)
6458 goto free_vmcs;
5e4a0b3c 6459 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6460 err = alloc_apic_access_page(kvm);
6461 if (err)
5e4a0b3c 6462 goto free_vmcs;
fb3f0f51 6463
b927a3ce
SY		 6464 if (enable_ept) {
6465 if (!kvm->arch.ept_identity_map_addr)
6466 kvm->arch.ept_identity_map_addr =
6467 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6468 err = -ENOMEM;
b7ebfb05
SY		 6469 if (alloc_identity_pagetable(kvm) != 0)
6470 goto free_vmcs;
93ea5388
GN		 6471 if (!init_rmode_identity_map(kvm))
6472 goto free_vmcs;
b927a3ce 6473 }
b7ebfb05 6474
a9d30f33
NHE		 6475 vmx->nested.current_vmptr = -1ull;
6476 vmx->nested.current_vmcs12 = NULL;
6477
fb3f0f51
RR		 6478 return &vmx->vcpu;
6479
6480free_vmcs:
5f3fbc34 6481 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6482free_msrs:
fb3f0f51
RR		 6483 kfree(vmx->guest_msrs);
6484uninit_vcpu:
6485 kvm_vcpu_uninit(&vmx->vcpu);
6486free_vcpu:
cdbecfc3 6487 free_vpid(vmx);
a4770347 6488 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6489 return ERR_PTR(err);
6aa8b732
AK		 6490}
6491
002c7f7c
YS		 6492static void __init vmx_check_processor_compat(void *rtn)
6493{
6494 struct vmcs_config vmcs_conf;
6495
6496 *(int *)rtn = 0;
6497 if (setup_vmcs_config(&vmcs_conf) < 0)
6498 *(int *)rtn = -EIO;
6499 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6500 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6501 smp_processor_id());
6502 *(int *)rtn = -EIO;
6503 }
6504}
6505
67253af5
SY		 6506static int get_ept_level(void)
6507{
6508 return VMX_EPT_DEFAULT_GAW + 1;
6509}
6510
4b12f0de 6511static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6512{
4b12f0de
SY		 6513 u64 ret;
6514
522c68c4
SY		 6515 /* For VT-d and EPT combination
6516 * 1. MMIO: always map as UC
6517 * 2. EPT with VT-d:
6518 * a. VT-d without snooping control feature: can't guarantee the
6519 * result, try to trust guest.
6520 * b. VT-d with snooping control feature: snooping control feature of
6521 * VT-d engine can guarantee the cache correctness. Just set it
6522 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6523 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6524 * consistent with host MTRR
6525 */
4b12f0de
SY		 6526 if (is_mmio)
6527 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6528 else if (vcpu->kvm->arch.iommu_domain &&
6529 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6530 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6531 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6532 else
522c68c4 6533 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6534 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6535
6536 return ret;
64d4d521
SY		 6537}
6538
17cc3935 6539static int vmx_get_lpage_level(void)
344f414f 6540{
878403b7
SY		 6541 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6542 return PT_DIRECTORY_LEVEL;
6543 else
6544 /* For shadow and EPT supported 1GB page */
6545 return PT_PDPE_LEVEL;
344f414f
JR		 6546}
6547
0e851880
SY		 6548static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6549{
4e47c7a6
SY		 6550 struct kvm_cpuid_entry2 *best;
6551 struct vcpu_vmx *vmx = to_vmx(vcpu);
6552 u32 exec_control;
6553
6554 vmx->rdtscp_enabled = false;
6555 if (vmx_rdtscp_supported()) {
6556 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6557 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6558 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6559 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6560 vmx->rdtscp_enabled = true;
6561 else {
6562 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6563 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6564 exec_control);
6565 }
6566 }
6567 }
ad756a16
MJ		 6568
6569 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6570 /* Exposing INVPCID only when PCID is exposed */
6571 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6572 if (vmx_invpcid_supported() &&
4f977045 6573 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16
MJ		 6574 guest_cpuid_has_pcid(vcpu)) {
6575 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6576 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6577 exec_control);
6578 } else {
6579 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6580 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6581 exec_control);
6582 if (best)
4f977045 6583 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6584 }
0e851880
SY		 6585}
6586
d4330ef2
JR		 6587static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6588{
7b8050f5
NHE		 6589 if (func == 1 && nested)
6590 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6591}
6592
fe3ef05c
NHE		 6593/*
6594 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6595 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6596 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6597 * guest in a way that will both be appropriate to L1's requests, and our
6598 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6599 * function also has additional necessary side-effects, like setting various
6600 * vcpu->arch fields.
6601 */
6602static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6603{
6604 struct vcpu_vmx *vmx = to_vmx(vcpu);
6605 u32 exec_control;
6606
6607 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6608 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6609 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6610 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6611 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6612 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6613 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6614 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6615 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6616 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6617 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6618 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6619 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6620 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6621 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6622 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6623 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6624 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6625 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6626 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6627 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6628 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6629 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6630 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6631 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6632 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6633 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6634 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6635 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6636 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6637 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6638 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6639 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6640 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6641 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6642 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6643
6644 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6645 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6646 vmcs12->vm_entry_intr_info_field);
6647 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6648 vmcs12->vm_entry_exception_error_code);
6649 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6650 vmcs12->vm_entry_instruction_len);
6651 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6652 vmcs12->guest_interruptibility_info);
6653 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6654 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6655 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6656 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6657 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6658 vmcs12->guest_pending_dbg_exceptions);
6659 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6660 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6661
6662 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6663
6664 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6665 (vmcs_config.pin_based_exec_ctrl |
6666 vmcs12->pin_based_vm_exec_control));
6667
6668 /*
6669 * Whether page-faults are trapped is determined by a combination of
6670 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6671 * If enable_ept, L0 doesn't care about page faults and we should
6672 * set all of these to L1's desires. However, if !enable_ept, L0 does
6673 * care about (at least some) page faults, and because it is not easy
6674 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6675 * to exit on each and every L2 page fault. This is done by setting
6676 * MASK=MATCH=0 and (see below) EB.PF=1.
6677 * Note that below we don't need special code to set EB.PF beyond the
6678 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6679 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6680 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6681 *
6682 * A problem with this approach (when !enable_ept) is that L1 may be
6683 * injected with more page faults than it asked for. This could have
6684 * caused problems, but in practice existing hypervisors don't care.
6685 * To fix this, we will need to emulate the PFEC checking (on the L1
6686 * page tables), using walk_addr(), when injecting PFs to L1.
6687 */
6688 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6689 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6690 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6691 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6692
6693 if (cpu_has_secondary_exec_ctrls()) {
6694 u32 exec_control = vmx_secondary_exec_control(vmx);
6695 if (!vmx->rdtscp_enabled)
6696 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6697 /* Take the following fields only from vmcs12 */
6698 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6699 if (nested_cpu_has(vmcs12,
6700 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6701 exec_control |= vmcs12->secondary_vm_exec_control;
6702
6703 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6704 /*
6705 * Translate L1 physical address to host physical
6706 * address for vmcs02. Keep the page pinned, so this
6707 * physical address remains valid. We keep a reference
6708 * to it so we can release it later.
6709 */
6710 if (vmx->nested.apic_access_page) /* shouldn't happen */
6711 nested_release_page(vmx->nested.apic_access_page);
6712 vmx->nested.apic_access_page =
6713 nested_get_page(vcpu, vmcs12->apic_access_addr);
6714 /*
6715 * If translation failed, no matter: This feature asks
6716 * to exit when accessing the given address, and if it
6717 * can never be accessed, this feature won't do
6718 * anything anyway.
6719 */
6720 if (!vmx->nested.apic_access_page)
6721 exec_control &=
6722 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6723 else
6724 vmcs_write64(APIC_ACCESS_ADDR,
6725 page_to_phys(vmx->nested.apic_access_page));
6726 }
6727
6728 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6729 }
6730
6731
6732 /*
6733 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6734 * Some constant fields are set here by vmx_set_constant_host_state().
6735 * Other fields are different per CPU, and will be set later when
6736 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6737 */
6738 vmx_set_constant_host_state();
6739
6740 /*
6741 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6742 * entry, but only if the current (host) sp changed from the value
6743 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6744 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6745 * here we just force the write to happen on entry.
6746 */
6747 vmx->host_rsp = 0;
6748
6749 exec_control = vmx_exec_control(vmx); /* L0's desires */
6750 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6751 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6752 exec_control &= ~CPU_BASED_TPR_SHADOW;
6753 exec_control |= vmcs12->cpu_based_vm_exec_control;
6754 /*
6755 * Merging of IO and MSR bitmaps not currently supported.
6756 * Rather, exit every time.
6757 */
6758 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6759 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6760 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6761
6762 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6763
6764 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6765 * bitwise-or of what L1 wants to trap for L2, and what we want to
6766 * trap. Note that CR0.TS also needs updating - we do this later.
6767 */
6768 update_exception_bitmap(vcpu);
6769 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6770 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6771
6772 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6773 vmcs_write32(VM_EXIT_CONTROLS,
6774 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6775 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6776 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6777
6778 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6779 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6780 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6781 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6782
6783
6784 set_cr4_guest_host_mask(vmx);
6785
27fc51b2
NHE		 6786 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6787 vmcs_write64(TSC_OFFSET,
6788 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6789 else
6790 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6791
6792 if (enable_vpid) {
6793 /*
6794 * Trivially support vpid by letting L2s share their parent
6795 * L1's vpid. TODO: move to a more elaborate solution, giving
6796 * each L2 its own vpid and exposing the vpid feature to L1.
6797 */
6798 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6799 vmx_flush_tlb(vcpu);
6800 }
6801
6802 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6803 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6804 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6805 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6806 else
6807 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6808 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6809 vmx_set_efer(vcpu, vcpu->arch.efer);
6810
6811 /*
6812 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6813 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6814 * The CR0_READ_SHADOW is what L2 should have expected to read given
6815 * the specifications by L1; It's not enough to take
6816 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6817 * have more bits than L1 expected.
6818 */
6819 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6820 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6821
6822 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6823 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6824
6825 /* shadow page tables on either EPT or shadow page tables */
6826 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6827 kvm_mmu_reset_context(vcpu);
6828
6829 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6830 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6831}
6832
cd232ad0
NHE		 6833/*
6834 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6835 * for running an L2 nested guest.
6836 */
6837static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6838{
6839 struct vmcs12 *vmcs12;
6840 struct vcpu_vmx *vmx = to_vmx(vcpu);
6841 int cpu;
6842 struct loaded_vmcs *vmcs02;
6843
6844 if (!nested_vmx_check_permission(vcpu) ||
6845 !nested_vmx_check_vmcs12(vcpu))
6846 return 1;
6847
6848 skip_emulated_instruction(vcpu);
6849 vmcs12 = get_vmcs12(vcpu);
6850
7c177938
NHE		 6851 /*
6852 * The nested entry process starts with enforcing various prerequisites
6853 * on vmcs12 as required by the Intel SDM, and act appropriately when
6854 * they fail: As the SDM explains, some conditions should cause the
6855 * instruction to fail, while others will cause the instruction to seem
6856 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6857 * To speed up the normal (success) code path, we should avoid checking
6858 * for misconfigurations which will anyway be caught by the processor
6859 * when using the merged vmcs02.
6860 */
6861 if (vmcs12->launch_state == launch) {
6862 nested_vmx_failValid(vcpu,
6863 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6864 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6865 return 1;
6866 }
6867
6868 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6869 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6870 /*TODO: Also verify bits beyond physical address width are 0*/
6871 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6872 return 1;
6873 }
6874
6875 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6876 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6877 /*TODO: Also verify bits beyond physical address width are 0*/
6878 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6879 return 1;
6880 }
6881
6882 if (vmcs12->vm_entry_msr_load_count > 0 ||
6883 vmcs12->vm_exit_msr_load_count > 0 ||
6884 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6885 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6886 __func__);
7c177938
NHE		 6887 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6888 return 1;
6889 }
6890
6891 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6892 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6893 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6894 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6895 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6896 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6897 !vmx_control_verify(vmcs12->vm_exit_controls,
6898 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6899 !vmx_control_verify(vmcs12->vm_entry_controls,
6900 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6901 {
6902 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6903 return 1;
6904 }
6905
6906 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6907 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6908 nested_vmx_failValid(vcpu,
6909 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6910 return 1;
6911 }
6912
6913 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6914 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6915 nested_vmx_entry_failure(vcpu, vmcs12,
6916 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6917 return 1;
6918 }
6919 if (vmcs12->vmcs_link_pointer != -1ull) {
6920 nested_vmx_entry_failure(vcpu, vmcs12,
6921 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6922 return 1;
6923 }
6924
6925 /*
6926 * We're finally done with prerequisite checking, and can start with
6927 * the nested entry.
6928 */
6929
cd232ad0
NHE		 6930 vmcs02 = nested_get_current_vmcs02(vmx);
6931 if (!vmcs02)
6932 return -ENOMEM;
6933
6934 enter_guest_mode(vcpu);
6935
6936 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6937
6938 cpu = get_cpu();
6939 vmx->loaded_vmcs = vmcs02;
6940 vmx_vcpu_put(vcpu);
6941 vmx_vcpu_load(vcpu, cpu);
6942 vcpu->cpu = cpu;
6943 put_cpu();
6944
6945 vmcs12->launch_state = 1;
6946
6947 prepare_vmcs02(vcpu, vmcs12);
6948
6949 /*
6950 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6951 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6952 * returned as far as L1 is concerned. It will only return (and set
6953 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6954 */
6955 return 1;
6956}
6957
4704d0be
NHE		 6958/*
6959 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6960 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6961 * This function returns the new value we should put in vmcs12.guest_cr0.
6962 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6963 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6964 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6965 * didn't trap the bit, because if L1 did, so would L0).
6966 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6967 * been modified by L2, and L1 knows it. So just leave the old value of
6968 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6969 * isn't relevant, because if L0 traps this bit it can set it to anything.
6970 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6971 * changed these bits, and therefore they need to be updated, but L0
6972 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6973 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6974 */
6975static inline unsigned long
6976vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6977{
6978 return
6979 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6980 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6981 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6982 vcpu->arch.cr0_guest_owned_bits));
6983}
6984
6985static inline unsigned long
6986vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6987{
6988 return
6989 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6990 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6991 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6992 vcpu->arch.cr4_guest_owned_bits));
6993}
6994
6995/*
6996 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6997 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6998 * and this function updates it to reflect the changes to the guest state while
6999 * L2 was running (and perhaps made some exits which were handled directly by L0
7000 * without going back to L1), and to reflect the exit reason.
7001 * Note that we do not have to copy here all VMCS fields, just those that
7002 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7003 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7004 * which already writes to vmcs12 directly.
7005 */
7006void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7007{
7008 /* update guest state fields: */
7009 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7010 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7011
7012 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7013 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7014 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7015 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7016
7017 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7018 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7019 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7020 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7021 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7022 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7023 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7024 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7025 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7026 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7027 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7028 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7029 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7030 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7031 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7032 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7033 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7034 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7035 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7036 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7037 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7038 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7039 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7040 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7041 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7042 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7043 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7044 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7045 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7046 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7047 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7048 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7049 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7050 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7051 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7052 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7053
7054 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7055 vmcs12->guest_interruptibility_info =
7056 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7057 vmcs12->guest_pending_dbg_exceptions =
7058 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7059
7060 /* TODO: These cannot have changed unless we have MSR bitmaps and
7061 * the relevant bit asks not to trap the change */
7062 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7063 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7064 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7065 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7066 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7067 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7068
7069 /* update exit information fields: */
7070
7071 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7072 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7073
7074 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7075 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7076 vmcs12->idt_vectoring_info_field =
7077 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7078 vmcs12->idt_vectoring_error_code =
7079 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7080 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7081 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7082
7083 /* clear vm-entry fields which are to be cleared on exit */
7084 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7085 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7086}
7087
7088/*
7089 * A part of what we need to when the nested L2 guest exits and we want to
7090 * run its L1 parent, is to reset L1's guest state to the host state specified
7091 * in vmcs12.
7092 * This function is to be called not only on normal nested exit, but also on
7093 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7094 * Failures During or After Loading Guest State").
7095 * This function should be called when the active VMCS is L1's (vmcs01).
7096 */
7097void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7098{
7099 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7100 vcpu->arch.efer = vmcs12->host_ia32_efer;
7101 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7102 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7103 else
7104 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7105 vmx_set_efer(vcpu, vcpu->arch.efer);
7106
7107 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7108 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7109 /*
7110 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7111 * actually changed, because it depends on the current state of
7112 * fpu_active (which may have changed).
7113 * Note that vmx_set_cr0 refers to efer set above.
7114 */
7115 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7116 /*
7117 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7118 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7119 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7120 */
7121 update_exception_bitmap(vcpu);
7122 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7123 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7124
7125 /*
7126 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7127 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7128 */
7129 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7130 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7131
7132 /* shadow page tables on either EPT or shadow page tables */
7133 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7134 kvm_mmu_reset_context(vcpu);
7135
7136 if (enable_vpid) {
7137 /*
7138 * Trivially support vpid by letting L2s share their parent
7139 * L1's vpid. TODO: move to a more elaborate solution, giving
7140 * each L2 its own vpid and exposing the vpid feature to L1.
7141 */
7142 vmx_flush_tlb(vcpu);
7143 }
7144
7145
7146 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7147 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7148 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7149 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7150 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7151 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7152 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7153 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7154 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7155 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7156 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7157 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7158 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7159 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7160 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7161
7162 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7163 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7164 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7165 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7166 vmcs12->host_ia32_perf_global_ctrl);
7167}
7168
7169/*
7170 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7171 * and modify vmcs12 to make it see what it would expect to see there if
7172 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7173 */
7174static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7175{
7176 struct vcpu_vmx *vmx = to_vmx(vcpu);
7177 int cpu;
7178 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7179
7180 leave_guest_mode(vcpu);
7181 prepare_vmcs12(vcpu, vmcs12);
7182
7183 cpu = get_cpu();
7184 vmx->loaded_vmcs = &vmx->vmcs01;
7185 vmx_vcpu_put(vcpu);
7186 vmx_vcpu_load(vcpu, cpu);
7187 vcpu->cpu = cpu;
7188 put_cpu();
7189
7190 /* if no vmcs02 cache requested, remove the one we used */
7191 if (VMCS02_POOL_SIZE == 0)
7192 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7193
7194 load_vmcs12_host_state(vcpu, vmcs12);
7195
27fc51b2 7196 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7197 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7198
7199 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7200 vmx->host_rsp = 0;
7201
7202 /* Unpin physical memory we referred to in vmcs02 */
7203 if (vmx->nested.apic_access_page) {
7204 nested_release_page(vmx->nested.apic_access_page);
7205 vmx->nested.apic_access_page = 0;
7206 }
7207
7208 /*
7209 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7210 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7211 * success or failure flag accordingly.
7212 */
7213 if (unlikely(vmx->fail)) {
7214 vmx->fail = 0;
7215 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7216 } else
7217 nested_vmx_succeed(vcpu);
7218}
7219
7c177938
NHE		 7220/*
7221 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7222 * 23.7 "VM-entry failures during or after loading guest state" (this also
7223 * lists the acceptable exit-reason and exit-qualification parameters).
7224 * It should only be called before L2 actually succeeded to run, and when
7225 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7226 */
7227static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7228 struct vmcs12 *vmcs12,
7229 u32 reason, unsigned long qualification)
7230{
7231 load_vmcs12_host_state(vcpu, vmcs12);
7232 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7233 vmcs12->exit_qualification = qualification;
7234 nested_vmx_succeed(vcpu);
7235}
7236
8a76d7f2
JR		 7237static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7238 struct x86_instruction_info *info,
7239 enum x86_intercept_stage stage)
7240{
7241 return X86EMUL_CONTINUE;
7242}
7243
cbdd1bea 7244static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7245 .cpu_has_kvm_support = cpu_has_kvm_support,
7246 .disabled_by_bios = vmx_disabled_by_bios,
7247 .hardware_setup = hardware_setup,
7248 .hardware_unsetup = hardware_unsetup,
002c7f7c 7249 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7250 .hardware_enable = hardware_enable,
7251 .hardware_disable = hardware_disable,
04547156 7252 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7253
7254 .vcpu_create = vmx_create_vcpu,
7255 .vcpu_free = vmx_free_vcpu,
04d2cc77 7256 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7257
04d2cc77 7258 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7259 .vcpu_load = vmx_vcpu_load,
7260 .vcpu_put = vmx_vcpu_put,
7261
c8639010 7262 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7263 .get_msr = vmx_get_msr,
7264 .set_msr = vmx_set_msr,
7265 .get_segment_base = vmx_get_segment_base,
7266 .get_segment = vmx_get_segment,
7267 .set_segment = vmx_set_segment,
2e4d2653 7268 .get_cpl = vmx_get_cpl,
6aa8b732 7269 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7270 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7271 .decache_cr3 = vmx_decache_cr3,
25c4c276 7272 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7273 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7274 .set_cr3 = vmx_set_cr3,
7275 .set_cr4 = vmx_set_cr4,
6aa8b732 7276 .set_efer = vmx_set_efer,
6aa8b732
AK		 7277 .get_idt = vmx_get_idt,
7278 .set_idt = vmx_set_idt,
7279 .get_gdt = vmx_get_gdt,
7280 .set_gdt = vmx_set_gdt,
020df079 7281 .set_dr7 = vmx_set_dr7,
5fdbf976 7282 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7283 .get_rflags = vmx_get_rflags,
7284 .set_rflags = vmx_set_rflags,
ebcbab4c 7285 .fpu_activate = vmx_fpu_activate,
02daab21 7286 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7287
7288 .tlb_flush = vmx_flush_tlb,
6aa8b732 7289
6aa8b732 7290 .run = vmx_vcpu_run,
6062d012 7291 .handle_exit = vmx_handle_exit,
6aa8b732 7292 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7293 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7294 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7295 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7296 .set_irq = vmx_inject_irq,
95ba8273 7297 .set_nmi = vmx_inject_nmi,
298101da 7298 .queue_exception = vmx_queue_exception,
b463a6f7 7299 .cancel_injection = vmx_cancel_injection,
78646121 7300 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7301 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7302 .get_nmi_mask = vmx_get_nmi_mask,
7303 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7304 .enable_nmi_window = enable_nmi_window,
7305 .enable_irq_window = enable_irq_window,
7306 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7307
cbc94022 7308 .set_tss_addr = vmx_set_tss_addr,
67253af5 7309 .get_tdp_level = get_ept_level,
4b12f0de 7310 .get_mt_mask = vmx_get_mt_mask,
229456fc 7311
586f9607 7312 .get_exit_info = vmx_get_exit_info,
586f9607 7313
17cc3935 7314 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7315
7316 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7317
7318 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7319 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7320
7321 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7322
7323 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7324
4051b188 7325 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7326 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7327 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7328 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7329 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7330
7331 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7332
7333 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7334};
7335
7336static int __init vmx_init(void)
7337{
26bb0981
AK		 7338 int r, i;
7339
7340 rdmsrl_safe(MSR_EFER, &host_efer);
7341
7342 for (i = 0; i < NR_VMX_MSR; ++i)
7343 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7344
3e7c73e9 7345 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7346 if (!vmx_io_bitmap_a)
7347 return -ENOMEM;
7348
2106a548
GC		 7349 r = -ENOMEM;
7350
3e7c73e9 7351 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7352 if (!vmx_io_bitmap_b)
fdef3ad1 7353 goto out;
fdef3ad1 7354
5897297b 7355 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7356 if (!vmx_msr_bitmap_legacy)
25c5f225 7357 goto out1;
2106a548 7358
25c5f225 7359
5897297b 7360 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7361 if (!vmx_msr_bitmap_longmode)
5897297b 7362 goto out2;
2106a548 7363
5897297b 7364
fdef3ad1
HQ		 7365 /*
7366 * Allow direct access to the PC debug port (it is often used for I/O
7367 * delays, but the vmexits simply slow things down).
7368 */
3e7c73e9
AK		 7369 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7370 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7371
3e7c73e9 7372 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7373
5897297b
AK		 7374 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7375 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7376
2384d2b3
SY		 7377 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7378
0ee75bea
AK		 7379 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7380 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7381 if (r)
5897297b 7382 goto out3;
25c5f225 7383
5897297b
AK		 7384 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7385 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7386 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7387 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7388 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7389 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7390
089d034e 7391 if (enable_ept) {
3f6d8c8a
XH		 7392 kvm_mmu_set_mask_ptes(0ull,
7393 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7394 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7395 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7396 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7397 kvm_enable_tdp();
7398 } else
7399 kvm_disable_tdp();
1439442c 7400
fdef3ad1
HQ		 7401 return 0;
7402
5897297b
AK		 7403out3:
7404 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7405out2:
5897297b 7406 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7407out1:
3e7c73e9 7408 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7409out:
3e7c73e9 7410 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7411 return r;
6aa8b732
AK		 7412}
7413
7414static void __exit vmx_exit(void)
7415{
5897297b
AK		 7416 free_page((unsigned long)vmx_msr_bitmap_legacy);
7417 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7418 free_page((unsigned long)vmx_io_bitmap_b);
7419 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7420
cb498ea2 7421 kvm_exit();
6aa8b732
AK		 7422}
7423
7424module_init(vmx_init)
7425module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)