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KVM: VMX: reset CPL only on CS register write.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
801d3424
NHE		 87/*
88 * If nested=1, nested virtualization is supported, i.e., guests may use
89 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
90 * use VMX instructions.
91 */
476bc001 92static bool __read_mostly nested = 0;
801d3424
NHE		 93module_param(nested, bool, S_IRUGO);
94
cdc0e244
AK		 95#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
96 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
97#define KVM_GUEST_CR0_MASK \
98 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
99#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 100 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 101#define KVM_VM_CR0_ALWAYS_ON \
102 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 103#define KVM_CR4_GUEST_OWNED_BITS \
104 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
105 | X86_CR4_OSXMMEXCPT)
106
cdc0e244
AK		 107#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
108#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109
78ac8b47
AK		 110#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111
4b8d54f9
ZE		 112/*
113 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
114 * ple_gap: upper bound on the amount of time between two successive
115 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 116 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 117 * ple_window: upper bound on the amount of time a guest is allowed to execute
118 * in a PAUSE loop. Tests indicate that most spinlocks are held for
119 * less than 2^12 cycles
120 * Time is measured based on a counter that runs at the same rate as the TSC,
121 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 */
00c25bce 123#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 124#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
125static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
126module_param(ple_gap, int, S_IRUGO);
127
128static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
129module_param(ple_window, int, S_IRUGO);
130
83287ea4
AK		 131extern const ulong vmx_return;
132
8bf00a52 133#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 134#define VMCS02_POOL_SIZE 1
61d2ef2c 135
a2fa3e9f
GH		 136struct vmcs {
137 u32 revision_id;
138 u32 abort;
139 char data[0];
140};
141
d462b819
NHE		 142/*
143 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
144 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
145 * loaded on this CPU (so we can clear them if the CPU goes down).
146 */
147struct loaded_vmcs {
148 struct vmcs *vmcs;
149 int cpu;
150 int launched;
151 struct list_head loaded_vmcss_on_cpu_link;
152};
153
26bb0981
AK		 154struct shared_msr_entry {
155 unsigned index;
156 u64 data;
d5696725 157 u64 mask;
26bb0981
AK		 158};
159
a9d30f33
NHE		 160/*
161 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
162 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
163 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
164 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
165 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
166 * More than one of these structures may exist, if L1 runs multiple L2 guests.
167 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
168 * underlying hardware which will be used to run L2.
169 * This structure is packed to ensure that its layout is identical across
170 * machines (necessary for live migration).
171 * If there are changes in this struct, VMCS12_REVISION must be changed.
172 */
22bd0358 173typedef u64 natural_width;
a9d30f33
NHE		 174struct __packed vmcs12 {
175 /* According to the Intel spec, a VMCS region must start with the
176 * following two fields. Then follow implementation-specific data.
177 */
178 u32 revision_id;
179 u32 abort;
22bd0358 180
27d6c865
NHE		 181 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
182 u32 padding[7]; /* room for future expansion */
183
22bd0358
NHE		 184 u64 io_bitmap_a;
185 u64 io_bitmap_b;
186 u64 msr_bitmap;
187 u64 vm_exit_msr_store_addr;
188 u64 vm_exit_msr_load_addr;
189 u64 vm_entry_msr_load_addr;
190 u64 tsc_offset;
191 u64 virtual_apic_page_addr;
192 u64 apic_access_addr;
193 u64 ept_pointer;
194 u64 guest_physical_address;
195 u64 vmcs_link_pointer;
196 u64 guest_ia32_debugctl;
197 u64 guest_ia32_pat;
198 u64 guest_ia32_efer;
199 u64 guest_ia32_perf_global_ctrl;
200 u64 guest_pdptr0;
201 u64 guest_pdptr1;
202 u64 guest_pdptr2;
203 u64 guest_pdptr3;
204 u64 host_ia32_pat;
205 u64 host_ia32_efer;
206 u64 host_ia32_perf_global_ctrl;
207 u64 padding64[8]; /* room for future expansion */
208 /*
209 * To allow migration of L1 (complete with its L2 guests) between
210 * machines of different natural widths (32 or 64 bit), we cannot have
211 * unsigned long fields with no explict size. We use u64 (aliased
212 * natural_width) instead. Luckily, x86 is little-endian.
213 */
214 natural_width cr0_guest_host_mask;
215 natural_width cr4_guest_host_mask;
216 natural_width cr0_read_shadow;
217 natural_width cr4_read_shadow;
218 natural_width cr3_target_value0;
219 natural_width cr3_target_value1;
220 natural_width cr3_target_value2;
221 natural_width cr3_target_value3;
222 natural_width exit_qualification;
223 natural_width guest_linear_address;
224 natural_width guest_cr0;
225 natural_width guest_cr3;
226 natural_width guest_cr4;
227 natural_width guest_es_base;
228 natural_width guest_cs_base;
229 natural_width guest_ss_base;
230 natural_width guest_ds_base;
231 natural_width guest_fs_base;
232 natural_width guest_gs_base;
233 natural_width guest_ldtr_base;
234 natural_width guest_tr_base;
235 natural_width guest_gdtr_base;
236 natural_width guest_idtr_base;
237 natural_width guest_dr7;
238 natural_width guest_rsp;
239 natural_width guest_rip;
240 natural_width guest_rflags;
241 natural_width guest_pending_dbg_exceptions;
242 natural_width guest_sysenter_esp;
243 natural_width guest_sysenter_eip;
244 natural_width host_cr0;
245 natural_width host_cr3;
246 natural_width host_cr4;
247 natural_width host_fs_base;
248 natural_width host_gs_base;
249 natural_width host_tr_base;
250 natural_width host_gdtr_base;
251 natural_width host_idtr_base;
252 natural_width host_ia32_sysenter_esp;
253 natural_width host_ia32_sysenter_eip;
254 natural_width host_rsp;
255 natural_width host_rip;
256 natural_width paddingl[8]; /* room for future expansion */
257 u32 pin_based_vm_exec_control;
258 u32 cpu_based_vm_exec_control;
259 u32 exception_bitmap;
260 u32 page_fault_error_code_mask;
261 u32 page_fault_error_code_match;
262 u32 cr3_target_count;
263 u32 vm_exit_controls;
264 u32 vm_exit_msr_store_count;
265 u32 vm_exit_msr_load_count;
266 u32 vm_entry_controls;
267 u32 vm_entry_msr_load_count;
268 u32 vm_entry_intr_info_field;
269 u32 vm_entry_exception_error_code;
270 u32 vm_entry_instruction_len;
271 u32 tpr_threshold;
272 u32 secondary_vm_exec_control;
273 u32 vm_instruction_error;
274 u32 vm_exit_reason;
275 u32 vm_exit_intr_info;
276 u32 vm_exit_intr_error_code;
277 u32 idt_vectoring_info_field;
278 u32 idt_vectoring_error_code;
279 u32 vm_exit_instruction_len;
280 u32 vmx_instruction_info;
281 u32 guest_es_limit;
282 u32 guest_cs_limit;
283 u32 guest_ss_limit;
284 u32 guest_ds_limit;
285 u32 guest_fs_limit;
286 u32 guest_gs_limit;
287 u32 guest_ldtr_limit;
288 u32 guest_tr_limit;
289 u32 guest_gdtr_limit;
290 u32 guest_idtr_limit;
291 u32 guest_es_ar_bytes;
292 u32 guest_cs_ar_bytes;
293 u32 guest_ss_ar_bytes;
294 u32 guest_ds_ar_bytes;
295 u32 guest_fs_ar_bytes;
296 u32 guest_gs_ar_bytes;
297 u32 guest_ldtr_ar_bytes;
298 u32 guest_tr_ar_bytes;
299 u32 guest_interruptibility_info;
300 u32 guest_activity_state;
301 u32 guest_sysenter_cs;
302 u32 host_ia32_sysenter_cs;
303 u32 padding32[8]; /* room for future expansion */
304 u16 virtual_processor_id;
305 u16 guest_es_selector;
306 u16 guest_cs_selector;
307 u16 guest_ss_selector;
308 u16 guest_ds_selector;
309 u16 guest_fs_selector;
310 u16 guest_gs_selector;
311 u16 guest_ldtr_selector;
312 u16 guest_tr_selector;
313 u16 host_es_selector;
314 u16 host_cs_selector;
315 u16 host_ss_selector;
316 u16 host_ds_selector;
317 u16 host_fs_selector;
318 u16 host_gs_selector;
319 u16 host_tr_selector;
a9d30f33
NHE		 320};
321
322/*
323 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
324 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
325 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 */
327#define VMCS12_REVISION 0x11e57ed0
328
329/*
330 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
331 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
332 * current implementation, 4K are reserved to avoid future complications.
333 */
334#define VMCS12_SIZE 0x1000
335
ff2f6fe9
NHE		 336/* Used to remember the last vmcs02 used for some recently used vmcs12s */
337struct vmcs02_list {
338 struct list_head list;
339 gpa_t vmptr;
340 struct loaded_vmcs vmcs02;
341};
342
ec378aee
NHE		 343/*
344 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
345 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 */
347struct nested_vmx {
348 /* Has the level1 guest done vmxon? */
349 bool vmxon;
a9d30f33
NHE		 350
351 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 gpa_t current_vmptr;
353 /* The host-usable pointer to the above */
354 struct page *current_vmcs12_page;
355 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 356
357 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
358 struct list_head vmcs02_pool;
359 int vmcs02_num;
fe3ef05c 360 u64 vmcs01_tsc_offset;
644d711a
NHE		 361 /* L2 must run next, and mustn't decide to exit to L1. */
362 bool nested_run_pending;
fe3ef05c
NHE		 363 /*
364 * Guest pages referred to in vmcs02 with host-physical pointers, so
365 * we must keep them pinned while L2 runs.
366 */
367 struct page *apic_access_page;
ec378aee
NHE		 368};
369
a2fa3e9f 370struct vcpu_vmx {
fb3f0f51 371 struct kvm_vcpu vcpu;
313dbd49 372 unsigned long host_rsp;
29bd8a78 373 u8 fail;
69c73028 374 u8 cpl;
9d58b931 375 bool nmi_known_unmasked;
51aa01d1 376 u32 exit_intr_info;
1155f76a 377 u32 idt_vectoring_info;
6de12732 378 ulong rflags;
26bb0981 379 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 380 int nmsrs;
381 int save_nmsrs;
a2fa3e9f 382#ifdef CONFIG_X86_64
44ea2b17
AK		 383 u64 msr_host_kernel_gs_base;
384 u64 msr_guest_kernel_gs_base;
a2fa3e9f 385#endif
d462b819
NHE		 386 /*
387 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
388 * non-nested (L1) guest, it always points to vmcs01. For a nested
389 * guest (L2), it points to a different VMCS.
390 */
391 struct loaded_vmcs vmcs01;
392 struct loaded_vmcs *loaded_vmcs;
393 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 394 struct msr_autoload {
395 unsigned nr;
396 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
397 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
398 } msr_autoload;
a2fa3e9f
GH		 399 struct {
400 int loaded;
401 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 402#ifdef CONFIG_X86_64
403 u16 ds_sel, es_sel;
404#endif
152d3f2f
LV		 405 int gs_ldt_reload_needed;
406 int fs_reload_needed;
d77c26fc 407 } host_state;
9c8cba37 408 struct {
7ffd92c5 409 int vm86_active;
78ac8b47 410 ulong save_rflags;
f5f7b2fe
AK		 411 struct kvm_segment segs[8];
412 } rmode;
413 struct {
414 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 415 struct kvm_save_segment {
416 u16 selector;
417 unsigned long base;
418 u32 limit;
419 u32 ar;
f5f7b2fe 420 } seg[8];
2fb92db1 421 } segment_cache;
2384d2b3 422 int vpid;
04fa4d32 423 bool emulation_required;
3b86cd99
JK		 424
425 /* Support for vnmi-less CPUs */
426 int soft_vnmi_blocked;
427 ktime_t entry_time;
428 s64 vnmi_blocked_time;
a0861c02 429 u32 exit_reason;
4e47c7a6
SY		 430
431 bool rdtscp_enabled;
ec378aee
NHE		 432
433 /* Support for a guest hypervisor (nested VMX) */
434 struct nested_vmx nested;
a2fa3e9f
GH		 435};
436
2fb92db1
AK		 437enum segment_cache_field {
438 SEG_FIELD_SEL = 0,
439 SEG_FIELD_BASE = 1,
440 SEG_FIELD_LIMIT = 2,
441 SEG_FIELD_AR = 3,
442
443 SEG_FIELD_NR = 4
444};
445
a2fa3e9f
GH		 446static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
447{
fb3f0f51 448 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 449}
450
22bd0358
NHE		 451#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
452#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
453#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
454 [number##_HIGH] = VMCS12_OFFSET(name)+4
455
772e0318 456static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 457 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
458 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
459 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
460 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
461 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
462 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
463 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
464 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
465 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
466 FIELD(HOST_ES_SELECTOR, host_es_selector),
467 FIELD(HOST_CS_SELECTOR, host_cs_selector),
468 FIELD(HOST_SS_SELECTOR, host_ss_selector),
469 FIELD(HOST_DS_SELECTOR, host_ds_selector),
470 FIELD(HOST_FS_SELECTOR, host_fs_selector),
471 FIELD(HOST_GS_SELECTOR, host_gs_selector),
472 FIELD(HOST_TR_SELECTOR, host_tr_selector),
473 FIELD64(IO_BITMAP_A, io_bitmap_a),
474 FIELD64(IO_BITMAP_B, io_bitmap_b),
475 FIELD64(MSR_BITMAP, msr_bitmap),
476 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
477 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
478 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
479 FIELD64(TSC_OFFSET, tsc_offset),
480 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
481 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
482 FIELD64(EPT_POINTER, ept_pointer),
483 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
484 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
485 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
486 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
487 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
488 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
489 FIELD64(GUEST_PDPTR0, guest_pdptr0),
490 FIELD64(GUEST_PDPTR1, guest_pdptr1),
491 FIELD64(GUEST_PDPTR2, guest_pdptr2),
492 FIELD64(GUEST_PDPTR3, guest_pdptr3),
493 FIELD64(HOST_IA32_PAT, host_ia32_pat),
494 FIELD64(HOST_IA32_EFER, host_ia32_efer),
495 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
496 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
497 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
498 FIELD(EXCEPTION_BITMAP, exception_bitmap),
499 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
500 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
501 FIELD(CR3_TARGET_COUNT, cr3_target_count),
502 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
503 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
504 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
505 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
506 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
507 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
508 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
509 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
510 FIELD(TPR_THRESHOLD, tpr_threshold),
511 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
512 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
513 FIELD(VM_EXIT_REASON, vm_exit_reason),
514 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
515 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
516 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
517 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
518 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
519 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
520 FIELD(GUEST_ES_LIMIT, guest_es_limit),
521 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
522 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
523 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
524 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
525 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
526 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
527 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
528 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
529 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
530 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
531 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
532 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
533 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
534 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
535 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
536 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
537 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
538 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
539 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
540 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
541 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
542 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
543 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
544 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
545 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
546 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
547 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
548 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
549 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
550 FIELD(EXIT_QUALIFICATION, exit_qualification),
551 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
552 FIELD(GUEST_CR0, guest_cr0),
553 FIELD(GUEST_CR3, guest_cr3),
554 FIELD(GUEST_CR4, guest_cr4),
555 FIELD(GUEST_ES_BASE, guest_es_base),
556 FIELD(GUEST_CS_BASE, guest_cs_base),
557 FIELD(GUEST_SS_BASE, guest_ss_base),
558 FIELD(GUEST_DS_BASE, guest_ds_base),
559 FIELD(GUEST_FS_BASE, guest_fs_base),
560 FIELD(GUEST_GS_BASE, guest_gs_base),
561 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
562 FIELD(GUEST_TR_BASE, guest_tr_base),
563 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
564 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
565 FIELD(GUEST_DR7, guest_dr7),
566 FIELD(GUEST_RSP, guest_rsp),
567 FIELD(GUEST_RIP, guest_rip),
568 FIELD(GUEST_RFLAGS, guest_rflags),
569 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
570 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
571 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
572 FIELD(HOST_CR0, host_cr0),
573 FIELD(HOST_CR3, host_cr3),
574 FIELD(HOST_CR4, host_cr4),
575 FIELD(HOST_FS_BASE, host_fs_base),
576 FIELD(HOST_GS_BASE, host_gs_base),
577 FIELD(HOST_TR_BASE, host_tr_base),
578 FIELD(HOST_GDTR_BASE, host_gdtr_base),
579 FIELD(HOST_IDTR_BASE, host_idtr_base),
580 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
581 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
582 FIELD(HOST_RSP, host_rsp),
583 FIELD(HOST_RIP, host_rip),
584};
585static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
586
587static inline short vmcs_field_to_offset(unsigned long field)
588{
589 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
590 return -1;
591 return vmcs_field_to_offset_table[field];
592}
593
a9d30f33
NHE		 594static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
595{
596 return to_vmx(vcpu)->nested.current_vmcs12;
597}
598
599static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
600{
601 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 602 if (is_error_page(page))
a9d30f33 603 return NULL;
32cad84f 604
a9d30f33
NHE		 605 return page;
606}
607
608static void nested_release_page(struct page *page)
609{
610 kvm_release_page_dirty(page);
611}
612
613static void nested_release_page_clean(struct page *page)
614{
615 kvm_release_page_clean(page);
616}
617
4e1096d2 618static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 619static void kvm_cpu_vmxon(u64 addr);
620static void kvm_cpu_vmxoff(void);
aff48baa 621static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 622static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 623static void vmx_set_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
625static void vmx_get_segment(struct kvm_vcpu *vcpu,
626 struct kvm_segment *var, int seg);
d99e4152
GN		 627static bool guest_state_valid(struct kvm_vcpu *vcpu);
628static u32 vmx_segment_access_rights(struct kvm_segment *var);
75880a01 629
6aa8b732
AK		 630static DEFINE_PER_CPU(struct vmcs *, vmxarea);
631static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 632/*
633 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
634 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
635 */
636static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 637static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 638
3e7c73e9
AK		 639static unsigned long *vmx_io_bitmap_a;
640static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 641static unsigned long *vmx_msr_bitmap_legacy;
642static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 643
110312c8 644static bool cpu_has_load_ia32_efer;
8bf00a52 645static bool cpu_has_load_perf_global_ctrl;
110312c8 646
2384d2b3
SY		 647static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
648static DEFINE_SPINLOCK(vmx_vpid_lock);
649
1c3d14fe 650static struct vmcs_config {
6aa8b732
AK		 651 int size;
652 int order;
653 u32 revision_id;
1c3d14fe
YS		 654 u32 pin_based_exec_ctrl;
655 u32 cpu_based_exec_ctrl;
f78e0e2e 656 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 657 u32 vmexit_ctrl;
658 u32 vmentry_ctrl;
659} vmcs_config;
6aa8b732 660
efff9e53 661static struct vmx_capability {
d56f546d
SY		 662 u32 ept;
663 u32 vpid;
664} vmx_capability;
665
6aa8b732
AK		 666#define VMX_SEGMENT_FIELD(seg) \
667 [VCPU_SREG_##seg] = { \
668 .selector = GUEST_##seg##_SELECTOR, \
669 .base = GUEST_##seg##_BASE, \
670 .limit = GUEST_##seg##_LIMIT, \
671 .ar_bytes = GUEST_##seg##_AR_BYTES, \
672 }
673
772e0318 674static const struct kvm_vmx_segment_field {
6aa8b732
AK		 675 unsigned selector;
676 unsigned base;
677 unsigned limit;
678 unsigned ar_bytes;
679} kvm_vmx_segment_fields[] = {
680 VMX_SEGMENT_FIELD(CS),
681 VMX_SEGMENT_FIELD(DS),
682 VMX_SEGMENT_FIELD(ES),
683 VMX_SEGMENT_FIELD(FS),
684 VMX_SEGMENT_FIELD(GS),
685 VMX_SEGMENT_FIELD(SS),
686 VMX_SEGMENT_FIELD(TR),
687 VMX_SEGMENT_FIELD(LDTR),
688};
689
26bb0981
AK		 690static u64 host_efer;
691
6de4f3ad
AK		 692static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
693
4d56c8a7 694/*
8c06585d 695 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 696 * away by decrementing the array size.
697 */
6aa8b732 698static const u32 vmx_msr_index[] = {
05b3e0c2 699#ifdef CONFIG_X86_64
44ea2b17 700 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 701#endif
8c06585d 702 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 703};
9d8f549d 704#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 705
31299944 706static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
709 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 710 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 711}
712
31299944 713static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 714{
715 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
716 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 717 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 718}
719
31299944 720static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 721{
722 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
723 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 724 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 725}
726
31299944 727static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 728{
729 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
730 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
731}
732
31299944 733static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 734{
735 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
736 INTR_INFO_VALID_MASK)) ==
737 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
738}
739
31299944 740static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 741{
04547156 742 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 743}
744
31299944 745static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 746{
04547156 747 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 748}
749
31299944 750static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 751{
04547156 752 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 753}
754
31299944 755static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 756{
04547156
SY		 757 return vmcs_config.cpu_based_exec_ctrl &
758 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 759}
760
774ead3a 761static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 762{
04547156
SY		 763 return vmcs_config.cpu_based_2nd_exec_ctrl &
764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
765}
766
767static inline bool cpu_has_vmx_flexpriority(void)
768{
769 return cpu_has_vmx_tpr_shadow() &&
770 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 771}
772
e799794e
MT		 773static inline bool cpu_has_vmx_ept_execute_only(void)
774{
31299944 775 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 776}
777
778static inline bool cpu_has_vmx_eptp_uncacheable(void)
779{
31299944 780 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 781}
782
783static inline bool cpu_has_vmx_eptp_writeback(void)
784{
31299944 785 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 786}
787
788static inline bool cpu_has_vmx_ept_2m_page(void)
789{
31299944 790 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 791}
792
878403b7
SY		 793static inline bool cpu_has_vmx_ept_1g_page(void)
794{
31299944 795 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 796}
797
4bc9b982
SY		 798static inline bool cpu_has_vmx_ept_4levels(void)
799{
800 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
801}
802
83c3a331
XH		 803static inline bool cpu_has_vmx_ept_ad_bits(void)
804{
805 return vmx_capability.ept & VMX_EPT_AD_BIT;
806}
807
31299944 808static inline bool cpu_has_vmx_invept_context(void)
d56f546d 809{
31299944 810 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 811}
812
31299944 813static inline bool cpu_has_vmx_invept_global(void)
d56f546d 814{
31299944 815 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 816}
817
518c8aee
GJ		 818static inline bool cpu_has_vmx_invvpid_single(void)
819{
820 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
821}
822
b9d762fa
GJ		 823static inline bool cpu_has_vmx_invvpid_global(void)
824{
825 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
826}
827
31299944 828static inline bool cpu_has_vmx_ept(void)
d56f546d 829{
04547156
SY		 830 return vmcs_config.cpu_based_2nd_exec_ctrl &
831 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 832}
833
31299944 834static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 835{
836 return vmcs_config.cpu_based_2nd_exec_ctrl &
837 SECONDARY_EXEC_UNRESTRICTED_GUEST;
838}
839
31299944 840static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 841{
842 return vmcs_config.cpu_based_2nd_exec_ctrl &
843 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
844}
845
31299944 846static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 847{
6d3e435e 848 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_vpid(void)
2384d2b3 852{
04547156
SY		 853 return vmcs_config.cpu_based_2nd_exec_ctrl &
854 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 855}
856
31299944 857static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 858{
859 return vmcs_config.cpu_based_2nd_exec_ctrl &
860 SECONDARY_EXEC_RDTSCP;
861}
862
ad756a16
MJ		 863static inline bool cpu_has_vmx_invpcid(void)
864{
865 return vmcs_config.cpu_based_2nd_exec_ctrl &
866 SECONDARY_EXEC_ENABLE_INVPCID;
867}
868
31299944 869static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 870{
871 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
872}
873
f5f48ee1
SY		 874static inline bool cpu_has_vmx_wbinvd_exit(void)
875{
876 return vmcs_config.cpu_based_2nd_exec_ctrl &
877 SECONDARY_EXEC_WBINVD_EXITING;
878}
879
04547156
SY		 880static inline bool report_flexpriority(void)
881{
882 return flexpriority_enabled;
883}
884
fe3ef05c
NHE		 885static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
886{
887 return vmcs12->cpu_based_vm_exec_control & bit;
888}
889
890static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
891{
892 return (vmcs12->cpu_based_vm_exec_control &
893 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
894 (vmcs12->secondary_vm_exec_control & bit);
895}
896
644d711a
NHE		 897static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
898 struct kvm_vcpu *vcpu)
899{
900 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
901}
902
903static inline bool is_exception(u32 intr_info)
904{
905 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
906 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
907}
908
909static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 910static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
911 struct vmcs12 *vmcs12,
912 u32 reason, unsigned long qualification);
913
8b9cf98c 914static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 915{
916 int i;
917
a2fa3e9f 918 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 919 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 920 return i;
921 return -1;
922}
923
2384d2b3
SY		 924static inline void __invvpid(int ext, u16 vpid, gva_t gva)
925{
926 struct {
927 u64 vpid : 16;
928 u64 rsvd : 48;
929 u64 gva;
930 } operand = { vpid, 0, gva };
931
4ecac3fd 932 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 933 /* CF==1 or ZF==1 --> rc = -1 */
934 "; ja 1f ; ud2 ; 1:"
935 : : "a"(&operand), "c"(ext) : "cc", "memory");
936}
937
1439442c
SY		 938static inline void __invept(int ext, u64 eptp, gpa_t gpa)
939{
940 struct {
941 u64 eptp, gpa;
942 } operand = {eptp, gpa};
943
4ecac3fd 944 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 945 /* CF==1 or ZF==1 --> rc = -1 */
946 "; ja 1f ; ud2 ; 1:\n"
947 : : "a" (&operand), "c" (ext) : "cc", "memory");
948}
949
26bb0981 950static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 951{
952 int i;
953
8b9cf98c 954 i = __find_msr_index(vmx, msr);
a75beee6 955 if (i >= 0)
a2fa3e9f 956 return &vmx->guest_msrs[i];
8b6d44c7 957 return NULL;
7725f0ba
AK		 958}
959
6aa8b732
AK		 960static void vmcs_clear(struct vmcs *vmcs)
961{
962 u64 phys_addr = __pa(vmcs);
963 u8 error;
964
4ecac3fd 965 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 966 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 967 : "cc", "memory");
968 if (error)
969 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
970 vmcs, phys_addr);
971}
972
d462b819
NHE		 973static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
974{
975 vmcs_clear(loaded_vmcs->vmcs);
976 loaded_vmcs->cpu = -1;
977 loaded_vmcs->launched = 0;
978}
979
7725b894
DX		 980static void vmcs_load(struct vmcs *vmcs)
981{
982 u64 phys_addr = __pa(vmcs);
983 u8 error;
984
985 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 986 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 987 : "cc", "memory");
988 if (error)
2844d849 989 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 990 vmcs, phys_addr);
991}
992
8f536b76
ZY		 993#ifdef CONFIG_KEXEC
994/*
995 * This bitmap is used to indicate whether the vmclear
996 * operation is enabled on all cpus. All disabled by
997 * default.
998 */
999static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1000
1001static inline void crash_enable_local_vmclear(int cpu)
1002{
1003 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1004}
1005
1006static inline void crash_disable_local_vmclear(int cpu)
1007{
1008 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1009}
1010
1011static inline int crash_local_vmclear_enabled(int cpu)
1012{
1013 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1014}
1015
1016static void crash_vmclear_local_loaded_vmcss(void)
1017{
1018 int cpu = raw_smp_processor_id();
1019 struct loaded_vmcs *v;
1020
1021 if (!crash_local_vmclear_enabled(cpu))
1022 return;
1023
1024 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1025 loaded_vmcss_on_cpu_link)
1026 vmcs_clear(v->vmcs);
1027}
1028#else
1029static inline void crash_enable_local_vmclear(int cpu) { }
1030static inline void crash_disable_local_vmclear(int cpu) { }
1031#endif /* CONFIG_KEXEC */
1032
d462b819 1033static void __loaded_vmcs_clear(void *arg)
6aa8b732 1034{
d462b819 1035 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1036 int cpu = raw_smp_processor_id();
6aa8b732 1037
d462b819
NHE		 1038 if (loaded_vmcs->cpu != cpu)
1039 return; /* vcpu migration can race with cpu offline */
1040 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1041 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1042 crash_disable_local_vmclear(cpu);
d462b819 1043 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1044
1045 /*
1046 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1047 * is before setting loaded_vmcs->vcpu to -1 which is done in
1048 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1049 * then adds the vmcs into percpu list before it is deleted.
1050 */
1051 smp_wmb();
1052
d462b819 1053 loaded_vmcs_init(loaded_vmcs);
8f536b76 1054 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1055}
1056
d462b819 1057static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1058{
e6c7d321
XG		 1059 int cpu = loaded_vmcs->cpu;
1060
1061 if (cpu != -1)
1062 smp_call_function_single(cpu,
1063 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1064}
1065
1760dd49 1066static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1067{
1068 if (vmx->vpid == 0)
1069 return;
1070
518c8aee
GJ		 1071 if (cpu_has_vmx_invvpid_single())
1072 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1073}
1074
b9d762fa
GJ		 1075static inline void vpid_sync_vcpu_global(void)
1076{
1077 if (cpu_has_vmx_invvpid_global())
1078 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1079}
1080
1081static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1082{
1083 if (cpu_has_vmx_invvpid_single())
1760dd49 1084 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1085 else
1086 vpid_sync_vcpu_global();
1087}
1088
1439442c
SY		 1089static inline void ept_sync_global(void)
1090{
1091 if (cpu_has_vmx_invept_global())
1092 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1093}
1094
1095static inline void ept_sync_context(u64 eptp)
1096{
089d034e 1097 if (enable_ept) {
1439442c
SY		 1098 if (cpu_has_vmx_invept_context())
1099 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1100 else
1101 ept_sync_global();
1102 }
1103}
1104
96304217 1105static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1106{
5e520e62 1107 unsigned long value;
6aa8b732 1108
5e520e62
AK		 1109 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1110 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1111 return value;
1112}
1113
96304217 1114static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1115{
1116 return vmcs_readl(field);
1117}
1118
96304217 1119static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1120{
1121 return vmcs_readl(field);
1122}
1123
96304217 1124static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1125{
05b3e0c2 1126#ifdef CONFIG_X86_64
6aa8b732
AK		 1127 return vmcs_readl(field);
1128#else
1129 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1130#endif
1131}
1132
e52de1b8
AK		 1133static noinline void vmwrite_error(unsigned long field, unsigned long value)
1134{
1135 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1136 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1137 dump_stack();
1138}
1139
6aa8b732
AK		 1140static void vmcs_writel(unsigned long field, unsigned long value)
1141{
1142 u8 error;
1143
4ecac3fd 1144 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1145 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1146 if (unlikely(error))
1147 vmwrite_error(field, value);
6aa8b732
AK		 1148}
1149
1150static void vmcs_write16(unsigned long field, u16 value)
1151{
1152 vmcs_writel(field, value);
1153}
1154
1155static void vmcs_write32(unsigned long field, u32 value)
1156{
1157 vmcs_writel(field, value);
1158}
1159
1160static void vmcs_write64(unsigned long field, u64 value)
1161{
6aa8b732 1162 vmcs_writel(field, value);
7682f2d0 1163#ifndef CONFIG_X86_64
6aa8b732
AK		 1164 asm volatile ("");
1165 vmcs_writel(field+1, value >> 32);
1166#endif
1167}
1168
2ab455cc
AL		 1169static void vmcs_clear_bits(unsigned long field, u32 mask)
1170{
1171 vmcs_writel(field, vmcs_readl(field) & ~mask);
1172}
1173
1174static void vmcs_set_bits(unsigned long field, u32 mask)
1175{
1176 vmcs_writel(field, vmcs_readl(field) | mask);
1177}
1178
2fb92db1
AK		 1179static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1180{
1181 vmx->segment_cache.bitmask = 0;
1182}
1183
1184static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1185 unsigned field)
1186{
1187 bool ret;
1188 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1189
1190 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1191 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1192 vmx->segment_cache.bitmask = 0;
1193 }
1194 ret = vmx->segment_cache.bitmask & mask;
1195 vmx->segment_cache.bitmask |= mask;
1196 return ret;
1197}
1198
1199static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1200{
1201 u16 *p = &vmx->segment_cache.seg[seg].selector;
1202
1203 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1204 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1205 return *p;
1206}
1207
1208static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1209{
1210 ulong *p = &vmx->segment_cache.seg[seg].base;
1211
1212 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1213 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1214 return *p;
1215}
1216
1217static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1218{
1219 u32 *p = &vmx->segment_cache.seg[seg].limit;
1220
1221 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1222 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1223 return *p;
1224}
1225
1226static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1227{
1228 u32 *p = &vmx->segment_cache.seg[seg].ar;
1229
1230 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1231 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1232 return *p;
1233}
1234
abd3f2d6
AK		 1235static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1236{
1237 u32 eb;
1238
fd7373cc
JK		 1239 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1240 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1241 if ((vcpu->guest_debug &
1242 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1243 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1244 eb |= 1u << BP_VECTOR;
7ffd92c5 1245 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1246 eb = ~0;
089d034e 1247 if (enable_ept)
1439442c 1248 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1249 if (vcpu->fpu_active)
1250 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1251
1252 /* When we are running a nested L2 guest and L1 specified for it a
1253 * certain exception bitmap, we must trap the same exceptions and pass
1254 * them to L1. When running L2, we will only handle the exceptions
1255 * specified above if L1 did not want them.
1256 */
1257 if (is_guest_mode(vcpu))
1258 eb |= get_vmcs12(vcpu)->exception_bitmap;
1259
abd3f2d6
AK		 1260 vmcs_write32(EXCEPTION_BITMAP, eb);
1261}
1262
8bf00a52
GN		 1263static void clear_atomic_switch_msr_special(unsigned long entry,
1264 unsigned long exit)
1265{
1266 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1267 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1268}
1269
61d2ef2c
AK		 1270static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1271{
1272 unsigned i;
1273 struct msr_autoload *m = &vmx->msr_autoload;
1274
8bf00a52
GN		 1275 switch (msr) {
1276 case MSR_EFER:
1277 if (cpu_has_load_ia32_efer) {
1278 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1279 VM_EXIT_LOAD_IA32_EFER);
1280 return;
1281 }
1282 break;
1283 case MSR_CORE_PERF_GLOBAL_CTRL:
1284 if (cpu_has_load_perf_global_ctrl) {
1285 clear_atomic_switch_msr_special(
1286 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1287 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1288 return;
1289 }
1290 break;
110312c8
AK		 1291 }
1292
61d2ef2c
AK		 1293 for (i = 0; i < m->nr; ++i)
1294 if (m->guest[i].index == msr)
1295 break;
1296
1297 if (i == m->nr)
1298 return;
1299 --m->nr;
1300 m->guest[i] = m->guest[m->nr];
1301 m->host[i] = m->host[m->nr];
1302 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1303 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1304}
1305
8bf00a52
GN		 1306static void add_atomic_switch_msr_special(unsigned long entry,
1307 unsigned long exit, unsigned long guest_val_vmcs,
1308 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1309{
1310 vmcs_write64(guest_val_vmcs, guest_val);
1311 vmcs_write64(host_val_vmcs, host_val);
1312 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1313 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1314}
1315
61d2ef2c
AK		 1316static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1317 u64 guest_val, u64 host_val)
1318{
1319 unsigned i;
1320 struct msr_autoload *m = &vmx->msr_autoload;
1321
8bf00a52
GN		 1322 switch (msr) {
1323 case MSR_EFER:
1324 if (cpu_has_load_ia32_efer) {
1325 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1326 VM_EXIT_LOAD_IA32_EFER,
1327 GUEST_IA32_EFER,
1328 HOST_IA32_EFER,
1329 guest_val, host_val);
1330 return;
1331 }
1332 break;
1333 case MSR_CORE_PERF_GLOBAL_CTRL:
1334 if (cpu_has_load_perf_global_ctrl) {
1335 add_atomic_switch_msr_special(
1336 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1337 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1338 GUEST_IA32_PERF_GLOBAL_CTRL,
1339 HOST_IA32_PERF_GLOBAL_CTRL,
1340 guest_val, host_val);
1341 return;
1342 }
1343 break;
110312c8
AK		 1344 }
1345
61d2ef2c
AK		 1346 for (i = 0; i < m->nr; ++i)
1347 if (m->guest[i].index == msr)
1348 break;
1349
e7fc6f93
GN		 1350 if (i == NR_AUTOLOAD_MSRS) {
1351 printk_once(KERN_WARNING"Not enough mst switch entries. "
1352 "Can't add msr %x\n", msr);
1353 return;
1354 } else if (i == m->nr) {
61d2ef2c
AK		 1355 ++m->nr;
1356 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1357 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1358 }
1359
1360 m->guest[i].index = msr;
1361 m->guest[i].value = guest_val;
1362 m->host[i].index = msr;
1363 m->host[i].value = host_val;
1364}
1365
33ed6329
AK		 1366static void reload_tss(void)
1367{
33ed6329
AK		 1368 /*
1369 * VT restores TR but not its size. Useless.
1370 */
d359192f 1371 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1372 struct desc_struct *descs;
33ed6329 1373
d359192f 1374 descs = (void *)gdt->address;
33ed6329
AK		 1375 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1376 load_TR_desc();
33ed6329
AK		 1377}
1378
92c0d900 1379static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1380{
3a34a881 1381 u64 guest_efer;
51c6cf66
AK		 1382 u64 ignore_bits;
1383
f6801dff 1384 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1385
51c6cf66 1386 /*
0fa06071 1387 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1388 * outside long mode
1389 */
1390 ignore_bits = EFER_NX | EFER_SCE;
1391#ifdef CONFIG_X86_64
1392 ignore_bits |= EFER_LMA | EFER_LME;
1393 /* SCE is meaningful only in long mode on Intel */
1394 if (guest_efer & EFER_LMA)
1395 ignore_bits &= ~(u64)EFER_SCE;
1396#endif
51c6cf66
AK		 1397 guest_efer &= ~ignore_bits;
1398 guest_efer |= host_efer & ignore_bits;
26bb0981 1399 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1400 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1401
1402 clear_atomic_switch_msr(vmx, MSR_EFER);
1403 /* On ept, can't emulate nx, and must switch nx atomically */
1404 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1405 guest_efer = vmx->vcpu.arch.efer;
1406 if (!(guest_efer & EFER_LMA))
1407 guest_efer &= ~EFER_LME;
1408 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1409 return false;
1410 }
1411
26bb0981 1412 return true;
51c6cf66
AK		 1413}
1414
2d49ec72
GN		 1415static unsigned long segment_base(u16 selector)
1416{
d359192f 1417 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1418 struct desc_struct *d;
1419 unsigned long table_base;
1420 unsigned long v;
1421
1422 if (!(selector & ~3))
1423 return 0;
1424
d359192f 1425 table_base = gdt->address;
2d49ec72
GN		 1426
1427 if (selector & 4) { /* from ldt */
1428 u16 ldt_selector = kvm_read_ldt();
1429
1430 if (!(ldt_selector & ~3))
1431 return 0;
1432
1433 table_base = segment_base(ldt_selector);
1434 }
1435 d = (struct desc_struct *)(table_base + (selector & ~7));
1436 v = get_desc_base(d);
1437#ifdef CONFIG_X86_64
1438 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1439 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1440#endif
1441 return v;
1442}
1443
1444static inline unsigned long kvm_read_tr_base(void)
1445{
1446 u16 tr;
1447 asm("str %0" : "=g"(tr));
1448 return segment_base(tr);
1449}
1450
04d2cc77 1451static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1452{
04d2cc77 1453 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1454 int i;
04d2cc77 1455
a2fa3e9f 1456 if (vmx->host_state.loaded)
33ed6329
AK		 1457 return;
1458
a2fa3e9f 1459 vmx->host_state.loaded = 1;
33ed6329
AK		 1460 /*
1461 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1462 * allow segment selectors with cpl > 0 or ti == 1.
1463 */
d6e88aec 1464 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1465 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1466 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1467 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1468 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1469 vmx->host_state.fs_reload_needed = 0;
1470 } else {
33ed6329 1471 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1472 vmx->host_state.fs_reload_needed = 1;
33ed6329 1473 }
9581d442 1474 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1475 if (!(vmx->host_state.gs_sel & 7))
1476 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1477 else {
1478 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1479 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1480 }
1481
b2da15ac
AK		 1482#ifdef CONFIG_X86_64
1483 savesegment(ds, vmx->host_state.ds_sel);
1484 savesegment(es, vmx->host_state.es_sel);
1485#endif
1486
33ed6329
AK		 1487#ifdef CONFIG_X86_64
1488 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1489 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1490#else
a2fa3e9f
GH		 1491 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1492 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1493#endif
707c0874
AK		 1494
1495#ifdef CONFIG_X86_64
c8770e7b
AK		 1496 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1497 if (is_long_mode(&vmx->vcpu))
44ea2b17 1498 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1499#endif
26bb0981
AK		 1500 for (i = 0; i < vmx->save_nmsrs; ++i)
1501 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1502 vmx->guest_msrs[i].data,
1503 vmx->guest_msrs[i].mask);
33ed6329
AK		 1504}
1505
a9b21b62 1506static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1507{
a2fa3e9f 1508 if (!vmx->host_state.loaded)
33ed6329
AK		 1509 return;
1510
e1beb1d3 1511 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1512 vmx->host_state.loaded = 0;
c8770e7b
AK		 1513#ifdef CONFIG_X86_64
1514 if (is_long_mode(&vmx->vcpu))
1515 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1516#endif
152d3f2f 1517 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1518 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1519#ifdef CONFIG_X86_64
9581d442 1520 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1521#else
1522 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1523#endif
33ed6329 1524 }
0a77fe4c
AK		 1525 if (vmx->host_state.fs_reload_needed)
1526 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1527#ifdef CONFIG_X86_64
1528 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1529 loadsegment(ds, vmx->host_state.ds_sel);
1530 loadsegment(es, vmx->host_state.es_sel);
1531 }
b2da15ac 1532#endif
152d3f2f 1533 reload_tss();
44ea2b17 1534#ifdef CONFIG_X86_64
c8770e7b 1535 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1536#endif
b1a74bf8
SS		 1537 /*
1538 * If the FPU is not active (through the host task or
1539 * the guest vcpu), then restore the cr0.TS bit.
1540 */
1541 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1542 stts();
3444d7da 1543 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1544}
1545
a9b21b62
AK		 1546static void vmx_load_host_state(struct vcpu_vmx *vmx)
1547{
1548 preempt_disable();
1549 __vmx_load_host_state(vmx);
1550 preempt_enable();
1551}
1552
6aa8b732
AK		 1553/*
1554 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1555 * vcpu mutex is already taken.
1556 */
15ad7146 1557static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1558{
a2fa3e9f 1559 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1560 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1561
4610c9cc
DX		 1562 if (!vmm_exclusive)
1563 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1564 else if (vmx->loaded_vmcs->cpu != cpu)
1565 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1566
d462b819
NHE		 1567 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1568 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1569 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1570 }
1571
d462b819 1572 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1573 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1574 unsigned long sysenter_esp;
1575
a8eeb04a 1576 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1577 local_irq_disable();
8f536b76 1578 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1579
1580 /*
1581 * Read loaded_vmcs->cpu should be before fetching
1582 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1583 * See the comments in __loaded_vmcs_clear().
1584 */
1585 smp_rmb();
1586
d462b819
NHE		 1587 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1588 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1589 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1590 local_irq_enable();
1591
6aa8b732
AK		 1592 /*
1593 * Linux uses per-cpu TSS and GDT, so set these when switching
1594 * processors.
1595 */
d6e88aec 1596 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1597 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1598
1599 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1600 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1601 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1602 }
6aa8b732
AK		 1603}
1604
1605static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1606{
a9b21b62 1607 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1608 if (!vmm_exclusive) {
d462b819
NHE		 1609 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1610 vcpu->cpu = -1;
4610c9cc
DX		 1611 kvm_cpu_vmxoff();
1612 }
6aa8b732
AK		 1613}
1614
5fd86fcf
AK		 1615static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1616{
81231c69
AK		 1617 ulong cr0;
1618
5fd86fcf
AK		 1619 if (vcpu->fpu_active)
1620 return;
1621 vcpu->fpu_active = 1;
81231c69
AK		 1622 cr0 = vmcs_readl(GUEST_CR0);
1623 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1624 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1625 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1626 update_exception_bitmap(vcpu);
edcafe3c 1627 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1628 if (is_guest_mode(vcpu))
1629 vcpu->arch.cr0_guest_owned_bits &=
1630 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1631 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1632}
1633
edcafe3c
AK		 1634static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1635
fe3ef05c
NHE		 1636/*
1637 * Return the cr0 value that a nested guest would read. This is a combination
1638 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1639 * its hypervisor (cr0_read_shadow).
1640 */
1641static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1642{
1643 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1644 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1645}
1646static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1647{
1648 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1649 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1650}
1651
5fd86fcf
AK		 1652static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1653{
36cf24e0
NHE		 1654 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1655 * set this *before* calling this function.
1656 */
edcafe3c 1657 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1658 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1659 update_exception_bitmap(vcpu);
edcafe3c
AK		 1660 vcpu->arch.cr0_guest_owned_bits = 0;
1661 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1662 if (is_guest_mode(vcpu)) {
1663 /*
1664 * L1's specified read shadow might not contain the TS bit,
1665 * so now that we turned on shadowing of this bit, we need to
1666 * set this bit of the shadow. Like in nested_vmx_run we need
1667 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1668 * up-to-date here because we just decached cr0.TS (and we'll
1669 * only update vmcs12->guest_cr0 on nested exit).
1670 */
1671 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1672 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1673 (vcpu->arch.cr0 & X86_CR0_TS);
1674 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1675 } else
1676 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1677}
1678
6aa8b732
AK		 1679static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1680{
78ac8b47 1681 unsigned long rflags, save_rflags;
345dcaa8 1682
6de12732
AK		 1683 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1684 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1685 rflags = vmcs_readl(GUEST_RFLAGS);
1686 if (to_vmx(vcpu)->rmode.vm86_active) {
1687 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1688 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1689 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1690 }
1691 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1692 }
6de12732 1693 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1694}
1695
1696static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1697{
6de12732
AK		 1698 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1699 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1700 if (to_vmx(vcpu)->rmode.vm86_active) {
1701 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1702 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1703 }
6aa8b732
AK		 1704 vmcs_writel(GUEST_RFLAGS, rflags);
1705}
1706
2809f5d2
GC		 1707static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1708{
1709 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1710 int ret = 0;
1711
1712 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1713 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1714 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1715 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1716
1717 return ret & mask;
1718}
1719
1720static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1721{
1722 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1723 u32 interruptibility = interruptibility_old;
1724
1725 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1726
48005f64 1727 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1728 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1729 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1730 interruptibility |= GUEST_INTR_STATE_STI;
1731
1732 if ((interruptibility != interruptibility_old))
1733 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1734}
1735
6aa8b732
AK		 1736static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1737{
1738 unsigned long rip;
6aa8b732 1739
5fdbf976 1740 rip = kvm_rip_read(vcpu);
6aa8b732 1741 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1742 kvm_rip_write(vcpu, rip);
6aa8b732 1743
2809f5d2
GC		 1744 /* skipping an emulated instruction also counts */
1745 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1746}
1747
0b6ac343
NHE		 1748/*
1749 * KVM wants to inject page-faults which it got to the guest. This function
1750 * checks whether in a nested guest, we need to inject them to L1 or L2.
1751 * This function assumes it is called with the exit reason in vmcs02 being
1752 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1753 * is running).
1754 */
1755static int nested_pf_handled(struct kvm_vcpu *vcpu)
1756{
1757 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1758
1759 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1760 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1761 return 0;
1762
1763 nested_vmx_vmexit(vcpu);
1764 return 1;
1765}
1766
298101da 1767static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1768 bool has_error_code, u32 error_code,
1769 bool reinject)
298101da 1770{
77ab6db0 1771 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1772 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1773
0b6ac343
NHE		 1774 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1775 nested_pf_handled(vcpu))
1776 return;
1777
8ab2d2e2 1778 if (has_error_code) {
77ab6db0 1779 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1780 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1781 }
77ab6db0 1782
7ffd92c5 1783 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1784 int inc_eip = 0;
1785 if (kvm_exception_is_soft(nr))
1786 inc_eip = vcpu->arch.event_exit_inst_len;
1787 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1788 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1789 return;
1790 }
1791
66fd3f7f
GN		 1792 if (kvm_exception_is_soft(nr)) {
1793 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1794 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1795 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1796 } else
1797 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1798
1799 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1800}
1801
4e47c7a6
SY		 1802static bool vmx_rdtscp_supported(void)
1803{
1804 return cpu_has_vmx_rdtscp();
1805}
1806
ad756a16
MJ		 1807static bool vmx_invpcid_supported(void)
1808{
1809 return cpu_has_vmx_invpcid() && enable_ept;
1810}
1811
a75beee6
ED		 1812/*
1813 * Swap MSR entry in host/guest MSR entry array.
1814 */
8b9cf98c 1815static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1816{
26bb0981 1817 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1818
1819 tmp = vmx->guest_msrs[to];
1820 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1821 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1822}
1823
e38aea3e
AK		 1824/*
1825 * Set up the vmcs to automatically save and restore system
1826 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1827 * mode, as fiddling with msrs is very expensive.
1828 */
8b9cf98c 1829static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1830{
26bb0981 1831 int save_nmsrs, index;
5897297b 1832 unsigned long *msr_bitmap;
e38aea3e 1833
a75beee6
ED		 1834 save_nmsrs = 0;
1835#ifdef CONFIG_X86_64
8b9cf98c 1836 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1837 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1838 if (index >= 0)
8b9cf98c
RR		 1839 move_msr_up(vmx, index, save_nmsrs++);
1840 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1841 if (index >= 0)
8b9cf98c
RR		 1842 move_msr_up(vmx, index, save_nmsrs++);
1843 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1844 if (index >= 0)
8b9cf98c 1845 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1846 index = __find_msr_index(vmx, MSR_TSC_AUX);
1847 if (index >= 0 && vmx->rdtscp_enabled)
1848 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1849 /*
8c06585d 1850 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1851 * if efer.sce is enabled.
1852 */
8c06585d 1853 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1854 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1855 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1856 }
1857#endif
92c0d900
AK		 1858 index = __find_msr_index(vmx, MSR_EFER);
1859 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1860 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1861
26bb0981 1862 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1863
1864 if (cpu_has_vmx_msr_bitmap()) {
1865 if (is_long_mode(&vmx->vcpu))
1866 msr_bitmap = vmx_msr_bitmap_longmode;
1867 else
1868 msr_bitmap = vmx_msr_bitmap_legacy;
1869
1870 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1871 }
e38aea3e
AK		 1872}
1873
6aa8b732
AK		 1874/*
1875 * reads and returns guest's timestamp counter "register"
1876 * guest_tsc = host_tsc + tsc_offset -- 21.3
1877 */
1878static u64 guest_read_tsc(void)
1879{
1880 u64 host_tsc, tsc_offset;
1881
1882 rdtscll(host_tsc);
1883 tsc_offset = vmcs_read64(TSC_OFFSET);
1884 return host_tsc + tsc_offset;
1885}
1886
d5c1785d
NHE		 1887/*
1888 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1889 * counter, even if a nested guest (L2) is currently running.
1890 */
886b470c 1891u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1892{
886b470c 1893 u64 tsc_offset;
d5c1785d 1894
d5c1785d
NHE		 1895 tsc_offset = is_guest_mode(vcpu) ?
1896 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1897 vmcs_read64(TSC_OFFSET);
1898 return host_tsc + tsc_offset;
1899}
1900
4051b188 1901/*
cc578287
ZA		 1902 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1903 * software catchup for faster rates on slower CPUs.
4051b188 1904 */
cc578287 1905static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1906{
cc578287
ZA		 1907 if (!scale)
1908 return;
1909
1910 if (user_tsc_khz > tsc_khz) {
1911 vcpu->arch.tsc_catchup = 1;
1912 vcpu->arch.tsc_always_catchup = 1;
1913 } else
1914 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1915}
1916
ba904635
WA		 1917static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1918{
1919 return vmcs_read64(TSC_OFFSET);
1920}
1921
6aa8b732 1922/*
99e3e30a 1923 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1924 */
99e3e30a 1925static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1926{
27fc51b2 1927 if (is_guest_mode(vcpu)) {
7991825b 1928 /*
27fc51b2
NHE		 1929 * We're here if L1 chose not to trap WRMSR to TSC. According
1930 * to the spec, this should set L1's TSC; The offset that L1
1931 * set for L2 remains unchanged, and still needs to be added
1932 * to the newly set TSC to get L2's TSC.
7991825b 1933 */
27fc51b2
NHE		 1934 struct vmcs12 *vmcs12;
1935 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1936 /* recalculate vmcs02.TSC_OFFSET: */
1937 vmcs12 = get_vmcs12(vcpu);
1938 vmcs_write64(TSC_OFFSET, offset +
1939 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1940 vmcs12->tsc_offset : 0));
1941 } else {
1942 vmcs_write64(TSC_OFFSET, offset);
1943 }
6aa8b732
AK		 1944}
1945
f1e2b260 1946static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1947{
1948 u64 offset = vmcs_read64(TSC_OFFSET);
1949 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1950 if (is_guest_mode(vcpu)) {
1951 /* Even when running L2, the adjustment needs to apply to L1 */
1952 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1953 }
e48672fa
ZA		 1954}
1955
857e4099
JR		 1956static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1957{
1958 return target_tsc - native_read_tsc();
1959}
1960
801d3424
NHE		 1961static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1962{
1963 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1964 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1965}
1966
1967/*
1968 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1969 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1970 * all guests if the "nested" module option is off, and can also be disabled
1971 * for a single guest by disabling its VMX cpuid bit.
1972 */
1973static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1974{
1975 return nested && guest_cpuid_has_vmx(vcpu);
1976}
1977
b87a51ae
NHE		 1978/*
1979 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1980 * returned for the various VMX controls MSRs when nested VMX is enabled.
1981 * The same values should also be used to verify that vmcs12 control fields are
1982 * valid during nested entry from L1 to L2.
1983 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1984 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1985 * bit in the high half is on if the corresponding bit in the control field
1986 * may be on. See also vmx_control_verify().
1987 * TODO: allow these variables to be modified (downgraded) by module options
1988 * or other means.
1989 */
1990static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1991static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1992static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1993static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1994static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1995static __init void nested_vmx_setup_ctls_msrs(void)
1996{
1997 /*
1998 * Note that as a general rule, the high half of the MSRs (bits in
1999 * the control fields which may be 1) should be initialized by the
2000 * intersection of the underlying hardware's MSR (i.e., features which
2001 * can be supported) and the list of features we want to expose -
2002 * because they are known to be properly supported in our code.
2003 * Also, usually, the low half of the MSRs (bits which must be 1) can
2004 * be set to 0, meaning that L1 may turn off any of these bits. The
2005 * reason is that if one of these bits is necessary, it will appear
2006 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2007 * fields of vmcs01 and vmcs02, will turn these bits off - and
2008 * nested_vmx_exit_handled() will not pass related exits to L1.
2009 * These rules have exceptions below.
2010 */
2011
2012 /* pin-based controls */
2013 /*
2014 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2015 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2016 */
2017 nested_vmx_pinbased_ctls_low = 0x16 ;
2018 nested_vmx_pinbased_ctls_high = 0x16 |
2019 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2020 PIN_BASED_VIRTUAL_NMIS;
2021
2022 /* exit controls */
2023 nested_vmx_exit_ctls_low = 0;
b6f1250e 2024 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2025#ifdef CONFIG_X86_64
2026 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2027#else
2028 nested_vmx_exit_ctls_high = 0;
2029#endif
2030
2031 /* entry controls */
2032 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2033 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2034 nested_vmx_entry_ctls_low = 0;
2035 nested_vmx_entry_ctls_high &=
2036 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2037
2038 /* cpu-based controls */
2039 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2040 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2041 nested_vmx_procbased_ctls_low = 0;
2042 nested_vmx_procbased_ctls_high &=
2043 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2044 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2045 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2046 CPU_BASED_CR3_STORE_EXITING |
2047#ifdef CONFIG_X86_64
2048 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2049#endif
2050 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2051 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2052 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2053 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2054 /*
2055 * We can allow some features even when not supported by the
2056 * hardware. For example, L1 can specify an MSR bitmap - and we
2057 * can use it to avoid exits to L1 - even when L0 runs L2
2058 * without MSR bitmaps.
2059 */
2060 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2061
2062 /* secondary cpu-based controls */
2063 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2064 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2065 nested_vmx_secondary_ctls_low = 0;
2066 nested_vmx_secondary_ctls_high &=
2067 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2068}
2069
2070static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2071{
2072 /*
2073 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2074 */
2075 return ((control & high) | low) == control;
2076}
2077
2078static inline u64 vmx_control_msr(u32 low, u32 high)
2079{
2080 return low | ((u64)high << 32);
2081}
2082
2083/*
2084 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2085 * also let it use VMX-specific MSRs.
2086 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2087 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2088 * like all other MSRs).
2089 */
2090static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2091{
2092 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2093 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2094 /*
2095 * According to the spec, processors which do not support VMX
2096 * should throw a #GP(0) when VMX capability MSRs are read.
2097 */
2098 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2099 return 1;
2100 }
2101
2102 switch (msr_index) {
2103 case MSR_IA32_FEATURE_CONTROL:
2104 *pdata = 0;
2105 break;
2106 case MSR_IA32_VMX_BASIC:
2107 /*
2108 * This MSR reports some information about VMX support. We
2109 * should return information about the VMX we emulate for the
2110 * guest, and the VMCS structure we give it - not about the
2111 * VMX support of the underlying hardware.
2112 */
2113 *pdata = VMCS12_REVISION |
2114 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2115 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2116 break;
2117 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2118 case MSR_IA32_VMX_PINBASED_CTLS:
2119 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2120 nested_vmx_pinbased_ctls_high);
2121 break;
2122 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2123 case MSR_IA32_VMX_PROCBASED_CTLS:
2124 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2125 nested_vmx_procbased_ctls_high);
2126 break;
2127 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2128 case MSR_IA32_VMX_EXIT_CTLS:
2129 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2130 nested_vmx_exit_ctls_high);
2131 break;
2132 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2133 case MSR_IA32_VMX_ENTRY_CTLS:
2134 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2135 nested_vmx_entry_ctls_high);
2136 break;
2137 case MSR_IA32_VMX_MISC:
2138 *pdata = 0;
2139 break;
2140 /*
2141 * These MSRs specify bits which the guest must keep fixed (on or off)
2142 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2143 * We picked the standard core2 setting.
2144 */
2145#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2146#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2147 case MSR_IA32_VMX_CR0_FIXED0:
2148 *pdata = VMXON_CR0_ALWAYSON;
2149 break;
2150 case MSR_IA32_VMX_CR0_FIXED1:
2151 *pdata = -1ULL;
2152 break;
2153 case MSR_IA32_VMX_CR4_FIXED0:
2154 *pdata = VMXON_CR4_ALWAYSON;
2155 break;
2156 case MSR_IA32_VMX_CR4_FIXED1:
2157 *pdata = -1ULL;
2158 break;
2159 case MSR_IA32_VMX_VMCS_ENUM:
2160 *pdata = 0x1f;
2161 break;
2162 case MSR_IA32_VMX_PROCBASED_CTLS2:
2163 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2164 nested_vmx_secondary_ctls_high);
2165 break;
2166 case MSR_IA32_VMX_EPT_VPID_CAP:
2167 /* Currently, no nested ept or nested vpid */
2168 *pdata = 0;
2169 break;
2170 default:
2171 return 0;
2172 }
2173
2174 return 1;
2175}
2176
2177static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2178{
2179 if (!nested_vmx_allowed(vcpu))
2180 return 0;
2181
2182 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2183 /* TODO: the right thing. */
2184 return 1;
2185 /*
2186 * No need to treat VMX capability MSRs specially: If we don't handle
2187 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2188 */
2189 return 0;
2190}
2191
6aa8b732
AK		 2192/*
2193 * Reads an msr value (of 'msr_index') into 'pdata'.
2194 * Returns 0 on success, non-0 otherwise.
2195 * Assumes vcpu_load() was already called.
2196 */
2197static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2198{
2199 u64 data;
26bb0981 2200 struct shared_msr_entry *msr;
6aa8b732
AK		 2201
2202 if (!pdata) {
2203 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2204 return -EINVAL;
2205 }
2206
2207 switch (msr_index) {
05b3e0c2 2208#ifdef CONFIG_X86_64
6aa8b732
AK		 2209 case MSR_FS_BASE:
2210 data = vmcs_readl(GUEST_FS_BASE);
2211 break;
2212 case MSR_GS_BASE:
2213 data = vmcs_readl(GUEST_GS_BASE);
2214 break;
44ea2b17
AK		 2215 case MSR_KERNEL_GS_BASE:
2216 vmx_load_host_state(to_vmx(vcpu));
2217 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2218 break;
26bb0981 2219#endif
6aa8b732 2220 case MSR_EFER:
3bab1f5d 2221 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2222 case MSR_IA32_TSC:
6aa8b732
AK		 2223 data = guest_read_tsc();
2224 break;
2225 case MSR_IA32_SYSENTER_CS:
2226 data = vmcs_read32(GUEST_SYSENTER_CS);
2227 break;
2228 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2229 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2230 break;
2231 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2232 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2233 break;
4e47c7a6
SY		 2234 case MSR_TSC_AUX:
2235 if (!to_vmx(vcpu)->rdtscp_enabled)
2236 return 1;
2237 /* Otherwise falls through */
6aa8b732 2238 default:
b87a51ae
NHE		 2239 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2240 return 0;
8b9cf98c 2241 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2242 if (msr) {
2243 data = msr->data;
2244 break;
6aa8b732 2245 }
3bab1f5d 2246 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2247 }
2248
2249 *pdata = data;
2250 return 0;
2251}
2252
2253/*
2254 * Writes msr value into into the appropriate "register".
2255 * Returns 0 on success, non-0 otherwise.
2256 * Assumes vcpu_load() was already called.
2257 */
8fe8ab46 2258static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2259{
a2fa3e9f 2260 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2261 struct shared_msr_entry *msr;
2cc51560 2262 int ret = 0;
8fe8ab46
WA		 2263 u32 msr_index = msr_info->index;
2264 u64 data = msr_info->data;
2cc51560 2265
6aa8b732 2266 switch (msr_index) {
3bab1f5d 2267 case MSR_EFER:
8fe8ab46 2268 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2269 break;
16175a79 2270#ifdef CONFIG_X86_64
6aa8b732 2271 case MSR_FS_BASE:
2fb92db1 2272 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2273 vmcs_writel(GUEST_FS_BASE, data);
2274 break;
2275 case MSR_GS_BASE:
2fb92db1 2276 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2277 vmcs_writel(GUEST_GS_BASE, data);
2278 break;
44ea2b17
AK		 2279 case MSR_KERNEL_GS_BASE:
2280 vmx_load_host_state(vmx);
2281 vmx->msr_guest_kernel_gs_base = data;
2282 break;
6aa8b732
AK		 2283#endif
2284 case MSR_IA32_SYSENTER_CS:
2285 vmcs_write32(GUEST_SYSENTER_CS, data);
2286 break;
2287 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2288 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2289 break;
2290 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2291 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2292 break;
af24a4e4 2293 case MSR_IA32_TSC:
8fe8ab46 2294 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2295 break;
468d472f
SY		 2296 case MSR_IA32_CR_PAT:
2297 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2298 vmcs_write64(GUEST_IA32_PAT, data);
2299 vcpu->arch.pat = data;
2300 break;
2301 }
8fe8ab46 2302 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2303 break;
ba904635
WA		 2304 case MSR_IA32_TSC_ADJUST:
2305 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2306 break;
2307 case MSR_TSC_AUX:
2308 if (!vmx->rdtscp_enabled)
2309 return 1;
2310 /* Check reserved bit, higher 32 bits should be zero */
2311 if ((data >> 32) != 0)
2312 return 1;
2313 /* Otherwise falls through */
6aa8b732 2314 default:
b87a51ae
NHE		 2315 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2316 break;
8b9cf98c 2317 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2318 if (msr) {
2319 msr->data = data;
2225fd56
AK		 2320 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2321 preempt_disable();
9ee73970
AK		 2322 kvm_set_shared_msr(msr->index, msr->data,
2323 msr->mask);
2225fd56
AK		 2324 preempt_enable();
2325 }
3bab1f5d 2326 break;
6aa8b732 2327 }
8fe8ab46 2328 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2329 }
2330
2cc51560 2331 return ret;
6aa8b732
AK		 2332}
2333
5fdbf976 2334static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2335{
5fdbf976
MT		 2336 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2337 switch (reg) {
2338 case VCPU_REGS_RSP:
2339 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2340 break;
2341 case VCPU_REGS_RIP:
2342 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2343 break;
6de4f3ad
AK		 2344 case VCPU_EXREG_PDPTR:
2345 if (enable_ept)
2346 ept_save_pdptrs(vcpu);
2347 break;
5fdbf976
MT		 2348 default:
2349 break;
2350 }
6aa8b732
AK		 2351}
2352
6aa8b732
AK		 2353static __init int cpu_has_kvm_support(void)
2354{
6210e37b 2355 return cpu_has_vmx();
6aa8b732
AK		 2356}
2357
2358static __init int vmx_disabled_by_bios(void)
2359{
2360 u64 msr;
2361
2362 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2363 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2364 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2365 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2366 && tboot_enabled())
2367 return 1;
23f3e991 2368 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2369 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2370 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2371 && !tboot_enabled()) {
2372 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2373 "activate TXT before enabling KVM\n");
cafd6659 2374 return 1;
f9335afe 2375 }
23f3e991
JC		 2376 /* launched w/o TXT and VMX disabled */
2377 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2378 && !tboot_enabled())
2379 return 1;
cafd6659
SW		 2380 }
2381
2382 return 0;
6aa8b732
AK		 2383}
2384
7725b894
DX		 2385static void kvm_cpu_vmxon(u64 addr)
2386{
2387 asm volatile (ASM_VMX_VMXON_RAX
2388 : : "a"(&addr), "m"(addr)
2389 : "memory", "cc");
2390}
2391
10474ae8 2392static int hardware_enable(void *garbage)
6aa8b732
AK		 2393{
2394 int cpu = raw_smp_processor_id();
2395 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2396 u64 old, test_bits;
6aa8b732 2397
10474ae8
AG		 2398 if (read_cr4() & X86_CR4_VMXE)
2399 return -EBUSY;
2400
d462b819 2401 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2402
2403 /*
2404 * Now we can enable the vmclear operation in kdump
2405 * since the loaded_vmcss_on_cpu list on this cpu
2406 * has been initialized.
2407 *
2408 * Though the cpu is not in VMX operation now, there
2409 * is no problem to enable the vmclear operation
2410 * for the loaded_vmcss_on_cpu list is empty!
2411 */
2412 crash_enable_local_vmclear(cpu);
2413
6aa8b732 2414 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2415
2416 test_bits = FEATURE_CONTROL_LOCKED;
2417 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2418 if (tboot_enabled())
2419 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2420
2421 if ((old & test_bits) != test_bits) {
6aa8b732 2422 /* enable and lock */
cafd6659
SW		 2423 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2424 }
66aee91a 2425 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2426
4610c9cc
DX		 2427 if (vmm_exclusive) {
2428 kvm_cpu_vmxon(phys_addr);
2429 ept_sync_global();
2430 }
10474ae8 2431
3444d7da
AK		 2432 store_gdt(&__get_cpu_var(host_gdt));
2433
10474ae8 2434 return 0;
6aa8b732
AK		 2435}
2436
d462b819 2437static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2438{
2439 int cpu = raw_smp_processor_id();
d462b819 2440 struct loaded_vmcs *v, *n;
543e4243 2441
d462b819
NHE		 2442 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2443 loaded_vmcss_on_cpu_link)
2444 __loaded_vmcs_clear(v);
543e4243
AK		 2445}
2446
710ff4a8
EH		 2447
2448/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2449 * tricks.
2450 */
2451static void kvm_cpu_vmxoff(void)
6aa8b732 2452{
4ecac3fd 2453 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2454}
2455
710ff4a8
EH		 2456static void hardware_disable(void *garbage)
2457{
4610c9cc 2458 if (vmm_exclusive) {
d462b819 2459 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2460 kvm_cpu_vmxoff();
2461 }
7725b894 2462 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2463}
2464
1c3d14fe 2465static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2466 u32 msr, u32 *result)
1c3d14fe
YS		 2467{
2468 u32 vmx_msr_low, vmx_msr_high;
2469 u32 ctl = ctl_min | ctl_opt;
2470
2471 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2472
2473 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2474 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2475
2476 /* Ensure minimum (required) set of control bits are supported. */
2477 if (ctl_min & ~ctl)
002c7f7c 2478 return -EIO;
1c3d14fe
YS		 2479
2480 *result = ctl;
2481 return 0;
2482}
2483
110312c8
AK		 2484static __init bool allow_1_setting(u32 msr, u32 ctl)
2485{
2486 u32 vmx_msr_low, vmx_msr_high;
2487
2488 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2489 return vmx_msr_high & ctl;
2490}
2491
002c7f7c 2492static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2493{
2494 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2495 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2496 u32 _pin_based_exec_control = 0;
2497 u32 _cpu_based_exec_control = 0;
f78e0e2e 2498 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2499 u32 _vmexit_control = 0;
2500 u32 _vmentry_control = 0;
2501
2502 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2503 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2504 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2505 &_pin_based_exec_control) < 0)
002c7f7c 2506 return -EIO;
1c3d14fe 2507
10166744 2508 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2509#ifdef CONFIG_X86_64
2510 CPU_BASED_CR8_LOAD_EXITING |
2511 CPU_BASED_CR8_STORE_EXITING |
2512#endif
d56f546d
SY		 2513 CPU_BASED_CR3_LOAD_EXITING |
2514 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2515 CPU_BASED_USE_IO_BITMAPS |
2516 CPU_BASED_MOV_DR_EXITING |
a7052897 2517 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2518 CPU_BASED_MWAIT_EXITING |
2519 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2520 CPU_BASED_INVLPG_EXITING |
2521 CPU_BASED_RDPMC_EXITING;
443381a8 2522
f78e0e2e 2523 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2524 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2525 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2526 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2527 &_cpu_based_exec_control) < 0)
002c7f7c 2528 return -EIO;
6e5d865c
YS		 2529#ifdef CONFIG_X86_64
2530 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2531 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2532 ~CPU_BASED_CR8_STORE_EXITING;
2533#endif
f78e0e2e 2534 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2535 min2 = 0;
2536 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2537 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2538 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2539 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2540 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2541 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2542 SECONDARY_EXEC_RDTSCP |
2543 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2544 if (adjust_vmx_controls(min2, opt2,
2545 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2546 &_cpu_based_2nd_exec_control) < 0)
2547 return -EIO;
2548 }
2549#ifndef CONFIG_X86_64
2550 if (!(_cpu_based_2nd_exec_control &
2551 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2552 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2553#endif
d56f546d 2554 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2555 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2556 enabled */
5fff7d27
GN		 2557 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2558 CPU_BASED_CR3_STORE_EXITING |
2559 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2560 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2561 vmx_capability.ept, vmx_capability.vpid);
2562 }
1c3d14fe
YS		 2563
2564 min = 0;
2565#ifdef CONFIG_X86_64
2566 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2567#endif
468d472f 2568 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2569 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2570 &_vmexit_control) < 0)
002c7f7c 2571 return -EIO;
1c3d14fe 2572
468d472f
SY		 2573 min = 0;
2574 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2575 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2576 &_vmentry_control) < 0)
002c7f7c 2577 return -EIO;
6aa8b732 2578
c68876fd 2579 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2580
2581 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2582 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2583 return -EIO;
1c3d14fe
YS		 2584
2585#ifdef CONFIG_X86_64
2586 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2587 if (vmx_msr_high & (1u<<16))
002c7f7c 2588 return -EIO;
1c3d14fe
YS		 2589#endif
2590
2591 /* Require Write-Back (WB) memory type for VMCS accesses. */
2592 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2593 return -EIO;
1c3d14fe 2594
002c7f7c
YS		 2595 vmcs_conf->size = vmx_msr_high & 0x1fff;
2596 vmcs_conf->order = get_order(vmcs_config.size);
2597 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2598
002c7f7c
YS		 2599 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2600 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2601 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2602 vmcs_conf->vmexit_ctrl = _vmexit_control;
2603 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2604
110312c8
AK		 2605 cpu_has_load_ia32_efer =
2606 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2607 VM_ENTRY_LOAD_IA32_EFER)
2608 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2609 VM_EXIT_LOAD_IA32_EFER);
2610
8bf00a52
GN		 2611 cpu_has_load_perf_global_ctrl =
2612 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2613 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2614 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2615 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2616
2617 /*
2618 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2619 * but due to arrata below it can't be used. Workaround is to use
2620 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2621 *
2622 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2623 *
2624 * AAK155 (model 26)
2625 * AAP115 (model 30)
2626 * AAT100 (model 37)
2627 * BC86,AAY89,BD102 (model 44)
2628 * BA97 (model 46)
2629 *
2630 */
2631 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2632 switch (boot_cpu_data.x86_model) {
2633 case 26:
2634 case 30:
2635 case 37:
2636 case 44:
2637 case 46:
2638 cpu_has_load_perf_global_ctrl = false;
2639 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2640 "does not work properly. Using workaround\n");
2641 break;
2642 default:
2643 break;
2644 }
2645 }
2646
1c3d14fe 2647 return 0;
c68876fd 2648}
6aa8b732
AK		 2649
2650static struct vmcs *alloc_vmcs_cpu(int cpu)
2651{
2652 int node = cpu_to_node(cpu);
2653 struct page *pages;
2654 struct vmcs *vmcs;
2655
6484eb3e 2656 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2657 if (!pages)
2658 return NULL;
2659 vmcs = page_address(pages);
1c3d14fe
YS		 2660 memset(vmcs, 0, vmcs_config.size);
2661 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2662 return vmcs;
2663}
2664
2665static struct vmcs *alloc_vmcs(void)
2666{
d3b2c338 2667 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2668}
2669
2670static void free_vmcs(struct vmcs *vmcs)
2671{
1c3d14fe 2672 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2673}
2674
d462b819
NHE		 2675/*
2676 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2677 */
2678static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2679{
2680 if (!loaded_vmcs->vmcs)
2681 return;
2682 loaded_vmcs_clear(loaded_vmcs);
2683 free_vmcs(loaded_vmcs->vmcs);
2684 loaded_vmcs->vmcs = NULL;
2685}
2686
39959588 2687static void free_kvm_area(void)
6aa8b732
AK		 2688{
2689 int cpu;
2690
3230bb47 2691 for_each_possible_cpu(cpu) {
6aa8b732 2692 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2693 per_cpu(vmxarea, cpu) = NULL;
2694 }
6aa8b732
AK		 2695}
2696
6aa8b732
AK		 2697static __init int alloc_kvm_area(void)
2698{
2699 int cpu;
2700
3230bb47 2701 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2702 struct vmcs *vmcs;
2703
2704 vmcs = alloc_vmcs_cpu(cpu);
2705 if (!vmcs) {
2706 free_kvm_area();
2707 return -ENOMEM;
2708 }
2709
2710 per_cpu(vmxarea, cpu) = vmcs;
2711 }
2712 return 0;
2713}
2714
2715static __init int hardware_setup(void)
2716{
002c7f7c
YS		 2717 if (setup_vmcs_config(&vmcs_config) < 0)
2718 return -EIO;
50a37eb4
JR		 2719
2720 if (boot_cpu_has(X86_FEATURE_NX))
2721 kvm_enable_efer_bits(EFER_NX);
2722
93ba03c2
SY		 2723 if (!cpu_has_vmx_vpid())
2724 enable_vpid = 0;
2725
4bc9b982
SY		 2726 if (!cpu_has_vmx_ept() ||
2727 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2728 enable_ept = 0;
3a624e29 2729 enable_unrestricted_guest = 0;
83c3a331 2730 enable_ept_ad_bits = 0;
3a624e29
NK		 2731 }
2732
83c3a331
XH		 2733 if (!cpu_has_vmx_ept_ad_bits())
2734 enable_ept_ad_bits = 0;
2735
3a624e29
NK		 2736 if (!cpu_has_vmx_unrestricted_guest())
2737 enable_unrestricted_guest = 0;
93ba03c2
SY		 2738
2739 if (!cpu_has_vmx_flexpriority())
2740 flexpriority_enabled = 0;
2741
95ba8273
GN		 2742 if (!cpu_has_vmx_tpr_shadow())
2743 kvm_x86_ops->update_cr8_intercept = NULL;
2744
54dee993
MT		 2745 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2746 kvm_disable_largepages();
2747
4b8d54f9
ZE		 2748 if (!cpu_has_vmx_ple())
2749 ple_gap = 0;
2750
b87a51ae
NHE		 2751 if (nested)
2752 nested_vmx_setup_ctls_msrs();
2753
6aa8b732
AK		 2754 return alloc_kvm_area();
2755}
2756
2757static __exit void hardware_unsetup(void)
2758{
2759 free_kvm_area();
2760}
2761
d99e4152
GN		 2762static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg,
2763 struct kvm_segment *save)
6aa8b732 2764{
d99e4152
GN		 2765 if (!emulate_invalid_guest_state) {
2766 /*
2767 * CS and SS RPL should be equal during guest entry according
2768 * to VMX spec, but in reality it is not always so. Since vcpu
2769 * is in the middle of the transition from real mode to
2770 * protected mode it is safe to assume that RPL 0 is a good
2771 * default value.
2772 */
2773 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2774 save->selector &= ~SELECTOR_RPL_MASK;
2775 save->dpl = save->selector & SELECTOR_RPL_MASK;
2776 save->s = 1;
6aa8b732 2777 }
d99e4152 2778 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2779}
2780
2781static void enter_pmode(struct kvm_vcpu *vcpu)
2782{
2783 unsigned long flags;
a89a8fb9 2784 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2785
d99e4152
GN		 2786 /*
2787 * Update real mode segment cache. It may be not up-to-date if sement
2788 * register was written while vcpu was in a guest mode.
2789 */
2790 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2791 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2792 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2793 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2794 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2795 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2796
a89a8fb9 2797 vmx->emulation_required = 1;
7ffd92c5 2798 vmx->rmode.vm86_active = 0;
6aa8b732 2799
2fb92db1
AK		 2800 vmx_segment_cache_clear(vmx);
2801
f5f7b2fe 2802 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2803
2804 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2805 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2806 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2807 vmcs_writel(GUEST_RFLAGS, flags);
2808
66aee91a
RR		 2809 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2810 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2811
2812 update_exception_bitmap(vcpu);
2813
d99e4152
GN		 2814 fix_pmode_dataseg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2815 fix_pmode_dataseg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
f5f7b2fe
AK		 2816 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2817 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2818 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2819 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 2820
2821 /* CPL is always 0 when CPU enters protected mode */
2822 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2823 vmx->cpl = 0;
6aa8b732
AK		 2824}
2825
d77c26fc 2826static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2827{
bfc6d222 2828 if (!kvm->arch.tss_addr) {
bc6678a3 2829 struct kvm_memslots *slots;
28a37544 2830 struct kvm_memory_slot *slot;
bc6678a3
MT		 2831 gfn_t base_gfn;
2832
90d83dc3 2833 slots = kvm_memslots(kvm);
28a37544
XG		 2834 slot = id_to_memslot(slots, 0);
2835 base_gfn = slot->base_gfn + slot->npages - 3;
2836
cbc94022
IE		 2837 return base_gfn << PAGE_SHIFT;
2838 }
bfc6d222 2839 return kvm->arch.tss_addr;
6aa8b732
AK		 2840}
2841
f5f7b2fe 2842static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2843{
772e0318 2844 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2845 struct kvm_segment var = *save;
2846
2847 var.dpl = 0x3;
2848 if (seg == VCPU_SREG_CS)
2849 var.type = 0x3;
2850
2851 if (!emulate_invalid_guest_state) {
2852 var.selector = var.base >> 4;
2853 var.base = var.base & 0xffff0;
2854 var.limit = 0xffff;
2855 var.g = 0;
2856 var.db = 0;
2857 var.present = 1;
2858 var.s = 1;
2859 var.l = 0;
2860 var.unusable = 0;
2861 var.type = 0x3;
2862 var.avl = 0;
2863 if (save->base & 0xf)
2864 printk_once(KERN_WARNING "kvm: segment base is not "
2865 "paragraph aligned when entering "
2866 "protected mode (seg=%d)", seg);
2867 }
6aa8b732 2868
d99e4152
GN		 2869 vmcs_write16(sf->selector, var.selector);
2870 vmcs_write32(sf->base, var.base);
2871 vmcs_write32(sf->limit, var.limit);
2872 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2873}
2874
2875static void enter_rmode(struct kvm_vcpu *vcpu)
2876{
2877 unsigned long flags;
a89a8fb9 2878 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2879
3a624e29
NK		 2880 if (enable_unrestricted_guest)
2881 return;
2882
f5f7b2fe
AK		 2883 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2884 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2885 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2886 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2887 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2888 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2889 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2890
a89a8fb9 2891 vmx->emulation_required = 1;
7ffd92c5 2892 vmx->rmode.vm86_active = 1;
6aa8b732 2893
776e58ea
GN		 2894 /*
2895 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2896 * vcpu. Call it here with phys address pointing 16M below 4G.
2897 */
2898 if (!vcpu->kvm->arch.tss_addr) {
2899 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2900 "called before entering vcpu\n");
2901 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2902 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2903 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2904 }
2905
2fb92db1
AK		 2906 vmx_segment_cache_clear(vmx);
2907
6aa8b732 2908 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2909 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2910 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2911
2912 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2913 vmx->rmode.save_rflags = flags;
6aa8b732 2914
053de044 2915 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2916
2917 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2918 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2919 update_exception_bitmap(vcpu);
2920
d99e4152
GN		 2921 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2922 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2923 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2924 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2925 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2926 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2927
8668a3c4 2928 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2929}
2930
401d10de
AS		 2931static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2932{
2933 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2934 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2935
2936 if (!msr)
2937 return;
401d10de 2938
44ea2b17
AK		 2939 /*
2940 * Force kernel_gs_base reloading before EFER changes, as control
2941 * of this msr depends on is_long_mode().
2942 */
2943 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2944 vcpu->arch.efer = efer;
401d10de
AS		 2945 if (efer & EFER_LMA) {
2946 vmcs_write32(VM_ENTRY_CONTROLS,
2947 vmcs_read32(VM_ENTRY_CONTROLS) |
2948 VM_ENTRY_IA32E_MODE);
2949 msr->data = efer;
2950 } else {
2951 vmcs_write32(VM_ENTRY_CONTROLS,
2952 vmcs_read32(VM_ENTRY_CONTROLS) &
2953 ~VM_ENTRY_IA32E_MODE);
2954
2955 msr->data = efer & ~EFER_LME;
2956 }
2957 setup_msrs(vmx);
2958}
2959
05b3e0c2 2960#ifdef CONFIG_X86_64
6aa8b732
AK		 2961
2962static void enter_lmode(struct kvm_vcpu *vcpu)
2963{
2964 u32 guest_tr_ar;
2965
2fb92db1
AK		 2966 vmx_segment_cache_clear(to_vmx(vcpu));
2967
6aa8b732
AK		 2968 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2969 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2970 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2971 __func__);
6aa8b732
AK		 2972 vmcs_write32(GUEST_TR_AR_BYTES,
2973 (guest_tr_ar & ~AR_TYPE_MASK)
2974 | AR_TYPE_BUSY_64_TSS);
2975 }
da38f438 2976 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2977}
2978
2979static void exit_lmode(struct kvm_vcpu *vcpu)
2980{
6aa8b732
AK		 2981 vmcs_write32(VM_ENTRY_CONTROLS,
2982 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2983 & ~VM_ENTRY_IA32E_MODE);
da38f438 2984 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2985}
2986
2987#endif
2988
2384d2b3
SY		 2989static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2990{
b9d762fa 2991 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2992 if (enable_ept) {
2993 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2994 return;
4e1096d2 2995 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2996 }
2384d2b3
SY		 2997}
2998
e8467fda
AK		 2999static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3000{
3001 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3002
3003 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3004 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3005}
3006
aff48baa
AK		 3007static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3008{
3009 if (enable_ept && is_paging(vcpu))
3010 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3011 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3012}
3013
25c4c276 3014static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3015{
fc78f519
AK		 3016 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3017
3018 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3019 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3020}
3021
1439442c
SY		 3022static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3023{
6de4f3ad
AK		 3024 if (!test_bit(VCPU_EXREG_PDPTR,
3025 (unsigned long *)&vcpu->arch.regs_dirty))
3026 return;
3027
1439442c 3028 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3029 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3030 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3031 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3032 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3033 }
3034}
3035
8f5d549f
AK		 3036static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3037{
3038 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3039 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3040 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3041 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3042 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3043 }
6de4f3ad
AK		 3044
3045 __set_bit(VCPU_EXREG_PDPTR,
3046 (unsigned long *)&vcpu->arch.regs_avail);
3047 __set_bit(VCPU_EXREG_PDPTR,
3048 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3049}
3050
5e1746d6 3051static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3052
3053static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3054 unsigned long cr0,
3055 struct kvm_vcpu *vcpu)
3056{
5233dd51
MT		 3057 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3058 vmx_decache_cr3(vcpu);
1439442c
SY		 3059 if (!(cr0 & X86_CR0_PG)) {
3060 /* From paging/starting to nonpaging */
3061 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3062 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3063 (CPU_BASED_CR3_LOAD_EXITING |
3064 CPU_BASED_CR3_STORE_EXITING));
3065 vcpu->arch.cr0 = cr0;
fc78f519 3066 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3067 } else if (!is_paging(vcpu)) {
3068 /* From nonpaging to paging */
3069 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3070 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3071 ~(CPU_BASED_CR3_LOAD_EXITING |
3072 CPU_BASED_CR3_STORE_EXITING));
3073 vcpu->arch.cr0 = cr0;
fc78f519 3074 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3075 }
95eb84a7
SY		 3076
3077 if (!(cr0 & X86_CR0_WP))
3078 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3079}
3080
6aa8b732
AK		 3081static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3082{
7ffd92c5 3083 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3084 unsigned long hw_cr0;
3085
3086 if (enable_unrestricted_guest)
3087 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3088 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3089 else
3090 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3091
7ffd92c5 3092 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3093 enter_pmode(vcpu);
3094
7ffd92c5 3095 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3096 enter_rmode(vcpu);
3097
05b3e0c2 3098#ifdef CONFIG_X86_64
f6801dff 3099 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3100 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3101 enter_lmode(vcpu);
707d92fa 3102 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3103 exit_lmode(vcpu);
3104 }
3105#endif
3106
089d034e 3107 if (enable_ept)
1439442c
SY		 3108 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3109
02daab21 3110 if (!vcpu->fpu_active)
81231c69 3111 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3112
6aa8b732 3113 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3114 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3115 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 3116}
3117
1439442c
SY		 3118static u64 construct_eptp(unsigned long root_hpa)
3119{
3120 u64 eptp;
3121
3122 /* TODO write the value reading from MSR */
3123 eptp = VMX_EPT_DEFAULT_MT |
3124 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3125 if (enable_ept_ad_bits)
3126 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3127 eptp |= (root_hpa & PAGE_MASK);
3128
3129 return eptp;
3130}
3131
6aa8b732
AK		 3132static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3133{
1439442c
SY		 3134 unsigned long guest_cr3;
3135 u64 eptp;
3136
3137 guest_cr3 = cr3;
089d034e 3138 if (enable_ept) {
1439442c
SY		 3139 eptp = construct_eptp(cr3);
3140 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3141 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3142 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3143 ept_load_pdptrs(vcpu);
1439442c
SY		 3144 }
3145
2384d2b3 3146 vmx_flush_tlb(vcpu);
1439442c 3147 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3148}
3149
5e1746d6 3150static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3151{
7ffd92c5 3152 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3153 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3154
5e1746d6
NHE		 3155 if (cr4 & X86_CR4_VMXE) {
3156 /*
3157 * To use VMXON (and later other VMX instructions), a guest
3158 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3159 * So basically the check on whether to allow nested VMX
3160 * is here.
3161 */
3162 if (!nested_vmx_allowed(vcpu))
3163 return 1;
3164 } else if (to_vmx(vcpu)->nested.vmxon)
3165 return 1;
3166
ad312c7c 3167 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3168 if (enable_ept) {
3169 if (!is_paging(vcpu)) {
3170 hw_cr4 &= ~X86_CR4_PAE;
3171 hw_cr4 |= X86_CR4_PSE;
3172 } else if (!(cr4 & X86_CR4_PAE)) {
3173 hw_cr4 &= ~X86_CR4_PAE;
3174 }
3175 }
1439442c
SY		 3176
3177 vmcs_writel(CR4_READ_SHADOW, cr4);
3178 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3179 return 0;
6aa8b732
AK		 3180}
3181
6aa8b732
AK		 3182static void vmx_get_segment(struct kvm_vcpu *vcpu,
3183 struct kvm_segment *var, int seg)
3184{
a9179499 3185 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3186 u32 ar;
3187
c6ad1153 3188 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3189 *var = vmx->rmode.segs[seg];
a9179499 3190 if (seg == VCPU_SREG_TR
2fb92db1 3191 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3192 return;
1390a28b
AK		 3193 var->base = vmx_read_guest_seg_base(vmx, seg);
3194 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3195 return;
a9179499 3196 }
2fb92db1
AK		 3197 var->base = vmx_read_guest_seg_base(vmx, seg);
3198 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3199 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3200 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3201 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3202 ar = 0;
3203 var->type = ar & 15;
3204 var->s = (ar >> 4) & 1;
3205 var->dpl = (ar >> 5) & 3;
3206 var->present = (ar >> 7) & 1;
3207 var->avl = (ar >> 12) & 1;
3208 var->l = (ar >> 13) & 1;
3209 var->db = (ar >> 14) & 1;
3210 var->g = (ar >> 15) & 1;
3211 var->unusable = (ar >> 16) & 1;
3212}
3213
a9179499
AK		 3214static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3215{
a9179499
AK		 3216 struct kvm_segment s;
3217
3218 if (to_vmx(vcpu)->rmode.vm86_active) {
3219 vmx_get_segment(vcpu, &s, seg);
3220 return s.base;
3221 }
2fb92db1 3222 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3223}
3224
b09408d0 3225static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3226{
b09408d0
MT		 3227 struct vcpu_vmx *vmx = to_vmx(vcpu);
3228
3eeb3288 3229 if (!is_protmode(vcpu))
2e4d2653
IE		 3230 return 0;
3231
f4c63e5d
AK		 3232 if (!is_long_mode(vcpu)
3233 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3234 return 3;
3235
69c73028
AK		 3236 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3237 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3238 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3239 }
d881e6f6
AK		 3240
3241 return vmx->cpl;
69c73028
AK		 3242}
3243
3244
653e3108 3245static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3246{
6aa8b732
AK		 3247 u32 ar;
3248
f0495f9b 3249 if (var->unusable || !var->present)
6aa8b732
AK		 3250 ar = 1 << 16;
3251 else {
3252 ar = var->type & 15;
3253 ar |= (var->s & 1) << 4;
3254 ar |= (var->dpl & 3) << 5;
3255 ar |= (var->present & 1) << 7;
3256 ar |= (var->avl & 1) << 12;
3257 ar |= (var->l & 1) << 13;
3258 ar |= (var->db & 1) << 14;
3259 ar |= (var->g & 1) << 15;
3260 }
653e3108
AK		 3261
3262 return ar;
3263}
3264
3265static void vmx_set_segment(struct kvm_vcpu *vcpu,
3266 struct kvm_segment *var, int seg)
3267{
7ffd92c5 3268 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3269 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3270
2fb92db1 3271 vmx_segment_cache_clear(vmx);
2f143240
GN		 3272 if (seg == VCPU_SREG_CS)
3273 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3274
1ecd50a9
GN		 3275 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3276 vmx->rmode.segs[seg] = *var;
3277 if (seg == VCPU_SREG_TR)
3278 vmcs_write16(sf->selector, var->selector);
3279 else if (var->s)
3280 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3281 goto out;
653e3108 3282 }
1ecd50a9 3283
653e3108
AK		 3284 vmcs_writel(sf->base, var->base);
3285 vmcs_write32(sf->limit, var->limit);
3286 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3287
3288 /*
3289 * Fix the "Accessed" bit in AR field of segment registers for older
3290 * qemu binaries.
3291 * IA32 arch specifies that at the time of processor reset the
3292 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3293 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3294 * state vmexit when "unrestricted guest" mode is turned on.
3295 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3296 * tree. Newer qemu binaries with that qemu fix would not need this
3297 * kvm hack.
3298 */
3299 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3300 var->type |= 0x1; /* Accessed */
3a624e29 3301
f924d66d 3302 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3303
3304out:
3305 if (!vmx->emulation_required)
3306 vmx->emulation_required = !guest_state_valid(vcpu);
6aa8b732
AK		 3307}
3308
6aa8b732
AK		 3309static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3310{
2fb92db1 3311 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3312
3313 *db = (ar >> 14) & 1;
3314 *l = (ar >> 13) & 1;
3315}
3316
89a27f4d 3317static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3318{
89a27f4d
GN		 3319 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3320 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3321}
3322
89a27f4d 3323static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3324{
89a27f4d
GN		 3325 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3326 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3327}
3328
89a27f4d 3329static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3330{
89a27f4d
GN		 3331 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3332 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3333}
3334
89a27f4d 3335static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3336{
89a27f4d
GN		 3337 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3338 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3339}
3340
648dfaa7
MG		 3341static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3342{
3343 struct kvm_segment var;
3344 u32 ar;
3345
3346 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3347 var.dpl = 0x3;
0647f4aa
GN		 3348 if (seg == VCPU_SREG_CS)
3349 var.type = 0x3;
648dfaa7
MG		 3350 ar = vmx_segment_access_rights(&var);
3351
3352 if (var.base != (var.selector << 4))
3353 return false;
89efbed0 3354 if (var.limit != 0xffff)
648dfaa7 3355 return false;
07f42f5f 3356 if (ar != 0xf3)
648dfaa7
MG		 3357 return false;
3358
3359 return true;
3360}
3361
3362static bool code_segment_valid(struct kvm_vcpu *vcpu)
3363{
3364 struct kvm_segment cs;
3365 unsigned int cs_rpl;
3366
3367 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3368 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3369
1872a3f4
AK		 3370 if (cs.unusable)
3371 return false;
648dfaa7
MG		 3372 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3373 return false;
3374 if (!cs.s)
3375 return false;
1872a3f4 3376 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3377 if (cs.dpl > cs_rpl)
3378 return false;
1872a3f4 3379 } else {
648dfaa7
MG		 3380 if (cs.dpl != cs_rpl)
3381 return false;
3382 }
3383 if (!cs.present)
3384 return false;
3385
3386 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3387 return true;
3388}
3389
3390static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3391{
3392 struct kvm_segment ss;
3393 unsigned int ss_rpl;
3394
3395 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3396 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3397
1872a3f4
AK		 3398 if (ss.unusable)
3399 return true;
3400 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3401 return false;
3402 if (!ss.s)
3403 return false;
3404 if (ss.dpl != ss_rpl) /* DPL != RPL */
3405 return false;
3406 if (!ss.present)
3407 return false;
3408
3409 return true;
3410}
3411
3412static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3413{
3414 struct kvm_segment var;
3415 unsigned int rpl;
3416
3417 vmx_get_segment(vcpu, &var, seg);
3418 rpl = var.selector & SELECTOR_RPL_MASK;
3419
1872a3f4
AK		 3420 if (var.unusable)
3421 return true;
648dfaa7
MG		 3422 if (!var.s)
3423 return false;
3424 if (!var.present)
3425 return false;
3426 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3427 if (var.dpl < rpl) /* DPL < RPL */
3428 return false;
3429 }
3430
3431 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3432 * rights flags
3433 */
3434 return true;
3435}
3436
3437static bool tr_valid(struct kvm_vcpu *vcpu)
3438{
3439 struct kvm_segment tr;
3440
3441 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3442
1872a3f4
AK		 3443 if (tr.unusable)
3444 return false;
648dfaa7
MG		 3445 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3446 return false;
1872a3f4 3447 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3448 return false;
3449 if (!tr.present)
3450 return false;
3451
3452 return true;
3453}
3454
3455static bool ldtr_valid(struct kvm_vcpu *vcpu)
3456{
3457 struct kvm_segment ldtr;
3458
3459 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3460
1872a3f4
AK		 3461 if (ldtr.unusable)
3462 return true;
648dfaa7
MG		 3463 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3464 return false;
3465 if (ldtr.type != 2)
3466 return false;
3467 if (!ldtr.present)
3468 return false;
3469
3470 return true;
3471}
3472
3473static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3474{
3475 struct kvm_segment cs, ss;
3476
3477 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3478 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3479
3480 return ((cs.selector & SELECTOR_RPL_MASK) ==
3481 (ss.selector & SELECTOR_RPL_MASK));
3482}
3483
3484/*
3485 * Check if guest state is valid. Returns true if valid, false if
3486 * not.
3487 * We assume that registers are always usable
3488 */
3489static bool guest_state_valid(struct kvm_vcpu *vcpu)
3490{
3491 /* real mode guest state checks */
3eeb3288 3492 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3493 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3494 return false;
3495 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3496 return false;
3497 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3498 return false;
3499 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3500 return false;
3501 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3502 return false;
3503 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3504 return false;
3505 } else {
3506 /* protected mode guest state checks */
3507 if (!cs_ss_rpl_check(vcpu))
3508 return false;
3509 if (!code_segment_valid(vcpu))
3510 return false;
3511 if (!stack_segment_valid(vcpu))
3512 return false;
3513 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3514 return false;
3515 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3516 return false;
3517 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3518 return false;
3519 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3520 return false;
3521 if (!tr_valid(vcpu))
3522 return false;
3523 if (!ldtr_valid(vcpu))
3524 return false;
3525 }
3526 /* TODO:
3527 * - Add checks on RIP
3528 * - Add checks on RFLAGS
3529 */
3530
3531 return true;
3532}
3533
d77c26fc 3534static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3535{
40dcaa9f 3536 gfn_t fn;
195aefde 3537 u16 data = 0;
40dcaa9f 3538 int r, idx, ret = 0;
6aa8b732 3539
40dcaa9f
XG		 3540 idx = srcu_read_lock(&kvm->srcu);
3541 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3542 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3543 if (r < 0)
10589a46 3544 goto out;
195aefde 3545 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3546 r = kvm_write_guest_page(kvm, fn++, &data,
3547 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3548 if (r < 0)
10589a46 3549 goto out;
195aefde
IE		 3550 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3551 if (r < 0)
10589a46 3552 goto out;
195aefde
IE		 3553 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3554 if (r < 0)
10589a46 3555 goto out;
195aefde 3556 data = ~0;
10589a46
MT		 3557 r = kvm_write_guest_page(kvm, fn, &data,
3558 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3559 sizeof(u8));
195aefde 3560 if (r < 0)
10589a46
MT		 3561 goto out;
3562
3563 ret = 1;
3564out:
40dcaa9f 3565 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3566 return ret;
6aa8b732
AK		 3567}
3568
b7ebfb05
SY		 3569static int init_rmode_identity_map(struct kvm *kvm)
3570{
40dcaa9f 3571 int i, idx, r, ret;
b7ebfb05
SY		 3572 pfn_t identity_map_pfn;
3573 u32 tmp;
3574
089d034e 3575 if (!enable_ept)
b7ebfb05
SY		 3576 return 1;
3577 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3578 printk(KERN_ERR "EPT: identity-mapping pagetable "
3579 "haven't been allocated!\n");
3580 return 0;
3581 }
3582 if (likely(kvm->arch.ept_identity_pagetable_done))
3583 return 1;
3584 ret = 0;
b927a3ce 3585 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3586 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3587 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3588 if (r < 0)
3589 goto out;
3590 /* Set up identity-mapping pagetable for EPT in real mode */
3591 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3592 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3593 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3594 r = kvm_write_guest_page(kvm, identity_map_pfn,
3595 &tmp, i * sizeof(tmp), sizeof(tmp));
3596 if (r < 0)
3597 goto out;
3598 }
3599 kvm->arch.ept_identity_pagetable_done = true;
3600 ret = 1;
3601out:
40dcaa9f 3602 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3603 return ret;
3604}
3605
6aa8b732
AK		 3606static void seg_setup(int seg)
3607{
772e0318 3608 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3609 unsigned int ar;
6aa8b732
AK		 3610
3611 vmcs_write16(sf->selector, 0);
3612 vmcs_writel(sf->base, 0);
3613 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3614 ar = 0x93;
3615 if (seg == VCPU_SREG_CS)
3616 ar |= 0x08; /* code segment */
3a624e29
NK		 3617
3618 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3619}
3620
f78e0e2e
SY		 3621static int alloc_apic_access_page(struct kvm *kvm)
3622{
4484141a 3623 struct page *page;
f78e0e2e
SY		 3624 struct kvm_userspace_memory_region kvm_userspace_mem;
3625 int r = 0;
3626
79fac95e 3627 mutex_lock(&kvm->slots_lock);
bfc6d222 3628 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3629 goto out;
3630 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3631 kvm_userspace_mem.flags = 0;
3632 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3633 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3634 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
f78e0e2e
SY		 3635 if (r)
3636 goto out;
72dc67a6 3637
4484141a
XG		 3638 page = gfn_to_page(kvm, 0xfee00);
3639 if (is_error_page(page)) {
3640 r = -EFAULT;
3641 goto out;
3642 }
3643
3644 kvm->arch.apic_access_page = page;
f78e0e2e 3645out:
79fac95e 3646 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3647 return r;
3648}
3649
b7ebfb05
SY		 3650static int alloc_identity_pagetable(struct kvm *kvm)
3651{
4484141a 3652 struct page *page;
b7ebfb05
SY		 3653 struct kvm_userspace_memory_region kvm_userspace_mem;
3654 int r = 0;
3655
79fac95e 3656 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3657 if (kvm->arch.ept_identity_pagetable)
3658 goto out;
3659 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3660 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3661 kvm_userspace_mem.guest_phys_addr =
3662 kvm->arch.ept_identity_map_addr;
b7ebfb05 3663 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3664 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
b7ebfb05
SY		 3665 if (r)
3666 goto out;
3667
4484141a
XG		 3668 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3669 if (is_error_page(page)) {
3670 r = -EFAULT;
3671 goto out;
3672 }
3673
3674 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3675out:
79fac95e 3676 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3677 return r;
3678}
3679
2384d2b3
SY		 3680static void allocate_vpid(struct vcpu_vmx *vmx)
3681{
3682 int vpid;
3683
3684 vmx->vpid = 0;
919818ab 3685 if (!enable_vpid)
2384d2b3
SY		 3686 return;
3687 spin_lock(&vmx_vpid_lock);
3688 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3689 if (vpid < VMX_NR_VPIDS) {
3690 vmx->vpid = vpid;
3691 __set_bit(vpid, vmx_vpid_bitmap);
3692 }
3693 spin_unlock(&vmx_vpid_lock);
3694}
3695
cdbecfc3
LJ		 3696static void free_vpid(struct vcpu_vmx *vmx)
3697{
3698 if (!enable_vpid)
3699 return;
3700 spin_lock(&vmx_vpid_lock);
3701 if (vmx->vpid != 0)
3702 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3703 spin_unlock(&vmx_vpid_lock);
3704}
3705
5897297b 3706static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3707{
3e7c73e9 3708 int f = sizeof(unsigned long);
25c5f225
SY		 3709
3710 if (!cpu_has_vmx_msr_bitmap())
3711 return;
3712
3713 /*
3714 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3715 * have the write-low and read-high bitmap offsets the wrong way round.
3716 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3717 */
25c5f225 3718 if (msr <= 0x1fff) {
3e7c73e9
AK		 3719 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3720 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3721 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3722 msr &= 0x1fff;
3e7c73e9
AK		 3723 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3724 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3725 }
25c5f225
SY		 3726}
3727
5897297b
AK		 3728static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3729{
3730 if (!longmode_only)
3731 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3732 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3733}
3734
a3a8ff8e
NHE		 3735/*
3736 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3737 * will not change in the lifetime of the guest.
3738 * Note that host-state that does change is set elsewhere. E.g., host-state
3739 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3740 */
3741static void vmx_set_constant_host_state(void)
3742{
3743 u32 low32, high32;
3744 unsigned long tmpl;
3745 struct desc_ptr dt;
3746
b1a74bf8 3747 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3748 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3749 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3750
3751 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3752#ifdef CONFIG_X86_64
3753 /*
3754 * Load null selectors, so we can avoid reloading them in
3755 * __vmx_load_host_state(), in case userspace uses the null selectors
3756 * too (the expected case).
3757 */
3758 vmcs_write16(HOST_DS_SELECTOR, 0);
3759 vmcs_write16(HOST_ES_SELECTOR, 0);
3760#else
a3a8ff8e
NHE		 3761 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3762 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3763#endif
a3a8ff8e
NHE		 3764 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3765 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3766
3767 native_store_idt(&dt);
3768 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3769
83287ea4 3770 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3771
3772 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3773 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3774 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3775 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3776
3777 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3778 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3779 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3780 }
3781}
3782
bf8179a0
NHE		 3783static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3784{
3785 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3786 if (enable_ept)
3787 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3788 if (is_guest_mode(&vmx->vcpu))
3789 vmx->vcpu.arch.cr4_guest_owned_bits &=
3790 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3791 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3792}
3793
3794static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3795{
3796 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3797 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3798 exec_control &= ~CPU_BASED_TPR_SHADOW;
3799#ifdef CONFIG_X86_64
3800 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3801 CPU_BASED_CR8_LOAD_EXITING;
3802#endif
3803 }
3804 if (!enable_ept)
3805 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3806 CPU_BASED_CR3_LOAD_EXITING |
3807 CPU_BASED_INVLPG_EXITING;
3808 return exec_control;
3809}
3810
3811static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3812{
3813 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3814 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3815 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3816 if (vmx->vpid == 0)
3817 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3818 if (!enable_ept) {
3819 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3820 enable_unrestricted_guest = 0;
ad756a16
MJ		 3821 /* Enable INVPCID for non-ept guests may cause performance regression. */
3822 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3823 }
3824 if (!enable_unrestricted_guest)
3825 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3826 if (!ple_gap)
3827 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3828 return exec_control;
3829}
3830
ce88decf
XG		 3831static void ept_set_mmio_spte_mask(void)
3832{
3833 /*
3834 * EPT Misconfigurations can be generated if the value of bits 2:0
3835 * of an EPT paging-structure entry is 110b (write/execute).
3836 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3837 * spte.
3838 */
3839 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3840}
3841
6aa8b732
AK		 3842/*
3843 * Sets up the vmcs for emulated real mode.
3844 */
8b9cf98c 3845static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3846{
2e4ce7f5 3847#ifdef CONFIG_X86_64
6aa8b732 3848 unsigned long a;
2e4ce7f5 3849#endif
6aa8b732 3850 int i;
6aa8b732 3851
6aa8b732 3852 /* I/O */
3e7c73e9
AK		 3853 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3854 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3855
25c5f225 3856 if (cpu_has_vmx_msr_bitmap())
5897297b 3857 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3858
6aa8b732
AK		 3859 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3860
6aa8b732 3861 /* Control */
1c3d14fe
YS		 3862 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3863 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3864
bf8179a0 3865 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3866
83ff3b9d 3867 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3868 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3869 vmx_secondary_exec_control(vmx));
83ff3b9d 3870 }
f78e0e2e 3871
4b8d54f9
ZE		 3872 if (ple_gap) {
3873 vmcs_write32(PLE_GAP, ple_gap);
3874 vmcs_write32(PLE_WINDOW, ple_window);
3875 }
3876
c3707958
XG		 3877 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3878 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3879 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3880
9581d442
AK		 3881 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3882 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3883 vmx_set_constant_host_state();
05b3e0c2 3884#ifdef CONFIG_X86_64
6aa8b732
AK		 3885 rdmsrl(MSR_FS_BASE, a);
3886 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3887 rdmsrl(MSR_GS_BASE, a);
3888 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3889#else
3890 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3891 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3892#endif
3893
2cc51560
ED		 3894 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3895 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3896 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3897 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3898 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3899
468d472f 3900 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3901 u32 msr_low, msr_high;
3902 u64 host_pat;
468d472f
SY		 3903 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3904 host_pat = msr_low | ((u64) msr_high << 32);
3905 /* Write the default value follow host pat */
3906 vmcs_write64(GUEST_IA32_PAT, host_pat);
3907 /* Keep arch.pat sync with GUEST_IA32_PAT */
3908 vmx->vcpu.arch.pat = host_pat;
3909 }
3910
6aa8b732
AK		 3911 for (i = 0; i < NR_VMX_MSR; ++i) {
3912 u32 index = vmx_msr_index[i];
3913 u32 data_low, data_high;
a2fa3e9f 3914 int j = vmx->nmsrs;
6aa8b732
AK		 3915
3916 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3917 continue;
432bd6cb
AK		 3918 if (wrmsr_safe(index, data_low, data_high) < 0)
3919 continue;
26bb0981
AK		 3920 vmx->guest_msrs[j].index = i;
3921 vmx->guest_msrs[j].data = 0;
d5696725 3922 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3923 ++vmx->nmsrs;
6aa8b732 3924 }
6aa8b732 3925
1c3d14fe 3926 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3927
3928 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3929 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3930
e00c8cf2 3931 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3932 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 3933
3934 return 0;
3935}
3936
3937static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3938{
3939 struct vcpu_vmx *vmx = to_vmx(vcpu);
3940 u64 msr;
4b9d3a04 3941 int ret;
e00c8cf2 3942
7ffd92c5 3943 vmx->rmode.vm86_active = 0;
e00c8cf2 3944
3b86cd99
JK		 3945 vmx->soft_vnmi_blocked = 0;
3946
ad312c7c 3947 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3948 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3949 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3950 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3951 msr |= MSR_IA32_APICBASE_BSP;
3952 kvm_set_apic_base(&vmx->vcpu, msr);
3953
2fb92db1
AK		 3954 vmx_segment_cache_clear(vmx);
3955
5706be0d 3956 seg_setup(VCPU_SREG_CS);
d54d07b2 3957 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2 3958 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
d54d07b2 3959 else {
ad312c7c
ZX		 3960 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3961 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3962 }
e00c8cf2
AK		 3963
3964 seg_setup(VCPU_SREG_DS);
3965 seg_setup(VCPU_SREG_ES);
3966 seg_setup(VCPU_SREG_FS);
3967 seg_setup(VCPU_SREG_GS);
3968 seg_setup(VCPU_SREG_SS);
3969
3970 vmcs_write16(GUEST_TR_SELECTOR, 0);
3971 vmcs_writel(GUEST_TR_BASE, 0);
3972 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3973 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3974
3975 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3976 vmcs_writel(GUEST_LDTR_BASE, 0);
3977 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3978 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3979
3980 vmcs_write32(GUEST_SYSENTER_CS, 0);
3981 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3982 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3983
3984 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3985 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3986 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3987 else
5fdbf976 3988 kvm_rip_write(vcpu, 0);
e00c8cf2 3989
e00c8cf2
AK		 3990 vmcs_writel(GUEST_GDTR_BASE, 0);
3991 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3992
3993 vmcs_writel(GUEST_IDTR_BASE, 0);
3994 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3995
443381a8 3996 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3997 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3998 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3999
e00c8cf2
AK		 4000 /* Special registers */
4001 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4002
4003 setup_msrs(vmx);
4004
6aa8b732
AK		 4005 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4006
f78e0e2e
SY		 4007 if (cpu_has_vmx_tpr_shadow()) {
4008 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4009 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4010 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4011 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4012 vmcs_write32(TPR_THRESHOLD, 0);
4013 }
4014
4015 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4016 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4017 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4018
2384d2b3
SY		 4019 if (vmx->vpid != 0)
4020 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4021
fa40052c 4022 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4023 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4024 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4025 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4026 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4027 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4028 vmx_fpu_activate(&vmx->vcpu);
4029 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4030
b9d762fa 4031 vpid_sync_context(vmx);
2384d2b3 4032
3200f405 4033 ret = 0;
6aa8b732 4034
a89a8fb9
MG		 4035 /* HACK: Don't enable emulation on guest boot/reset */
4036 vmx->emulation_required = 0;
4037
6aa8b732
AK		 4038 return ret;
4039}
4040
b6f1250e
NHE		 4041/*
4042 * In nested virtualization, check if L1 asked to exit on external interrupts.
4043 * For most existing hypervisors, this will always return true.
4044 */
4045static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4046{
4047 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4048 PIN_BASED_EXT_INTR_MASK;
4049}
4050
3b86cd99
JK		 4051static void enable_irq_window(struct kvm_vcpu *vcpu)
4052{
4053 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4054 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4055 /*
4056 * We get here if vmx_interrupt_allowed() said we can't
4057 * inject to L1 now because L2 must run. Ask L2 to exit
4058 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4059 */
d6185f20 4060 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4061 return;
d6185f20 4062 }
3b86cd99
JK		 4063
4064 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4065 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4066 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4067}
4068
4069static void enable_nmi_window(struct kvm_vcpu *vcpu)
4070{
4071 u32 cpu_based_vm_exec_control;
4072
4073 if (!cpu_has_virtual_nmis()) {
4074 enable_irq_window(vcpu);
4075 return;
4076 }
4077
30bd0c4c
AK		 4078 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4079 enable_irq_window(vcpu);
4080 return;
4081 }
3b86cd99
JK		 4082 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4083 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4084 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4085}
4086
66fd3f7f 4087static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4088{
9c8cba37 4089 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4090 uint32_t intr;
4091 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4092
229456fc 4093 trace_kvm_inj_virq(irq);
2714d1d3 4094
fa89a817 4095 ++vcpu->stat.irq_injections;
7ffd92c5 4096 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4097 int inc_eip = 0;
4098 if (vcpu->arch.interrupt.soft)
4099 inc_eip = vcpu->arch.event_exit_inst_len;
4100 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4101 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4102 return;
4103 }
66fd3f7f
GN		 4104 intr = irq | INTR_INFO_VALID_MASK;
4105 if (vcpu->arch.interrupt.soft) {
4106 intr |= INTR_TYPE_SOFT_INTR;
4107 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4108 vmx->vcpu.arch.event_exit_inst_len);
4109 } else
4110 intr |= INTR_TYPE_EXT_INTR;
4111 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4112}
4113
f08864b4
SY		 4114static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4115{
66a5a347
JK		 4116 struct vcpu_vmx *vmx = to_vmx(vcpu);
4117
0b6ac343
NHE		 4118 if (is_guest_mode(vcpu))
4119 return;
4120
3b86cd99
JK		 4121 if (!cpu_has_virtual_nmis()) {
4122 /*
4123 * Tracking the NMI-blocked state in software is built upon
4124 * finding the next open IRQ window. This, in turn, depends on
4125 * well-behaving guests: They have to keep IRQs disabled at
4126 * least as long as the NMI handler runs. Otherwise we may
4127 * cause NMI nesting, maybe breaking the guest. But as this is
4128 * highly unlikely, we can live with the residual risk.
4129 */
4130 vmx->soft_vnmi_blocked = 1;
4131 vmx->vnmi_blocked_time = 0;
4132 }
4133
487b391d 4134 ++vcpu->stat.nmi_injections;
9d58b931 4135 vmx->nmi_known_unmasked = false;
7ffd92c5 4136 if (vmx->rmode.vm86_active) {
71f9833b 4137 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4138 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4139 return;
4140 }
f08864b4
SY		 4141 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4142 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4143}
4144
c4282df9 4145static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4146{
3b86cd99 4147 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4148 return 0;
33f089ca 4149
c4282df9 4150 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4151 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4152 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4153}
4154
3cfc3092
JK		 4155static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4156{
4157 if (!cpu_has_virtual_nmis())
4158 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4159 if (to_vmx(vcpu)->nmi_known_unmasked)
4160 return false;
c332c83a 4161 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4162}
4163
4164static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4165{
4166 struct vcpu_vmx *vmx = to_vmx(vcpu);
4167
4168 if (!cpu_has_virtual_nmis()) {
4169 if (vmx->soft_vnmi_blocked != masked) {
4170 vmx->soft_vnmi_blocked = masked;
4171 vmx->vnmi_blocked_time = 0;
4172 }
4173 } else {
9d58b931 4174 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4175 if (masked)
4176 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4177 GUEST_INTR_STATE_NMI);
4178 else
4179 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4180 GUEST_INTR_STATE_NMI);
4181 }
4182}
4183
78646121
GN		 4184static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4185{
b6f1250e 4186 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4187 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4188 if (to_vmx(vcpu)->nested.nested_run_pending ||
4189 (vmcs12->idt_vectoring_info_field &
4190 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4191 return 0;
4192 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4193 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4194 vmcs12->vm_exit_intr_info = 0;
4195 /* fall through to normal code, but now in L1, not L2 */
4196 }
4197
c4282df9
GN		 4198 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4199 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4200 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4201}
4202
cbc94022
IE		 4203static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4204{
4205 int ret;
4206 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4207 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4208 .guest_phys_addr = addr,
4209 .memory_size = PAGE_SIZE * 3,
4210 .flags = 0,
4211 };
4212
f82a8cfe 4213 ret = kvm_set_memory_region(kvm, &tss_mem, false);
cbc94022
IE		 4214 if (ret)
4215 return ret;
bfc6d222 4216 kvm->arch.tss_addr = addr;
93ea5388
GN		 4217 if (!init_rmode_tss(kvm))
4218 return -ENOMEM;
4219
cbc94022
IE		 4220 return 0;
4221}
4222
0ca1b4f4 4223static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4224{
77ab6db0 4225 switch (vec) {
77ab6db0 4226 case BP_VECTOR:
c573cd22
JK		 4227 /*
4228 * Update instruction length as we may reinject the exception
4229 * from user space while in guest debugging mode.
4230 */
4231 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4232 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4233 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4234 return false;
4235 /* fall through */
4236 case DB_VECTOR:
4237 if (vcpu->guest_debug &
4238 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4239 return false;
d0bfb940
JK		 4240 /* fall through */
4241 case DE_VECTOR:
77ab6db0
JK		 4242 case OF_VECTOR:
4243 case BR_VECTOR:
4244 case UD_VECTOR:
4245 case DF_VECTOR:
4246 case SS_VECTOR:
4247 case GP_VECTOR:
4248 case MF_VECTOR:
0ca1b4f4
GN		 4249 return true;
4250 break;
77ab6db0 4251 }
0ca1b4f4
GN		 4252 return false;
4253}
4254
4255static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4256 int vec, u32 err_code)
4257{
4258 /*
4259 * Instruction with address size override prefix opcode 0x67
4260 * Cause the #SS fault with 0 error code in VM86 mode.
4261 */
4262 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4263 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4264 if (vcpu->arch.halt_request) {
4265 vcpu->arch.halt_request = 0;
4266 return kvm_emulate_halt(vcpu);
4267 }
4268 return 1;
4269 }
4270 return 0;
4271 }
4272
4273 /*
4274 * Forward all other exceptions that are valid in real mode.
4275 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4276 * the required debugging infrastructure rework.
4277 */
4278 kvm_queue_exception(vcpu, vec);
4279 return 1;
6aa8b732
AK		 4280}
4281
a0861c02
AK		 4282/*
4283 * Trigger machine check on the host. We assume all the MSRs are already set up
4284 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4285 * We pass a fake environment to the machine check handler because we want
4286 * the guest to be always treated like user space, no matter what context
4287 * it used internally.
4288 */
4289static void kvm_machine_check(void)
4290{
4291#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4292 struct pt_regs regs = {
4293 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4294 .flags = X86_EFLAGS_IF,
4295 };
4296
4297 do_machine_check(&regs, 0);
4298#endif
4299}
4300
851ba692 4301static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4302{
4303 /* already handled by vcpu_run */
4304 return 1;
4305}
4306
851ba692 4307static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4308{
1155f76a 4309 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4310 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4311 u32 intr_info, ex_no, error_code;
42dbaa5a 4312 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4313 u32 vect_info;
4314 enum emulation_result er;
4315
1155f76a 4316 vect_info = vmx->idt_vectoring_info;
88786475 4317 intr_info = vmx->exit_intr_info;
6aa8b732 4318
a0861c02 4319 if (is_machine_check(intr_info))
851ba692 4320 return handle_machine_check(vcpu);
a0861c02 4321
e4a41889 4322 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4323 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4324
4325 if (is_no_device(intr_info)) {
5fd86fcf 4326 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4327 return 1;
4328 }
4329
7aa81cc0 4330 if (is_invalid_opcode(intr_info)) {
51d8b661 4331 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4332 if (er != EMULATE_DONE)
7ee5d940 4333 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4334 return 1;
4335 }
4336
6aa8b732 4337 error_code = 0;
2e11384c 4338 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4339 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4340
4341 /*
4342 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4343 * MMIO, it is better to report an internal error.
4344 * See the comments in vmx_handle_exit.
4345 */
4346 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4347 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4348 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4349 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4350 vcpu->run->internal.ndata = 2;
4351 vcpu->run->internal.data[0] = vect_info;
4352 vcpu->run->internal.data[1] = intr_info;
4353 return 0;
4354 }
4355
6aa8b732 4356 if (is_page_fault(intr_info)) {
1439442c 4357 /* EPT won't cause page fault directly */
cf3ace79 4358 BUG_ON(enable_ept);
6aa8b732 4359 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4360 trace_kvm_page_fault(cr2, error_code);
4361
3298b75c 4362 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4363 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4364 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4365 }
4366
d0bfb940 4367 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4368
4369 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4370 return handle_rmode_exception(vcpu, ex_no, error_code);
4371
42dbaa5a
JK		 4372 switch (ex_no) {
4373 case DB_VECTOR:
4374 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4375 if (!(vcpu->guest_debug &
4376 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4377 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4378 kvm_queue_exception(vcpu, DB_VECTOR);
4379 return 1;
4380 }
4381 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4382 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4383 /* fall through */
4384 case BP_VECTOR:
c573cd22
JK		 4385 /*
4386 * Update instruction length as we may reinject #BP from
4387 * user space while in guest debugging mode. Reading it for
4388 * #DB as well causes no harm, it is not used in that case.
4389 */
4390 vmx->vcpu.arch.event_exit_inst_len =
4391 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4392 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4393 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4394 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4395 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4396 break;
4397 default:
d0bfb940
JK		 4398 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4399 kvm_run->ex.exception = ex_no;
4400 kvm_run->ex.error_code = error_code;
42dbaa5a 4401 break;
6aa8b732 4402 }
6aa8b732
AK		 4403 return 0;
4404}
4405
851ba692 4406static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4407{
1165f5fe 4408 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4409 return 1;
4410}
4411
851ba692 4412static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4413{
851ba692 4414 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4415 return 0;
4416}
6aa8b732 4417
851ba692 4418static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4419{
bfdaab09 4420 unsigned long exit_qualification;
34c33d16 4421 int size, in, string;
039576c0 4422 unsigned port;
6aa8b732 4423
bfdaab09 4424 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4425 string = (exit_qualification & 16) != 0;
cf8f70bf 4426 in = (exit_qualification & 8) != 0;
e70669ab 4427
cf8f70bf 4428 ++vcpu->stat.io_exits;
e70669ab 4429
cf8f70bf 4430 if (string || in)
51d8b661 4431 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4432
cf8f70bf
GN		 4433 port = exit_qualification >> 16;
4434 size = (exit_qualification & 7) + 1;
e93f36bc 4435 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4436
4437 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4438}
4439
102d8325
IM		 4440static void
4441vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4442{
4443 /*
4444 * Patch in the VMCALL instruction:
4445 */
4446 hypercall[0] = 0x0f;
4447 hypercall[1] = 0x01;
4448 hypercall[2] = 0xc1;
102d8325
IM		 4449}
4450
0fa06071 4451/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4452static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4453{
4454 if (to_vmx(vcpu)->nested.vmxon &&
4455 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4456 return 1;
4457
4458 if (is_guest_mode(vcpu)) {
4459 /*
4460 * We get here when L2 changed cr0 in a way that did not change
4461 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4462 * but did change L0 shadowed bits. This can currently happen
4463 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4464 * loading) while pretending to allow the guest to change it.
4465 */
4466 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4467 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4468 return 1;
4469 vmcs_writel(CR0_READ_SHADOW, val);
4470 return 0;
4471 } else
4472 return kvm_set_cr0(vcpu, val);
4473}
4474
4475static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4476{
4477 if (is_guest_mode(vcpu)) {
4478 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4479 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4480 return 1;
4481 vmcs_writel(CR4_READ_SHADOW, val);
4482 return 0;
4483 } else
4484 return kvm_set_cr4(vcpu, val);
4485}
4486
4487/* called to set cr0 as approriate for clts instruction exit. */
4488static void handle_clts(struct kvm_vcpu *vcpu)
4489{
4490 if (is_guest_mode(vcpu)) {
4491 /*
4492 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4493 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4494 * just pretend it's off (also in arch.cr0 for fpu_activate).
4495 */
4496 vmcs_writel(CR0_READ_SHADOW,
4497 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4498 vcpu->arch.cr0 &= ~X86_CR0_TS;
4499 } else
4500 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4501}
4502
851ba692 4503static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4504{
229456fc 4505 unsigned long exit_qualification, val;
6aa8b732
AK		 4506 int cr;
4507 int reg;
49a9b07e 4508 int err;
6aa8b732 4509
bfdaab09 4510 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4511 cr = exit_qualification & 15;
4512 reg = (exit_qualification >> 8) & 15;
4513 switch ((exit_qualification >> 4) & 3) {
4514 case 0: /* mov to cr */
229456fc
MT		 4515 val = kvm_register_read(vcpu, reg);
4516 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4517 switch (cr) {
4518 case 0:
eeadf9e7 4519 err = handle_set_cr0(vcpu, val);
db8fcefa 4520 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4521 return 1;
4522 case 3:
2390218b 4523 err = kvm_set_cr3(vcpu, val);
db8fcefa 4524 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4525 return 1;
4526 case 4:
eeadf9e7 4527 err = handle_set_cr4(vcpu, val);
db8fcefa 4528 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4529 return 1;
0a5fff19
GN		 4530 case 8: {
4531 u8 cr8_prev = kvm_get_cr8(vcpu);
4532 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4533 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4534 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4535 if (irqchip_in_kernel(vcpu->kvm))
4536 return 1;
4537 if (cr8_prev <= cr8)
4538 return 1;
851ba692 4539 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4540 return 0;
4541 }
4b8073e4 4542 }
6aa8b732 4543 break;
25c4c276 4544 case 2: /* clts */
eeadf9e7 4545 handle_clts(vcpu);
4d4ec087 4546 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4547 skip_emulated_instruction(vcpu);
6b52d186 4548 vmx_fpu_activate(vcpu);
25c4c276 4549 return 1;
6aa8b732
AK		 4550 case 1: /*mov from cr*/
4551 switch (cr) {
4552 case 3:
9f8fe504
AK		 4553 val = kvm_read_cr3(vcpu);
4554 kvm_register_write(vcpu, reg, val);
4555 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4556 skip_emulated_instruction(vcpu);
4557 return 1;
4558 case 8:
229456fc
MT		 4559 val = kvm_get_cr8(vcpu);
4560 kvm_register_write(vcpu, reg, val);
4561 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4562 skip_emulated_instruction(vcpu);
4563 return 1;
4564 }
4565 break;
4566 case 3: /* lmsw */
a1f83a74 4567 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4568 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4569 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4570
4571 skip_emulated_instruction(vcpu);
4572 return 1;
4573 default:
4574 break;
4575 }
851ba692 4576 vcpu->run->exit_reason = 0;
a737f256 4577 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4578 (int)(exit_qualification >> 4) & 3, cr);
4579 return 0;
4580}
4581
851ba692 4582static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4583{
bfdaab09 4584 unsigned long exit_qualification;
6aa8b732
AK		 4585 int dr, reg;
4586
f2483415 4587 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4588 if (!kvm_require_cpl(vcpu, 0))
4589 return 1;
42dbaa5a
JK		 4590 dr = vmcs_readl(GUEST_DR7);
4591 if (dr & DR7_GD) {
4592 /*
4593 * As the vm-exit takes precedence over the debug trap, we
4594 * need to emulate the latter, either for the host or the
4595 * guest debugging itself.
4596 */
4597 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4598 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4599 vcpu->run->debug.arch.dr7 = dr;
4600 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4601 vmcs_readl(GUEST_CS_BASE) +
4602 vmcs_readl(GUEST_RIP);
851ba692
AK		 4603 vcpu->run->debug.arch.exception = DB_VECTOR;
4604 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4605 return 0;
4606 } else {
4607 vcpu->arch.dr7 &= ~DR7_GD;
4608 vcpu->arch.dr6 |= DR6_BD;
4609 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4610 kvm_queue_exception(vcpu, DB_VECTOR);
4611 return 1;
4612 }
4613 }
4614
bfdaab09 4615 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4616 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4617 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4618 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4619 unsigned long val;
4620 if (!kvm_get_dr(vcpu, dr, &val))
4621 kvm_register_write(vcpu, reg, val);
4622 } else
4623 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4624 skip_emulated_instruction(vcpu);
4625 return 1;
4626}
4627
020df079
GN		 4628static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4629{
4630 vmcs_writel(GUEST_DR7, val);
4631}
4632
851ba692 4633static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4634{
06465c5a
AK		 4635 kvm_emulate_cpuid(vcpu);
4636 return 1;
6aa8b732
AK		 4637}
4638
851ba692 4639static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4640{
ad312c7c 4641 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4642 u64 data;
4643
4644 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4645 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4646 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4647 return 1;
4648 }
4649
229456fc 4650 trace_kvm_msr_read(ecx, data);
2714d1d3 4651
6aa8b732 4652 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4653 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4654 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4655 skip_emulated_instruction(vcpu);
4656 return 1;
4657}
4658
851ba692 4659static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4660{
8fe8ab46 4661 struct msr_data msr;
ad312c7c
ZX		 4662 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4663 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4664 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4665
8fe8ab46
WA		 4666 msr.data = data;
4667 msr.index = ecx;
4668 msr.host_initiated = false;
4669 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4670 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4671 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4672 return 1;
4673 }
4674
59200273 4675 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4676 skip_emulated_instruction(vcpu);
4677 return 1;
4678}
4679
851ba692 4680static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4681{
3842d135 4682 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4683 return 1;
4684}
4685
851ba692 4686static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4687{
85f455f7
ED		 4688 u32 cpu_based_vm_exec_control;
4689
4690 /* clear pending irq */
4691 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4692 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4693 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4694
3842d135
AK		 4695 kvm_make_request(KVM_REQ_EVENT, vcpu);
4696
a26bf12a 4697 ++vcpu->stat.irq_window_exits;
2714d1d3 4698
c1150d8c
DL		 4699 /*
4700 * If the user space waits to inject interrupts, exit as soon as
4701 * possible
4702 */
8061823a 4703 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4704 vcpu->run->request_interrupt_window &&
8061823a 4705 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4706 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4707 return 0;
4708 }
6aa8b732
AK		 4709 return 1;
4710}
4711
851ba692 4712static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4713{
4714 skip_emulated_instruction(vcpu);
d3bef15f 4715 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4716}
4717
851ba692 4718static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4719{
510043da 4720 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4721 kvm_emulate_hypercall(vcpu);
4722 return 1;
c21415e8
IM		 4723}
4724
ec25d5e6
GN		 4725static int handle_invd(struct kvm_vcpu *vcpu)
4726{
51d8b661 4727 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4728}
4729
851ba692 4730static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4731{
f9c617f6 4732 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4733
4734 kvm_mmu_invlpg(vcpu, exit_qualification);
4735 skip_emulated_instruction(vcpu);
4736 return 1;
4737}
4738
fee84b07
AK		 4739static int handle_rdpmc(struct kvm_vcpu *vcpu)
4740{
4741 int err;
4742
4743 err = kvm_rdpmc(vcpu);
4744 kvm_complete_insn_gp(vcpu, err);
4745
4746 return 1;
4747}
4748
851ba692 4749static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4750{
4751 skip_emulated_instruction(vcpu);
f5f48ee1 4752 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4753 return 1;
4754}
4755
2acf923e
DC		 4756static int handle_xsetbv(struct kvm_vcpu *vcpu)
4757{
4758 u64 new_bv = kvm_read_edx_eax(vcpu);
4759 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4760
4761 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4762 skip_emulated_instruction(vcpu);
4763 return 1;
4764}
4765
851ba692 4766static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4767{
58fbbf26
KT		 4768 if (likely(fasteoi)) {
4769 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4770 int access_type, offset;
4771
4772 access_type = exit_qualification & APIC_ACCESS_TYPE;
4773 offset = exit_qualification & APIC_ACCESS_OFFSET;
4774 /*
4775 * Sane guest uses MOV to write EOI, with written value
4776 * not cared. So make a short-circuit here by avoiding
4777 * heavy instruction emulation.
4778 */
4779 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4780 (offset == APIC_EOI)) {
4781 kvm_lapic_set_eoi(vcpu);
4782 skip_emulated_instruction(vcpu);
4783 return 1;
4784 }
4785 }
51d8b661 4786 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4787}
4788
851ba692 4789static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4790{
60637aac 4791 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4792 unsigned long exit_qualification;
e269fb21
JK		 4793 bool has_error_code = false;
4794 u32 error_code = 0;
37817f29 4795 u16 tss_selector;
7f3d35fd 4796 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4797
4798 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4799 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4800 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4801
4802 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4803
4804 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4805 if (reason == TASK_SWITCH_GATE && idt_v) {
4806 switch (type) {
4807 case INTR_TYPE_NMI_INTR:
4808 vcpu->arch.nmi_injected = false;
654f06fc 4809 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4810 break;
4811 case INTR_TYPE_EXT_INTR:
66fd3f7f 4812 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4813 kvm_clear_interrupt_queue(vcpu);
4814 break;
4815 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4816 if (vmx->idt_vectoring_info &
4817 VECTORING_INFO_DELIVER_CODE_MASK) {
4818 has_error_code = true;
4819 error_code =
4820 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4821 }
4822 /* fall through */
64a7ec06
GN		 4823 case INTR_TYPE_SOFT_EXCEPTION:
4824 kvm_clear_exception_queue(vcpu);
4825 break;
4826 default:
4827 break;
4828 }
60637aac 4829 }
37817f29
IE		 4830 tss_selector = exit_qualification;
4831
64a7ec06
GN		 4832 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4833 type != INTR_TYPE_EXT_INTR &&
4834 type != INTR_TYPE_NMI_INTR))
4835 skip_emulated_instruction(vcpu);
4836
7f3d35fd
KW		 4837 if (kvm_task_switch(vcpu, tss_selector,
4838 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4839 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4840 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4841 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4842 vcpu->run->internal.ndata = 0;
42dbaa5a 4843 return 0;
acb54517 4844 }
42dbaa5a
JK		 4845
4846 /* clear all local breakpoint enable flags */
4847 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4848
4849 /*
4850 * TODO: What about debug traps on tss switch?
4851 * Are we supposed to inject them and update dr6?
4852 */
4853
4854 return 1;
37817f29
IE		 4855}
4856
851ba692 4857static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4858{
f9c617f6 4859 unsigned long exit_qualification;
1439442c 4860 gpa_t gpa;
4f5982a5 4861 u32 error_code;
1439442c 4862 int gla_validity;
1439442c 4863
f9c617f6 4864 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 4865
1439442c
SY		 4866 gla_validity = (exit_qualification >> 7) & 0x3;
4867 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4868 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4869 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4870 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4871 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4872 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4873 (long unsigned int)exit_qualification);
851ba692
AK		 4874 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4875 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4876 return 0;
1439442c
SY		 4877 }
4878
4879 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4880 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4881
4882 /* It is a write fault? */
4883 error_code = exit_qualification & (1U << 1);
4884 /* ept page table is present? */
4885 error_code |= (exit_qualification >> 3) & 0x1;
4886
4887 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4888}
4889
68f89400
MT		 4890static u64 ept_rsvd_mask(u64 spte, int level)
4891{
4892 int i;
4893 u64 mask = 0;
4894
4895 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4896 mask |= (1ULL << i);
4897
4898 if (level > 2)
4899 /* bits 7:3 reserved */
4900 mask |= 0xf8;
4901 else if (level == 2) {
4902 if (spte & (1ULL << 7))
4903 /* 2MB ref, bits 20:12 reserved */
4904 mask |= 0x1ff000;
4905 else
4906 /* bits 6:3 reserved */
4907 mask |= 0x78;
4908 }
4909
4910 return mask;
4911}
4912
4913static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4914 int level)
4915{
4916 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4917
4918 /* 010b (write-only) */
4919 WARN_ON((spte & 0x7) == 0x2);
4920
4921 /* 110b (write/execute) */
4922 WARN_ON((spte & 0x7) == 0x6);
4923
4924 /* 100b (execute-only) and value not supported by logical processor */
4925 if (!cpu_has_vmx_ept_execute_only())
4926 WARN_ON((spte & 0x7) == 0x4);
4927
4928 /* not 000b */
4929 if ((spte & 0x7)) {
4930 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4931
4932 if (rsvd_bits != 0) {
4933 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4934 __func__, rsvd_bits);
4935 WARN_ON(1);
4936 }
4937
4938 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4939 u64 ept_mem_type = (spte & 0x38) >> 3;
4940
4941 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4942 ept_mem_type == 7) {
4943 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4944 __func__, ept_mem_type);
4945 WARN_ON(1);
4946 }
4947 }
4948 }
4949}
4950
851ba692 4951static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4952{
4953 u64 sptes[4];
ce88decf 4954 int nr_sptes, i, ret;
68f89400
MT		 4955 gpa_t gpa;
4956
4957 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4958
ce88decf
XG		 4959 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4960 if (likely(ret == 1))
4961 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4962 EMULATE_DONE;
4963 if (unlikely(!ret))
4964 return 1;
4965
4966 /* It is the real ept misconfig */
68f89400
MT		 4967 printk(KERN_ERR "EPT: Misconfiguration.\n");
4968 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4969
4970 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4971
4972 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4973 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4974
851ba692
AK		 4975 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4976 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4977
4978 return 0;
4979}
4980
851ba692 4981static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4982{
4983 u32 cpu_based_vm_exec_control;
4984
4985 /* clear pending NMI */
4986 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4987 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4988 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4989 ++vcpu->stat.nmi_window_exits;
3842d135 4990 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4991
4992 return 1;
4993}
4994
80ced186 4995static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4996{
8b3079a5
AK		 4997 struct vcpu_vmx *vmx = to_vmx(vcpu);
4998 enum emulation_result err = EMULATE_DONE;
80ced186 4999 int ret = 1;
49e9d557
AK		 5000 u32 cpu_exec_ctrl;
5001 bool intr_window_requested;
b8405c18 5002 unsigned count = 130;
49e9d557
AK		 5003
5004 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5005 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5006
b8405c18 5007 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5008 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5009 return handle_interrupt_window(&vmx->vcpu);
5010
de87dcdd
AK		 5011 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5012 return 1;
5013
51d8b661 5014 err = emulate_instruction(vcpu, 0);
ea953ef0 5015
80ced186
MG		 5016 if (err == EMULATE_DO_MMIO) {
5017 ret = 0;
5018 goto out;
5019 }
1d5a4d9b 5020
de5f70e0
AK		 5021 if (err != EMULATE_DONE) {
5022 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5023 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5024 vcpu->run->internal.ndata = 0;
6d77dbfc 5025 return 0;
de5f70e0 5026 }
ea953ef0
MG		 5027
5028 if (signal_pending(current))
80ced186 5029 goto out;
ea953ef0
MG		 5030 if (need_resched())
5031 schedule();
5032 }
5033
7c068e45 5034 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5035out:
5036 return ret;
ea953ef0
MG		 5037}
5038
4b8d54f9
ZE		 5039/*
5040 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5041 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5042 */
9fb41ba8 5043static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5044{
5045 skip_emulated_instruction(vcpu);
5046 kvm_vcpu_on_spin(vcpu);
5047
5048 return 1;
5049}
5050
59708670
SY		 5051static int handle_invalid_op(struct kvm_vcpu *vcpu)
5052{
5053 kvm_queue_exception(vcpu, UD_VECTOR);
5054 return 1;
5055}
5056
ff2f6fe9
NHE		 5057/*
5058 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5059 * We could reuse a single VMCS for all the L2 guests, but we also want the
5060 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5061 * allows keeping them loaded on the processor, and in the future will allow
5062 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5063 * every entry if they never change.
5064 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5065 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5066 *
5067 * The following functions allocate and free a vmcs02 in this pool.
5068 */
5069
5070/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5071static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5072{
5073 struct vmcs02_list *item;
5074 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5075 if (item->vmptr == vmx->nested.current_vmptr) {
5076 list_move(&item->list, &vmx->nested.vmcs02_pool);
5077 return &item->vmcs02;
5078 }
5079
5080 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5081 /* Recycle the least recently used VMCS. */
5082 item = list_entry(vmx->nested.vmcs02_pool.prev,
5083 struct vmcs02_list, list);
5084 item->vmptr = vmx->nested.current_vmptr;
5085 list_move(&item->list, &vmx->nested.vmcs02_pool);
5086 return &item->vmcs02;
5087 }
5088
5089 /* Create a new VMCS */
5090 item = (struct vmcs02_list *)
5091 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5092 if (!item)
5093 return NULL;
5094 item->vmcs02.vmcs = alloc_vmcs();
5095 if (!item->vmcs02.vmcs) {
5096 kfree(item);
5097 return NULL;
5098 }
5099 loaded_vmcs_init(&item->vmcs02);
5100 item->vmptr = vmx->nested.current_vmptr;
5101 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5102 vmx->nested.vmcs02_num++;
5103 return &item->vmcs02;
5104}
5105
5106/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5107static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5108{
5109 struct vmcs02_list *item;
5110 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5111 if (item->vmptr == vmptr) {
5112 free_loaded_vmcs(&item->vmcs02);
5113 list_del(&item->list);
5114 kfree(item);
5115 vmx->nested.vmcs02_num--;
5116 return;
5117 }
5118}
5119
5120/*
5121 * Free all VMCSs saved for this vcpu, except the one pointed by
5122 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5123 * currently used, if running L2), and vmcs01 when running L2.
5124 */
5125static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5126{
5127 struct vmcs02_list *item, *n;
5128 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5129 if (vmx->loaded_vmcs != &item->vmcs02)
5130 free_loaded_vmcs(&item->vmcs02);
5131 list_del(&item->list);
5132 kfree(item);
5133 }
5134 vmx->nested.vmcs02_num = 0;
5135
5136 if (vmx->loaded_vmcs != &vmx->vmcs01)
5137 free_loaded_vmcs(&vmx->vmcs01);
5138}
5139
ec378aee
NHE		 5140/*
5141 * Emulate the VMXON instruction.
5142 * Currently, we just remember that VMX is active, and do not save or even
5143 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5144 * do not currently need to store anything in that guest-allocated memory
5145 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5146 * argument is different from the VMXON pointer (which the spec says they do).
5147 */
5148static int handle_vmon(struct kvm_vcpu *vcpu)
5149{
5150 struct kvm_segment cs;
5151 struct vcpu_vmx *vmx = to_vmx(vcpu);
5152
5153 /* The Intel VMX Instruction Reference lists a bunch of bits that
5154 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5155 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5156 * Otherwise, we should fail with #UD. We test these now:
5157 */
5158 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5159 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5160 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5161 kvm_queue_exception(vcpu, UD_VECTOR);
5162 return 1;
5163 }
5164
5165 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5166 if (is_long_mode(vcpu) && !cs.l) {
5167 kvm_queue_exception(vcpu, UD_VECTOR);
5168 return 1;
5169 }
5170
5171 if (vmx_get_cpl(vcpu)) {
5172 kvm_inject_gp(vcpu, 0);
5173 return 1;
5174 }
5175
ff2f6fe9
NHE		 5176 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5177 vmx->nested.vmcs02_num = 0;
5178
ec378aee
NHE		 5179 vmx->nested.vmxon = true;
5180
5181 skip_emulated_instruction(vcpu);
5182 return 1;
5183}
5184
5185/*
5186 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5187 * for running VMX instructions (except VMXON, whose prerequisites are
5188 * slightly different). It also specifies what exception to inject otherwise.
5189 */
5190static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5191{
5192 struct kvm_segment cs;
5193 struct vcpu_vmx *vmx = to_vmx(vcpu);
5194
5195 if (!vmx->nested.vmxon) {
5196 kvm_queue_exception(vcpu, UD_VECTOR);
5197 return 0;
5198 }
5199
5200 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5201 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5202 (is_long_mode(vcpu) && !cs.l)) {
5203 kvm_queue_exception(vcpu, UD_VECTOR);
5204 return 0;
5205 }
5206
5207 if (vmx_get_cpl(vcpu)) {
5208 kvm_inject_gp(vcpu, 0);
5209 return 0;
5210 }
5211
5212 return 1;
5213}
5214
5215/*
5216 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5217 * just stops using VMX.
5218 */
5219static void free_nested(struct vcpu_vmx *vmx)
5220{
5221 if (!vmx->nested.vmxon)
5222 return;
5223 vmx->nested.vmxon = false;
a9d30f33
NHE		 5224 if (vmx->nested.current_vmptr != -1ull) {
5225 kunmap(vmx->nested.current_vmcs12_page);
5226 nested_release_page(vmx->nested.current_vmcs12_page);
5227 vmx->nested.current_vmptr = -1ull;
5228 vmx->nested.current_vmcs12 = NULL;
5229 }
fe3ef05c
NHE		 5230 /* Unpin physical memory we referred to in current vmcs02 */
5231 if (vmx->nested.apic_access_page) {
5232 nested_release_page(vmx->nested.apic_access_page);
5233 vmx->nested.apic_access_page = 0;
5234 }
ff2f6fe9
NHE		 5235
5236 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5237}
5238
5239/* Emulate the VMXOFF instruction */
5240static int handle_vmoff(struct kvm_vcpu *vcpu)
5241{
5242 if (!nested_vmx_check_permission(vcpu))
5243 return 1;
5244 free_nested(to_vmx(vcpu));
5245 skip_emulated_instruction(vcpu);
5246 return 1;
5247}
5248
064aea77
NHE		 5249/*
5250 * Decode the memory-address operand of a vmx instruction, as recorded on an
5251 * exit caused by such an instruction (run by a guest hypervisor).
5252 * On success, returns 0. When the operand is invalid, returns 1 and throws
5253 * #UD or #GP.
5254 */
5255static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5256 unsigned long exit_qualification,
5257 u32 vmx_instruction_info, gva_t *ret)
5258{
5259 /*
5260 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5261 * Execution", on an exit, vmx_instruction_info holds most of the
5262 * addressing components of the operand. Only the displacement part
5263 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5264 * For how an actual address is calculated from all these components,
5265 * refer to Vol. 1, "Operand Addressing".
5266 */
5267 int scaling = vmx_instruction_info & 3;
5268 int addr_size = (vmx_instruction_info >> 7) & 7;
5269 bool is_reg = vmx_instruction_info & (1u << 10);
5270 int seg_reg = (vmx_instruction_info >> 15) & 7;
5271 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5272 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5273 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5274 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5275
5276 if (is_reg) {
5277 kvm_queue_exception(vcpu, UD_VECTOR);
5278 return 1;
5279 }
5280
5281 /* Addr = segment_base + offset */
5282 /* offset = base + [index * scale] + displacement */
5283 *ret = vmx_get_segment_base(vcpu, seg_reg);
5284 if (base_is_valid)
5285 *ret += kvm_register_read(vcpu, base_reg);
5286 if (index_is_valid)
5287 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5288 *ret += exit_qualification; /* holds the displacement */
5289
5290 if (addr_size == 1) /* 32 bit */
5291 *ret &= 0xffffffff;
5292
5293 /*
5294 * TODO: throw #GP (and return 1) in various cases that the VM*
5295 * instructions require it - e.g., offset beyond segment limit,
5296 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5297 * address, and so on. Currently these are not checked.
5298 */
5299 return 0;
5300}
5301
0140caea
NHE		 5302/*
5303 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5304 * set the success or error code of an emulated VMX instruction, as specified
5305 * by Vol 2B, VMX Instruction Reference, "Conventions".
5306 */
5307static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5308{
5309 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5310 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5311 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5312}
5313
5314static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5315{
5316 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5317 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5318 X86_EFLAGS_SF | X86_EFLAGS_OF))
5319 | X86_EFLAGS_CF);
5320}
5321
5322static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5323 u32 vm_instruction_error)
5324{
5325 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5326 /*
5327 * failValid writes the error number to the current VMCS, which
5328 * can't be done there isn't a current VMCS.
5329 */
5330 nested_vmx_failInvalid(vcpu);
5331 return;
5332 }
5333 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5334 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5335 X86_EFLAGS_SF | X86_EFLAGS_OF))
5336 | X86_EFLAGS_ZF);
5337 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5338}
5339
27d6c865
NHE		 5340/* Emulate the VMCLEAR instruction */
5341static int handle_vmclear(struct kvm_vcpu *vcpu)
5342{
5343 struct vcpu_vmx *vmx = to_vmx(vcpu);
5344 gva_t gva;
5345 gpa_t vmptr;
5346 struct vmcs12 *vmcs12;
5347 struct page *page;
5348 struct x86_exception e;
5349
5350 if (!nested_vmx_check_permission(vcpu))
5351 return 1;
5352
5353 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5354 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5355 return 1;
5356
5357 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5358 sizeof(vmptr), &e)) {
5359 kvm_inject_page_fault(vcpu, &e);
5360 return 1;
5361 }
5362
5363 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5364 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5365 skip_emulated_instruction(vcpu);
5366 return 1;
5367 }
5368
5369 if (vmptr == vmx->nested.current_vmptr) {
5370 kunmap(vmx->nested.current_vmcs12_page);
5371 nested_release_page(vmx->nested.current_vmcs12_page);
5372 vmx->nested.current_vmptr = -1ull;
5373 vmx->nested.current_vmcs12 = NULL;
5374 }
5375
5376 page = nested_get_page(vcpu, vmptr);
5377 if (page == NULL) {
5378 /*
5379 * For accurate processor emulation, VMCLEAR beyond available
5380 * physical memory should do nothing at all. However, it is
5381 * possible that a nested vmx bug, not a guest hypervisor bug,
5382 * resulted in this case, so let's shut down before doing any
5383 * more damage:
5384 */
5385 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5386 return 1;
5387 }
5388 vmcs12 = kmap(page);
5389 vmcs12->launch_state = 0;
5390 kunmap(page);
5391 nested_release_page(page);
5392
5393 nested_free_vmcs02(vmx, vmptr);
5394
5395 skip_emulated_instruction(vcpu);
5396 nested_vmx_succeed(vcpu);
5397 return 1;
5398}
5399
cd232ad0
NHE		 5400static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5401
5402/* Emulate the VMLAUNCH instruction */
5403static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5404{
5405 return nested_vmx_run(vcpu, true);
5406}
5407
5408/* Emulate the VMRESUME instruction */
5409static int handle_vmresume(struct kvm_vcpu *vcpu)
5410{
5411
5412 return nested_vmx_run(vcpu, false);
5413}
5414
49f705c5
NHE		 5415enum vmcs_field_type {
5416 VMCS_FIELD_TYPE_U16 = 0,
5417 VMCS_FIELD_TYPE_U64 = 1,
5418 VMCS_FIELD_TYPE_U32 = 2,
5419 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5420};
5421
5422static inline int vmcs_field_type(unsigned long field)
5423{
5424 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5425 return VMCS_FIELD_TYPE_U32;
5426 return (field >> 13) & 0x3 ;
5427}
5428
5429static inline int vmcs_field_readonly(unsigned long field)
5430{
5431 return (((field >> 10) & 0x3) == 1);
5432}
5433
5434/*
5435 * Read a vmcs12 field. Since these can have varying lengths and we return
5436 * one type, we chose the biggest type (u64) and zero-extend the return value
5437 * to that size. Note that the caller, handle_vmread, might need to use only
5438 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5439 * 64-bit fields are to be returned).
5440 */
5441static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5442 unsigned long field, u64 *ret)
5443{
5444 short offset = vmcs_field_to_offset(field);
5445 char *p;
5446
5447 if (offset < 0)
5448 return 0;
5449
5450 p = ((char *)(get_vmcs12(vcpu))) + offset;
5451
5452 switch (vmcs_field_type(field)) {
5453 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5454 *ret = *((natural_width *)p);
5455 return 1;
5456 case VMCS_FIELD_TYPE_U16:
5457 *ret = *((u16 *)p);
5458 return 1;
5459 case VMCS_FIELD_TYPE_U32:
5460 *ret = *((u32 *)p);
5461 return 1;
5462 case VMCS_FIELD_TYPE_U64:
5463 *ret = *((u64 *)p);
5464 return 1;
5465 default:
5466 return 0; /* can never happen. */
5467 }
5468}
5469
5470/*
5471 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5472 * used before) all generate the same failure when it is missing.
5473 */
5474static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5475{
5476 struct vcpu_vmx *vmx = to_vmx(vcpu);
5477 if (vmx->nested.current_vmptr == -1ull) {
5478 nested_vmx_failInvalid(vcpu);
5479 skip_emulated_instruction(vcpu);
5480 return 0;
5481 }
5482 return 1;
5483}
5484
5485static int handle_vmread(struct kvm_vcpu *vcpu)
5486{
5487 unsigned long field;
5488 u64 field_value;
5489 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5490 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5491 gva_t gva = 0;
5492
5493 if (!nested_vmx_check_permission(vcpu) ||
5494 !nested_vmx_check_vmcs12(vcpu))
5495 return 1;
5496
5497 /* Decode instruction info and find the field to read */
5498 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5499 /* Read the field, zero-extended to a u64 field_value */
5500 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5501 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5502 skip_emulated_instruction(vcpu);
5503 return 1;
5504 }
5505 /*
5506 * Now copy part of this value to register or memory, as requested.
5507 * Note that the number of bits actually copied is 32 or 64 depending
5508 * on the guest's mode (32 or 64 bit), not on the given field's length.
5509 */
5510 if (vmx_instruction_info & (1u << 10)) {
5511 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5512 field_value);
5513 } else {
5514 if (get_vmx_mem_address(vcpu, exit_qualification,
5515 vmx_instruction_info, &gva))
5516 return 1;
5517 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5518 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5519 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5520 }
5521
5522 nested_vmx_succeed(vcpu);
5523 skip_emulated_instruction(vcpu);
5524 return 1;
5525}
5526
5527
5528static int handle_vmwrite(struct kvm_vcpu *vcpu)
5529{
5530 unsigned long field;
5531 gva_t gva;
5532 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5533 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5534 char *p;
5535 short offset;
5536 /* The value to write might be 32 or 64 bits, depending on L1's long
5537 * mode, and eventually we need to write that into a field of several
5538 * possible lengths. The code below first zero-extends the value to 64
5539 * bit (field_value), and then copies only the approriate number of
5540 * bits into the vmcs12 field.
5541 */
5542 u64 field_value = 0;
5543 struct x86_exception e;
5544
5545 if (!nested_vmx_check_permission(vcpu) ||
5546 !nested_vmx_check_vmcs12(vcpu))
5547 return 1;
5548
5549 if (vmx_instruction_info & (1u << 10))
5550 field_value = kvm_register_read(vcpu,
5551 (((vmx_instruction_info) >> 3) & 0xf));
5552 else {
5553 if (get_vmx_mem_address(vcpu, exit_qualification,
5554 vmx_instruction_info, &gva))
5555 return 1;
5556 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5557 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5558 kvm_inject_page_fault(vcpu, &e);
5559 return 1;
5560 }
5561 }
5562
5563
5564 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5565 if (vmcs_field_readonly(field)) {
5566 nested_vmx_failValid(vcpu,
5567 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5568 skip_emulated_instruction(vcpu);
5569 return 1;
5570 }
5571
5572 offset = vmcs_field_to_offset(field);
5573 if (offset < 0) {
5574 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5575 skip_emulated_instruction(vcpu);
5576 return 1;
5577 }
5578 p = ((char *) get_vmcs12(vcpu)) + offset;
5579
5580 switch (vmcs_field_type(field)) {
5581 case VMCS_FIELD_TYPE_U16:
5582 *(u16 *)p = field_value;
5583 break;
5584 case VMCS_FIELD_TYPE_U32:
5585 *(u32 *)p = field_value;
5586 break;
5587 case VMCS_FIELD_TYPE_U64:
5588 *(u64 *)p = field_value;
5589 break;
5590 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5591 *(natural_width *)p = field_value;
5592 break;
5593 default:
5594 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5595 skip_emulated_instruction(vcpu);
5596 return 1;
5597 }
5598
5599 nested_vmx_succeed(vcpu);
5600 skip_emulated_instruction(vcpu);
5601 return 1;
5602}
5603
63846663
NHE		 5604/* Emulate the VMPTRLD instruction */
5605static int handle_vmptrld(struct kvm_vcpu *vcpu)
5606{
5607 struct vcpu_vmx *vmx = to_vmx(vcpu);
5608 gva_t gva;
5609 gpa_t vmptr;
5610 struct x86_exception e;
5611
5612 if (!nested_vmx_check_permission(vcpu))
5613 return 1;
5614
5615 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5616 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5617 return 1;
5618
5619 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5620 sizeof(vmptr), &e)) {
5621 kvm_inject_page_fault(vcpu, &e);
5622 return 1;
5623 }
5624
5625 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5626 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5627 skip_emulated_instruction(vcpu);
5628 return 1;
5629 }
5630
5631 if (vmx->nested.current_vmptr != vmptr) {
5632 struct vmcs12 *new_vmcs12;
5633 struct page *page;
5634 page = nested_get_page(vcpu, vmptr);
5635 if (page == NULL) {
5636 nested_vmx_failInvalid(vcpu);
5637 skip_emulated_instruction(vcpu);
5638 return 1;
5639 }
5640 new_vmcs12 = kmap(page);
5641 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5642 kunmap(page);
5643 nested_release_page_clean(page);
5644 nested_vmx_failValid(vcpu,
5645 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5646 skip_emulated_instruction(vcpu);
5647 return 1;
5648 }
5649 if (vmx->nested.current_vmptr != -1ull) {
5650 kunmap(vmx->nested.current_vmcs12_page);
5651 nested_release_page(vmx->nested.current_vmcs12_page);
5652 }
5653
5654 vmx->nested.current_vmptr = vmptr;
5655 vmx->nested.current_vmcs12 = new_vmcs12;
5656 vmx->nested.current_vmcs12_page = page;
5657 }
5658
5659 nested_vmx_succeed(vcpu);
5660 skip_emulated_instruction(vcpu);
5661 return 1;
5662}
5663
6a4d7550
NHE		 5664/* Emulate the VMPTRST instruction */
5665static int handle_vmptrst(struct kvm_vcpu *vcpu)
5666{
5667 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5668 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5669 gva_t vmcs_gva;
5670 struct x86_exception e;
5671
5672 if (!nested_vmx_check_permission(vcpu))
5673 return 1;
5674
5675 if (get_vmx_mem_address(vcpu, exit_qualification,
5676 vmx_instruction_info, &vmcs_gva))
5677 return 1;
5678 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5679 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5680 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5681 sizeof(u64), &e)) {
5682 kvm_inject_page_fault(vcpu, &e);
5683 return 1;
5684 }
5685 nested_vmx_succeed(vcpu);
5686 skip_emulated_instruction(vcpu);
5687 return 1;
5688}
5689
6aa8b732
AK		 5690/*
5691 * The exit handlers return 1 if the exit was handled fully and guest execution
5692 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5693 * to be done to userspace and return 0.
5694 */
772e0318 5695static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5696 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5697 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5698 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5699 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5700 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5701 [EXIT_REASON_CR_ACCESS] = handle_cr,
5702 [EXIT_REASON_DR_ACCESS] = handle_dr,
5703 [EXIT_REASON_CPUID] = handle_cpuid,
5704 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5705 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5706 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5707 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5708 [EXIT_REASON_INVD] = handle_invd,
a7052897 5709 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5710 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5711 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5712 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5713 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5714 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5715 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5716 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5717 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5718 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5719 [EXIT_REASON_VMOFF] = handle_vmoff,
5720 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5721 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5722 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5723 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5724 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5725 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5726 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5727 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5728 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5729 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5730 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5731 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5732};
5733
5734static const int kvm_vmx_max_exit_handlers =
50a3485c 5735 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5736
644d711a
NHE		 5737/*
5738 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5739 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5740 * disinterest in the current event (read or write a specific MSR) by using an
5741 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5742 */
5743static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5744 struct vmcs12 *vmcs12, u32 exit_reason)
5745{
5746 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5747 gpa_t bitmap;
5748
5749 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5750 return 1;
5751
5752 /*
5753 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5754 * for the four combinations of read/write and low/high MSR numbers.
5755 * First we need to figure out which of the four to use:
5756 */
5757 bitmap = vmcs12->msr_bitmap;
5758 if (exit_reason == EXIT_REASON_MSR_WRITE)
5759 bitmap += 2048;
5760 if (msr_index >= 0xc0000000) {
5761 msr_index -= 0xc0000000;
5762 bitmap += 1024;
5763 }
5764
5765 /* Then read the msr_index'th bit from this bitmap: */
5766 if (msr_index < 1024*8) {
5767 unsigned char b;
5768 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5769 return 1 & (b >> (msr_index & 7));
5770 } else
5771 return 1; /* let L1 handle the wrong parameter */
5772}
5773
5774/*
5775 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5776 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5777 * intercept (via guest_host_mask etc.) the current event.
5778 */
5779static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5780 struct vmcs12 *vmcs12)
5781{
5782 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5783 int cr = exit_qualification & 15;
5784 int reg = (exit_qualification >> 8) & 15;
5785 unsigned long val = kvm_register_read(vcpu, reg);
5786
5787 switch ((exit_qualification >> 4) & 3) {
5788 case 0: /* mov to cr */
5789 switch (cr) {
5790 case 0:
5791 if (vmcs12->cr0_guest_host_mask &
5792 (val ^ vmcs12->cr0_read_shadow))
5793 return 1;
5794 break;
5795 case 3:
5796 if ((vmcs12->cr3_target_count >= 1 &&
5797 vmcs12->cr3_target_value0 == val) ||
5798 (vmcs12->cr3_target_count >= 2 &&
5799 vmcs12->cr3_target_value1 == val) ||
5800 (vmcs12->cr3_target_count >= 3 &&
5801 vmcs12->cr3_target_value2 == val) ||
5802 (vmcs12->cr3_target_count >= 4 &&
5803 vmcs12->cr3_target_value3 == val))
5804 return 0;
5805 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5806 return 1;
5807 break;
5808 case 4:
5809 if (vmcs12->cr4_guest_host_mask &
5810 (vmcs12->cr4_read_shadow ^ val))
5811 return 1;
5812 break;
5813 case 8:
5814 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5815 return 1;
5816 break;
5817 }
5818 break;
5819 case 2: /* clts */
5820 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5821 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5822 return 1;
5823 break;
5824 case 1: /* mov from cr */
5825 switch (cr) {
5826 case 3:
5827 if (vmcs12->cpu_based_vm_exec_control &
5828 CPU_BASED_CR3_STORE_EXITING)
5829 return 1;
5830 break;
5831 case 8:
5832 if (vmcs12->cpu_based_vm_exec_control &
5833 CPU_BASED_CR8_STORE_EXITING)
5834 return 1;
5835 break;
5836 }
5837 break;
5838 case 3: /* lmsw */
5839 /*
5840 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5841 * cr0. Other attempted changes are ignored, with no exit.
5842 */
5843 if (vmcs12->cr0_guest_host_mask & 0xe &
5844 (val ^ vmcs12->cr0_read_shadow))
5845 return 1;
5846 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5847 !(vmcs12->cr0_read_shadow & 0x1) &&
5848 (val & 0x1))
5849 return 1;
5850 break;
5851 }
5852 return 0;
5853}
5854
5855/*
5856 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5857 * should handle it ourselves in L0 (and then continue L2). Only call this
5858 * when in is_guest_mode (L2).
5859 */
5860static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5861{
5862 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5863 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5864 struct vcpu_vmx *vmx = to_vmx(vcpu);
5865 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5866
5867 if (vmx->nested.nested_run_pending)
5868 return 0;
5869
5870 if (unlikely(vmx->fail)) {
bd80158a
JK		 5871 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5872 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5873 return 1;
5874 }
5875
5876 switch (exit_reason) {
5877 case EXIT_REASON_EXCEPTION_NMI:
5878 if (!is_exception(intr_info))
5879 return 0;
5880 else if (is_page_fault(intr_info))
5881 return enable_ept;
5882 return vmcs12->exception_bitmap &
5883 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5884 case EXIT_REASON_EXTERNAL_INTERRUPT:
5885 return 0;
5886 case EXIT_REASON_TRIPLE_FAULT:
5887 return 1;
5888 case EXIT_REASON_PENDING_INTERRUPT:
5889 case EXIT_REASON_NMI_WINDOW:
5890 /*
5891 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5892 * (aka Interrupt Window Exiting) only when L1 turned it on,
5893 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5894 * Same for NMI Window Exiting.
5895 */
5896 return 1;
5897 case EXIT_REASON_TASK_SWITCH:
5898 return 1;
5899 case EXIT_REASON_CPUID:
5900 return 1;
5901 case EXIT_REASON_HLT:
5902 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5903 case EXIT_REASON_INVD:
5904 return 1;
5905 case EXIT_REASON_INVLPG:
5906 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5907 case EXIT_REASON_RDPMC:
5908 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5909 case EXIT_REASON_RDTSC:
5910 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5911 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5912 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5913 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5914 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5915 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5916 /*
5917 * VMX instructions trap unconditionally. This allows L1 to
5918 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5919 */
5920 return 1;
5921 case EXIT_REASON_CR_ACCESS:
5922 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5923 case EXIT_REASON_DR_ACCESS:
5924 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5925 case EXIT_REASON_IO_INSTRUCTION:
5926 /* TODO: support IO bitmaps */
5927 return 1;
5928 case EXIT_REASON_MSR_READ:
5929 case EXIT_REASON_MSR_WRITE:
5930 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5931 case EXIT_REASON_INVALID_STATE:
5932 return 1;
5933 case EXIT_REASON_MWAIT_INSTRUCTION:
5934 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5935 case EXIT_REASON_MONITOR_INSTRUCTION:
5936 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5937 case EXIT_REASON_PAUSE_INSTRUCTION:
5938 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5939 nested_cpu_has2(vmcs12,
5940 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5941 case EXIT_REASON_MCE_DURING_VMENTRY:
5942 return 0;
5943 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5944 return 1;
5945 case EXIT_REASON_APIC_ACCESS:
5946 return nested_cpu_has2(vmcs12,
5947 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5948 case EXIT_REASON_EPT_VIOLATION:
5949 case EXIT_REASON_EPT_MISCONFIG:
5950 return 0;
5951 case EXIT_REASON_WBINVD:
5952 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5953 case EXIT_REASON_XSETBV:
5954 return 1;
5955 default:
5956 return 1;
5957 }
5958}
5959
586f9607
AK		 5960static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5961{
5962 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5963 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5964}
5965
6aa8b732
AK		 5966/*
5967 * The guest has exited. See if we can fix it or if we need userspace
5968 * assistance.
5969 */
851ba692 5970static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5971{
29bd8a78 5972 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5973 u32 exit_reason = vmx->exit_reason;
1155f76a 5974 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5975
80ced186
MG		 5976 /* If guest state is invalid, start emulating */
5977 if (vmx->emulation_required && emulate_invalid_guest_state)
5978 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5979
b6f1250e
NHE		 5980 /*
5981 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5982 * we did not inject a still-pending event to L1 now because of
5983 * nested_run_pending, we need to re-enable this bit.
5984 */
5985 if (vmx->nested.nested_run_pending)
5986 kvm_make_request(KVM_REQ_EVENT, vcpu);
5987
509c75ea
NHE		 5988 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5989 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5990 vmx->nested.nested_run_pending = 1;
5991 else
5992 vmx->nested.nested_run_pending = 0;
5993
5994 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5995 nested_vmx_vmexit(vcpu);
5996 return 1;
5997 }
5998
5120702e
MG		 5999 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6000 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6001 vcpu->run->fail_entry.hardware_entry_failure_reason
6002 = exit_reason;
6003 return 0;
6004 }
6005
29bd8a78 6006 if (unlikely(vmx->fail)) {
851ba692
AK		 6007 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6008 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6009 = vmcs_read32(VM_INSTRUCTION_ERROR);
6010 return 0;
6011 }
6aa8b732 6012
b9bf6882
XG		 6013 /*
6014 * Note:
6015 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6016 * delivery event since it indicates guest is accessing MMIO.
6017 * The vm-exit can be triggered again after return to guest that
6018 * will cause infinite loop.
6019 */
d77c26fc 6020 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6021 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6022 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6023 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6024 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6025 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6026 vcpu->run->internal.ndata = 2;
6027 vcpu->run->internal.data[0] = vectoring_info;
6028 vcpu->run->internal.data[1] = exit_reason;
6029 return 0;
6030 }
3b86cd99 6031
644d711a
NHE		 6032 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6033 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6034 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6035 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6036 vmx->soft_vnmi_blocked = 0;
3b86cd99 6037 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6038 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6039 /*
6040 * This CPU don't support us in finding the end of an
6041 * NMI-blocked window if the guest runs with IRQs
6042 * disabled. So we pull the trigger after 1 s of
6043 * futile waiting, but inform the user about this.
6044 */
6045 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6046 "state on VCPU %d after 1 s timeout\n",
6047 __func__, vcpu->vcpu_id);
6048 vmx->soft_vnmi_blocked = 0;
3b86cd99 6049 }
3b86cd99
JK		 6050 }
6051
6aa8b732
AK		 6052 if (exit_reason < kvm_vmx_max_exit_handlers
6053 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6054 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6055 else {
851ba692
AK		 6056 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6057 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6058 }
6059 return 0;
6060}
6061
95ba8273 6062static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6063{
95ba8273 6064 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6065 vmcs_write32(TPR_THRESHOLD, 0);
6066 return;
6067 }
6068
95ba8273 6069 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6070}
6071
51aa01d1 6072static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6073{
00eba012
AK		 6074 u32 exit_intr_info;
6075
6076 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6077 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6078 return;
6079
c5ca8e57 6080 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6081 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6082
6083 /* Handle machine checks before interrupts are enabled */
00eba012 6084 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6085 kvm_machine_check();
6086
20f65983 6087 /* We need to handle NMIs before interrupts are enabled */
00eba012 6088 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6089 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6090 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6091 asm("int $2");
ff9d07a0
ZY		 6092 kvm_after_handle_nmi(&vmx->vcpu);
6093 }
51aa01d1 6094}
20f65983 6095
51aa01d1
AK		 6096static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6097{
c5ca8e57 6098 u32 exit_intr_info;
51aa01d1
AK		 6099 bool unblock_nmi;
6100 u8 vector;
6101 bool idtv_info_valid;
6102
6103 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6104
cf393f75 6105 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6106 if (vmx->nmi_known_unmasked)
6107 return;
c5ca8e57
AK		 6108 /*
6109 * Can't use vmx->exit_intr_info since we're not sure what
6110 * the exit reason is.
6111 */
6112 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6113 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6114 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6115 /*
7b4a25cb 6116 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6117 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6118 * a guest IRET fault.
7b4a25cb
GN		 6119 * SDM 3: 23.2.2 (September 2008)
6120 * Bit 12 is undefined in any of the following cases:
6121 * If the VM exit sets the valid bit in the IDT-vectoring
6122 * information field.
6123 * If the VM exit is due to a double fault.
cf393f75 6124 */
7b4a25cb
GN		 6125 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6126 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6127 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6128 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6129 else
6130 vmx->nmi_known_unmasked =
6131 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6132 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6133 } else if (unlikely(vmx->soft_vnmi_blocked))
6134 vmx->vnmi_blocked_time +=
6135 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6136}
6137
83422e17
AK		 6138static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6139 u32 idt_vectoring_info,
6140 int instr_len_field,
6141 int error_code_field)
51aa01d1 6142{
51aa01d1
AK		 6143 u8 vector;
6144 int type;
6145 bool idtv_info_valid;
6146
6147 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6148
37b96e98
GN		 6149 vmx->vcpu.arch.nmi_injected = false;
6150 kvm_clear_exception_queue(&vmx->vcpu);
6151 kvm_clear_interrupt_queue(&vmx->vcpu);
6152
6153 if (!idtv_info_valid)
6154 return;
6155
3842d135
AK		 6156 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6157
668f612f
AK		 6158 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6159 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6160
64a7ec06 6161 switch (type) {
37b96e98
GN		 6162 case INTR_TYPE_NMI_INTR:
6163 vmx->vcpu.arch.nmi_injected = true;
668f612f 6164 /*
7b4a25cb 6165 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6166 * Clear bit "block by NMI" before VM entry if a NMI
6167 * delivery faulted.
668f612f 6168 */
654f06fc 6169 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6170 break;
37b96e98 6171 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6172 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6173 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6174 /* fall through */
6175 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6176 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6177 u32 err = vmcs_read32(error_code_field);
37b96e98 6178 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6179 } else
6180 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6181 break;
66fd3f7f
GN		 6182 case INTR_TYPE_SOFT_INTR:
6183 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6184 vmcs_read32(instr_len_field);
66fd3f7f 6185 /* fall through */
37b96e98 6186 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6187 kvm_queue_interrupt(&vmx->vcpu, vector,
6188 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6189 break;
6190 default:
6191 break;
f7d9238f 6192 }
cf393f75
AK		 6193}
6194
83422e17
AK		 6195static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6196{
66c78ae4
NHE		 6197 if (is_guest_mode(&vmx->vcpu))
6198 return;
83422e17
AK		 6199 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6200 VM_EXIT_INSTRUCTION_LEN,
6201 IDT_VECTORING_ERROR_CODE);
6202}
6203
b463a6f7
AK		 6204static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6205{
66c78ae4
NHE		 6206 if (is_guest_mode(vcpu))
6207 return;
b463a6f7
AK		 6208 __vmx_complete_interrupts(to_vmx(vcpu),
6209 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6210 VM_ENTRY_INSTRUCTION_LEN,
6211 VM_ENTRY_EXCEPTION_ERROR_CODE);
6212
6213 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6214}
6215
d7cd9796
GN		 6216static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6217{
6218 int i, nr_msrs;
6219 struct perf_guest_switch_msr *msrs;
6220
6221 msrs = perf_guest_get_msrs(&nr_msrs);
6222
6223 if (!msrs)
6224 return;
6225
6226 for (i = 0; i < nr_msrs; i++)
6227 if (msrs[i].host == msrs[i].guest)
6228 clear_atomic_switch_msr(vmx, msrs[i].msr);
6229 else
6230 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6231 msrs[i].host);
6232}
6233
a3b5ba49 6234static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6235{
a2fa3e9f 6236 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6237 unsigned long debugctlmsr;
104f226b 6238
66c78ae4
NHE		 6239 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6240 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6241 if (vmcs12->idt_vectoring_info_field &
6242 VECTORING_INFO_VALID_MASK) {
6243 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6244 vmcs12->idt_vectoring_info_field);
6245 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6246 vmcs12->vm_exit_instruction_len);
6247 if (vmcs12->idt_vectoring_info_field &
6248 VECTORING_INFO_DELIVER_CODE_MASK)
6249 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6250 vmcs12->idt_vectoring_error_code);
6251 }
6252 }
6253
104f226b
AK		 6254 /* Record the guest's net vcpu time for enforced NMI injections. */
6255 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6256 vmx->entry_time = ktime_get();
6257
6258 /* Don't enter VMX if guest state is invalid, let the exit handler
6259 start emulation until we arrive back to a valid state */
6260 if (vmx->emulation_required && emulate_invalid_guest_state)
6261 return;
6262
6263 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6264 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6265 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6266 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6267
6268 /* When single-stepping over STI and MOV SS, we must clear the
6269 * corresponding interruptibility bits in the guest state. Otherwise
6270 * vmentry fails as it then expects bit 14 (BS) in pending debug
6271 * exceptions being set, but that's not correct for the guest debugging
6272 * case. */
6273 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6274 vmx_set_interrupt_shadow(vcpu, 0);
6275
d7cd9796 6276 atomic_switch_perf_msrs(vmx);
2a7921b7 6277 debugctlmsr = get_debugctlmsr();
d7cd9796 6278
d462b819 6279 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6280 asm(
6aa8b732 6281 /* Store host registers */
b188c81f
AK		 6282 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6283 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6284 "push %%" _ASM_CX " \n\t"
6285 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6286 "je 1f \n\t"
b188c81f 6287 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6288 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6289 "1: \n\t"
d3edefc0 6290 /* Reload cr2 if changed */
b188c81f
AK		 6291 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6292 "mov %%cr2, %%" _ASM_DX " \n\t"
6293 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6294 "je 2f \n\t"
b188c81f 6295 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6296 "2: \n\t"
6aa8b732 6297 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6298 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6299 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6300 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6301 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6302 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6303 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6304 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6305 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6306#ifdef CONFIG_X86_64
e08aa78a
AK		 6307 "mov %c[r8](%0), %%r8 \n\t"
6308 "mov %c[r9](%0), %%r9 \n\t"
6309 "mov %c[r10](%0), %%r10 \n\t"
6310 "mov %c[r11](%0), %%r11 \n\t"
6311 "mov %c[r12](%0), %%r12 \n\t"
6312 "mov %c[r13](%0), %%r13 \n\t"
6313 "mov %c[r14](%0), %%r14 \n\t"
6314 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6315#endif
b188c81f 6316 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6317
6aa8b732 6318 /* Enter guest mode */
83287ea4 6319 "jne 1f \n\t"
4ecac3fd 6320 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6321 "jmp 2f \n\t"
6322 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6323 "2: "
6aa8b732 6324 /* Save guest registers, load host registers, keep flags */
b188c81f 6325 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6326 "pop %0 \n\t"
b188c81f
AK		 6327 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6328 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6329 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6330 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6331 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6332 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6333 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6334#ifdef CONFIG_X86_64
e08aa78a
AK		 6335 "mov %%r8, %c[r8](%0) \n\t"
6336 "mov %%r9, %c[r9](%0) \n\t"
6337 "mov %%r10, %c[r10](%0) \n\t"
6338 "mov %%r11, %c[r11](%0) \n\t"
6339 "mov %%r12, %c[r12](%0) \n\t"
6340 "mov %%r13, %c[r13](%0) \n\t"
6341 "mov %%r14, %c[r14](%0) \n\t"
6342 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6343#endif
b188c81f
AK		 6344 "mov %%cr2, %%" _ASM_AX " \n\t"
6345 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6346
b188c81f 6347 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6348 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6349 ".pushsection .rodata \n\t"
6350 ".global vmx_return \n\t"
6351 "vmx_return: " _ASM_PTR " 2b \n\t"
6352 ".popsection"
e08aa78a 6353 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6354 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6355 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6356 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6357 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6358 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6359 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6360 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6361 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6362 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6363 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6364#ifdef CONFIG_X86_64
ad312c7c
ZX		 6365 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6366 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6367 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6368 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6369 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6370 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6371 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6372 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6373#endif
40712fae
AK		 6374 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6375 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6376 : "cc", "memory"
6377#ifdef CONFIG_X86_64
b188c81f 6378 , "rax", "rbx", "rdi", "rsi"
c2036300 6379 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6380#else
6381 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6382#endif
6383 );
6aa8b732 6384
2a7921b7
GN		 6385 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6386 if (debugctlmsr)
6387 update_debugctlmsr(debugctlmsr);
6388
aa67f609
AK		 6389#ifndef CONFIG_X86_64
6390 /*
6391 * The sysexit path does not restore ds/es, so we must set them to
6392 * a reasonable value ourselves.
6393 *
6394 * We can't defer this to vmx_load_host_state() since that function
6395 * may be executed in interrupt context, which saves and restore segments
6396 * around it, nullifying its effect.
6397 */
6398 loadsegment(ds, __USER_DS);
6399 loadsegment(es, __USER_DS);
6400#endif
6401
6de4f3ad 6402 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6403 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6404 | (1 << VCPU_EXREG_CPL)
aff48baa 6405 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6406 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6407 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6408 vcpu->arch.regs_dirty = 0;
6409
1155f76a
AK		 6410 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6411
66c78ae4
NHE		 6412 if (is_guest_mode(vcpu)) {
6413 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6414 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6415 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6416 vmcs12->idt_vectoring_error_code =
6417 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6418 vmcs12->vm_exit_instruction_len =
6419 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6420 }
6421 }
6422
d462b819 6423 vmx->loaded_vmcs->launched = 1;
1b6269db 6424
51aa01d1 6425 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6426 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6427
6428 vmx_complete_atomic_exit(vmx);
6429 vmx_recover_nmi_blocking(vmx);
cf393f75 6430 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6431}
6432
6aa8b732
AK		 6433static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6434{
fb3f0f51
RR		 6435 struct vcpu_vmx *vmx = to_vmx(vcpu);
6436
cdbecfc3 6437 free_vpid(vmx);
ec378aee 6438 free_nested(vmx);
d462b819 6439 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6440 kfree(vmx->guest_msrs);
6441 kvm_vcpu_uninit(vcpu);
a4770347 6442 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6443}
6444
fb3f0f51 6445static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6446{
fb3f0f51 6447 int err;
c16f862d 6448 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6449 int cpu;
6aa8b732 6450
a2fa3e9f 6451 if (!vmx)
fb3f0f51
RR		 6452 return ERR_PTR(-ENOMEM);
6453
2384d2b3
SY		 6454 allocate_vpid(vmx);
6455
fb3f0f51
RR		 6456 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6457 if (err)
6458 goto free_vcpu;
965b58a5 6459
a2fa3e9f 6460 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6461 err = -ENOMEM;
fb3f0f51 6462 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6463 goto uninit_vcpu;
6464 }
965b58a5 6465
d462b819
NHE		 6466 vmx->loaded_vmcs = &vmx->vmcs01;
6467 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6468 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6469 goto free_msrs;
d462b819
NHE		 6470 if (!vmm_exclusive)
6471 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6472 loaded_vmcs_init(vmx->loaded_vmcs);
6473 if (!vmm_exclusive)
6474 kvm_cpu_vmxoff();
a2fa3e9f 6475
15ad7146
AK		 6476 cpu = get_cpu();
6477 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6478 vmx->vcpu.cpu = cpu;
8b9cf98c 6479 err = vmx_vcpu_setup(vmx);
fb3f0f51 6480 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6481 put_cpu();
fb3f0f51
RR		 6482 if (err)
6483 goto free_vmcs;
5e4a0b3c 6484 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6485 err = alloc_apic_access_page(kvm);
6486 if (err)
5e4a0b3c 6487 goto free_vmcs;
fb3f0f51 6488
b927a3ce
SY		 6489 if (enable_ept) {
6490 if (!kvm->arch.ept_identity_map_addr)
6491 kvm->arch.ept_identity_map_addr =
6492 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6493 err = -ENOMEM;
b7ebfb05
SY		 6494 if (alloc_identity_pagetable(kvm) != 0)
6495 goto free_vmcs;
93ea5388
GN		 6496 if (!init_rmode_identity_map(kvm))
6497 goto free_vmcs;
b927a3ce 6498 }
b7ebfb05 6499
a9d30f33
NHE		 6500 vmx->nested.current_vmptr = -1ull;
6501 vmx->nested.current_vmcs12 = NULL;
6502
fb3f0f51
RR		 6503 return &vmx->vcpu;
6504
6505free_vmcs:
5f3fbc34 6506 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6507free_msrs:
fb3f0f51
RR		 6508 kfree(vmx->guest_msrs);
6509uninit_vcpu:
6510 kvm_vcpu_uninit(&vmx->vcpu);
6511free_vcpu:
cdbecfc3 6512 free_vpid(vmx);
a4770347 6513 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6514 return ERR_PTR(err);
6aa8b732
AK		 6515}
6516
002c7f7c
YS		 6517static void __init vmx_check_processor_compat(void *rtn)
6518{
6519 struct vmcs_config vmcs_conf;
6520
6521 *(int *)rtn = 0;
6522 if (setup_vmcs_config(&vmcs_conf) < 0)
6523 *(int *)rtn = -EIO;
6524 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6525 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6526 smp_processor_id());
6527 *(int *)rtn = -EIO;
6528 }
6529}
6530
67253af5
SY		 6531static int get_ept_level(void)
6532{
6533 return VMX_EPT_DEFAULT_GAW + 1;
6534}
6535
4b12f0de 6536static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6537{
4b12f0de
SY		 6538 u64 ret;
6539
522c68c4
SY		 6540 /* For VT-d and EPT combination
6541 * 1. MMIO: always map as UC
6542 * 2. EPT with VT-d:
6543 * a. VT-d without snooping control feature: can't guarantee the
6544 * result, try to trust guest.
6545 * b. VT-d with snooping control feature: snooping control feature of
6546 * VT-d engine can guarantee the cache correctness. Just set it
6547 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6548 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6549 * consistent with host MTRR
6550 */
4b12f0de
SY		 6551 if (is_mmio)
6552 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6553 else if (vcpu->kvm->arch.iommu_domain &&
6554 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6555 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6556 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6557 else
522c68c4 6558 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6559 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6560
6561 return ret;
64d4d521
SY		 6562}
6563
17cc3935 6564static int vmx_get_lpage_level(void)
344f414f 6565{
878403b7
SY		 6566 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6567 return PT_DIRECTORY_LEVEL;
6568 else
6569 /* For shadow and EPT supported 1GB page */
6570 return PT_PDPE_LEVEL;
344f414f
JR		 6571}
6572
0e851880
SY		 6573static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6574{
4e47c7a6
SY		 6575 struct kvm_cpuid_entry2 *best;
6576 struct vcpu_vmx *vmx = to_vmx(vcpu);
6577 u32 exec_control;
6578
6579 vmx->rdtscp_enabled = false;
6580 if (vmx_rdtscp_supported()) {
6581 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6582 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6583 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6584 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6585 vmx->rdtscp_enabled = true;
6586 else {
6587 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6588 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6589 exec_control);
6590 }
6591 }
6592 }
ad756a16 6593
ad756a16
MJ		 6594 /* Exposing INVPCID only when PCID is exposed */
6595 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6596 if (vmx_invpcid_supported() &&
4f977045 6597 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6598 guest_cpuid_has_pcid(vcpu)) {
29282fde 6599 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 6600 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6601 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6602 exec_control);
6603 } else {
29282fde
TI		 6604 if (cpu_has_secondary_exec_ctrls()) {
6605 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6606 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6607 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6608 exec_control);
6609 }
ad756a16 6610 if (best)
4f977045 6611 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6612 }
0e851880
SY		 6613}
6614
d4330ef2
JR		 6615static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6616{
7b8050f5
NHE		 6617 if (func == 1 && nested)
6618 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6619}
6620
fe3ef05c
NHE		 6621/*
6622 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6623 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6624 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6625 * guest in a way that will both be appropriate to L1's requests, and our
6626 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6627 * function also has additional necessary side-effects, like setting various
6628 * vcpu->arch fields.
6629 */
6630static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6631{
6632 struct vcpu_vmx *vmx = to_vmx(vcpu);
6633 u32 exec_control;
6634
6635 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6636 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6637 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6638 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6639 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6640 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6641 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6642 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6643 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6644 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6645 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6646 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6647 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6648 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6649 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6650 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6651 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6652 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6653 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6654 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6655 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6656 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6657 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6658 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6659 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6660 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6661 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6662 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6663 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6664 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6665 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6666 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6667 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6668 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6669 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6670 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6671
6672 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6673 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6674 vmcs12->vm_entry_intr_info_field);
6675 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6676 vmcs12->vm_entry_exception_error_code);
6677 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6678 vmcs12->vm_entry_instruction_len);
6679 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6680 vmcs12->guest_interruptibility_info);
6681 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6682 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6683 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6684 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6685 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6686 vmcs12->guest_pending_dbg_exceptions);
6687 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6688 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6689
6690 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6691
6692 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6693 (vmcs_config.pin_based_exec_ctrl |
6694 vmcs12->pin_based_vm_exec_control));
6695
6696 /*
6697 * Whether page-faults are trapped is determined by a combination of
6698 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6699 * If enable_ept, L0 doesn't care about page faults and we should
6700 * set all of these to L1's desires. However, if !enable_ept, L0 does
6701 * care about (at least some) page faults, and because it is not easy
6702 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6703 * to exit on each and every L2 page fault. This is done by setting
6704 * MASK=MATCH=0 and (see below) EB.PF=1.
6705 * Note that below we don't need special code to set EB.PF beyond the
6706 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6707 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6708 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6709 *
6710 * A problem with this approach (when !enable_ept) is that L1 may be
6711 * injected with more page faults than it asked for. This could have
6712 * caused problems, but in practice existing hypervisors don't care.
6713 * To fix this, we will need to emulate the PFEC checking (on the L1
6714 * page tables), using walk_addr(), when injecting PFs to L1.
6715 */
6716 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6717 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6718 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6719 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6720
6721 if (cpu_has_secondary_exec_ctrls()) {
6722 u32 exec_control = vmx_secondary_exec_control(vmx);
6723 if (!vmx->rdtscp_enabled)
6724 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6725 /* Take the following fields only from vmcs12 */
6726 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6727 if (nested_cpu_has(vmcs12,
6728 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6729 exec_control |= vmcs12->secondary_vm_exec_control;
6730
6731 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6732 /*
6733 * Translate L1 physical address to host physical
6734 * address for vmcs02. Keep the page pinned, so this
6735 * physical address remains valid. We keep a reference
6736 * to it so we can release it later.
6737 */
6738 if (vmx->nested.apic_access_page) /* shouldn't happen */
6739 nested_release_page(vmx->nested.apic_access_page);
6740 vmx->nested.apic_access_page =
6741 nested_get_page(vcpu, vmcs12->apic_access_addr);
6742 /*
6743 * If translation failed, no matter: This feature asks
6744 * to exit when accessing the given address, and if it
6745 * can never be accessed, this feature won't do
6746 * anything anyway.
6747 */
6748 if (!vmx->nested.apic_access_page)
6749 exec_control &=
6750 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6751 else
6752 vmcs_write64(APIC_ACCESS_ADDR,
6753 page_to_phys(vmx->nested.apic_access_page));
6754 }
6755
6756 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6757 }
6758
6759
6760 /*
6761 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6762 * Some constant fields are set here by vmx_set_constant_host_state().
6763 * Other fields are different per CPU, and will be set later when
6764 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6765 */
6766 vmx_set_constant_host_state();
6767
6768 /*
6769 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6770 * entry, but only if the current (host) sp changed from the value
6771 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6772 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6773 * here we just force the write to happen on entry.
6774 */
6775 vmx->host_rsp = 0;
6776
6777 exec_control = vmx_exec_control(vmx); /* L0's desires */
6778 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6779 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6780 exec_control &= ~CPU_BASED_TPR_SHADOW;
6781 exec_control |= vmcs12->cpu_based_vm_exec_control;
6782 /*
6783 * Merging of IO and MSR bitmaps not currently supported.
6784 * Rather, exit every time.
6785 */
6786 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6787 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6788 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6789
6790 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6791
6792 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6793 * bitwise-or of what L1 wants to trap for L2, and what we want to
6794 * trap. Note that CR0.TS also needs updating - we do this later.
6795 */
6796 update_exception_bitmap(vcpu);
6797 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6798 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6799
6800 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6801 vmcs_write32(VM_EXIT_CONTROLS,
6802 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6803 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6804 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6805
6806 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6807 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6808 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6809 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6810
6811
6812 set_cr4_guest_host_mask(vmx);
6813
27fc51b2
NHE		 6814 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6815 vmcs_write64(TSC_OFFSET,
6816 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6817 else
6818 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6819
6820 if (enable_vpid) {
6821 /*
6822 * Trivially support vpid by letting L2s share their parent
6823 * L1's vpid. TODO: move to a more elaborate solution, giving
6824 * each L2 its own vpid and exposing the vpid feature to L1.
6825 */
6826 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6827 vmx_flush_tlb(vcpu);
6828 }
6829
6830 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6831 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6832 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6833 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6834 else
6835 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6836 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6837 vmx_set_efer(vcpu, vcpu->arch.efer);
6838
6839 /*
6840 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6841 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6842 * The CR0_READ_SHADOW is what L2 should have expected to read given
6843 * the specifications by L1; It's not enough to take
6844 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6845 * have more bits than L1 expected.
6846 */
6847 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6848 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6849
6850 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6851 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6852
6853 /* shadow page tables on either EPT or shadow page tables */
6854 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6855 kvm_mmu_reset_context(vcpu);
6856
6857 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6858 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6859}
6860
cd232ad0
NHE		 6861/*
6862 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6863 * for running an L2 nested guest.
6864 */
6865static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6866{
6867 struct vmcs12 *vmcs12;
6868 struct vcpu_vmx *vmx = to_vmx(vcpu);
6869 int cpu;
6870 struct loaded_vmcs *vmcs02;
6871
6872 if (!nested_vmx_check_permission(vcpu) ||
6873 !nested_vmx_check_vmcs12(vcpu))
6874 return 1;
6875
6876 skip_emulated_instruction(vcpu);
6877 vmcs12 = get_vmcs12(vcpu);
6878
7c177938
NHE		 6879 /*
6880 * The nested entry process starts with enforcing various prerequisites
6881 * on vmcs12 as required by the Intel SDM, and act appropriately when
6882 * they fail: As the SDM explains, some conditions should cause the
6883 * instruction to fail, while others will cause the instruction to seem
6884 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6885 * To speed up the normal (success) code path, we should avoid checking
6886 * for misconfigurations which will anyway be caught by the processor
6887 * when using the merged vmcs02.
6888 */
6889 if (vmcs12->launch_state == launch) {
6890 nested_vmx_failValid(vcpu,
6891 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6892 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6893 return 1;
6894 }
6895
6896 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6897 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6898 /*TODO: Also verify bits beyond physical address width are 0*/
6899 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6900 return 1;
6901 }
6902
6903 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6904 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6905 /*TODO: Also verify bits beyond physical address width are 0*/
6906 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6907 return 1;
6908 }
6909
6910 if (vmcs12->vm_entry_msr_load_count > 0 ||
6911 vmcs12->vm_exit_msr_load_count > 0 ||
6912 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6913 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6914 __func__);
7c177938
NHE		 6915 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6916 return 1;
6917 }
6918
6919 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6920 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6921 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6922 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6923 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6924 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6925 !vmx_control_verify(vmcs12->vm_exit_controls,
6926 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6927 !vmx_control_verify(vmcs12->vm_entry_controls,
6928 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6929 {
6930 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6931 return 1;
6932 }
6933
6934 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6935 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6936 nested_vmx_failValid(vcpu,
6937 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6938 return 1;
6939 }
6940
6941 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6942 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6943 nested_vmx_entry_failure(vcpu, vmcs12,
6944 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6945 return 1;
6946 }
6947 if (vmcs12->vmcs_link_pointer != -1ull) {
6948 nested_vmx_entry_failure(vcpu, vmcs12,
6949 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6950 return 1;
6951 }
6952
6953 /*
6954 * We're finally done with prerequisite checking, and can start with
6955 * the nested entry.
6956 */
6957
cd232ad0
NHE		 6958 vmcs02 = nested_get_current_vmcs02(vmx);
6959 if (!vmcs02)
6960 return -ENOMEM;
6961
6962 enter_guest_mode(vcpu);
6963
6964 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6965
6966 cpu = get_cpu();
6967 vmx->loaded_vmcs = vmcs02;
6968 vmx_vcpu_put(vcpu);
6969 vmx_vcpu_load(vcpu, cpu);
6970 vcpu->cpu = cpu;
6971 put_cpu();
6972
6973 vmcs12->launch_state = 1;
6974
6975 prepare_vmcs02(vcpu, vmcs12);
6976
6977 /*
6978 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6979 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6980 * returned as far as L1 is concerned. It will only return (and set
6981 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6982 */
6983 return 1;
6984}
6985
4704d0be
NHE		 6986/*
6987 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6988 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6989 * This function returns the new value we should put in vmcs12.guest_cr0.
6990 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6991 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6992 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6993 * didn't trap the bit, because if L1 did, so would L0).
6994 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6995 * been modified by L2, and L1 knows it. So just leave the old value of
6996 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6997 * isn't relevant, because if L0 traps this bit it can set it to anything.
6998 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6999 * changed these bits, and therefore they need to be updated, but L0
7000 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7001 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7002 */
7003static inline unsigned long
7004vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7005{
7006 return
7007 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7008 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7009 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7010 vcpu->arch.cr0_guest_owned_bits));
7011}
7012
7013static inline unsigned long
7014vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7015{
7016 return
7017 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7018 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7019 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7020 vcpu->arch.cr4_guest_owned_bits));
7021}
7022
7023/*
7024 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7025 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7026 * and this function updates it to reflect the changes to the guest state while
7027 * L2 was running (and perhaps made some exits which were handled directly by L0
7028 * without going back to L1), and to reflect the exit reason.
7029 * Note that we do not have to copy here all VMCS fields, just those that
7030 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7031 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7032 * which already writes to vmcs12 directly.
7033 */
7034void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7035{
7036 /* update guest state fields: */
7037 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7038 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7039
7040 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7041 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7042 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7043 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7044
7045 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7046 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7047 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7048 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7049 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7050 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7051 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7052 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7053 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7054 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7055 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7056 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7057 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7058 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7059 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7060 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7061 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7062 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7063 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7064 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7065 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7066 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7067 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7068 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7069 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7070 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7071 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7072 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7073 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7074 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7075 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7076 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7077 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7078 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7079 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7080 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7081
7082 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7083 vmcs12->guest_interruptibility_info =
7084 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7085 vmcs12->guest_pending_dbg_exceptions =
7086 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7087
7088 /* TODO: These cannot have changed unless we have MSR bitmaps and
7089 * the relevant bit asks not to trap the change */
7090 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7091 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7092 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7093 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7094 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7095 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7096
7097 /* update exit information fields: */
7098
7099 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7100 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7101
7102 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7103 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7104 vmcs12->idt_vectoring_info_field =
7105 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7106 vmcs12->idt_vectoring_error_code =
7107 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7108 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7109 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7110
7111 /* clear vm-entry fields which are to be cleared on exit */
7112 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7113 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7114}
7115
7116/*
7117 * A part of what we need to when the nested L2 guest exits and we want to
7118 * run its L1 parent, is to reset L1's guest state to the host state specified
7119 * in vmcs12.
7120 * This function is to be called not only on normal nested exit, but also on
7121 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7122 * Failures During or After Loading Guest State").
7123 * This function should be called when the active VMCS is L1's (vmcs01).
7124 */
7125void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7126{
7127 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7128 vcpu->arch.efer = vmcs12->host_ia32_efer;
7129 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7130 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7131 else
7132 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7133 vmx_set_efer(vcpu, vcpu->arch.efer);
7134
7135 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7136 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7137 /*
7138 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7139 * actually changed, because it depends on the current state of
7140 * fpu_active (which may have changed).
7141 * Note that vmx_set_cr0 refers to efer set above.
7142 */
7143 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7144 /*
7145 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7146 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7147 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7148 */
7149 update_exception_bitmap(vcpu);
7150 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7151 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7152
7153 /*
7154 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7155 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7156 */
7157 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7158 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7159
7160 /* shadow page tables on either EPT or shadow page tables */
7161 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7162 kvm_mmu_reset_context(vcpu);
7163
7164 if (enable_vpid) {
7165 /*
7166 * Trivially support vpid by letting L2s share their parent
7167 * L1's vpid. TODO: move to a more elaborate solution, giving
7168 * each L2 its own vpid and exposing the vpid feature to L1.
7169 */
7170 vmx_flush_tlb(vcpu);
7171 }
7172
7173
7174 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7175 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7176 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7177 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7178 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7179 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7180 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7181 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7182 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7183 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7184 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7185 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7186 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7187 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7188 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7189
7190 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7191 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7192 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7193 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7194 vmcs12->host_ia32_perf_global_ctrl);
7195}
7196
7197/*
7198 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7199 * and modify vmcs12 to make it see what it would expect to see there if
7200 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7201 */
7202static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7203{
7204 struct vcpu_vmx *vmx = to_vmx(vcpu);
7205 int cpu;
7206 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7207
7208 leave_guest_mode(vcpu);
7209 prepare_vmcs12(vcpu, vmcs12);
7210
7211 cpu = get_cpu();
7212 vmx->loaded_vmcs = &vmx->vmcs01;
7213 vmx_vcpu_put(vcpu);
7214 vmx_vcpu_load(vcpu, cpu);
7215 vcpu->cpu = cpu;
7216 put_cpu();
7217
7218 /* if no vmcs02 cache requested, remove the one we used */
7219 if (VMCS02_POOL_SIZE == 0)
7220 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7221
7222 load_vmcs12_host_state(vcpu, vmcs12);
7223
27fc51b2 7224 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7225 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7226
7227 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7228 vmx->host_rsp = 0;
7229
7230 /* Unpin physical memory we referred to in vmcs02 */
7231 if (vmx->nested.apic_access_page) {
7232 nested_release_page(vmx->nested.apic_access_page);
7233 vmx->nested.apic_access_page = 0;
7234 }
7235
7236 /*
7237 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7238 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7239 * success or failure flag accordingly.
7240 */
7241 if (unlikely(vmx->fail)) {
7242 vmx->fail = 0;
7243 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7244 } else
7245 nested_vmx_succeed(vcpu);
7246}
7247
7c177938
NHE		 7248/*
7249 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7250 * 23.7 "VM-entry failures during or after loading guest state" (this also
7251 * lists the acceptable exit-reason and exit-qualification parameters).
7252 * It should only be called before L2 actually succeeded to run, and when
7253 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7254 */
7255static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7256 struct vmcs12 *vmcs12,
7257 u32 reason, unsigned long qualification)
7258{
7259 load_vmcs12_host_state(vcpu, vmcs12);
7260 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7261 vmcs12->exit_qualification = qualification;
7262 nested_vmx_succeed(vcpu);
7263}
7264
8a76d7f2
JR		 7265static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7266 struct x86_instruction_info *info,
7267 enum x86_intercept_stage stage)
7268{
7269 return X86EMUL_CONTINUE;
7270}
7271
cbdd1bea 7272static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7273 .cpu_has_kvm_support = cpu_has_kvm_support,
7274 .disabled_by_bios = vmx_disabled_by_bios,
7275 .hardware_setup = hardware_setup,
7276 .hardware_unsetup = hardware_unsetup,
002c7f7c 7277 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7278 .hardware_enable = hardware_enable,
7279 .hardware_disable = hardware_disable,
04547156 7280 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7281
7282 .vcpu_create = vmx_create_vcpu,
7283 .vcpu_free = vmx_free_vcpu,
04d2cc77 7284 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7285
04d2cc77 7286 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7287 .vcpu_load = vmx_vcpu_load,
7288 .vcpu_put = vmx_vcpu_put,
7289
c8639010 7290 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7291 .get_msr = vmx_get_msr,
7292 .set_msr = vmx_set_msr,
7293 .get_segment_base = vmx_get_segment_base,
7294 .get_segment = vmx_get_segment,
7295 .set_segment = vmx_set_segment,
2e4d2653 7296 .get_cpl = vmx_get_cpl,
6aa8b732 7297 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7298 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7299 .decache_cr3 = vmx_decache_cr3,
25c4c276 7300 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7301 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7302 .set_cr3 = vmx_set_cr3,
7303 .set_cr4 = vmx_set_cr4,
6aa8b732 7304 .set_efer = vmx_set_efer,
6aa8b732
AK		 7305 .get_idt = vmx_get_idt,
7306 .set_idt = vmx_set_idt,
7307 .get_gdt = vmx_get_gdt,
7308 .set_gdt = vmx_set_gdt,
020df079 7309 .set_dr7 = vmx_set_dr7,
5fdbf976 7310 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7311 .get_rflags = vmx_get_rflags,
7312 .set_rflags = vmx_set_rflags,
ebcbab4c 7313 .fpu_activate = vmx_fpu_activate,
02daab21 7314 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7315
7316 .tlb_flush = vmx_flush_tlb,
6aa8b732 7317
6aa8b732 7318 .run = vmx_vcpu_run,
6062d012 7319 .handle_exit = vmx_handle_exit,
6aa8b732 7320 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7321 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7322 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7323 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7324 .set_irq = vmx_inject_irq,
95ba8273 7325 .set_nmi = vmx_inject_nmi,
298101da 7326 .queue_exception = vmx_queue_exception,
b463a6f7 7327 .cancel_injection = vmx_cancel_injection,
78646121 7328 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7329 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7330 .get_nmi_mask = vmx_get_nmi_mask,
7331 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7332 .enable_nmi_window = enable_nmi_window,
7333 .enable_irq_window = enable_irq_window,
7334 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7335
cbc94022 7336 .set_tss_addr = vmx_set_tss_addr,
67253af5 7337 .get_tdp_level = get_ept_level,
4b12f0de 7338 .get_mt_mask = vmx_get_mt_mask,
229456fc 7339
586f9607 7340 .get_exit_info = vmx_get_exit_info,
586f9607 7341
17cc3935 7342 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7343
7344 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7345
7346 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7347 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7348
7349 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7350
7351 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7352
4051b188 7353 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7354 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7355 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7356 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7357 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7358 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7359
7360 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7361
7362 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7363};
7364
7365static int __init vmx_init(void)
7366{
26bb0981
AK		 7367 int r, i;
7368
7369 rdmsrl_safe(MSR_EFER, &host_efer);
7370
7371 for (i = 0; i < NR_VMX_MSR; ++i)
7372 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7373
3e7c73e9 7374 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7375 if (!vmx_io_bitmap_a)
7376 return -ENOMEM;
7377
2106a548
GC		 7378 r = -ENOMEM;
7379
3e7c73e9 7380 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7381 if (!vmx_io_bitmap_b)
fdef3ad1 7382 goto out;
fdef3ad1 7383
5897297b 7384 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7385 if (!vmx_msr_bitmap_legacy)
25c5f225 7386 goto out1;
2106a548 7387
25c5f225 7388
5897297b 7389 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7390 if (!vmx_msr_bitmap_longmode)
5897297b 7391 goto out2;
2106a548 7392
5897297b 7393
fdef3ad1
HQ		 7394 /*
7395 * Allow direct access to the PC debug port (it is often used for I/O
7396 * delays, but the vmexits simply slow things down).
7397 */
3e7c73e9
AK		 7398 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7399 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7400
3e7c73e9 7401 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7402
5897297b
AK		 7403 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7404 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7405
2384d2b3
SY		 7406 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7407
0ee75bea
AK		 7408 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7409 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7410 if (r)
5897297b 7411 goto out3;
25c5f225 7412
8f536b76
ZY		 7413#ifdef CONFIG_KEXEC
7414 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7415 crash_vmclear_local_loaded_vmcss);
7416#endif
7417
5897297b
AK		 7418 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7419 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7420 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7421 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7422 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7423 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7424
089d034e 7425 if (enable_ept) {
3f6d8c8a
XH		 7426 kvm_mmu_set_mask_ptes(0ull,
7427 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7428 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7429 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7430 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7431 kvm_enable_tdp();
7432 } else
7433 kvm_disable_tdp();
1439442c 7434
fdef3ad1
HQ		 7435 return 0;
7436
5897297b
AK		 7437out3:
7438 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7439out2:
5897297b 7440 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7441out1:
3e7c73e9 7442 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7443out:
3e7c73e9 7444 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7445 return r;
6aa8b732
AK		 7446}
7447
7448static void __exit vmx_exit(void)
7449{
5897297b
AK		 7450 free_page((unsigned long)vmx_msr_bitmap_legacy);
7451 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7452 free_page((unsigned long)vmx_io_bitmap_b);
7453 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7454
8f536b76
ZY		 7455#ifdef CONFIG_KEXEC
7456 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7457 synchronize_rcu();
7458#endif
7459
cb498ea2 7460 kvm_exit();
6aa8b732
AK		 7461}
7462
7463module_init(vmx_init)
7464module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)