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KVM: x86 emulator: Use opcode::execute for CLI/STI(FA/FB)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 46#define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 48
6aa8b732
AK		 49MODULE_AUTHOR("Qumranet");
50MODULE_LICENSE("GPL");
51
4462d21a 52static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 53module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 54
4462d21a 55static int __read_mostly enable_vpid = 1;
736caefe 56module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 57
4462d21a 58static int __read_mostly flexpriority_enabled = 1;
736caefe 59module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 60
4462d21a 61static int __read_mostly enable_ept = 1;
736caefe 62module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 63
3a624e29
NK		 64static int __read_mostly enable_unrestricted_guest = 1;
65module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
67
4462d21a 68static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 69module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 70
b923e62e
DX		 71static int __read_mostly vmm_exclusive = 1;
72module_param(vmm_exclusive, bool, S_IRUGO);
73
443381a8
AL		 74static int __read_mostly yield_on_hlt = 1;
75module_param(yield_on_hlt, bool, S_IRUGO);
76
801d3424
NHE		 77/*
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
81 */
82static int __read_mostly nested = 0;
83module_param(nested, bool, S_IRUGO);
84
cdc0e244
AK		 85#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87#define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 90 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 91#define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 93#define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
95 | X86_CR4_OSXMMEXCPT)
96
cdc0e244
AK		 97#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
78ac8b47
AK		 100#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
4b8d54f9
ZE		 102/*
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 106 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
112 */
00c25bce 113#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 114#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116module_param(ple_gap, int, S_IRUGO);
117
118static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119module_param(ple_window, int, S_IRUGO);
120
61d2ef2c 121#define NR_AUTOLOAD_MSRS 1
ff2f6fe9 122#define VMCS02_POOL_SIZE 1
61d2ef2c 123
a2fa3e9f
GH		 124struct vmcs {
125 u32 revision_id;
126 u32 abort;
127 char data[0];
128};
129
d462b819
NHE		 130/*
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
134 */
135struct loaded_vmcs {
136 struct vmcs *vmcs;
137 int cpu;
138 int launched;
139 struct list_head loaded_vmcss_on_cpu_link;
140};
141
26bb0981
AK		 142struct shared_msr_entry {
143 unsigned index;
144 u64 data;
d5696725 145 u64 mask;
26bb0981
AK		 146};
147
a9d30f33
NHE		 148/*
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
160 */
22bd0358 161typedef u64 natural_width;
a9d30f33
NHE		 162struct __packed vmcs12 {
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
165 */
166 u32 revision_id;
167 u32 abort;
22bd0358 168
27d6c865
NHE		 169 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding[7]; /* room for future expansion */
171
22bd0358
NHE		 172 u64 io_bitmap_a;
173 u64 io_bitmap_b;
174 u64 msr_bitmap;
175 u64 vm_exit_msr_store_addr;
176 u64 vm_exit_msr_load_addr;
177 u64 vm_entry_msr_load_addr;
178 u64 tsc_offset;
179 u64 virtual_apic_page_addr;
180 u64 apic_access_addr;
181 u64 ept_pointer;
182 u64 guest_physical_address;
183 u64 vmcs_link_pointer;
184 u64 guest_ia32_debugctl;
185 u64 guest_ia32_pat;
186 u64 guest_ia32_efer;
187 u64 guest_ia32_perf_global_ctrl;
188 u64 guest_pdptr0;
189 u64 guest_pdptr1;
190 u64 guest_pdptr2;
191 u64 guest_pdptr3;
192 u64 host_ia32_pat;
193 u64 host_ia32_efer;
194 u64 host_ia32_perf_global_ctrl;
195 u64 padding64[8]; /* room for future expansion */
196 /*
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
201 */
202 natural_width cr0_guest_host_mask;
203 natural_width cr4_guest_host_mask;
204 natural_width cr0_read_shadow;
205 natural_width cr4_read_shadow;
206 natural_width cr3_target_value0;
207 natural_width cr3_target_value1;
208 natural_width cr3_target_value2;
209 natural_width cr3_target_value3;
210 natural_width exit_qualification;
211 natural_width guest_linear_address;
212 natural_width guest_cr0;
213 natural_width guest_cr3;
214 natural_width guest_cr4;
215 natural_width guest_es_base;
216 natural_width guest_cs_base;
217 natural_width guest_ss_base;
218 natural_width guest_ds_base;
219 natural_width guest_fs_base;
220 natural_width guest_gs_base;
221 natural_width guest_ldtr_base;
222 natural_width guest_tr_base;
223 natural_width guest_gdtr_base;
224 natural_width guest_idtr_base;
225 natural_width guest_dr7;
226 natural_width guest_rsp;
227 natural_width guest_rip;
228 natural_width guest_rflags;
229 natural_width guest_pending_dbg_exceptions;
230 natural_width guest_sysenter_esp;
231 natural_width guest_sysenter_eip;
232 natural_width host_cr0;
233 natural_width host_cr3;
234 natural_width host_cr4;
235 natural_width host_fs_base;
236 natural_width host_gs_base;
237 natural_width host_tr_base;
238 natural_width host_gdtr_base;
239 natural_width host_idtr_base;
240 natural_width host_ia32_sysenter_esp;
241 natural_width host_ia32_sysenter_eip;
242 natural_width host_rsp;
243 natural_width host_rip;
244 natural_width paddingl[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control;
246 u32 cpu_based_vm_exec_control;
247 u32 exception_bitmap;
248 u32 page_fault_error_code_mask;
249 u32 page_fault_error_code_match;
250 u32 cr3_target_count;
251 u32 vm_exit_controls;
252 u32 vm_exit_msr_store_count;
253 u32 vm_exit_msr_load_count;
254 u32 vm_entry_controls;
255 u32 vm_entry_msr_load_count;
256 u32 vm_entry_intr_info_field;
257 u32 vm_entry_exception_error_code;
258 u32 vm_entry_instruction_len;
259 u32 tpr_threshold;
260 u32 secondary_vm_exec_control;
261 u32 vm_instruction_error;
262 u32 vm_exit_reason;
263 u32 vm_exit_intr_info;
264 u32 vm_exit_intr_error_code;
265 u32 idt_vectoring_info_field;
266 u32 idt_vectoring_error_code;
267 u32 vm_exit_instruction_len;
268 u32 vmx_instruction_info;
269 u32 guest_es_limit;
270 u32 guest_cs_limit;
271 u32 guest_ss_limit;
272 u32 guest_ds_limit;
273 u32 guest_fs_limit;
274 u32 guest_gs_limit;
275 u32 guest_ldtr_limit;
276 u32 guest_tr_limit;
277 u32 guest_gdtr_limit;
278 u32 guest_idtr_limit;
279 u32 guest_es_ar_bytes;
280 u32 guest_cs_ar_bytes;
281 u32 guest_ss_ar_bytes;
282 u32 guest_ds_ar_bytes;
283 u32 guest_fs_ar_bytes;
284 u32 guest_gs_ar_bytes;
285 u32 guest_ldtr_ar_bytes;
286 u32 guest_tr_ar_bytes;
287 u32 guest_interruptibility_info;
288 u32 guest_activity_state;
289 u32 guest_sysenter_cs;
290 u32 host_ia32_sysenter_cs;
291 u32 padding32[8]; /* room for future expansion */
292 u16 virtual_processor_id;
293 u16 guest_es_selector;
294 u16 guest_cs_selector;
295 u16 guest_ss_selector;
296 u16 guest_ds_selector;
297 u16 guest_fs_selector;
298 u16 guest_gs_selector;
299 u16 guest_ldtr_selector;
300 u16 guest_tr_selector;
301 u16 host_es_selector;
302 u16 host_cs_selector;
303 u16 host_ss_selector;
304 u16 host_ds_selector;
305 u16 host_fs_selector;
306 u16 host_gs_selector;
307 u16 host_tr_selector;
a9d30f33
NHE		 308};
309
310/*
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314 */
315#define VMCS12_REVISION 0x11e57ed0
316
317/*
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
321 */
322#define VMCS12_SIZE 0x1000
323
ff2f6fe9
NHE		 324/* Used to remember the last vmcs02 used for some recently used vmcs12s */
325struct vmcs02_list {
326 struct list_head list;
327 gpa_t vmptr;
328 struct loaded_vmcs vmcs02;
329};
330
ec378aee
NHE		 331/*
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
334 */
335struct nested_vmx {
336 /* Has the level1 guest done vmxon? */
337 bool vmxon;
a9d30f33
NHE		 338
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
340 gpa_t current_vmptr;
341 /* The host-usable pointer to the above */
342 struct page *current_vmcs12_page;
343 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 344
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool;
347 int vmcs02_num;
fe3ef05c 348 u64 vmcs01_tsc_offset;
644d711a
NHE		 349 /* L2 must run next, and mustn't decide to exit to L1. */
350 bool nested_run_pending;
fe3ef05c
NHE		 351 /*
352 * Guest pages referred to in vmcs02 with host-physical pointers, so
353 * we must keep them pinned while L2 runs.
354 */
355 struct page *apic_access_page;
ec378aee
NHE		 356};
357
a2fa3e9f 358struct vcpu_vmx {
fb3f0f51 359 struct kvm_vcpu vcpu;
313dbd49 360 unsigned long host_rsp;
29bd8a78 361 u8 fail;
69c73028 362 u8 cpl;
9d58b931 363 bool nmi_known_unmasked;
51aa01d1 364 u32 exit_intr_info;
1155f76a 365 u32 idt_vectoring_info;
6de12732 366 ulong rflags;
26bb0981 367 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 368 int nmsrs;
369 int save_nmsrs;
a2fa3e9f 370#ifdef CONFIG_X86_64
44ea2b17
AK		 371 u64 msr_host_kernel_gs_base;
372 u64 msr_guest_kernel_gs_base;
a2fa3e9f 373#endif
d462b819
NHE		 374 /*
375 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376 * non-nested (L1) guest, it always points to vmcs01. For a nested
377 * guest (L2), it points to a different VMCS.
378 */
379 struct loaded_vmcs vmcs01;
380 struct loaded_vmcs *loaded_vmcs;
381 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 382 struct msr_autoload {
383 unsigned nr;
384 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
385 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
386 } msr_autoload;
a2fa3e9f
GH		 387 struct {
388 int loaded;
389 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 390 int gs_ldt_reload_needed;
391 int fs_reload_needed;
d77c26fc 392 } host_state;
9c8cba37 393 struct {
7ffd92c5 394 int vm86_active;
78ac8b47 395 ulong save_rflags;
7ffd92c5
AK		 396 struct kvm_save_segment {
397 u16 selector;
398 unsigned long base;
399 u32 limit;
400 u32 ar;
401 } tr, es, ds, fs, gs;
9c8cba37 402 } rmode;
2fb92db1
AK		 403 struct {
404 u32 bitmask; /* 4 bits per segment (1 bit per field) */
405 struct kvm_save_segment seg[8];
406 } segment_cache;
2384d2b3 407 int vpid;
04fa4d32 408 bool emulation_required;
3b86cd99
JK		 409
410 /* Support for vnmi-less CPUs */
411 int soft_vnmi_blocked;
412 ktime_t entry_time;
413 s64 vnmi_blocked_time;
a0861c02 414 u32 exit_reason;
4e47c7a6
SY		 415
416 bool rdtscp_enabled;
ec378aee
NHE		 417
418 /* Support for a guest hypervisor (nested VMX) */
419 struct nested_vmx nested;
a2fa3e9f
GH		 420};
421
2fb92db1
AK		 422enum segment_cache_field {
423 SEG_FIELD_SEL = 0,
424 SEG_FIELD_BASE = 1,
425 SEG_FIELD_LIMIT = 2,
426 SEG_FIELD_AR = 3,
427
428 SEG_FIELD_NR = 4
429};
430
a2fa3e9f
GH		 431static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
432{
fb3f0f51 433 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 434}
435
22bd0358
NHE		 436#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
438#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
439 [number##_HIGH] = VMCS12_OFFSET(name)+4
440
441static unsigned short vmcs_field_to_offset_table[] = {
442 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
443 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
444 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
445 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
446 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
447 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
448 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
449 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
450 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
451 FIELD(HOST_ES_SELECTOR, host_es_selector),
452 FIELD(HOST_CS_SELECTOR, host_cs_selector),
453 FIELD(HOST_SS_SELECTOR, host_ss_selector),
454 FIELD(HOST_DS_SELECTOR, host_ds_selector),
455 FIELD(HOST_FS_SELECTOR, host_fs_selector),
456 FIELD(HOST_GS_SELECTOR, host_gs_selector),
457 FIELD(HOST_TR_SELECTOR, host_tr_selector),
458 FIELD64(IO_BITMAP_A, io_bitmap_a),
459 FIELD64(IO_BITMAP_B, io_bitmap_b),
460 FIELD64(MSR_BITMAP, msr_bitmap),
461 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
462 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
463 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
464 FIELD64(TSC_OFFSET, tsc_offset),
465 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
466 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
467 FIELD64(EPT_POINTER, ept_pointer),
468 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
469 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
470 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
471 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
472 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
473 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
474 FIELD64(GUEST_PDPTR0, guest_pdptr0),
475 FIELD64(GUEST_PDPTR1, guest_pdptr1),
476 FIELD64(GUEST_PDPTR2, guest_pdptr2),
477 FIELD64(GUEST_PDPTR3, guest_pdptr3),
478 FIELD64(HOST_IA32_PAT, host_ia32_pat),
479 FIELD64(HOST_IA32_EFER, host_ia32_efer),
480 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
481 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
482 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
483 FIELD(EXCEPTION_BITMAP, exception_bitmap),
484 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
485 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
486 FIELD(CR3_TARGET_COUNT, cr3_target_count),
487 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
488 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
489 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
490 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
491 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
492 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
493 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
494 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
495 FIELD(TPR_THRESHOLD, tpr_threshold),
496 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
497 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
498 FIELD(VM_EXIT_REASON, vm_exit_reason),
499 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
500 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
501 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
502 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
503 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
504 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
505 FIELD(GUEST_ES_LIMIT, guest_es_limit),
506 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
507 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
508 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
509 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
510 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
511 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
512 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
513 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
514 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
515 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
516 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
517 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
518 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
519 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
520 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
521 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
522 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
523 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
524 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
525 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
526 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
527 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
528 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
529 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
530 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
531 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
532 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
533 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
534 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
535 FIELD(EXIT_QUALIFICATION, exit_qualification),
536 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
537 FIELD(GUEST_CR0, guest_cr0),
538 FIELD(GUEST_CR3, guest_cr3),
539 FIELD(GUEST_CR4, guest_cr4),
540 FIELD(GUEST_ES_BASE, guest_es_base),
541 FIELD(GUEST_CS_BASE, guest_cs_base),
542 FIELD(GUEST_SS_BASE, guest_ss_base),
543 FIELD(GUEST_DS_BASE, guest_ds_base),
544 FIELD(GUEST_FS_BASE, guest_fs_base),
545 FIELD(GUEST_GS_BASE, guest_gs_base),
546 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
547 FIELD(GUEST_TR_BASE, guest_tr_base),
548 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
549 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
550 FIELD(GUEST_DR7, guest_dr7),
551 FIELD(GUEST_RSP, guest_rsp),
552 FIELD(GUEST_RIP, guest_rip),
553 FIELD(GUEST_RFLAGS, guest_rflags),
554 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
555 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
556 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
557 FIELD(HOST_CR0, host_cr0),
558 FIELD(HOST_CR3, host_cr3),
559 FIELD(HOST_CR4, host_cr4),
560 FIELD(HOST_FS_BASE, host_fs_base),
561 FIELD(HOST_GS_BASE, host_gs_base),
562 FIELD(HOST_TR_BASE, host_tr_base),
563 FIELD(HOST_GDTR_BASE, host_gdtr_base),
564 FIELD(HOST_IDTR_BASE, host_idtr_base),
565 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
566 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
567 FIELD(HOST_RSP, host_rsp),
568 FIELD(HOST_RIP, host_rip),
569};
570static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
571
572static inline short vmcs_field_to_offset(unsigned long field)
573{
574 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
575 return -1;
576 return vmcs_field_to_offset_table[field];
577}
578
a9d30f33
NHE		 579static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
580{
581 return to_vmx(vcpu)->nested.current_vmcs12;
582}
583
584static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
585{
586 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
587 if (is_error_page(page)) {
588 kvm_release_page_clean(page);
589 return NULL;
590 }
591 return page;
592}
593
594static void nested_release_page(struct page *page)
595{
596 kvm_release_page_dirty(page);
597}
598
599static void nested_release_page_clean(struct page *page)
600{
601 kvm_release_page_clean(page);
602}
603
4e1096d2 604static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 605static void kvm_cpu_vmxon(u64 addr);
606static void kvm_cpu_vmxoff(void);
aff48baa 607static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 608static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 609
6aa8b732
AK		 610static DEFINE_PER_CPU(struct vmcs *, vmxarea);
611static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 612/*
613 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
615 */
616static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 617static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 618
3e7c73e9
AK		 619static unsigned long *vmx_io_bitmap_a;
620static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 621static unsigned long *vmx_msr_bitmap_legacy;
622static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 623
110312c8
AK		 624static bool cpu_has_load_ia32_efer;
625
2384d2b3
SY		 626static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
627static DEFINE_SPINLOCK(vmx_vpid_lock);
628
1c3d14fe 629static struct vmcs_config {
6aa8b732
AK		 630 int size;
631 int order;
632 u32 revision_id;
1c3d14fe
YS		 633 u32 pin_based_exec_ctrl;
634 u32 cpu_based_exec_ctrl;
f78e0e2e 635 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 636 u32 vmexit_ctrl;
637 u32 vmentry_ctrl;
638} vmcs_config;
6aa8b732 639
efff9e53 640static struct vmx_capability {
d56f546d
SY		 641 u32 ept;
642 u32 vpid;
643} vmx_capability;
644
6aa8b732
AK		 645#define VMX_SEGMENT_FIELD(seg) \
646 [VCPU_SREG_##seg] = { \
647 .selector = GUEST_##seg##_SELECTOR, \
648 .base = GUEST_##seg##_BASE, \
649 .limit = GUEST_##seg##_LIMIT, \
650 .ar_bytes = GUEST_##seg##_AR_BYTES, \
651 }
652
653static struct kvm_vmx_segment_field {
654 unsigned selector;
655 unsigned base;
656 unsigned limit;
657 unsigned ar_bytes;
658} kvm_vmx_segment_fields[] = {
659 VMX_SEGMENT_FIELD(CS),
660 VMX_SEGMENT_FIELD(DS),
661 VMX_SEGMENT_FIELD(ES),
662 VMX_SEGMENT_FIELD(FS),
663 VMX_SEGMENT_FIELD(GS),
664 VMX_SEGMENT_FIELD(SS),
665 VMX_SEGMENT_FIELD(TR),
666 VMX_SEGMENT_FIELD(LDTR),
667};
668
26bb0981
AK		 669static u64 host_efer;
670
6de4f3ad
AK		 671static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
672
4d56c8a7 673/*
8c06585d 674 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 675 * away by decrementing the array size.
676 */
6aa8b732 677static const u32 vmx_msr_index[] = {
05b3e0c2 678#ifdef CONFIG_X86_64
44ea2b17 679 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 680#endif
8c06585d 681 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 682};
9d8f549d 683#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 684
31299944 685static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 686{
687 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
688 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 689 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 690}
691
31299944 692static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 693{
694 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
695 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 696 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 697}
698
31299944 699static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 700{
701 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
702 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 703 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 704}
705
31299944 706static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
709 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
710}
711
31299944 712static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 713{
714 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715 INTR_INFO_VALID_MASK)) ==
716 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
717}
718
31299944 719static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 720{
04547156 721 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 722}
723
31299944 724static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 725{
04547156 726 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 727}
728
31299944 729static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 730{
04547156 731 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 732}
733
31299944 734static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 735{
04547156
SY		 736 return vmcs_config.cpu_based_exec_ctrl &
737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 738}
739
774ead3a 740static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 741{
04547156
SY		 742 return vmcs_config.cpu_based_2nd_exec_ctrl &
743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
744}
745
746static inline bool cpu_has_vmx_flexpriority(void)
747{
748 return cpu_has_vmx_tpr_shadow() &&
749 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 750}
751
e799794e
MT		 752static inline bool cpu_has_vmx_ept_execute_only(void)
753{
31299944 754 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 755}
756
757static inline bool cpu_has_vmx_eptp_uncacheable(void)
758{
31299944 759 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 760}
761
762static inline bool cpu_has_vmx_eptp_writeback(void)
763{
31299944 764 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 765}
766
767static inline bool cpu_has_vmx_ept_2m_page(void)
768{
31299944 769 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 770}
771
878403b7
SY		 772static inline bool cpu_has_vmx_ept_1g_page(void)
773{
31299944 774 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 775}
776
4bc9b982
SY		 777static inline bool cpu_has_vmx_ept_4levels(void)
778{
779 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
780}
781
31299944 782static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 783{
31299944 784 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 785}
786
31299944 787static inline bool cpu_has_vmx_invept_context(void)
d56f546d 788{
31299944 789 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 790}
791
31299944 792static inline bool cpu_has_vmx_invept_global(void)
d56f546d 793{
31299944 794 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 795}
796
518c8aee
GJ		 797static inline bool cpu_has_vmx_invvpid_single(void)
798{
799 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
800}
801
b9d762fa
GJ		 802static inline bool cpu_has_vmx_invvpid_global(void)
803{
804 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
805}
806
31299944 807static inline bool cpu_has_vmx_ept(void)
d56f546d 808{
04547156
SY		 809 return vmcs_config.cpu_based_2nd_exec_ctrl &
810 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 811}
812
31299944 813static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 814{
815 return vmcs_config.cpu_based_2nd_exec_ctrl &
816 SECONDARY_EXEC_UNRESTRICTED_GUEST;
817}
818
31299944 819static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 820{
821 return vmcs_config.cpu_based_2nd_exec_ctrl &
822 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
823}
824
31299944 825static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 826{
6d3e435e 827 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 828}
829
31299944 830static inline bool cpu_has_vmx_vpid(void)
2384d2b3 831{
04547156
SY		 832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 834}
835
31299944 836static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 837{
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_RDTSCP;
840}
841
31299944 842static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 843{
844 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
845}
846
f5f48ee1
SY		 847static inline bool cpu_has_vmx_wbinvd_exit(void)
848{
849 return vmcs_config.cpu_based_2nd_exec_ctrl &
850 SECONDARY_EXEC_WBINVD_EXITING;
851}
852
04547156
SY		 853static inline bool report_flexpriority(void)
854{
855 return flexpriority_enabled;
856}
857
fe3ef05c
NHE		 858static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
859{
860 return vmcs12->cpu_based_vm_exec_control & bit;
861}
862
863static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
864{
865 return (vmcs12->cpu_based_vm_exec_control &
866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
867 (vmcs12->secondary_vm_exec_control & bit);
868}
869
644d711a
NHE		 870static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
871 struct kvm_vcpu *vcpu)
872{
873 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
874}
875
876static inline bool is_exception(u32 intr_info)
877{
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
880}
881
882static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 883static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
884 struct vmcs12 *vmcs12,
885 u32 reason, unsigned long qualification);
886
8b9cf98c 887static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 888{
889 int i;
890
a2fa3e9f 891 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 892 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 893 return i;
894 return -1;
895}
896
2384d2b3
SY		 897static inline void __invvpid(int ext, u16 vpid, gva_t gva)
898{
899 struct {
900 u64 vpid : 16;
901 u64 rsvd : 48;
902 u64 gva;
903 } operand = { vpid, 0, gva };
904
4ecac3fd 905 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 906 /* CF==1 or ZF==1 --> rc = -1 */
907 "; ja 1f ; ud2 ; 1:"
908 : : "a"(&operand), "c"(ext) : "cc", "memory");
909}
910
1439442c
SY		 911static inline void __invept(int ext, u64 eptp, gpa_t gpa)
912{
913 struct {
914 u64 eptp, gpa;
915 } operand = {eptp, gpa};
916
4ecac3fd 917 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 918 /* CF==1 or ZF==1 --> rc = -1 */
919 "; ja 1f ; ud2 ; 1:\n"
920 : : "a" (&operand), "c" (ext) : "cc", "memory");
921}
922
26bb0981 923static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 924{
925 int i;
926
8b9cf98c 927 i = __find_msr_index(vmx, msr);
a75beee6 928 if (i >= 0)
a2fa3e9f 929 return &vmx->guest_msrs[i];
8b6d44c7 930 return NULL;
7725f0ba
AK		 931}
932
6aa8b732
AK		 933static void vmcs_clear(struct vmcs *vmcs)
934{
935 u64 phys_addr = __pa(vmcs);
936 u8 error;
937
4ecac3fd 938 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 939 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 940 : "cc", "memory");
941 if (error)
942 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
943 vmcs, phys_addr);
944}
945
d462b819
NHE		 946static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
947{
948 vmcs_clear(loaded_vmcs->vmcs);
949 loaded_vmcs->cpu = -1;
950 loaded_vmcs->launched = 0;
951}
952
7725b894
DX		 953static void vmcs_load(struct vmcs *vmcs)
954{
955 u64 phys_addr = __pa(vmcs);
956 u8 error;
957
958 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 959 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 960 : "cc", "memory");
961 if (error)
2844d849 962 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 963 vmcs, phys_addr);
964}
965
d462b819 966static void __loaded_vmcs_clear(void *arg)
6aa8b732 967{
d462b819 968 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 969 int cpu = raw_smp_processor_id();
6aa8b732 970
d462b819
NHE		 971 if (loaded_vmcs->cpu != cpu)
972 return; /* vcpu migration can race with cpu offline */
973 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 974 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 975 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
976 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 977}
978
d462b819 979static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 980{
d462b819
NHE		 981 if (loaded_vmcs->cpu != -1)
982 smp_call_function_single(
983 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 984}
985
1760dd49 986static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 987{
988 if (vmx->vpid == 0)
989 return;
990
518c8aee
GJ		 991 if (cpu_has_vmx_invvpid_single())
992 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 993}
994
b9d762fa
GJ		 995static inline void vpid_sync_vcpu_global(void)
996{
997 if (cpu_has_vmx_invvpid_global())
998 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
999}
1000
1001static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002{
1003 if (cpu_has_vmx_invvpid_single())
1760dd49 1004 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1005 else
1006 vpid_sync_vcpu_global();
1007}
1008
1439442c
SY		 1009static inline void ept_sync_global(void)
1010{
1011 if (cpu_has_vmx_invept_global())
1012 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013}
1014
1015static inline void ept_sync_context(u64 eptp)
1016{
089d034e 1017 if (enable_ept) {
1439442c
SY		 1018 if (cpu_has_vmx_invept_context())
1019 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020 else
1021 ept_sync_global();
1022 }
1023}
1024
1025static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026{
089d034e 1027 if (enable_ept) {
1439442c
SY		 1028 if (cpu_has_vmx_invept_individual_addr())
1029 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030 eptp, gpa);
1031 else
1032 ept_sync_context(eptp);
1033 }
1034}
1035
96304217 1036static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1037{
5e520e62 1038 unsigned long value;
6aa8b732 1039
5e520e62
AK		 1040 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1042 return value;
1043}
1044
96304217 1045static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1046{
1047 return vmcs_readl(field);
1048}
1049
96304217 1050static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1051{
1052 return vmcs_readl(field);
1053}
1054
96304217 1055static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1056{
05b3e0c2 1057#ifdef CONFIG_X86_64
6aa8b732
AK		 1058 return vmcs_readl(field);
1059#else
1060 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061#endif
1062}
1063
e52de1b8
AK		 1064static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065{
1066 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068 dump_stack();
1069}
1070
6aa8b732
AK		 1071static void vmcs_writel(unsigned long field, unsigned long value)
1072{
1073 u8 error;
1074
4ecac3fd 1075 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1076 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1077 if (unlikely(error))
1078 vmwrite_error(field, value);
6aa8b732
AK		 1079}
1080
1081static void vmcs_write16(unsigned long field, u16 value)
1082{
1083 vmcs_writel(field, value);
1084}
1085
1086static void vmcs_write32(unsigned long field, u32 value)
1087{
1088 vmcs_writel(field, value);
1089}
1090
1091static void vmcs_write64(unsigned long field, u64 value)
1092{
6aa8b732 1093 vmcs_writel(field, value);
7682f2d0 1094#ifndef CONFIG_X86_64
6aa8b732
AK		 1095 asm volatile ("");
1096 vmcs_writel(field+1, value >> 32);
1097#endif
1098}
1099
2ab455cc
AL		 1100static void vmcs_clear_bits(unsigned long field, u32 mask)
1101{
1102 vmcs_writel(field, vmcs_readl(field) & ~mask);
1103}
1104
1105static void vmcs_set_bits(unsigned long field, u32 mask)
1106{
1107 vmcs_writel(field, vmcs_readl(field) | mask);
1108}
1109
2fb92db1
AK		 1110static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111{
1112 vmx->segment_cache.bitmask = 0;
1113}
1114
1115static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116 unsigned field)
1117{
1118 bool ret;
1119 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123 vmx->segment_cache.bitmask = 0;
1124 }
1125 ret = vmx->segment_cache.bitmask & mask;
1126 vmx->segment_cache.bitmask |= mask;
1127 return ret;
1128}
1129
1130static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131{
1132 u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136 return *p;
1137}
1138
1139static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140{
1141 ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145 return *p;
1146}
1147
1148static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149{
1150 u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154 return *p;
1155}
1156
1157static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158{
1159 u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163 return *p;
1164}
1165
abd3f2d6
AK		 1166static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167{
1168 u32 eb;
1169
fd7373cc
JK		 1170 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172 if ((vcpu->guest_debug &
1173 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175 eb |= 1u << BP_VECTOR;
7ffd92c5 1176 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1177 eb = ~0;
089d034e 1178 if (enable_ept)
1439442c 1179 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1180 if (vcpu->fpu_active)
1181 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1182
1183 /* When we are running a nested L2 guest and L1 specified for it a
1184 * certain exception bitmap, we must trap the same exceptions and pass
1185 * them to L1. When running L2, we will only handle the exceptions
1186 * specified above if L1 did not want them.
1187 */
1188 if (is_guest_mode(vcpu))
1189 eb |= get_vmcs12(vcpu)->exception_bitmap;
1190
abd3f2d6
AK		 1191 vmcs_write32(EXCEPTION_BITMAP, eb);
1192}
1193
61d2ef2c
AK		 1194static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1195{
1196 unsigned i;
1197 struct msr_autoload *m = &vmx->msr_autoload;
1198
110312c8
AK		 1199 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1200 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1201 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1202 return;
1203 }
1204
61d2ef2c
AK		 1205 for (i = 0; i < m->nr; ++i)
1206 if (m->guest[i].index == msr)
1207 break;
1208
1209 if (i == m->nr)
1210 return;
1211 --m->nr;
1212 m->guest[i] = m->guest[m->nr];
1213 m->host[i] = m->host[m->nr];
1214 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1215 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1216}
1217
1218static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1219 u64 guest_val, u64 host_val)
1220{
1221 unsigned i;
1222 struct msr_autoload *m = &vmx->msr_autoload;
1223
110312c8
AK		 1224 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1225 vmcs_write64(GUEST_IA32_EFER, guest_val);
1226 vmcs_write64(HOST_IA32_EFER, host_val);
1227 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1228 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1229 return;
1230 }
1231
61d2ef2c
AK		 1232 for (i = 0; i < m->nr; ++i)
1233 if (m->guest[i].index == msr)
1234 break;
1235
1236 if (i == m->nr) {
1237 ++m->nr;
1238 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1239 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1240 }
1241
1242 m->guest[i].index = msr;
1243 m->guest[i].value = guest_val;
1244 m->host[i].index = msr;
1245 m->host[i].value = host_val;
1246}
1247
33ed6329
AK		 1248static void reload_tss(void)
1249{
33ed6329
AK		 1250 /*
1251 * VT restores TR but not its size. Useless.
1252 */
d359192f 1253 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1254 struct desc_struct *descs;
33ed6329 1255
d359192f 1256 descs = (void *)gdt->address;
33ed6329
AK		 1257 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1258 load_TR_desc();
33ed6329
AK		 1259}
1260
92c0d900 1261static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1262{
3a34a881 1263 u64 guest_efer;
51c6cf66
AK		 1264 u64 ignore_bits;
1265
f6801dff 1266 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1267
51c6cf66
AK		 1268 /*
1269 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1270 * outside long mode
1271 */
1272 ignore_bits = EFER_NX | EFER_SCE;
1273#ifdef CONFIG_X86_64
1274 ignore_bits |= EFER_LMA | EFER_LME;
1275 /* SCE is meaningful only in long mode on Intel */
1276 if (guest_efer & EFER_LMA)
1277 ignore_bits &= ~(u64)EFER_SCE;
1278#endif
51c6cf66
AK		 1279 guest_efer &= ~ignore_bits;
1280 guest_efer |= host_efer & ignore_bits;
26bb0981 1281 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1282 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1283
1284 clear_atomic_switch_msr(vmx, MSR_EFER);
1285 /* On ept, can't emulate nx, and must switch nx atomically */
1286 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1287 guest_efer = vmx->vcpu.arch.efer;
1288 if (!(guest_efer & EFER_LMA))
1289 guest_efer &= ~EFER_LME;
1290 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1291 return false;
1292 }
1293
26bb0981 1294 return true;
51c6cf66
AK		 1295}
1296
2d49ec72
GN		 1297static unsigned long segment_base(u16 selector)
1298{
d359192f 1299 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1300 struct desc_struct *d;
1301 unsigned long table_base;
1302 unsigned long v;
1303
1304 if (!(selector & ~3))
1305 return 0;
1306
d359192f 1307 table_base = gdt->address;
2d49ec72
GN		 1308
1309 if (selector & 4) { /* from ldt */
1310 u16 ldt_selector = kvm_read_ldt();
1311
1312 if (!(ldt_selector & ~3))
1313 return 0;
1314
1315 table_base = segment_base(ldt_selector);
1316 }
1317 d = (struct desc_struct *)(table_base + (selector & ~7));
1318 v = get_desc_base(d);
1319#ifdef CONFIG_X86_64
1320 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1321 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1322#endif
1323 return v;
1324}
1325
1326static inline unsigned long kvm_read_tr_base(void)
1327{
1328 u16 tr;
1329 asm("str %0" : "=g"(tr));
1330 return segment_base(tr);
1331}
1332
04d2cc77 1333static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1334{
04d2cc77 1335 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1336 int i;
04d2cc77 1337
a2fa3e9f 1338 if (vmx->host_state.loaded)
33ed6329
AK		 1339 return;
1340
a2fa3e9f 1341 vmx->host_state.loaded = 1;
33ed6329
AK		 1342 /*
1343 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1344 * allow segment selectors with cpl > 0 or ti == 1.
1345 */
d6e88aec 1346 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1347 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1348 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1349 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1350 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1351 vmx->host_state.fs_reload_needed = 0;
1352 } else {
33ed6329 1353 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1354 vmx->host_state.fs_reload_needed = 1;
33ed6329 1355 }
9581d442 1356 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1357 if (!(vmx->host_state.gs_sel & 7))
1358 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1359 else {
1360 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1361 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1362 }
1363
1364#ifdef CONFIG_X86_64
1365 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1366 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1367#else
a2fa3e9f
GH		 1368 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1369 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1370#endif
707c0874
AK		 1371
1372#ifdef CONFIG_X86_64
c8770e7b
AK		 1373 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1374 if (is_long_mode(&vmx->vcpu))
44ea2b17 1375 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1376#endif
26bb0981
AK		 1377 for (i = 0; i < vmx->save_nmsrs; ++i)
1378 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1379 vmx->guest_msrs[i].data,
1380 vmx->guest_msrs[i].mask);
33ed6329
AK		 1381}
1382
a9b21b62 1383static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1384{
a2fa3e9f 1385 if (!vmx->host_state.loaded)
33ed6329
AK		 1386 return;
1387
e1beb1d3 1388 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1389 vmx->host_state.loaded = 0;
c8770e7b
AK		 1390#ifdef CONFIG_X86_64
1391 if (is_long_mode(&vmx->vcpu))
1392 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1393#endif
152d3f2f 1394 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1395 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1396#ifdef CONFIG_X86_64
9581d442 1397 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1398#else
1399 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1400#endif
33ed6329 1401 }
0a77fe4c
AK		 1402 if (vmx->host_state.fs_reload_needed)
1403 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1404 reload_tss();
44ea2b17 1405#ifdef CONFIG_X86_64
c8770e7b 1406 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1407#endif
1c11e713
AK		 1408 if (current_thread_info()->status & TS_USEDFPU)
1409 clts();
3444d7da 1410 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1411}
1412
a9b21b62
AK		 1413static void vmx_load_host_state(struct vcpu_vmx *vmx)
1414{
1415 preempt_disable();
1416 __vmx_load_host_state(vmx);
1417 preempt_enable();
1418}
1419
6aa8b732
AK		 1420/*
1421 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1422 * vcpu mutex is already taken.
1423 */
15ad7146 1424static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1425{
a2fa3e9f 1426 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1427 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1428
4610c9cc
DX		 1429 if (!vmm_exclusive)
1430 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1431 else if (vmx->loaded_vmcs->cpu != cpu)
1432 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1433
d462b819
NHE		 1434 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1435 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1436 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1437 }
1438
d462b819 1439 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1440 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1441 unsigned long sysenter_esp;
1442
a8eeb04a 1443 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1444 local_irq_disable();
d462b819
NHE		 1445 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1446 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1447 local_irq_enable();
1448
6aa8b732
AK		 1449 /*
1450 * Linux uses per-cpu TSS and GDT, so set these when switching
1451 * processors.
1452 */
d6e88aec 1453 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1454 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1455
1456 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1457 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1458 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1459 }
6aa8b732
AK		 1460}
1461
1462static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1463{
a9b21b62 1464 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1465 if (!vmm_exclusive) {
d462b819
NHE		 1466 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1467 vcpu->cpu = -1;
4610c9cc
DX		 1468 kvm_cpu_vmxoff();
1469 }
6aa8b732
AK		 1470}
1471
5fd86fcf
AK		 1472static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1473{
81231c69
AK		 1474 ulong cr0;
1475
5fd86fcf
AK		 1476 if (vcpu->fpu_active)
1477 return;
1478 vcpu->fpu_active = 1;
81231c69
AK		 1479 cr0 = vmcs_readl(GUEST_CR0);
1480 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1481 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1482 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1483 update_exception_bitmap(vcpu);
edcafe3c 1484 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1485 if (is_guest_mode(vcpu))
1486 vcpu->arch.cr0_guest_owned_bits &=
1487 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1488 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1489}
1490
edcafe3c
AK		 1491static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1492
fe3ef05c
NHE		 1493/*
1494 * Return the cr0 value that a nested guest would read. This is a combination
1495 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1496 * its hypervisor (cr0_read_shadow).
1497 */
1498static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1499{
1500 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1501 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1502}
1503static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1504{
1505 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1506 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1507}
1508
5fd86fcf
AK		 1509static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1510{
36cf24e0
NHE		 1511 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1512 * set this *before* calling this function.
1513 */
edcafe3c 1514 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1515 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1516 update_exception_bitmap(vcpu);
edcafe3c
AK		 1517 vcpu->arch.cr0_guest_owned_bits = 0;
1518 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1519 if (is_guest_mode(vcpu)) {
1520 /*
1521 * L1's specified read shadow might not contain the TS bit,
1522 * so now that we turned on shadowing of this bit, we need to
1523 * set this bit of the shadow. Like in nested_vmx_run we need
1524 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1525 * up-to-date here because we just decached cr0.TS (and we'll
1526 * only update vmcs12->guest_cr0 on nested exit).
1527 */
1528 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1529 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1530 (vcpu->arch.cr0 & X86_CR0_TS);
1531 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1532 } else
1533 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1534}
1535
6aa8b732
AK		 1536static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1537{
78ac8b47 1538 unsigned long rflags, save_rflags;
345dcaa8 1539
6de12732
AK		 1540 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1541 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1542 rflags = vmcs_readl(GUEST_RFLAGS);
1543 if (to_vmx(vcpu)->rmode.vm86_active) {
1544 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1545 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1546 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1547 }
1548 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1549 }
6de12732 1550 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1551}
1552
1553static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1554{
6de12732 1555 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1556 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1557 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1558 if (to_vmx(vcpu)->rmode.vm86_active) {
1559 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1560 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1561 }
6aa8b732
AK		 1562 vmcs_writel(GUEST_RFLAGS, rflags);
1563}
1564
2809f5d2
GC		 1565static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1566{
1567 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1568 int ret = 0;
1569
1570 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1571 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1572 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1573 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1574
1575 return ret & mask;
1576}
1577
1578static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1579{
1580 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1581 u32 interruptibility = interruptibility_old;
1582
1583 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1584
48005f64 1585 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1586 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1587 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1588 interruptibility |= GUEST_INTR_STATE_STI;
1589
1590 if ((interruptibility != interruptibility_old))
1591 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1592}
1593
6aa8b732
AK		 1594static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1595{
1596 unsigned long rip;
6aa8b732 1597
5fdbf976 1598 rip = kvm_rip_read(vcpu);
6aa8b732 1599 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1600 kvm_rip_write(vcpu, rip);
6aa8b732 1601
2809f5d2
GC		 1602 /* skipping an emulated instruction also counts */
1603 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1604}
1605
443381a8
AL		 1606static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1607{
1608 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1609 * explicitly skip the instruction because if the HLT state is set, then
1610 * the instruction is already executing and RIP has already been
1611 * advanced. */
1612 if (!yield_on_hlt &&
1613 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1614 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1615}
1616
0b6ac343
NHE		 1617/*
1618 * KVM wants to inject page-faults which it got to the guest. This function
1619 * checks whether in a nested guest, we need to inject them to L1 or L2.
1620 * This function assumes it is called with the exit reason in vmcs02 being
1621 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1622 * is running).
1623 */
1624static int nested_pf_handled(struct kvm_vcpu *vcpu)
1625{
1626 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1627
1628 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1629 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1630 return 0;
1631
1632 nested_vmx_vmexit(vcpu);
1633 return 1;
1634}
1635
298101da 1636static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1637 bool has_error_code, u32 error_code,
1638 bool reinject)
298101da 1639{
77ab6db0 1640 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1641 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1642
0b6ac343
NHE		 1643 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1644 nested_pf_handled(vcpu))
1645 return;
1646
8ab2d2e2 1647 if (has_error_code) {
77ab6db0 1648 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1649 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1650 }
77ab6db0 1651
7ffd92c5 1652 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1653 int inc_eip = 0;
1654 if (kvm_exception_is_soft(nr))
1655 inc_eip = vcpu->arch.event_exit_inst_len;
1656 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1657 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1658 return;
1659 }
1660
66fd3f7f
GN		 1661 if (kvm_exception_is_soft(nr)) {
1662 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1663 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1664 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1665 } else
1666 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1667
1668 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1669 vmx_clear_hlt(vcpu);
298101da
AK		 1670}
1671
4e47c7a6
SY		 1672static bool vmx_rdtscp_supported(void)
1673{
1674 return cpu_has_vmx_rdtscp();
1675}
1676
a75beee6
ED		 1677/*
1678 * Swap MSR entry in host/guest MSR entry array.
1679 */
8b9cf98c 1680static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1681{
26bb0981 1682 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1683
1684 tmp = vmx->guest_msrs[to];
1685 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1686 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1687}
1688
e38aea3e
AK		 1689/*
1690 * Set up the vmcs to automatically save and restore system
1691 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1692 * mode, as fiddling with msrs is very expensive.
1693 */
8b9cf98c 1694static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1695{
26bb0981 1696 int save_nmsrs, index;
5897297b 1697 unsigned long *msr_bitmap;
e38aea3e 1698
33f9c505 1699 vmx_load_host_state(vmx);
a75beee6
ED		 1700 save_nmsrs = 0;
1701#ifdef CONFIG_X86_64
8b9cf98c 1702 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1703 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1704 if (index >= 0)
8b9cf98c
RR		 1705 move_msr_up(vmx, index, save_nmsrs++);
1706 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1707 if (index >= 0)
8b9cf98c
RR		 1708 move_msr_up(vmx, index, save_nmsrs++);
1709 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1710 if (index >= 0)
8b9cf98c 1711 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1712 index = __find_msr_index(vmx, MSR_TSC_AUX);
1713 if (index >= 0 && vmx->rdtscp_enabled)
1714 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1715 /*
8c06585d 1716 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1717 * if efer.sce is enabled.
1718 */
8c06585d 1719 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1720 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1721 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1722 }
1723#endif
92c0d900
AK		 1724 index = __find_msr_index(vmx, MSR_EFER);
1725 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1726 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1727
26bb0981 1728 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1729
1730 if (cpu_has_vmx_msr_bitmap()) {
1731 if (is_long_mode(&vmx->vcpu))
1732 msr_bitmap = vmx_msr_bitmap_longmode;
1733 else
1734 msr_bitmap = vmx_msr_bitmap_legacy;
1735
1736 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1737 }
e38aea3e
AK		 1738}
1739
6aa8b732
AK		 1740/*
1741 * reads and returns guest's timestamp counter "register"
1742 * guest_tsc = host_tsc + tsc_offset -- 21.3
1743 */
1744static u64 guest_read_tsc(void)
1745{
1746 u64 host_tsc, tsc_offset;
1747
1748 rdtscll(host_tsc);
1749 tsc_offset = vmcs_read64(TSC_OFFSET);
1750 return host_tsc + tsc_offset;
1751}
1752
4051b188
JR		 1753/*
1754 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1755 * ioctl. In this case the call-back should update internal vmx state to make
1756 * the changes effective.
1757 */
1758static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1759{
1760 /* Nothing to do here */
1761}
1762
6aa8b732 1763/*
99e3e30a 1764 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1765 */
99e3e30a 1766static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1767{
f4e1b3c8 1768 vmcs_write64(TSC_OFFSET, offset);
7991825b
NHE		 1769 if (is_guest_mode(vcpu))
1770 /*
1771 * We're here if L1 chose not to trap the TSC MSR. Since
1772 * prepare_vmcs12() does not copy tsc_offset, we need to also
1773 * set the vmcs12 field here.
1774 */
1775 get_vmcs12(vcpu)->tsc_offset = offset -
1776 to_vmx(vcpu)->nested.vmcs01_tsc_offset;
6aa8b732
AK		 1777}
1778
e48672fa
ZA		 1779static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1780{
1781 u64 offset = vmcs_read64(TSC_OFFSET);
1782 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1783 if (is_guest_mode(vcpu)) {
1784 /* Even when running L2, the adjustment needs to apply to L1 */
1785 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1786 }
e48672fa
ZA		 1787}
1788
857e4099
JR		 1789static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1790{
1791 return target_tsc - native_read_tsc();
1792}
1793
801d3424
NHE		 1794static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1795{
1796 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1797 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1798}
1799
1800/*
1801 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1802 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1803 * all guests if the "nested" module option is off, and can also be disabled
1804 * for a single guest by disabling its VMX cpuid bit.
1805 */
1806static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1807{
1808 return nested && guest_cpuid_has_vmx(vcpu);
1809}
1810
b87a51ae
NHE		 1811/*
1812 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1813 * returned for the various VMX controls MSRs when nested VMX is enabled.
1814 * The same values should also be used to verify that vmcs12 control fields are
1815 * valid during nested entry from L1 to L2.
1816 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1817 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1818 * bit in the high half is on if the corresponding bit in the control field
1819 * may be on. See also vmx_control_verify().
1820 * TODO: allow these variables to be modified (downgraded) by module options
1821 * or other means.
1822 */
1823static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1824static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1825static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1826static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1827static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1828static __init void nested_vmx_setup_ctls_msrs(void)
1829{
1830 /*
1831 * Note that as a general rule, the high half of the MSRs (bits in
1832 * the control fields which may be 1) should be initialized by the
1833 * intersection of the underlying hardware's MSR (i.e., features which
1834 * can be supported) and the list of features we want to expose -
1835 * because they are known to be properly supported in our code.
1836 * Also, usually, the low half of the MSRs (bits which must be 1) can
1837 * be set to 0, meaning that L1 may turn off any of these bits. The
1838 * reason is that if one of these bits is necessary, it will appear
1839 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1840 * fields of vmcs01 and vmcs02, will turn these bits off - and
1841 * nested_vmx_exit_handled() will not pass related exits to L1.
1842 * These rules have exceptions below.
1843 */
1844
1845 /* pin-based controls */
1846 /*
1847 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1848 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1849 */
1850 nested_vmx_pinbased_ctls_low = 0x16 ;
1851 nested_vmx_pinbased_ctls_high = 0x16 |
1852 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1853 PIN_BASED_VIRTUAL_NMIS;
1854
1855 /* exit controls */
1856 nested_vmx_exit_ctls_low = 0;
b6f1250e 1857 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1858#ifdef CONFIG_X86_64
1859 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1860#else
1861 nested_vmx_exit_ctls_high = 0;
1862#endif
1863
1864 /* entry controls */
1865 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1866 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1867 nested_vmx_entry_ctls_low = 0;
1868 nested_vmx_entry_ctls_high &=
1869 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1870
1871 /* cpu-based controls */
1872 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1873 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1874 nested_vmx_procbased_ctls_low = 0;
1875 nested_vmx_procbased_ctls_high &=
1876 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1877 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1878 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1879 CPU_BASED_CR3_STORE_EXITING |
1880#ifdef CONFIG_X86_64
1881 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1882#endif
1883 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1884 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1885 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1886 /*
1887 * We can allow some features even when not supported by the
1888 * hardware. For example, L1 can specify an MSR bitmap - and we
1889 * can use it to avoid exits to L1 - even when L0 runs L2
1890 * without MSR bitmaps.
1891 */
1892 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1893
1894 /* secondary cpu-based controls */
1895 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1896 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1897 nested_vmx_secondary_ctls_low = 0;
1898 nested_vmx_secondary_ctls_high &=
1899 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1900}
1901
1902static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1903{
1904 /*
1905 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1906 */
1907 return ((control & high) | low) == control;
1908}
1909
1910static inline u64 vmx_control_msr(u32 low, u32 high)
1911{
1912 return low | ((u64)high << 32);
1913}
1914
1915/*
1916 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1917 * also let it use VMX-specific MSRs.
1918 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1919 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1920 * like all other MSRs).
1921 */
1922static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1923{
1924 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1925 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1926 /*
1927 * According to the spec, processors which do not support VMX
1928 * should throw a #GP(0) when VMX capability MSRs are read.
1929 */
1930 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1931 return 1;
1932 }
1933
1934 switch (msr_index) {
1935 case MSR_IA32_FEATURE_CONTROL:
1936 *pdata = 0;
1937 break;
1938 case MSR_IA32_VMX_BASIC:
1939 /*
1940 * This MSR reports some information about VMX support. We
1941 * should return information about the VMX we emulate for the
1942 * guest, and the VMCS structure we give it - not about the
1943 * VMX support of the underlying hardware.
1944 */
1945 *pdata = VMCS12_REVISION |
1946 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1947 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1948 break;
1949 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1950 case MSR_IA32_VMX_PINBASED_CTLS:
1951 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1952 nested_vmx_pinbased_ctls_high);
1953 break;
1954 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1955 case MSR_IA32_VMX_PROCBASED_CTLS:
1956 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1957 nested_vmx_procbased_ctls_high);
1958 break;
1959 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1960 case MSR_IA32_VMX_EXIT_CTLS:
1961 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1962 nested_vmx_exit_ctls_high);
1963 break;
1964 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1965 case MSR_IA32_VMX_ENTRY_CTLS:
1966 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1967 nested_vmx_entry_ctls_high);
1968 break;
1969 case MSR_IA32_VMX_MISC:
1970 *pdata = 0;
1971 break;
1972 /*
1973 * These MSRs specify bits which the guest must keep fixed (on or off)
1974 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1975 * We picked the standard core2 setting.
1976 */
1977#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1978#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1979 case MSR_IA32_VMX_CR0_FIXED0:
1980 *pdata = VMXON_CR0_ALWAYSON;
1981 break;
1982 case MSR_IA32_VMX_CR0_FIXED1:
1983 *pdata = -1ULL;
1984 break;
1985 case MSR_IA32_VMX_CR4_FIXED0:
1986 *pdata = VMXON_CR4_ALWAYSON;
1987 break;
1988 case MSR_IA32_VMX_CR4_FIXED1:
1989 *pdata = -1ULL;
1990 break;
1991 case MSR_IA32_VMX_VMCS_ENUM:
1992 *pdata = 0x1f;
1993 break;
1994 case MSR_IA32_VMX_PROCBASED_CTLS2:
1995 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1996 nested_vmx_secondary_ctls_high);
1997 break;
1998 case MSR_IA32_VMX_EPT_VPID_CAP:
1999 /* Currently, no nested ept or nested vpid */
2000 *pdata = 0;
2001 break;
2002 default:
2003 return 0;
2004 }
2005
2006 return 1;
2007}
2008
2009static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2010{
2011 if (!nested_vmx_allowed(vcpu))
2012 return 0;
2013
2014 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2015 /* TODO: the right thing. */
2016 return 1;
2017 /*
2018 * No need to treat VMX capability MSRs specially: If we don't handle
2019 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2020 */
2021 return 0;
2022}
2023
6aa8b732
AK		 2024/*
2025 * Reads an msr value (of 'msr_index') into 'pdata'.
2026 * Returns 0 on success, non-0 otherwise.
2027 * Assumes vcpu_load() was already called.
2028 */
2029static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2030{
2031 u64 data;
26bb0981 2032 struct shared_msr_entry *msr;
6aa8b732
AK		 2033
2034 if (!pdata) {
2035 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2036 return -EINVAL;
2037 }
2038
2039 switch (msr_index) {
05b3e0c2 2040#ifdef CONFIG_X86_64
6aa8b732
AK		 2041 case MSR_FS_BASE:
2042 data = vmcs_readl(GUEST_FS_BASE);
2043 break;
2044 case MSR_GS_BASE:
2045 data = vmcs_readl(GUEST_GS_BASE);
2046 break;
44ea2b17
AK		 2047 case MSR_KERNEL_GS_BASE:
2048 vmx_load_host_state(to_vmx(vcpu));
2049 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2050 break;
26bb0981 2051#endif
6aa8b732 2052 case MSR_EFER:
3bab1f5d 2053 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2054 case MSR_IA32_TSC:
6aa8b732
AK		 2055 data = guest_read_tsc();
2056 break;
2057 case MSR_IA32_SYSENTER_CS:
2058 data = vmcs_read32(GUEST_SYSENTER_CS);
2059 break;
2060 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2061 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2062 break;
2063 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2064 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2065 break;
4e47c7a6
SY		 2066 case MSR_TSC_AUX:
2067 if (!to_vmx(vcpu)->rdtscp_enabled)
2068 return 1;
2069 /* Otherwise falls through */
6aa8b732 2070 default:
26bb0981 2071 vmx_load_host_state(to_vmx(vcpu));
b87a51ae
NHE		 2072 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2073 return 0;
8b9cf98c 2074 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 2075 if (msr) {
542423b0 2076 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 2077 data = msr->data;
2078 break;
6aa8b732 2079 }
3bab1f5d 2080 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2081 }
2082
2083 *pdata = data;
2084 return 0;
2085}
2086
2087/*
2088 * Writes msr value into into the appropriate "register".
2089 * Returns 0 on success, non-0 otherwise.
2090 * Assumes vcpu_load() was already called.
2091 */
2092static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2093{
a2fa3e9f 2094 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2095 struct shared_msr_entry *msr;
2cc51560
ED		 2096 int ret = 0;
2097
6aa8b732 2098 switch (msr_index) {
3bab1f5d 2099 case MSR_EFER:
a9b21b62 2100 vmx_load_host_state(vmx);
2cc51560 2101 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2102 break;
16175a79 2103#ifdef CONFIG_X86_64
6aa8b732 2104 case MSR_FS_BASE:
2fb92db1 2105 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2106 vmcs_writel(GUEST_FS_BASE, data);
2107 break;
2108 case MSR_GS_BASE:
2fb92db1 2109 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2110 vmcs_writel(GUEST_GS_BASE, data);
2111 break;
44ea2b17
AK		 2112 case MSR_KERNEL_GS_BASE:
2113 vmx_load_host_state(vmx);
2114 vmx->msr_guest_kernel_gs_base = data;
2115 break;
6aa8b732
AK		 2116#endif
2117 case MSR_IA32_SYSENTER_CS:
2118 vmcs_write32(GUEST_SYSENTER_CS, data);
2119 break;
2120 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2121 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2122 break;
2123 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2124 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2125 break;
af24a4e4 2126 case MSR_IA32_TSC:
99e3e30a 2127 kvm_write_tsc(vcpu, data);
6aa8b732 2128 break;
468d472f
SY		 2129 case MSR_IA32_CR_PAT:
2130 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2131 vmcs_write64(GUEST_IA32_PAT, data);
2132 vcpu->arch.pat = data;
2133 break;
2134 }
4e47c7a6
SY		 2135 ret = kvm_set_msr_common(vcpu, msr_index, data);
2136 break;
2137 case MSR_TSC_AUX:
2138 if (!vmx->rdtscp_enabled)
2139 return 1;
2140 /* Check reserved bit, higher 32 bits should be zero */
2141 if ((data >> 32) != 0)
2142 return 1;
2143 /* Otherwise falls through */
6aa8b732 2144 default:
b87a51ae
NHE		 2145 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2146 break;
8b9cf98c 2147 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2148 if (msr) {
542423b0 2149 vmx_load_host_state(vmx);
3bab1f5d
AK		 2150 msr->data = data;
2151 break;
6aa8b732 2152 }
2cc51560 2153 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2154 }
2155
2cc51560 2156 return ret;
6aa8b732
AK		 2157}
2158
5fdbf976 2159static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2160{
5fdbf976
MT		 2161 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2162 switch (reg) {
2163 case VCPU_REGS_RSP:
2164 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2165 break;
2166 case VCPU_REGS_RIP:
2167 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2168 break;
6de4f3ad
AK		 2169 case VCPU_EXREG_PDPTR:
2170 if (enable_ept)
2171 ept_save_pdptrs(vcpu);
2172 break;
5fdbf976
MT		 2173 default:
2174 break;
2175 }
6aa8b732
AK		 2176}
2177
355be0b9 2178static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2179{
ae675ef0
JK		 2180 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2181 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2182 else
2183 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2184
abd3f2d6 2185 update_exception_bitmap(vcpu);
6aa8b732
AK		 2186}
2187
2188static __init int cpu_has_kvm_support(void)
2189{
6210e37b 2190 return cpu_has_vmx();
6aa8b732
AK		 2191}
2192
2193static __init int vmx_disabled_by_bios(void)
2194{
2195 u64 msr;
2196
2197 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2198 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2199 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2200 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2201 && tboot_enabled())
2202 return 1;
23f3e991 2203 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2204 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2205 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2206 && !tboot_enabled()) {
2207 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2208 "activate TXT before enabling KVM\n");
cafd6659 2209 return 1;
f9335afe 2210 }
23f3e991
JC		 2211 /* launched w/o TXT and VMX disabled */
2212 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2213 && !tboot_enabled())
2214 return 1;
cafd6659
SW		 2215 }
2216
2217 return 0;
6aa8b732
AK		 2218}
2219
7725b894
DX		 2220static void kvm_cpu_vmxon(u64 addr)
2221{
2222 asm volatile (ASM_VMX_VMXON_RAX
2223 : : "a"(&addr), "m"(addr)
2224 : "memory", "cc");
2225}
2226
10474ae8 2227static int hardware_enable(void *garbage)
6aa8b732
AK		 2228{
2229 int cpu = raw_smp_processor_id();
2230 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2231 u64 old, test_bits;
6aa8b732 2232
10474ae8
AG		 2233 if (read_cr4() & X86_CR4_VMXE)
2234 return -EBUSY;
2235
d462b819 2236 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2237 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2238
2239 test_bits = FEATURE_CONTROL_LOCKED;
2240 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2241 if (tboot_enabled())
2242 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2243
2244 if ((old & test_bits) != test_bits) {
6aa8b732 2245 /* enable and lock */
cafd6659
SW		 2246 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2247 }
66aee91a 2248 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2249
4610c9cc
DX		 2250 if (vmm_exclusive) {
2251 kvm_cpu_vmxon(phys_addr);
2252 ept_sync_global();
2253 }
10474ae8 2254
3444d7da
AK		 2255 store_gdt(&__get_cpu_var(host_gdt));
2256
10474ae8 2257 return 0;
6aa8b732
AK		 2258}
2259
d462b819 2260static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2261{
2262 int cpu = raw_smp_processor_id();
d462b819 2263 struct loaded_vmcs *v, *n;
543e4243 2264
d462b819
NHE		 2265 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2266 loaded_vmcss_on_cpu_link)
2267 __loaded_vmcs_clear(v);
543e4243
AK		 2268}
2269
710ff4a8
EH		 2270
2271/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2272 * tricks.
2273 */
2274static void kvm_cpu_vmxoff(void)
6aa8b732 2275{
4ecac3fd 2276 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2277}
2278
710ff4a8
EH		 2279static void hardware_disable(void *garbage)
2280{
4610c9cc 2281 if (vmm_exclusive) {
d462b819 2282 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2283 kvm_cpu_vmxoff();
2284 }
7725b894 2285 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2286}
2287
1c3d14fe 2288static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2289 u32 msr, u32 *result)
1c3d14fe
YS		 2290{
2291 u32 vmx_msr_low, vmx_msr_high;
2292 u32 ctl = ctl_min | ctl_opt;
2293
2294 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2295
2296 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2297 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2298
2299 /* Ensure minimum (required) set of control bits are supported. */
2300 if (ctl_min & ~ctl)
002c7f7c 2301 return -EIO;
1c3d14fe
YS		 2302
2303 *result = ctl;
2304 return 0;
2305}
2306
110312c8
AK		 2307static __init bool allow_1_setting(u32 msr, u32 ctl)
2308{
2309 u32 vmx_msr_low, vmx_msr_high;
2310
2311 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2312 return vmx_msr_high & ctl;
2313}
2314
002c7f7c 2315static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2316{
2317 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2318 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2319 u32 _pin_based_exec_control = 0;
2320 u32 _cpu_based_exec_control = 0;
f78e0e2e 2321 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2322 u32 _vmexit_control = 0;
2323 u32 _vmentry_control = 0;
2324
2325 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2326 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2327 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2328 &_pin_based_exec_control) < 0)
002c7f7c 2329 return -EIO;
1c3d14fe 2330
443381a8 2331 min =
1c3d14fe
YS		 2332#ifdef CONFIG_X86_64
2333 CPU_BASED_CR8_LOAD_EXITING |
2334 CPU_BASED_CR8_STORE_EXITING |
2335#endif
d56f546d
SY		 2336 CPU_BASED_CR3_LOAD_EXITING |
2337 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2338 CPU_BASED_USE_IO_BITMAPS |
2339 CPU_BASED_MOV_DR_EXITING |
a7052897 2340 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2341 CPU_BASED_MWAIT_EXITING |
2342 CPU_BASED_MONITOR_EXITING |
a7052897 2343 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2344
2345 if (yield_on_hlt)
2346 min |= CPU_BASED_HLT_EXITING;
2347
f78e0e2e 2348 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2349 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2350 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2351 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2352 &_cpu_based_exec_control) < 0)
002c7f7c 2353 return -EIO;
6e5d865c
YS		 2354#ifdef CONFIG_X86_64
2355 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2356 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2357 ~CPU_BASED_CR8_STORE_EXITING;
2358#endif
f78e0e2e 2359 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2360 min2 = 0;
2361 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2362 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2363 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2364 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2365 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2366 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2367 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2368 if (adjust_vmx_controls(min2, opt2,
2369 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2370 &_cpu_based_2nd_exec_control) < 0)
2371 return -EIO;
2372 }
2373#ifndef CONFIG_X86_64
2374 if (!(_cpu_based_2nd_exec_control &
2375 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2376 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2377#endif
d56f546d 2378 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2379 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2380 enabled */
5fff7d27
GN		 2381 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2382 CPU_BASED_CR3_STORE_EXITING |
2383 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2384 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2385 vmx_capability.ept, vmx_capability.vpid);
2386 }
1c3d14fe
YS		 2387
2388 min = 0;
2389#ifdef CONFIG_X86_64
2390 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2391#endif
468d472f 2392 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2393 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2394 &_vmexit_control) < 0)
002c7f7c 2395 return -EIO;
1c3d14fe 2396
468d472f
SY		 2397 min = 0;
2398 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2399 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2400 &_vmentry_control) < 0)
002c7f7c 2401 return -EIO;
6aa8b732 2402
c68876fd 2403 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2404
2405 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2406 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2407 return -EIO;
1c3d14fe
YS		 2408
2409#ifdef CONFIG_X86_64
2410 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2411 if (vmx_msr_high & (1u<<16))
002c7f7c 2412 return -EIO;
1c3d14fe
YS		 2413#endif
2414
2415 /* Require Write-Back (WB) memory type for VMCS accesses. */
2416 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2417 return -EIO;
1c3d14fe 2418
002c7f7c
YS		 2419 vmcs_conf->size = vmx_msr_high & 0x1fff;
2420 vmcs_conf->order = get_order(vmcs_config.size);
2421 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2422
002c7f7c
YS		 2423 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2424 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2425 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2426 vmcs_conf->vmexit_ctrl = _vmexit_control;
2427 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2428
110312c8
AK		 2429 cpu_has_load_ia32_efer =
2430 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2431 VM_ENTRY_LOAD_IA32_EFER)
2432 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2433 VM_EXIT_LOAD_IA32_EFER);
2434
1c3d14fe 2435 return 0;
c68876fd 2436}
6aa8b732
AK		 2437
2438static struct vmcs *alloc_vmcs_cpu(int cpu)
2439{
2440 int node = cpu_to_node(cpu);
2441 struct page *pages;
2442 struct vmcs *vmcs;
2443
6484eb3e 2444 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2445 if (!pages)
2446 return NULL;
2447 vmcs = page_address(pages);
1c3d14fe
YS		 2448 memset(vmcs, 0, vmcs_config.size);
2449 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2450 return vmcs;
2451}
2452
2453static struct vmcs *alloc_vmcs(void)
2454{
d3b2c338 2455 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2456}
2457
2458static void free_vmcs(struct vmcs *vmcs)
2459{
1c3d14fe 2460 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2461}
2462
d462b819
NHE		 2463/*
2464 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2465 */
2466static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2467{
2468 if (!loaded_vmcs->vmcs)
2469 return;
2470 loaded_vmcs_clear(loaded_vmcs);
2471 free_vmcs(loaded_vmcs->vmcs);
2472 loaded_vmcs->vmcs = NULL;
2473}
2474
39959588 2475static void free_kvm_area(void)
6aa8b732
AK		 2476{
2477 int cpu;
2478
3230bb47 2479 for_each_possible_cpu(cpu) {
6aa8b732 2480 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2481 per_cpu(vmxarea, cpu) = NULL;
2482 }
6aa8b732
AK		 2483}
2484
6aa8b732
AK		 2485static __init int alloc_kvm_area(void)
2486{
2487 int cpu;
2488
3230bb47 2489 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2490 struct vmcs *vmcs;
2491
2492 vmcs = alloc_vmcs_cpu(cpu);
2493 if (!vmcs) {
2494 free_kvm_area();
2495 return -ENOMEM;
2496 }
2497
2498 per_cpu(vmxarea, cpu) = vmcs;
2499 }
2500 return 0;
2501}
2502
2503static __init int hardware_setup(void)
2504{
002c7f7c
YS		 2505 if (setup_vmcs_config(&vmcs_config) < 0)
2506 return -EIO;
50a37eb4
JR		 2507
2508 if (boot_cpu_has(X86_FEATURE_NX))
2509 kvm_enable_efer_bits(EFER_NX);
2510
93ba03c2
SY		 2511 if (!cpu_has_vmx_vpid())
2512 enable_vpid = 0;
2513
4bc9b982
SY		 2514 if (!cpu_has_vmx_ept() ||
2515 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2516 enable_ept = 0;
3a624e29
NK		 2517 enable_unrestricted_guest = 0;
2518 }
2519
2520 if (!cpu_has_vmx_unrestricted_guest())
2521 enable_unrestricted_guest = 0;
93ba03c2
SY		 2522
2523 if (!cpu_has_vmx_flexpriority())
2524 flexpriority_enabled = 0;
2525
95ba8273
GN		 2526 if (!cpu_has_vmx_tpr_shadow())
2527 kvm_x86_ops->update_cr8_intercept = NULL;
2528
54dee993
MT		 2529 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2530 kvm_disable_largepages();
2531
4b8d54f9
ZE		 2532 if (!cpu_has_vmx_ple())
2533 ple_gap = 0;
2534
b87a51ae
NHE		 2535 if (nested)
2536 nested_vmx_setup_ctls_msrs();
2537
6aa8b732
AK		 2538 return alloc_kvm_area();
2539}
2540
2541static __exit void hardware_unsetup(void)
2542{
2543 free_kvm_area();
2544}
2545
6aa8b732
AK		 2546static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2547{
2548 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2549
6af11b9e 2550 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2551 vmcs_write16(sf->selector, save->selector);
2552 vmcs_writel(sf->base, save->base);
2553 vmcs_write32(sf->limit, save->limit);
2554 vmcs_write32(sf->ar_bytes, save->ar);
2555 } else {
2556 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2557 << AR_DPL_SHIFT;
2558 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2559 }
2560}
2561
2562static void enter_pmode(struct kvm_vcpu *vcpu)
2563{
2564 unsigned long flags;
a89a8fb9 2565 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2566
a89a8fb9 2567 vmx->emulation_required = 1;
7ffd92c5 2568 vmx->rmode.vm86_active = 0;
6aa8b732 2569
2fb92db1
AK		 2570 vmx_segment_cache_clear(vmx);
2571
d0ba64f9 2572 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2573 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2574 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2575 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2576
2577 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2578 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2579 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2580 vmcs_writel(GUEST_RFLAGS, flags);
2581
66aee91a
RR		 2582 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2583 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2584
2585 update_exception_bitmap(vcpu);
2586
a89a8fb9
MG		 2587 if (emulate_invalid_guest_state)
2588 return;
2589
7ffd92c5
AK		 2590 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2591 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2592 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2593 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2594
2fb92db1
AK		 2595 vmx_segment_cache_clear(vmx);
2596
6aa8b732
AK		 2597 vmcs_write16(GUEST_SS_SELECTOR, 0);
2598 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2599
2600 vmcs_write16(GUEST_CS_SELECTOR,
2601 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2602 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2603}
2604
d77c26fc 2605static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2606{
bfc6d222 2607 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 2608 struct kvm_memslots *slots;
2609 gfn_t base_gfn;
2610
90d83dc3 2611 slots = kvm_memslots(kvm);
f495c6e5 2612 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 2613 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 2614 return base_gfn << PAGE_SHIFT;
2615 }
bfc6d222 2616 return kvm->arch.tss_addr;
6aa8b732
AK		 2617}
2618
2619static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2620{
2621 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2622
2623 save->selector = vmcs_read16(sf->selector);
2624 save->base = vmcs_readl(sf->base);
2625 save->limit = vmcs_read32(sf->limit);
2626 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2627 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2628 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2629 vmcs_write32(sf->limit, 0xffff);
2630 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2631 if (save->base & 0xf)
2632 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2633 " aligned when entering protected mode (seg=%d)",
2634 seg);
6aa8b732
AK		 2635}
2636
2637static void enter_rmode(struct kvm_vcpu *vcpu)
2638{
2639 unsigned long flags;
a89a8fb9 2640 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2641
3a624e29
NK		 2642 if (enable_unrestricted_guest)
2643 return;
2644
a89a8fb9 2645 vmx->emulation_required = 1;
7ffd92c5 2646 vmx->rmode.vm86_active = 1;
6aa8b732 2647
776e58ea
GN		 2648 /*
2649 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2650 * vcpu. Call it here with phys address pointing 16M below 4G.
2651 */
2652 if (!vcpu->kvm->arch.tss_addr) {
2653 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2654 "called before entering vcpu\n");
2655 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2656 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2657 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2658 }
2659
2fb92db1
AK		 2660 vmx_segment_cache_clear(vmx);
2661
d0ba64f9 2662 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2663 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2664 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2665
7ffd92c5 2666 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2667 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2668
7ffd92c5 2669 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2670 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2671
2672 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2673 vmx->rmode.save_rflags = flags;
6aa8b732 2674
053de044 2675 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2676
2677 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2678 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2679 update_exception_bitmap(vcpu);
2680
a89a8fb9
MG		 2681 if (emulate_invalid_guest_state)
2682 goto continue_rmode;
2683
6aa8b732
AK		 2684 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2685 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2686 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2687
2688 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2689 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2690 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2691 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2692 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2693
7ffd92c5
AK		 2694 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2695 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2696 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2697 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2698
a89a8fb9 2699continue_rmode:
8668a3c4 2700 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2701}
2702
401d10de
AS		 2703static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2704{
2705 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2706 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2707
2708 if (!msr)
2709 return;
401d10de 2710
44ea2b17
AK		 2711 /*
2712 * Force kernel_gs_base reloading before EFER changes, as control
2713 * of this msr depends on is_long_mode().
2714 */
2715 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2716 vcpu->arch.efer = efer;
401d10de
AS		 2717 if (efer & EFER_LMA) {
2718 vmcs_write32(VM_ENTRY_CONTROLS,
2719 vmcs_read32(VM_ENTRY_CONTROLS) |
2720 VM_ENTRY_IA32E_MODE);
2721 msr->data = efer;
2722 } else {
2723 vmcs_write32(VM_ENTRY_CONTROLS,
2724 vmcs_read32(VM_ENTRY_CONTROLS) &
2725 ~VM_ENTRY_IA32E_MODE);
2726
2727 msr->data = efer & ~EFER_LME;
2728 }
2729 setup_msrs(vmx);
2730}
2731
05b3e0c2 2732#ifdef CONFIG_X86_64
6aa8b732
AK		 2733
2734static void enter_lmode(struct kvm_vcpu *vcpu)
2735{
2736 u32 guest_tr_ar;
2737
2fb92db1
AK		 2738 vmx_segment_cache_clear(to_vmx(vcpu));
2739
6aa8b732
AK		 2740 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2741 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2742 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 2743 __func__);
6aa8b732
AK		 2744 vmcs_write32(GUEST_TR_AR_BYTES,
2745 (guest_tr_ar & ~AR_TYPE_MASK)
2746 | AR_TYPE_BUSY_64_TSS);
2747 }
da38f438 2748 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2749}
2750
2751static void exit_lmode(struct kvm_vcpu *vcpu)
2752{
6aa8b732
AK		 2753 vmcs_write32(VM_ENTRY_CONTROLS,
2754 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2755 & ~VM_ENTRY_IA32E_MODE);
da38f438 2756 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2757}
2758
2759#endif
2760
2384d2b3
SY		 2761static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2762{
b9d762fa 2763 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2764 if (enable_ept) {
2765 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2766 return;
4e1096d2 2767 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2768 }
2384d2b3
SY		 2769}
2770
e8467fda
AK		 2771static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2772{
2773 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2774
2775 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2776 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2777}
2778
aff48baa
AK		 2779static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2780{
2781 if (enable_ept && is_paging(vcpu))
2782 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2783 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2784}
2785
25c4c276 2786static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2787{
fc78f519
AK		 2788 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2789
2790 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2791 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2792}
2793
1439442c
SY		 2794static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2795{
6de4f3ad
AK		 2796 if (!test_bit(VCPU_EXREG_PDPTR,
2797 (unsigned long *)&vcpu->arch.regs_dirty))
2798 return;
2799
1439442c 2800 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2801 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2802 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2803 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2804 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2805 }
2806}
2807
8f5d549f
AK		 2808static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2809{
2810 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2811 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2812 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2813 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2814 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2815 }
6de4f3ad
AK		 2816
2817 __set_bit(VCPU_EXREG_PDPTR,
2818 (unsigned long *)&vcpu->arch.regs_avail);
2819 __set_bit(VCPU_EXREG_PDPTR,
2820 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2821}
2822
5e1746d6 2823static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2824
2825static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2826 unsigned long cr0,
2827 struct kvm_vcpu *vcpu)
2828{
5233dd51
MT		 2829 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2830 vmx_decache_cr3(vcpu);
1439442c
SY		 2831 if (!(cr0 & X86_CR0_PG)) {
2832 /* From paging/starting to nonpaging */
2833 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2834 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2835 (CPU_BASED_CR3_LOAD_EXITING |
2836 CPU_BASED_CR3_STORE_EXITING));
2837 vcpu->arch.cr0 = cr0;
fc78f519 2838 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2839 } else if (!is_paging(vcpu)) {
2840 /* From nonpaging to paging */
2841 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2842 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2843 ~(CPU_BASED_CR3_LOAD_EXITING |
2844 CPU_BASED_CR3_STORE_EXITING));
2845 vcpu->arch.cr0 = cr0;
fc78f519 2846 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2847 }
95eb84a7
SY		 2848
2849 if (!(cr0 & X86_CR0_WP))
2850 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2851}
2852
6aa8b732
AK		 2853static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2854{
7ffd92c5 2855 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2856 unsigned long hw_cr0;
2857
2858 if (enable_unrestricted_guest)
2859 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2860 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2861 else
2862 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2863
7ffd92c5 2864 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2865 enter_pmode(vcpu);
2866
7ffd92c5 2867 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2868 enter_rmode(vcpu);
2869
05b3e0c2 2870#ifdef CONFIG_X86_64
f6801dff 2871 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2872 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2873 enter_lmode(vcpu);
707d92fa 2874 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2875 exit_lmode(vcpu);
2876 }
2877#endif
2878
089d034e 2879 if (enable_ept)
1439442c
SY		 2880 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2881
02daab21 2882 if (!vcpu->fpu_active)
81231c69 2883 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2884
6aa8b732 2885 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2886 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2887 vcpu->arch.cr0 = cr0;
69c73028 2888 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2889}
2890
1439442c
SY		 2891static u64 construct_eptp(unsigned long root_hpa)
2892{
2893 u64 eptp;
2894
2895 /* TODO write the value reading from MSR */
2896 eptp = VMX_EPT_DEFAULT_MT |
2897 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2898 eptp |= (root_hpa & PAGE_MASK);
2899
2900 return eptp;
2901}
2902
6aa8b732
AK		 2903static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2904{
1439442c
SY		 2905 unsigned long guest_cr3;
2906 u64 eptp;
2907
2908 guest_cr3 = cr3;
089d034e 2909 if (enable_ept) {
1439442c
SY		 2910 eptp = construct_eptp(cr3);
2911 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2912 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2913 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2914 ept_load_pdptrs(vcpu);
1439442c
SY		 2915 }
2916
2384d2b3 2917 vmx_flush_tlb(vcpu);
1439442c 2918 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2919}
2920
5e1746d6 2921static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2922{
7ffd92c5 2923 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2924 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2925
5e1746d6
NHE		 2926 if (cr4 & X86_CR4_VMXE) {
2927 /*
2928 * To use VMXON (and later other VMX instructions), a guest
2929 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2930 * So basically the check on whether to allow nested VMX
2931 * is here.
2932 */
2933 if (!nested_vmx_allowed(vcpu))
2934 return 1;
2935 } else if (to_vmx(vcpu)->nested.vmxon)
2936 return 1;
2937
ad312c7c 2938 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2939 if (enable_ept) {
2940 if (!is_paging(vcpu)) {
2941 hw_cr4 &= ~X86_CR4_PAE;
2942 hw_cr4 |= X86_CR4_PSE;
2943 } else if (!(cr4 & X86_CR4_PAE)) {
2944 hw_cr4 &= ~X86_CR4_PAE;
2945 }
2946 }
1439442c
SY		 2947
2948 vmcs_writel(CR4_READ_SHADOW, cr4);
2949 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2950 return 0;
6aa8b732
AK		 2951}
2952
6aa8b732
AK		 2953static void vmx_get_segment(struct kvm_vcpu *vcpu,
2954 struct kvm_segment *var, int seg)
2955{
a9179499 2956 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 2957 struct kvm_save_segment *save;
6aa8b732
AK		 2958 u32 ar;
2959
a9179499
AK		 2960 if (vmx->rmode.vm86_active
2961 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2962 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2963 || seg == VCPU_SREG_GS)
2964 && !emulate_invalid_guest_state) {
2965 switch (seg) {
2966 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2967 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2968 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2969 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2970 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2971 default: BUG();
2972 }
2973 var->selector = save->selector;
2974 var->base = save->base;
2975 var->limit = save->limit;
2976 ar = save->ar;
2977 if (seg == VCPU_SREG_TR
2fb92db1 2978 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 2979 goto use_saved_rmode_seg;
2980 }
2fb92db1
AK		 2981 var->base = vmx_read_guest_seg_base(vmx, seg);
2982 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2983 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2984 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 2985use_saved_rmode_seg:
9fd4a3b7 2986 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2987 ar = 0;
2988 var->type = ar & 15;
2989 var->s = (ar >> 4) & 1;
2990 var->dpl = (ar >> 5) & 3;
2991 var->present = (ar >> 7) & 1;
2992 var->avl = (ar >> 12) & 1;
2993 var->l = (ar >> 13) & 1;
2994 var->db = (ar >> 14) & 1;
2995 var->g = (ar >> 15) & 1;
2996 var->unusable = (ar >> 16) & 1;
2997}
2998
a9179499
AK		 2999static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3000{
a9179499
AK		 3001 struct kvm_segment s;
3002
3003 if (to_vmx(vcpu)->rmode.vm86_active) {
3004 vmx_get_segment(vcpu, &s, seg);
3005 return s.base;
3006 }
2fb92db1 3007 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3008}
3009
69c73028 3010static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3011{
3eeb3288 3012 if (!is_protmode(vcpu))
2e4d2653
IE		 3013 return 0;
3014
f4c63e5d
AK		 3015 if (!is_long_mode(vcpu)
3016 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3017 return 3;
3018
2fb92db1 3019 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3020}
3021
69c73028
AK		 3022static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3023{
3024 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3025 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3026 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3027 }
3028 return to_vmx(vcpu)->cpl;
3029}
3030
3031
653e3108 3032static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3033{
6aa8b732
AK		 3034 u32 ar;
3035
653e3108 3036 if (var->unusable)
6aa8b732
AK		 3037 ar = 1 << 16;
3038 else {
3039 ar = var->type & 15;
3040 ar |= (var->s & 1) << 4;
3041 ar |= (var->dpl & 3) << 5;
3042 ar |= (var->present & 1) << 7;
3043 ar |= (var->avl & 1) << 12;
3044 ar |= (var->l & 1) << 13;
3045 ar |= (var->db & 1) << 14;
3046 ar |= (var->g & 1) << 15;
3047 }
f7fbf1fd
UL		 3048 if (ar == 0) /* a 0 value means unusable */
3049 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3050
3051 return ar;
3052}
3053
3054static void vmx_set_segment(struct kvm_vcpu *vcpu,
3055 struct kvm_segment *var, int seg)
3056{
7ffd92c5 3057 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3058 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3059 u32 ar;
3060
2fb92db1
AK		 3061 vmx_segment_cache_clear(vmx);
3062
7ffd92c5 3063 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3064 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3065 vmx->rmode.tr.selector = var->selector;
3066 vmx->rmode.tr.base = var->base;
3067 vmx->rmode.tr.limit = var->limit;
3068 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3069 return;
3070 }
3071 vmcs_writel(sf->base, var->base);
3072 vmcs_write32(sf->limit, var->limit);
3073 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3074 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3075 /*
3076 * Hack real-mode segments into vm86 compatibility.
3077 */
3078 if (var->base == 0xffff0000 && var->selector == 0xf000)
3079 vmcs_writel(sf->base, 0xf0000);
3080 ar = 0xf3;
3081 } else
3082 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3083
3084 /*
3085 * Fix the "Accessed" bit in AR field of segment registers for older
3086 * qemu binaries.
3087 * IA32 arch specifies that at the time of processor reset the
3088 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3089 * is setting it to 0 in the usedland code. This causes invalid guest
3090 * state vmexit when "unrestricted guest" mode is turned on.
3091 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3092 * tree. Newer qemu binaries with that qemu fix would not need this
3093 * kvm hack.
3094 */
3095 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3096 ar |= 0x1; /* Accessed */
3097
6aa8b732 3098 vmcs_write32(sf->ar_bytes, ar);
69c73028 3099 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3100}
3101
6aa8b732
AK		 3102static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3103{
2fb92db1 3104 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3105
3106 *db = (ar >> 14) & 1;
3107 *l = (ar >> 13) & 1;
3108}
3109
89a27f4d 3110static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3111{
89a27f4d
GN		 3112 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3113 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3114}
3115
89a27f4d 3116static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3117{
89a27f4d
GN		 3118 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3119 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3120}
3121
89a27f4d 3122static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3123{
89a27f4d
GN		 3124 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3125 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3126}
3127
89a27f4d 3128static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3129{
89a27f4d
GN		 3130 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3131 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3132}
3133
648dfaa7
MG		 3134static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3135{
3136 struct kvm_segment var;
3137 u32 ar;
3138
3139 vmx_get_segment(vcpu, &var, seg);
3140 ar = vmx_segment_access_rights(&var);
3141
3142 if (var.base != (var.selector << 4))
3143 return false;
3144 if (var.limit != 0xffff)
3145 return false;
3146 if (ar != 0xf3)
3147 return false;
3148
3149 return true;
3150}
3151
3152static bool code_segment_valid(struct kvm_vcpu *vcpu)
3153{
3154 struct kvm_segment cs;
3155 unsigned int cs_rpl;
3156
3157 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3158 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3159
1872a3f4
AK		 3160 if (cs.unusable)
3161 return false;
648dfaa7
MG		 3162 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3163 return false;
3164 if (!cs.s)
3165 return false;
1872a3f4 3166 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3167 if (cs.dpl > cs_rpl)
3168 return false;
1872a3f4 3169 } else {
648dfaa7
MG		 3170 if (cs.dpl != cs_rpl)
3171 return false;
3172 }
3173 if (!cs.present)
3174 return false;
3175
3176 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3177 return true;
3178}
3179
3180static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3181{
3182 struct kvm_segment ss;
3183 unsigned int ss_rpl;
3184
3185 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3186 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3187
1872a3f4
AK		 3188 if (ss.unusable)
3189 return true;
3190 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3191 return false;
3192 if (!ss.s)
3193 return false;
3194 if (ss.dpl != ss_rpl) /* DPL != RPL */
3195 return false;
3196 if (!ss.present)
3197 return false;
3198
3199 return true;
3200}
3201
3202static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3203{
3204 struct kvm_segment var;
3205 unsigned int rpl;
3206
3207 vmx_get_segment(vcpu, &var, seg);
3208 rpl = var.selector & SELECTOR_RPL_MASK;
3209
1872a3f4
AK		 3210 if (var.unusable)
3211 return true;
648dfaa7
MG		 3212 if (!var.s)
3213 return false;
3214 if (!var.present)
3215 return false;
3216 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3217 if (var.dpl < rpl) /* DPL < RPL */
3218 return false;
3219 }
3220
3221 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3222 * rights flags
3223 */
3224 return true;
3225}
3226
3227static bool tr_valid(struct kvm_vcpu *vcpu)
3228{
3229 struct kvm_segment tr;
3230
3231 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3232
1872a3f4
AK		 3233 if (tr.unusable)
3234 return false;
648dfaa7
MG		 3235 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3236 return false;
1872a3f4 3237 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3238 return false;
3239 if (!tr.present)
3240 return false;
3241
3242 return true;
3243}
3244
3245static bool ldtr_valid(struct kvm_vcpu *vcpu)
3246{
3247 struct kvm_segment ldtr;
3248
3249 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3250
1872a3f4
AK		 3251 if (ldtr.unusable)
3252 return true;
648dfaa7
MG		 3253 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3254 return false;
3255 if (ldtr.type != 2)
3256 return false;
3257 if (!ldtr.present)
3258 return false;
3259
3260 return true;
3261}
3262
3263static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3264{
3265 struct kvm_segment cs, ss;
3266
3267 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3268 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3269
3270 return ((cs.selector & SELECTOR_RPL_MASK) ==
3271 (ss.selector & SELECTOR_RPL_MASK));
3272}
3273
3274/*
3275 * Check if guest state is valid. Returns true if valid, false if
3276 * not.
3277 * We assume that registers are always usable
3278 */
3279static bool guest_state_valid(struct kvm_vcpu *vcpu)
3280{
3281 /* real mode guest state checks */
3eeb3288 3282 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3283 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3284 return false;
3285 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3286 return false;
3287 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3288 return false;
3289 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3290 return false;
3291 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3292 return false;
3293 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3294 return false;
3295 } else {
3296 /* protected mode guest state checks */
3297 if (!cs_ss_rpl_check(vcpu))
3298 return false;
3299 if (!code_segment_valid(vcpu))
3300 return false;
3301 if (!stack_segment_valid(vcpu))
3302 return false;
3303 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3304 return false;
3305 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3306 return false;
3307 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3308 return false;
3309 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3310 return false;
3311 if (!tr_valid(vcpu))
3312 return false;
3313 if (!ldtr_valid(vcpu))
3314 return false;
3315 }
3316 /* TODO:
3317 * - Add checks on RIP
3318 * - Add checks on RFLAGS
3319 */
3320
3321 return true;
3322}
3323
d77c26fc 3324static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3325{
40dcaa9f 3326 gfn_t fn;
195aefde 3327 u16 data = 0;
40dcaa9f 3328 int r, idx, ret = 0;
6aa8b732 3329
40dcaa9f
XG		 3330 idx = srcu_read_lock(&kvm->srcu);
3331 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3332 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3333 if (r < 0)
10589a46 3334 goto out;
195aefde 3335 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3336 r = kvm_write_guest_page(kvm, fn++, &data,
3337 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3338 if (r < 0)
10589a46 3339 goto out;
195aefde
IE		 3340 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3341 if (r < 0)
10589a46 3342 goto out;
195aefde
IE		 3343 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3344 if (r < 0)
10589a46 3345 goto out;
195aefde 3346 data = ~0;
10589a46
MT		 3347 r = kvm_write_guest_page(kvm, fn, &data,
3348 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3349 sizeof(u8));
195aefde 3350 if (r < 0)
10589a46
MT		 3351 goto out;
3352
3353 ret = 1;
3354out:
40dcaa9f 3355 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3356 return ret;
6aa8b732
AK		 3357}
3358
b7ebfb05
SY		 3359static int init_rmode_identity_map(struct kvm *kvm)
3360{
40dcaa9f 3361 int i, idx, r, ret;
b7ebfb05
SY		 3362 pfn_t identity_map_pfn;
3363 u32 tmp;
3364
089d034e 3365 if (!enable_ept)
b7ebfb05
SY		 3366 return 1;
3367 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3368 printk(KERN_ERR "EPT: identity-mapping pagetable "
3369 "haven't been allocated!\n");
3370 return 0;
3371 }
3372 if (likely(kvm->arch.ept_identity_pagetable_done))
3373 return 1;
3374 ret = 0;
b927a3ce 3375 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3376 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3377 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3378 if (r < 0)
3379 goto out;
3380 /* Set up identity-mapping pagetable for EPT in real mode */
3381 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3382 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3383 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3384 r = kvm_write_guest_page(kvm, identity_map_pfn,
3385 &tmp, i * sizeof(tmp), sizeof(tmp));
3386 if (r < 0)
3387 goto out;
3388 }
3389 kvm->arch.ept_identity_pagetable_done = true;
3390 ret = 1;
3391out:
40dcaa9f 3392 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3393 return ret;
3394}
3395
6aa8b732
AK		 3396static void seg_setup(int seg)
3397{
3398 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3399 unsigned int ar;
6aa8b732
AK		 3400
3401 vmcs_write16(sf->selector, 0);
3402 vmcs_writel(sf->base, 0);
3403 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3404 if (enable_unrestricted_guest) {
3405 ar = 0x93;
3406 if (seg == VCPU_SREG_CS)
3407 ar |= 0x08; /* code segment */
3408 } else
3409 ar = 0xf3;
3410
3411 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3412}
3413
f78e0e2e
SY		 3414static int alloc_apic_access_page(struct kvm *kvm)
3415{
3416 struct kvm_userspace_memory_region kvm_userspace_mem;
3417 int r = 0;
3418
79fac95e 3419 mutex_lock(&kvm->slots_lock);
bfc6d222 3420 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3421 goto out;
3422 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3423 kvm_userspace_mem.flags = 0;
3424 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3425 kvm_userspace_mem.memory_size = PAGE_SIZE;
3426 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3427 if (r)
3428 goto out;
72dc67a6 3429
bfc6d222 3430 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3431out:
79fac95e 3432 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3433 return r;
3434}
3435
b7ebfb05
SY		 3436static int alloc_identity_pagetable(struct kvm *kvm)
3437{
3438 struct kvm_userspace_memory_region kvm_userspace_mem;
3439 int r = 0;
3440
79fac95e 3441 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3442 if (kvm->arch.ept_identity_pagetable)
3443 goto out;
3444 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3445 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3446 kvm_userspace_mem.guest_phys_addr =
3447 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3448 kvm_userspace_mem.memory_size = PAGE_SIZE;
3449 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3450 if (r)
3451 goto out;
3452
b7ebfb05 3453 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3454 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3455out:
79fac95e 3456 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3457 return r;
3458}
3459
2384d2b3
SY		 3460static void allocate_vpid(struct vcpu_vmx *vmx)
3461{
3462 int vpid;
3463
3464 vmx->vpid = 0;
919818ab 3465 if (!enable_vpid)
2384d2b3
SY		 3466 return;
3467 spin_lock(&vmx_vpid_lock);
3468 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3469 if (vpid < VMX_NR_VPIDS) {
3470 vmx->vpid = vpid;
3471 __set_bit(vpid, vmx_vpid_bitmap);
3472 }
3473 spin_unlock(&vmx_vpid_lock);
3474}
3475
cdbecfc3
LJ		 3476static void free_vpid(struct vcpu_vmx *vmx)
3477{
3478 if (!enable_vpid)
3479 return;
3480 spin_lock(&vmx_vpid_lock);
3481 if (vmx->vpid != 0)
3482 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3483 spin_unlock(&vmx_vpid_lock);
3484}
3485
5897297b 3486static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3487{
3e7c73e9 3488 int f = sizeof(unsigned long);
25c5f225
SY		 3489
3490 if (!cpu_has_vmx_msr_bitmap())
3491 return;
3492
3493 /*
3494 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3495 * have the write-low and read-high bitmap offsets the wrong way round.
3496 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3497 */
25c5f225 3498 if (msr <= 0x1fff) {
3e7c73e9
AK		 3499 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3500 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3501 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3502 msr &= 0x1fff;
3e7c73e9
AK		 3503 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3504 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3505 }
25c5f225
SY		 3506}
3507
5897297b
AK		 3508static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3509{
3510 if (!longmode_only)
3511 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3512 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3513}
3514
a3a8ff8e
NHE		 3515/*
3516 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3517 * will not change in the lifetime of the guest.
3518 * Note that host-state that does change is set elsewhere. E.g., host-state
3519 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3520 */
3521static void vmx_set_constant_host_state(void)
3522{
3523 u32 low32, high32;
3524 unsigned long tmpl;
3525 struct desc_ptr dt;
3526
3527 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3528 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3529 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3530
3531 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3532 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3533 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3534 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3535 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3536
3537 native_store_idt(&dt);
3538 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3539
3540 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3541 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3542
3543 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3544 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3545 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3546 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3547
3548 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3549 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3550 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3551 }
3552}
3553
bf8179a0
NHE		 3554static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3555{
3556 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3557 if (enable_ept)
3558 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3559 if (is_guest_mode(&vmx->vcpu))
3560 vmx->vcpu.arch.cr4_guest_owned_bits &=
3561 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3562 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3563}
3564
3565static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3566{
3567 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3568 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3569 exec_control &= ~CPU_BASED_TPR_SHADOW;
3570#ifdef CONFIG_X86_64
3571 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3572 CPU_BASED_CR8_LOAD_EXITING;
3573#endif
3574 }
3575 if (!enable_ept)
3576 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3577 CPU_BASED_CR3_LOAD_EXITING |
3578 CPU_BASED_INVLPG_EXITING;
3579 return exec_control;
3580}
3581
3582static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3583{
3584 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3585 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3586 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3587 if (vmx->vpid == 0)
3588 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3589 if (!enable_ept) {
3590 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3591 enable_unrestricted_guest = 0;
3592 }
3593 if (!enable_unrestricted_guest)
3594 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3595 if (!ple_gap)
3596 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3597 return exec_control;
3598}
3599
6aa8b732
AK		 3600/*
3601 * Sets up the vmcs for emulated real mode.
3602 */
8b9cf98c 3603static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3604{
6aa8b732 3605 unsigned long a;
6aa8b732 3606 int i;
6aa8b732 3607
6aa8b732 3608 /* I/O */
3e7c73e9
AK		 3609 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3610 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3611
25c5f225 3612 if (cpu_has_vmx_msr_bitmap())
5897297b 3613 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3614
6aa8b732
AK		 3615 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3616
6aa8b732 3617 /* Control */
1c3d14fe
YS		 3618 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3619 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3620
bf8179a0 3621 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3622
83ff3b9d 3623 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3624 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3625 vmx_secondary_exec_control(vmx));
83ff3b9d 3626 }
f78e0e2e 3627
4b8d54f9
ZE		 3628 if (ple_gap) {
3629 vmcs_write32(PLE_GAP, ple_gap);
3630 vmcs_write32(PLE_WINDOW, ple_window);
3631 }
3632
c7addb90
AK		 3633 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3634 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 3635 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3636
9581d442
AK		 3637 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3638 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3639 vmx_set_constant_host_state();
05b3e0c2 3640#ifdef CONFIG_X86_64
6aa8b732
AK		 3641 rdmsrl(MSR_FS_BASE, a);
3642 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3643 rdmsrl(MSR_GS_BASE, a);
3644 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3645#else
3646 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3647 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3648#endif
3649
2cc51560
ED		 3650 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3651 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3652 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3653 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3654 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3655
468d472f 3656 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3657 u32 msr_low, msr_high;
3658 u64 host_pat;
468d472f
SY		 3659 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3660 host_pat = msr_low | ((u64) msr_high << 32);
3661 /* Write the default value follow host pat */
3662 vmcs_write64(GUEST_IA32_PAT, host_pat);
3663 /* Keep arch.pat sync with GUEST_IA32_PAT */
3664 vmx->vcpu.arch.pat = host_pat;
3665 }
3666
6aa8b732
AK		 3667 for (i = 0; i < NR_VMX_MSR; ++i) {
3668 u32 index = vmx_msr_index[i];
3669 u32 data_low, data_high;
a2fa3e9f 3670 int j = vmx->nmsrs;
6aa8b732
AK		 3671
3672 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3673 continue;
432bd6cb
AK		 3674 if (wrmsr_safe(index, data_low, data_high) < 0)
3675 continue;
26bb0981
AK		 3676 vmx->guest_msrs[j].index = i;
3677 vmx->guest_msrs[j].data = 0;
d5696725 3678 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3679 ++vmx->nmsrs;
6aa8b732 3680 }
6aa8b732 3681
1c3d14fe 3682 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3683
3684 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3685 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3686
e00c8cf2 3687 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3688 set_cr4_guest_host_mask(vmx);
e00c8cf2 3689
99e3e30a 3690 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3691
e00c8cf2
AK		 3692 return 0;
3693}
3694
3695static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3696{
3697 struct vcpu_vmx *vmx = to_vmx(vcpu);
3698 u64 msr;
4b9d3a04 3699 int ret;
e00c8cf2 3700
5fdbf976 3701 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3702
7ffd92c5 3703 vmx->rmode.vm86_active = 0;
e00c8cf2 3704
3b86cd99
JK		 3705 vmx->soft_vnmi_blocked = 0;
3706
ad312c7c 3707 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3708 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3709 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3710 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3711 msr |= MSR_IA32_APICBASE_BSP;
3712 kvm_set_apic_base(&vmx->vcpu, msr);
3713
10ab25cd
JK		 3714 ret = fx_init(&vmx->vcpu);
3715 if (ret != 0)
3716 goto out;
e00c8cf2 3717
2fb92db1
AK		 3718 vmx_segment_cache_clear(vmx);
3719
5706be0d 3720 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3721 /*
3722 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3723 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3724 */
c5af89b6 3725 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3726 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3727 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3728 } else {
ad312c7c
ZX		 3729 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3730 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3731 }
e00c8cf2
AK		 3732
3733 seg_setup(VCPU_SREG_DS);
3734 seg_setup(VCPU_SREG_ES);
3735 seg_setup(VCPU_SREG_FS);
3736 seg_setup(VCPU_SREG_GS);
3737 seg_setup(VCPU_SREG_SS);
3738
3739 vmcs_write16(GUEST_TR_SELECTOR, 0);
3740 vmcs_writel(GUEST_TR_BASE, 0);
3741 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3742 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3743
3744 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3745 vmcs_writel(GUEST_LDTR_BASE, 0);
3746 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3747 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3748
3749 vmcs_write32(GUEST_SYSENTER_CS, 0);
3750 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3751 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3752
3753 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3754 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3755 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3756 else
5fdbf976
MT		 3757 kvm_rip_write(vcpu, 0);
3758 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3759
e00c8cf2
AK		 3760 vmcs_writel(GUEST_DR7, 0x400);
3761
3762 vmcs_writel(GUEST_GDTR_BASE, 0);
3763 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3764
3765 vmcs_writel(GUEST_IDTR_BASE, 0);
3766 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3767
443381a8 3768 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3769 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3770 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3771
e00c8cf2
AK		 3772 /* Special registers */
3773 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3774
3775 setup_msrs(vmx);
3776
6aa8b732
AK		 3777 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3778
f78e0e2e
SY		 3779 if (cpu_has_vmx_tpr_shadow()) {
3780 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3781 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3782 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3783 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3784 vmcs_write32(TPR_THRESHOLD, 0);
3785 }
3786
3787 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3788 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3789 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3790
2384d2b3
SY		 3791 if (vmx->vpid != 0)
3792 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3793
fa40052c 3794 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3795 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3796 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3797 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3798 vmx_fpu_activate(&vmx->vcpu);
3799 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3800
b9d762fa 3801 vpid_sync_context(vmx);
2384d2b3 3802
3200f405 3803 ret = 0;
6aa8b732 3804
a89a8fb9
MG		 3805 /* HACK: Don't enable emulation on guest boot/reset */
3806 vmx->emulation_required = 0;
3807
6aa8b732
AK		 3808out:
3809 return ret;
3810}
3811
b6f1250e
NHE		 3812/*
3813 * In nested virtualization, check if L1 asked to exit on external interrupts.
3814 * For most existing hypervisors, this will always return true.
3815 */
3816static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3817{
3818 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3819 PIN_BASED_EXT_INTR_MASK;
3820}
3821
3b86cd99
JK		 3822static void enable_irq_window(struct kvm_vcpu *vcpu)
3823{
3824 u32 cpu_based_vm_exec_control;
b6f1250e
NHE		 3825 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3826 /* We can get here when nested_run_pending caused
3827 * vmx_interrupt_allowed() to return false. In this case, do
3828 * nothing - the interrupt will be injected later.
3829 */
3830 return;
3b86cd99
JK		 3831
3832 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3833 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3834 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3835}
3836
3837static void enable_nmi_window(struct kvm_vcpu *vcpu)
3838{
3839 u32 cpu_based_vm_exec_control;
3840
3841 if (!cpu_has_virtual_nmis()) {
3842 enable_irq_window(vcpu);
3843 return;
3844 }
3845
30bd0c4c
AK		 3846 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3847 enable_irq_window(vcpu);
3848 return;
3849 }
3b86cd99
JK		 3850 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3851 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3852 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3853}
3854
66fd3f7f 3855static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3856{
9c8cba37 3857 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3858 uint32_t intr;
3859 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3860
229456fc 3861 trace_kvm_inj_virq(irq);
2714d1d3 3862
fa89a817 3863 ++vcpu->stat.irq_injections;
7ffd92c5 3864 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3865 int inc_eip = 0;
3866 if (vcpu->arch.interrupt.soft)
3867 inc_eip = vcpu->arch.event_exit_inst_len;
3868 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3869 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3870 return;
3871 }
66fd3f7f
GN		 3872 intr = irq | INTR_INFO_VALID_MASK;
3873 if (vcpu->arch.interrupt.soft) {
3874 intr |= INTR_TYPE_SOFT_INTR;
3875 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3876 vmx->vcpu.arch.event_exit_inst_len);
3877 } else
3878 intr |= INTR_TYPE_EXT_INTR;
3879 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 3880 vmx_clear_hlt(vcpu);
85f455f7
ED		 3881}
3882
f08864b4
SY		 3883static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3884{
66a5a347
JK		 3885 struct vcpu_vmx *vmx = to_vmx(vcpu);
3886
0b6ac343
NHE		 3887 if (is_guest_mode(vcpu))
3888 return;
3889
3b86cd99
JK		 3890 if (!cpu_has_virtual_nmis()) {
3891 /*
3892 * Tracking the NMI-blocked state in software is built upon
3893 * finding the next open IRQ window. This, in turn, depends on
3894 * well-behaving guests: They have to keep IRQs disabled at
3895 * least as long as the NMI handler runs. Otherwise we may
3896 * cause NMI nesting, maybe breaking the guest. But as this is
3897 * highly unlikely, we can live with the residual risk.
3898 */
3899 vmx->soft_vnmi_blocked = 1;
3900 vmx->vnmi_blocked_time = 0;
3901 }
3902
487b391d 3903 ++vcpu->stat.nmi_injections;
9d58b931 3904 vmx->nmi_known_unmasked = false;
7ffd92c5 3905 if (vmx->rmode.vm86_active) {
71f9833b 3906 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 3907 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 3908 return;
3909 }
f08864b4
SY		 3910 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3911 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 3912 vmx_clear_hlt(vcpu);
f08864b4
SY		 3913}
3914
c4282df9 3915static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 3916{
3b86cd99 3917 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 3918 return 0;
33f089ca 3919
c4282df9 3920 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 3921 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3922 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 3923}
3924
3cfc3092
JK		 3925static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3926{
3927 if (!cpu_has_virtual_nmis())
3928 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 3929 if (to_vmx(vcpu)->nmi_known_unmasked)
3930 return false;
c332c83a 3931 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3932}
3933
3934static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3935{
3936 struct vcpu_vmx *vmx = to_vmx(vcpu);
3937
3938 if (!cpu_has_virtual_nmis()) {
3939 if (vmx->soft_vnmi_blocked != masked) {
3940 vmx->soft_vnmi_blocked = masked;
3941 vmx->vnmi_blocked_time = 0;
3942 }
3943 } else {
9d58b931 3944 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3945 if (masked)
3946 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3947 GUEST_INTR_STATE_NMI);
3948 else
3949 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3950 GUEST_INTR_STATE_NMI);
3951 }
3952}
3953
78646121
GN		 3954static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3955{
b6f1250e
NHE		 3956 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3957 struct vmcs12 *vmcs12;
3958 if (to_vmx(vcpu)->nested.nested_run_pending)
3959 return 0;
3960 nested_vmx_vmexit(vcpu);
3961 vmcs12 = get_vmcs12(vcpu);
3962 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3963 vmcs12->vm_exit_intr_info = 0;
3964 /* fall through to normal code, but now in L1, not L2 */
3965 }
3966
c4282df9
GN		 3967 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3968 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3969 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3970}
3971
cbc94022
IE		 3972static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3973{
3974 int ret;
3975 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3976 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3977 .guest_phys_addr = addr,
3978 .memory_size = PAGE_SIZE * 3,
3979 .flags = 0,
3980 };
3981
3982 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3983 if (ret)
3984 return ret;
bfc6d222 3985 kvm->arch.tss_addr = addr;
93ea5388
GN		 3986 if (!init_rmode_tss(kvm))
3987 return -ENOMEM;
3988
cbc94022
IE		 3989 return 0;
3990}
3991
6aa8b732
AK		 3992static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3993 int vec, u32 err_code)
3994{
b3f37707
NK		 3995 /*
3996 * Instruction with address size override prefix opcode 0x67
3997 * Cause the #SS fault with 0 error code in VM86 mode.
3998 */
3999 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4000 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4001 return 1;
77ab6db0
JK		 4002 /*
4003 * Forward all other exceptions that are valid in real mode.
4004 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4005 * the required debugging infrastructure rework.
4006 */
4007 switch (vec) {
77ab6db0 4008 case DB_VECTOR:
d0bfb940
JK		 4009 if (vcpu->guest_debug &
4010 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4011 return 0;
4012 kvm_queue_exception(vcpu, vec);
4013 return 1;
77ab6db0 4014 case BP_VECTOR:
c573cd22
JK		 4015 /*
4016 * Update instruction length as we may reinject the exception
4017 * from user space while in guest debugging mode.
4018 */
4019 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4020 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4022 return 0;
4023 /* fall through */
4024 case DE_VECTOR:
77ab6db0
JK		 4025 case OF_VECTOR:
4026 case BR_VECTOR:
4027 case UD_VECTOR:
4028 case DF_VECTOR:
4029 case SS_VECTOR:
4030 case GP_VECTOR:
4031 case MF_VECTOR:
4032 kvm_queue_exception(vcpu, vec);
4033 return 1;
4034 }
6aa8b732
AK		 4035 return 0;
4036}
4037
a0861c02
AK		 4038/*
4039 * Trigger machine check on the host. We assume all the MSRs are already set up
4040 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4041 * We pass a fake environment to the machine check handler because we want
4042 * the guest to be always treated like user space, no matter what context
4043 * it used internally.
4044 */
4045static void kvm_machine_check(void)
4046{
4047#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4048 struct pt_regs regs = {
4049 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4050 .flags = X86_EFLAGS_IF,
4051 };
4052
4053 do_machine_check(&regs, 0);
4054#endif
4055}
4056
851ba692 4057static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4058{
4059 /* already handled by vcpu_run */
4060 return 1;
4061}
4062
851ba692 4063static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4064{
1155f76a 4065 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4066 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4067 u32 intr_info, ex_no, error_code;
42dbaa5a 4068 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4069 u32 vect_info;
4070 enum emulation_result er;
4071
1155f76a 4072 vect_info = vmx->idt_vectoring_info;
88786475 4073 intr_info = vmx->exit_intr_info;
6aa8b732 4074
a0861c02 4075 if (is_machine_check(intr_info))
851ba692 4076 return handle_machine_check(vcpu);
a0861c02 4077
6aa8b732 4078 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4079 !is_page_fault(intr_info)) {
4080 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4081 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4082 vcpu->run->internal.ndata = 2;
4083 vcpu->run->internal.data[0] = vect_info;
4084 vcpu->run->internal.data[1] = intr_info;
4085 return 0;
4086 }
6aa8b732 4087
e4a41889 4088 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4089 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4090
4091 if (is_no_device(intr_info)) {
5fd86fcf 4092 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4093 return 1;
4094 }
4095
7aa81cc0 4096 if (is_invalid_opcode(intr_info)) {
51d8b661 4097 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4098 if (er != EMULATE_DONE)
7ee5d940 4099 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4100 return 1;
4101 }
4102
6aa8b732 4103 error_code = 0;
2e11384c 4104 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4105 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4106 if (is_page_fault(intr_info)) {
1439442c 4107 /* EPT won't cause page fault directly */
089d034e 4108 if (enable_ept)
1439442c 4109 BUG();
6aa8b732 4110 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4111 trace_kvm_page_fault(cr2, error_code);
4112
3298b75c 4113 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4114 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4115 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4116 }
4117
7ffd92c5 4118 if (vmx->rmode.vm86_active &&
6aa8b732 4119 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4120 error_code)) {
ad312c7c
ZX		 4121 if (vcpu->arch.halt_request) {
4122 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4123 return kvm_emulate_halt(vcpu);
4124 }
6aa8b732 4125 return 1;
72d6e5a0 4126 }
6aa8b732 4127
d0bfb940 4128 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4129 switch (ex_no) {
4130 case DB_VECTOR:
4131 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4132 if (!(vcpu->guest_debug &
4133 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4134 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4135 kvm_queue_exception(vcpu, DB_VECTOR);
4136 return 1;
4137 }
4138 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4139 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4140 /* fall through */
4141 case BP_VECTOR:
c573cd22
JK		 4142 /*
4143 * Update instruction length as we may reinject #BP from
4144 * user space while in guest debugging mode. Reading it for
4145 * #DB as well causes no harm, it is not used in that case.
4146 */
4147 vmx->vcpu.arch.event_exit_inst_len =
4148 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4149 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4150 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4151 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4152 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4153 break;
4154 default:
d0bfb940
JK		 4155 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4156 kvm_run->ex.exception = ex_no;
4157 kvm_run->ex.error_code = error_code;
42dbaa5a 4158 break;
6aa8b732 4159 }
6aa8b732
AK		 4160 return 0;
4161}
4162
851ba692 4163static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4164{
1165f5fe 4165 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4166 return 1;
4167}
4168
851ba692 4169static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4170{
851ba692 4171 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4172 return 0;
4173}
6aa8b732 4174
851ba692 4175static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4176{
bfdaab09 4177 unsigned long exit_qualification;
34c33d16 4178 int size, in, string;
039576c0 4179 unsigned port;
6aa8b732 4180
bfdaab09 4181 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4182 string = (exit_qualification & 16) != 0;
cf8f70bf 4183 in = (exit_qualification & 8) != 0;
e70669ab 4184
cf8f70bf 4185 ++vcpu->stat.io_exits;
e70669ab 4186
cf8f70bf 4187 if (string || in)
51d8b661 4188 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4189
cf8f70bf
GN		 4190 port = exit_qualification >> 16;
4191 size = (exit_qualification & 7) + 1;
e93f36bc 4192 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4193
4194 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4195}
4196
102d8325
IM		 4197static void
4198vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4199{
4200 /*
4201 * Patch in the VMCALL instruction:
4202 */
4203 hypercall[0] = 0x0f;
4204 hypercall[1] = 0x01;
4205 hypercall[2] = 0xc1;
102d8325
IM		 4206}
4207
eeadf9e7
NHE		 4208/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4209static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4210{
4211 if (to_vmx(vcpu)->nested.vmxon &&
4212 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4213 return 1;
4214
4215 if (is_guest_mode(vcpu)) {
4216 /*
4217 * We get here when L2 changed cr0 in a way that did not change
4218 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4219 * but did change L0 shadowed bits. This can currently happen
4220 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4221 * loading) while pretending to allow the guest to change it.
4222 */
4223 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4224 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4225 return 1;
4226 vmcs_writel(CR0_READ_SHADOW, val);
4227 return 0;
4228 } else
4229 return kvm_set_cr0(vcpu, val);
4230}
4231
4232static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4233{
4234 if (is_guest_mode(vcpu)) {
4235 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4236 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4237 return 1;
4238 vmcs_writel(CR4_READ_SHADOW, val);
4239 return 0;
4240 } else
4241 return kvm_set_cr4(vcpu, val);
4242}
4243
4244/* called to set cr0 as approriate for clts instruction exit. */
4245static void handle_clts(struct kvm_vcpu *vcpu)
4246{
4247 if (is_guest_mode(vcpu)) {
4248 /*
4249 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4250 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4251 * just pretend it's off (also in arch.cr0 for fpu_activate).
4252 */
4253 vmcs_writel(CR0_READ_SHADOW,
4254 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4255 vcpu->arch.cr0 &= ~X86_CR0_TS;
4256 } else
4257 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4258}
4259
851ba692 4260static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4261{
229456fc 4262 unsigned long exit_qualification, val;
6aa8b732
AK		 4263 int cr;
4264 int reg;
49a9b07e 4265 int err;
6aa8b732 4266
bfdaab09 4267 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4268 cr = exit_qualification & 15;
4269 reg = (exit_qualification >> 8) & 15;
4270 switch ((exit_qualification >> 4) & 3) {
4271 case 0: /* mov to cr */
229456fc
MT		 4272 val = kvm_register_read(vcpu, reg);
4273 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4274 switch (cr) {
4275 case 0:
eeadf9e7 4276 err = handle_set_cr0(vcpu, val);
db8fcefa 4277 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4278 return 1;
4279 case 3:
2390218b 4280 err = kvm_set_cr3(vcpu, val);
db8fcefa 4281 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4282 return 1;
4283 case 4:
eeadf9e7 4284 err = handle_set_cr4(vcpu, val);
db8fcefa 4285 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4286 return 1;
0a5fff19
GN		 4287 case 8: {
4288 u8 cr8_prev = kvm_get_cr8(vcpu);
4289 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4290 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4291 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4292 if (irqchip_in_kernel(vcpu->kvm))
4293 return 1;
4294 if (cr8_prev <= cr8)
4295 return 1;
851ba692 4296 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4297 return 0;
4298 }
6aa8b732
AK		 4299 };
4300 break;
25c4c276 4301 case 2: /* clts */
eeadf9e7 4302 handle_clts(vcpu);
4d4ec087 4303 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4304 skip_emulated_instruction(vcpu);
6b52d186 4305 vmx_fpu_activate(vcpu);
25c4c276 4306 return 1;
6aa8b732
AK		 4307 case 1: /*mov from cr*/
4308 switch (cr) {
4309 case 3:
9f8fe504
AK		 4310 val = kvm_read_cr3(vcpu);
4311 kvm_register_write(vcpu, reg, val);
4312 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4313 skip_emulated_instruction(vcpu);
4314 return 1;
4315 case 8:
229456fc
MT		 4316 val = kvm_get_cr8(vcpu);
4317 kvm_register_write(vcpu, reg, val);
4318 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4319 skip_emulated_instruction(vcpu);
4320 return 1;
4321 }
4322 break;
4323 case 3: /* lmsw */
a1f83a74 4324 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4325 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4326 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4327
4328 skip_emulated_instruction(vcpu);
4329 return 1;
4330 default:
4331 break;
4332 }
851ba692 4333 vcpu->run->exit_reason = 0;
f0242478 4334 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4335 (int)(exit_qualification >> 4) & 3, cr);
4336 return 0;
4337}
4338
851ba692 4339static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4340{
bfdaab09 4341 unsigned long exit_qualification;
6aa8b732
AK		 4342 int dr, reg;
4343
f2483415 4344 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4345 if (!kvm_require_cpl(vcpu, 0))
4346 return 1;
42dbaa5a
JK		 4347 dr = vmcs_readl(GUEST_DR7);
4348 if (dr & DR7_GD) {
4349 /*
4350 * As the vm-exit takes precedence over the debug trap, we
4351 * need to emulate the latter, either for the host or the
4352 * guest debugging itself.
4353 */
4354 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4355 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4356 vcpu->run->debug.arch.dr7 = dr;
4357 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4358 vmcs_readl(GUEST_CS_BASE) +
4359 vmcs_readl(GUEST_RIP);
851ba692
AK		 4360 vcpu->run->debug.arch.exception = DB_VECTOR;
4361 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4362 return 0;
4363 } else {
4364 vcpu->arch.dr7 &= ~DR7_GD;
4365 vcpu->arch.dr6 |= DR6_BD;
4366 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4367 kvm_queue_exception(vcpu, DB_VECTOR);
4368 return 1;
4369 }
4370 }
4371
bfdaab09 4372 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4373 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4374 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4375 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4376 unsigned long val;
4377 if (!kvm_get_dr(vcpu, dr, &val))
4378 kvm_register_write(vcpu, reg, val);
4379 } else
4380 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4381 skip_emulated_instruction(vcpu);
4382 return 1;
4383}
4384
020df079
GN		 4385static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4386{
4387 vmcs_writel(GUEST_DR7, val);
4388}
4389
851ba692 4390static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4391{
06465c5a
AK		 4392 kvm_emulate_cpuid(vcpu);
4393 return 1;
6aa8b732
AK		 4394}
4395
851ba692 4396static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4397{
ad312c7c 4398 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4399 u64 data;
4400
4401 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4402 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4403 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4404 return 1;
4405 }
4406
229456fc 4407 trace_kvm_msr_read(ecx, data);
2714d1d3 4408
6aa8b732 4409 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4410 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4411 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4412 skip_emulated_instruction(vcpu);
4413 return 1;
4414}
4415
851ba692 4416static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4417{
ad312c7c
ZX		 4418 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4419 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4420 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4421
4422 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4423 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4424 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4425 return 1;
4426 }
4427
59200273 4428 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4429 skip_emulated_instruction(vcpu);
4430 return 1;
4431}
4432
851ba692 4433static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4434{
3842d135 4435 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4436 return 1;
4437}
4438
851ba692 4439static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4440{
85f455f7
ED		 4441 u32 cpu_based_vm_exec_control;
4442
4443 /* clear pending irq */
4444 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4445 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4446 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4447
3842d135
AK		 4448 kvm_make_request(KVM_REQ_EVENT, vcpu);
4449
a26bf12a 4450 ++vcpu->stat.irq_window_exits;
2714d1d3 4451
c1150d8c
DL		 4452 /*
4453 * If the user space waits to inject interrupts, exit as soon as
4454 * possible
4455 */
8061823a 4456 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4457 vcpu->run->request_interrupt_window &&
8061823a 4458 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4459 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4460 return 0;
4461 }
6aa8b732
AK		 4462 return 1;
4463}
4464
851ba692 4465static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4466{
4467 skip_emulated_instruction(vcpu);
d3bef15f 4468 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4469}
4470
851ba692 4471static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4472{
510043da 4473 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4474 kvm_emulate_hypercall(vcpu);
4475 return 1;
c21415e8
IM		 4476}
4477
ec25d5e6
GN		 4478static int handle_invd(struct kvm_vcpu *vcpu)
4479{
51d8b661 4480 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4481}
4482
851ba692 4483static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4484{
f9c617f6 4485 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4486
4487 kvm_mmu_invlpg(vcpu, exit_qualification);
4488 skip_emulated_instruction(vcpu);
4489 return 1;
4490}
4491
851ba692 4492static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4493{
4494 skip_emulated_instruction(vcpu);
f5f48ee1 4495 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4496 return 1;
4497}
4498
2acf923e
DC		 4499static int handle_xsetbv(struct kvm_vcpu *vcpu)
4500{
4501 u64 new_bv = kvm_read_edx_eax(vcpu);
4502 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4503
4504 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4505 skip_emulated_instruction(vcpu);
4506 return 1;
4507}
4508
851ba692 4509static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4510{
51d8b661 4511 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4512}
4513
851ba692 4514static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4515{
60637aac 4516 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4517 unsigned long exit_qualification;
e269fb21
JK		 4518 bool has_error_code = false;
4519 u32 error_code = 0;
37817f29 4520 u16 tss_selector;
64a7ec06
GN		 4521 int reason, type, idt_v;
4522
4523 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4524 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4525
4526 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4527
4528 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4529 if (reason == TASK_SWITCH_GATE && idt_v) {
4530 switch (type) {
4531 case INTR_TYPE_NMI_INTR:
4532 vcpu->arch.nmi_injected = false;
654f06fc 4533 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4534 break;
4535 case INTR_TYPE_EXT_INTR:
66fd3f7f 4536 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4537 kvm_clear_interrupt_queue(vcpu);
4538 break;
4539 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4540 if (vmx->idt_vectoring_info &
4541 VECTORING_INFO_DELIVER_CODE_MASK) {
4542 has_error_code = true;
4543 error_code =
4544 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4545 }
4546 /* fall through */
64a7ec06
GN		 4547 case INTR_TYPE_SOFT_EXCEPTION:
4548 kvm_clear_exception_queue(vcpu);
4549 break;
4550 default:
4551 break;
4552 }
60637aac 4553 }
37817f29
IE		 4554 tss_selector = exit_qualification;
4555
64a7ec06
GN		 4556 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4557 type != INTR_TYPE_EXT_INTR &&
4558 type != INTR_TYPE_NMI_INTR))
4559 skip_emulated_instruction(vcpu);
4560
acb54517
GN		 4561 if (kvm_task_switch(vcpu, tss_selector, reason,
4562 has_error_code, error_code) == EMULATE_FAIL) {
4563 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4564 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4565 vcpu->run->internal.ndata = 0;
42dbaa5a 4566 return 0;
acb54517 4567 }
42dbaa5a
JK		 4568
4569 /* clear all local breakpoint enable flags */
4570 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4571
4572 /*
4573 * TODO: What about debug traps on tss switch?
4574 * Are we supposed to inject them and update dr6?
4575 */
4576
4577 return 1;
37817f29
IE		 4578}
4579
851ba692 4580static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4581{
f9c617f6 4582 unsigned long exit_qualification;
1439442c 4583 gpa_t gpa;
1439442c 4584 int gla_validity;
1439442c 4585
f9c617f6 4586 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4587
4588 if (exit_qualification & (1 << 6)) {
4589 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4590 return -EINVAL;
1439442c
SY		 4591 }
4592
4593 gla_validity = (exit_qualification >> 7) & 0x3;
4594 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4595 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4596 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4597 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4598 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4599 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4600 (long unsigned int)exit_qualification);
851ba692
AK		 4601 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4602 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4603 return 0;
1439442c
SY		 4604 }
4605
4606 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4607 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4608 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4609}
4610
68f89400
MT		 4611static u64 ept_rsvd_mask(u64 spte, int level)
4612{
4613 int i;
4614 u64 mask = 0;
4615
4616 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4617 mask |= (1ULL << i);
4618
4619 if (level > 2)
4620 /* bits 7:3 reserved */
4621 mask |= 0xf8;
4622 else if (level == 2) {
4623 if (spte & (1ULL << 7))
4624 /* 2MB ref, bits 20:12 reserved */
4625 mask |= 0x1ff000;
4626 else
4627 /* bits 6:3 reserved */
4628 mask |= 0x78;
4629 }
4630
4631 return mask;
4632}
4633
4634static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4635 int level)
4636{
4637 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4638
4639 /* 010b (write-only) */
4640 WARN_ON((spte & 0x7) == 0x2);
4641
4642 /* 110b (write/execute) */
4643 WARN_ON((spte & 0x7) == 0x6);
4644
4645 /* 100b (execute-only) and value not supported by logical processor */
4646 if (!cpu_has_vmx_ept_execute_only())
4647 WARN_ON((spte & 0x7) == 0x4);
4648
4649 /* not 000b */
4650 if ((spte & 0x7)) {
4651 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4652
4653 if (rsvd_bits != 0) {
4654 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4655 __func__, rsvd_bits);
4656 WARN_ON(1);
4657 }
4658
4659 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4660 u64 ept_mem_type = (spte & 0x38) >> 3;
4661
4662 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4663 ept_mem_type == 7) {
4664 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4665 __func__, ept_mem_type);
4666 WARN_ON(1);
4667 }
4668 }
4669 }
4670}
4671
851ba692 4672static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4673{
4674 u64 sptes[4];
4675 int nr_sptes, i;
4676 gpa_t gpa;
4677
4678 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4679
4680 printk(KERN_ERR "EPT: Misconfiguration.\n");
4681 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4682
4683 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4684
4685 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4686 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4687
851ba692
AK		 4688 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4689 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4690
4691 return 0;
4692}
4693
851ba692 4694static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4695{
4696 u32 cpu_based_vm_exec_control;
4697
4698 /* clear pending NMI */
4699 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4700 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4701 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4702 ++vcpu->stat.nmi_window_exits;
3842d135 4703 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4704
4705 return 1;
4706}
4707
80ced186 4708static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4709{
8b3079a5
AK		 4710 struct vcpu_vmx *vmx = to_vmx(vcpu);
4711 enum emulation_result err = EMULATE_DONE;
80ced186 4712 int ret = 1;
49e9d557
AK		 4713 u32 cpu_exec_ctrl;
4714 bool intr_window_requested;
4715
4716 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4717 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4718
4719 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4720 if (intr_window_requested
4721 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4722 return handle_interrupt_window(&vmx->vcpu);
4723
51d8b661 4724 err = emulate_instruction(vcpu, 0);
ea953ef0 4725
80ced186
MG		 4726 if (err == EMULATE_DO_MMIO) {
4727 ret = 0;
4728 goto out;
4729 }
1d5a4d9b 4730
6d77dbfc
GN		 4731 if (err != EMULATE_DONE)
4732 return 0;
ea953ef0
MG		 4733
4734 if (signal_pending(current))
80ced186 4735 goto out;
ea953ef0
MG		 4736 if (need_resched())
4737 schedule();
4738 }
4739
80ced186
MG		 4740 vmx->emulation_required = 0;
4741out:
4742 return ret;
ea953ef0
MG		 4743}
4744
4b8d54f9
ZE		 4745/*
4746 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4747 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4748 */
9fb41ba8 4749static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4750{
4751 skip_emulated_instruction(vcpu);
4752 kvm_vcpu_on_spin(vcpu);
4753
4754 return 1;
4755}
4756
59708670
SY		 4757static int handle_invalid_op(struct kvm_vcpu *vcpu)
4758{
4759 kvm_queue_exception(vcpu, UD_VECTOR);
4760 return 1;
4761}
4762
ff2f6fe9
NHE		 4763/*
4764 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4765 * We could reuse a single VMCS for all the L2 guests, but we also want the
4766 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4767 * allows keeping them loaded on the processor, and in the future will allow
4768 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4769 * every entry if they never change.
4770 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4771 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4772 *
4773 * The following functions allocate and free a vmcs02 in this pool.
4774 */
4775
4776/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4777static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4778{
4779 struct vmcs02_list *item;
4780 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4781 if (item->vmptr == vmx->nested.current_vmptr) {
4782 list_move(&item->list, &vmx->nested.vmcs02_pool);
4783 return &item->vmcs02;
4784 }
4785
4786 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4787 /* Recycle the least recently used VMCS. */
4788 item = list_entry(vmx->nested.vmcs02_pool.prev,
4789 struct vmcs02_list, list);
4790 item->vmptr = vmx->nested.current_vmptr;
4791 list_move(&item->list, &vmx->nested.vmcs02_pool);
4792 return &item->vmcs02;
4793 }
4794
4795 /* Create a new VMCS */
4796 item = (struct vmcs02_list *)
4797 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4798 if (!item)
4799 return NULL;
4800 item->vmcs02.vmcs = alloc_vmcs();
4801 if (!item->vmcs02.vmcs) {
4802 kfree(item);
4803 return NULL;
4804 }
4805 loaded_vmcs_init(&item->vmcs02);
4806 item->vmptr = vmx->nested.current_vmptr;
4807 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4808 vmx->nested.vmcs02_num++;
4809 return &item->vmcs02;
4810}
4811
4812/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4813static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4814{
4815 struct vmcs02_list *item;
4816 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4817 if (item->vmptr == vmptr) {
4818 free_loaded_vmcs(&item->vmcs02);
4819 list_del(&item->list);
4820 kfree(item);
4821 vmx->nested.vmcs02_num--;
4822 return;
4823 }
4824}
4825
4826/*
4827 * Free all VMCSs saved for this vcpu, except the one pointed by
4828 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4829 * currently used, if running L2), and vmcs01 when running L2.
4830 */
4831static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4832{
4833 struct vmcs02_list *item, *n;
4834 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4835 if (vmx->loaded_vmcs != &item->vmcs02)
4836 free_loaded_vmcs(&item->vmcs02);
4837 list_del(&item->list);
4838 kfree(item);
4839 }
4840 vmx->nested.vmcs02_num = 0;
4841
4842 if (vmx->loaded_vmcs != &vmx->vmcs01)
4843 free_loaded_vmcs(&vmx->vmcs01);
4844}
4845
ec378aee
NHE		 4846/*
4847 * Emulate the VMXON instruction.
4848 * Currently, we just remember that VMX is active, and do not save or even
4849 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4850 * do not currently need to store anything in that guest-allocated memory
4851 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4852 * argument is different from the VMXON pointer (which the spec says they do).
4853 */
4854static int handle_vmon(struct kvm_vcpu *vcpu)
4855{
4856 struct kvm_segment cs;
4857 struct vcpu_vmx *vmx = to_vmx(vcpu);
4858
4859 /* The Intel VMX Instruction Reference lists a bunch of bits that
4860 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4861 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4862 * Otherwise, we should fail with #UD. We test these now:
4863 */
4864 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4865 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4866 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4867 kvm_queue_exception(vcpu, UD_VECTOR);
4868 return 1;
4869 }
4870
4871 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4872 if (is_long_mode(vcpu) && !cs.l) {
4873 kvm_queue_exception(vcpu, UD_VECTOR);
4874 return 1;
4875 }
4876
4877 if (vmx_get_cpl(vcpu)) {
4878 kvm_inject_gp(vcpu, 0);
4879 return 1;
4880 }
4881
ff2f6fe9
NHE		 4882 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4883 vmx->nested.vmcs02_num = 0;
4884
ec378aee
NHE		 4885 vmx->nested.vmxon = true;
4886
4887 skip_emulated_instruction(vcpu);
4888 return 1;
4889}
4890
4891/*
4892 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4893 * for running VMX instructions (except VMXON, whose prerequisites are
4894 * slightly different). It also specifies what exception to inject otherwise.
4895 */
4896static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4897{
4898 struct kvm_segment cs;
4899 struct vcpu_vmx *vmx = to_vmx(vcpu);
4900
4901 if (!vmx->nested.vmxon) {
4902 kvm_queue_exception(vcpu, UD_VECTOR);
4903 return 0;
4904 }
4905
4906 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4907 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4908 (is_long_mode(vcpu) && !cs.l)) {
4909 kvm_queue_exception(vcpu, UD_VECTOR);
4910 return 0;
4911 }
4912
4913 if (vmx_get_cpl(vcpu)) {
4914 kvm_inject_gp(vcpu, 0);
4915 return 0;
4916 }
4917
4918 return 1;
4919}
4920
4921/*
4922 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4923 * just stops using VMX.
4924 */
4925static void free_nested(struct vcpu_vmx *vmx)
4926{
4927 if (!vmx->nested.vmxon)
4928 return;
4929 vmx->nested.vmxon = false;
a9d30f33
NHE		 4930 if (vmx->nested.current_vmptr != -1ull) {
4931 kunmap(vmx->nested.current_vmcs12_page);
4932 nested_release_page(vmx->nested.current_vmcs12_page);
4933 vmx->nested.current_vmptr = -1ull;
4934 vmx->nested.current_vmcs12 = NULL;
4935 }
fe3ef05c
NHE		 4936 /* Unpin physical memory we referred to in current vmcs02 */
4937 if (vmx->nested.apic_access_page) {
4938 nested_release_page(vmx->nested.apic_access_page);
4939 vmx->nested.apic_access_page = 0;
4940 }
ff2f6fe9
NHE		 4941
4942 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 4943}
4944
4945/* Emulate the VMXOFF instruction */
4946static int handle_vmoff(struct kvm_vcpu *vcpu)
4947{
4948 if (!nested_vmx_check_permission(vcpu))
4949 return 1;
4950 free_nested(to_vmx(vcpu));
4951 skip_emulated_instruction(vcpu);
4952 return 1;
4953}
4954
064aea77
NHE		 4955/*
4956 * Decode the memory-address operand of a vmx instruction, as recorded on an
4957 * exit caused by such an instruction (run by a guest hypervisor).
4958 * On success, returns 0. When the operand is invalid, returns 1 and throws
4959 * #UD or #GP.
4960 */
4961static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4962 unsigned long exit_qualification,
4963 u32 vmx_instruction_info, gva_t *ret)
4964{
4965 /*
4966 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4967 * Execution", on an exit, vmx_instruction_info holds most of the
4968 * addressing components of the operand. Only the displacement part
4969 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4970 * For how an actual address is calculated from all these components,
4971 * refer to Vol. 1, "Operand Addressing".
4972 */
4973 int scaling = vmx_instruction_info & 3;
4974 int addr_size = (vmx_instruction_info >> 7) & 7;
4975 bool is_reg = vmx_instruction_info & (1u << 10);
4976 int seg_reg = (vmx_instruction_info >> 15) & 7;
4977 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4978 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4979 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4980 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4981
4982 if (is_reg) {
4983 kvm_queue_exception(vcpu, UD_VECTOR);
4984 return 1;
4985 }
4986
4987 /* Addr = segment_base + offset */
4988 /* offset = base + [index * scale] + displacement */
4989 *ret = vmx_get_segment_base(vcpu, seg_reg);
4990 if (base_is_valid)
4991 *ret += kvm_register_read(vcpu, base_reg);
4992 if (index_is_valid)
4993 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4994 *ret += exit_qualification; /* holds the displacement */
4995
4996 if (addr_size == 1) /* 32 bit */
4997 *ret &= 0xffffffff;
4998
4999 /*
5000 * TODO: throw #GP (and return 1) in various cases that the VM*
5001 * instructions require it - e.g., offset beyond segment limit,
5002 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5003 * address, and so on. Currently these are not checked.
5004 */
5005 return 0;
5006}
5007
0140caea
NHE		 5008/*
5009 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5010 * set the success or error code of an emulated VMX instruction, as specified
5011 * by Vol 2B, VMX Instruction Reference, "Conventions".
5012 */
5013static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5014{
5015 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5016 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5017 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5018}
5019
5020static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5021{
5022 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5023 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5024 X86_EFLAGS_SF | X86_EFLAGS_OF))
5025 | X86_EFLAGS_CF);
5026}
5027
5028static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5029 u32 vm_instruction_error)
5030{
5031 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5032 /*
5033 * failValid writes the error number to the current VMCS, which
5034 * can't be done there isn't a current VMCS.
5035 */
5036 nested_vmx_failInvalid(vcpu);
5037 return;
5038 }
5039 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5040 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5041 X86_EFLAGS_SF | X86_EFLAGS_OF))
5042 | X86_EFLAGS_ZF);
5043 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5044}
5045
27d6c865
NHE		 5046/* Emulate the VMCLEAR instruction */
5047static int handle_vmclear(struct kvm_vcpu *vcpu)
5048{
5049 struct vcpu_vmx *vmx = to_vmx(vcpu);
5050 gva_t gva;
5051 gpa_t vmptr;
5052 struct vmcs12 *vmcs12;
5053 struct page *page;
5054 struct x86_exception e;
5055
5056 if (!nested_vmx_check_permission(vcpu))
5057 return 1;
5058
5059 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5060 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5061 return 1;
5062
5063 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5064 sizeof(vmptr), &e)) {
5065 kvm_inject_page_fault(vcpu, &e);
5066 return 1;
5067 }
5068
5069 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5070 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5071 skip_emulated_instruction(vcpu);
5072 return 1;
5073 }
5074
5075 if (vmptr == vmx->nested.current_vmptr) {
5076 kunmap(vmx->nested.current_vmcs12_page);
5077 nested_release_page(vmx->nested.current_vmcs12_page);
5078 vmx->nested.current_vmptr = -1ull;
5079 vmx->nested.current_vmcs12 = NULL;
5080 }
5081
5082 page = nested_get_page(vcpu, vmptr);
5083 if (page == NULL) {
5084 /*
5085 * For accurate processor emulation, VMCLEAR beyond available
5086 * physical memory should do nothing at all. However, it is
5087 * possible that a nested vmx bug, not a guest hypervisor bug,
5088 * resulted in this case, so let's shut down before doing any
5089 * more damage:
5090 */
5091 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5092 return 1;
5093 }
5094 vmcs12 = kmap(page);
5095 vmcs12->launch_state = 0;
5096 kunmap(page);
5097 nested_release_page(page);
5098
5099 nested_free_vmcs02(vmx, vmptr);
5100
5101 skip_emulated_instruction(vcpu);
5102 nested_vmx_succeed(vcpu);
5103 return 1;
5104}
5105
cd232ad0
NHE		 5106static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5107
5108/* Emulate the VMLAUNCH instruction */
5109static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5110{
5111 return nested_vmx_run(vcpu, true);
5112}
5113
5114/* Emulate the VMRESUME instruction */
5115static int handle_vmresume(struct kvm_vcpu *vcpu)
5116{
5117
5118 return nested_vmx_run(vcpu, false);
5119}
5120
49f705c5
NHE		 5121enum vmcs_field_type {
5122 VMCS_FIELD_TYPE_U16 = 0,
5123 VMCS_FIELD_TYPE_U64 = 1,
5124 VMCS_FIELD_TYPE_U32 = 2,
5125 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5126};
5127
5128static inline int vmcs_field_type(unsigned long field)
5129{
5130 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5131 return VMCS_FIELD_TYPE_U32;
5132 return (field >> 13) & 0x3 ;
5133}
5134
5135static inline int vmcs_field_readonly(unsigned long field)
5136{
5137 return (((field >> 10) & 0x3) == 1);
5138}
5139
5140/*
5141 * Read a vmcs12 field. Since these can have varying lengths and we return
5142 * one type, we chose the biggest type (u64) and zero-extend the return value
5143 * to that size. Note that the caller, handle_vmread, might need to use only
5144 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5145 * 64-bit fields are to be returned).
5146 */
5147static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5148 unsigned long field, u64 *ret)
5149{
5150 short offset = vmcs_field_to_offset(field);
5151 char *p;
5152
5153 if (offset < 0)
5154 return 0;
5155
5156 p = ((char *)(get_vmcs12(vcpu))) + offset;
5157
5158 switch (vmcs_field_type(field)) {
5159 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5160 *ret = *((natural_width *)p);
5161 return 1;
5162 case VMCS_FIELD_TYPE_U16:
5163 *ret = *((u16 *)p);
5164 return 1;
5165 case VMCS_FIELD_TYPE_U32:
5166 *ret = *((u32 *)p);
5167 return 1;
5168 case VMCS_FIELD_TYPE_U64:
5169 *ret = *((u64 *)p);
5170 return 1;
5171 default:
5172 return 0; /* can never happen. */
5173 }
5174}
5175
5176/*
5177 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5178 * used before) all generate the same failure when it is missing.
5179 */
5180static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5181{
5182 struct vcpu_vmx *vmx = to_vmx(vcpu);
5183 if (vmx->nested.current_vmptr == -1ull) {
5184 nested_vmx_failInvalid(vcpu);
5185 skip_emulated_instruction(vcpu);
5186 return 0;
5187 }
5188 return 1;
5189}
5190
5191static int handle_vmread(struct kvm_vcpu *vcpu)
5192{
5193 unsigned long field;
5194 u64 field_value;
5195 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5196 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5197 gva_t gva = 0;
5198
5199 if (!nested_vmx_check_permission(vcpu) ||
5200 !nested_vmx_check_vmcs12(vcpu))
5201 return 1;
5202
5203 /* Decode instruction info and find the field to read */
5204 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5205 /* Read the field, zero-extended to a u64 field_value */
5206 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5207 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5208 skip_emulated_instruction(vcpu);
5209 return 1;
5210 }
5211 /*
5212 * Now copy part of this value to register or memory, as requested.
5213 * Note that the number of bits actually copied is 32 or 64 depending
5214 * on the guest's mode (32 or 64 bit), not on the given field's length.
5215 */
5216 if (vmx_instruction_info & (1u << 10)) {
5217 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5218 field_value);
5219 } else {
5220 if (get_vmx_mem_address(vcpu, exit_qualification,
5221 vmx_instruction_info, &gva))
5222 return 1;
5223 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5224 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5225 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5226 }
5227
5228 nested_vmx_succeed(vcpu);
5229 skip_emulated_instruction(vcpu);
5230 return 1;
5231}
5232
5233
5234static int handle_vmwrite(struct kvm_vcpu *vcpu)
5235{
5236 unsigned long field;
5237 gva_t gva;
5238 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5239 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5240 char *p;
5241 short offset;
5242 /* The value to write might be 32 or 64 bits, depending on L1's long
5243 * mode, and eventually we need to write that into a field of several
5244 * possible lengths. The code below first zero-extends the value to 64
5245 * bit (field_value), and then copies only the approriate number of
5246 * bits into the vmcs12 field.
5247 */
5248 u64 field_value = 0;
5249 struct x86_exception e;
5250
5251 if (!nested_vmx_check_permission(vcpu) ||
5252 !nested_vmx_check_vmcs12(vcpu))
5253 return 1;
5254
5255 if (vmx_instruction_info & (1u << 10))
5256 field_value = kvm_register_read(vcpu,
5257 (((vmx_instruction_info) >> 3) & 0xf));
5258 else {
5259 if (get_vmx_mem_address(vcpu, exit_qualification,
5260 vmx_instruction_info, &gva))
5261 return 1;
5262 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5263 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5264 kvm_inject_page_fault(vcpu, &e);
5265 return 1;
5266 }
5267 }
5268
5269
5270 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5271 if (vmcs_field_readonly(field)) {
5272 nested_vmx_failValid(vcpu,
5273 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5274 skip_emulated_instruction(vcpu);
5275 return 1;
5276 }
5277
5278 offset = vmcs_field_to_offset(field);
5279 if (offset < 0) {
5280 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5281 skip_emulated_instruction(vcpu);
5282 return 1;
5283 }
5284 p = ((char *) get_vmcs12(vcpu)) + offset;
5285
5286 switch (vmcs_field_type(field)) {
5287 case VMCS_FIELD_TYPE_U16:
5288 *(u16 *)p = field_value;
5289 break;
5290 case VMCS_FIELD_TYPE_U32:
5291 *(u32 *)p = field_value;
5292 break;
5293 case VMCS_FIELD_TYPE_U64:
5294 *(u64 *)p = field_value;
5295 break;
5296 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5297 *(natural_width *)p = field_value;
5298 break;
5299 default:
5300 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5301 skip_emulated_instruction(vcpu);
5302 return 1;
5303 }
5304
5305 nested_vmx_succeed(vcpu);
5306 skip_emulated_instruction(vcpu);
5307 return 1;
5308}
5309
63846663
NHE		 5310/* Emulate the VMPTRLD instruction */
5311static int handle_vmptrld(struct kvm_vcpu *vcpu)
5312{
5313 struct vcpu_vmx *vmx = to_vmx(vcpu);
5314 gva_t gva;
5315 gpa_t vmptr;
5316 struct x86_exception e;
5317
5318 if (!nested_vmx_check_permission(vcpu))
5319 return 1;
5320
5321 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5322 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5323 return 1;
5324
5325 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5326 sizeof(vmptr), &e)) {
5327 kvm_inject_page_fault(vcpu, &e);
5328 return 1;
5329 }
5330
5331 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5332 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5333 skip_emulated_instruction(vcpu);
5334 return 1;
5335 }
5336
5337 if (vmx->nested.current_vmptr != vmptr) {
5338 struct vmcs12 *new_vmcs12;
5339 struct page *page;
5340 page = nested_get_page(vcpu, vmptr);
5341 if (page == NULL) {
5342 nested_vmx_failInvalid(vcpu);
5343 skip_emulated_instruction(vcpu);
5344 return 1;
5345 }
5346 new_vmcs12 = kmap(page);
5347 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5348 kunmap(page);
5349 nested_release_page_clean(page);
5350 nested_vmx_failValid(vcpu,
5351 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5352 skip_emulated_instruction(vcpu);
5353 return 1;
5354 }
5355 if (vmx->nested.current_vmptr != -1ull) {
5356 kunmap(vmx->nested.current_vmcs12_page);
5357 nested_release_page(vmx->nested.current_vmcs12_page);
5358 }
5359
5360 vmx->nested.current_vmptr = vmptr;
5361 vmx->nested.current_vmcs12 = new_vmcs12;
5362 vmx->nested.current_vmcs12_page = page;
5363 }
5364
5365 nested_vmx_succeed(vcpu);
5366 skip_emulated_instruction(vcpu);
5367 return 1;
5368}
5369
6a4d7550
NHE		 5370/* Emulate the VMPTRST instruction */
5371static int handle_vmptrst(struct kvm_vcpu *vcpu)
5372{
5373 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5374 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5375 gva_t vmcs_gva;
5376 struct x86_exception e;
5377
5378 if (!nested_vmx_check_permission(vcpu))
5379 return 1;
5380
5381 if (get_vmx_mem_address(vcpu, exit_qualification,
5382 vmx_instruction_info, &vmcs_gva))
5383 return 1;
5384 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5385 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5386 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5387 sizeof(u64), &e)) {
5388 kvm_inject_page_fault(vcpu, &e);
5389 return 1;
5390 }
5391 nested_vmx_succeed(vcpu);
5392 skip_emulated_instruction(vcpu);
5393 return 1;
5394}
5395
6aa8b732
AK		 5396/*
5397 * The exit handlers return 1 if the exit was handled fully and guest execution
5398 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5399 * to be done to userspace and return 0.
5400 */
851ba692 5401static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5402 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5403 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5404 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5405 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5406 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5407 [EXIT_REASON_CR_ACCESS] = handle_cr,
5408 [EXIT_REASON_DR_ACCESS] = handle_dr,
5409 [EXIT_REASON_CPUID] = handle_cpuid,
5410 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5411 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5412 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5413 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5414 [EXIT_REASON_INVD] = handle_invd,
a7052897 5415 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5416 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5417 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5418 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5419 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5420 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5421 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5422 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5423 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5424 [EXIT_REASON_VMOFF] = handle_vmoff,
5425 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5426 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5427 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5428 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5429 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5430 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5431 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5432 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5433 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5434 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5435 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5436 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5437};
5438
5439static const int kvm_vmx_max_exit_handlers =
50a3485c 5440 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5441
644d711a
NHE		 5442/*
5443 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5444 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5445 * disinterest in the current event (read or write a specific MSR) by using an
5446 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5447 */
5448static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5449 struct vmcs12 *vmcs12, u32 exit_reason)
5450{
5451 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5452 gpa_t bitmap;
5453
5454 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5455 return 1;
5456
5457 /*
5458 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5459 * for the four combinations of read/write and low/high MSR numbers.
5460 * First we need to figure out which of the four to use:
5461 */
5462 bitmap = vmcs12->msr_bitmap;
5463 if (exit_reason == EXIT_REASON_MSR_WRITE)
5464 bitmap += 2048;
5465 if (msr_index >= 0xc0000000) {
5466 msr_index -= 0xc0000000;
5467 bitmap += 1024;
5468 }
5469
5470 /* Then read the msr_index'th bit from this bitmap: */
5471 if (msr_index < 1024*8) {
5472 unsigned char b;
5473 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5474 return 1 & (b >> (msr_index & 7));
5475 } else
5476 return 1; /* let L1 handle the wrong parameter */
5477}
5478
5479/*
5480 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5481 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5482 * intercept (via guest_host_mask etc.) the current event.
5483 */
5484static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5485 struct vmcs12 *vmcs12)
5486{
5487 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5488 int cr = exit_qualification & 15;
5489 int reg = (exit_qualification >> 8) & 15;
5490 unsigned long val = kvm_register_read(vcpu, reg);
5491
5492 switch ((exit_qualification >> 4) & 3) {
5493 case 0: /* mov to cr */
5494 switch (cr) {
5495 case 0:
5496 if (vmcs12->cr0_guest_host_mask &
5497 (val ^ vmcs12->cr0_read_shadow))
5498 return 1;
5499 break;
5500 case 3:
5501 if ((vmcs12->cr3_target_count >= 1 &&
5502 vmcs12->cr3_target_value0 == val) ||
5503 (vmcs12->cr3_target_count >= 2 &&
5504 vmcs12->cr3_target_value1 == val) ||
5505 (vmcs12->cr3_target_count >= 3 &&
5506 vmcs12->cr3_target_value2 == val) ||
5507 (vmcs12->cr3_target_count >= 4 &&
5508 vmcs12->cr3_target_value3 == val))
5509 return 0;
5510 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5511 return 1;
5512 break;
5513 case 4:
5514 if (vmcs12->cr4_guest_host_mask &
5515 (vmcs12->cr4_read_shadow ^ val))
5516 return 1;
5517 break;
5518 case 8:
5519 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5520 return 1;
5521 break;
5522 }
5523 break;
5524 case 2: /* clts */
5525 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5526 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5527 return 1;
5528 break;
5529 case 1: /* mov from cr */
5530 switch (cr) {
5531 case 3:
5532 if (vmcs12->cpu_based_vm_exec_control &
5533 CPU_BASED_CR3_STORE_EXITING)
5534 return 1;
5535 break;
5536 case 8:
5537 if (vmcs12->cpu_based_vm_exec_control &
5538 CPU_BASED_CR8_STORE_EXITING)
5539 return 1;
5540 break;
5541 }
5542 break;
5543 case 3: /* lmsw */
5544 /*
5545 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5546 * cr0. Other attempted changes are ignored, with no exit.
5547 */
5548 if (vmcs12->cr0_guest_host_mask & 0xe &
5549 (val ^ vmcs12->cr0_read_shadow))
5550 return 1;
5551 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5552 !(vmcs12->cr0_read_shadow & 0x1) &&
5553 (val & 0x1))
5554 return 1;
5555 break;
5556 }
5557 return 0;
5558}
5559
5560/*
5561 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5562 * should handle it ourselves in L0 (and then continue L2). Only call this
5563 * when in is_guest_mode (L2).
5564 */
5565static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5566{
5567 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5568 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5569 struct vcpu_vmx *vmx = to_vmx(vcpu);
5570 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5571
5572 if (vmx->nested.nested_run_pending)
5573 return 0;
5574
5575 if (unlikely(vmx->fail)) {
5576 printk(KERN_INFO "%s failed vm entry %x\n",
5577 __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5578 return 1;
5579 }
5580
5581 switch (exit_reason) {
5582 case EXIT_REASON_EXCEPTION_NMI:
5583 if (!is_exception(intr_info))
5584 return 0;
5585 else if (is_page_fault(intr_info))
5586 return enable_ept;
5587 return vmcs12->exception_bitmap &
5588 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5589 case EXIT_REASON_EXTERNAL_INTERRUPT:
5590 return 0;
5591 case EXIT_REASON_TRIPLE_FAULT:
5592 return 1;
5593 case EXIT_REASON_PENDING_INTERRUPT:
5594 case EXIT_REASON_NMI_WINDOW:
5595 /*
5596 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5597 * (aka Interrupt Window Exiting) only when L1 turned it on,
5598 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5599 * Same for NMI Window Exiting.
5600 */
5601 return 1;
5602 case EXIT_REASON_TASK_SWITCH:
5603 return 1;
5604 case EXIT_REASON_CPUID:
5605 return 1;
5606 case EXIT_REASON_HLT:
5607 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5608 case EXIT_REASON_INVD:
5609 return 1;
5610 case EXIT_REASON_INVLPG:
5611 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5612 case EXIT_REASON_RDPMC:
5613 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5614 case EXIT_REASON_RDTSC:
5615 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5616 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5617 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5618 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5619 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5620 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5621 /*
5622 * VMX instructions trap unconditionally. This allows L1 to
5623 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5624 */
5625 return 1;
5626 case EXIT_REASON_CR_ACCESS:
5627 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5628 case EXIT_REASON_DR_ACCESS:
5629 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5630 case EXIT_REASON_IO_INSTRUCTION:
5631 /* TODO: support IO bitmaps */
5632 return 1;
5633 case EXIT_REASON_MSR_READ:
5634 case EXIT_REASON_MSR_WRITE:
5635 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5636 case EXIT_REASON_INVALID_STATE:
5637 return 1;
5638 case EXIT_REASON_MWAIT_INSTRUCTION:
5639 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5640 case EXIT_REASON_MONITOR_INSTRUCTION:
5641 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5642 case EXIT_REASON_PAUSE_INSTRUCTION:
5643 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5644 nested_cpu_has2(vmcs12,
5645 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5646 case EXIT_REASON_MCE_DURING_VMENTRY:
5647 return 0;
5648 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5649 return 1;
5650 case EXIT_REASON_APIC_ACCESS:
5651 return nested_cpu_has2(vmcs12,
5652 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5653 case EXIT_REASON_EPT_VIOLATION:
5654 case EXIT_REASON_EPT_MISCONFIG:
5655 return 0;
5656 case EXIT_REASON_WBINVD:
5657 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5658 case EXIT_REASON_XSETBV:
5659 return 1;
5660 default:
5661 return 1;
5662 }
5663}
5664
586f9607
AK		 5665static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5666{
5667 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5668 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5669}
5670
6aa8b732
AK		 5671/*
5672 * The guest has exited. See if we can fix it or if we need userspace
5673 * assistance.
5674 */
851ba692 5675static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5676{
29bd8a78 5677 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5678 u32 exit_reason = vmx->exit_reason;
1155f76a 5679 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5680
aa17911e 5681 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 5682
80ced186
MG		 5683 /* If guest state is invalid, start emulating */
5684 if (vmx->emulation_required && emulate_invalid_guest_state)
5685 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5686
b6f1250e
NHE		 5687 /*
5688 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5689 * we did not inject a still-pending event to L1 now because of
5690 * nested_run_pending, we need to re-enable this bit.
5691 */
5692 if (vmx->nested.nested_run_pending)
5693 kvm_make_request(KVM_REQ_EVENT, vcpu);
5694
644d711a
NHE		 5695 if (exit_reason == EXIT_REASON_VMLAUNCH ||
5696 exit_reason == EXIT_REASON_VMRESUME)
5697 vmx->nested.nested_run_pending = 1;
5698 else
5699 vmx->nested.nested_run_pending = 0;
5700
5701 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5702 nested_vmx_vmexit(vcpu);
5703 return 1;
5704 }
5705
5120702e
MG		 5706 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5707 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5708 vcpu->run->fail_entry.hardware_entry_failure_reason
5709 = exit_reason;
5710 return 0;
5711 }
5712
29bd8a78 5713 if (unlikely(vmx->fail)) {
851ba692
AK		 5714 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5715 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5716 = vmcs_read32(VM_INSTRUCTION_ERROR);
5717 return 0;
5718 }
6aa8b732 5719
d77c26fc 5720 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5721 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5722 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5723 exit_reason != EXIT_REASON_TASK_SWITCH))
5724 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5725 "(0x%x) and exit reason is 0x%x\n",
5726 __func__, vectoring_info, exit_reason);
3b86cd99 5727
644d711a
NHE		 5728 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5729 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5730 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5731 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5732 vmx->soft_vnmi_blocked = 0;
3b86cd99 5733 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5734 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5735 /*
5736 * This CPU don't support us in finding the end of an
5737 * NMI-blocked window if the guest runs with IRQs
5738 * disabled. So we pull the trigger after 1 s of
5739 * futile waiting, but inform the user about this.
5740 */
5741 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5742 "state on VCPU %d after 1 s timeout\n",
5743 __func__, vcpu->vcpu_id);
5744 vmx->soft_vnmi_blocked = 0;
3b86cd99 5745 }
3b86cd99
JK		 5746 }
5747
6aa8b732
AK		 5748 if (exit_reason < kvm_vmx_max_exit_handlers
5749 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5750 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5751 else {
851ba692
AK		 5752 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5753 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5754 }
5755 return 0;
5756}
5757
95ba8273 5758static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5759{
95ba8273 5760 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5761 vmcs_write32(TPR_THRESHOLD, 0);
5762 return;
5763 }
5764
95ba8273 5765 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5766}
5767
51aa01d1 5768static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5769{
00eba012
AK		 5770 u32 exit_intr_info;
5771
5772 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5773 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5774 return;
5775
c5ca8e57 5776 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5777 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5778
5779 /* Handle machine checks before interrupts are enabled */
00eba012 5780 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5781 kvm_machine_check();
5782
20f65983 5783 /* We need to handle NMIs before interrupts are enabled */
00eba012 5784 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5785 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5786 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5787 asm("int $2");
ff9d07a0
ZY		 5788 kvm_after_handle_nmi(&vmx->vcpu);
5789 }
51aa01d1 5790}
20f65983 5791
51aa01d1
AK		 5792static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5793{
c5ca8e57 5794 u32 exit_intr_info;
51aa01d1
AK		 5795 bool unblock_nmi;
5796 u8 vector;
5797 bool idtv_info_valid;
5798
5799 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5800
cf393f75 5801 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5802 if (vmx->nmi_known_unmasked)
5803 return;
c5ca8e57
AK		 5804 /*
5805 * Can't use vmx->exit_intr_info since we're not sure what
5806 * the exit reason is.
5807 */
5808 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5809 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5810 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5811 /*
7b4a25cb 5812 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5813 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5814 * a guest IRET fault.
7b4a25cb
GN		 5815 * SDM 3: 23.2.2 (September 2008)
5816 * Bit 12 is undefined in any of the following cases:
5817 * If the VM exit sets the valid bit in the IDT-vectoring
5818 * information field.
5819 * If the VM exit is due to a double fault.
cf393f75 5820 */
7b4a25cb
GN		 5821 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5822 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5823 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5824 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5825 else
5826 vmx->nmi_known_unmasked =
5827 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5828 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5829 } else if (unlikely(vmx->soft_vnmi_blocked))
5830 vmx->vnmi_blocked_time +=
5831 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5832}
5833
83422e17
AK		 5834static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5835 u32 idt_vectoring_info,
5836 int instr_len_field,
5837 int error_code_field)
51aa01d1 5838{
51aa01d1
AK		 5839 u8 vector;
5840 int type;
5841 bool idtv_info_valid;
5842
5843 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5844
37b96e98
GN		 5845 vmx->vcpu.arch.nmi_injected = false;
5846 kvm_clear_exception_queue(&vmx->vcpu);
5847 kvm_clear_interrupt_queue(&vmx->vcpu);
5848
5849 if (!idtv_info_valid)
5850 return;
5851
3842d135
AK		 5852 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5853
668f612f
AK		 5854 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5855 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 5856
64a7ec06 5857 switch (type) {
37b96e98
GN		 5858 case INTR_TYPE_NMI_INTR:
5859 vmx->vcpu.arch.nmi_injected = true;
668f612f 5860 /*
7b4a25cb 5861 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 5862 * Clear bit "block by NMI" before VM entry if a NMI
5863 * delivery faulted.
668f612f 5864 */
654f06fc 5865 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 5866 break;
37b96e98 5867 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 5868 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5869 vmcs_read32(instr_len_field);
66fd3f7f
GN		 5870 /* fall through */
5871 case INTR_TYPE_HARD_EXCEPTION:
35920a35 5872 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 5873 u32 err = vmcs_read32(error_code_field);
37b96e98 5874 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 5875 } else
5876 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 5877 break;
66fd3f7f
GN		 5878 case INTR_TYPE_SOFT_INTR:
5879 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5880 vmcs_read32(instr_len_field);
66fd3f7f 5881 /* fall through */
37b96e98 5882 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 5883 kvm_queue_interrupt(&vmx->vcpu, vector,
5884 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 5885 break;
5886 default:
5887 break;
f7d9238f 5888 }
cf393f75
AK		 5889}
5890
83422e17
AK		 5891static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5892{
66c78ae4
NHE		 5893 if (is_guest_mode(&vmx->vcpu))
5894 return;
83422e17
AK		 5895 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5896 VM_EXIT_INSTRUCTION_LEN,
5897 IDT_VECTORING_ERROR_CODE);
5898}
5899
b463a6f7
AK		 5900static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5901{
66c78ae4
NHE		 5902 if (is_guest_mode(vcpu))
5903 return;
b463a6f7
AK		 5904 __vmx_complete_interrupts(to_vmx(vcpu),
5905 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5906 VM_ENTRY_INSTRUCTION_LEN,
5907 VM_ENTRY_EXCEPTION_ERROR_CODE);
5908
5909 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5910}
5911
c801949d
AK		 5912#ifdef CONFIG_X86_64
5913#define R "r"
5914#define Q "q"
5915#else
5916#define R "e"
5917#define Q "l"
5918#endif
5919
a3b5ba49 5920static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 5921{
a2fa3e9f 5922 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 5923
66c78ae4
NHE		 5924 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
5925 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5926 if (vmcs12->idt_vectoring_info_field &
5927 VECTORING_INFO_VALID_MASK) {
5928 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5929 vmcs12->idt_vectoring_info_field);
5930 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5931 vmcs12->vm_exit_instruction_len);
5932 if (vmcs12->idt_vectoring_info_field &
5933 VECTORING_INFO_DELIVER_CODE_MASK)
5934 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5935 vmcs12->idt_vectoring_error_code);
5936 }
5937 }
5938
104f226b
AK		 5939 /* Record the guest's net vcpu time for enforced NMI injections. */
5940 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5941 vmx->entry_time = ktime_get();
5942
5943 /* Don't enter VMX if guest state is invalid, let the exit handler
5944 start emulation until we arrive back to a valid state */
5945 if (vmx->emulation_required && emulate_invalid_guest_state)
5946 return;
5947
5948 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5949 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5950 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5951 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5952
5953 /* When single-stepping over STI and MOV SS, we must clear the
5954 * corresponding interruptibility bits in the guest state. Otherwise
5955 * vmentry fails as it then expects bit 14 (BS) in pending debug
5956 * exceptions being set, but that's not correct for the guest debugging
5957 * case. */
5958 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5959 vmx_set_interrupt_shadow(vcpu, 0);
5960
d462b819 5961 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 5962 asm(
6aa8b732 5963 /* Store host registers */
c801949d 5964 "push %%"R"dx; push %%"R"bp;"
40712fae 5965 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 5966 "push %%"R"cx \n\t"
313dbd49
AK		 5967 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5968 "je 1f \n\t"
5969 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 5970 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 5971 "1: \n\t"
d3edefc0
AK		 5972 /* Reload cr2 if changed */
5973 "mov %c[cr2](%0), %%"R"ax \n\t"
5974 "mov %%cr2, %%"R"dx \n\t"
5975 "cmp %%"R"ax, %%"R"dx \n\t"
5976 "je 2f \n\t"
5977 "mov %%"R"ax, %%cr2 \n\t"
5978 "2: \n\t"
6aa8b732 5979 /* Check if vmlaunch of vmresume is needed */
e08aa78a 5980 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 5981 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 5982 "mov %c[rax](%0), %%"R"ax \n\t"
5983 "mov %c[rbx](%0), %%"R"bx \n\t"
5984 "mov %c[rdx](%0), %%"R"dx \n\t"
5985 "mov %c[rsi](%0), %%"R"si \n\t"
5986 "mov %c[rdi](%0), %%"R"di \n\t"
5987 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 5988#ifdef CONFIG_X86_64
e08aa78a
AK		 5989 "mov %c[r8](%0), %%r8 \n\t"
5990 "mov %c[r9](%0), %%r9 \n\t"
5991 "mov %c[r10](%0), %%r10 \n\t"
5992 "mov %c[r11](%0), %%r11 \n\t"
5993 "mov %c[r12](%0), %%r12 \n\t"
5994 "mov %c[r13](%0), %%r13 \n\t"
5995 "mov %c[r14](%0), %%r14 \n\t"
5996 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 5997#endif
c801949d
AK		 5998 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5999
6aa8b732 6000 /* Enter guest mode */
cd2276a7 6001 "jne .Llaunched \n\t"
4ecac3fd 6002 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6003 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6004 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6005 ".Lkvm_vmx_return: "
6aa8b732 6006 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6007 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6008 "pop %0 \n\t"
c801949d
AK		 6009 "mov %%"R"ax, %c[rax](%0) \n\t"
6010 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6011 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6012 "mov %%"R"dx, %c[rdx](%0) \n\t"
6013 "mov %%"R"si, %c[rsi](%0) \n\t"
6014 "mov %%"R"di, %c[rdi](%0) \n\t"
6015 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6016#ifdef CONFIG_X86_64
e08aa78a
AK		 6017 "mov %%r8, %c[r8](%0) \n\t"
6018 "mov %%r9, %c[r9](%0) \n\t"
6019 "mov %%r10, %c[r10](%0) \n\t"
6020 "mov %%r11, %c[r11](%0) \n\t"
6021 "mov %%r12, %c[r12](%0) \n\t"
6022 "mov %%r13, %c[r13](%0) \n\t"
6023 "mov %%r14, %c[r14](%0) \n\t"
6024 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6025#endif
c801949d
AK		 6026 "mov %%cr2, %%"R"ax \n\t"
6027 "mov %%"R"ax, %c[cr2](%0) \n\t"
6028
1c696d0e 6029 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6030 "setbe %c[fail](%0) \n\t"
6031 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6032 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6033 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6034 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6035 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6036 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6037 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6038 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6039 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6040 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6041 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6042#ifdef CONFIG_X86_64
ad312c7c
ZX		 6043 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6044 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6045 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6046 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6047 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6048 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6049 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6050 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6051#endif
40712fae
AK		 6052 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6053 [wordsize]"i"(sizeof(ulong))
c2036300 6054 : "cc", "memory"
07d6f555 6055 , R"ax", R"bx", R"di", R"si"
c2036300 6056#ifdef CONFIG_X86_64
c2036300
LV		 6057 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6058#endif
6059 );
6aa8b732 6060
6de4f3ad 6061 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6062 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6063 | (1 << VCPU_EXREG_CPL)
aff48baa 6064 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6065 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6066 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6067 vcpu->arch.regs_dirty = 0;
6068
1155f76a
AK		 6069 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6070
66c78ae4
NHE		 6071 if (is_guest_mode(vcpu)) {
6072 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6073 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6074 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6075 vmcs12->idt_vectoring_error_code =
6076 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6077 vmcs12->vm_exit_instruction_len =
6078 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6079 }
6080 }
6081
d77c26fc 6082 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 6083 vmx->loaded_vmcs->launched = 1;
1b6269db 6084
51aa01d1 6085 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 6086
6087 vmx_complete_atomic_exit(vmx);
6088 vmx_recover_nmi_blocking(vmx);
cf393f75 6089 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6090}
6091
c801949d
AK		 6092#undef R
6093#undef Q
6094
6aa8b732
AK		 6095static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6096{
fb3f0f51
RR		 6097 struct vcpu_vmx *vmx = to_vmx(vcpu);
6098
cdbecfc3 6099 free_vpid(vmx);
ec378aee 6100 free_nested(vmx);
d462b819 6101 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6102 kfree(vmx->guest_msrs);
6103 kvm_vcpu_uninit(vcpu);
a4770347 6104 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6105}
6106
fb3f0f51 6107static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6108{
fb3f0f51 6109 int err;
c16f862d 6110 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6111 int cpu;
6aa8b732 6112
a2fa3e9f 6113 if (!vmx)
fb3f0f51
RR		 6114 return ERR_PTR(-ENOMEM);
6115
2384d2b3
SY		 6116 allocate_vpid(vmx);
6117
fb3f0f51
RR		 6118 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6119 if (err)
6120 goto free_vcpu;
965b58a5 6121
a2fa3e9f 6122 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6123 err = -ENOMEM;
fb3f0f51 6124 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6125 goto uninit_vcpu;
6126 }
965b58a5 6127
d462b819
NHE		 6128 vmx->loaded_vmcs = &vmx->vmcs01;
6129 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6130 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6131 goto free_msrs;
d462b819
NHE		 6132 if (!vmm_exclusive)
6133 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6134 loaded_vmcs_init(vmx->loaded_vmcs);
6135 if (!vmm_exclusive)
6136 kvm_cpu_vmxoff();
a2fa3e9f 6137
15ad7146
AK		 6138 cpu = get_cpu();
6139 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6140 vmx->vcpu.cpu = cpu;
8b9cf98c 6141 err = vmx_vcpu_setup(vmx);
fb3f0f51 6142 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6143 put_cpu();
fb3f0f51
RR		 6144 if (err)
6145 goto free_vmcs;
5e4a0b3c 6146 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6147 err = alloc_apic_access_page(kvm);
6148 if (err)
5e4a0b3c 6149 goto free_vmcs;
fb3f0f51 6150
b927a3ce
SY		 6151 if (enable_ept) {
6152 if (!kvm->arch.ept_identity_map_addr)
6153 kvm->arch.ept_identity_map_addr =
6154 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6155 err = -ENOMEM;
b7ebfb05
SY		 6156 if (alloc_identity_pagetable(kvm) != 0)
6157 goto free_vmcs;
93ea5388
GN		 6158 if (!init_rmode_identity_map(kvm))
6159 goto free_vmcs;
b927a3ce 6160 }
b7ebfb05 6161
a9d30f33
NHE		 6162 vmx->nested.current_vmptr = -1ull;
6163 vmx->nested.current_vmcs12 = NULL;
6164
fb3f0f51
RR		 6165 return &vmx->vcpu;
6166
6167free_vmcs:
d462b819 6168 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6169free_msrs:
fb3f0f51
RR		 6170 kfree(vmx->guest_msrs);
6171uninit_vcpu:
6172 kvm_vcpu_uninit(&vmx->vcpu);
6173free_vcpu:
cdbecfc3 6174 free_vpid(vmx);
a4770347 6175 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6176 return ERR_PTR(err);
6aa8b732
AK		 6177}
6178
002c7f7c
YS		 6179static void __init vmx_check_processor_compat(void *rtn)
6180{
6181 struct vmcs_config vmcs_conf;
6182
6183 *(int *)rtn = 0;
6184 if (setup_vmcs_config(&vmcs_conf) < 0)
6185 *(int *)rtn = -EIO;
6186 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6187 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6188 smp_processor_id());
6189 *(int *)rtn = -EIO;
6190 }
6191}
6192
67253af5
SY		 6193static int get_ept_level(void)
6194{
6195 return VMX_EPT_DEFAULT_GAW + 1;
6196}
6197
4b12f0de 6198static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6199{
4b12f0de
SY		 6200 u64 ret;
6201
522c68c4
SY		 6202 /* For VT-d and EPT combination
6203 * 1. MMIO: always map as UC
6204 * 2. EPT with VT-d:
6205 * a. VT-d without snooping control feature: can't guarantee the
6206 * result, try to trust guest.
6207 * b. VT-d with snooping control feature: snooping control feature of
6208 * VT-d engine can guarantee the cache correctness. Just set it
6209 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6210 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6211 * consistent with host MTRR
6212 */
4b12f0de
SY		 6213 if (is_mmio)
6214 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6215 else if (vcpu->kvm->arch.iommu_domain &&
6216 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6217 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6218 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6219 else
522c68c4 6220 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6221 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6222
6223 return ret;
64d4d521
SY		 6224}
6225
f4c9e87c
AK		 6226#define _ER(x) { EXIT_REASON_##x, #x }
6227
229456fc 6228static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 6229 _ER(EXCEPTION_NMI),
6230 _ER(EXTERNAL_INTERRUPT),
6231 _ER(TRIPLE_FAULT),
6232 _ER(PENDING_INTERRUPT),
6233 _ER(NMI_WINDOW),
6234 _ER(TASK_SWITCH),
6235 _ER(CPUID),
6236 _ER(HLT),
6237 _ER(INVLPG),
6238 _ER(RDPMC),
6239 _ER(RDTSC),
6240 _ER(VMCALL),
6241 _ER(VMCLEAR),
6242 _ER(VMLAUNCH),
6243 _ER(VMPTRLD),
6244 _ER(VMPTRST),
6245 _ER(VMREAD),
6246 _ER(VMRESUME),
6247 _ER(VMWRITE),
6248 _ER(VMOFF),
6249 _ER(VMON),
6250 _ER(CR_ACCESS),
6251 _ER(DR_ACCESS),
6252 _ER(IO_INSTRUCTION),
6253 _ER(MSR_READ),
6254 _ER(MSR_WRITE),
6255 _ER(MWAIT_INSTRUCTION),
6256 _ER(MONITOR_INSTRUCTION),
6257 _ER(PAUSE_INSTRUCTION),
6258 _ER(MCE_DURING_VMENTRY),
6259 _ER(TPR_BELOW_THRESHOLD),
6260 _ER(APIC_ACCESS),
6261 _ER(EPT_VIOLATION),
6262 _ER(EPT_MISCONFIG),
6263 _ER(WBINVD),
229456fc
MT		 6264 { -1, NULL }
6265};
6266
f4c9e87c
AK		 6267#undef _ER
6268
17cc3935 6269static int vmx_get_lpage_level(void)
344f414f 6270{
878403b7
SY		 6271 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6272 return PT_DIRECTORY_LEVEL;
6273 else
6274 /* For shadow and EPT supported 1GB page */
6275 return PT_PDPE_LEVEL;
344f414f
JR		 6276}
6277
0e851880
SY		 6278static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6279{
4e47c7a6
SY		 6280 struct kvm_cpuid_entry2 *best;
6281 struct vcpu_vmx *vmx = to_vmx(vcpu);
6282 u32 exec_control;
6283
6284 vmx->rdtscp_enabled = false;
6285 if (vmx_rdtscp_supported()) {
6286 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6287 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6288 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6289 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6290 vmx->rdtscp_enabled = true;
6291 else {
6292 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6293 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6294 exec_control);
6295 }
6296 }
6297 }
0e851880
SY		 6298}
6299
d4330ef2
JR		 6300static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6301{
7b8050f5
NHE		 6302 if (func == 1 && nested)
6303 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6304}
6305
fe3ef05c
NHE		 6306/*
6307 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6308 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6309 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6310 * guest in a way that will both be appropriate to L1's requests, and our
6311 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6312 * function also has additional necessary side-effects, like setting various
6313 * vcpu->arch fields.
6314 */
6315static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6316{
6317 struct vcpu_vmx *vmx = to_vmx(vcpu);
6318 u32 exec_control;
6319
6320 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6321 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6322 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6323 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6324 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6325 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6326 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6327 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6328 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6329 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6330 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6331 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6332 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6333 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6334 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6335 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6336 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6337 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6338 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6339 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6340 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6341 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6342 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6343 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6344 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6345 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6346 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6347 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6348 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6349 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6350 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6351 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6352 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6353 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6354 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6355 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6356
6357 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6358 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6359 vmcs12->vm_entry_intr_info_field);
6360 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6361 vmcs12->vm_entry_exception_error_code);
6362 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6363 vmcs12->vm_entry_instruction_len);
6364 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6365 vmcs12->guest_interruptibility_info);
6366 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6367 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6368 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6369 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6370 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6371 vmcs12->guest_pending_dbg_exceptions);
6372 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6373 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6374
6375 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6376
6377 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6378 (vmcs_config.pin_based_exec_ctrl |
6379 vmcs12->pin_based_vm_exec_control));
6380
6381 /*
6382 * Whether page-faults are trapped is determined by a combination of
6383 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6384 * If enable_ept, L0 doesn't care about page faults and we should
6385 * set all of these to L1's desires. However, if !enable_ept, L0 does
6386 * care about (at least some) page faults, and because it is not easy
6387 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6388 * to exit on each and every L2 page fault. This is done by setting
6389 * MASK=MATCH=0 and (see below) EB.PF=1.
6390 * Note that below we don't need special code to set EB.PF beyond the
6391 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6392 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6393 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6394 *
6395 * A problem with this approach (when !enable_ept) is that L1 may be
6396 * injected with more page faults than it asked for. This could have
6397 * caused problems, but in practice existing hypervisors don't care.
6398 * To fix this, we will need to emulate the PFEC checking (on the L1
6399 * page tables), using walk_addr(), when injecting PFs to L1.
6400 */
6401 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6402 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6403 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6404 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6405
6406 if (cpu_has_secondary_exec_ctrls()) {
6407 u32 exec_control = vmx_secondary_exec_control(vmx);
6408 if (!vmx->rdtscp_enabled)
6409 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6410 /* Take the following fields only from vmcs12 */
6411 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6412 if (nested_cpu_has(vmcs12,
6413 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6414 exec_control |= vmcs12->secondary_vm_exec_control;
6415
6416 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6417 /*
6418 * Translate L1 physical address to host physical
6419 * address for vmcs02. Keep the page pinned, so this
6420 * physical address remains valid. We keep a reference
6421 * to it so we can release it later.
6422 */
6423 if (vmx->nested.apic_access_page) /* shouldn't happen */
6424 nested_release_page(vmx->nested.apic_access_page);
6425 vmx->nested.apic_access_page =
6426 nested_get_page(vcpu, vmcs12->apic_access_addr);
6427 /*
6428 * If translation failed, no matter: This feature asks
6429 * to exit when accessing the given address, and if it
6430 * can never be accessed, this feature won't do
6431 * anything anyway.
6432 */
6433 if (!vmx->nested.apic_access_page)
6434 exec_control &=
6435 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6436 else
6437 vmcs_write64(APIC_ACCESS_ADDR,
6438 page_to_phys(vmx->nested.apic_access_page));
6439 }
6440
6441 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6442 }
6443
6444
6445 /*
6446 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6447 * Some constant fields are set here by vmx_set_constant_host_state().
6448 * Other fields are different per CPU, and will be set later when
6449 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6450 */
6451 vmx_set_constant_host_state();
6452
6453 /*
6454 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6455 * entry, but only if the current (host) sp changed from the value
6456 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6457 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6458 * here we just force the write to happen on entry.
6459 */
6460 vmx->host_rsp = 0;
6461
6462 exec_control = vmx_exec_control(vmx); /* L0's desires */
6463 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6464 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6465 exec_control &= ~CPU_BASED_TPR_SHADOW;
6466 exec_control |= vmcs12->cpu_based_vm_exec_control;
6467 /*
6468 * Merging of IO and MSR bitmaps not currently supported.
6469 * Rather, exit every time.
6470 */
6471 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6472 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6473 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6474
6475 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6476
6477 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6478 * bitwise-or of what L1 wants to trap for L2, and what we want to
6479 * trap. Note that CR0.TS also needs updating - we do this later.
6480 */
6481 update_exception_bitmap(vcpu);
6482 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6483 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6484
6485 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6486 vmcs_write32(VM_EXIT_CONTROLS,
6487 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6488 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6489 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6490
6491 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6492 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6493 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6494 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6495
6496
6497 set_cr4_guest_host_mask(vmx);
6498
6499 vmcs_write64(TSC_OFFSET,
6500 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6501
6502 if (enable_vpid) {
6503 /*
6504 * Trivially support vpid by letting L2s share their parent
6505 * L1's vpid. TODO: move to a more elaborate solution, giving
6506 * each L2 its own vpid and exposing the vpid feature to L1.
6507 */
6508 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6509 vmx_flush_tlb(vcpu);
6510 }
6511
6512 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6513 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6514 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6515 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6516 else
6517 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6518 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6519 vmx_set_efer(vcpu, vcpu->arch.efer);
6520
6521 /*
6522 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6523 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6524 * The CR0_READ_SHADOW is what L2 should have expected to read given
6525 * the specifications by L1; It's not enough to take
6526 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6527 * have more bits than L1 expected.
6528 */
6529 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6530 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6531
6532 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6533 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6534
6535 /* shadow page tables on either EPT or shadow page tables */
6536 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6537 kvm_mmu_reset_context(vcpu);
6538
6539 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6540 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6541}
6542
cd232ad0
NHE		 6543/*
6544 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6545 * for running an L2 nested guest.
6546 */
6547static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6548{
6549 struct vmcs12 *vmcs12;
6550 struct vcpu_vmx *vmx = to_vmx(vcpu);
6551 int cpu;
6552 struct loaded_vmcs *vmcs02;
6553
6554 if (!nested_vmx_check_permission(vcpu) ||
6555 !nested_vmx_check_vmcs12(vcpu))
6556 return 1;
6557
6558 skip_emulated_instruction(vcpu);
6559 vmcs12 = get_vmcs12(vcpu);
6560
7c177938
NHE		 6561 /*
6562 * The nested entry process starts with enforcing various prerequisites
6563 * on vmcs12 as required by the Intel SDM, and act appropriately when
6564 * they fail: As the SDM explains, some conditions should cause the
6565 * instruction to fail, while others will cause the instruction to seem
6566 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6567 * To speed up the normal (success) code path, we should avoid checking
6568 * for misconfigurations which will anyway be caught by the processor
6569 * when using the merged vmcs02.
6570 */
6571 if (vmcs12->launch_state == launch) {
6572 nested_vmx_failValid(vcpu,
6573 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6574 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6575 return 1;
6576 }
6577
6578 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6579 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6580 /*TODO: Also verify bits beyond physical address width are 0*/
6581 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6582 return 1;
6583 }
6584
6585 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6586 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6587 /*TODO: Also verify bits beyond physical address width are 0*/
6588 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6589 return 1;
6590 }
6591
6592 if (vmcs12->vm_entry_msr_load_count > 0 ||
6593 vmcs12->vm_exit_msr_load_count > 0 ||
6594 vmcs12->vm_exit_msr_store_count > 0) {
6595 if (printk_ratelimit())
6596 printk(KERN_WARNING
6597 "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6598 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6599 return 1;
6600 }
6601
6602 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6603 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6604 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6605 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6606 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6607 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6608 !vmx_control_verify(vmcs12->vm_exit_controls,
6609 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6610 !vmx_control_verify(vmcs12->vm_entry_controls,
6611 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6612 {
6613 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6614 return 1;
6615 }
6616
6617 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6618 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6619 nested_vmx_failValid(vcpu,
6620 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6621 return 1;
6622 }
6623
6624 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6625 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6626 nested_vmx_entry_failure(vcpu, vmcs12,
6627 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6628 return 1;
6629 }
6630 if (vmcs12->vmcs_link_pointer != -1ull) {
6631 nested_vmx_entry_failure(vcpu, vmcs12,
6632 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6633 return 1;
6634 }
6635
6636 /*
6637 * We're finally done with prerequisite checking, and can start with
6638 * the nested entry.
6639 */
6640
cd232ad0
NHE		 6641 vmcs02 = nested_get_current_vmcs02(vmx);
6642 if (!vmcs02)
6643 return -ENOMEM;
6644
6645 enter_guest_mode(vcpu);
6646
6647 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6648
6649 cpu = get_cpu();
6650 vmx->loaded_vmcs = vmcs02;
6651 vmx_vcpu_put(vcpu);
6652 vmx_vcpu_load(vcpu, cpu);
6653 vcpu->cpu = cpu;
6654 put_cpu();
6655
6656 vmcs12->launch_state = 1;
6657
6658 prepare_vmcs02(vcpu, vmcs12);
6659
6660 /*
6661 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6662 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6663 * returned as far as L1 is concerned. It will only return (and set
6664 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6665 */
6666 return 1;
6667}
6668
4704d0be
NHE		 6669/*
6670 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6671 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6672 * This function returns the new value we should put in vmcs12.guest_cr0.
6673 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6674 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6675 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6676 * didn't trap the bit, because if L1 did, so would L0).
6677 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6678 * been modified by L2, and L1 knows it. So just leave the old value of
6679 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6680 * isn't relevant, because if L0 traps this bit it can set it to anything.
6681 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6682 * changed these bits, and therefore they need to be updated, but L0
6683 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6684 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6685 */
6686static inline unsigned long
6687vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6688{
6689 return
6690 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6691 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6692 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6693 vcpu->arch.cr0_guest_owned_bits));
6694}
6695
6696static inline unsigned long
6697vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6698{
6699 return
6700 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6701 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6702 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6703 vcpu->arch.cr4_guest_owned_bits));
6704}
6705
6706/*
6707 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6708 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6709 * and this function updates it to reflect the changes to the guest state while
6710 * L2 was running (and perhaps made some exits which were handled directly by L0
6711 * without going back to L1), and to reflect the exit reason.
6712 * Note that we do not have to copy here all VMCS fields, just those that
6713 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6714 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6715 * which already writes to vmcs12 directly.
6716 */
6717void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6718{
6719 /* update guest state fields: */
6720 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6721 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6722
6723 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6724 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6725 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6726 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6727
6728 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6729 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6730 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6731 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6732 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6733 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6734 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6735 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6736 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6737 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6738 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6739 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6740 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6741 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6742 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6743 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6744 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6745 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6746 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6747 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6748 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6749 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6750 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6751 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6752 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6753 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6754 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6755 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6756 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6757 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6758 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6759 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6760 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6761 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6762 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6763 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6764
6765 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6766 vmcs12->guest_interruptibility_info =
6767 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6768 vmcs12->guest_pending_dbg_exceptions =
6769 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6770
6771 /* TODO: These cannot have changed unless we have MSR bitmaps and
6772 * the relevant bit asks not to trap the change */
6773 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6774 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6775 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6776 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6777 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6778 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6779
6780 /* update exit information fields: */
6781
6782 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6783 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6784
6785 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6786 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6787 vmcs12->idt_vectoring_info_field =
6788 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6789 vmcs12->idt_vectoring_error_code =
6790 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6791 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6792 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6793
6794 /* clear vm-entry fields which are to be cleared on exit */
6795 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6796 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6797}
6798
6799/*
6800 * A part of what we need to when the nested L2 guest exits and we want to
6801 * run its L1 parent, is to reset L1's guest state to the host state specified
6802 * in vmcs12.
6803 * This function is to be called not only on normal nested exit, but also on
6804 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6805 * Failures During or After Loading Guest State").
6806 * This function should be called when the active VMCS is L1's (vmcs01).
6807 */
6808void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6809{
6810 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6811 vcpu->arch.efer = vmcs12->host_ia32_efer;
6812 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6813 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6814 else
6815 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6816 vmx_set_efer(vcpu, vcpu->arch.efer);
6817
6818 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6819 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6820 /*
6821 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6822 * actually changed, because it depends on the current state of
6823 * fpu_active (which may have changed).
6824 * Note that vmx_set_cr0 refers to efer set above.
6825 */
6826 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6827 /*
6828 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6829 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6830 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6831 */
6832 update_exception_bitmap(vcpu);
6833 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6834 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6835
6836 /*
6837 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6838 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6839 */
6840 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6841 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6842
6843 /* shadow page tables on either EPT or shadow page tables */
6844 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6845 kvm_mmu_reset_context(vcpu);
6846
6847 if (enable_vpid) {
6848 /*
6849 * Trivially support vpid by letting L2s share their parent
6850 * L1's vpid. TODO: move to a more elaborate solution, giving
6851 * each L2 its own vpid and exposing the vpid feature to L1.
6852 */
6853 vmx_flush_tlb(vcpu);
6854 }
6855
6856
6857 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6858 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6859 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6860 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6861 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6862 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6863 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6864 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6865 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6866 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6867 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6868 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6869 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6870 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6871 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6872
6873 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6874 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6875 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6876 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6877 vmcs12->host_ia32_perf_global_ctrl);
6878}
6879
6880/*
6881 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6882 * and modify vmcs12 to make it see what it would expect to see there if
6883 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6884 */
6885static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6886{
6887 struct vcpu_vmx *vmx = to_vmx(vcpu);
6888 int cpu;
6889 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6890
6891 leave_guest_mode(vcpu);
6892 prepare_vmcs12(vcpu, vmcs12);
6893
6894 cpu = get_cpu();
6895 vmx->loaded_vmcs = &vmx->vmcs01;
6896 vmx_vcpu_put(vcpu);
6897 vmx_vcpu_load(vcpu, cpu);
6898 vcpu->cpu = cpu;
6899 put_cpu();
6900
6901 /* if no vmcs02 cache requested, remove the one we used */
6902 if (VMCS02_POOL_SIZE == 0)
6903 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6904
6905 load_vmcs12_host_state(vcpu, vmcs12);
6906
6907 /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6908 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6909
6910 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6911 vmx->host_rsp = 0;
6912
6913 /* Unpin physical memory we referred to in vmcs02 */
6914 if (vmx->nested.apic_access_page) {
6915 nested_release_page(vmx->nested.apic_access_page);
6916 vmx->nested.apic_access_page = 0;
6917 }
6918
6919 /*
6920 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6921 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6922 * success or failure flag accordingly.
6923 */
6924 if (unlikely(vmx->fail)) {
6925 vmx->fail = 0;
6926 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6927 } else
6928 nested_vmx_succeed(vcpu);
6929}
6930
7c177938
NHE		 6931/*
6932 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6933 * 23.7 "VM-entry failures during or after loading guest state" (this also
6934 * lists the acceptable exit-reason and exit-qualification parameters).
6935 * It should only be called before L2 actually succeeded to run, and when
6936 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6937 */
6938static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6939 struct vmcs12 *vmcs12,
6940 u32 reason, unsigned long qualification)
6941{
6942 load_vmcs12_host_state(vcpu, vmcs12);
6943 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6944 vmcs12->exit_qualification = qualification;
6945 nested_vmx_succeed(vcpu);
6946}
6947
8a76d7f2
JR		 6948static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6949 struct x86_instruction_info *info,
6950 enum x86_intercept_stage stage)
6951{
6952 return X86EMUL_CONTINUE;
6953}
6954
cbdd1bea 6955static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 6956 .cpu_has_kvm_support = cpu_has_kvm_support,
6957 .disabled_by_bios = vmx_disabled_by_bios,
6958 .hardware_setup = hardware_setup,
6959 .hardware_unsetup = hardware_unsetup,
002c7f7c 6960 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 6961 .hardware_enable = hardware_enable,
6962 .hardware_disable = hardware_disable,
04547156 6963 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 6964
6965 .vcpu_create = vmx_create_vcpu,
6966 .vcpu_free = vmx_free_vcpu,
04d2cc77 6967 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 6968
04d2cc77 6969 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 6970 .vcpu_load = vmx_vcpu_load,
6971 .vcpu_put = vmx_vcpu_put,
6972
6973 .set_guest_debug = set_guest_debug,
6974 .get_msr = vmx_get_msr,
6975 .set_msr = vmx_set_msr,
6976 .get_segment_base = vmx_get_segment_base,
6977 .get_segment = vmx_get_segment,
6978 .set_segment = vmx_set_segment,
2e4d2653 6979 .get_cpl = vmx_get_cpl,
6aa8b732 6980 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 6981 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 6982 .decache_cr3 = vmx_decache_cr3,
25c4c276 6983 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 6984 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 6985 .set_cr3 = vmx_set_cr3,
6986 .set_cr4 = vmx_set_cr4,
6aa8b732 6987 .set_efer = vmx_set_efer,
6aa8b732
AK		 6988 .get_idt = vmx_get_idt,
6989 .set_idt = vmx_set_idt,
6990 .get_gdt = vmx_get_gdt,
6991 .set_gdt = vmx_set_gdt,
020df079 6992 .set_dr7 = vmx_set_dr7,
5fdbf976 6993 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 6994 .get_rflags = vmx_get_rflags,
6995 .set_rflags = vmx_set_rflags,
ebcbab4c 6996 .fpu_activate = vmx_fpu_activate,
02daab21 6997 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 6998
6999 .tlb_flush = vmx_flush_tlb,
6aa8b732 7000
6aa8b732 7001 .run = vmx_vcpu_run,
6062d012 7002 .handle_exit = vmx_handle_exit,
6aa8b732 7003 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7004 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7005 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7006 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7007 .set_irq = vmx_inject_irq,
95ba8273 7008 .set_nmi = vmx_inject_nmi,
298101da 7009 .queue_exception = vmx_queue_exception,
b463a6f7 7010 .cancel_injection = vmx_cancel_injection,
78646121 7011 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7012 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7013 .get_nmi_mask = vmx_get_nmi_mask,
7014 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7015 .enable_nmi_window = enable_nmi_window,
7016 .enable_irq_window = enable_irq_window,
7017 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7018
cbc94022 7019 .set_tss_addr = vmx_set_tss_addr,
67253af5 7020 .get_tdp_level = get_ept_level,
4b12f0de 7021 .get_mt_mask = vmx_get_mt_mask,
229456fc 7022
586f9607 7023 .get_exit_info = vmx_get_exit_info,
229456fc 7024 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 7025
17cc3935 7026 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7027
7028 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7029
7030 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7031
7032 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7033
7034 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7035
4051b188 7036 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7037 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7038 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7039 .compute_tsc_offset = vmx_compute_tsc_offset,
1c97f0a0
JR		 7040
7041 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7042
7043 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7044};
7045
7046static int __init vmx_init(void)
7047{
26bb0981
AK		 7048 int r, i;
7049
7050 rdmsrl_safe(MSR_EFER, &host_efer);
7051
7052 for (i = 0; i < NR_VMX_MSR; ++i)
7053 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7054
3e7c73e9 7055 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7056 if (!vmx_io_bitmap_a)
7057 return -ENOMEM;
7058
3e7c73e9 7059 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7060 if (!vmx_io_bitmap_b) {
7061 r = -ENOMEM;
7062 goto out;
7063 }
7064
5897297b
AK		 7065 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7066 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7067 r = -ENOMEM;
7068 goto out1;
7069 }
7070
5897297b
AK		 7071 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7072 if (!vmx_msr_bitmap_longmode) {
7073 r = -ENOMEM;
7074 goto out2;
7075 }
7076
fdef3ad1
HQ		 7077 /*
7078 * Allow direct access to the PC debug port (it is often used for I/O
7079 * delays, but the vmexits simply slow things down).
7080 */
3e7c73e9
AK		 7081 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7082 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7083
3e7c73e9 7084 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7085
5897297b
AK		 7086 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7087 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7088
2384d2b3
SY		 7089 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7090
0ee75bea
AK		 7091 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7092 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7093 if (r)
5897297b 7094 goto out3;
25c5f225 7095
5897297b
AK		 7096 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7097 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7098 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7099 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7100 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7101 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7102
089d034e 7103 if (enable_ept) {
1439442c 7104 bypass_guest_pf = 0;
534e38b4 7105 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 7106 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 7107 kvm_enable_tdp();
7108 } else
7109 kvm_disable_tdp();
1439442c 7110
c7addb90
AK		 7111 if (bypass_guest_pf)
7112 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
7113
fdef3ad1
HQ		 7114 return 0;
7115
5897297b
AK		 7116out3:
7117 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7118out2:
5897297b 7119 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7120out1:
3e7c73e9 7121 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7122out:
3e7c73e9 7123 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7124 return r;
6aa8b732
AK		 7125}
7126
7127static void __exit vmx_exit(void)
7128{
5897297b
AK		 7129 free_page((unsigned long)vmx_msr_bitmap_legacy);
7130 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7131 free_page((unsigned long)vmx_io_bitmap_b);
7132 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7133
cb498ea2 7134 kvm_exit();
6aa8b732
AK		 7135}
7136
7137module_init(vmx_init)
7138module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)