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KVM: x86: properly update ready_for_interrupt_injection
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
5fdbf976 30#include "kvm_cache_regs.h"
35920a35 31#include "x86.h"
e495606d 32
6aa8b732 33#include <asm/io.h>
3b3be0d1 34#include <asm/desc.h>
13673a90 35#include <asm/vmx.h>
6210e37b 36#include <asm/virtext.h>
a0861c02 37#include <asm/mce.h>
6aa8b732 38
229456fc
MT		 39#include "trace.h"
40
4ecac3fd
AK		 41#define __ex(x) __kvm_handle_fault_on_reboot(x)
42
6aa8b732
AK		 43MODULE_AUTHOR("Qumranet");
44MODULE_LICENSE("GPL");
45
4462d21a 46static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 47module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 48
4462d21a 49static int __read_mostly enable_vpid = 1;
736caefe 50module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 51
4462d21a 52static int __read_mostly flexpriority_enabled = 1;
736caefe 53module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 54
4462d21a 55static int __read_mostly enable_ept = 1;
736caefe 56module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 57
3a624e29
NK		 58static int __read_mostly enable_unrestricted_guest = 1;
59module_param_named(unrestricted_guest,
60 enable_unrestricted_guest, bool, S_IRUGO);
61
4462d21a 62static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 63module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 64
cdc0e244
AK		 65#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
66 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
67#define KVM_GUEST_CR0_MASK \
68 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
69#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 70 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 71#define KVM_VM_CR0_ALWAYS_ON \
72 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 73#define KVM_CR4_GUEST_OWNED_BITS \
74 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
75 | X86_CR4_OSXMMEXCPT)
76
cdc0e244
AK		 77#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
78#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
79
78ac8b47
AK		 80#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
81
4b8d54f9
ZE		 82/*
83 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
84 * ple_gap: upper bound on the amount of time between two successive
85 * executions of PAUSE in a loop. Also indicate if ple enabled.
86 * According to test, this time is usually small than 41 cycles.
87 * ple_window: upper bound on the amount of time a guest is allowed to execute
88 * in a PAUSE loop. Tests indicate that most spinlocks are held for
89 * less than 2^12 cycles
90 * Time is measured based on a counter that runs at the same rate as the TSC,
91 * refer SDM volume 3b section 21.6.13 & 22.1.3.
92 */
93#define KVM_VMX_DEFAULT_PLE_GAP 41
94#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
95static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
96module_param(ple_gap, int, S_IRUGO);
97
98static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
99module_param(ple_window, int, S_IRUGO);
100
61d2ef2c
AK		 101#define NR_AUTOLOAD_MSRS 1
102
a2fa3e9f
GH		 103struct vmcs {
104 u32 revision_id;
105 u32 abort;
106 char data[0];
107};
108
26bb0981
AK		 109struct shared_msr_entry {
110 unsigned index;
111 u64 data;
d5696725 112 u64 mask;
26bb0981
AK		 113};
114
a2fa3e9f 115struct vcpu_vmx {
fb3f0f51 116 struct kvm_vcpu vcpu;
543e4243 117 struct list_head local_vcpus_link;
313dbd49 118 unsigned long host_rsp;
a2fa3e9f 119 int launched;
29bd8a78 120 u8 fail;
1155f76a 121 u32 idt_vectoring_info;
26bb0981 122 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 123 int nmsrs;
124 int save_nmsrs;
a2fa3e9f 125#ifdef CONFIG_X86_64
44ea2b17
AK		 126 u64 msr_host_kernel_gs_base;
127 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 128#endif
129 struct vmcs *vmcs;
61d2ef2c
AK		 130 struct msr_autoload {
131 unsigned nr;
132 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
133 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
134 } msr_autoload;
a2fa3e9f
GH		 135 struct {
136 int loaded;
137 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 138 int gs_ldt_reload_needed;
139 int fs_reload_needed;
d77c26fc 140 } host_state;
9c8cba37 141 struct {
7ffd92c5 142 int vm86_active;
78ac8b47 143 ulong save_rflags;
7ffd92c5
AK		 144 struct kvm_save_segment {
145 u16 selector;
146 unsigned long base;
147 u32 limit;
148 u32 ar;
149 } tr, es, ds, fs, gs;
9c8cba37
AK		 150 struct {
151 bool pending;
152 u8 vector;
153 unsigned rip;
154 } irq;
155 } rmode;
2384d2b3 156 int vpid;
04fa4d32 157 bool emulation_required;
3b86cd99
JK		 158
159 /* Support for vnmi-less CPUs */
160 int soft_vnmi_blocked;
161 ktime_t entry_time;
162 s64 vnmi_blocked_time;
a0861c02 163 u32 exit_reason;
4e47c7a6
SY		 164
165 bool rdtscp_enabled;
a2fa3e9f
GH		 166};
167
168static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
169{
fb3f0f51 170 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 171}
172
b7ebfb05 173static int init_rmode(struct kvm *kvm);
4e1096d2 174static u64 construct_eptp(unsigned long root_hpa);
75880a01 175
6aa8b732
AK		 176static DEFINE_PER_CPU(struct vmcs *, vmxarea);
177static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 178static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 179
3e7c73e9
AK		 180static unsigned long *vmx_io_bitmap_a;
181static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 182static unsigned long *vmx_msr_bitmap_legacy;
183static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 184
2384d2b3
SY		 185static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
186static DEFINE_SPINLOCK(vmx_vpid_lock);
187
1c3d14fe 188static struct vmcs_config {
6aa8b732
AK		 189 int size;
190 int order;
191 u32 revision_id;
1c3d14fe
YS		 192 u32 pin_based_exec_ctrl;
193 u32 cpu_based_exec_ctrl;
f78e0e2e 194 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 195 u32 vmexit_ctrl;
196 u32 vmentry_ctrl;
197} vmcs_config;
6aa8b732 198
efff9e53 199static struct vmx_capability {
d56f546d
SY		 200 u32 ept;
201 u32 vpid;
202} vmx_capability;
203
6aa8b732
AK		 204#define VMX_SEGMENT_FIELD(seg) \
205 [VCPU_SREG_##seg] = { \
206 .selector = GUEST_##seg##_SELECTOR, \
207 .base = GUEST_##seg##_BASE, \
208 .limit = GUEST_##seg##_LIMIT, \
209 .ar_bytes = GUEST_##seg##_AR_BYTES, \
210 }
211
212static struct kvm_vmx_segment_field {
213 unsigned selector;
214 unsigned base;
215 unsigned limit;
216 unsigned ar_bytes;
217} kvm_vmx_segment_fields[] = {
218 VMX_SEGMENT_FIELD(CS),
219 VMX_SEGMENT_FIELD(DS),
220 VMX_SEGMENT_FIELD(ES),
221 VMX_SEGMENT_FIELD(FS),
222 VMX_SEGMENT_FIELD(GS),
223 VMX_SEGMENT_FIELD(SS),
224 VMX_SEGMENT_FIELD(TR),
225 VMX_SEGMENT_FIELD(LDTR),
226};
227
26bb0981
AK		 228static u64 host_efer;
229
6de4f3ad
AK		 230static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
231
4d56c8a7
AK		 232/*
233 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
234 * away by decrementing the array size.
235 */
6aa8b732 236static const u32 vmx_msr_index[] = {
05b3e0c2 237#ifdef CONFIG_X86_64
44ea2b17 238 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 239#endif
4e47c7a6 240 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 241};
9d8f549d 242#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 243
31299944 244static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 245{
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 248 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 249}
250
31299944 251static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 252{
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 255 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 256}
257
31299944 258static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 259{
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
261 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 262 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 263}
264
31299944 265static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 266{
267 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
268 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
269}
270
31299944 271static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 272{
273 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
274 INTR_INFO_VALID_MASK)) ==
275 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
276}
277
31299944 278static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 279{
04547156 280 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 281}
282
31299944 283static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 284{
04547156 285 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 286}
287
31299944 288static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 289{
04547156 290 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 291}
292
31299944 293static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 294{
04547156
SY		 295 return vmcs_config.cpu_based_exec_ctrl &
296 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 297}
298
774ead3a 299static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 300{
04547156
SY		 301 return vmcs_config.cpu_based_2nd_exec_ctrl &
302 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
303}
304
305static inline bool cpu_has_vmx_flexpriority(void)
306{
307 return cpu_has_vmx_tpr_shadow() &&
308 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 309}
310
e799794e
MT		 311static inline bool cpu_has_vmx_ept_execute_only(void)
312{
31299944 313 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 314}
315
316static inline bool cpu_has_vmx_eptp_uncacheable(void)
317{
31299944 318 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 319}
320
321static inline bool cpu_has_vmx_eptp_writeback(void)
322{
31299944 323 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 324}
325
326static inline bool cpu_has_vmx_ept_2m_page(void)
327{
31299944 328 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 329}
330
878403b7
SY		 331static inline bool cpu_has_vmx_ept_1g_page(void)
332{
31299944 333 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 334}
335
31299944 336static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 337{
31299944 338 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 339}
340
31299944 341static inline bool cpu_has_vmx_invept_context(void)
d56f546d 342{
31299944 343 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 344}
345
31299944 346static inline bool cpu_has_vmx_invept_global(void)
d56f546d 347{
31299944 348 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 349}
350
31299944 351static inline bool cpu_has_vmx_ept(void)
d56f546d 352{
04547156
SY		 353 return vmcs_config.cpu_based_2nd_exec_ctrl &
354 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 355}
356
31299944 357static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 358{
359 return vmcs_config.cpu_based_2nd_exec_ctrl &
360 SECONDARY_EXEC_UNRESTRICTED_GUEST;
361}
362
31299944 363static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 364{
365 return vmcs_config.cpu_based_2nd_exec_ctrl &
366 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
367}
368
31299944 369static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 370{
6d3e435e 371 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 372}
373
31299944 374static inline bool cpu_has_vmx_vpid(void)
2384d2b3 375{
04547156
SY		 376 return vmcs_config.cpu_based_2nd_exec_ctrl &
377 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 378}
379
31299944 380static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 381{
382 return vmcs_config.cpu_based_2nd_exec_ctrl &
383 SECONDARY_EXEC_RDTSCP;
384}
385
31299944 386static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 387{
388 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
389}
390
04547156
SY		 391static inline bool report_flexpriority(void)
392{
393 return flexpriority_enabled;
394}
395
8b9cf98c 396static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 397{
398 int i;
399
a2fa3e9f 400 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 401 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 402 return i;
403 return -1;
404}
405
2384d2b3
SY		 406static inline void __invvpid(int ext, u16 vpid, gva_t gva)
407{
408 struct {
409 u64 vpid : 16;
410 u64 rsvd : 48;
411 u64 gva;
412 } operand = { vpid, 0, gva };
413
4ecac3fd 414 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 415 /* CF==1 or ZF==1 --> rc = -1 */
416 "; ja 1f ; ud2 ; 1:"
417 : : "a"(&operand), "c"(ext) : "cc", "memory");
418}
419
1439442c
SY		 420static inline void __invept(int ext, u64 eptp, gpa_t gpa)
421{
422 struct {
423 u64 eptp, gpa;
424 } operand = {eptp, gpa};
425
4ecac3fd 426 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 427 /* CF==1 or ZF==1 --> rc = -1 */
428 "; ja 1f ; ud2 ; 1:\n"
429 : : "a" (&operand), "c" (ext) : "cc", "memory");
430}
431
26bb0981 432static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 433{
434 int i;
435
8b9cf98c 436 i = __find_msr_index(vmx, msr);
a75beee6 437 if (i >= 0)
a2fa3e9f 438 return &vmx->guest_msrs[i];
8b6d44c7 439 return NULL;
7725f0ba
AK		 440}
441
6aa8b732
AK		 442static void vmcs_clear(struct vmcs *vmcs)
443{
444 u64 phys_addr = __pa(vmcs);
445 u8 error;
446
4ecac3fd 447 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 448 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
449 : "cc", "memory");
450 if (error)
451 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
452 vmcs, phys_addr);
453}
454
455static void __vcpu_clear(void *arg)
456{
8b9cf98c 457 struct vcpu_vmx *vmx = arg;
d3b2c338 458 int cpu = raw_smp_processor_id();
6aa8b732 459
8b9cf98c 460 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 461 vmcs_clear(vmx->vmcs);
462 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 463 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 464 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 465 list_del(&vmx->local_vcpus_link);
466 vmx->vcpu.cpu = -1;
467 vmx->launched = 0;
6aa8b732
AK		 468}
469
8b9cf98c 470static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 471{
eae5ecb5
AK		 472 if (vmx->vcpu.cpu == -1)
473 return;
8691e5a8 474 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 475}
476
2384d2b3
SY		 477static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
478{
479 if (vmx->vpid == 0)
480 return;
481
482 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
483}
484
1439442c
SY		 485static inline void ept_sync_global(void)
486{
487 if (cpu_has_vmx_invept_global())
488 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
489}
490
491static inline void ept_sync_context(u64 eptp)
492{
089d034e 493 if (enable_ept) {
1439442c
SY		 494 if (cpu_has_vmx_invept_context())
495 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
496 else
497 ept_sync_global();
498 }
499}
500
501static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
502{
089d034e 503 if (enable_ept) {
1439442c
SY		 504 if (cpu_has_vmx_invept_individual_addr())
505 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
506 eptp, gpa);
507 else
508 ept_sync_context(eptp);
509 }
510}
511
6aa8b732
AK		 512static unsigned long vmcs_readl(unsigned long field)
513{
514 unsigned long value;
515
4ecac3fd 516 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 517 : "=a"(value) : "d"(field) : "cc");
518 return value;
519}
520
521static u16 vmcs_read16(unsigned long field)
522{
523 return vmcs_readl(field);
524}
525
526static u32 vmcs_read32(unsigned long field)
527{
528 return vmcs_readl(field);
529}
530
531static u64 vmcs_read64(unsigned long field)
532{
05b3e0c2 533#ifdef CONFIG_X86_64
6aa8b732
AK		 534 return vmcs_readl(field);
535#else
536 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
537#endif
538}
539
e52de1b8
AK		 540static noinline void vmwrite_error(unsigned long field, unsigned long value)
541{
542 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
543 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
544 dump_stack();
545}
546
6aa8b732
AK		 547static void vmcs_writel(unsigned long field, unsigned long value)
548{
549 u8 error;
550
4ecac3fd 551 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 552 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 553 if (unlikely(error))
554 vmwrite_error(field, value);
6aa8b732
AK		 555}
556
557static void vmcs_write16(unsigned long field, u16 value)
558{
559 vmcs_writel(field, value);
560}
561
562static void vmcs_write32(unsigned long field, u32 value)
563{
564 vmcs_writel(field, value);
565}
566
567static void vmcs_write64(unsigned long field, u64 value)
568{
6aa8b732 569 vmcs_writel(field, value);
7682f2d0 570#ifndef CONFIG_X86_64
6aa8b732
AK		 571 asm volatile ("");
572 vmcs_writel(field+1, value >> 32);
573#endif
574}
575
2ab455cc
AL		 576static void vmcs_clear_bits(unsigned long field, u32 mask)
577{
578 vmcs_writel(field, vmcs_readl(field) & ~mask);
579}
580
581static void vmcs_set_bits(unsigned long field, u32 mask)
582{
583 vmcs_writel(field, vmcs_readl(field) | mask);
584}
585
abd3f2d6
AK		 586static void update_exception_bitmap(struct kvm_vcpu *vcpu)
587{
588 u32 eb;
589
fd7373cc
JK		 590 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
591 (1u << NM_VECTOR) | (1u << DB_VECTOR);
592 if ((vcpu->guest_debug &
593 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
594 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
595 eb |= 1u << BP_VECTOR;
7ffd92c5 596 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 597 eb = ~0;
089d034e 598 if (enable_ept)
1439442c 599 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 600 if (vcpu->fpu_active)
601 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 602 vmcs_write32(EXCEPTION_BITMAP, eb);
603}
604
61d2ef2c
AK		 605static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
606{
607 unsigned i;
608 struct msr_autoload *m = &vmx->msr_autoload;
609
610 for (i = 0; i < m->nr; ++i)
611 if (m->guest[i].index == msr)
612 break;
613
614 if (i == m->nr)
615 return;
616 --m->nr;
617 m->guest[i] = m->guest[m->nr];
618 m->host[i] = m->host[m->nr];
619 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
620 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
621}
622
623static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
624 u64 guest_val, u64 host_val)
625{
626 unsigned i;
627 struct msr_autoload *m = &vmx->msr_autoload;
628
629 for (i = 0; i < m->nr; ++i)
630 if (m->guest[i].index == msr)
631 break;
632
633 if (i == m->nr) {
634 ++m->nr;
635 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
636 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
637 }
638
639 m->guest[i].index = msr;
640 m->guest[i].value = guest_val;
641 m->host[i].index = msr;
642 m->host[i].value = host_val;
643}
644
33ed6329
AK		 645static void reload_tss(void)
646{
33ed6329
AK		 647 /*
648 * VT restores TR but not its size. Useless.
649 */
89a27f4d 650 struct desc_ptr gdt;
a5f61300 651 struct desc_struct *descs;
33ed6329 652
d6ab1ed4 653 native_store_gdt(&gdt);
89a27f4d 654 descs = (void *)gdt.address;
33ed6329
AK		 655 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
656 load_TR_desc();
33ed6329
AK		 657}
658
92c0d900 659static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 660{
3a34a881 661 u64 guest_efer;
51c6cf66
AK		 662 u64 ignore_bits;
663
f6801dff 664 guest_efer = vmx->vcpu.arch.efer;
3a34a881 665
51c6cf66
AK		 666 /*
667 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
668 * outside long mode
669 */
670 ignore_bits = EFER_NX | EFER_SCE;
671#ifdef CONFIG_X86_64
672 ignore_bits |= EFER_LMA | EFER_LME;
673 /* SCE is meaningful only in long mode on Intel */
674 if (guest_efer & EFER_LMA)
675 ignore_bits &= ~(u64)EFER_SCE;
676#endif
51c6cf66
AK		 677 guest_efer &= ~ignore_bits;
678 guest_efer |= host_efer & ignore_bits;
26bb0981 679 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 680 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 681
682 clear_atomic_switch_msr(vmx, MSR_EFER);
683 /* On ept, can't emulate nx, and must switch nx atomically */
684 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
685 guest_efer = vmx->vcpu.arch.efer;
686 if (!(guest_efer & EFER_LMA))
687 guest_efer &= ~EFER_LME;
688 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
689 return false;
690 }
691
26bb0981 692 return true;
51c6cf66
AK		 693}
694
2d49ec72
GN		 695static unsigned long segment_base(u16 selector)
696{
697 struct desc_ptr gdt;
698 struct desc_struct *d;
699 unsigned long table_base;
700 unsigned long v;
701
702 if (!(selector & ~3))
703 return 0;
704
705 native_store_gdt(&gdt);
706 table_base = gdt.address;
707
708 if (selector & 4) { /* from ldt */
709 u16 ldt_selector = kvm_read_ldt();
710
711 if (!(ldt_selector & ~3))
712 return 0;
713
714 table_base = segment_base(ldt_selector);
715 }
716 d = (struct desc_struct *)(table_base + (selector & ~7));
717 v = get_desc_base(d);
718#ifdef CONFIG_X86_64
719 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
720 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
721#endif
722 return v;
723}
724
725static inline unsigned long kvm_read_tr_base(void)
726{
727 u16 tr;
728 asm("str %0" : "=g"(tr));
729 return segment_base(tr);
730}
731
04d2cc77 732static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 733{
04d2cc77 734 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 735 int i;
04d2cc77 736
a2fa3e9f 737 if (vmx->host_state.loaded)
33ed6329
AK		 738 return;
739
a2fa3e9f 740 vmx->host_state.loaded = 1;
33ed6329
AK		 741 /*
742 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
743 * allow segment selectors with cpl > 0 or ti == 1.
744 */
d6e88aec 745 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 746 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 747 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 748 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 749 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 750 vmx->host_state.fs_reload_needed = 0;
751 } else {
33ed6329 752 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 753 vmx->host_state.fs_reload_needed = 1;
33ed6329 754 }
d6e88aec 755 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 756 if (!(vmx->host_state.gs_sel & 7))
757 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 758 else {
759 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 760 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 761 }
762
763#ifdef CONFIG_X86_64
764 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
765 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
766#else
a2fa3e9f
GH		 767 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
768 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 769#endif
707c0874
AK		 770
771#ifdef CONFIG_X86_64
44ea2b17
AK		 772 if (is_long_mode(&vmx->vcpu)) {
773 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
774 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
775 }
707c0874 776#endif
26bb0981
AK		 777 for (i = 0; i < vmx->save_nmsrs; ++i)
778 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 779 vmx->guest_msrs[i].data,
780 vmx->guest_msrs[i].mask);
33ed6329
AK		 781}
782
a9b21b62 783static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 784{
15ad7146 785 unsigned long flags;
33ed6329 786
a2fa3e9f 787 if (!vmx->host_state.loaded)
33ed6329
AK		 788 return;
789
e1beb1d3 790 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 791 vmx->host_state.loaded = 0;
152d3f2f 792 if (vmx->host_state.fs_reload_needed)
d6e88aec 793 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 794 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 795 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 796 /*
797 * If we have to reload gs, we must take care to
798 * preserve our gs base.
799 */
15ad7146 800 local_irq_save(flags);
d6e88aec 801 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 802#ifdef CONFIG_X86_64
803 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
804#endif
15ad7146 805 local_irq_restore(flags);
33ed6329 806 }
152d3f2f 807 reload_tss();
44ea2b17
AK		 808#ifdef CONFIG_X86_64
809 if (is_long_mode(&vmx->vcpu)) {
810 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
811 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
812 }
813#endif
33ed6329
AK		 814}
815
a9b21b62
AK		 816static void vmx_load_host_state(struct vcpu_vmx *vmx)
817{
818 preempt_disable();
819 __vmx_load_host_state(vmx);
820 preempt_enable();
821}
822
6aa8b732
AK		 823/*
824 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
825 * vcpu mutex is already taken.
826 */
15ad7146 827static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 828{
a2fa3e9f
GH		 829 struct vcpu_vmx *vmx = to_vmx(vcpu);
830 u64 phys_addr = __pa(vmx->vmcs);
019960ae 831 u64 tsc_this, delta, new_offset;
6aa8b732 832
a3d7f85f 833 if (vcpu->cpu != cpu) {
8b9cf98c 834 vcpu_clear(vmx);
2f599714 835 kvm_migrate_timers(vcpu);
eb5109e3 836 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 837 local_irq_disable();
838 list_add(&vmx->local_vcpus_link,
839 &per_cpu(vcpus_on_cpu, cpu));
840 local_irq_enable();
a3d7f85f 841 }
6aa8b732 842
a2fa3e9f 843 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 844 u8 error;
845
a2fa3e9f 846 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 847 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 848 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
849 : "cc");
850 if (error)
851 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 852 vmx->vmcs, phys_addr);
6aa8b732
AK		 853 }
854
855 if (vcpu->cpu != cpu) {
89a27f4d 856 struct desc_ptr dt;
6aa8b732
AK		 857 unsigned long sysenter_esp;
858
859 vcpu->cpu = cpu;
860 /*
861 * Linux uses per-cpu TSS and GDT, so set these when switching
862 * processors.
863 */
d6e88aec 864 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d6ab1ed4 865 native_store_gdt(&dt);
89a27f4d 866 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732
AK		 867
868 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
869 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 870
871 /*
872 * Make sure the time stamp counter is monotonous.
873 */
874 rdtscll(tsc_this);
019960ae
AK		 875 if (tsc_this < vcpu->arch.host_tsc) {
876 delta = vcpu->arch.host_tsc - tsc_this;
877 new_offset = vmcs_read64(TSC_OFFSET) + delta;
878 vmcs_write64(TSC_OFFSET, new_offset);
879 }
6aa8b732 880 }
6aa8b732
AK		 881}
882
883static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
884{
a9b21b62 885 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 886}
887
5fd86fcf
AK		 888static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
889{
81231c69
AK		 890 ulong cr0;
891
5fd86fcf
AK		 892 if (vcpu->fpu_active)
893 return;
894 vcpu->fpu_active = 1;
81231c69
AK		 895 cr0 = vmcs_readl(GUEST_CR0);
896 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
897 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
898 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 899 update_exception_bitmap(vcpu);
edcafe3c
AK		 900 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
901 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 902}
903
edcafe3c
AK		 904static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
905
5fd86fcf
AK		 906static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
907{
edcafe3c 908 vmx_decache_cr0_guest_bits(vcpu);
81231c69 909 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 910 update_exception_bitmap(vcpu);
edcafe3c
AK		 911 vcpu->arch.cr0_guest_owned_bits = 0;
912 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
913 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 914}
915
6aa8b732
AK		 916static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
917{
78ac8b47 918 unsigned long rflags, save_rflags;
345dcaa8
AK		 919
920 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 921 if (to_vmx(vcpu)->rmode.vm86_active) {
922 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
923 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
924 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
925 }
345dcaa8 926 return rflags;
6aa8b732
AK		 927}
928
929static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
930{
78ac8b47
AK		 931 if (to_vmx(vcpu)->rmode.vm86_active) {
932 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 933 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 934 }
6aa8b732
AK		 935 vmcs_writel(GUEST_RFLAGS, rflags);
936}
937
2809f5d2
GC		 938static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
939{
940 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
941 int ret = 0;
942
943 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 944 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 945 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 946 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 947
948 return ret & mask;
949}
950
951static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
952{
953 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
954 u32 interruptibility = interruptibility_old;
955
956 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
957
48005f64 958 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 959 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 960 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 961 interruptibility |= GUEST_INTR_STATE_STI;
962
963 if ((interruptibility != interruptibility_old))
964 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
965}
966
6aa8b732
AK		 967static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
968{
969 unsigned long rip;
6aa8b732 970
5fdbf976 971 rip = kvm_rip_read(vcpu);
6aa8b732 972 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 973 kvm_rip_write(vcpu, rip);
6aa8b732 974
2809f5d2
GC		 975 /* skipping an emulated instruction also counts */
976 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 977}
978
298101da 979static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 980 bool has_error_code, u32 error_code,
981 bool reinject)
298101da 982{
77ab6db0 983 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 984 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 985
8ab2d2e2 986 if (has_error_code) {
77ab6db0 987 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 988 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
989 }
77ab6db0 990
7ffd92c5 991 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 992 vmx->rmode.irq.pending = true;
993 vmx->rmode.irq.vector = nr;
994 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 995 if (kvm_exception_is_soft(nr))
996 vmx->rmode.irq.rip +=
997 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 998 intr_info |= INTR_TYPE_SOFT_INTR;
999 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1000 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1001 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1002 return;
1003 }
1004
66fd3f7f
GN		 1005 if (kvm_exception_is_soft(nr)) {
1006 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1007 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1008 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1009 } else
1010 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1011
1012 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1013}
1014
4e47c7a6
SY		 1015static bool vmx_rdtscp_supported(void)
1016{
1017 return cpu_has_vmx_rdtscp();
1018}
1019
a75beee6
ED		 1020/*
1021 * Swap MSR entry in host/guest MSR entry array.
1022 */
8b9cf98c 1023static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1024{
26bb0981 1025 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1026
1027 tmp = vmx->guest_msrs[to];
1028 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1029 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1030}
1031
e38aea3e
AK		 1032/*
1033 * Set up the vmcs to automatically save and restore system
1034 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1035 * mode, as fiddling with msrs is very expensive.
1036 */
8b9cf98c 1037static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1038{
26bb0981 1039 int save_nmsrs, index;
5897297b 1040 unsigned long *msr_bitmap;
e38aea3e 1041
33f9c505 1042 vmx_load_host_state(vmx);
a75beee6
ED		 1043 save_nmsrs = 0;
1044#ifdef CONFIG_X86_64
8b9cf98c 1045 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1046 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1047 if (index >= 0)
8b9cf98c
RR		 1048 move_msr_up(vmx, index, save_nmsrs++);
1049 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1050 if (index >= 0)
8b9cf98c
RR		 1051 move_msr_up(vmx, index, save_nmsrs++);
1052 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1053 if (index >= 0)
8b9cf98c 1054 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1055 index = __find_msr_index(vmx, MSR_TSC_AUX);
1056 if (index >= 0 && vmx->rdtscp_enabled)
1057 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1058 /*
1059 * MSR_K6_STAR is only needed on long mode guests, and only
1060 * if efer.sce is enabled.
1061 */
8b9cf98c 1062 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 1063 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1064 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1065 }
1066#endif
92c0d900
AK		 1067 index = __find_msr_index(vmx, MSR_EFER);
1068 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1069 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1070
26bb0981 1071 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1072
1073 if (cpu_has_vmx_msr_bitmap()) {
1074 if (is_long_mode(&vmx->vcpu))
1075 msr_bitmap = vmx_msr_bitmap_longmode;
1076 else
1077 msr_bitmap = vmx_msr_bitmap_legacy;
1078
1079 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1080 }
e38aea3e
AK		 1081}
1082
6aa8b732
AK		 1083/*
1084 * reads and returns guest's timestamp counter "register"
1085 * guest_tsc = host_tsc + tsc_offset -- 21.3
1086 */
1087static u64 guest_read_tsc(void)
1088{
1089 u64 host_tsc, tsc_offset;
1090
1091 rdtscll(host_tsc);
1092 tsc_offset = vmcs_read64(TSC_OFFSET);
1093 return host_tsc + tsc_offset;
1094}
1095
1096/*
1097 * writes 'guest_tsc' into guest's timestamp counter "register"
1098 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1099 */
53f658b3 1100static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1101{
6aa8b732
AK		 1102 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1103}
1104
6aa8b732
AK		 1105/*
1106 * Reads an msr value (of 'msr_index') into 'pdata'.
1107 * Returns 0 on success, non-0 otherwise.
1108 * Assumes vcpu_load() was already called.
1109 */
1110static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1111{
1112 u64 data;
26bb0981 1113 struct shared_msr_entry *msr;
6aa8b732
AK		 1114
1115 if (!pdata) {
1116 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1117 return -EINVAL;
1118 }
1119
1120 switch (msr_index) {
05b3e0c2 1121#ifdef CONFIG_X86_64
6aa8b732
AK		 1122 case MSR_FS_BASE:
1123 data = vmcs_readl(GUEST_FS_BASE);
1124 break;
1125 case MSR_GS_BASE:
1126 data = vmcs_readl(GUEST_GS_BASE);
1127 break;
44ea2b17
AK		 1128 case MSR_KERNEL_GS_BASE:
1129 vmx_load_host_state(to_vmx(vcpu));
1130 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1131 break;
26bb0981 1132#endif
6aa8b732 1133 case MSR_EFER:
3bab1f5d 1134 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1135 case MSR_IA32_TSC:
6aa8b732
AK		 1136 data = guest_read_tsc();
1137 break;
1138 case MSR_IA32_SYSENTER_CS:
1139 data = vmcs_read32(GUEST_SYSENTER_CS);
1140 break;
1141 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1142 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1143 break;
1144 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1145 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1146 break;
4e47c7a6
SY		 1147 case MSR_TSC_AUX:
1148 if (!to_vmx(vcpu)->rdtscp_enabled)
1149 return 1;
1150 /* Otherwise falls through */
6aa8b732 1151 default:
26bb0981 1152 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1153 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1154 if (msr) {
542423b0 1155 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1156 data = msr->data;
1157 break;
6aa8b732 1158 }
3bab1f5d 1159 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1160 }
1161
1162 *pdata = data;
1163 return 0;
1164}
1165
1166/*
1167 * Writes msr value into into the appropriate "register".
1168 * Returns 0 on success, non-0 otherwise.
1169 * Assumes vcpu_load() was already called.
1170 */
1171static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1172{
a2fa3e9f 1173 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1174 struct shared_msr_entry *msr;
53f658b3 1175 u64 host_tsc;
2cc51560
ED		 1176 int ret = 0;
1177
6aa8b732 1178 switch (msr_index) {
3bab1f5d 1179 case MSR_EFER:
a9b21b62 1180 vmx_load_host_state(vmx);
2cc51560 1181 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1182 break;
16175a79 1183#ifdef CONFIG_X86_64
6aa8b732
AK		 1184 case MSR_FS_BASE:
1185 vmcs_writel(GUEST_FS_BASE, data);
1186 break;
1187 case MSR_GS_BASE:
1188 vmcs_writel(GUEST_GS_BASE, data);
1189 break;
44ea2b17
AK		 1190 case MSR_KERNEL_GS_BASE:
1191 vmx_load_host_state(vmx);
1192 vmx->msr_guest_kernel_gs_base = data;
1193 break;
6aa8b732
AK		 1194#endif
1195 case MSR_IA32_SYSENTER_CS:
1196 vmcs_write32(GUEST_SYSENTER_CS, data);
1197 break;
1198 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1199 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1200 break;
1201 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1202 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1203 break;
af24a4e4 1204 case MSR_IA32_TSC:
53f658b3
MT		 1205 rdtscll(host_tsc);
1206 guest_write_tsc(data, host_tsc);
6aa8b732 1207 break;
468d472f
SY		 1208 case MSR_IA32_CR_PAT:
1209 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1210 vmcs_write64(GUEST_IA32_PAT, data);
1211 vcpu->arch.pat = data;
1212 break;
1213 }
4e47c7a6
SY		 1214 ret = kvm_set_msr_common(vcpu, msr_index, data);
1215 break;
1216 case MSR_TSC_AUX:
1217 if (!vmx->rdtscp_enabled)
1218 return 1;
1219 /* Check reserved bit, higher 32 bits should be zero */
1220 if ((data >> 32) != 0)
1221 return 1;
1222 /* Otherwise falls through */
6aa8b732 1223 default:
8b9cf98c 1224 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1225 if (msr) {
542423b0 1226 vmx_load_host_state(vmx);
3bab1f5d
AK		 1227 msr->data = data;
1228 break;
6aa8b732 1229 }
2cc51560 1230 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1231 }
1232
2cc51560 1233 return ret;
6aa8b732
AK		 1234}
1235
5fdbf976 1236static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1237{
5fdbf976
MT		 1238 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1239 switch (reg) {
1240 case VCPU_REGS_RSP:
1241 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1242 break;
1243 case VCPU_REGS_RIP:
1244 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1245 break;
6de4f3ad
AK		 1246 case VCPU_EXREG_PDPTR:
1247 if (enable_ept)
1248 ept_save_pdptrs(vcpu);
1249 break;
5fdbf976
MT		 1250 default:
1251 break;
1252 }
6aa8b732
AK		 1253}
1254
355be0b9 1255static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1256{
ae675ef0
JK		 1257 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1258 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1259 else
1260 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1261
abd3f2d6 1262 update_exception_bitmap(vcpu);
6aa8b732
AK		 1263}
1264
1265static __init int cpu_has_kvm_support(void)
1266{
6210e37b 1267 return cpu_has_vmx();
6aa8b732
AK		 1268}
1269
1270static __init int vmx_disabled_by_bios(void)
1271{
1272 u64 msr;
1273
1274 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1275 return (msr & (FEATURE_CONTROL_LOCKED |
1276 FEATURE_CONTROL_VMXON_ENABLED))
1277 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1278 /* locked but not enabled */
6aa8b732
AK		 1279}
1280
10474ae8 1281static int hardware_enable(void *garbage)
6aa8b732
AK		 1282{
1283 int cpu = raw_smp_processor_id();
1284 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1285 u64 old;
1286
10474ae8
AG		 1287 if (read_cr4() & X86_CR4_VMXE)
1288 return -EBUSY;
1289
543e4243 1290 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1291 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1292 if ((old & (FEATURE_CONTROL_LOCKED |
1293 FEATURE_CONTROL_VMXON_ENABLED))
1294 != (FEATURE_CONTROL_LOCKED |
1295 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1296 /* enable and lock */
62b3ffb8 1297 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1298 FEATURE_CONTROL_LOCKED |
1299 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1300 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1301 asm volatile (ASM_VMX_VMXON_RAX
1302 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1303 : "memory", "cc");
10474ae8
AG		 1304
1305 ept_sync_global();
1306
1307 return 0;
6aa8b732
AK		 1308}
1309
543e4243
AK		 1310static void vmclear_local_vcpus(void)
1311{
1312 int cpu = raw_smp_processor_id();
1313 struct vcpu_vmx *vmx, *n;
1314
1315 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1316 local_vcpus_link)
1317 __vcpu_clear(vmx);
1318}
1319
710ff4a8
EH		 1320
1321/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1322 * tricks.
1323 */
1324static void kvm_cpu_vmxoff(void)
6aa8b732 1325{
4ecac3fd 1326 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1327 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1328}
1329
710ff4a8
EH		 1330static void hardware_disable(void *garbage)
1331{
1332 vmclear_local_vcpus();
1333 kvm_cpu_vmxoff();
1334}
1335
1c3d14fe 1336static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1337 u32 msr, u32 *result)
1c3d14fe
YS		 1338{
1339 u32 vmx_msr_low, vmx_msr_high;
1340 u32 ctl = ctl_min | ctl_opt;
1341
1342 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1343
1344 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1345 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1346
1347 /* Ensure minimum (required) set of control bits are supported. */
1348 if (ctl_min & ~ctl)
002c7f7c 1349 return -EIO;
1c3d14fe
YS		 1350
1351 *result = ctl;
1352 return 0;
1353}
1354
002c7f7c 1355static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1356{
1357 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1358 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1359 u32 _pin_based_exec_control = 0;
1360 u32 _cpu_based_exec_control = 0;
f78e0e2e 1361 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1362 u32 _vmexit_control = 0;
1363 u32 _vmentry_control = 0;
1364
1365 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1366 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1367 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1368 &_pin_based_exec_control) < 0)
002c7f7c 1369 return -EIO;
1c3d14fe
YS		 1370
1371 min = CPU_BASED_HLT_EXITING |
1372#ifdef CONFIG_X86_64
1373 CPU_BASED_CR8_LOAD_EXITING |
1374 CPU_BASED_CR8_STORE_EXITING |
1375#endif
d56f546d
SY		 1376 CPU_BASED_CR3_LOAD_EXITING |
1377 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1378 CPU_BASED_USE_IO_BITMAPS |
1379 CPU_BASED_MOV_DR_EXITING |
a7052897 1380 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1381 CPU_BASED_MWAIT_EXITING |
1382 CPU_BASED_MONITOR_EXITING |
a7052897 1383 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1384 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1385 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1386 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1387 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1388 &_cpu_based_exec_control) < 0)
002c7f7c 1389 return -EIO;
6e5d865c
YS		 1390#ifdef CONFIG_X86_64
1391 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1392 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1393 ~CPU_BASED_CR8_STORE_EXITING;
1394#endif
f78e0e2e 1395 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1396 min2 = 0;
1397 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1398 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1399 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1400 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1401 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1402 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1403 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1404 if (adjust_vmx_controls(min2, opt2,
1405 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1406 &_cpu_based_2nd_exec_control) < 0)
1407 return -EIO;
1408 }
1409#ifndef CONFIG_X86_64
1410 if (!(_cpu_based_2nd_exec_control &
1411 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1412 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1413#endif
d56f546d 1414 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1415 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1416 enabled */
5fff7d27
GN		 1417 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1418 CPU_BASED_CR3_STORE_EXITING |
1419 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1420 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1421 vmx_capability.ept, vmx_capability.vpid);
1422 }
1c3d14fe
YS		 1423
1424 min = 0;
1425#ifdef CONFIG_X86_64
1426 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1427#endif
468d472f 1428 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1429 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1430 &_vmexit_control) < 0)
002c7f7c 1431 return -EIO;
1c3d14fe 1432
468d472f
SY		 1433 min = 0;
1434 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1435 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1436 &_vmentry_control) < 0)
002c7f7c 1437 return -EIO;
6aa8b732 1438
c68876fd 1439 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1440
1441 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1442 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1443 return -EIO;
1c3d14fe
YS		 1444
1445#ifdef CONFIG_X86_64
1446 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1447 if (vmx_msr_high & (1u<<16))
002c7f7c 1448 return -EIO;
1c3d14fe
YS		 1449#endif
1450
1451 /* Require Write-Back (WB) memory type for VMCS accesses. */
1452 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1453 return -EIO;
1c3d14fe 1454
002c7f7c
YS		 1455 vmcs_conf->size = vmx_msr_high & 0x1fff;
1456 vmcs_conf->order = get_order(vmcs_config.size);
1457 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1458
002c7f7c
YS		 1459 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1460 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1461 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1462 vmcs_conf->vmexit_ctrl = _vmexit_control;
1463 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1464
1465 return 0;
c68876fd 1466}
6aa8b732
AK		 1467
1468static struct vmcs *alloc_vmcs_cpu(int cpu)
1469{
1470 int node = cpu_to_node(cpu);
1471 struct page *pages;
1472 struct vmcs *vmcs;
1473
6484eb3e 1474 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1475 if (!pages)
1476 return NULL;
1477 vmcs = page_address(pages);
1c3d14fe
YS		 1478 memset(vmcs, 0, vmcs_config.size);
1479 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1480 return vmcs;
1481}
1482
1483static struct vmcs *alloc_vmcs(void)
1484{
d3b2c338 1485 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1486}
1487
1488static void free_vmcs(struct vmcs *vmcs)
1489{
1c3d14fe 1490 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1491}
1492
39959588 1493static void free_kvm_area(void)
6aa8b732
AK		 1494{
1495 int cpu;
1496
3230bb47 1497 for_each_possible_cpu(cpu) {
6aa8b732 1498 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1499 per_cpu(vmxarea, cpu) = NULL;
1500 }
6aa8b732
AK		 1501}
1502
6aa8b732
AK		 1503static __init int alloc_kvm_area(void)
1504{
1505 int cpu;
1506
3230bb47 1507 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1508 struct vmcs *vmcs;
1509
1510 vmcs = alloc_vmcs_cpu(cpu);
1511 if (!vmcs) {
1512 free_kvm_area();
1513 return -ENOMEM;
1514 }
1515
1516 per_cpu(vmxarea, cpu) = vmcs;
1517 }
1518 return 0;
1519}
1520
1521static __init int hardware_setup(void)
1522{
002c7f7c
YS		 1523 if (setup_vmcs_config(&vmcs_config) < 0)
1524 return -EIO;
50a37eb4
JR		 1525
1526 if (boot_cpu_has(X86_FEATURE_NX))
1527 kvm_enable_efer_bits(EFER_NX);
1528
93ba03c2
SY		 1529 if (!cpu_has_vmx_vpid())
1530 enable_vpid = 0;
1531
3a624e29 1532 if (!cpu_has_vmx_ept()) {
93ba03c2 1533 enable_ept = 0;
3a624e29
NK		 1534 enable_unrestricted_guest = 0;
1535 }
1536
1537 if (!cpu_has_vmx_unrestricted_guest())
1538 enable_unrestricted_guest = 0;
93ba03c2
SY		 1539
1540 if (!cpu_has_vmx_flexpriority())
1541 flexpriority_enabled = 0;
1542
95ba8273
GN		 1543 if (!cpu_has_vmx_tpr_shadow())
1544 kvm_x86_ops->update_cr8_intercept = NULL;
1545
54dee993
MT		 1546 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1547 kvm_disable_largepages();
1548
4b8d54f9
ZE		 1549 if (!cpu_has_vmx_ple())
1550 ple_gap = 0;
1551
6aa8b732
AK		 1552 return alloc_kvm_area();
1553}
1554
1555static __exit void hardware_unsetup(void)
1556{
1557 free_kvm_area();
1558}
1559
6aa8b732
AK		 1560static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1561{
1562 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1563
6af11b9e 1564 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1565 vmcs_write16(sf->selector, save->selector);
1566 vmcs_writel(sf->base, save->base);
1567 vmcs_write32(sf->limit, save->limit);
1568 vmcs_write32(sf->ar_bytes, save->ar);
1569 } else {
1570 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1571 << AR_DPL_SHIFT;
1572 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1573 }
1574}
1575
1576static void enter_pmode(struct kvm_vcpu *vcpu)
1577{
1578 unsigned long flags;
a89a8fb9 1579 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1580
a89a8fb9 1581 vmx->emulation_required = 1;
7ffd92c5 1582 vmx->rmode.vm86_active = 0;
6aa8b732 1583
7ffd92c5
AK		 1584 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1585 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1586 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1587
1588 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1589 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1590 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1591 vmcs_writel(GUEST_RFLAGS, flags);
1592
66aee91a
RR		 1593 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1594 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1595
1596 update_exception_bitmap(vcpu);
1597
a89a8fb9
MG		 1598 if (emulate_invalid_guest_state)
1599 return;
1600
7ffd92c5
AK		 1601 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1602 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1603 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1604 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1605
1606 vmcs_write16(GUEST_SS_SELECTOR, 0);
1607 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1608
1609 vmcs_write16(GUEST_CS_SELECTOR,
1610 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1611 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1612}
1613
d77c26fc 1614static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1615{
bfc6d222 1616 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1617 struct kvm_memslots *slots;
1618 gfn_t base_gfn;
1619
90d83dc3 1620 slots = kvm_memslots(kvm);
bc6678a3 1621 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1622 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1623 return base_gfn << PAGE_SHIFT;
1624 }
bfc6d222 1625 return kvm->arch.tss_addr;
6aa8b732
AK		 1626}
1627
1628static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1629{
1630 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1631
1632 save->selector = vmcs_read16(sf->selector);
1633 save->base = vmcs_readl(sf->base);
1634 save->limit = vmcs_read32(sf->limit);
1635 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1636 vmcs_write16(sf->selector, save->base >> 4);
1637 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1638 vmcs_write32(sf->limit, 0xffff);
1639 vmcs_write32(sf->ar_bytes, 0xf3);
1640}
1641
1642static void enter_rmode(struct kvm_vcpu *vcpu)
1643{
1644 unsigned long flags;
a89a8fb9 1645 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1646
3a624e29
NK		 1647 if (enable_unrestricted_guest)
1648 return;
1649
a89a8fb9 1650 vmx->emulation_required = 1;
7ffd92c5 1651 vmx->rmode.vm86_active = 1;
6aa8b732 1652
7ffd92c5 1653 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1654 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1655
7ffd92c5 1656 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1657 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1658
7ffd92c5 1659 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1660 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1661
1662 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1663 vmx->rmode.save_rflags = flags;
6aa8b732 1664
053de044 1665 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1666
1667 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1668 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1669 update_exception_bitmap(vcpu);
1670
a89a8fb9
MG		 1671 if (emulate_invalid_guest_state)
1672 goto continue_rmode;
1673
6aa8b732
AK		 1674 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1675 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1676 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1677
1678 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1679 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1680 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1681 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1682 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1683
7ffd92c5
AK		 1684 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1685 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1686 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1687 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1688
a89a8fb9 1689continue_rmode:
8668a3c4 1690 kvm_mmu_reset_context(vcpu);
b7ebfb05 1691 init_rmode(vcpu->kvm);
6aa8b732
AK		 1692}
1693
401d10de
AS		 1694static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1695{
1696 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1697 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1698
1699 if (!msr)
1700 return;
401d10de 1701
44ea2b17
AK		 1702 /*
1703 * Force kernel_gs_base reloading before EFER changes, as control
1704 * of this msr depends on is_long_mode().
1705 */
1706 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1707 vcpu->arch.efer = efer;
401d10de
AS		 1708 if (efer & EFER_LMA) {
1709 vmcs_write32(VM_ENTRY_CONTROLS,
1710 vmcs_read32(VM_ENTRY_CONTROLS) |
1711 VM_ENTRY_IA32E_MODE);
1712 msr->data = efer;
1713 } else {
1714 vmcs_write32(VM_ENTRY_CONTROLS,
1715 vmcs_read32(VM_ENTRY_CONTROLS) &
1716 ~VM_ENTRY_IA32E_MODE);
1717
1718 msr->data = efer & ~EFER_LME;
1719 }
1720 setup_msrs(vmx);
1721}
1722
05b3e0c2 1723#ifdef CONFIG_X86_64
6aa8b732
AK		 1724
1725static void enter_lmode(struct kvm_vcpu *vcpu)
1726{
1727 u32 guest_tr_ar;
1728
1729 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1730 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1731 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1732 __func__);
6aa8b732
AK		 1733 vmcs_write32(GUEST_TR_AR_BYTES,
1734 (guest_tr_ar & ~AR_TYPE_MASK)
1735 | AR_TYPE_BUSY_64_TSS);
1736 }
f6801dff
AK		 1737 vcpu->arch.efer |= EFER_LMA;
1738 vmx_set_efer(vcpu, vcpu->arch.efer);
6aa8b732
AK		 1739}
1740
1741static void exit_lmode(struct kvm_vcpu *vcpu)
1742{
f6801dff 1743 vcpu->arch.efer &= ~EFER_LMA;
6aa8b732
AK		 1744
1745 vmcs_write32(VM_ENTRY_CONTROLS,
1746 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1747 & ~VM_ENTRY_IA32E_MODE);
84ad33ef 1748 vmx_set_efer(vcpu, vcpu->arch.efer);
6aa8b732
AK		 1749}
1750
1751#endif
1752
2384d2b3
SY		 1753static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1754{
1755 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1756 if (enable_ept)
4e1096d2 1757 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1758}
1759
e8467fda
AK		 1760static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1761{
1762 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1763
1764 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1765 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1766}
1767
25c4c276 1768static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1769{
fc78f519
AK		 1770 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1771
1772 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1773 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1774}
1775
1439442c
SY		 1776static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1777{
6de4f3ad
AK		 1778 if (!test_bit(VCPU_EXREG_PDPTR,
1779 (unsigned long *)&vcpu->arch.regs_dirty))
1780 return;
1781
1439442c 1782 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1783 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1784 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1785 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1786 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1787 }
1788}
1789
8f5d549f
AK		 1790static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1791{
1792 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1793 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1794 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1795 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1796 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1797 }
6de4f3ad
AK		 1798
1799 __set_bit(VCPU_EXREG_PDPTR,
1800 (unsigned long *)&vcpu->arch.regs_avail);
1801 __set_bit(VCPU_EXREG_PDPTR,
1802 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1803}
1804
1439442c
SY		 1805static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1806
1807static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1808 unsigned long cr0,
1809 struct kvm_vcpu *vcpu)
1810{
1811 if (!(cr0 & X86_CR0_PG)) {
1812 /* From paging/starting to nonpaging */
1813 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1814 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1815 (CPU_BASED_CR3_LOAD_EXITING |
1816 CPU_BASED_CR3_STORE_EXITING));
1817 vcpu->arch.cr0 = cr0;
fc78f519 1818 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1819 } else if (!is_paging(vcpu)) {
1820 /* From nonpaging to paging */
1821 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1822 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1823 ~(CPU_BASED_CR3_LOAD_EXITING |
1824 CPU_BASED_CR3_STORE_EXITING));
1825 vcpu->arch.cr0 = cr0;
fc78f519 1826 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1827 }
95eb84a7
SY		 1828
1829 if (!(cr0 & X86_CR0_WP))
1830 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1831}
1832
6aa8b732
AK		 1833static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1834{
7ffd92c5 1835 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1836 unsigned long hw_cr0;
1837
1838 if (enable_unrestricted_guest)
1839 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1840 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1841 else
1842 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1843
7ffd92c5 1844 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1845 enter_pmode(vcpu);
1846
7ffd92c5 1847 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1848 enter_rmode(vcpu);
1849
05b3e0c2 1850#ifdef CONFIG_X86_64
f6801dff 1851 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1852 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1853 enter_lmode(vcpu);
707d92fa 1854 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1855 exit_lmode(vcpu);
1856 }
1857#endif
1858
089d034e 1859 if (enable_ept)
1439442c
SY		 1860 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1861
02daab21 1862 if (!vcpu->fpu_active)
81231c69 1863 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1864
6aa8b732 1865 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1866 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1867 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1868}
1869
1439442c
SY		 1870static u64 construct_eptp(unsigned long root_hpa)
1871{
1872 u64 eptp;
1873
1874 /* TODO write the value reading from MSR */
1875 eptp = VMX_EPT_DEFAULT_MT |
1876 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1877 eptp |= (root_hpa & PAGE_MASK);
1878
1879 return eptp;
1880}
1881
6aa8b732
AK		 1882static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1883{
1439442c
SY		 1884 unsigned long guest_cr3;
1885 u64 eptp;
1886
1887 guest_cr3 = cr3;
089d034e 1888 if (enable_ept) {
1439442c
SY		 1889 eptp = construct_eptp(cr3);
1890 vmcs_write64(EPT_POINTER, eptp);
1439442c 1891 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1892 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1893 ept_load_pdptrs(vcpu);
1439442c
SY		 1894 }
1895
2384d2b3 1896 vmx_flush_tlb(vcpu);
1439442c 1897 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1898}
1899
1900static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1901{
7ffd92c5 1902 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1903 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1904
ad312c7c 1905 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1906 if (enable_ept) {
1907 if (!is_paging(vcpu)) {
1908 hw_cr4 &= ~X86_CR4_PAE;
1909 hw_cr4 |= X86_CR4_PSE;
1910 } else if (!(cr4 & X86_CR4_PAE)) {
1911 hw_cr4 &= ~X86_CR4_PAE;
1912 }
1913 }
1439442c
SY		 1914
1915 vmcs_writel(CR4_READ_SHADOW, cr4);
1916 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1917}
1918
6aa8b732
AK		 1919static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1920{
1921 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1922
1923 return vmcs_readl(sf->base);
1924}
1925
1926static void vmx_get_segment(struct kvm_vcpu *vcpu,
1927 struct kvm_segment *var, int seg)
1928{
1929 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1930 u32 ar;
1931
1932 var->base = vmcs_readl(sf->base);
1933 var->limit = vmcs_read32(sf->limit);
1934 var->selector = vmcs_read16(sf->selector);
1935 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1936 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1937 ar = 0;
1938 var->type = ar & 15;
1939 var->s = (ar >> 4) & 1;
1940 var->dpl = (ar >> 5) & 3;
1941 var->present = (ar >> 7) & 1;
1942 var->avl = (ar >> 12) & 1;
1943 var->l = (ar >> 13) & 1;
1944 var->db = (ar >> 14) & 1;
1945 var->g = (ar >> 15) & 1;
1946 var->unusable = (ar >> 16) & 1;
1947}
1948
2e4d2653
IE		 1949static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1950{
3eeb3288 1951 if (!is_protmode(vcpu))
2e4d2653
IE		 1952 return 0;
1953
1954 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1955 return 3;
1956
eab4b8aa 1957 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1958}
1959
653e3108 1960static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1961{
6aa8b732
AK		 1962 u32 ar;
1963
653e3108 1964 if (var->unusable)
6aa8b732
AK		 1965 ar = 1 << 16;
1966 else {
1967 ar = var->type & 15;
1968 ar |= (var->s & 1) << 4;
1969 ar |= (var->dpl & 3) << 5;
1970 ar |= (var->present & 1) << 7;
1971 ar |= (var->avl & 1) << 12;
1972 ar |= (var->l & 1) << 13;
1973 ar |= (var->db & 1) << 14;
1974 ar |= (var->g & 1) << 15;
1975 }
f7fbf1fd
UL		 1976 if (ar == 0) /* a 0 value means unusable */
1977 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1978
1979 return ar;
1980}
1981
1982static void vmx_set_segment(struct kvm_vcpu *vcpu,
1983 struct kvm_segment *var, int seg)
1984{
7ffd92c5 1985 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1986 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1987 u32 ar;
1988
7ffd92c5
AK		 1989 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1990 vmx->rmode.tr.selector = var->selector;
1991 vmx->rmode.tr.base = var->base;
1992 vmx->rmode.tr.limit = var->limit;
1993 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1994 return;
1995 }
1996 vmcs_writel(sf->base, var->base);
1997 vmcs_write32(sf->limit, var->limit);
1998 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1999 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2000 /*
2001 * Hack real-mode segments into vm86 compatibility.
2002 */
2003 if (var->base == 0xffff0000 && var->selector == 0xf000)
2004 vmcs_writel(sf->base, 0xf0000);
2005 ar = 0xf3;
2006 } else
2007 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2008
2009 /*
2010 * Fix the "Accessed" bit in AR field of segment registers for older
2011 * qemu binaries.
2012 * IA32 arch specifies that at the time of processor reset the
2013 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2014 * is setting it to 0 in the usedland code. This causes invalid guest
2015 * state vmexit when "unrestricted guest" mode is turned on.
2016 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2017 * tree. Newer qemu binaries with that qemu fix would not need this
2018 * kvm hack.
2019 */
2020 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2021 ar |= 0x1; /* Accessed */
2022
6aa8b732
AK		 2023 vmcs_write32(sf->ar_bytes, ar);
2024}
2025
6aa8b732
AK		 2026static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2027{
2028 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2029
2030 *db = (ar >> 14) & 1;
2031 *l = (ar >> 13) & 1;
2032}
2033
89a27f4d 2034static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2035{
89a27f4d
GN		 2036 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2037 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2038}
2039
89a27f4d 2040static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2041{
89a27f4d
GN		 2042 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2043 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2044}
2045
89a27f4d 2046static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2047{
89a27f4d
GN		 2048 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2049 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2050}
2051
89a27f4d 2052static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2053{
89a27f4d
GN		 2054 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2055 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2056}
2057
648dfaa7
MG		 2058static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2059{
2060 struct kvm_segment var;
2061 u32 ar;
2062
2063 vmx_get_segment(vcpu, &var, seg);
2064 ar = vmx_segment_access_rights(&var);
2065
2066 if (var.base != (var.selector << 4))
2067 return false;
2068 if (var.limit != 0xffff)
2069 return false;
2070 if (ar != 0xf3)
2071 return false;
2072
2073 return true;
2074}
2075
2076static bool code_segment_valid(struct kvm_vcpu *vcpu)
2077{
2078 struct kvm_segment cs;
2079 unsigned int cs_rpl;
2080
2081 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2082 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2083
1872a3f4
AK		 2084 if (cs.unusable)
2085 return false;
648dfaa7
MG		 2086 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2087 return false;
2088 if (!cs.s)
2089 return false;
1872a3f4 2090 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2091 if (cs.dpl > cs_rpl)
2092 return false;
1872a3f4 2093 } else {
648dfaa7
MG		 2094 if (cs.dpl != cs_rpl)
2095 return false;
2096 }
2097 if (!cs.present)
2098 return false;
2099
2100 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2101 return true;
2102}
2103
2104static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2105{
2106 struct kvm_segment ss;
2107 unsigned int ss_rpl;
2108
2109 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2110 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2111
1872a3f4
AK		 2112 if (ss.unusable)
2113 return true;
2114 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2115 return false;
2116 if (!ss.s)
2117 return false;
2118 if (ss.dpl != ss_rpl) /* DPL != RPL */
2119 return false;
2120 if (!ss.present)
2121 return false;
2122
2123 return true;
2124}
2125
2126static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2127{
2128 struct kvm_segment var;
2129 unsigned int rpl;
2130
2131 vmx_get_segment(vcpu, &var, seg);
2132 rpl = var.selector & SELECTOR_RPL_MASK;
2133
1872a3f4
AK		 2134 if (var.unusable)
2135 return true;
648dfaa7
MG		 2136 if (!var.s)
2137 return false;
2138 if (!var.present)
2139 return false;
2140 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2141 if (var.dpl < rpl) /* DPL < RPL */
2142 return false;
2143 }
2144
2145 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2146 * rights flags
2147 */
2148 return true;
2149}
2150
2151static bool tr_valid(struct kvm_vcpu *vcpu)
2152{
2153 struct kvm_segment tr;
2154
2155 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2156
1872a3f4
AK		 2157 if (tr.unusable)
2158 return false;
648dfaa7
MG		 2159 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2160 return false;
1872a3f4 2161 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2162 return false;
2163 if (!tr.present)
2164 return false;
2165
2166 return true;
2167}
2168
2169static bool ldtr_valid(struct kvm_vcpu *vcpu)
2170{
2171 struct kvm_segment ldtr;
2172
2173 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2174
1872a3f4
AK		 2175 if (ldtr.unusable)
2176 return true;
648dfaa7
MG		 2177 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2178 return false;
2179 if (ldtr.type != 2)
2180 return false;
2181 if (!ldtr.present)
2182 return false;
2183
2184 return true;
2185}
2186
2187static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2188{
2189 struct kvm_segment cs, ss;
2190
2191 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2192 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2193
2194 return ((cs.selector & SELECTOR_RPL_MASK) ==
2195 (ss.selector & SELECTOR_RPL_MASK));
2196}
2197
2198/*
2199 * Check if guest state is valid. Returns true if valid, false if
2200 * not.
2201 * We assume that registers are always usable
2202 */
2203static bool guest_state_valid(struct kvm_vcpu *vcpu)
2204{
2205 /* real mode guest state checks */
3eeb3288 2206 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2207 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2208 return false;
2209 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2210 return false;
2211 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2212 return false;
2213 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2214 return false;
2215 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2216 return false;
2217 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2218 return false;
2219 } else {
2220 /* protected mode guest state checks */
2221 if (!cs_ss_rpl_check(vcpu))
2222 return false;
2223 if (!code_segment_valid(vcpu))
2224 return false;
2225 if (!stack_segment_valid(vcpu))
2226 return false;
2227 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2228 return false;
2229 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2230 return false;
2231 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2232 return false;
2233 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2234 return false;
2235 if (!tr_valid(vcpu))
2236 return false;
2237 if (!ldtr_valid(vcpu))
2238 return false;
2239 }
2240 /* TODO:
2241 * - Add checks on RIP
2242 * - Add checks on RFLAGS
2243 */
2244
2245 return true;
2246}
2247
d77c26fc 2248static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2249{
6aa8b732 2250 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2251 u16 data = 0;
10589a46 2252 int ret = 0;
195aefde 2253 int r;
6aa8b732 2254
195aefde
IE		 2255 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2256 if (r < 0)
10589a46 2257 goto out;
195aefde 2258 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2259 r = kvm_write_guest_page(kvm, fn++, &data,
2260 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2261 if (r < 0)
10589a46 2262 goto out;
195aefde
IE		 2263 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2264 if (r < 0)
10589a46 2265 goto out;
195aefde
IE		 2266 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2267 if (r < 0)
10589a46 2268 goto out;
195aefde 2269 data = ~0;
10589a46
MT		 2270 r = kvm_write_guest_page(kvm, fn, &data,
2271 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2272 sizeof(u8));
195aefde 2273 if (r < 0)
10589a46
MT		 2274 goto out;
2275
2276 ret = 1;
2277out:
10589a46 2278 return ret;
6aa8b732
AK		 2279}
2280
b7ebfb05
SY		 2281static int init_rmode_identity_map(struct kvm *kvm)
2282{
2283 int i, r, ret;
2284 pfn_t identity_map_pfn;
2285 u32 tmp;
2286
089d034e 2287 if (!enable_ept)
b7ebfb05
SY		 2288 return 1;
2289 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2290 printk(KERN_ERR "EPT: identity-mapping pagetable "
2291 "haven't been allocated!\n");
2292 return 0;
2293 }
2294 if (likely(kvm->arch.ept_identity_pagetable_done))
2295 return 1;
2296 ret = 0;
b927a3ce 2297 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2298 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2299 if (r < 0)
2300 goto out;
2301 /* Set up identity-mapping pagetable for EPT in real mode */
2302 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2303 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2304 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2305 r = kvm_write_guest_page(kvm, identity_map_pfn,
2306 &tmp, i * sizeof(tmp), sizeof(tmp));
2307 if (r < 0)
2308 goto out;
2309 }
2310 kvm->arch.ept_identity_pagetable_done = true;
2311 ret = 1;
2312out:
2313 return ret;
2314}
2315
6aa8b732
AK		 2316static void seg_setup(int seg)
2317{
2318 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2319 unsigned int ar;
6aa8b732
AK		 2320
2321 vmcs_write16(sf->selector, 0);
2322 vmcs_writel(sf->base, 0);
2323 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2324 if (enable_unrestricted_guest) {
2325 ar = 0x93;
2326 if (seg == VCPU_SREG_CS)
2327 ar |= 0x08; /* code segment */
2328 } else
2329 ar = 0xf3;
2330
2331 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2332}
2333
f78e0e2e
SY		 2334static int alloc_apic_access_page(struct kvm *kvm)
2335{
2336 struct kvm_userspace_memory_region kvm_userspace_mem;
2337 int r = 0;
2338
79fac95e 2339 mutex_lock(&kvm->slots_lock);
bfc6d222 2340 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2341 goto out;
2342 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2343 kvm_userspace_mem.flags = 0;
2344 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2345 kvm_userspace_mem.memory_size = PAGE_SIZE;
2346 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2347 if (r)
2348 goto out;
72dc67a6 2349
bfc6d222 2350 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2351out:
79fac95e 2352 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2353 return r;
2354}
2355
b7ebfb05
SY		 2356static int alloc_identity_pagetable(struct kvm *kvm)
2357{
2358 struct kvm_userspace_memory_region kvm_userspace_mem;
2359 int r = 0;
2360
79fac95e 2361 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2362 if (kvm->arch.ept_identity_pagetable)
2363 goto out;
2364 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2365 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2366 kvm_userspace_mem.guest_phys_addr =
2367 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2368 kvm_userspace_mem.memory_size = PAGE_SIZE;
2369 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2370 if (r)
2371 goto out;
2372
b7ebfb05 2373 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2374 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2375out:
79fac95e 2376 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2377 return r;
2378}
2379
2384d2b3
SY		 2380static void allocate_vpid(struct vcpu_vmx *vmx)
2381{
2382 int vpid;
2383
2384 vmx->vpid = 0;
919818ab 2385 if (!enable_vpid)
2384d2b3
SY		 2386 return;
2387 spin_lock(&vmx_vpid_lock);
2388 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2389 if (vpid < VMX_NR_VPIDS) {
2390 vmx->vpid = vpid;
2391 __set_bit(vpid, vmx_vpid_bitmap);
2392 }
2393 spin_unlock(&vmx_vpid_lock);
2394}
2395
cdbecfc3
LJ		 2396static void free_vpid(struct vcpu_vmx *vmx)
2397{
2398 if (!enable_vpid)
2399 return;
2400 spin_lock(&vmx_vpid_lock);
2401 if (vmx->vpid != 0)
2402 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2403 spin_unlock(&vmx_vpid_lock);
2404}
2405
5897297b 2406static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2407{
3e7c73e9 2408 int f = sizeof(unsigned long);
25c5f225
SY		 2409
2410 if (!cpu_has_vmx_msr_bitmap())
2411 return;
2412
2413 /*
2414 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2415 * have the write-low and read-high bitmap offsets the wrong way round.
2416 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2417 */
25c5f225 2418 if (msr <= 0x1fff) {
3e7c73e9
AK		 2419 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2420 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2421 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2422 msr &= 0x1fff;
3e7c73e9
AK		 2423 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2424 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2425 }
25c5f225
SY		 2426}
2427
5897297b
AK		 2428static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2429{
2430 if (!longmode_only)
2431 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2432 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2433}
2434
6aa8b732
AK		 2435/*
2436 * Sets up the vmcs for emulated real mode.
2437 */
8b9cf98c 2438static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2439{
468d472f 2440 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2441 u32 junk;
53f658b3 2442 u64 host_pat, tsc_this, tsc_base;
6aa8b732 2443 unsigned long a;
89a27f4d 2444 struct desc_ptr dt;
6aa8b732 2445 int i;
cd2276a7 2446 unsigned long kvm_vmx_return;
6e5d865c 2447 u32 exec_control;
6aa8b732 2448
6aa8b732 2449 /* I/O */
3e7c73e9
AK		 2450 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2451 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2452
25c5f225 2453 if (cpu_has_vmx_msr_bitmap())
5897297b 2454 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2455
6aa8b732
AK		 2456 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2457
6aa8b732 2458 /* Control */
1c3d14fe
YS		 2459 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2460 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2461
2462 exec_control = vmcs_config.cpu_based_exec_ctrl;
2463 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2464 exec_control &= ~CPU_BASED_TPR_SHADOW;
2465#ifdef CONFIG_X86_64
2466 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2467 CPU_BASED_CR8_LOAD_EXITING;
2468#endif
2469 }
089d034e 2470 if (!enable_ept)
d56f546d 2471 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2472 CPU_BASED_CR3_LOAD_EXITING |
2473 CPU_BASED_INVLPG_EXITING;
6e5d865c 2474 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2475
83ff3b9d
SY		 2476 if (cpu_has_secondary_exec_ctrls()) {
2477 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2478 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2479 exec_control &=
2480 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2481 if (vmx->vpid == 0)
2482 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2483 if (!enable_ept) {
d56f546d 2484 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2485 enable_unrestricted_guest = 0;
2486 }
3a624e29
NK		 2487 if (!enable_unrestricted_guest)
2488 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2489 if (!ple_gap)
2490 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2491 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2492 }
f78e0e2e 2493
4b8d54f9
ZE		 2494 if (ple_gap) {
2495 vmcs_write32(PLE_GAP, ple_gap);
2496 vmcs_write32(PLE_WINDOW, ple_window);
2497 }
2498
c7addb90
AK		 2499 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2500 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2501 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2502
2503 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2504 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2505 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2506
2507 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2508 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2509 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2510 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2511 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2512 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2513#ifdef CONFIG_X86_64
6aa8b732
AK		 2514 rdmsrl(MSR_FS_BASE, a);
2515 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2516 rdmsrl(MSR_GS_BASE, a);
2517 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2518#else
2519 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2520 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2521#endif
2522
2523 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2524
ec68798c 2525 native_store_idt(&dt);
89a27f4d 2526 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2527
d77c26fc 2528 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2529 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2530 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2531 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2532 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2533 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2534 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2535
2536 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2537 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2538 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2539 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2540 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2541 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2542
468d472f
SY		 2543 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2544 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2545 host_pat = msr_low | ((u64) msr_high << 32);
2546 vmcs_write64(HOST_IA32_PAT, host_pat);
2547 }
2548 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2549 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2550 host_pat = msr_low | ((u64) msr_high << 32);
2551 /* Write the default value follow host pat */
2552 vmcs_write64(GUEST_IA32_PAT, host_pat);
2553 /* Keep arch.pat sync with GUEST_IA32_PAT */
2554 vmx->vcpu.arch.pat = host_pat;
2555 }
2556
6aa8b732
AK		 2557 for (i = 0; i < NR_VMX_MSR; ++i) {
2558 u32 index = vmx_msr_index[i];
2559 u32 data_low, data_high;
a2fa3e9f 2560 int j = vmx->nmsrs;
6aa8b732
AK		 2561
2562 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2563 continue;
432bd6cb
AK		 2564 if (wrmsr_safe(index, data_low, data_high) < 0)
2565 continue;
26bb0981
AK		 2566 vmx->guest_msrs[j].index = i;
2567 vmx->guest_msrs[j].data = 0;
d5696725 2568 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2569 ++vmx->nmsrs;
6aa8b732 2570 }
6aa8b732 2571
1c3d14fe 2572 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2573
2574 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2575 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2576
e00c8cf2 2577 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2578 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2579 if (enable_ept)
2580 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2581 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2582
53f658b3
MT		 2583 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2584 rdtscll(tsc_this);
2585 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2586 tsc_base = tsc_this;
2587
2588 guest_write_tsc(0, tsc_base);
f78e0e2e 2589
e00c8cf2
AK		 2590 return 0;
2591}
2592
b7ebfb05
SY		 2593static int init_rmode(struct kvm *kvm)
2594{
2595 if (!init_rmode_tss(kvm))
2596 return 0;
2597 if (!init_rmode_identity_map(kvm))
2598 return 0;
2599 return 1;
2600}
2601
e00c8cf2
AK		 2602static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2603{
2604 struct vcpu_vmx *vmx = to_vmx(vcpu);
2605 u64 msr;
f656ce01 2606 int ret, idx;
e00c8cf2 2607
5fdbf976 2608 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2609 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2610 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2611 ret = -ENOMEM;
2612 goto out;
2613 }
2614
7ffd92c5 2615 vmx->rmode.vm86_active = 0;
e00c8cf2 2616
3b86cd99
JK		 2617 vmx->soft_vnmi_blocked = 0;
2618
ad312c7c 2619 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2620 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2621 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2622 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2623 msr |= MSR_IA32_APICBASE_BSP;
2624 kvm_set_apic_base(&vmx->vcpu, msr);
2625
2626 fx_init(&vmx->vcpu);
2627
5706be0d 2628 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2629 /*
2630 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2631 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2632 */
c5af89b6 2633 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2634 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2635 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2636 } else {
ad312c7c
ZX		 2637 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2638 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2639 }
e00c8cf2
AK		 2640
2641 seg_setup(VCPU_SREG_DS);
2642 seg_setup(VCPU_SREG_ES);
2643 seg_setup(VCPU_SREG_FS);
2644 seg_setup(VCPU_SREG_GS);
2645 seg_setup(VCPU_SREG_SS);
2646
2647 vmcs_write16(GUEST_TR_SELECTOR, 0);
2648 vmcs_writel(GUEST_TR_BASE, 0);
2649 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2650 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2651
2652 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2653 vmcs_writel(GUEST_LDTR_BASE, 0);
2654 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2655 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2656
2657 vmcs_write32(GUEST_SYSENTER_CS, 0);
2658 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2659 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2660
2661 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2662 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2663 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2664 else
5fdbf976
MT		 2665 kvm_rip_write(vcpu, 0);
2666 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2667
e00c8cf2
AK		 2668 vmcs_writel(GUEST_DR7, 0x400);
2669
2670 vmcs_writel(GUEST_GDTR_BASE, 0);
2671 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2672
2673 vmcs_writel(GUEST_IDTR_BASE, 0);
2674 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2675
2676 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2677 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2678 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2679
e00c8cf2
AK		 2680 /* Special registers */
2681 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2682
2683 setup_msrs(vmx);
2684
6aa8b732
AK		 2685 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2686
f78e0e2e
SY		 2687 if (cpu_has_vmx_tpr_shadow()) {
2688 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2689 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2690 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2691 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2692 vmcs_write32(TPR_THRESHOLD, 0);
2693 }
2694
2695 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2696 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2697 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2698
2384d2b3
SY		 2699 if (vmx->vpid != 0)
2700 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2701
fa40052c 2702 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2703 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2704 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2705 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2706 vmx_fpu_activate(&vmx->vcpu);
2707 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2708
2384d2b3
SY		 2709 vpid_sync_vcpu_all(vmx);
2710
3200f405 2711 ret = 0;
6aa8b732 2712
a89a8fb9
MG		 2713 /* HACK: Don't enable emulation on guest boot/reset */
2714 vmx->emulation_required = 0;
2715
6aa8b732 2716out:
f656ce01 2717 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2718 return ret;
2719}
2720
3b86cd99
JK		 2721static void enable_irq_window(struct kvm_vcpu *vcpu)
2722{
2723 u32 cpu_based_vm_exec_control;
2724
2725 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2726 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2727 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2728}
2729
2730static void enable_nmi_window(struct kvm_vcpu *vcpu)
2731{
2732 u32 cpu_based_vm_exec_control;
2733
2734 if (!cpu_has_virtual_nmis()) {
2735 enable_irq_window(vcpu);
2736 return;
2737 }
2738
2739 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2740 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2741 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2742}
2743
66fd3f7f 2744static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2745{
9c8cba37 2746 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2747 uint32_t intr;
2748 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2749
229456fc 2750 trace_kvm_inj_virq(irq);
2714d1d3 2751
fa89a817 2752 ++vcpu->stat.irq_injections;
7ffd92c5 2753 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2754 vmx->rmode.irq.pending = true;
2755 vmx->rmode.irq.vector = irq;
5fdbf976 2756 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2757 if (vcpu->arch.interrupt.soft)
2758 vmx->rmode.irq.rip +=
2759 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2760 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2761 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2762 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2763 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2764 return;
2765 }
66fd3f7f
GN		 2766 intr = irq | INTR_INFO_VALID_MASK;
2767 if (vcpu->arch.interrupt.soft) {
2768 intr |= INTR_TYPE_SOFT_INTR;
2769 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2770 vmx->vcpu.arch.event_exit_inst_len);
2771 } else
2772 intr |= INTR_TYPE_EXT_INTR;
2773 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2774}
2775
f08864b4
SY		 2776static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2777{
66a5a347
JK		 2778 struct vcpu_vmx *vmx = to_vmx(vcpu);
2779
3b86cd99
JK		 2780 if (!cpu_has_virtual_nmis()) {
2781 /*
2782 * Tracking the NMI-blocked state in software is built upon
2783 * finding the next open IRQ window. This, in turn, depends on
2784 * well-behaving guests: They have to keep IRQs disabled at
2785 * least as long as the NMI handler runs. Otherwise we may
2786 * cause NMI nesting, maybe breaking the guest. But as this is
2787 * highly unlikely, we can live with the residual risk.
2788 */
2789 vmx->soft_vnmi_blocked = 1;
2790 vmx->vnmi_blocked_time = 0;
2791 }
2792
487b391d 2793 ++vcpu->stat.nmi_injections;
7ffd92c5 2794 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2795 vmx->rmode.irq.pending = true;
2796 vmx->rmode.irq.vector = NMI_VECTOR;
2797 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2798 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2799 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2800 INTR_INFO_VALID_MASK);
2801 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2802 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2803 return;
2804 }
f08864b4
SY		 2805 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2806 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2807}
2808
c4282df9 2809static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2810{
3b86cd99 2811 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2812 return 0;
33f089ca 2813
c4282df9
GN		 2814 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2815 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2816 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2817}
2818
3cfc3092
JK		 2819static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2820{
2821 if (!cpu_has_virtual_nmis())
2822 return to_vmx(vcpu)->soft_vnmi_blocked;
2823 else
2824 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2825 GUEST_INTR_STATE_NMI);
2826}
2827
2828static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2829{
2830 struct vcpu_vmx *vmx = to_vmx(vcpu);
2831
2832 if (!cpu_has_virtual_nmis()) {
2833 if (vmx->soft_vnmi_blocked != masked) {
2834 vmx->soft_vnmi_blocked = masked;
2835 vmx->vnmi_blocked_time = 0;
2836 }
2837 } else {
2838 if (masked)
2839 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2840 GUEST_INTR_STATE_NMI);
2841 else
2842 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2843 GUEST_INTR_STATE_NMI);
2844 }
2845}
2846
78646121
GN		 2847static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2848{
c4282df9
GN		 2849 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2850 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2851 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2852}
2853
cbc94022
IE		 2854static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2855{
2856 int ret;
2857 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2858 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2859 .guest_phys_addr = addr,
2860 .memory_size = PAGE_SIZE * 3,
2861 .flags = 0,
2862 };
2863
2864 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2865 if (ret)
2866 return ret;
bfc6d222 2867 kvm->arch.tss_addr = addr;
cbc94022
IE		 2868 return 0;
2869}
2870
6aa8b732
AK		 2871static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2872 int vec, u32 err_code)
2873{
b3f37707
NK		 2874 /*
2875 * Instruction with address size override prefix opcode 0x67
2876 * Cause the #SS fault with 0 error code in VM86 mode.
2877 */
2878 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2879 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2880 return 1;
77ab6db0
JK		 2881 /*
2882 * Forward all other exceptions that are valid in real mode.
2883 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2884 * the required debugging infrastructure rework.
2885 */
2886 switch (vec) {
77ab6db0 2887 case DB_VECTOR:
d0bfb940
JK		 2888 if (vcpu->guest_debug &
2889 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2890 return 0;
2891 kvm_queue_exception(vcpu, vec);
2892 return 1;
77ab6db0 2893 case BP_VECTOR:
c573cd22
JK		 2894 /*
2895 * Update instruction length as we may reinject the exception
2896 * from user space while in guest debugging mode.
2897 */
2898 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2899 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2901 return 0;
2902 /* fall through */
2903 case DE_VECTOR:
77ab6db0
JK		 2904 case OF_VECTOR:
2905 case BR_VECTOR:
2906 case UD_VECTOR:
2907 case DF_VECTOR:
2908 case SS_VECTOR:
2909 case GP_VECTOR:
2910 case MF_VECTOR:
2911 kvm_queue_exception(vcpu, vec);
2912 return 1;
2913 }
6aa8b732
AK		 2914 return 0;
2915}
2916
a0861c02
AK		 2917/*
2918 * Trigger machine check on the host. We assume all the MSRs are already set up
2919 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2920 * We pass a fake environment to the machine check handler because we want
2921 * the guest to be always treated like user space, no matter what context
2922 * it used internally.
2923 */
2924static void kvm_machine_check(void)
2925{
2926#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2927 struct pt_regs regs = {
2928 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2929 .flags = X86_EFLAGS_IF,
2930 };
2931
2932 do_machine_check(&regs, 0);
2933#endif
2934}
2935
851ba692 2936static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2937{
2938 /* already handled by vcpu_run */
2939 return 1;
2940}
2941
851ba692 2942static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2943{
1155f76a 2944 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2945 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2946 u32 intr_info, ex_no, error_code;
42dbaa5a 2947 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2948 u32 vect_info;
2949 enum emulation_result er;
2950
1155f76a 2951 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2952 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2953
a0861c02 2954 if (is_machine_check(intr_info))
851ba692 2955 return handle_machine_check(vcpu);
a0861c02 2956
6aa8b732 2957 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2958 !is_page_fault(intr_info)) {
2959 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2960 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2961 vcpu->run->internal.ndata = 2;
2962 vcpu->run->internal.data[0] = vect_info;
2963 vcpu->run->internal.data[1] = intr_info;
2964 return 0;
2965 }
6aa8b732 2966
e4a41889 2967 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2968 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2969
2970 if (is_no_device(intr_info)) {
5fd86fcf 2971 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2972 return 1;
2973 }
2974
7aa81cc0 2975 if (is_invalid_opcode(intr_info)) {
851ba692 2976 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2977 if (er != EMULATE_DONE)
7ee5d940 2978 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2979 return 1;
2980 }
2981
6aa8b732 2982 error_code = 0;
5fdbf976 2983 rip = kvm_rip_read(vcpu);
2e11384c 2984 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2985 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2986 if (is_page_fault(intr_info)) {
1439442c 2987 /* EPT won't cause page fault directly */
089d034e 2988 if (enable_ept)
1439442c 2989 BUG();
6aa8b732 2990 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2991 trace_kvm_page_fault(cr2, error_code);
2992
3298b75c 2993 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2994 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2995 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2996 }
2997
7ffd92c5 2998 if (vmx->rmode.vm86_active &&
6aa8b732 2999 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3000 error_code)) {
ad312c7c
ZX		 3001 if (vcpu->arch.halt_request) {
3002 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3003 return kvm_emulate_halt(vcpu);
3004 }
6aa8b732 3005 return 1;
72d6e5a0 3006 }
6aa8b732 3007
d0bfb940 3008 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3009 switch (ex_no) {
3010 case DB_VECTOR:
3011 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3012 if (!(vcpu->guest_debug &
3013 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3014 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3015 kvm_queue_exception(vcpu, DB_VECTOR);
3016 return 1;
3017 }
3018 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3019 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3020 /* fall through */
3021 case BP_VECTOR:
c573cd22
JK		 3022 /*
3023 * Update instruction length as we may reinject #BP from
3024 * user space while in guest debugging mode. Reading it for
3025 * #DB as well causes no harm, it is not used in that case.
3026 */
3027 vmx->vcpu.arch.event_exit_inst_len =
3028 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3029 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3030 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3031 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3032 break;
3033 default:
d0bfb940
JK		 3034 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3035 kvm_run->ex.exception = ex_no;
3036 kvm_run->ex.error_code = error_code;
42dbaa5a 3037 break;
6aa8b732 3038 }
6aa8b732
AK		 3039 return 0;
3040}
3041
851ba692 3042static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3043{
1165f5fe 3044 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3045 return 1;
3046}
3047
851ba692 3048static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3049{
851ba692 3050 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3051 return 0;
3052}
6aa8b732 3053
851ba692 3054static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3055{
bfdaab09 3056 unsigned long exit_qualification;
34c33d16 3057 int size, in, string;
039576c0 3058 unsigned port;
6aa8b732 3059
bfdaab09 3060 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3061 string = (exit_qualification & 16) != 0;
cf8f70bf 3062 in = (exit_qualification & 8) != 0;
e70669ab 3063
cf8f70bf 3064 ++vcpu->stat.io_exits;
e70669ab 3065
cf8f70bf
GN		 3066 if (string || in)
3067 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
e70669ab 3068
cf8f70bf
GN		 3069 port = exit_qualification >> 16;
3070 size = (exit_qualification & 7) + 1;
e93f36bc 3071 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3072
3073 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3074}
3075
102d8325
IM		 3076static void
3077vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3078{
3079 /*
3080 * Patch in the VMCALL instruction:
3081 */
3082 hypercall[0] = 0x0f;
3083 hypercall[1] = 0x01;
3084 hypercall[2] = 0xc1;
102d8325
IM		 3085}
3086
851ba692 3087static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3088{
229456fc 3089 unsigned long exit_qualification, val;
6aa8b732
AK		 3090 int cr;
3091 int reg;
3092
bfdaab09 3093 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3094 cr = exit_qualification & 15;
3095 reg = (exit_qualification >> 8) & 15;
3096 switch ((exit_qualification >> 4) & 3) {
3097 case 0: /* mov to cr */
229456fc
MT		 3098 val = kvm_register_read(vcpu, reg);
3099 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3100 switch (cr) {
3101 case 0:
229456fc 3102 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 3103 skip_emulated_instruction(vcpu);
3104 return 1;
3105 case 3:
229456fc 3106 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 3107 skip_emulated_instruction(vcpu);
3108 return 1;
3109 case 4:
229456fc 3110 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 3111 skip_emulated_instruction(vcpu);
3112 return 1;
0a5fff19
GN		 3113 case 8: {
3114 u8 cr8_prev = kvm_get_cr8(vcpu);
3115 u8 cr8 = kvm_register_read(vcpu, reg);
3116 kvm_set_cr8(vcpu, cr8);
3117 skip_emulated_instruction(vcpu);
3118 if (irqchip_in_kernel(vcpu->kvm))
3119 return 1;
3120 if (cr8_prev <= cr8)
3121 return 1;
851ba692 3122 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3123 return 0;
3124 }
6aa8b732
AK		 3125 };
3126 break;
25c4c276 3127 case 2: /* clts */
edcafe3c 3128 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3129 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3130 skip_emulated_instruction(vcpu);
6b52d186 3131 vmx_fpu_activate(vcpu);
25c4c276 3132 return 1;
6aa8b732
AK		 3133 case 1: /*mov from cr*/
3134 switch (cr) {
3135 case 3:
5fdbf976 3136 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3137 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3138 skip_emulated_instruction(vcpu);
3139 return 1;
3140 case 8:
229456fc
MT		 3141 val = kvm_get_cr8(vcpu);
3142 kvm_register_write(vcpu, reg, val);
3143 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3144 skip_emulated_instruction(vcpu);
3145 return 1;
3146 }
3147 break;
3148 case 3: /* lmsw */
a1f83a74 3149 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3150 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3151 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3152
3153 skip_emulated_instruction(vcpu);
3154 return 1;
3155 default:
3156 break;
3157 }
851ba692 3158 vcpu->run->exit_reason = 0;
f0242478 3159 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3160 (int)(exit_qualification >> 4) & 3, cr);
3161 return 0;
3162}
3163
851ba692 3164static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3165{
bfdaab09 3166 unsigned long exit_qualification;
6aa8b732
AK		 3167 int dr, reg;
3168
f2483415 3169 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3170 if (!kvm_require_cpl(vcpu, 0))
3171 return 1;
42dbaa5a
JK		 3172 dr = vmcs_readl(GUEST_DR7);
3173 if (dr & DR7_GD) {
3174 /*
3175 * As the vm-exit takes precedence over the debug trap, we
3176 * need to emulate the latter, either for the host or the
3177 * guest debugging itself.
3178 */
3179 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3180 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3181 vcpu->run->debug.arch.dr7 = dr;
3182 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3183 vmcs_readl(GUEST_CS_BASE) +
3184 vmcs_readl(GUEST_RIP);
851ba692
AK		 3185 vcpu->run->debug.arch.exception = DB_VECTOR;
3186 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3187 return 0;
3188 } else {
3189 vcpu->arch.dr7 &= ~DR7_GD;
3190 vcpu->arch.dr6 |= DR6_BD;
3191 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3192 kvm_queue_exception(vcpu, DB_VECTOR);
3193 return 1;
3194 }
3195 }
3196
bfdaab09 3197 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3198 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3199 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3200 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3201 unsigned long val;
3202 if (!kvm_get_dr(vcpu, dr, &val))
3203 kvm_register_write(vcpu, reg, val);
3204 } else
3205 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3206 skip_emulated_instruction(vcpu);
3207 return 1;
3208}
3209
020df079
GN		 3210static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3211{
3212 vmcs_writel(GUEST_DR7, val);
3213}
3214
851ba692 3215static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3216{
06465c5a
AK		 3217 kvm_emulate_cpuid(vcpu);
3218 return 1;
6aa8b732
AK		 3219}
3220
851ba692 3221static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3222{
ad312c7c 3223 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3224 u64 data;
3225
3226 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3227 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3228 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3229 return 1;
3230 }
3231
229456fc 3232 trace_kvm_msr_read(ecx, data);
2714d1d3 3233
6aa8b732 3234 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3235 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3236 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3237 skip_emulated_instruction(vcpu);
3238 return 1;
3239}
3240
851ba692 3241static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3242{
ad312c7c
ZX		 3243 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3244 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3245 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3246
3247 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3248 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3249 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3250 return 1;
3251 }
3252
59200273 3253 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3254 skip_emulated_instruction(vcpu);
3255 return 1;
3256}
3257
851ba692 3258static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3259{
3260 return 1;
3261}
3262
851ba692 3263static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3264{
85f455f7
ED		 3265 u32 cpu_based_vm_exec_control;
3266
3267 /* clear pending irq */
3268 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3269 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3270 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3271
a26bf12a 3272 ++vcpu->stat.irq_window_exits;
2714d1d3 3273
c1150d8c
DL		 3274 /*
3275 * If the user space waits to inject interrupts, exit as soon as
3276 * possible
3277 */
8061823a 3278 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3279 vcpu->run->request_interrupt_window &&
8061823a 3280 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3281 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3282 return 0;
3283 }
6aa8b732
AK		 3284 return 1;
3285}
3286
851ba692 3287static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3288{
3289 skip_emulated_instruction(vcpu);
d3bef15f 3290 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3291}
3292
851ba692 3293static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3294{
510043da 3295 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3296 kvm_emulate_hypercall(vcpu);
3297 return 1;
c21415e8
IM		 3298}
3299
851ba692 3300static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3301{
3302 kvm_queue_exception(vcpu, UD_VECTOR);
3303 return 1;
3304}
3305
851ba692 3306static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3307{
f9c617f6 3308 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3309
3310 kvm_mmu_invlpg(vcpu, exit_qualification);
3311 skip_emulated_instruction(vcpu);
3312 return 1;
3313}
3314
851ba692 3315static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3316{
3317 skip_emulated_instruction(vcpu);
3318 /* TODO: Add support for VT-d/pass-through device */
3319 return 1;
3320}
3321
851ba692 3322static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3323{
f9c617f6 3324 unsigned long exit_qualification;
f78e0e2e
SY		 3325 enum emulation_result er;
3326 unsigned long offset;
3327
f9c617f6 3328 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3329 offset = exit_qualification & 0xffful;
3330
851ba692 3331 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3332
3333 if (er != EMULATE_DONE) {
3334 printk(KERN_ERR
3335 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3336 offset);
7f582ab6 3337 return -ENOEXEC;
f78e0e2e
SY		 3338 }
3339 return 1;
3340}
3341
851ba692 3342static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3343{
60637aac 3344 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3345 unsigned long exit_qualification;
e269fb21
JK		 3346 bool has_error_code = false;
3347 u32 error_code = 0;
37817f29 3348 u16 tss_selector;
64a7ec06
GN		 3349 int reason, type, idt_v;
3350
3351 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3352 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3353
3354 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3355
3356 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3357 if (reason == TASK_SWITCH_GATE && idt_v) {
3358 switch (type) {
3359 case INTR_TYPE_NMI_INTR:
3360 vcpu->arch.nmi_injected = false;
3361 if (cpu_has_virtual_nmis())
3362 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3363 GUEST_INTR_STATE_NMI);
3364 break;
3365 case INTR_TYPE_EXT_INTR:
66fd3f7f 3366 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3367 kvm_clear_interrupt_queue(vcpu);
3368 break;
3369 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3370 if (vmx->idt_vectoring_info &
3371 VECTORING_INFO_DELIVER_CODE_MASK) {
3372 has_error_code = true;
3373 error_code =
3374 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3375 }
3376 /* fall through */
64a7ec06
GN		 3377 case INTR_TYPE_SOFT_EXCEPTION:
3378 kvm_clear_exception_queue(vcpu);
3379 break;
3380 default:
3381 break;
3382 }
60637aac 3383 }
37817f29
IE		 3384 tss_selector = exit_qualification;
3385
64a7ec06
GN		 3386 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3387 type != INTR_TYPE_EXT_INTR &&
3388 type != INTR_TYPE_NMI_INTR))
3389 skip_emulated_instruction(vcpu);
3390
acb54517
GN		 3391 if (kvm_task_switch(vcpu, tss_selector, reason,
3392 has_error_code, error_code) == EMULATE_FAIL) {
3393 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3394 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3395 vcpu->run->internal.ndata = 0;
42dbaa5a 3396 return 0;
acb54517 3397 }
42dbaa5a
JK		 3398
3399 /* clear all local breakpoint enable flags */
3400 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3401
3402 /*
3403 * TODO: What about debug traps on tss switch?
3404 * Are we supposed to inject them and update dr6?
3405 */
3406
3407 return 1;
37817f29
IE		 3408}
3409
851ba692 3410static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3411{
f9c617f6 3412 unsigned long exit_qualification;
1439442c 3413 gpa_t gpa;
1439442c 3414 int gla_validity;
1439442c 3415
f9c617f6 3416 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3417
3418 if (exit_qualification & (1 << 6)) {
3419 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3420 return -EINVAL;
1439442c
SY		 3421 }
3422
3423 gla_validity = (exit_qualification >> 7) & 0x3;
3424 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3425 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3426 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3427 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3428 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3429 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3430 (long unsigned int)exit_qualification);
851ba692
AK		 3431 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3432 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3433 return 0;
1439442c
SY		 3434 }
3435
3436 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3437 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3438 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3439}
3440
68f89400
MT		 3441static u64 ept_rsvd_mask(u64 spte, int level)
3442{
3443 int i;
3444 u64 mask = 0;
3445
3446 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3447 mask |= (1ULL << i);
3448
3449 if (level > 2)
3450 /* bits 7:3 reserved */
3451 mask |= 0xf8;
3452 else if (level == 2) {
3453 if (spte & (1ULL << 7))
3454 /* 2MB ref, bits 20:12 reserved */
3455 mask |= 0x1ff000;
3456 else
3457 /* bits 6:3 reserved */
3458 mask |= 0x78;
3459 }
3460
3461 return mask;
3462}
3463
3464static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3465 int level)
3466{
3467 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3468
3469 /* 010b (write-only) */
3470 WARN_ON((spte & 0x7) == 0x2);
3471
3472 /* 110b (write/execute) */
3473 WARN_ON((spte & 0x7) == 0x6);
3474
3475 /* 100b (execute-only) and value not supported by logical processor */
3476 if (!cpu_has_vmx_ept_execute_only())
3477 WARN_ON((spte & 0x7) == 0x4);
3478
3479 /* not 000b */
3480 if ((spte & 0x7)) {
3481 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3482
3483 if (rsvd_bits != 0) {
3484 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3485 __func__, rsvd_bits);
3486 WARN_ON(1);
3487 }
3488
3489 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3490 u64 ept_mem_type = (spte & 0x38) >> 3;
3491
3492 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3493 ept_mem_type == 7) {
3494 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3495 __func__, ept_mem_type);
3496 WARN_ON(1);
3497 }
3498 }
3499 }
3500}
3501
851ba692 3502static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3503{
3504 u64 sptes[4];
3505 int nr_sptes, i;
3506 gpa_t gpa;
3507
3508 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3509
3510 printk(KERN_ERR "EPT: Misconfiguration.\n");
3511 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3512
3513 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3514
3515 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3516 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3517
851ba692
AK		 3518 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3519 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3520
3521 return 0;
3522}
3523
851ba692 3524static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3525{
3526 u32 cpu_based_vm_exec_control;
3527
3528 /* clear pending NMI */
3529 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3530 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3531 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3532 ++vcpu->stat.nmi_window_exits;
3533
3534 return 1;
3535}
3536
80ced186 3537static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3538{
8b3079a5
AK		 3539 struct vcpu_vmx *vmx = to_vmx(vcpu);
3540 enum emulation_result err = EMULATE_DONE;
80ced186 3541 int ret = 1;
ea953ef0
MG		 3542
3543 while (!guest_state_valid(vcpu)) {
851ba692 3544 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3545
80ced186
MG		 3546 if (err == EMULATE_DO_MMIO) {
3547 ret = 0;
3548 goto out;
3549 }
1d5a4d9b
GT		 3550
3551 if (err != EMULATE_DONE) {
80ced186
MG		 3552 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3553 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3554 vcpu->run->internal.ndata = 0;
80ced186
MG		 3555 ret = 0;
3556 goto out;
ea953ef0
MG		 3557 }
3558
3559 if (signal_pending(current))
80ced186 3560 goto out;
ea953ef0
MG		 3561 if (need_resched())
3562 schedule();
3563 }
3564
80ced186
MG		 3565 vmx->emulation_required = 0;
3566out:
3567 return ret;
ea953ef0
MG		 3568}
3569
4b8d54f9
ZE		 3570/*
3571 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3572 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3573 */
9fb41ba8 3574static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3575{
3576 skip_emulated_instruction(vcpu);
3577 kvm_vcpu_on_spin(vcpu);
3578
3579 return 1;
3580}
3581
59708670
SY		 3582static int handle_invalid_op(struct kvm_vcpu *vcpu)
3583{
3584 kvm_queue_exception(vcpu, UD_VECTOR);
3585 return 1;
3586}
3587
6aa8b732
AK		 3588/*
3589 * The exit handlers return 1 if the exit was handled fully and guest execution
3590 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3591 * to be done to userspace and return 0.
3592 */
851ba692 3593static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3594 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3595 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3596 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3597 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3598 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3599 [EXIT_REASON_CR_ACCESS] = handle_cr,
3600 [EXIT_REASON_DR_ACCESS] = handle_dr,
3601 [EXIT_REASON_CPUID] = handle_cpuid,
3602 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3603 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3604 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3605 [EXIT_REASON_HLT] = handle_halt,
a7052897 3606 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3607 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3608 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3609 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3610 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3611 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3612 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3613 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3614 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3615 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3616 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3617 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3618 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3619 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3620 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3621 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3622 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3623 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3624 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3625 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3626 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3627};
3628
3629static const int kvm_vmx_max_exit_handlers =
50a3485c 3630 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3631
3632/*
3633 * The guest has exited. See if we can fix it or if we need userspace
3634 * assistance.
3635 */
851ba692 3636static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3637{
29bd8a78 3638 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3639 u32 exit_reason = vmx->exit_reason;
1155f76a 3640 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3641
5bfd8b54 3642 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3643
80ced186
MG		 3644 /* If guest state is invalid, start emulating */
3645 if (vmx->emulation_required && emulate_invalid_guest_state)
3646 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3647
1439442c
SY		 3648 /* Access CR3 don't cause VMExit in paging mode, so we need
3649 * to sync with guest real CR3. */
6de4f3ad 3650 if (enable_ept && is_paging(vcpu))
1439442c 3651 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3652
29bd8a78 3653 if (unlikely(vmx->fail)) {
851ba692
AK		 3654 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3655 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3656 = vmcs_read32(VM_INSTRUCTION_ERROR);
3657 return 0;
3658 }
6aa8b732 3659
d77c26fc 3660 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3661 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3662 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3663 exit_reason != EXIT_REASON_TASK_SWITCH))
3664 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3665 "(0x%x) and exit reason is 0x%x\n",
3666 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3667
3668 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3669 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3670 vmx->soft_vnmi_blocked = 0;
3b86cd99 3671 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3672 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3673 /*
3674 * This CPU don't support us in finding the end of an
3675 * NMI-blocked window if the guest runs with IRQs
3676 * disabled. So we pull the trigger after 1 s of
3677 * futile waiting, but inform the user about this.
3678 */
3679 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3680 "state on VCPU %d after 1 s timeout\n",
3681 __func__, vcpu->vcpu_id);
3682 vmx->soft_vnmi_blocked = 0;
3b86cd99 3683 }
3b86cd99
JK		 3684 }
3685
6aa8b732
AK		 3686 if (exit_reason < kvm_vmx_max_exit_handlers
3687 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3688 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3689 else {
851ba692
AK		 3690 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3691 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3692 }
3693 return 0;
3694}
3695
95ba8273 3696static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3697{
95ba8273 3698 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3699 vmcs_write32(TPR_THRESHOLD, 0);
3700 return;
3701 }
3702
95ba8273 3703 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3704}
3705
cf393f75
AK		 3706static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3707{
3708 u32 exit_intr_info;
7b4a25cb 3709 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3710 bool unblock_nmi;
3711 u8 vector;
668f612f
AK		 3712 int type;
3713 bool idtv_info_valid;
cf393f75
AK		 3714
3715 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3716
a0861c02
AK		 3717 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3718
3719 /* Handle machine checks before interrupts are enabled */
3720 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3721 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3722 && is_machine_check(exit_intr_info)))
3723 kvm_machine_check();
3724
20f65983
GN		 3725 /* We need to handle NMIs before interrupts are enabled */
3726 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3727 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3728 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3729 asm("int $2");
ff9d07a0
ZY		 3730 kvm_after_handle_nmi(&vmx->vcpu);
3731 }
20f65983
GN		 3732
3733 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3734
cf393f75
AK		 3735 if (cpu_has_virtual_nmis()) {
3736 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3737 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3738 /*
7b4a25cb 3739 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3740 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3741 * a guest IRET fault.
7b4a25cb
GN		 3742 * SDM 3: 23.2.2 (September 2008)
3743 * Bit 12 is undefined in any of the following cases:
3744 * If the VM exit sets the valid bit in the IDT-vectoring
3745 * information field.
3746 * If the VM exit is due to a double fault.
cf393f75 3747 */
7b4a25cb
GN		 3748 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3749 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3750 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3751 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3752 } else if (unlikely(vmx->soft_vnmi_blocked))
3753 vmx->vnmi_blocked_time +=
3754 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3755
37b96e98
GN		 3756 vmx->vcpu.arch.nmi_injected = false;
3757 kvm_clear_exception_queue(&vmx->vcpu);
3758 kvm_clear_interrupt_queue(&vmx->vcpu);
3759
3760 if (!idtv_info_valid)
3761 return;
3762
668f612f
AK		 3763 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3764 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3765
64a7ec06 3766 switch (type) {
37b96e98
GN		 3767 case INTR_TYPE_NMI_INTR:
3768 vmx->vcpu.arch.nmi_injected = true;
668f612f 3769 /*
7b4a25cb 3770 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3771 * Clear bit "block by NMI" before VM entry if a NMI
3772 * delivery faulted.
668f612f 3773 */
37b96e98
GN		 3774 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3775 GUEST_INTR_STATE_NMI);
3776 break;
37b96e98 3777 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3778 vmx->vcpu.arch.event_exit_inst_len =
3779 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3780 /* fall through */
3781 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3782 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3783 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3784 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3785 } else
3786 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3787 break;
66fd3f7f
GN		 3788 case INTR_TYPE_SOFT_INTR:
3789 vmx->vcpu.arch.event_exit_inst_len =
3790 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3791 /* fall through */
37b96e98 3792 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3793 kvm_queue_interrupt(&vmx->vcpu, vector,
3794 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3795 break;
3796 default:
3797 break;
f7d9238f 3798 }
cf393f75
AK		 3799}
3800
9c8cba37
AK		 3801/*
3802 * Failure to inject an interrupt should give us the information
3803 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3804 * when fetching the interrupt redirection bitmap in the real-mode
3805 * tss, this doesn't happen. So we do it ourselves.
3806 */
3807static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3808{
3809 vmx->rmode.irq.pending = 0;
5fdbf976 3810 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3811 return;
5fdbf976 3812 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3813 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3814 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3815 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3816 return;
3817 }
3818 vmx->idt_vectoring_info =
3819 VECTORING_INFO_VALID_MASK
3820 | INTR_TYPE_EXT_INTR
3821 | vmx->rmode.irq.vector;
3822}
3823
c801949d
AK		 3824#ifdef CONFIG_X86_64
3825#define R "r"
3826#define Q "q"
3827#else
3828#define R "e"
3829#define Q "l"
3830#endif
3831
851ba692 3832static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3833{
a2fa3e9f 3834 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3835
3b86cd99
JK		 3836 /* Record the guest's net vcpu time for enforced NMI injections. */
3837 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3838 vmx->entry_time = ktime_get();
3839
80ced186
MG		 3840 /* Don't enter VMX if guest state is invalid, let the exit handler
3841 start emulation until we arrive back to a valid state */
3842 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3843 return;
a89a8fb9 3844
5fdbf976
MT		 3845 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3846 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3847 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3848 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3849
787ff736
GN		 3850 /* When single-stepping over STI and MOV SS, we must clear the
3851 * corresponding interruptibility bits in the guest state. Otherwise
3852 * vmentry fails as it then expects bit 14 (BS) in pending debug
3853 * exceptions being set, but that's not correct for the guest debugging
3854 * case. */
3855 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3856 vmx_set_interrupt_shadow(vcpu, 0);
3857
e6adf283
AK		 3858 /*
3859 * Loading guest fpu may have cleared host cr0.ts
3860 */
3861 vmcs_writel(HOST_CR0, read_cr0());
3862
d77c26fc 3863 asm(
6aa8b732 3864 /* Store host registers */
c801949d
AK		 3865 "push %%"R"dx; push %%"R"bp;"
3866 "push %%"R"cx \n\t"
313dbd49
AK		 3867 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3868 "je 1f \n\t"
3869 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3870 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3871 "1: \n\t"
d3edefc0
AK		 3872 /* Reload cr2 if changed */
3873 "mov %c[cr2](%0), %%"R"ax \n\t"
3874 "mov %%cr2, %%"R"dx \n\t"
3875 "cmp %%"R"ax, %%"R"dx \n\t"
3876 "je 2f \n\t"
3877 "mov %%"R"ax, %%cr2 \n\t"
3878 "2: \n\t"
6aa8b732 3879 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3880 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3881 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3882 "mov %c[rax](%0), %%"R"ax \n\t"
3883 "mov %c[rbx](%0), %%"R"bx \n\t"
3884 "mov %c[rdx](%0), %%"R"dx \n\t"
3885 "mov %c[rsi](%0), %%"R"si \n\t"
3886 "mov %c[rdi](%0), %%"R"di \n\t"
3887 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3888#ifdef CONFIG_X86_64
e08aa78a
AK		 3889 "mov %c[r8](%0), %%r8 \n\t"
3890 "mov %c[r9](%0), %%r9 \n\t"
3891 "mov %c[r10](%0), %%r10 \n\t"
3892 "mov %c[r11](%0), %%r11 \n\t"
3893 "mov %c[r12](%0), %%r12 \n\t"
3894 "mov %c[r13](%0), %%r13 \n\t"
3895 "mov %c[r14](%0), %%r14 \n\t"
3896 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3897#endif
c801949d
AK		 3898 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3899
6aa8b732 3900 /* Enter guest mode */
cd2276a7 3901 "jne .Llaunched \n\t"
4ecac3fd 3902 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3903 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3904 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3905 ".Lkvm_vmx_return: "
6aa8b732 3906 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3907 "xchg %0, (%%"R"sp) \n\t"
3908 "mov %%"R"ax, %c[rax](%0) \n\t"
3909 "mov %%"R"bx, %c[rbx](%0) \n\t"
3910 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3911 "mov %%"R"dx, %c[rdx](%0) \n\t"
3912 "mov %%"R"si, %c[rsi](%0) \n\t"
3913 "mov %%"R"di, %c[rdi](%0) \n\t"
3914 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3915#ifdef CONFIG_X86_64
e08aa78a
AK		 3916 "mov %%r8, %c[r8](%0) \n\t"
3917 "mov %%r9, %c[r9](%0) \n\t"
3918 "mov %%r10, %c[r10](%0) \n\t"
3919 "mov %%r11, %c[r11](%0) \n\t"
3920 "mov %%r12, %c[r12](%0) \n\t"
3921 "mov %%r13, %c[r13](%0) \n\t"
3922 "mov %%r14, %c[r14](%0) \n\t"
3923 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3924#endif
c801949d
AK		 3925 "mov %%cr2, %%"R"ax \n\t"
3926 "mov %%"R"ax, %c[cr2](%0) \n\t"
3927
3928 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3929 "setbe %c[fail](%0) \n\t"
3930 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3931 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3932 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3933 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3934 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3935 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3936 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3937 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3938 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3939 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3940 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3941#ifdef CONFIG_X86_64
ad312c7c
ZX		 3942 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3943 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3944 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3945 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3946 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3947 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3948 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3949 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3950#endif
ad312c7c 3951 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3952 : "cc", "memory"
c801949d 3953 , R"bx", R"di", R"si"
c2036300 3954#ifdef CONFIG_X86_64
c2036300
LV		 3955 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3956#endif
3957 );
6aa8b732 3958
6de4f3ad
AK		 3959 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3960 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3961 vcpu->arch.regs_dirty = 0;
3962
1155f76a 3963 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3964 if (vmx->rmode.irq.pending)
3965 fixup_rmode_irq(vmx);
1155f76a 3966
d77c26fc 3967 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3968 vmx->launched = 1;
1b6269db 3969
cf393f75 3970 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3971}
3972
c801949d
AK		 3973#undef R
3974#undef Q
3975
6aa8b732
AK		 3976static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3977{
a2fa3e9f
GH		 3978 struct vcpu_vmx *vmx = to_vmx(vcpu);
3979
3980 if (vmx->vmcs) {
543e4243 3981 vcpu_clear(vmx);
a2fa3e9f
GH		 3982 free_vmcs(vmx->vmcs);
3983 vmx->vmcs = NULL;
6aa8b732
AK		 3984 }
3985}
3986
3987static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3988{
fb3f0f51
RR		 3989 struct vcpu_vmx *vmx = to_vmx(vcpu);
3990
cdbecfc3 3991 free_vpid(vmx);
6aa8b732 3992 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3993 kfree(vmx->guest_msrs);
3994 kvm_vcpu_uninit(vcpu);
a4770347 3995 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3996}
3997
fb3f0f51 3998static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3999{
fb3f0f51 4000 int err;
c16f862d 4001 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4002 int cpu;
6aa8b732 4003
a2fa3e9f 4004 if (!vmx)
fb3f0f51
RR		 4005 return ERR_PTR(-ENOMEM);
4006
2384d2b3
SY		 4007 allocate_vpid(vmx);
4008
fb3f0f51
RR		 4009 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4010 if (err)
4011 goto free_vcpu;
965b58a5 4012
a2fa3e9f 4013 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4014 if (!vmx->guest_msrs) {
4015 err = -ENOMEM;
4016 goto uninit_vcpu;
4017 }
965b58a5 4018
a2fa3e9f
GH		 4019 vmx->vmcs = alloc_vmcs();
4020 if (!vmx->vmcs)
fb3f0f51 4021 goto free_msrs;
a2fa3e9f
GH		 4022
4023 vmcs_clear(vmx->vmcs);
4024
15ad7146
AK		 4025 cpu = get_cpu();
4026 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 4027 err = vmx_vcpu_setup(vmx);
fb3f0f51 4028 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4029 put_cpu();
fb3f0f51
RR		 4030 if (err)
4031 goto free_vmcs;
5e4a0b3c
MT		 4032 if (vm_need_virtualize_apic_accesses(kvm))
4033 if (alloc_apic_access_page(kvm) != 0)
4034 goto free_vmcs;
fb3f0f51 4035
b927a3ce
SY		 4036 if (enable_ept) {
4037 if (!kvm->arch.ept_identity_map_addr)
4038 kvm->arch.ept_identity_map_addr =
4039 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4040 if (alloc_identity_pagetable(kvm) != 0)
4041 goto free_vmcs;
b927a3ce 4042 }
b7ebfb05 4043
fb3f0f51
RR		 4044 return &vmx->vcpu;
4045
4046free_vmcs:
4047 free_vmcs(vmx->vmcs);
4048free_msrs:
fb3f0f51
RR		 4049 kfree(vmx->guest_msrs);
4050uninit_vcpu:
4051 kvm_vcpu_uninit(&vmx->vcpu);
4052free_vcpu:
cdbecfc3 4053 free_vpid(vmx);
a4770347 4054 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4055 return ERR_PTR(err);
6aa8b732
AK		 4056}
4057
002c7f7c
YS		 4058static void __init vmx_check_processor_compat(void *rtn)
4059{
4060 struct vmcs_config vmcs_conf;
4061
4062 *(int *)rtn = 0;
4063 if (setup_vmcs_config(&vmcs_conf) < 0)
4064 *(int *)rtn = -EIO;
4065 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4066 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4067 smp_processor_id());
4068 *(int *)rtn = -EIO;
4069 }
4070}
4071
67253af5
SY		 4072static int get_ept_level(void)
4073{
4074 return VMX_EPT_DEFAULT_GAW + 1;
4075}
4076
4b12f0de 4077static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4078{
4b12f0de
SY		 4079 u64 ret;
4080
522c68c4
SY		 4081 /* For VT-d and EPT combination
4082 * 1. MMIO: always map as UC
4083 * 2. EPT with VT-d:
4084 * a. VT-d without snooping control feature: can't guarantee the
4085 * result, try to trust guest.
4086 * b. VT-d with snooping control feature: snooping control feature of
4087 * VT-d engine can guarantee the cache correctness. Just set it
4088 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4089 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4090 * consistent with host MTRR
4091 */
4b12f0de
SY		 4092 if (is_mmio)
4093 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4094 else if (vcpu->kvm->arch.iommu_domain &&
4095 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4096 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4097 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4098 else
522c68c4 4099 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4100 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4101
4102 return ret;
64d4d521
SY		 4103}
4104
f4c9e87c
AK		 4105#define _ER(x) { EXIT_REASON_##x, #x }
4106
229456fc 4107static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4108 _ER(EXCEPTION_NMI),
4109 _ER(EXTERNAL_INTERRUPT),
4110 _ER(TRIPLE_FAULT),
4111 _ER(PENDING_INTERRUPT),
4112 _ER(NMI_WINDOW),
4113 _ER(TASK_SWITCH),
4114 _ER(CPUID),
4115 _ER(HLT),
4116 _ER(INVLPG),
4117 _ER(RDPMC),
4118 _ER(RDTSC),
4119 _ER(VMCALL),
4120 _ER(VMCLEAR),
4121 _ER(VMLAUNCH),
4122 _ER(VMPTRLD),
4123 _ER(VMPTRST),
4124 _ER(VMREAD),
4125 _ER(VMRESUME),
4126 _ER(VMWRITE),
4127 _ER(VMOFF),
4128 _ER(VMON),
4129 _ER(CR_ACCESS),
4130 _ER(DR_ACCESS),
4131 _ER(IO_INSTRUCTION),
4132 _ER(MSR_READ),
4133 _ER(MSR_WRITE),
4134 _ER(MWAIT_INSTRUCTION),
4135 _ER(MONITOR_INSTRUCTION),
4136 _ER(PAUSE_INSTRUCTION),
4137 _ER(MCE_DURING_VMENTRY),
4138 _ER(TPR_BELOW_THRESHOLD),
4139 _ER(APIC_ACCESS),
4140 _ER(EPT_VIOLATION),
4141 _ER(EPT_MISCONFIG),
4142 _ER(WBINVD),
229456fc
MT		 4143 { -1, NULL }
4144};
4145
f4c9e87c
AK		 4146#undef _ER
4147
17cc3935 4148static int vmx_get_lpage_level(void)
344f414f 4149{
878403b7
SY		 4150 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4151 return PT_DIRECTORY_LEVEL;
4152 else
4153 /* For shadow and EPT supported 1GB page */
4154 return PT_PDPE_LEVEL;
344f414f
JR		 4155}
4156
4e47c7a6
SY		 4157static inline u32 bit(int bitno)
4158{
4159 return 1 << (bitno & 31);
4160}
4161
0e851880
SY		 4162static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4163{
4e47c7a6
SY		 4164 struct kvm_cpuid_entry2 *best;
4165 struct vcpu_vmx *vmx = to_vmx(vcpu);
4166 u32 exec_control;
4167
4168 vmx->rdtscp_enabled = false;
4169 if (vmx_rdtscp_supported()) {
4170 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4171 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4172 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4173 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4174 vmx->rdtscp_enabled = true;
4175 else {
4176 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4177 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4178 exec_control);
4179 }
4180 }
4181 }
0e851880
SY		 4182}
4183
d4330ef2
JR		 4184static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4185{
4186}
4187
cbdd1bea 4188static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4189 .cpu_has_kvm_support = cpu_has_kvm_support,
4190 .disabled_by_bios = vmx_disabled_by_bios,
4191 .hardware_setup = hardware_setup,
4192 .hardware_unsetup = hardware_unsetup,
002c7f7c 4193 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4194 .hardware_enable = hardware_enable,
4195 .hardware_disable = hardware_disable,
04547156 4196 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4197
4198 .vcpu_create = vmx_create_vcpu,
4199 .vcpu_free = vmx_free_vcpu,
04d2cc77 4200 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4201
04d2cc77 4202 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4203 .vcpu_load = vmx_vcpu_load,
4204 .vcpu_put = vmx_vcpu_put,
4205
4206 .set_guest_debug = set_guest_debug,
4207 .get_msr = vmx_get_msr,
4208 .set_msr = vmx_set_msr,
4209 .get_segment_base = vmx_get_segment_base,
4210 .get_segment = vmx_get_segment,
4211 .set_segment = vmx_set_segment,
2e4d2653 4212 .get_cpl = vmx_get_cpl,
6aa8b732 4213 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4214 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4215 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4216 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4217 .set_cr3 = vmx_set_cr3,
4218 .set_cr4 = vmx_set_cr4,
6aa8b732 4219 .set_efer = vmx_set_efer,
6aa8b732
AK		 4220 .get_idt = vmx_get_idt,
4221 .set_idt = vmx_set_idt,
4222 .get_gdt = vmx_get_gdt,
4223 .set_gdt = vmx_set_gdt,
020df079 4224 .set_dr7 = vmx_set_dr7,
5fdbf976 4225 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4226 .get_rflags = vmx_get_rflags,
4227 .set_rflags = vmx_set_rflags,
ebcbab4c 4228 .fpu_activate = vmx_fpu_activate,
02daab21 4229 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4230
4231 .tlb_flush = vmx_flush_tlb,
6aa8b732 4232
6aa8b732 4233 .run = vmx_vcpu_run,
6062d012 4234 .handle_exit = vmx_handle_exit,
6aa8b732 4235 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4236 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4237 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4238 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4239 .set_irq = vmx_inject_irq,
95ba8273 4240 .set_nmi = vmx_inject_nmi,
298101da 4241 .queue_exception = vmx_queue_exception,
78646121 4242 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4243 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4244 .get_nmi_mask = vmx_get_nmi_mask,
4245 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4246 .enable_nmi_window = enable_nmi_window,
4247 .enable_irq_window = enable_irq_window,
4248 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4249
cbc94022 4250 .set_tss_addr = vmx_set_tss_addr,
67253af5 4251 .get_tdp_level = get_ept_level,
4b12f0de 4252 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4253
4254 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4255 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4256
4257 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4258
4259 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4260
4261 .set_supported_cpuid = vmx_set_supported_cpuid,
6aa8b732
AK		 4262};
4263
4264static int __init vmx_init(void)
4265{
26bb0981
AK		 4266 int r, i;
4267
4268 rdmsrl_safe(MSR_EFER, &host_efer);
4269
4270 for (i = 0; i < NR_VMX_MSR; ++i)
4271 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4272
3e7c73e9 4273 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4274 if (!vmx_io_bitmap_a)
4275 return -ENOMEM;
4276
3e7c73e9 4277 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4278 if (!vmx_io_bitmap_b) {
4279 r = -ENOMEM;
4280 goto out;
4281 }
4282
5897297b
AK		 4283 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4284 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4285 r = -ENOMEM;
4286 goto out1;
4287 }
4288
5897297b
AK		 4289 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4290 if (!vmx_msr_bitmap_longmode) {
4291 r = -ENOMEM;
4292 goto out2;
4293 }
4294
fdef3ad1
HQ		 4295 /*
4296 * Allow direct access to the PC debug port (it is often used for I/O
4297 * delays, but the vmexits simply slow things down).
4298 */
3e7c73e9
AK		 4299 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4300 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4301
3e7c73e9 4302 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4303
5897297b
AK		 4304 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4305 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4306
2384d2b3
SY		 4307 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4308
0ee75bea
AK		 4309 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4310 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4311 if (r)
5897297b 4312 goto out3;
25c5f225 4313
5897297b
AK		 4314 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4315 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4316 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4317 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4318 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4319 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4320
089d034e 4321 if (enable_ept) {
1439442c 4322 bypass_guest_pf = 0;
5fdbcb9d 4323 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4324 VMX_EPT_WRITABLE_MASK);
534e38b4 4325 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4326 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4327 kvm_enable_tdp();
4328 } else
4329 kvm_disable_tdp();
1439442c 4330
c7addb90
AK		 4331 if (bypass_guest_pf)
4332 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4333
fdef3ad1
HQ		 4334 return 0;
4335
5897297b
AK		 4336out3:
4337 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4338out2:
5897297b 4339 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4340out1:
3e7c73e9 4341 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4342out:
3e7c73e9 4343 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4344 return r;
6aa8b732
AK		 4345}
4346
4347static void __exit vmx_exit(void)
4348{
5897297b
AK		 4349 free_page((unsigned long)vmx_msr_bitmap_legacy);
4350 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4351 free_page((unsigned long)vmx_io_bitmap_b);
4352 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4353
cb498ea2 4354 kvm_exit();
6aa8b732
AK		 4355}
4356
4357module_init(vmx_init)
4358module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)