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KVM: Trivial: Avoid hardware_disable predeclaration
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
e495606d
AK		 20#include "segment_descriptor.h"
21
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
07031e14 26#include <linux/profile.h>
e8edc6e0 27#include <linux/sched.h>
e495606d 28
6aa8b732 29#include <asm/io.h>
3b3be0d1 30#include <asm/desc.h>
6aa8b732 31
6aa8b732
AK		 32MODULE_AUTHOR("Qumranet");
33MODULE_LICENSE("GPL");
34
75880a01
AK		 35static int init_rmode_tss(struct kvm *kvm);
36
6aa8b732
AK		 37static DEFINE_PER_CPU(struct vmcs *, vmxarea);
38static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
39
fdef3ad1
HQ		 40static struct page *vmx_io_bitmap_a;
41static struct page *vmx_io_bitmap_b;
42
05b3e0c2 43#ifdef CONFIG_X86_64
6aa8b732
AK		 44#define HOST_IS_64 1
45#else
46#define HOST_IS_64 0
47#endif
2cc51560 48#define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
6aa8b732
AK		 49
50static struct vmcs_descriptor {
51 int size;
52 int order;
53 u32 revision_id;
54} vmcs_descriptor;
55
56#define VMX_SEGMENT_FIELD(seg) \
57 [VCPU_SREG_##seg] = { \
58 .selector = GUEST_##seg##_SELECTOR, \
59 .base = GUEST_##seg##_BASE, \
60 .limit = GUEST_##seg##_LIMIT, \
61 .ar_bytes = GUEST_##seg##_AR_BYTES, \
62 }
63
64static struct kvm_vmx_segment_field {
65 unsigned selector;
66 unsigned base;
67 unsigned limit;
68 unsigned ar_bytes;
69} kvm_vmx_segment_fields[] = {
70 VMX_SEGMENT_FIELD(CS),
71 VMX_SEGMENT_FIELD(DS),
72 VMX_SEGMENT_FIELD(ES),
73 VMX_SEGMENT_FIELD(FS),
74 VMX_SEGMENT_FIELD(GS),
75 VMX_SEGMENT_FIELD(SS),
76 VMX_SEGMENT_FIELD(TR),
77 VMX_SEGMENT_FIELD(LDTR),
78};
79
4d56c8a7
AK		 80/*
81 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
82 * away by decrementing the array size.
83 */
6aa8b732 84static const u32 vmx_msr_index[] = {
05b3e0c2 85#ifdef CONFIG_X86_64
6aa8b732
AK		 86 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
87#endif
88 MSR_EFER, MSR_K6_STAR,
89};
9d8f549d 90#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 91
2cc51560
ED		 92static inline u64 msr_efer_save_restore_bits(struct vmx_msr_entry msr)
93{
94 return (u64)msr.data & EFER_SAVE_RESTORE_BITS;
95}
96
97static inline int msr_efer_need_save_restore(struct kvm_vcpu *vcpu)
98{
99 int efer_offset = vcpu->msr_offset_efer;
100 return msr_efer_save_restore_bits(vcpu->host_msrs[efer_offset]) !=
101 msr_efer_save_restore_bits(vcpu->guest_msrs[efer_offset]);
102}
103
6aa8b732
AK		 104static inline int is_page_fault(u32 intr_info)
105{
106 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
107 INTR_INFO_VALID_MASK)) ==
108 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
109}
110
2ab455cc
AL		 111static inline int is_no_device(u32 intr_info)
112{
113 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
114 INTR_INFO_VALID_MASK)) ==
115 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
116}
117
6aa8b732
AK		 118static inline int is_external_interrupt(u32 intr_info)
119{
120 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
121 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
122}
123
a75beee6 124static int __find_msr_index(struct kvm_vcpu *vcpu, u32 msr)
7725f0ba
AK		 125{
126 int i;
127
128 for (i = 0; i < vcpu->nmsrs; ++i)
129 if (vcpu->guest_msrs[i].index == msr)
a75beee6
ED		 130 return i;
131 return -1;
132}
133
134static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
135{
136 int i;
137
138 i = __find_msr_index(vcpu, msr);
139 if (i >= 0)
140 return &vcpu->guest_msrs[i];
8b6d44c7 141 return NULL;
7725f0ba
AK		 142}
143
6aa8b732
AK		 144static void vmcs_clear(struct vmcs *vmcs)
145{
146 u64 phys_addr = __pa(vmcs);
147 u8 error;
148
149 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
150 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
151 : "cc", "memory");
152 if (error)
153 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
154 vmcs, phys_addr);
155}
156
157static void __vcpu_clear(void *arg)
158{
159 struct kvm_vcpu *vcpu = arg;
d3b2c338 160 int cpu = raw_smp_processor_id();
6aa8b732
AK		 161
162 if (vcpu->cpu == cpu)
163 vmcs_clear(vcpu->vmcs);
164 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
165 per_cpu(current_vmcs, cpu) = NULL;
7700270e 166 rdtscll(vcpu->host_tsc);
6aa8b732
AK		 167}
168
8d0be2b3
AK		 169static void vcpu_clear(struct kvm_vcpu *vcpu)
170{
171 if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1)
172 smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1);
173 else
174 __vcpu_clear(vcpu);
175 vcpu->launched = 0;
176}
177
6aa8b732
AK		 178static unsigned long vmcs_readl(unsigned long field)
179{
180 unsigned long value;
181
182 asm volatile (ASM_VMX_VMREAD_RDX_RAX
183 : "=a"(value) : "d"(field) : "cc");
184 return value;
185}
186
187static u16 vmcs_read16(unsigned long field)
188{
189 return vmcs_readl(field);
190}
191
192static u32 vmcs_read32(unsigned long field)
193{
194 return vmcs_readl(field);
195}
196
197static u64 vmcs_read64(unsigned long field)
198{
05b3e0c2 199#ifdef CONFIG_X86_64
6aa8b732
AK		 200 return vmcs_readl(field);
201#else
202 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
203#endif
204}
205
e52de1b8
AK		 206static noinline void vmwrite_error(unsigned long field, unsigned long value)
207{
208 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
209 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
210 dump_stack();
211}
212
6aa8b732
AK		 213static void vmcs_writel(unsigned long field, unsigned long value)
214{
215 u8 error;
216
217 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
218 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 219 if (unlikely(error))
220 vmwrite_error(field, value);
6aa8b732
AK		 221}
222
223static void vmcs_write16(unsigned long field, u16 value)
224{
225 vmcs_writel(field, value);
226}
227
228static void vmcs_write32(unsigned long field, u32 value)
229{
230 vmcs_writel(field, value);
231}
232
233static void vmcs_write64(unsigned long field, u64 value)
234{
05b3e0c2 235#ifdef CONFIG_X86_64
6aa8b732
AK		 236 vmcs_writel(field, value);
237#else
238 vmcs_writel(field, value);
239 asm volatile ("");
240 vmcs_writel(field+1, value >> 32);
241#endif
242}
243
2ab455cc
AL		 244static void vmcs_clear_bits(unsigned long field, u32 mask)
245{
246 vmcs_writel(field, vmcs_readl(field) & ~mask);
247}
248
249static void vmcs_set_bits(unsigned long field, u32 mask)
250{
251 vmcs_writel(field, vmcs_readl(field) | mask);
252}
253
abd3f2d6
AK		 254static void update_exception_bitmap(struct kvm_vcpu *vcpu)
255{
256 u32 eb;
257
258 eb = 1u << PF_VECTOR;
259 if (!vcpu->fpu_active)
260 eb |= 1u << NM_VECTOR;
261 if (vcpu->guest_debug.enabled)
262 eb |= 1u << 1;
263 if (vcpu->rmode.active)
264 eb = ~0;
265 vmcs_write32(EXCEPTION_BITMAP, eb);
266}
267
33ed6329
AK		 268static void reload_tss(void)
269{
270#ifndef CONFIG_X86_64
271
272 /*
273 * VT restores TR but not its size. Useless.
274 */
275 struct descriptor_table gdt;
276 struct segment_descriptor *descs;
277
278 get_gdt(&gdt);
279 descs = (void *)gdt.base;
280 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
281 load_TR_desc();
282#endif
283}
284
2cc51560
ED		 285static void load_transition_efer(struct kvm_vcpu *vcpu)
286{
287 u64 trans_efer;
288 int efer_offset = vcpu->msr_offset_efer;
289
290 trans_efer = vcpu->host_msrs[efer_offset].data;
291 trans_efer &= ~EFER_SAVE_RESTORE_BITS;
292 trans_efer |= msr_efer_save_restore_bits(
293 vcpu->guest_msrs[efer_offset]);
294 wrmsrl(MSR_EFER, trans_efer);
295 vcpu->stat.efer_reload++;
296}
297
33ed6329
AK		 298static void vmx_save_host_state(struct kvm_vcpu *vcpu)
299{
300 struct vmx_host_state *hs = &vcpu->vmx_host_state;
301
302 if (hs->loaded)
303 return;
304
305 hs->loaded = 1;
306 /*
307 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
308 * allow segment selectors with cpl > 0 or ti == 1.
309 */
310 hs->ldt_sel = read_ldt();
311 hs->fs_gs_ldt_reload_needed = hs->ldt_sel;
312 hs->fs_sel = read_fs();
313 if (!(hs->fs_sel & 7))
314 vmcs_write16(HOST_FS_SELECTOR, hs->fs_sel);
315 else {
316 vmcs_write16(HOST_FS_SELECTOR, 0);
317 hs->fs_gs_ldt_reload_needed = 1;
318 }
319 hs->gs_sel = read_gs();
320 if (!(hs->gs_sel & 7))
321 vmcs_write16(HOST_GS_SELECTOR, hs->gs_sel);
322 else {
323 vmcs_write16(HOST_GS_SELECTOR, 0);
324 hs->fs_gs_ldt_reload_needed = 1;
325 }
326
327#ifdef CONFIG_X86_64
328 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
329 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
330#else
331 vmcs_writel(HOST_FS_BASE, segment_base(hs->fs_sel));
332 vmcs_writel(HOST_GS_BASE, segment_base(hs->gs_sel));
333#endif
707c0874
AK		 334
335#ifdef CONFIG_X86_64
336 if (is_long_mode(vcpu)) {
a75beee6 337 save_msrs(vcpu->host_msrs + vcpu->msr_offset_kernel_gs_base, 1);
707c0874
AK		 338 }
339#endif
a75beee6 340 load_msrs(vcpu->guest_msrs, vcpu->save_nmsrs);
2cc51560
ED		 341 if (msr_efer_need_save_restore(vcpu))
342 load_transition_efer(vcpu);
33ed6329
AK		 343}
344
345static void vmx_load_host_state(struct kvm_vcpu *vcpu)
346{
347 struct vmx_host_state *hs = &vcpu->vmx_host_state;
348
349 if (!hs->loaded)
350 return;
351
352 hs->loaded = 0;
353 if (hs->fs_gs_ldt_reload_needed) {
354 load_ldt(hs->ldt_sel);
355 load_fs(hs->fs_sel);
356 /*
357 * If we have to reload gs, we must take care to
358 * preserve our gs base.
359 */
360 local_irq_disable();
361 load_gs(hs->gs_sel);
362#ifdef CONFIG_X86_64
363 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
364#endif
365 local_irq_enable();
366
367 reload_tss();
368 }
a75beee6
ED		 369 save_msrs(vcpu->guest_msrs, vcpu->save_nmsrs);
370 load_msrs(vcpu->host_msrs, vcpu->save_nmsrs);
2cc51560
ED		 371 if (msr_efer_need_save_restore(vcpu))
372 load_msrs(vcpu->host_msrs + vcpu->msr_offset_efer, 1);
33ed6329
AK		 373}
374
6aa8b732
AK		 375/*
376 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
377 * vcpu mutex is already taken.
378 */
bccf2150 379static void vmx_vcpu_load(struct kvm_vcpu *vcpu)
6aa8b732
AK		 380{
381 u64 phys_addr = __pa(vcpu->vmcs);
382 int cpu;
7700270e 383 u64 tsc_this, delta;
6aa8b732
AK		 384
385 cpu = get_cpu();
386
8d0be2b3
AK		 387 if (vcpu->cpu != cpu)
388 vcpu_clear(vcpu);
6aa8b732
AK		 389
390 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
391 u8 error;
392
393 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
394 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
395 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
396 : "cc");
397 if (error)
398 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
399 vcpu->vmcs, phys_addr);
400 }
401
402 if (vcpu->cpu != cpu) {
403 struct descriptor_table dt;
404 unsigned long sysenter_esp;
405
406 vcpu->cpu = cpu;
407 /*
408 * Linux uses per-cpu TSS and GDT, so set these when switching
409 * processors.
410 */
411 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
412 get_gdt(&dt);
413 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
414
415 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
416 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 417
418 /*
419 * Make sure the time stamp counter is monotonous.
420 */
421 rdtscll(tsc_this);
422 delta = vcpu->host_tsc - tsc_this;
423 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 424 }
6aa8b732
AK		 425}
426
427static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
428{
33ed6329 429 vmx_load_host_state(vcpu);
7702fd1f 430 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 431 put_cpu();
432}
433
5fd86fcf
AK		 434static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
435{
436 if (vcpu->fpu_active)
437 return;
438 vcpu->fpu_active = 1;
439 vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK);
440 if (vcpu->cr0 & CR0_TS_MASK)
441 vmcs_set_bits(GUEST_CR0, CR0_TS_MASK);
442 update_exception_bitmap(vcpu);
443}
444
445static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
446{
447 if (!vcpu->fpu_active)
448 return;
449 vcpu->fpu_active = 0;
450 vmcs_set_bits(GUEST_CR0, CR0_TS_MASK);
451 update_exception_bitmap(vcpu);
452}
453
774c47f1
AK		 454static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
455{
456 vcpu_clear(vcpu);
457}
458
6aa8b732
AK		 459static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
460{
461 return vmcs_readl(GUEST_RFLAGS);
462}
463
464static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
465{
466 vmcs_writel(GUEST_RFLAGS, rflags);
467}
468
469static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
470{
471 unsigned long rip;
472 u32 interruptibility;
473
474 rip = vmcs_readl(GUEST_RIP);
475 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
476 vmcs_writel(GUEST_RIP, rip);
477
478 /*
479 * We emulated an instruction, so temporary interrupt blocking
480 * should be removed, if set.
481 */
482 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
483 if (interruptibility & 3)
484 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
485 interruptibility & ~3);
c1150d8c 486 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 487}
488
489static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
490{
491 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
492 vmcs_readl(GUEST_RIP));
493 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
494 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
495 GP_VECTOR |
496 INTR_TYPE_EXCEPTION |
497 INTR_INFO_DELIEVER_CODE_MASK |
498 INTR_INFO_VALID_MASK);
499}
500
a75beee6
ED		 501/*
502 * Swap MSR entry in host/guest MSR entry array.
503 */
504void move_msr_up(struct kvm_vcpu *vcpu, int from, int to)
505{
506 struct vmx_msr_entry tmp;
507 tmp = vcpu->guest_msrs[to];
508 vcpu->guest_msrs[to] = vcpu->guest_msrs[from];
509 vcpu->guest_msrs[from] = tmp;
510 tmp = vcpu->host_msrs[to];
511 vcpu->host_msrs[to] = vcpu->host_msrs[from];
512 vcpu->host_msrs[from] = tmp;
513}
514
e38aea3e
AK		 515/*
516 * Set up the vmcs to automatically save and restore system
517 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
518 * mode, as fiddling with msrs is very expensive.
519 */
520static void setup_msrs(struct kvm_vcpu *vcpu)
521{
2cc51560 522 int save_nmsrs;
e38aea3e 523
a75beee6
ED		 524 save_nmsrs = 0;
525#ifdef CONFIG_X86_64
526 if (is_long_mode(vcpu)) {
2cc51560
ED		 527 int index;
528
a75beee6
ED		 529 index = __find_msr_index(vcpu, MSR_SYSCALL_MASK);
530 if (index >= 0)
531 move_msr_up(vcpu, index, save_nmsrs++);
532 index = __find_msr_index(vcpu, MSR_LSTAR);
533 if (index >= 0)
534 move_msr_up(vcpu, index, save_nmsrs++);
535 index = __find_msr_index(vcpu, MSR_CSTAR);
536 if (index >= 0)
537 move_msr_up(vcpu, index, save_nmsrs++);
538 index = __find_msr_index(vcpu, MSR_KERNEL_GS_BASE);
539 if (index >= 0)
540 move_msr_up(vcpu, index, save_nmsrs++);
541 /*
542 * MSR_K6_STAR is only needed on long mode guests, and only
543 * if efer.sce is enabled.
544 */
545 index = __find_msr_index(vcpu, MSR_K6_STAR);
546 if ((index >= 0) && (vcpu->shadow_efer & EFER_SCE))
547 move_msr_up(vcpu, index, save_nmsrs++);
548 }
549#endif
550 vcpu->save_nmsrs = save_nmsrs;
e38aea3e 551
4d56c8a7 552#ifdef CONFIG_X86_64
a75beee6
ED		 553 vcpu->msr_offset_kernel_gs_base =
554 __find_msr_index(vcpu, MSR_KERNEL_GS_BASE);
4d56c8a7 555#endif
2cc51560 556 vcpu->msr_offset_efer = __find_msr_index(vcpu, MSR_EFER);
e38aea3e
AK		 557}
558
6aa8b732
AK		 559/*
560 * reads and returns guest's timestamp counter "register"
561 * guest_tsc = host_tsc + tsc_offset -- 21.3
562 */
563static u64 guest_read_tsc(void)
564{
565 u64 host_tsc, tsc_offset;
566
567 rdtscll(host_tsc);
568 tsc_offset = vmcs_read64(TSC_OFFSET);
569 return host_tsc + tsc_offset;
570}
571
572/*
573 * writes 'guest_tsc' into guest's timestamp counter "register"
574 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
575 */
576static void guest_write_tsc(u64 guest_tsc)
577{
578 u64 host_tsc;
579
580 rdtscll(host_tsc);
581 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
582}
583
6aa8b732
AK		 584/*
585 * Reads an msr value (of 'msr_index') into 'pdata'.
586 * Returns 0 on success, non-0 otherwise.
587 * Assumes vcpu_load() was already called.
588 */
589static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
590{
591 u64 data;
592 struct vmx_msr_entry *msr;
593
594 if (!pdata) {
595 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
596 return -EINVAL;
597 }
598
599 switch (msr_index) {
05b3e0c2 600#ifdef CONFIG_X86_64
6aa8b732
AK		 601 case MSR_FS_BASE:
602 data = vmcs_readl(GUEST_FS_BASE);
603 break;
604 case MSR_GS_BASE:
605 data = vmcs_readl(GUEST_GS_BASE);
606 break;
607 case MSR_EFER:
3bab1f5d 608 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 609#endif
610 case MSR_IA32_TIME_STAMP_COUNTER:
611 data = guest_read_tsc();
612 break;
613 case MSR_IA32_SYSENTER_CS:
614 data = vmcs_read32(GUEST_SYSENTER_CS);
615 break;
616 case MSR_IA32_SYSENTER_EIP:
f5b42c33 617 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 618 break;
619 case MSR_IA32_SYSENTER_ESP:
f5b42c33 620 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 621 break;
6aa8b732
AK		 622 default:
623 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 624 if (msr) {
625 data = msr->data;
626 break;
6aa8b732 627 }
3bab1f5d 628 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 629 }
630
631 *pdata = data;
632 return 0;
633}
634
635/*
636 * Writes msr value into into the appropriate "register".
637 * Returns 0 on success, non-0 otherwise.
638 * Assumes vcpu_load() was already called.
639 */
640static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
641{
642 struct vmx_msr_entry *msr;
2cc51560
ED		 643 int ret = 0;
644
6aa8b732 645 switch (msr_index) {
05b3e0c2 646#ifdef CONFIG_X86_64
3bab1f5d 647 case MSR_EFER:
2cc51560
ED		 648 ret = kvm_set_msr_common(vcpu, msr_index, data);
649 if (vcpu->vmx_host_state.loaded)
650 load_transition_efer(vcpu);
651 break;
6aa8b732
AK		 652 case MSR_FS_BASE:
653 vmcs_writel(GUEST_FS_BASE, data);
654 break;
655 case MSR_GS_BASE:
656 vmcs_writel(GUEST_GS_BASE, data);
657 break;
658#endif
659 case MSR_IA32_SYSENTER_CS:
660 vmcs_write32(GUEST_SYSENTER_CS, data);
661 break;
662 case MSR_IA32_SYSENTER_EIP:
f5b42c33 663 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 664 break;
665 case MSR_IA32_SYSENTER_ESP:
f5b42c33 666 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 667 break;
d27d4aca 668 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 669 guest_write_tsc(data);
670 break;
6aa8b732
AK		 671 default:
672 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 673 if (msr) {
674 msr->data = data;
a75beee6 675 if (vcpu->vmx_host_state.loaded)
2cc51560 676 load_msrs(vcpu->guest_msrs, vcpu->save_nmsrs);
3bab1f5d 677 break;
6aa8b732 678 }
2cc51560 679 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 680 }
681
2cc51560 682 return ret;
6aa8b732
AK		 683}
684
685/*
686 * Sync the rsp and rip registers into the vcpu structure. This allows
687 * registers to be accessed by indexing vcpu->regs.
688 */
689static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
690{
691 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
692 vcpu->rip = vmcs_readl(GUEST_RIP);
693}
694
695/*
696 * Syncs rsp and rip back into the vmcs. Should be called after possible
697 * modification.
698 */
699static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
700{
701 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
702 vmcs_writel(GUEST_RIP, vcpu->rip);
703}
704
705static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
706{
707 unsigned long dr7 = 0x400;
6aa8b732
AK		 708 int old_singlestep;
709
6aa8b732
AK		 710 old_singlestep = vcpu->guest_debug.singlestep;
711
712 vcpu->guest_debug.enabled = dbg->enabled;
713 if (vcpu->guest_debug.enabled) {
714 int i;
715
716 dr7 |= 0x200; /* exact */
717 for (i = 0; i < 4; ++i) {
718 if (!dbg->breakpoints[i].enabled)
719 continue;
720 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
721 dr7 |= 2 << (i*2); /* global enable */
722 dr7 |= 0 << (i*4+16); /* execution breakpoint */
723 }
724
6aa8b732 725 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 726 } else
6aa8b732 727 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 728
729 if (old_singlestep && !vcpu->guest_debug.singlestep) {
730 unsigned long flags;
731
732 flags = vmcs_readl(GUEST_RFLAGS);
733 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
734 vmcs_writel(GUEST_RFLAGS, flags);
735 }
736
abd3f2d6 737 update_exception_bitmap(vcpu);
6aa8b732
AK		 738 vmcs_writel(GUEST_DR7, dr7);
739
740 return 0;
741}
742
743static __init int cpu_has_kvm_support(void)
744{
745 unsigned long ecx = cpuid_ecx(1);
746 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
747}
748
749static __init int vmx_disabled_by_bios(void)
750{
751 u64 msr;
752
753 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
754 return (msr & 5) == 1; /* locked but not enabled */
755}
756
774c47f1 757static void hardware_enable(void *garbage)
6aa8b732
AK		 758{
759 int cpu = raw_smp_processor_id();
760 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
761 u64 old;
762
763 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
bfdc0c28 764 if ((old & 5) != 5)
6aa8b732
AK		 765 /* enable and lock */
766 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
767 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
768 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
769 : "memory", "cc");
770}
771
772static void hardware_disable(void *garbage)
773{
774 asm volatile (ASM_VMX_VMXOFF : : : "cc");
775}
776
777static __init void setup_vmcs_descriptor(void)
778{
779 u32 vmx_msr_low, vmx_msr_high;
780
c68876fd 781 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
6aa8b732
AK		 782 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
783 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
784 vmcs_descriptor.revision_id = vmx_msr_low;
c68876fd 785}
6aa8b732
AK		 786
787static struct vmcs *alloc_vmcs_cpu(int cpu)
788{
789 int node = cpu_to_node(cpu);
790 struct page *pages;
791 struct vmcs *vmcs;
792
793 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
794 if (!pages)
795 return NULL;
796 vmcs = page_address(pages);
797 memset(vmcs, 0, vmcs_descriptor.size);
798 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
799 return vmcs;
800}
801
802static struct vmcs *alloc_vmcs(void)
803{
d3b2c338 804 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 805}
806
807static void free_vmcs(struct vmcs *vmcs)
808{
809 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
810}
811
39959588 812static void free_kvm_area(void)
6aa8b732
AK		 813{
814 int cpu;
815
816 for_each_online_cpu(cpu)
817 free_vmcs(per_cpu(vmxarea, cpu));
818}
819
820extern struct vmcs *alloc_vmcs_cpu(int cpu);
821
822static __init int alloc_kvm_area(void)
823{
824 int cpu;
825
826 for_each_online_cpu(cpu) {
827 struct vmcs *vmcs;
828
829 vmcs = alloc_vmcs_cpu(cpu);
830 if (!vmcs) {
831 free_kvm_area();
832 return -ENOMEM;
833 }
834
835 per_cpu(vmxarea, cpu) = vmcs;
836 }
837 return 0;
838}
839
840static __init int hardware_setup(void)
841{
842 setup_vmcs_descriptor();
843 return alloc_kvm_area();
844}
845
846static __exit void hardware_unsetup(void)
847{
848 free_kvm_area();
849}
850
6aa8b732
AK		 851static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
852{
853 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
854
6af11b9e 855 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 856 vmcs_write16(sf->selector, save->selector);
857 vmcs_writel(sf->base, save->base);
858 vmcs_write32(sf->limit, save->limit);
859 vmcs_write32(sf->ar_bytes, save->ar);
860 } else {
861 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
862 << AR_DPL_SHIFT;
863 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
864 }
865}
866
867static void enter_pmode(struct kvm_vcpu *vcpu)
868{
869 unsigned long flags;
870
871 vcpu->rmode.active = 0;
872
873 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
874 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
875 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
876
877 flags = vmcs_readl(GUEST_RFLAGS);
878 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
879 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
880 vmcs_writel(GUEST_RFLAGS, flags);
881
882 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
883 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
884
885 update_exception_bitmap(vcpu);
886
887 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
888 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
889 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
890 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
891
892 vmcs_write16(GUEST_SS_SELECTOR, 0);
893 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
894
895 vmcs_write16(GUEST_CS_SELECTOR,
896 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
897 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
898}
899
900static int rmode_tss_base(struct kvm* kvm)
901{
902 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
903 return base_gfn << PAGE_SHIFT;
904}
905
906static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
907{
908 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
909
910 save->selector = vmcs_read16(sf->selector);
911 save->base = vmcs_readl(sf->base);
912 save->limit = vmcs_read32(sf->limit);
913 save->ar = vmcs_read32(sf->ar_bytes);
914 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
915 vmcs_write32(sf->limit, 0xffff);
916 vmcs_write32(sf->ar_bytes, 0xf3);
917}
918
919static void enter_rmode(struct kvm_vcpu *vcpu)
920{
921 unsigned long flags;
922
923 vcpu->rmode.active = 1;
924
925 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
926 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
927
928 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
929 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
930
931 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
932 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
933
934 flags = vmcs_readl(GUEST_RFLAGS);
935 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
936
937 flags |= IOPL_MASK | X86_EFLAGS_VM;
938
939 vmcs_writel(GUEST_RFLAGS, flags);
940 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
941 update_exception_bitmap(vcpu);
942
943 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
944 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
945 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
946
947 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 948 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 949 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
950 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 951 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
952
953 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
954 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
955 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
956 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01
AK		 957
958 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 959}
960
05b3e0c2 961#ifdef CONFIG_X86_64
6aa8b732
AK		 962
963static void enter_lmode(struct kvm_vcpu *vcpu)
964{
965 u32 guest_tr_ar;
966
967 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
968 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
969 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
970 __FUNCTION__);
971 vmcs_write32(GUEST_TR_AR_BYTES,
972 (guest_tr_ar & ~AR_TYPE_MASK)
973 | AR_TYPE_BUSY_64_TSS);
974 }
975
976 vcpu->shadow_efer |= EFER_LMA;
977
978 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
979 vmcs_write32(VM_ENTRY_CONTROLS,
980 vmcs_read32(VM_ENTRY_CONTROLS)
981 | VM_ENTRY_CONTROLS_IA32E_MASK);
982}
983
984static void exit_lmode(struct kvm_vcpu *vcpu)
985{
986 vcpu->shadow_efer &= ~EFER_LMA;
987
988 vmcs_write32(VM_ENTRY_CONTROLS,
989 vmcs_read32(VM_ENTRY_CONTROLS)
990 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
991}
992
993#endif
994
25c4c276 995static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 996{
399badf3
AK		 997 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
998 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
999}
1000
6aa8b732
AK		 1001static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1002{
5fd86fcf
AK		 1003 vmx_fpu_deactivate(vcpu);
1004
6aa8b732
AK		 1005 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
1006 enter_pmode(vcpu);
1007
1008 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
1009 enter_rmode(vcpu);
1010
05b3e0c2 1011#ifdef CONFIG_X86_64
6aa8b732
AK		 1012 if (vcpu->shadow_efer & EFER_LME) {
1013 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
1014 enter_lmode(vcpu);
1015 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
1016 exit_lmode(vcpu);
1017 }
1018#endif
1019
1020 vmcs_writel(CR0_READ_SHADOW, cr0);
1021 vmcs_writel(GUEST_CR0,
1022 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1023 vcpu->cr0 = cr0;
5fd86fcf
AK		 1024
1025 if (!(cr0 & CR0_TS_MASK) || !(cr0 & CR0_PE_MASK))
1026 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1027}
1028
6aa8b732
AK		 1029static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1030{
1031 vmcs_writel(GUEST_CR3, cr3);
5fd86fcf
AK		 1032 if (vcpu->cr0 & CR0_PE_MASK)
1033 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1034}
1035
1036static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1037{
1038 vmcs_writel(CR4_READ_SHADOW, cr4);
1039 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1040 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1041 vcpu->cr4 = cr4;
1042}
1043
05b3e0c2 1044#ifdef CONFIG_X86_64
6aa8b732
AK		 1045
1046static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1047{
1048 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
1049
1050 vcpu->shadow_efer = efer;
1051 if (efer & EFER_LMA) {
1052 vmcs_write32(VM_ENTRY_CONTROLS,
1053 vmcs_read32(VM_ENTRY_CONTROLS) |
1054 VM_ENTRY_CONTROLS_IA32E_MASK);
1055 msr->data = efer;
1056
1057 } else {
1058 vmcs_write32(VM_ENTRY_CONTROLS,
1059 vmcs_read32(VM_ENTRY_CONTROLS) &
1060 ~VM_ENTRY_CONTROLS_IA32E_MASK);
1061
1062 msr->data = efer & ~EFER_LME;
1063 }
e38aea3e 1064 setup_msrs(vcpu);
6aa8b732
AK		 1065}
1066
1067#endif
1068
1069static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1070{
1071 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1072
1073 return vmcs_readl(sf->base);
1074}
1075
1076static void vmx_get_segment(struct kvm_vcpu *vcpu,
1077 struct kvm_segment *var, int seg)
1078{
1079 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1080 u32 ar;
1081
1082 var->base = vmcs_readl(sf->base);
1083 var->limit = vmcs_read32(sf->limit);
1084 var->selector = vmcs_read16(sf->selector);
1085 ar = vmcs_read32(sf->ar_bytes);
1086 if (ar & AR_UNUSABLE_MASK)
1087 ar = 0;
1088 var->type = ar & 15;
1089 var->s = (ar >> 4) & 1;
1090 var->dpl = (ar >> 5) & 3;
1091 var->present = (ar >> 7) & 1;
1092 var->avl = (ar >> 12) & 1;
1093 var->l = (ar >> 13) & 1;
1094 var->db = (ar >> 14) & 1;
1095 var->g = (ar >> 15) & 1;
1096 var->unusable = (ar >> 16) & 1;
1097}
1098
653e3108 1099static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1100{
6aa8b732
AK		 1101 u32 ar;
1102
653e3108 1103 if (var->unusable)
6aa8b732
AK		 1104 ar = 1 << 16;
1105 else {
1106 ar = var->type & 15;
1107 ar |= (var->s & 1) << 4;
1108 ar |= (var->dpl & 3) << 5;
1109 ar |= (var->present & 1) << 7;
1110 ar |= (var->avl & 1) << 12;
1111 ar |= (var->l & 1) << 13;
1112 ar |= (var->db & 1) << 14;
1113 ar |= (var->g & 1) << 15;
1114 }
f7fbf1fd
UL		 1115 if (ar == 0) /* a 0 value means unusable */
1116 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1117
1118 return ar;
1119}
1120
1121static void vmx_set_segment(struct kvm_vcpu *vcpu,
1122 struct kvm_segment *var, int seg)
1123{
1124 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1125 u32 ar;
1126
1127 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1128 vcpu->rmode.tr.selector = var->selector;
1129 vcpu->rmode.tr.base = var->base;
1130 vcpu->rmode.tr.limit = var->limit;
1131 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1132 return;
1133 }
1134 vmcs_writel(sf->base, var->base);
1135 vmcs_write32(sf->limit, var->limit);
1136 vmcs_write16(sf->selector, var->selector);
1137 if (vcpu->rmode.active && var->s) {
1138 /*
1139 * Hack real-mode segments into vm86 compatibility.
1140 */
1141 if (var->base == 0xffff0000 && var->selector == 0xf000)
1142 vmcs_writel(sf->base, 0xf0000);
1143 ar = 0xf3;
1144 } else
1145 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1146 vmcs_write32(sf->ar_bytes, ar);
1147}
1148
6aa8b732
AK		 1149static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1150{
1151 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1152
1153 *db = (ar >> 14) & 1;
1154 *l = (ar >> 13) & 1;
1155}
1156
1157static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1158{
1159 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1160 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1161}
1162
1163static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1164{
1165 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1166 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1167}
1168
1169static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1170{
1171 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1172 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1173}
1174
1175static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1176{
1177 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1178 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1179}
1180
1181static int init_rmode_tss(struct kvm* kvm)
1182{
1183 struct page *p1, *p2, *p3;
1184 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1185 char *page;
1186
954bbbc2
AK		 1187 p1 = gfn_to_page(kvm, fn++);
1188 p2 = gfn_to_page(kvm, fn++);
1189 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1190
1191 if (!p1 || !p2 || !p3) {
1192 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1193 return 0;
1194 }
1195
1196 page = kmap_atomic(p1, KM_USER0);
a3870c47 1197 clear_page(page);
6aa8b732
AK		 1198 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1199 kunmap_atomic(page, KM_USER0);
1200
1201 page = kmap_atomic(p2, KM_USER0);
a3870c47 1202 clear_page(page);
6aa8b732
AK		 1203 kunmap_atomic(page, KM_USER0);
1204
1205 page = kmap_atomic(p3, KM_USER0);
a3870c47 1206 clear_page(page);
6aa8b732
AK		 1207 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1208 kunmap_atomic(page, KM_USER0);
1209
1210 return 1;
1211}
1212
1213static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
1214{
1215 u32 msr_high, msr_low;
1216
1217 rdmsr(msr, msr_low, msr_high);
1218
1219 val &= msr_high;
1220 val |= msr_low;
1221 vmcs_write32(vmcs_field, val);
1222}
1223
1224static void seg_setup(int seg)
1225{
1226 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1227
1228 vmcs_write16(sf->selector, 0);
1229 vmcs_writel(sf->base, 0);
1230 vmcs_write32(sf->limit, 0xffff);
1231 vmcs_write32(sf->ar_bytes, 0x93);
1232}
1233
1234/*
1235 * Sets up the vmcs for emulated real mode.
1236 */
1237static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
1238{
1239 u32 host_sysenter_cs;
1240 u32 junk;
1241 unsigned long a;
1242 struct descriptor_table dt;
1243 int i;
1244 int ret = 0;
cd2276a7 1245 unsigned long kvm_vmx_return;
6aa8b732
AK		 1246
1247 if (!init_rmode_tss(vcpu->kvm)) {
1248 ret = -ENOMEM;
1249 goto out;
1250 }
1251
1252 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1253 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1254 vcpu->cr8 = 0;
94cea1bb 1255 vcpu->apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
dad3795d 1256 if (vcpu->vcpu_id == 0)
94cea1bb 1257 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732
AK		 1258
1259 fx_init(vcpu);
1260
1261 /*
1262 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1263 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1264 */
1265 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1266 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1267 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1268 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1269
1270 seg_setup(VCPU_SREG_DS);
1271 seg_setup(VCPU_SREG_ES);
1272 seg_setup(VCPU_SREG_FS);
1273 seg_setup(VCPU_SREG_GS);
1274 seg_setup(VCPU_SREG_SS);
1275
1276 vmcs_write16(GUEST_TR_SELECTOR, 0);
1277 vmcs_writel(GUEST_TR_BASE, 0);
1278 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1279 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1280
1281 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1282 vmcs_writel(GUEST_LDTR_BASE, 0);
1283 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1284 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1285
1286 vmcs_write32(GUEST_SYSENTER_CS, 0);
1287 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1288 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1289
1290 vmcs_writel(GUEST_RFLAGS, 0x02);
1291 vmcs_writel(GUEST_RIP, 0xfff0);
1292 vmcs_writel(GUEST_RSP, 0);
1293
6aa8b732
AK		 1294 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1295 vmcs_writel(GUEST_DR7, 0x400);
1296
1297 vmcs_writel(GUEST_GDTR_BASE, 0);
1298 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1299
1300 vmcs_writel(GUEST_IDTR_BASE, 0);
1301 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1302
1303 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1304 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1305 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1306
1307 /* I/O */
fdef3ad1
HQ		 1308 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1309 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1310
1311 guest_write_tsc(0);
1312
1313 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1314
1315 /* Special registers */
1316 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1317
1318 /* Control */
c68876fd 1319 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
6aa8b732
AK		 1320 PIN_BASED_VM_EXEC_CONTROL,
1321 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1322 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1323 );
c68876fd 1324 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
6aa8b732
AK		 1325 CPU_BASED_VM_EXEC_CONTROL,
1326 CPU_BASED_HLT_EXITING /* 20.6.2 */
1327 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1328 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
fdef3ad1 1329 | CPU_BASED_ACTIVATE_IO_BITMAP /* 20.6.2 */
6aa8b732
AK		 1330 | CPU_BASED_MOV_DR_EXITING
1331 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1332 );
1333
6aa8b732
AK		 1334 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1335 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1336 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1337
1338 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1339 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1340 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1341
1342 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1343 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1344 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1345 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1346 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1347 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1348#ifdef CONFIG_X86_64
6aa8b732
AK		 1349 rdmsrl(MSR_FS_BASE, a);
1350 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1351 rdmsrl(MSR_GS_BASE, a);
1352 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1353#else
1354 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1355 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1356#endif
1357
1358 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1359
1360 get_idt(&dt);
1361 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1362
cd2276a7
AK		 1363 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1364 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1365 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1366 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1367 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1368
1369 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1370 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1371 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1372 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1373 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1374 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1375
6aa8b732
AK		 1376 for (i = 0; i < NR_VMX_MSR; ++i) {
1377 u32 index = vmx_msr_index[i];
1378 u32 data_low, data_high;
1379 u64 data;
1380 int j = vcpu->nmsrs;
1381
1382 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1383 continue;
432bd6cb
AK		 1384 if (wrmsr_safe(index, data_low, data_high) < 0)
1385 continue;
6aa8b732
AK		 1386 data = data_low | ((u64)data_high << 32);
1387 vcpu->host_msrs[j].index = index;
1388 vcpu->host_msrs[j].reserved = 0;
1389 vcpu->host_msrs[j].data = data;
1390 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1391 ++vcpu->nmsrs;
1392 }
6aa8b732 1393
e38aea3e
AK		 1394 setup_msrs(vcpu);
1395
c68876fd 1396 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
6aa8b732 1397 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
6aa8b732
AK		 1398
1399 /* 22.2.1, 20.8.1 */
c68876fd 1400 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
6aa8b732
AK		 1401 VM_ENTRY_CONTROLS, 0);
1402 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1403
3b99ab24 1404#ifdef CONFIG_X86_64
6aa8b732
AK		 1405 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1406 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1407#endif
6aa8b732 1408
25c4c276 1409 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1410 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1411
1412 vcpu->cr0 = 0x60000010;
1413 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1414 vmx_set_cr4(vcpu, 0);
05b3e0c2 1415#ifdef CONFIG_X86_64
6aa8b732
AK		 1416 vmx_set_efer(vcpu, 0);
1417#endif
5fd86fcf 1418 vmx_fpu_activate(vcpu);
abd3f2d6 1419 update_exception_bitmap(vcpu);
6aa8b732
AK		 1420
1421 return 0;
1422
6aa8b732
AK		 1423out:
1424 return ret;
1425}
1426
1427static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1428{
1429 u16 ent[2];
1430 u16 cs;
1431 u16 ip;
1432 unsigned long flags;
1433 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1434 u16 sp = vmcs_readl(GUEST_RSP);
1435 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1436
3964994b 1437 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1438 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1439 __FUNCTION__,
1440 vmcs_readl(GUEST_RSP),
1441 vmcs_readl(GUEST_SS_BASE),
1442 vmcs_read32(GUEST_SS_LIMIT));
1443 return;
1444 }
1445
1446 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1447 sizeof(ent)) {
1448 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1449 return;
1450 }
1451
1452 flags = vmcs_readl(GUEST_RFLAGS);
1453 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1454 ip = vmcs_readl(GUEST_RIP);
1455
1456
1457 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1458 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1459 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1460 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1461 return;
1462 }
1463
1464 vmcs_writel(GUEST_RFLAGS, flags &
1465 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1466 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1467 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1468 vmcs_writel(GUEST_RIP, ent[0]);
1469 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1470}
1471
1472static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1473{
1474 int word_index = __ffs(vcpu->irq_summary);
1475 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1476 int irq = word_index * BITS_PER_LONG + bit_index;
1477
1478 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1479 if (!vcpu->irq_pending[word_index])
1480 clear_bit(word_index, &vcpu->irq_summary);
1481
1482 if (vcpu->rmode.active) {
1483 inject_rmode_irq(vcpu, irq);
1484 return;
1485 }
1486 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1487 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1488}
1489
c1150d8c
DL		 1490
1491static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1492 struct kvm_run *kvm_run)
6aa8b732 1493{
c1150d8c
DL		 1494 u32 cpu_based_vm_exec_control;
1495
1496 vcpu->interrupt_window_open =
1497 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1498 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1499
1500 if (vcpu->interrupt_window_open &&
1501 vcpu->irq_summary &&
1502 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1503 /*
c1150d8c 1504 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1505 */
1506 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1507
1508 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1509 if (!vcpu->interrupt_window_open &&
1510 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1511 /*
1512 * Interrupts blocked. Wait for unblock.
1513 */
c1150d8c
DL		 1514 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1515 else
1516 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1517 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1518}
1519
1520static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1521{
1522 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1523
1524 set_debugreg(dbg->bp[0], 0);
1525 set_debugreg(dbg->bp[1], 1);
1526 set_debugreg(dbg->bp[2], 2);
1527 set_debugreg(dbg->bp[3], 3);
1528
1529 if (dbg->singlestep) {
1530 unsigned long flags;
1531
1532 flags = vmcs_readl(GUEST_RFLAGS);
1533 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1534 vmcs_writel(GUEST_RFLAGS, flags);
1535 }
1536}
1537
1538static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1539 int vec, u32 err_code)
1540{
1541 if (!vcpu->rmode.active)
1542 return 0;
1543
b3f37707
NK		 1544 /*
1545 * Instruction with address size override prefix opcode 0x67
1546 * Cause the #SS fault with 0 error code in VM86 mode.
1547 */
1548 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
6aa8b732
AK		 1549 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1550 return 1;
1551 return 0;
1552}
1553
1554static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1555{
1556 u32 intr_info, error_code;
1557 unsigned long cr2, rip;
1558 u32 vect_info;
1559 enum emulation_result er;
e2dec939 1560 int r;
6aa8b732
AK		 1561
1562 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1563 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1564
1565 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1566 !is_page_fault(intr_info)) {
1567 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1568 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1569 }
1570
1571 if (is_external_interrupt(vect_info)) {
1572 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1573 set_bit(irq, vcpu->irq_pending);
1574 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1575 }
1576
1577 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1578 asm ("int $2");
1579 return 1;
1580 }
2ab455cc
AL		 1581
1582 if (is_no_device(intr_info)) {
5fd86fcf 1583 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1584 return 1;
1585 }
1586
6aa8b732
AK		 1587 error_code = 0;
1588 rip = vmcs_readl(GUEST_RIP);
1589 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1590 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1591 if (is_page_fault(intr_info)) {
1592 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1593
1594 spin_lock(&vcpu->kvm->lock);
e2dec939
AK		 1595 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1596 if (r < 0) {
1597 spin_unlock(&vcpu->kvm->lock);
1598 return r;
1599 }
1600 if (!r) {
6aa8b732
AK		 1601 spin_unlock(&vcpu->kvm->lock);
1602 return 1;
1603 }
1604
1605 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1606 spin_unlock(&vcpu->kvm->lock);
1607
1608 switch (er) {
1609 case EMULATE_DONE:
1610 return 1;
1611 case EMULATE_DO_MMIO:
1165f5fe 1612 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1613 kvm_run->exit_reason = KVM_EXIT_MMIO;
1614 return 0;
1615 case EMULATE_FAIL:
1616 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1617 break;
1618 default:
1619 BUG();
1620 }
1621 }
1622
1623 if (vcpu->rmode.active &&
1624 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1625 error_code)) {
1626 if (vcpu->halt_request) {
1627 vcpu->halt_request = 0;
1628 return kvm_emulate_halt(vcpu);
1629 }
6aa8b732 1630 return 1;
72d6e5a0 1631 }
6aa8b732
AK		 1632
1633 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1634 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1635 return 0;
1636 }
1637 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1638 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1639 kvm_run->ex.error_code = error_code;
1640 return 0;
1641}
1642
1643static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1644 struct kvm_run *kvm_run)
1645{
1165f5fe 1646 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1647 return 1;
1648}
1649
988ad74f
AK		 1650static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1651{
1652 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1653 return 0;
1654}
6aa8b732 1655
039576c0 1656static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count)
6aa8b732
AK		 1657{
1658 u64 inst;
1659 gva_t rip;
1660 int countr_size;
1661 int i, n;
1662
1663 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1664 countr_size = 2;
1665 } else {
1666 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1667
1668 countr_size = (cs_ar & AR_L_MASK) ? 8:
1669 (cs_ar & AR_DB_MASK) ? 4: 2;
1670 }
1671
1672 rip = vmcs_readl(GUEST_RIP);
1673 if (countr_size != 8)
1674 rip += vmcs_readl(GUEST_CS_BASE);
1675
1676 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1677
1678 for (i = 0; i < n; i++) {
1679 switch (((u8*)&inst)[i]) {
1680 case 0xf0:
1681 case 0xf2:
1682 case 0xf3:
1683 case 0x2e:
1684 case 0x36:
1685 case 0x3e:
1686 case 0x26:
1687 case 0x64:
1688 case 0x65:
1689 case 0x66:
1690 break;
1691 case 0x67:
1692 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1693 default:
1694 goto done;
1695 }
1696 }
1697 return 0;
1698done:
1699 countr_size *= 8;
1700 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
039576c0 1701 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
6aa8b732
AK		 1702 return 1;
1703}
1704
1705static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1706{
1707 u64 exit_qualification;
039576c0
AK		 1708 int size, down, in, string, rep;
1709 unsigned port;
1710 unsigned long count;
1711 gva_t address;
6aa8b732 1712
1165f5fe 1713 ++vcpu->stat.io_exits;
6aa8b732 1714 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
039576c0
AK		 1715 in = (exit_qualification & 8) != 0;
1716 size = (exit_qualification & 7) + 1;
1717 string = (exit_qualification & 16) != 0;
1718 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1719 count = 1;
1720 rep = (exit_qualification & 32) != 0;
1721 port = exit_qualification >> 16;
1722 address = 0;
1723 if (string) {
1724 if (rep && !get_io_count(vcpu, &count))
6aa8b732 1725 return 1;
039576c0
AK		 1726 address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1727 }
1728 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1729 address, rep, port);
6aa8b732
AK		 1730}
1731
102d8325
IM		 1732static void
1733vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1734{
1735 /*
1736 * Patch in the VMCALL instruction:
1737 */
1738 hypercall[0] = 0x0f;
1739 hypercall[1] = 0x01;
1740 hypercall[2] = 0xc1;
1741 hypercall[3] = 0xc3;
1742}
1743
6aa8b732
AK		 1744static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1745{
1746 u64 exit_qualification;
1747 int cr;
1748 int reg;
1749
1750 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1751 cr = exit_qualification & 15;
1752 reg = (exit_qualification >> 8) & 15;
1753 switch ((exit_qualification >> 4) & 3) {
1754 case 0: /* mov to cr */
1755 switch (cr) {
1756 case 0:
1757 vcpu_load_rsp_rip(vcpu);
1758 set_cr0(vcpu, vcpu->regs[reg]);
1759 skip_emulated_instruction(vcpu);
1760 return 1;
1761 case 3:
1762 vcpu_load_rsp_rip(vcpu);
1763 set_cr3(vcpu, vcpu->regs[reg]);
1764 skip_emulated_instruction(vcpu);
1765 return 1;
1766 case 4:
1767 vcpu_load_rsp_rip(vcpu);
1768 set_cr4(vcpu, vcpu->regs[reg]);
1769 skip_emulated_instruction(vcpu);
1770 return 1;
1771 case 8:
1772 vcpu_load_rsp_rip(vcpu);
1773 set_cr8(vcpu, vcpu->regs[reg]);
1774 skip_emulated_instruction(vcpu);
1775 return 1;
1776 };
1777 break;
25c4c276
AL		 1778 case 2: /* clts */
1779 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1780 vmx_fpu_deactivate(vcpu);
2ab455cc
AL		 1781 vcpu->cr0 &= ~CR0_TS_MASK;
1782 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1783 vmx_fpu_activate(vcpu);
25c4c276
AL		 1784 skip_emulated_instruction(vcpu);
1785 return 1;
6aa8b732
AK		 1786 case 1: /*mov from cr*/
1787 switch (cr) {
1788 case 3:
1789 vcpu_load_rsp_rip(vcpu);
1790 vcpu->regs[reg] = vcpu->cr3;
1791 vcpu_put_rsp_rip(vcpu);
1792 skip_emulated_instruction(vcpu);
1793 return 1;
1794 case 8:
6aa8b732
AK		 1795 vcpu_load_rsp_rip(vcpu);
1796 vcpu->regs[reg] = vcpu->cr8;
1797 vcpu_put_rsp_rip(vcpu);
1798 skip_emulated_instruction(vcpu);
1799 return 1;
1800 }
1801 break;
1802 case 3: /* lmsw */
1803 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1804
1805 skip_emulated_instruction(vcpu);
1806 return 1;
1807 default:
1808 break;
1809 }
1810 kvm_run->exit_reason = 0;
1811 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1812 (int)(exit_qualification >> 4) & 3, cr);
1813 return 0;
1814}
1815
1816static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1817{
1818 u64 exit_qualification;
1819 unsigned long val;
1820 int dr, reg;
1821
1822 /*
1823 * FIXME: this code assumes the host is debugging the guest.
1824 * need to deal with guest debugging itself too.
1825 */
1826 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1827 dr = exit_qualification & 7;
1828 reg = (exit_qualification >> 8) & 15;
1829 vcpu_load_rsp_rip(vcpu);
1830 if (exit_qualification & 16) {
1831 /* mov from dr */
1832 switch (dr) {
1833 case 6:
1834 val = 0xffff0ff0;
1835 break;
1836 case 7:
1837 val = 0x400;
1838 break;
1839 default:
1840 val = 0;
1841 }
1842 vcpu->regs[reg] = val;
1843 } else {
1844 /* mov to dr */
1845 }
1846 vcpu_put_rsp_rip(vcpu);
1847 skip_emulated_instruction(vcpu);
1848 return 1;
1849}
1850
1851static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1852{
06465c5a
AK		 1853 kvm_emulate_cpuid(vcpu);
1854 return 1;
6aa8b732
AK		 1855}
1856
1857static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1858{
1859 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1860 u64 data;
1861
1862 if (vmx_get_msr(vcpu, ecx, &data)) {
1863 vmx_inject_gp(vcpu, 0);
1864 return 1;
1865 }
1866
1867 /* FIXME: handling of bits 32:63 of rax, rdx */
1868 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1869 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1870 skip_emulated_instruction(vcpu);
1871 return 1;
1872}
1873
1874static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1875{
1876 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1877 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1878 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1879
1880 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1881 vmx_inject_gp(vcpu, 0);
1882 return 1;
1883 }
1884
1885 skip_emulated_instruction(vcpu);
1886 return 1;
1887}
1888
c1150d8c
DL		 1889static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1890 struct kvm_run *kvm_run)
1891{
1892 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1893 kvm_run->cr8 = vcpu->cr8;
1894 kvm_run->apic_base = vcpu->apic_base;
1895 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1896 vcpu->irq_summary == 0);
1897}
1898
6aa8b732
AK		 1899static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1900 struct kvm_run *kvm_run)
1901{
c1150d8c
DL		 1902 /*
1903 * If the user space waits to inject interrupts, exit as soon as
1904 * possible
1905 */
1906 if (kvm_run->request_interrupt_window &&
022a9308 1907 !vcpu->irq_summary) {
c1150d8c 1908 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 1909 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1910 return 0;
1911 }
6aa8b732
AK		 1912 return 1;
1913}
1914
1915static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1916{
1917 skip_emulated_instruction(vcpu);
d3bef15f 1918 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 1919}
1920
c21415e8
IM		 1921static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1922{
510043da 1923 skip_emulated_instruction(vcpu);
270fd9b9 1924 return kvm_hypercall(vcpu, kvm_run);
c21415e8
IM		 1925}
1926
6aa8b732
AK		 1927/*
1928 * The exit handlers return 1 if the exit was handled fully and guest execution
1929 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1930 * to be done to userspace and return 0.
1931 */
1932static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1933 struct kvm_run *kvm_run) = {
1934 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1935 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 1936 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 1937 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 1938 [EXIT_REASON_CR_ACCESS] = handle_cr,
1939 [EXIT_REASON_DR_ACCESS] = handle_dr,
1940 [EXIT_REASON_CPUID] = handle_cpuid,
1941 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1942 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1943 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1944 [EXIT_REASON_HLT] = handle_halt,
c21415e8 1945 [EXIT_REASON_VMCALL] = handle_vmcall,
6aa8b732
AK		 1946};
1947
1948static const int kvm_vmx_max_exit_handlers =
50a3485c 1949 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 1950
1951/*
1952 * The guest has exited. See if we can fix it or if we need userspace
1953 * assistance.
1954 */
1955static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1956{
1957 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1958 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1959
1960 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1961 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1962 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1963 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 1964 if (exit_reason < kvm_vmx_max_exit_handlers
1965 && kvm_vmx_exit_handlers[exit_reason])
1966 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1967 else {
1968 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1969 kvm_run->hw.hardware_exit_reason = exit_reason;
1970 }
1971 return 0;
1972}
1973
c1150d8c
DL		 1974/*
1975 * Check if userspace requested an interrupt window, and that the
1976 * interrupt window is open.
1977 *
1978 * No need to exit to userspace if we already have an interrupt queued.
1979 */
1980static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1981 struct kvm_run *kvm_run)
1982{
1983 return (!vcpu->irq_summary &&
1984 kvm_run->request_interrupt_window &&
1985 vcpu->interrupt_window_open &&
1986 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
1987}
1988
d9e368d6
AK		 1989static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1990{
d9e368d6
AK		 1991}
1992
6aa8b732
AK		 1993static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1994{
1995 u8 fail;
e2dec939 1996 int r;
6aa8b732 1997
e6adf283 1998preempted:
6aa8b732
AK		 1999 if (vcpu->guest_debug.enabled)
2000 kvm_guest_debug_pre(vcpu);
2001
e6adf283 2002again:
ff1dc794
GH		 2003 if (!vcpu->mmio_read_completed)
2004 do_interrupt_requests(vcpu, kvm_run);
2005
33ed6329 2006 vmx_save_host_state(vcpu);
e6adf283
AK		 2007 kvm_load_guest_fpu(vcpu);
2008
17c3ba9d
AK		 2009 r = kvm_mmu_reload(vcpu);
2010 if (unlikely(r))
2011 goto out;
2012
e6adf283
AK		 2013 /*
2014 * Loading guest fpu may have cleared host cr0.ts
2015 */
2016 vmcs_writel(HOST_CR0, read_cr0());
2017
d9e368d6
AK		 2018 local_irq_disable();
2019
2020 vcpu->guest_mode = 1;
2021 if (vcpu->requests)
2022 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
2023 vmx_flush_tlb(vcpu);
2024
6aa8b732
AK		 2025 asm (
2026 /* Store host registers */
05b3e0c2 2027#ifdef CONFIG_X86_64
6aa8b732
AK		 2028 "push %%rax; push %%rbx; push %%rdx;"
2029 "push %%rsi; push %%rdi; push %%rbp;"
2030 "push %%r8; push %%r9; push %%r10; push %%r11;"
2031 "push %%r12; push %%r13; push %%r14; push %%r15;"
2032 "push %%rcx \n\t"
2033 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2034#else
2035 "pusha; push %%ecx \n\t"
2036 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2037#endif
2038 /* Check if vmlaunch of vmresume is needed */
2039 "cmp $0, %1 \n\t"
2040 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2041#ifdef CONFIG_X86_64
6aa8b732
AK		 2042 "mov %c[cr2](%3), %%rax \n\t"
2043 "mov %%rax, %%cr2 \n\t"
2044 "mov %c[rax](%3), %%rax \n\t"
2045 "mov %c[rbx](%3), %%rbx \n\t"
2046 "mov %c[rdx](%3), %%rdx \n\t"
2047 "mov %c[rsi](%3), %%rsi \n\t"
2048 "mov %c[rdi](%3), %%rdi \n\t"
2049 "mov %c[rbp](%3), %%rbp \n\t"
2050 "mov %c[r8](%3), %%r8 \n\t"
2051 "mov %c[r9](%3), %%r9 \n\t"
2052 "mov %c[r10](%3), %%r10 \n\t"
2053 "mov %c[r11](%3), %%r11 \n\t"
2054 "mov %c[r12](%3), %%r12 \n\t"
2055 "mov %c[r13](%3), %%r13 \n\t"
2056 "mov %c[r14](%3), %%r14 \n\t"
2057 "mov %c[r15](%3), %%r15 \n\t"
2058 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2059#else
2060 "mov %c[cr2](%3), %%eax \n\t"
2061 "mov %%eax, %%cr2 \n\t"
2062 "mov %c[rax](%3), %%eax \n\t"
2063 "mov %c[rbx](%3), %%ebx \n\t"
2064 "mov %c[rdx](%3), %%edx \n\t"
2065 "mov %c[rsi](%3), %%esi \n\t"
2066 "mov %c[rdi](%3), %%edi \n\t"
2067 "mov %c[rbp](%3), %%ebp \n\t"
2068 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2069#endif
2070 /* Enter guest mode */
cd2276a7 2071 "jne .Llaunched \n\t"
6aa8b732 2072 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2073 "jmp .Lkvm_vmx_return \n\t"
2074 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2075 ".Lkvm_vmx_return: "
6aa8b732 2076 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2077#ifdef CONFIG_X86_64
96958231 2078 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2079 "mov %%rax, %c[rax](%3) \n\t"
2080 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2081 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2082 "mov %%rdx, %c[rdx](%3) \n\t"
2083 "mov %%rsi, %c[rsi](%3) \n\t"
2084 "mov %%rdi, %c[rdi](%3) \n\t"
2085 "mov %%rbp, %c[rbp](%3) \n\t"
2086 "mov %%r8, %c[r8](%3) \n\t"
2087 "mov %%r9, %c[r9](%3) \n\t"
2088 "mov %%r10, %c[r10](%3) \n\t"
2089 "mov %%r11, %c[r11](%3) \n\t"
2090 "mov %%r12, %c[r12](%3) \n\t"
2091 "mov %%r13, %c[r13](%3) \n\t"
2092 "mov %%r14, %c[r14](%3) \n\t"
2093 "mov %%r15, %c[r15](%3) \n\t"
2094 "mov %%cr2, %%rax \n\t"
2095 "mov %%rax, %c[cr2](%3) \n\t"
96958231 2096 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 2097
2098 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2099 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2100 "pop %%rbp; pop %%rdi; pop %%rsi;"
2101 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2102#else
96958231 2103 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2104 "mov %%eax, %c[rax](%3) \n\t"
2105 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2106 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2107 "mov %%edx, %c[rdx](%3) \n\t"
2108 "mov %%esi, %c[rsi](%3) \n\t"
2109 "mov %%edi, %c[rdi](%3) \n\t"
2110 "mov %%ebp, %c[rbp](%3) \n\t"
2111 "mov %%cr2, %%eax \n\t"
2112 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2113 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2114
2115 "pop %%ecx; popa \n\t"
2116#endif
2117 "setbe %0 \n\t"
e0015489 2118 : "=q" (fail)
6aa8b732
AK		 2119 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
2120 "c"(vcpu),
2121 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2122 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2123 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2124 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2125 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2126 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2127 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2128#ifdef CONFIG_X86_64
6aa8b732
AK		 2129 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2130 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2131 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2132 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2133 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2134 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2135 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2136 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2137#endif
2138 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2139 : "cc", "memory" );
2140
d9e368d6
AK		 2141 vcpu->guest_mode = 0;
2142 local_irq_enable();
2143
1165f5fe 2144 ++vcpu->stat.exits;
6aa8b732 2145
c1150d8c 2146 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2147
6aa8b732 2148 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6aa8b732 2149
05e0c8c3 2150 if (unlikely(fail)) {
8eb7d334
AK		 2151 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2152 kvm_run->fail_entry.hardware_entry_failure_reason
2153 = vmcs_read32(VM_INSTRUCTION_ERROR);
e2dec939 2154 r = 0;
05e0c8c3
AK		 2155 goto out;
2156 }
2157 /*
2158 * Profile KVM exit RIPs:
2159 */
2160 if (unlikely(prof_on == KVM_PROFILING))
2161 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2162
2163 vcpu->launched = 1;
2164 r = kvm_handle_exit(kvm_run, vcpu);
2165 if (r > 0) {
2166 /* Give scheduler a change to reschedule. */
2167 if (signal_pending(current)) {
2168 r = -EINTR;
2169 kvm_run->exit_reason = KVM_EXIT_INTR;
2170 ++vcpu->stat.signal_exits;
2171 goto out;
2172 }
2173
2174 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2175 r = -EINTR;
2176 kvm_run->exit_reason = KVM_EXIT_INTR;
2177 ++vcpu->stat.request_irq_exits;
2178 goto out;
2179 }
2180 if (!need_resched()) {
2181 ++vcpu->stat.light_exits;
2182 goto again;
6aa8b732
AK		 2183 }
2184 }
c1150d8c 2185
e6adf283 2186out:
e6adf283
AK		 2187 if (r > 0) {
2188 kvm_resched(vcpu);
2189 goto preempted;
2190 }
2191
c1150d8c 2192 post_kvm_run_save(vcpu, kvm_run);
e2dec939 2193 return r;
6aa8b732
AK		 2194}
2195
6aa8b732
AK		 2196static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2197 unsigned long addr,
2198 u32 err_code)
2199{
2200 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2201
1165f5fe 2202 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2203
2204 if (is_page_fault(vect_info)) {
2205 printk(KERN_DEBUG "inject_page_fault: "
2206 "double fault 0x%lx @ 0x%lx\n",
2207 addr, vmcs_readl(GUEST_RIP));
2208 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2209 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2210 DF_VECTOR |
2211 INTR_TYPE_EXCEPTION |
2212 INTR_INFO_DELIEVER_CODE_MASK |
2213 INTR_INFO_VALID_MASK);
2214 return;
2215 }
2216 vcpu->cr2 = addr;
2217 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2218 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2219 PF_VECTOR |
2220 INTR_TYPE_EXCEPTION |
2221 INTR_INFO_DELIEVER_CODE_MASK |
2222 INTR_INFO_VALID_MASK);
2223
2224}
2225
2226static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2227{
2228 if (vcpu->vmcs) {
2229 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
2230 free_vmcs(vcpu->vmcs);
2231 vcpu->vmcs = NULL;
2232 }
2233}
2234
2235static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2236{
2237 vmx_free_vmcs(vcpu);
2238}
2239
2240static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
2241{
2242 struct vmcs *vmcs;
2243
965b58a5
IM		 2244 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2245 if (!vcpu->guest_msrs)
2246 return -ENOMEM;
2247
2248 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2249 if (!vcpu->host_msrs)
2250 goto out_free_guest_msrs;
2251
6aa8b732
AK		 2252 vmcs = alloc_vmcs();
2253 if (!vmcs)
965b58a5
IM		 2254 goto out_free_msrs;
2255
6aa8b732
AK		 2256 vmcs_clear(vmcs);
2257 vcpu->vmcs = vmcs;
2258 vcpu->launched = 0;
965b58a5 2259
6aa8b732 2260 return 0;
965b58a5
IM		 2261
2262out_free_msrs:
2263 kfree(vcpu->host_msrs);
2264 vcpu->host_msrs = NULL;
2265
2266out_free_guest_msrs:
2267 kfree(vcpu->guest_msrs);
2268 vcpu->guest_msrs = NULL;
2269
2270 return -ENOMEM;
6aa8b732
AK		 2271}
2272
2273static struct kvm_arch_ops vmx_arch_ops = {
2274 .cpu_has_kvm_support = cpu_has_kvm_support,
2275 .disabled_by_bios = vmx_disabled_by_bios,
2276 .hardware_setup = hardware_setup,
2277 .hardware_unsetup = hardware_unsetup,
2278 .hardware_enable = hardware_enable,
2279 .hardware_disable = hardware_disable,
2280
2281 .vcpu_create = vmx_create_vcpu,
2282 .vcpu_free = vmx_free_vcpu,
2283
2284 .vcpu_load = vmx_vcpu_load,
2285 .vcpu_put = vmx_vcpu_put,
774c47f1 2286 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2287
2288 .set_guest_debug = set_guest_debug,
2289 .get_msr = vmx_get_msr,
2290 .set_msr = vmx_set_msr,
2291 .get_segment_base = vmx_get_segment_base,
2292 .get_segment = vmx_get_segment,
2293 .set_segment = vmx_set_segment,
6aa8b732 2294 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2295 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2296 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2297 .set_cr3 = vmx_set_cr3,
2298 .set_cr4 = vmx_set_cr4,
05b3e0c2 2299#ifdef CONFIG_X86_64
6aa8b732
AK		 2300 .set_efer = vmx_set_efer,
2301#endif
2302 .get_idt = vmx_get_idt,
2303 .set_idt = vmx_set_idt,
2304 .get_gdt = vmx_get_gdt,
2305 .set_gdt = vmx_set_gdt,
2306 .cache_regs = vcpu_load_rsp_rip,
2307 .decache_regs = vcpu_put_rsp_rip,
2308 .get_rflags = vmx_get_rflags,
2309 .set_rflags = vmx_set_rflags,
2310
2311 .tlb_flush = vmx_flush_tlb,
2312 .inject_page_fault = vmx_inject_page_fault,
2313
2314 .inject_gp = vmx_inject_gp,
2315
2316 .run = vmx_vcpu_run,
2317 .skip_emulated_instruction = skip_emulated_instruction,
2318 .vcpu_setup = vmx_vcpu_setup,
102d8325 2319 .patch_hypercall = vmx_patch_hypercall,
6aa8b732
AK		 2320};
2321
2322static int __init vmx_init(void)
2323{
fdef3ad1
HQ		 2324 void *iova;
2325 int r;
2326
2327 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2328 if (!vmx_io_bitmap_a)
2329 return -ENOMEM;
2330
2331 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2332 if (!vmx_io_bitmap_b) {
2333 r = -ENOMEM;
2334 goto out;
2335 }
2336
2337 /*
2338 * Allow direct access to the PC debug port (it is often used for I/O
2339 * delays, but the vmexits simply slow things down).
2340 */
2341 iova = kmap(vmx_io_bitmap_a);
2342 memset(iova, 0xff, PAGE_SIZE);
2343 clear_bit(0x80, iova);
cd0536d7 2344 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2345
2346 iova = kmap(vmx_io_bitmap_b);
2347 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2348 kunmap(vmx_io_bitmap_b);
fdef3ad1
HQ		 2349
2350 r = kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2351 if (r)
2352 goto out1;
2353
2354 return 0;
2355
2356out1:
2357 __free_page(vmx_io_bitmap_b);
2358out:
2359 __free_page(vmx_io_bitmap_a);
2360 return r;
6aa8b732
AK		 2361}
2362
2363static void __exit vmx_exit(void)
2364{
fdef3ad1
HQ		 2365 __free_page(vmx_io_bitmap_b);
2366 __free_page(vmx_io_bitmap_a);
2367
6aa8b732
AK		 2368 kvm_exit_arch();
2369}
2370
2371module_init(vmx_init)
2372module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)