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KVM: x86 emulator: Add vmmcall/vmcall to x86_emulate (v3)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
e7d5d76c 19#include "x86_emulate.h"
85f455f7 20#include "irq.h"
6aa8b732 21#include "vmx.h"
e495606d
AK		 22#include "segment_descriptor.h"
23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
6aa8b732
AK		 33MODULE_AUTHOR("Qumranet");
34MODULE_LICENSE("GPL");
35
a2fa3e9f
GH		 36struct vmcs {
37 u32 revision_id;
38 u32 abort;
39 char data[0];
40};
41
42struct vcpu_vmx {
fb3f0f51 43 struct kvm_vcpu vcpu;
a2fa3e9f 44 int launched;
29bd8a78 45 u8 fail;
a2fa3e9f
GH		 46 struct kvm_msr_entry *guest_msrs;
47 struct kvm_msr_entry *host_msrs;
48 int nmsrs;
49 int save_nmsrs;
50 int msr_offset_efer;
51#ifdef CONFIG_X86_64
52 int msr_offset_kernel_gs_base;
53#endif
54 struct vmcs *vmcs;
55 struct {
56 int loaded;
57 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 58 int gs_ldt_reload_needed;
59 int fs_reload_needed;
a2fa3e9f
GH		 60 }host_state;
61
62};
63
64static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
65{
fb3f0f51 66 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 67}
68
75880a01
AK		 69static int init_rmode_tss(struct kvm *kvm);
70
6aa8b732
AK		 71static DEFINE_PER_CPU(struct vmcs *, vmxarea);
72static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
73
fdef3ad1
HQ		 74static struct page *vmx_io_bitmap_a;
75static struct page *vmx_io_bitmap_b;
76
2cc51560 77#define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
6aa8b732 78
1c3d14fe 79static struct vmcs_config {
6aa8b732
AK		 80 int size;
81 int order;
82 u32 revision_id;
1c3d14fe
YS		 83 u32 pin_based_exec_ctrl;
84 u32 cpu_based_exec_ctrl;
85 u32 vmexit_ctrl;
86 u32 vmentry_ctrl;
87} vmcs_config;
6aa8b732
AK		 88
89#define VMX_SEGMENT_FIELD(seg) \
90 [VCPU_SREG_##seg] = { \
91 .selector = GUEST_##seg##_SELECTOR, \
92 .base = GUEST_##seg##_BASE, \
93 .limit = GUEST_##seg##_LIMIT, \
94 .ar_bytes = GUEST_##seg##_AR_BYTES, \
95 }
96
97static struct kvm_vmx_segment_field {
98 unsigned selector;
99 unsigned base;
100 unsigned limit;
101 unsigned ar_bytes;
102} kvm_vmx_segment_fields[] = {
103 VMX_SEGMENT_FIELD(CS),
104 VMX_SEGMENT_FIELD(DS),
105 VMX_SEGMENT_FIELD(ES),
106 VMX_SEGMENT_FIELD(FS),
107 VMX_SEGMENT_FIELD(GS),
108 VMX_SEGMENT_FIELD(SS),
109 VMX_SEGMENT_FIELD(TR),
110 VMX_SEGMENT_FIELD(LDTR),
111};
112
4d56c8a7
AK		 113/*
114 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
115 * away by decrementing the array size.
116 */
6aa8b732 117static const u32 vmx_msr_index[] = {
05b3e0c2 118#ifdef CONFIG_X86_64
6aa8b732
AK		 119 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
120#endif
121 MSR_EFER, MSR_K6_STAR,
122};
9d8f549d 123#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 124
a2fa3e9f
GH		 125static void load_msrs(struct kvm_msr_entry *e, int n)
126{
127 int i;
128
129 for (i = 0; i < n; ++i)
130 wrmsrl(e[i].index, e[i].data);
131}
132
133static void save_msrs(struct kvm_msr_entry *e, int n)
134{
135 int i;
136
137 for (i = 0; i < n; ++i)
138 rdmsrl(e[i].index, e[i].data);
139}
140
141static inline u64 msr_efer_save_restore_bits(struct kvm_msr_entry msr)
2cc51560
ED		 142{
143 return (u64)msr.data & EFER_SAVE_RESTORE_BITS;
144}
145
8b9cf98c 146static inline int msr_efer_need_save_restore(struct vcpu_vmx *vmx)
2cc51560 147{
a2fa3e9f
GH		 148 int efer_offset = vmx->msr_offset_efer;
149 return msr_efer_save_restore_bits(vmx->host_msrs[efer_offset]) !=
150 msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
2cc51560
ED		 151}
152
6aa8b732
AK		 153static inline int is_page_fault(u32 intr_info)
154{
155 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
156 INTR_INFO_VALID_MASK)) ==
157 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
158}
159
2ab455cc
AL		 160static inline int is_no_device(u32 intr_info)
161{
162 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
163 INTR_INFO_VALID_MASK)) ==
164 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
165}
166
6aa8b732
AK		 167static inline int is_external_interrupt(u32 intr_info)
168{
169 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
170 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
171}
172
6e5d865c
YS		 173static inline int cpu_has_vmx_tpr_shadow(void)
174{
175 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
176}
177
178static inline int vm_need_tpr_shadow(struct kvm *kvm)
179{
180 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
181}
182
8b9cf98c 183static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 184{
185 int i;
186
a2fa3e9f
GH		 187 for (i = 0; i < vmx->nmsrs; ++i)
188 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 189 return i;
190 return -1;
191}
192
8b9cf98c 193static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 194{
195 int i;
196
8b9cf98c 197 i = __find_msr_index(vmx, msr);
a75beee6 198 if (i >= 0)
a2fa3e9f 199 return &vmx->guest_msrs[i];
8b6d44c7 200 return NULL;
7725f0ba
AK		 201}
202
6aa8b732
AK		 203static void vmcs_clear(struct vmcs *vmcs)
204{
205 u64 phys_addr = __pa(vmcs);
206 u8 error;
207
208 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
209 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
210 : "cc", "memory");
211 if (error)
212 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
213 vmcs, phys_addr);
214}
215
216static void __vcpu_clear(void *arg)
217{
8b9cf98c 218 struct vcpu_vmx *vmx = arg;
d3b2c338 219 int cpu = raw_smp_processor_id();
6aa8b732 220
8b9cf98c 221 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 222 vmcs_clear(vmx->vmcs);
223 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 224 per_cpu(current_vmcs, cpu) = NULL;
8b9cf98c 225 rdtscll(vmx->vcpu.host_tsc);
6aa8b732
AK		 226}
227
8b9cf98c 228static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 229{
8b9cf98c
RR		 230 if (vmx->vcpu.cpu != raw_smp_processor_id() && vmx->vcpu.cpu != -1)
231 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear,
232 vmx, 0, 1);
8d0be2b3 233 else
8b9cf98c
RR		 234 __vcpu_clear(vmx);
235 vmx->launched = 0;
8d0be2b3
AK		 236}
237
6aa8b732
AK		 238static unsigned long vmcs_readl(unsigned long field)
239{
240 unsigned long value;
241
242 asm volatile (ASM_VMX_VMREAD_RDX_RAX
243 : "=a"(value) : "d"(field) : "cc");
244 return value;
245}
246
247static u16 vmcs_read16(unsigned long field)
248{
249 return vmcs_readl(field);
250}
251
252static u32 vmcs_read32(unsigned long field)
253{
254 return vmcs_readl(field);
255}
256
257static u64 vmcs_read64(unsigned long field)
258{
05b3e0c2 259#ifdef CONFIG_X86_64
6aa8b732
AK		 260 return vmcs_readl(field);
261#else
262 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
263#endif
264}
265
e52de1b8
AK		 266static noinline void vmwrite_error(unsigned long field, unsigned long value)
267{
268 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
269 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
270 dump_stack();
271}
272
6aa8b732
AK		 273static void vmcs_writel(unsigned long field, unsigned long value)
274{
275 u8 error;
276
277 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
278 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 279 if (unlikely(error))
280 vmwrite_error(field, value);
6aa8b732
AK		 281}
282
283static void vmcs_write16(unsigned long field, u16 value)
284{
285 vmcs_writel(field, value);
286}
287
288static void vmcs_write32(unsigned long field, u32 value)
289{
290 vmcs_writel(field, value);
291}
292
293static void vmcs_write64(unsigned long field, u64 value)
294{
05b3e0c2 295#ifdef CONFIG_X86_64
6aa8b732
AK		 296 vmcs_writel(field, value);
297#else
298 vmcs_writel(field, value);
299 asm volatile ("");
300 vmcs_writel(field+1, value >> 32);
301#endif
302}
303
2ab455cc
AL		 304static void vmcs_clear_bits(unsigned long field, u32 mask)
305{
306 vmcs_writel(field, vmcs_readl(field) & ~mask);
307}
308
309static void vmcs_set_bits(unsigned long field, u32 mask)
310{
311 vmcs_writel(field, vmcs_readl(field) | mask);
312}
313
abd3f2d6
AK		 314static void update_exception_bitmap(struct kvm_vcpu *vcpu)
315{
316 u32 eb;
317
318 eb = 1u << PF_VECTOR;
319 if (!vcpu->fpu_active)
320 eb |= 1u << NM_VECTOR;
321 if (vcpu->guest_debug.enabled)
322 eb |= 1u << 1;
323 if (vcpu->rmode.active)
324 eb = ~0;
325 vmcs_write32(EXCEPTION_BITMAP, eb);
326}
327
33ed6329
AK		 328static void reload_tss(void)
329{
330#ifndef CONFIG_X86_64
331
332 /*
333 * VT restores TR but not its size. Useless.
334 */
335 struct descriptor_table gdt;
336 struct segment_descriptor *descs;
337
338 get_gdt(&gdt);
339 descs = (void *)gdt.base;
340 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
341 load_TR_desc();
342#endif
343}
344
8b9cf98c 345static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560
ED		 346{
347 u64 trans_efer;
a2fa3e9f 348 int efer_offset = vmx->msr_offset_efer;
2cc51560 349
a2fa3e9f 350 trans_efer = vmx->host_msrs[efer_offset].data;
2cc51560 351 trans_efer &= ~EFER_SAVE_RESTORE_BITS;
a2fa3e9f 352 trans_efer |= msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
2cc51560 353 wrmsrl(MSR_EFER, trans_efer);
8b9cf98c 354 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 355}
356
04d2cc77 357static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 358{
04d2cc77
AK		 359 struct vcpu_vmx *vmx = to_vmx(vcpu);
360
a2fa3e9f 361 if (vmx->host_state.loaded)
33ed6329
AK		 362 return;
363
a2fa3e9f 364 vmx->host_state.loaded = 1;
33ed6329
AK		 365 /*
366 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
367 * allow segment selectors with cpl > 0 or ti == 1.
368 */
a2fa3e9f 369 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 370 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 371 vmx->host_state.fs_sel = read_fs();
152d3f2f 372 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 373 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 374 vmx->host_state.fs_reload_needed = 0;
375 } else {
33ed6329 376 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 377 vmx->host_state.fs_reload_needed = 1;
33ed6329 378 }
a2fa3e9f
GH		 379 vmx->host_state.gs_sel = read_gs();
380 if (!(vmx->host_state.gs_sel & 7))
381 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 382 else {
383 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 384 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 385 }
386
387#ifdef CONFIG_X86_64
388 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
389 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
390#else
a2fa3e9f
GH		 391 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
392 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 393#endif
707c0874
AK		 394
395#ifdef CONFIG_X86_64
8b9cf98c 396 if (is_long_mode(&vmx->vcpu)) {
a2fa3e9f
GH		 397 save_msrs(vmx->host_msrs +
398 vmx->msr_offset_kernel_gs_base, 1);
707c0874
AK		 399 }
400#endif
a2fa3e9f 401 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
8b9cf98c
RR		 402 if (msr_efer_need_save_restore(vmx))
403 load_transition_efer(vmx);
33ed6329
AK		 404}
405
8b9cf98c 406static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 407{
15ad7146 408 unsigned long flags;
33ed6329 409
a2fa3e9f 410 if (!vmx->host_state.loaded)
33ed6329
AK		 411 return;
412
a2fa3e9f 413 vmx->host_state.loaded = 0;
152d3f2f 414 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 415 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 416 if (vmx->host_state.gs_ldt_reload_needed) {
417 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 418 /*
419 * If we have to reload gs, we must take care to
420 * preserve our gs base.
421 */
15ad7146 422 local_irq_save(flags);
a2fa3e9f 423 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 424#ifdef CONFIG_X86_64
425 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
426#endif
15ad7146 427 local_irq_restore(flags);
33ed6329 428 }
152d3f2f 429 reload_tss();
a2fa3e9f
GH		 430 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
431 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
8b9cf98c 432 if (msr_efer_need_save_restore(vmx))
a2fa3e9f 433 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
33ed6329
AK		 434}
435
6aa8b732
AK		 436/*
437 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
438 * vcpu mutex is already taken.
439 */
15ad7146 440static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 441{
a2fa3e9f
GH		 442 struct vcpu_vmx *vmx = to_vmx(vcpu);
443 u64 phys_addr = __pa(vmx->vmcs);
7700270e 444 u64 tsc_this, delta;
6aa8b732 445
a3d7f85f 446 if (vcpu->cpu != cpu) {
8b9cf98c 447 vcpu_clear(vmx);
a3d7f85f
ED		 448 kvm_migrate_apic_timer(vcpu);
449 }
6aa8b732 450
a2fa3e9f 451 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 452 u8 error;
453
a2fa3e9f 454 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 455 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
456 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
457 : "cc");
458 if (error)
459 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 460 vmx->vmcs, phys_addr);
6aa8b732
AK		 461 }
462
463 if (vcpu->cpu != cpu) {
464 struct descriptor_table dt;
465 unsigned long sysenter_esp;
466
467 vcpu->cpu = cpu;
468 /*
469 * Linux uses per-cpu TSS and GDT, so set these when switching
470 * processors.
471 */
472 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
473 get_gdt(&dt);
474 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
475
476 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
477 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 478
479 /*
480 * Make sure the time stamp counter is monotonous.
481 */
482 rdtscll(tsc_this);
483 delta = vcpu->host_tsc - tsc_this;
484 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 485 }
6aa8b732
AK		 486}
487
488static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
489{
8b9cf98c 490 vmx_load_host_state(to_vmx(vcpu));
7702fd1f 491 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 492}
493
5fd86fcf
AK		 494static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
495{
496 if (vcpu->fpu_active)
497 return;
498 vcpu->fpu_active = 1;
707d92fa
RR		 499 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
500 if (vcpu->cr0 & X86_CR0_TS)
501 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 502 update_exception_bitmap(vcpu);
503}
504
505static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
506{
507 if (!vcpu->fpu_active)
508 return;
509 vcpu->fpu_active = 0;
707d92fa 510 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 511 update_exception_bitmap(vcpu);
512}
513
774c47f1
AK		 514static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
515{
8b9cf98c 516 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 517}
518
6aa8b732
AK		 519static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
520{
521 return vmcs_readl(GUEST_RFLAGS);
522}
523
524static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
525{
78f78268 526 if (vcpu->rmode.active)
053de044 527 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 528 vmcs_writel(GUEST_RFLAGS, rflags);
529}
530
531static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
532{
533 unsigned long rip;
534 u32 interruptibility;
535
536 rip = vmcs_readl(GUEST_RIP);
537 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
538 vmcs_writel(GUEST_RIP, rip);
539
540 /*
541 * We emulated an instruction, so temporary interrupt blocking
542 * should be removed, if set.
543 */
544 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
545 if (interruptibility & 3)
546 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
547 interruptibility & ~3);
c1150d8c 548 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 549}
550
551static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
552{
553 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
554 vmcs_readl(GUEST_RIP));
555 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
556 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
557 GP_VECTOR |
558 INTR_TYPE_EXCEPTION |
559 INTR_INFO_DELIEVER_CODE_MASK |
560 INTR_INFO_VALID_MASK);
561}
562
a75beee6
ED		 563/*
564 * Swap MSR entry in host/guest MSR entry array.
565 */
54e11fa1 566#ifdef CONFIG_X86_64
8b9cf98c 567static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 568{
a2fa3e9f
GH		 569 struct kvm_msr_entry tmp;
570
571 tmp = vmx->guest_msrs[to];
572 vmx->guest_msrs[to] = vmx->guest_msrs[from];
573 vmx->guest_msrs[from] = tmp;
574 tmp = vmx->host_msrs[to];
575 vmx->host_msrs[to] = vmx->host_msrs[from];
576 vmx->host_msrs[from] = tmp;
a75beee6 577}
54e11fa1 578#endif
a75beee6 579
e38aea3e
AK		 580/*
581 * Set up the vmcs to automatically save and restore system
582 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
583 * mode, as fiddling with msrs is very expensive.
584 */
8b9cf98c 585static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 586{
2cc51560 587 int save_nmsrs;
e38aea3e 588
a75beee6
ED		 589 save_nmsrs = 0;
590#ifdef CONFIG_X86_64
8b9cf98c 591 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 592 int index;
593
8b9cf98c 594 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 595 if (index >= 0)
8b9cf98c
RR		 596 move_msr_up(vmx, index, save_nmsrs++);
597 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 598 if (index >= 0)
8b9cf98c
RR		 599 move_msr_up(vmx, index, save_nmsrs++);
600 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 601 if (index >= 0)
8b9cf98c
RR		 602 move_msr_up(vmx, index, save_nmsrs++);
603 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 604 if (index >= 0)
8b9cf98c 605 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 606 /*
607 * MSR_K6_STAR is only needed on long mode guests, and only
608 * if efer.sce is enabled.
609 */
8b9cf98c
RR		 610 index = __find_msr_index(vmx, MSR_K6_STAR);
611 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
612 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 613 }
614#endif
a2fa3e9f 615 vmx->save_nmsrs = save_nmsrs;
e38aea3e 616
4d56c8a7 617#ifdef CONFIG_X86_64
a2fa3e9f 618 vmx->msr_offset_kernel_gs_base =
8b9cf98c 619 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 620#endif
8b9cf98c 621 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 622}
623
6aa8b732
AK		 624/*
625 * reads and returns guest's timestamp counter "register"
626 * guest_tsc = host_tsc + tsc_offset -- 21.3
627 */
628static u64 guest_read_tsc(void)
629{
630 u64 host_tsc, tsc_offset;
631
632 rdtscll(host_tsc);
633 tsc_offset = vmcs_read64(TSC_OFFSET);
634 return host_tsc + tsc_offset;
635}
636
637/*
638 * writes 'guest_tsc' into guest's timestamp counter "register"
639 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
640 */
641static void guest_write_tsc(u64 guest_tsc)
642{
643 u64 host_tsc;
644
645 rdtscll(host_tsc);
646 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
647}
648
6aa8b732
AK		 649/*
650 * Reads an msr value (of 'msr_index') into 'pdata'.
651 * Returns 0 on success, non-0 otherwise.
652 * Assumes vcpu_load() was already called.
653 */
654static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
655{
656 u64 data;
a2fa3e9f 657 struct kvm_msr_entry *msr;
6aa8b732
AK		 658
659 if (!pdata) {
660 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
661 return -EINVAL;
662 }
663
664 switch (msr_index) {
05b3e0c2 665#ifdef CONFIG_X86_64
6aa8b732
AK		 666 case MSR_FS_BASE:
667 data = vmcs_readl(GUEST_FS_BASE);
668 break;
669 case MSR_GS_BASE:
670 data = vmcs_readl(GUEST_GS_BASE);
671 break;
672 case MSR_EFER:
3bab1f5d 673 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 674#endif
675 case MSR_IA32_TIME_STAMP_COUNTER:
676 data = guest_read_tsc();
677 break;
678 case MSR_IA32_SYSENTER_CS:
679 data = vmcs_read32(GUEST_SYSENTER_CS);
680 break;
681 case MSR_IA32_SYSENTER_EIP:
f5b42c33 682 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 683 break;
684 case MSR_IA32_SYSENTER_ESP:
f5b42c33 685 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 686 break;
6aa8b732 687 default:
8b9cf98c 688 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 689 if (msr) {
690 data = msr->data;
691 break;
6aa8b732 692 }
3bab1f5d 693 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 694 }
695
696 *pdata = data;
697 return 0;
698}
699
700/*
701 * Writes msr value into into the appropriate "register".
702 * Returns 0 on success, non-0 otherwise.
703 * Assumes vcpu_load() was already called.
704 */
705static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
706{
a2fa3e9f
GH		 707 struct vcpu_vmx *vmx = to_vmx(vcpu);
708 struct kvm_msr_entry *msr;
2cc51560
ED		 709 int ret = 0;
710
6aa8b732 711 switch (msr_index) {
05b3e0c2 712#ifdef CONFIG_X86_64
3bab1f5d 713 case MSR_EFER:
2cc51560 714 ret = kvm_set_msr_common(vcpu, msr_index, data);
a2fa3e9f 715 if (vmx->host_state.loaded)
8b9cf98c 716 load_transition_efer(vmx);
2cc51560 717 break;
6aa8b732
AK		 718 case MSR_FS_BASE:
719 vmcs_writel(GUEST_FS_BASE, data);
720 break;
721 case MSR_GS_BASE:
722 vmcs_writel(GUEST_GS_BASE, data);
723 break;
724#endif
725 case MSR_IA32_SYSENTER_CS:
726 vmcs_write32(GUEST_SYSENTER_CS, data);
727 break;
728 case MSR_IA32_SYSENTER_EIP:
f5b42c33 729 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 730 break;
731 case MSR_IA32_SYSENTER_ESP:
f5b42c33 732 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 733 break;
d27d4aca 734 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 735 guest_write_tsc(data);
736 break;
6aa8b732 737 default:
8b9cf98c 738 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 739 if (msr) {
740 msr->data = data;
a2fa3e9f
GH		 741 if (vmx->host_state.loaded)
742 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 743 break;
6aa8b732 744 }
2cc51560 745 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 746 }
747
2cc51560 748 return ret;
6aa8b732
AK		 749}
750
751/*
752 * Sync the rsp and rip registers into the vcpu structure. This allows
753 * registers to be accessed by indexing vcpu->regs.
754 */
755static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
756{
757 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
758 vcpu->rip = vmcs_readl(GUEST_RIP);
759}
760
761/*
762 * Syncs rsp and rip back into the vmcs. Should be called after possible
763 * modification.
764 */
765static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
766{
767 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
768 vmcs_writel(GUEST_RIP, vcpu->rip);
769}
770
771static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
772{
773 unsigned long dr7 = 0x400;
6aa8b732
AK		 774 int old_singlestep;
775
6aa8b732
AK		 776 old_singlestep = vcpu->guest_debug.singlestep;
777
778 vcpu->guest_debug.enabled = dbg->enabled;
779 if (vcpu->guest_debug.enabled) {
780 int i;
781
782 dr7 |= 0x200; /* exact */
783 for (i = 0; i < 4; ++i) {
784 if (!dbg->breakpoints[i].enabled)
785 continue;
786 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
787 dr7 |= 2 << (i*2); /* global enable */
788 dr7 |= 0 << (i*4+16); /* execution breakpoint */
789 }
790
6aa8b732 791 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 792 } else
6aa8b732 793 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 794
795 if (old_singlestep && !vcpu->guest_debug.singlestep) {
796 unsigned long flags;
797
798 flags = vmcs_readl(GUEST_RFLAGS);
799 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
800 vmcs_writel(GUEST_RFLAGS, flags);
801 }
802
abd3f2d6 803 update_exception_bitmap(vcpu);
6aa8b732
AK		 804 vmcs_writel(GUEST_DR7, dr7);
805
806 return 0;
807}
808
2a8067f1
ED		 809static int vmx_get_irq(struct kvm_vcpu *vcpu)
810{
811 u32 idtv_info_field;
812
813 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
814 if (idtv_info_field & INTR_INFO_VALID_MASK) {
815 if (is_external_interrupt(idtv_info_field))
816 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
817 else
818 printk("pending exception: not handled yet\n");
819 }
820 return -1;
821}
822
6aa8b732
AK		 823static __init int cpu_has_kvm_support(void)
824{
825 unsigned long ecx = cpuid_ecx(1);
826 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
827}
828
829static __init int vmx_disabled_by_bios(void)
830{
831 u64 msr;
832
833 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 834 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
835 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
836 == MSR_IA32_FEATURE_CONTROL_LOCKED;
837 /* locked but not enabled */
6aa8b732
AK		 838}
839
774c47f1 840static void hardware_enable(void *garbage)
6aa8b732
AK		 841{
842 int cpu = raw_smp_processor_id();
843 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
844 u64 old;
845
846 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 847 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
848 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
849 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
850 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 851 /* enable and lock */
62b3ffb8
YS		 852 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
853 MSR_IA32_FEATURE_CONTROL_LOCKED |
854 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 855 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 856 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
857 : "memory", "cc");
858}
859
860static void hardware_disable(void *garbage)
861{
862 asm volatile (ASM_VMX_VMXOFF : : : "cc");
863}
864
1c3d14fe
YS		 865static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
866 u32 msr, u32* result)
867{
868 u32 vmx_msr_low, vmx_msr_high;
869 u32 ctl = ctl_min | ctl_opt;
870
871 rdmsr(msr, vmx_msr_low, vmx_msr_high);
872
873 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
874 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
875
876 /* Ensure minimum (required) set of control bits are supported. */
877 if (ctl_min & ~ctl)
002c7f7c 878 return -EIO;
1c3d14fe
YS		 879
880 *result = ctl;
881 return 0;
882}
883
002c7f7c 884static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 885{
886 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 887 u32 min, opt;
888 u32 _pin_based_exec_control = 0;
889 u32 _cpu_based_exec_control = 0;
890 u32 _vmexit_control = 0;
891 u32 _vmentry_control = 0;
892
893 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
894 opt = 0;
895 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
896 &_pin_based_exec_control) < 0)
002c7f7c 897 return -EIO;
1c3d14fe
YS		 898
899 min = CPU_BASED_HLT_EXITING |
900#ifdef CONFIG_X86_64
901 CPU_BASED_CR8_LOAD_EXITING |
902 CPU_BASED_CR8_STORE_EXITING |
903#endif
904 CPU_BASED_USE_IO_BITMAPS |
905 CPU_BASED_MOV_DR_EXITING |
906 CPU_BASED_USE_TSC_OFFSETING;
6e5d865c
YS		 907#ifdef CONFIG_X86_64
908 opt = CPU_BASED_TPR_SHADOW;
909#else
1c3d14fe 910 opt = 0;
6e5d865c 911#endif
1c3d14fe
YS		 912 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
913 &_cpu_based_exec_control) < 0)
002c7f7c 914 return -EIO;
6e5d865c
YS		 915#ifdef CONFIG_X86_64
916 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
917 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
918 ~CPU_BASED_CR8_STORE_EXITING;
919#endif
1c3d14fe
YS		 920
921 min = 0;
922#ifdef CONFIG_X86_64
923 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
924#endif
925 opt = 0;
926 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
927 &_vmexit_control) < 0)
002c7f7c 928 return -EIO;
1c3d14fe
YS		 929
930 min = opt = 0;
931 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
932 &_vmentry_control) < 0)
002c7f7c 933 return -EIO;
6aa8b732 934
c68876fd 935 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 936
937 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
938 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 939 return -EIO;
1c3d14fe
YS		 940
941#ifdef CONFIG_X86_64
942 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
943 if (vmx_msr_high & (1u<<16))
002c7f7c 944 return -EIO;
1c3d14fe
YS		 945#endif
946
947 /* Require Write-Back (WB) memory type for VMCS accesses. */
948 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 949 return -EIO;
1c3d14fe 950
002c7f7c
YS		 951 vmcs_conf->size = vmx_msr_high & 0x1fff;
952 vmcs_conf->order = get_order(vmcs_config.size);
953 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 954
002c7f7c
YS		 955 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
956 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
957 vmcs_conf->vmexit_ctrl = _vmexit_control;
958 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 959
960 return 0;
c68876fd 961}
6aa8b732
AK		 962
963static struct vmcs *alloc_vmcs_cpu(int cpu)
964{
965 int node = cpu_to_node(cpu);
966 struct page *pages;
967 struct vmcs *vmcs;
968
1c3d14fe 969 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 970 if (!pages)
971 return NULL;
972 vmcs = page_address(pages);
1c3d14fe
YS		 973 memset(vmcs, 0, vmcs_config.size);
974 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 975 return vmcs;
976}
977
978static struct vmcs *alloc_vmcs(void)
979{
d3b2c338 980 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 981}
982
983static void free_vmcs(struct vmcs *vmcs)
984{
1c3d14fe 985 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 986}
987
39959588 988static void free_kvm_area(void)
6aa8b732
AK		 989{
990 int cpu;
991
992 for_each_online_cpu(cpu)
993 free_vmcs(per_cpu(vmxarea, cpu));
994}
995
6aa8b732
AK		 996static __init int alloc_kvm_area(void)
997{
998 int cpu;
999
1000 for_each_online_cpu(cpu) {
1001 struct vmcs *vmcs;
1002
1003 vmcs = alloc_vmcs_cpu(cpu);
1004 if (!vmcs) {
1005 free_kvm_area();
1006 return -ENOMEM;
1007 }
1008
1009 per_cpu(vmxarea, cpu) = vmcs;
1010 }
1011 return 0;
1012}
1013
1014static __init int hardware_setup(void)
1015{
002c7f7c
YS		 1016 if (setup_vmcs_config(&vmcs_config) < 0)
1017 return -EIO;
6aa8b732
AK		 1018 return alloc_kvm_area();
1019}
1020
1021static __exit void hardware_unsetup(void)
1022{
1023 free_kvm_area();
1024}
1025
6aa8b732
AK		 1026static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1027{
1028 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1029
6af11b9e 1030 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1031 vmcs_write16(sf->selector, save->selector);
1032 vmcs_writel(sf->base, save->base);
1033 vmcs_write32(sf->limit, save->limit);
1034 vmcs_write32(sf->ar_bytes, save->ar);
1035 } else {
1036 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1037 << AR_DPL_SHIFT;
1038 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1039 }
1040}
1041
1042static void enter_pmode(struct kvm_vcpu *vcpu)
1043{
1044 unsigned long flags;
1045
1046 vcpu->rmode.active = 0;
1047
1048 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1049 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1050 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1051
1052 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1053 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
6aa8b732
AK		 1054 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1055 vmcs_writel(GUEST_RFLAGS, flags);
1056
66aee91a
RR		 1057 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1058 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1059
1060 update_exception_bitmap(vcpu);
1061
1062 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1063 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1064 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1065 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1066
1067 vmcs_write16(GUEST_SS_SELECTOR, 0);
1068 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1069
1070 vmcs_write16(GUEST_CS_SELECTOR,
1071 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1072 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1073}
1074
33f5fa16 1075static gva_t rmode_tss_base(struct kvm* kvm)
6aa8b732
AK		 1076{
1077 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1078 return base_gfn << PAGE_SHIFT;
1079}
1080
1081static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1082{
1083 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1084
1085 save->selector = vmcs_read16(sf->selector);
1086 save->base = vmcs_readl(sf->base);
1087 save->limit = vmcs_read32(sf->limit);
1088 save->ar = vmcs_read32(sf->ar_bytes);
1089 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1090 vmcs_write32(sf->limit, 0xffff);
1091 vmcs_write32(sf->ar_bytes, 0xf3);
1092}
1093
1094static void enter_rmode(struct kvm_vcpu *vcpu)
1095{
1096 unsigned long flags;
1097
1098 vcpu->rmode.active = 1;
1099
1100 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1101 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1102
1103 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1104 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1105
1106 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1107 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1108
1109 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1110 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1111
053de044 1112 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1113
1114 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1115 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1116 update_exception_bitmap(vcpu);
1117
1118 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1119 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1120 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1121
1122 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1123 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1124 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1125 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1126 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1127
1128 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1129 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1130 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1131 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01 1132
8668a3c4 1133 kvm_mmu_reset_context(vcpu);
75880a01 1134 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1135}
1136
05b3e0c2 1137#ifdef CONFIG_X86_64
6aa8b732
AK		 1138
1139static void enter_lmode(struct kvm_vcpu *vcpu)
1140{
1141 u32 guest_tr_ar;
1142
1143 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1144 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1145 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1146 __FUNCTION__);
1147 vmcs_write32(GUEST_TR_AR_BYTES,
1148 (guest_tr_ar & ~AR_TYPE_MASK)
1149 | AR_TYPE_BUSY_64_TSS);
1150 }
1151
1152 vcpu->shadow_efer |= EFER_LMA;
1153
8b9cf98c 1154 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1155 vmcs_write32(VM_ENTRY_CONTROLS,
1156 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1157 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1158}
1159
1160static void exit_lmode(struct kvm_vcpu *vcpu)
1161{
1162 vcpu->shadow_efer &= ~EFER_LMA;
1163
1164 vmcs_write32(VM_ENTRY_CONTROLS,
1165 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1166 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1167}
1168
1169#endif
1170
25c4c276 1171static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1172{
399badf3
AK		 1173 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1174 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1175}
1176
6aa8b732
AK		 1177static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1178{
5fd86fcf
AK		 1179 vmx_fpu_deactivate(vcpu);
1180
707d92fa 1181 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1182 enter_pmode(vcpu);
1183
707d92fa 1184 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1185 enter_rmode(vcpu);
1186
05b3e0c2 1187#ifdef CONFIG_X86_64
6aa8b732 1188 if (vcpu->shadow_efer & EFER_LME) {
707d92fa 1189 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1190 enter_lmode(vcpu);
707d92fa 1191 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1192 exit_lmode(vcpu);
1193 }
1194#endif
1195
1196 vmcs_writel(CR0_READ_SHADOW, cr0);
1197 vmcs_writel(GUEST_CR0,
1198 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1199 vcpu->cr0 = cr0;
5fd86fcf 1200
707d92fa 1201 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1202 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1203}
1204
6aa8b732
AK		 1205static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1206{
1207 vmcs_writel(GUEST_CR3, cr3);
707d92fa 1208 if (vcpu->cr0 & X86_CR0_PE)
5fd86fcf 1209 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1210}
1211
1212static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1213{
1214 vmcs_writel(CR4_READ_SHADOW, cr4);
1215 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1216 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1217 vcpu->cr4 = cr4;
1218}
1219
05b3e0c2 1220#ifdef CONFIG_X86_64
6aa8b732
AK		 1221
1222static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1223{
8b9cf98c
RR		 1224 struct vcpu_vmx *vmx = to_vmx(vcpu);
1225 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732
AK		 1226
1227 vcpu->shadow_efer = efer;
1228 if (efer & EFER_LMA) {
1229 vmcs_write32(VM_ENTRY_CONTROLS,
1230 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1231 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1232 msr->data = efer;
1233
1234 } else {
1235 vmcs_write32(VM_ENTRY_CONTROLS,
1236 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1237 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1238
1239 msr->data = efer & ~EFER_LME;
1240 }
8b9cf98c 1241 setup_msrs(vmx);
6aa8b732
AK		 1242}
1243
1244#endif
1245
1246static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1247{
1248 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1249
1250 return vmcs_readl(sf->base);
1251}
1252
1253static void vmx_get_segment(struct kvm_vcpu *vcpu,
1254 struct kvm_segment *var, int seg)
1255{
1256 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1257 u32 ar;
1258
1259 var->base = vmcs_readl(sf->base);
1260 var->limit = vmcs_read32(sf->limit);
1261 var->selector = vmcs_read16(sf->selector);
1262 ar = vmcs_read32(sf->ar_bytes);
1263 if (ar & AR_UNUSABLE_MASK)
1264 ar = 0;
1265 var->type = ar & 15;
1266 var->s = (ar >> 4) & 1;
1267 var->dpl = (ar >> 5) & 3;
1268 var->present = (ar >> 7) & 1;
1269 var->avl = (ar >> 12) & 1;
1270 var->l = (ar >> 13) & 1;
1271 var->db = (ar >> 14) & 1;
1272 var->g = (ar >> 15) & 1;
1273 var->unusable = (ar >> 16) & 1;
1274}
1275
653e3108 1276static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1277{
6aa8b732
AK		 1278 u32 ar;
1279
653e3108 1280 if (var->unusable)
6aa8b732
AK		 1281 ar = 1 << 16;
1282 else {
1283 ar = var->type & 15;
1284 ar |= (var->s & 1) << 4;
1285 ar |= (var->dpl & 3) << 5;
1286 ar |= (var->present & 1) << 7;
1287 ar |= (var->avl & 1) << 12;
1288 ar |= (var->l & 1) << 13;
1289 ar |= (var->db & 1) << 14;
1290 ar |= (var->g & 1) << 15;
1291 }
f7fbf1fd
UL		 1292 if (ar == 0) /* a 0 value means unusable */
1293 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1294
1295 return ar;
1296}
1297
1298static void vmx_set_segment(struct kvm_vcpu *vcpu,
1299 struct kvm_segment *var, int seg)
1300{
1301 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1302 u32 ar;
1303
1304 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1305 vcpu->rmode.tr.selector = var->selector;
1306 vcpu->rmode.tr.base = var->base;
1307 vcpu->rmode.tr.limit = var->limit;
1308 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1309 return;
1310 }
1311 vmcs_writel(sf->base, var->base);
1312 vmcs_write32(sf->limit, var->limit);
1313 vmcs_write16(sf->selector, var->selector);
1314 if (vcpu->rmode.active && var->s) {
1315 /*
1316 * Hack real-mode segments into vm86 compatibility.
1317 */
1318 if (var->base == 0xffff0000 && var->selector == 0xf000)
1319 vmcs_writel(sf->base, 0xf0000);
1320 ar = 0xf3;
1321 } else
1322 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1323 vmcs_write32(sf->ar_bytes, ar);
1324}
1325
6aa8b732
AK		 1326static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1327{
1328 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1329
1330 *db = (ar >> 14) & 1;
1331 *l = (ar >> 13) & 1;
1332}
1333
1334static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1335{
1336 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1337 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1338}
1339
1340static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1341{
1342 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1343 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1344}
1345
1346static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1347{
1348 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1349 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1350}
1351
1352static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1353{
1354 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1355 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1356}
1357
1358static int init_rmode_tss(struct kvm* kvm)
1359{
1360 struct page *p1, *p2, *p3;
1361 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1362 char *page;
1363
954bbbc2
AK		 1364 p1 = gfn_to_page(kvm, fn++);
1365 p2 = gfn_to_page(kvm, fn++);
1366 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1367
1368 if (!p1 || !p2 || !p3) {
1369 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1370 return 0;
1371 }
1372
1373 page = kmap_atomic(p1, KM_USER0);
a3870c47 1374 clear_page(page);
6aa8b732
AK		 1375 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1376 kunmap_atomic(page, KM_USER0);
1377
1378 page = kmap_atomic(p2, KM_USER0);
a3870c47 1379 clear_page(page);
6aa8b732
AK		 1380 kunmap_atomic(page, KM_USER0);
1381
1382 page = kmap_atomic(p3, KM_USER0);
a3870c47 1383 clear_page(page);
6aa8b732
AK		 1384 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1385 kunmap_atomic(page, KM_USER0);
1386
1387 return 1;
1388}
1389
6aa8b732
AK		 1390static void seg_setup(int seg)
1391{
1392 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1393
1394 vmcs_write16(sf->selector, 0);
1395 vmcs_writel(sf->base, 0);
1396 vmcs_write32(sf->limit, 0xffff);
1397 vmcs_write32(sf->ar_bytes, 0x93);
1398}
1399
1400/*
1401 * Sets up the vmcs for emulated real mode.
1402 */
8b9cf98c 1403static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1404{
1405 u32 host_sysenter_cs;
1406 u32 junk;
1407 unsigned long a;
1408 struct descriptor_table dt;
1409 int i;
1410 int ret = 0;
cd2276a7 1411 unsigned long kvm_vmx_return;
7017fc3d 1412 u64 msr;
6e5d865c 1413 u32 exec_control;
6aa8b732 1414
8b9cf98c 1415 if (!init_rmode_tss(vmx->vcpu.kvm)) {
6aa8b732
AK		 1416 ret = -ENOMEM;
1417 goto out;
1418 }
1419
c5ec1534
HQ		 1420 vmx->vcpu.rmode.active = 0;
1421
8b9cf98c 1422 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
7017fc3d
ED		 1423 set_cr8(&vmx->vcpu, 0);
1424 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
8b9cf98c 1425 if (vmx->vcpu.vcpu_id == 0)
7017fc3d
ED		 1426 msr |= MSR_IA32_APICBASE_BSP;
1427 kvm_set_apic_base(&vmx->vcpu, msr);
6aa8b732 1428
8b9cf98c 1429 fx_init(&vmx->vcpu);
6aa8b732
AK		 1430
1431 /*
1432 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1433 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1434 */
c5ec1534
HQ		 1435 if (vmx->vcpu.vcpu_id == 0) {
1436 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1437 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1438 } else {
1439 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1440 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1441 }
6aa8b732
AK		 1442 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1443 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1444
1445 seg_setup(VCPU_SREG_DS);
1446 seg_setup(VCPU_SREG_ES);
1447 seg_setup(VCPU_SREG_FS);
1448 seg_setup(VCPU_SREG_GS);
1449 seg_setup(VCPU_SREG_SS);
1450
1451 vmcs_write16(GUEST_TR_SELECTOR, 0);
1452 vmcs_writel(GUEST_TR_BASE, 0);
1453 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1454 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1455
1456 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1457 vmcs_writel(GUEST_LDTR_BASE, 0);
1458 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1459 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1460
1461 vmcs_write32(GUEST_SYSENTER_CS, 0);
1462 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1463 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1464
1465 vmcs_writel(GUEST_RFLAGS, 0x02);
c5ec1534
HQ		 1466 if (vmx->vcpu.vcpu_id == 0)
1467 vmcs_writel(GUEST_RIP, 0xfff0);
1468 else
1469 vmcs_writel(GUEST_RIP, 0);
6aa8b732
AK		 1470 vmcs_writel(GUEST_RSP, 0);
1471
6aa8b732
AK		 1472 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1473 vmcs_writel(GUEST_DR7, 0x400);
1474
1475 vmcs_writel(GUEST_GDTR_BASE, 0);
1476 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1477
1478 vmcs_writel(GUEST_IDTR_BASE, 0);
1479 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1480
1481 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1482 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1483 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1484
1485 /* I/O */
fdef3ad1
HQ		 1486 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1487 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1488
1489 guest_write_tsc(0);
1490
1491 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1492
1493 /* Special registers */
1494 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1495
1496 /* Control */
1c3d14fe
YS		 1497 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1498 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1499
1500 exec_control = vmcs_config.cpu_based_exec_ctrl;
1501 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1502 exec_control &= ~CPU_BASED_TPR_SHADOW;
1503#ifdef CONFIG_X86_64
1504 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1505 CPU_BASED_CR8_LOAD_EXITING;
1506#endif
1507 }
1508 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1509
6aa8b732
AK		 1510 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1511 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1512 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1513
1514 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1515 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1516 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1517
1518 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1519 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1520 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1521 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1522 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1523 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1524#ifdef CONFIG_X86_64
6aa8b732
AK		 1525 rdmsrl(MSR_FS_BASE, a);
1526 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1527 rdmsrl(MSR_GS_BASE, a);
1528 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1529#else
1530 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1531 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1532#endif
1533
1534 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1535
1536 get_idt(&dt);
1537 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1538
cd2276a7
AK		 1539 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1540 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1541 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1542 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1543 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1544
1545 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1546 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1547 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1548 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1549 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1550 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1551
6aa8b732
AK		 1552 for (i = 0; i < NR_VMX_MSR; ++i) {
1553 u32 index = vmx_msr_index[i];
1554 u32 data_low, data_high;
1555 u64 data;
a2fa3e9f 1556 int j = vmx->nmsrs;
6aa8b732
AK		 1557
1558 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1559 continue;
432bd6cb
AK		 1560 if (wrmsr_safe(index, data_low, data_high) < 0)
1561 continue;
6aa8b732 1562 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1563 vmx->host_msrs[j].index = index;
1564 vmx->host_msrs[j].reserved = 0;
1565 vmx->host_msrs[j].data = data;
1566 vmx->guest_msrs[j] = vmx->host_msrs[j];
1567 ++vmx->nmsrs;
6aa8b732 1568 }
6aa8b732 1569
8b9cf98c 1570 setup_msrs(vmx);
e38aea3e 1571
1c3d14fe 1572 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1573
1574 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1575 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1576
6aa8b732
AK		 1577 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1578
3b99ab24 1579#ifdef CONFIG_X86_64
6e5d865c
YS		 1580 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1581 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1582 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1583 page_to_phys(vmx->vcpu.apic->regs_page));
1584 vmcs_write32(TPR_THRESHOLD, 0);
3b99ab24 1585#endif
6aa8b732 1586
25c4c276 1587 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1588 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1589
8b9cf98c
RR		 1590 vmx->vcpu.cr0 = 0x60000010;
1591 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1592 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1593#ifdef CONFIG_X86_64
8b9cf98c 1594 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1595#endif
8b9cf98c
RR		 1596 vmx_fpu_activate(&vmx->vcpu);
1597 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1598
1599 return 0;
1600
6aa8b732
AK		 1601out:
1602 return ret;
1603}
1604
04d2cc77
AK		 1605static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1606{
1607 struct vcpu_vmx *vmx = to_vmx(vcpu);
1608
1609 vmx_vcpu_setup(vmx);
1610}
1611
6aa8b732
AK		 1612static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1613{
1614 u16 ent[2];
1615 u16 cs;
1616 u16 ip;
1617 unsigned long flags;
1618 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1619 u16 sp = vmcs_readl(GUEST_RSP);
1620 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1621
3964994b 1622 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1623 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1624 __FUNCTION__,
1625 vmcs_readl(GUEST_RSP),
1626 vmcs_readl(GUEST_SS_BASE),
1627 vmcs_read32(GUEST_SS_LIMIT));
1628 return;
1629 }
1630
e7d5d76c
LV		 1631 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1632 X86EMUL_CONTINUE) {
6aa8b732
AK		 1633 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1634 return;
1635 }
1636
1637 flags = vmcs_readl(GUEST_RFLAGS);
1638 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1639 ip = vmcs_readl(GUEST_RIP);
1640
1641
e7d5d76c
LV		 1642 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1643 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1644 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
6aa8b732
AK		 1645 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1646 return;
1647 }
1648
1649 vmcs_writel(GUEST_RFLAGS, flags &
1650 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1651 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1652 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1653 vmcs_writel(GUEST_RIP, ent[0]);
1654 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1655}
1656
85f455f7
ED		 1657static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1658{
1659 if (vcpu->rmode.active) {
1660 inject_rmode_irq(vcpu, irq);
1661 return;
1662 }
1663 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1664 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1665}
1666
6aa8b732
AK		 1667static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1668{
1669 int word_index = __ffs(vcpu->irq_summary);
1670 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1671 int irq = word_index * BITS_PER_LONG + bit_index;
1672
1673 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1674 if (!vcpu->irq_pending[word_index])
1675 clear_bit(word_index, &vcpu->irq_summary);
85f455f7 1676 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1677}
1678
c1150d8c
DL		 1679
1680static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1681 struct kvm_run *kvm_run)
6aa8b732 1682{
c1150d8c
DL		 1683 u32 cpu_based_vm_exec_control;
1684
1685 vcpu->interrupt_window_open =
1686 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1687 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1688
1689 if (vcpu->interrupt_window_open &&
1690 vcpu->irq_summary &&
1691 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1692 /*
c1150d8c 1693 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1694 */
1695 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1696
1697 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1698 if (!vcpu->interrupt_window_open &&
1699 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1700 /*
1701 * Interrupts blocked. Wait for unblock.
1702 */
c1150d8c
DL		 1703 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1704 else
1705 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1706 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1707}
1708
1709static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1710{
1711 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1712
1713 set_debugreg(dbg->bp[0], 0);
1714 set_debugreg(dbg->bp[1], 1);
1715 set_debugreg(dbg->bp[2], 2);
1716 set_debugreg(dbg->bp[3], 3);
1717
1718 if (dbg->singlestep) {
1719 unsigned long flags;
1720
1721 flags = vmcs_readl(GUEST_RFLAGS);
1722 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1723 vmcs_writel(GUEST_RFLAGS, flags);
1724 }
1725}
1726
1727static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1728 int vec, u32 err_code)
1729{
1730 if (!vcpu->rmode.active)
1731 return 0;
1732
b3f37707
NK		 1733 /*
1734 * Instruction with address size override prefix opcode 0x67
1735 * Cause the #SS fault with 0 error code in VM86 mode.
1736 */
1737 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
6aa8b732
AK		 1738 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1739 return 1;
1740 return 0;
1741}
1742
1743static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1744{
1745 u32 intr_info, error_code;
1746 unsigned long cr2, rip;
1747 u32 vect_info;
1748 enum emulation_result er;
e2dec939 1749 int r;
6aa8b732
AK		 1750
1751 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1752 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1753
1754 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1755 !is_page_fault(intr_info)) {
1756 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1757 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1758 }
1759
85f455f7 1760 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732
AK		 1761 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1762 set_bit(irq, vcpu->irq_pending);
1763 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1764 }
1765
1b6269db
AK		 1766 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1767 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 1768
1769 if (is_no_device(intr_info)) {
5fd86fcf 1770 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1771 return 1;
1772 }
1773
6aa8b732
AK		 1774 error_code = 0;
1775 rip = vmcs_readl(GUEST_RIP);
1776 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1777 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1778 if (is_page_fault(intr_info)) {
1779 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1780
11ec2804 1781 mutex_lock(&vcpu->kvm->lock);
e2dec939
AK		 1782 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1783 if (r < 0) {
11ec2804 1784 mutex_unlock(&vcpu->kvm->lock);
e2dec939
AK		 1785 return r;
1786 }
1787 if (!r) {
11ec2804 1788 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1789 return 1;
1790 }
1791
1792 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
11ec2804 1793 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1794
1795 switch (er) {
1796 case EMULATE_DONE:
1797 return 1;
1798 case EMULATE_DO_MMIO:
1165f5fe 1799 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1800 return 0;
1801 case EMULATE_FAIL:
054b1369 1802 kvm_report_emulation_failure(vcpu, "pagetable");
6aa8b732
AK		 1803 break;
1804 default:
1805 BUG();
1806 }
1807 }
1808
1809 if (vcpu->rmode.active &&
1810 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1811 error_code)) {
1812 if (vcpu->halt_request) {
1813 vcpu->halt_request = 0;
1814 return kvm_emulate_halt(vcpu);
1815 }
6aa8b732 1816 return 1;
72d6e5a0 1817 }
6aa8b732
AK		 1818
1819 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1820 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1821 return 0;
1822 }
1823 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1824 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1825 kvm_run->ex.error_code = error_code;
1826 return 0;
1827}
1828
1829static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1830 struct kvm_run *kvm_run)
1831{
1165f5fe 1832 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1833 return 1;
1834}
1835
988ad74f
AK		 1836static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1837{
1838 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1839 return 0;
1840}
6aa8b732 1841
6aa8b732
AK		 1842static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1843{
bfdaab09 1844 unsigned long exit_qualification;
039576c0
AK		 1845 int size, down, in, string, rep;
1846 unsigned port;
6aa8b732 1847
1165f5fe 1848 ++vcpu->stat.io_exits;
bfdaab09 1849 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 1850 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1851
1852 if (string) {
1853 if (emulate_instruction(vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1854 return 0;
1855 return 1;
1856 }
1857
1858 size = (exit_qualification & 7) + 1;
1859 in = (exit_qualification & 8) != 0;
039576c0 1860 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 1861 rep = (exit_qualification & 32) != 0;
1862 port = exit_qualification >> 16;
e70669ab 1863
3090dd73 1864 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1865}
1866
102d8325
IM		 1867static void
1868vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1869{
1870 /*
1871 * Patch in the VMCALL instruction:
1872 */
1873 hypercall[0] = 0x0f;
1874 hypercall[1] = 0x01;
1875 hypercall[2] = 0xc1;
1876 hypercall[3] = 0xc3;
1877}
1878
6aa8b732
AK		 1879static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1880{
bfdaab09 1881 unsigned long exit_qualification;
6aa8b732
AK		 1882 int cr;
1883 int reg;
1884
bfdaab09 1885 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1886 cr = exit_qualification & 15;
1887 reg = (exit_qualification >> 8) & 15;
1888 switch ((exit_qualification >> 4) & 3) {
1889 case 0: /* mov to cr */
1890 switch (cr) {
1891 case 0:
1892 vcpu_load_rsp_rip(vcpu);
1893 set_cr0(vcpu, vcpu->regs[reg]);
1894 skip_emulated_instruction(vcpu);
1895 return 1;
1896 case 3:
1897 vcpu_load_rsp_rip(vcpu);
1898 set_cr3(vcpu, vcpu->regs[reg]);
1899 skip_emulated_instruction(vcpu);
1900 return 1;
1901 case 4:
1902 vcpu_load_rsp_rip(vcpu);
1903 set_cr4(vcpu, vcpu->regs[reg]);
1904 skip_emulated_instruction(vcpu);
1905 return 1;
1906 case 8:
1907 vcpu_load_rsp_rip(vcpu);
1908 set_cr8(vcpu, vcpu->regs[reg]);
1909 skip_emulated_instruction(vcpu);
253abdee
YS		 1910 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1911 return 0;
6aa8b732
AK		 1912 };
1913 break;
25c4c276
AL		 1914 case 2: /* clts */
1915 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1916 vmx_fpu_deactivate(vcpu);
707d92fa 1917 vcpu->cr0 &= ~X86_CR0_TS;
2ab455cc 1918 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1919 vmx_fpu_activate(vcpu);
25c4c276
AL		 1920 skip_emulated_instruction(vcpu);
1921 return 1;
6aa8b732
AK		 1922 case 1: /*mov from cr*/
1923 switch (cr) {
1924 case 3:
1925 vcpu_load_rsp_rip(vcpu);
1926 vcpu->regs[reg] = vcpu->cr3;
1927 vcpu_put_rsp_rip(vcpu);
1928 skip_emulated_instruction(vcpu);
1929 return 1;
1930 case 8:
6aa8b732 1931 vcpu_load_rsp_rip(vcpu);
7017fc3d 1932 vcpu->regs[reg] = get_cr8(vcpu);
6aa8b732
AK		 1933 vcpu_put_rsp_rip(vcpu);
1934 skip_emulated_instruction(vcpu);
1935 return 1;
1936 }
1937 break;
1938 case 3: /* lmsw */
1939 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1940
1941 skip_emulated_instruction(vcpu);
1942 return 1;
1943 default:
1944 break;
1945 }
1946 kvm_run->exit_reason = 0;
f0242478 1947 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 1948 (int)(exit_qualification >> 4) & 3, cr);
1949 return 0;
1950}
1951
1952static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1953{
bfdaab09 1954 unsigned long exit_qualification;
6aa8b732
AK		 1955 unsigned long val;
1956 int dr, reg;
1957
1958 /*
1959 * FIXME: this code assumes the host is debugging the guest.
1960 * need to deal with guest debugging itself too.
1961 */
bfdaab09 1962 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1963 dr = exit_qualification & 7;
1964 reg = (exit_qualification >> 8) & 15;
1965 vcpu_load_rsp_rip(vcpu);
1966 if (exit_qualification & 16) {
1967 /* mov from dr */
1968 switch (dr) {
1969 case 6:
1970 val = 0xffff0ff0;
1971 break;
1972 case 7:
1973 val = 0x400;
1974 break;
1975 default:
1976 val = 0;
1977 }
1978 vcpu->regs[reg] = val;
1979 } else {
1980 /* mov to dr */
1981 }
1982 vcpu_put_rsp_rip(vcpu);
1983 skip_emulated_instruction(vcpu);
1984 return 1;
1985}
1986
1987static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1988{
06465c5a
AK		 1989 kvm_emulate_cpuid(vcpu);
1990 return 1;
6aa8b732
AK		 1991}
1992
1993static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1994{
1995 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1996 u64 data;
1997
1998 if (vmx_get_msr(vcpu, ecx, &data)) {
1999 vmx_inject_gp(vcpu, 0);
2000 return 1;
2001 }
2002
2003 /* FIXME: handling of bits 32:63 of rax, rdx */
2004 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2005 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2006 skip_emulated_instruction(vcpu);
2007 return 1;
2008}
2009
2010static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2011{
2012 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2013 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2014 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2015
2016 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2017 vmx_inject_gp(vcpu, 0);
2018 return 1;
2019 }
2020
2021 skip_emulated_instruction(vcpu);
2022 return 1;
2023}
2024
6e5d865c
YS		 2025static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2026 struct kvm_run *kvm_run)
2027{
2028 return 1;
2029}
2030
6aa8b732
AK		 2031static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2032 struct kvm_run *kvm_run)
2033{
85f455f7
ED		 2034 u32 cpu_based_vm_exec_control;
2035
2036 /* clear pending irq */
2037 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2038 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2039 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
c1150d8c
DL		 2040 /*
2041 * If the user space waits to inject interrupts, exit as soon as
2042 * possible
2043 */
2044 if (kvm_run->request_interrupt_window &&
022a9308 2045 !vcpu->irq_summary) {
c1150d8c 2046 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2047 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2048 return 0;
2049 }
6aa8b732
AK		 2050 return 1;
2051}
2052
2053static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2054{
2055 skip_emulated_instruction(vcpu);
d3bef15f 2056 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2057}
2058
c21415e8
IM		 2059static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2060{
510043da 2061 skip_emulated_instruction(vcpu);
270fd9b9 2062 return kvm_hypercall(vcpu, kvm_run);
c21415e8
IM		 2063}
2064
6aa8b732
AK		 2065/*
2066 * The exit handlers return 1 if the exit was handled fully and guest execution
2067 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2068 * to be done to userspace and return 0.
2069 */
2070static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2071 struct kvm_run *kvm_run) = {
2072 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2073 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2074 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2075 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2076 [EXIT_REASON_CR_ACCESS] = handle_cr,
2077 [EXIT_REASON_DR_ACCESS] = handle_dr,
2078 [EXIT_REASON_CPUID] = handle_cpuid,
2079 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2080 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2081 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2082 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2083 [EXIT_REASON_VMCALL] = handle_vmcall,
6e5d865c 2084 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold
6aa8b732
AK		 2085};
2086
2087static const int kvm_vmx_max_exit_handlers =
50a3485c 2088 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2089
2090/*
2091 * The guest has exited. See if we can fix it or if we need userspace
2092 * assistance.
2093 */
2094static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2095{
2096 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2097 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78
AK		 2098 struct vcpu_vmx *vmx = to_vmx(vcpu);
2099
2100 if (unlikely(vmx->fail)) {
2101 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2102 kvm_run->fail_entry.hardware_entry_failure_reason
2103 = vmcs_read32(VM_INSTRUCTION_ERROR);
2104 return 0;
2105 }
6aa8b732
AK		 2106
2107 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2108 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2109 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2110 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2111 if (exit_reason < kvm_vmx_max_exit_handlers
2112 && kvm_vmx_exit_handlers[exit_reason])
2113 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2114 else {
2115 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2116 kvm_run->hw.hardware_exit_reason = exit_reason;
2117 }
2118 return 0;
2119}
2120
d9e368d6
AK		 2121static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2122{
d9e368d6
AK		 2123}
2124
6e5d865c
YS		 2125static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2126{
2127 int max_irr, tpr;
2128
2129 if (!vm_need_tpr_shadow(vcpu->kvm))
2130 return;
2131
2132 if (!kvm_lapic_enabled(vcpu) ||
2133 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2134 vmcs_write32(TPR_THRESHOLD, 0);
2135 return;
2136 }
2137
2138 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2139 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2140}
2141
85f455f7
ED		 2142static void enable_irq_window(struct kvm_vcpu *vcpu)
2143{
2144 u32 cpu_based_vm_exec_control;
2145
2146 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2147 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2148 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2149}
2150
2151static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2152{
2153 u32 idtv_info_field, intr_info_field;
2154 int has_ext_irq, interrupt_window_open;
1b9778da 2155 int vector;
85f455f7 2156
1b9778da 2157 kvm_inject_pending_timer_irqs(vcpu);
6e5d865c
YS		 2158 update_tpr_threshold(vcpu);
2159
85f455f7
ED		 2160 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2161 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2162 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2163 if (intr_info_field & INTR_INFO_VALID_MASK) {
2164 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2165 /* TODO: fault when IDT_Vectoring */
2166 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2167 }
2168 if (has_ext_irq)
2169 enable_irq_window(vcpu);
2170 return;
2171 }
2172 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2173 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2174 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2175 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2176
2177 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2178 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2179 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2180 if (unlikely(has_ext_irq))
2181 enable_irq_window(vcpu);
2182 return;
2183 }
2184 if (!has_ext_irq)
2185 return;
2186 interrupt_window_open =
2187 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2188 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2189 if (interrupt_window_open) {
2190 vector = kvm_cpu_get_interrupt(vcpu);
2191 vmx_inject_irq(vcpu, vector);
2192 kvm_timer_intr_post(vcpu, vector);
2193 } else
85f455f7
ED		 2194 enable_irq_window(vcpu);
2195}
2196
04d2cc77 2197static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2198{
a2fa3e9f 2199 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2200 u32 intr_info;
e6adf283
AK		 2201
2202 /*
2203 * Loading guest fpu may have cleared host cr0.ts
2204 */
2205 vmcs_writel(HOST_CR0, read_cr0());
2206
6aa8b732
AK		 2207 asm (
2208 /* Store host registers */
05b3e0c2 2209#ifdef CONFIG_X86_64
6aa8b732
AK		 2210 "push %%rax; push %%rbx; push %%rdx;"
2211 "push %%rsi; push %%rdi; push %%rbp;"
2212 "push %%r8; push %%r9; push %%r10; push %%r11;"
2213 "push %%r12; push %%r13; push %%r14; push %%r15;"
2214 "push %%rcx \n\t"
2215 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2216#else
2217 "pusha; push %%ecx \n\t"
2218 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2219#endif
2220 /* Check if vmlaunch of vmresume is needed */
2221 "cmp $0, %1 \n\t"
2222 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2223#ifdef CONFIG_X86_64
6aa8b732
AK		 2224 "mov %c[cr2](%3), %%rax \n\t"
2225 "mov %%rax, %%cr2 \n\t"
2226 "mov %c[rax](%3), %%rax \n\t"
2227 "mov %c[rbx](%3), %%rbx \n\t"
2228 "mov %c[rdx](%3), %%rdx \n\t"
2229 "mov %c[rsi](%3), %%rsi \n\t"
2230 "mov %c[rdi](%3), %%rdi \n\t"
2231 "mov %c[rbp](%3), %%rbp \n\t"
2232 "mov %c[r8](%3), %%r8 \n\t"
2233 "mov %c[r9](%3), %%r9 \n\t"
2234 "mov %c[r10](%3), %%r10 \n\t"
2235 "mov %c[r11](%3), %%r11 \n\t"
2236 "mov %c[r12](%3), %%r12 \n\t"
2237 "mov %c[r13](%3), %%r13 \n\t"
2238 "mov %c[r14](%3), %%r14 \n\t"
2239 "mov %c[r15](%3), %%r15 \n\t"
2240 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2241#else
2242 "mov %c[cr2](%3), %%eax \n\t"
2243 "mov %%eax, %%cr2 \n\t"
2244 "mov %c[rax](%3), %%eax \n\t"
2245 "mov %c[rbx](%3), %%ebx \n\t"
2246 "mov %c[rdx](%3), %%edx \n\t"
2247 "mov %c[rsi](%3), %%esi \n\t"
2248 "mov %c[rdi](%3), %%edi \n\t"
2249 "mov %c[rbp](%3), %%ebp \n\t"
2250 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2251#endif
2252 /* Enter guest mode */
cd2276a7 2253 "jne .Llaunched \n\t"
6aa8b732 2254 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2255 "jmp .Lkvm_vmx_return \n\t"
2256 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2257 ".Lkvm_vmx_return: "
6aa8b732 2258 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2259#ifdef CONFIG_X86_64
96958231 2260 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2261 "mov %%rax, %c[rax](%3) \n\t"
2262 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2263 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2264 "mov %%rdx, %c[rdx](%3) \n\t"
2265 "mov %%rsi, %c[rsi](%3) \n\t"
2266 "mov %%rdi, %c[rdi](%3) \n\t"
2267 "mov %%rbp, %c[rbp](%3) \n\t"
2268 "mov %%r8, %c[r8](%3) \n\t"
2269 "mov %%r9, %c[r9](%3) \n\t"
2270 "mov %%r10, %c[r10](%3) \n\t"
2271 "mov %%r11, %c[r11](%3) \n\t"
2272 "mov %%r12, %c[r12](%3) \n\t"
2273 "mov %%r13, %c[r13](%3) \n\t"
2274 "mov %%r14, %c[r14](%3) \n\t"
2275 "mov %%r15, %c[r15](%3) \n\t"
2276 "mov %%cr2, %%rax \n\t"
2277 "mov %%rax, %c[cr2](%3) \n\t"
96958231 2278 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 2279
2280 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2281 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2282 "pop %%rbp; pop %%rdi; pop %%rsi;"
2283 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2284#else
96958231 2285 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2286 "mov %%eax, %c[rax](%3) \n\t"
2287 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2288 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2289 "mov %%edx, %c[rdx](%3) \n\t"
2290 "mov %%esi, %c[rsi](%3) \n\t"
2291 "mov %%edi, %c[rdi](%3) \n\t"
2292 "mov %%ebp, %c[rbp](%3) \n\t"
2293 "mov %%cr2, %%eax \n\t"
2294 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2295 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2296
2297 "pop %%ecx; popa \n\t"
2298#endif
2299 "setbe %0 \n\t"
29bd8a78 2300 : "=q" (vmx->fail)
a2fa3e9f 2301 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
6aa8b732
AK		 2302 "c"(vcpu),
2303 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2304 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2305 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2306 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2307 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2308 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2309 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2310#ifdef CONFIG_X86_64
6aa8b732
AK		 2311 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2312 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2313 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2314 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2315 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2316 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2317 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2318 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2319#endif
2320 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2321 : "cc", "memory" );
2322
c1150d8c 2323 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2324
6aa8b732 2325 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2326 vmx->launched = 1;
1b6269db
AK		 2327
2328 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2329
2330 /* We need to handle NMIs before interrupts are enabled */
2331 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2332 asm("int $2");
6aa8b732
AK		 2333}
2334
6aa8b732
AK		 2335static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2336 unsigned long addr,
2337 u32 err_code)
2338{
2339 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2340
1165f5fe 2341 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2342
2343 if (is_page_fault(vect_info)) {
2344 printk(KERN_DEBUG "inject_page_fault: "
2345 "double fault 0x%lx @ 0x%lx\n",
2346 addr, vmcs_readl(GUEST_RIP));
2347 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2348 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2349 DF_VECTOR |
2350 INTR_TYPE_EXCEPTION |
2351 INTR_INFO_DELIEVER_CODE_MASK |
2352 INTR_INFO_VALID_MASK);
2353 return;
2354 }
2355 vcpu->cr2 = addr;
2356 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2357 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2358 PF_VECTOR |
2359 INTR_TYPE_EXCEPTION |
2360 INTR_INFO_DELIEVER_CODE_MASK |
2361 INTR_INFO_VALID_MASK);
2362
2363}
2364
2365static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2366{
a2fa3e9f
GH		 2367 struct vcpu_vmx *vmx = to_vmx(vcpu);
2368
2369 if (vmx->vmcs) {
8b9cf98c 2370 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2371 free_vmcs(vmx->vmcs);
2372 vmx->vmcs = NULL;
6aa8b732
AK		 2373 }
2374}
2375
2376static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2377{
fb3f0f51
RR		 2378 struct vcpu_vmx *vmx = to_vmx(vcpu);
2379
6aa8b732 2380 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2381 kfree(vmx->host_msrs);
2382 kfree(vmx->guest_msrs);
2383 kvm_vcpu_uninit(vcpu);
a4770347 2384 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2385}
2386
fb3f0f51 2387static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2388{
fb3f0f51 2389 int err;
c16f862d 2390 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2391 int cpu;
6aa8b732 2392
a2fa3e9f 2393 if (!vmx)
fb3f0f51
RR		 2394 return ERR_PTR(-ENOMEM);
2395
2396 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2397 if (err)
2398 goto free_vcpu;
965b58a5 2399
97222cc8
ED		 2400 if (irqchip_in_kernel(kvm)) {
2401 err = kvm_create_lapic(&vmx->vcpu);
2402 if (err < 0)
2403 goto free_vcpu;
2404 }
2405
a2fa3e9f 2406 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2407 if (!vmx->guest_msrs) {
2408 err = -ENOMEM;
2409 goto uninit_vcpu;
2410 }
965b58a5 2411
a2fa3e9f
GH		 2412 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2413 if (!vmx->host_msrs)
fb3f0f51 2414 goto free_guest_msrs;
965b58a5 2415
a2fa3e9f
GH		 2416 vmx->vmcs = alloc_vmcs();
2417 if (!vmx->vmcs)
fb3f0f51 2418 goto free_msrs;
a2fa3e9f
GH		 2419
2420 vmcs_clear(vmx->vmcs);
2421
15ad7146
AK		 2422 cpu = get_cpu();
2423 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2424 err = vmx_vcpu_setup(vmx);
fb3f0f51 2425 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2426 put_cpu();
fb3f0f51
RR		 2427 if (err)
2428 goto free_vmcs;
2429
2430 return &vmx->vcpu;
2431
2432free_vmcs:
2433 free_vmcs(vmx->vmcs);
2434free_msrs:
2435 kfree(vmx->host_msrs);
2436free_guest_msrs:
2437 kfree(vmx->guest_msrs);
2438uninit_vcpu:
2439 kvm_vcpu_uninit(&vmx->vcpu);
2440free_vcpu:
a4770347 2441 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2442 return ERR_PTR(err);
6aa8b732
AK		 2443}
2444
002c7f7c
YS		 2445static void __init vmx_check_processor_compat(void *rtn)
2446{
2447 struct vmcs_config vmcs_conf;
2448
2449 *(int *)rtn = 0;
2450 if (setup_vmcs_config(&vmcs_conf) < 0)
2451 *(int *)rtn = -EIO;
2452 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2453 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2454 smp_processor_id());
2455 *(int *)rtn = -EIO;
2456 }
2457}
2458
cbdd1bea 2459static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2460 .cpu_has_kvm_support = cpu_has_kvm_support,
2461 .disabled_by_bios = vmx_disabled_by_bios,
2462 .hardware_setup = hardware_setup,
2463 .hardware_unsetup = hardware_unsetup,
002c7f7c 2464 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2465 .hardware_enable = hardware_enable,
2466 .hardware_disable = hardware_disable,
2467
2468 .vcpu_create = vmx_create_vcpu,
2469 .vcpu_free = vmx_free_vcpu,
04d2cc77 2470 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2471
04d2cc77 2472 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2473 .vcpu_load = vmx_vcpu_load,
2474 .vcpu_put = vmx_vcpu_put,
774c47f1 2475 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2476
2477 .set_guest_debug = set_guest_debug,
04d2cc77 2478 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2479 .get_msr = vmx_get_msr,
2480 .set_msr = vmx_set_msr,
2481 .get_segment_base = vmx_get_segment_base,
2482 .get_segment = vmx_get_segment,
2483 .set_segment = vmx_set_segment,
6aa8b732 2484 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2485 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2486 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2487 .set_cr3 = vmx_set_cr3,
2488 .set_cr4 = vmx_set_cr4,
05b3e0c2 2489#ifdef CONFIG_X86_64
6aa8b732
AK		 2490 .set_efer = vmx_set_efer,
2491#endif
2492 .get_idt = vmx_get_idt,
2493 .set_idt = vmx_set_idt,
2494 .get_gdt = vmx_get_gdt,
2495 .set_gdt = vmx_set_gdt,
2496 .cache_regs = vcpu_load_rsp_rip,
2497 .decache_regs = vcpu_put_rsp_rip,
2498 .get_rflags = vmx_get_rflags,
2499 .set_rflags = vmx_set_rflags,
2500
2501 .tlb_flush = vmx_flush_tlb,
2502 .inject_page_fault = vmx_inject_page_fault,
2503
2504 .inject_gp = vmx_inject_gp,
2505
2506 .run = vmx_vcpu_run,
04d2cc77 2507 .handle_exit = kvm_handle_exit,
6aa8b732 2508 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2509 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2510 .get_irq = vmx_get_irq,
2511 .set_irq = vmx_inject_irq,
04d2cc77
AK		 2512 .inject_pending_irq = vmx_intr_assist,
2513 .inject_pending_vectors = do_interrupt_requests,
6aa8b732
AK		 2514};
2515
2516static int __init vmx_init(void)
2517{
fdef3ad1
HQ		 2518 void *iova;
2519 int r;
2520
2521 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2522 if (!vmx_io_bitmap_a)
2523 return -ENOMEM;
2524
2525 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2526 if (!vmx_io_bitmap_b) {
2527 r = -ENOMEM;
2528 goto out;
2529 }
2530
2531 /*
2532 * Allow direct access to the PC debug port (it is often used for I/O
2533 * delays, but the vmexits simply slow things down).
2534 */
2535 iova = kmap(vmx_io_bitmap_a);
2536 memset(iova, 0xff, PAGE_SIZE);
2537 clear_bit(0x80, iova);
cd0536d7 2538 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2539
2540 iova = kmap(vmx_io_bitmap_b);
2541 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2542 kunmap(vmx_io_bitmap_b);
fdef3ad1 2543
cbdd1bea 2544 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2545 if (r)
2546 goto out1;
2547
2548 return 0;
2549
2550out1:
2551 __free_page(vmx_io_bitmap_b);
2552out:
2553 __free_page(vmx_io_bitmap_a);
2554 return r;
6aa8b732
AK		 2555}
2556
2557static void __exit vmx_exit(void)
2558{
fdef3ad1
HQ		 2559 __free_page(vmx_io_bitmap_b);
2560 __free_page(vmx_io_bitmap_a);
2561
cbdd1bea 2562 kvm_exit_x86();
6aa8b732
AK		 2563}
2564
2565module_init(vmx_init)
2566module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)