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KVM: MMU: do not iterate over all VMs in mmu_shrink()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
476bc001 77static bool __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
8bf00a52 130#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 131#define VMCS02_POOL_SIZE 1
61d2ef2c 132
a2fa3e9f
GH		 133struct vmcs {
134 u32 revision_id;
135 u32 abort;
136 char data[0];
137};
138
d462b819
NHE		 139/*
140 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142 * loaded on this CPU (so we can clear them if the CPU goes down).
143 */
144struct loaded_vmcs {
145 struct vmcs *vmcs;
146 int cpu;
147 int launched;
148 struct list_head loaded_vmcss_on_cpu_link;
149};
150
26bb0981
AK		 151struct shared_msr_entry {
152 unsigned index;
153 u64 data;
d5696725 154 u64 mask;
26bb0981
AK		 155};
156
a9d30f33
NHE		 157/*
158 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163 * More than one of these structures may exist, if L1 runs multiple L2 guests.
164 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165 * underlying hardware which will be used to run L2.
166 * This structure is packed to ensure that its layout is identical across
167 * machines (necessary for live migration).
168 * If there are changes in this struct, VMCS12_REVISION must be changed.
169 */
22bd0358 170typedef u64 natural_width;
a9d30f33
NHE		 171struct __packed vmcs12 {
172 /* According to the Intel spec, a VMCS region must start with the
173 * following two fields. Then follow implementation-specific data.
174 */
175 u32 revision_id;
176 u32 abort;
22bd0358 177
27d6c865
NHE		 178 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179 u32 padding[7]; /* room for future expansion */
180
22bd0358
NHE		 181 u64 io_bitmap_a;
182 u64 io_bitmap_b;
183 u64 msr_bitmap;
184 u64 vm_exit_msr_store_addr;
185 u64 vm_exit_msr_load_addr;
186 u64 vm_entry_msr_load_addr;
187 u64 tsc_offset;
188 u64 virtual_apic_page_addr;
189 u64 apic_access_addr;
190 u64 ept_pointer;
191 u64 guest_physical_address;
192 u64 vmcs_link_pointer;
193 u64 guest_ia32_debugctl;
194 u64 guest_ia32_pat;
195 u64 guest_ia32_efer;
196 u64 guest_ia32_perf_global_ctrl;
197 u64 guest_pdptr0;
198 u64 guest_pdptr1;
199 u64 guest_pdptr2;
200 u64 guest_pdptr3;
201 u64 host_ia32_pat;
202 u64 host_ia32_efer;
203 u64 host_ia32_perf_global_ctrl;
204 u64 padding64[8]; /* room for future expansion */
205 /*
206 * To allow migration of L1 (complete with its L2 guests) between
207 * machines of different natural widths (32 or 64 bit), we cannot have
208 * unsigned long fields with no explict size. We use u64 (aliased
209 * natural_width) instead. Luckily, x86 is little-endian.
210 */
211 natural_width cr0_guest_host_mask;
212 natural_width cr4_guest_host_mask;
213 natural_width cr0_read_shadow;
214 natural_width cr4_read_shadow;
215 natural_width cr3_target_value0;
216 natural_width cr3_target_value1;
217 natural_width cr3_target_value2;
218 natural_width cr3_target_value3;
219 natural_width exit_qualification;
220 natural_width guest_linear_address;
221 natural_width guest_cr0;
222 natural_width guest_cr3;
223 natural_width guest_cr4;
224 natural_width guest_es_base;
225 natural_width guest_cs_base;
226 natural_width guest_ss_base;
227 natural_width guest_ds_base;
228 natural_width guest_fs_base;
229 natural_width guest_gs_base;
230 natural_width guest_ldtr_base;
231 natural_width guest_tr_base;
232 natural_width guest_gdtr_base;
233 natural_width guest_idtr_base;
234 natural_width guest_dr7;
235 natural_width guest_rsp;
236 natural_width guest_rip;
237 natural_width guest_rflags;
238 natural_width guest_pending_dbg_exceptions;
239 natural_width guest_sysenter_esp;
240 natural_width guest_sysenter_eip;
241 natural_width host_cr0;
242 natural_width host_cr3;
243 natural_width host_cr4;
244 natural_width host_fs_base;
245 natural_width host_gs_base;
246 natural_width host_tr_base;
247 natural_width host_gdtr_base;
248 natural_width host_idtr_base;
249 natural_width host_ia32_sysenter_esp;
250 natural_width host_ia32_sysenter_eip;
251 natural_width host_rsp;
252 natural_width host_rip;
253 natural_width paddingl[8]; /* room for future expansion */
254 u32 pin_based_vm_exec_control;
255 u32 cpu_based_vm_exec_control;
256 u32 exception_bitmap;
257 u32 page_fault_error_code_mask;
258 u32 page_fault_error_code_match;
259 u32 cr3_target_count;
260 u32 vm_exit_controls;
261 u32 vm_exit_msr_store_count;
262 u32 vm_exit_msr_load_count;
263 u32 vm_entry_controls;
264 u32 vm_entry_msr_load_count;
265 u32 vm_entry_intr_info_field;
266 u32 vm_entry_exception_error_code;
267 u32 vm_entry_instruction_len;
268 u32 tpr_threshold;
269 u32 secondary_vm_exec_control;
270 u32 vm_instruction_error;
271 u32 vm_exit_reason;
272 u32 vm_exit_intr_info;
273 u32 vm_exit_intr_error_code;
274 u32 idt_vectoring_info_field;
275 u32 idt_vectoring_error_code;
276 u32 vm_exit_instruction_len;
277 u32 vmx_instruction_info;
278 u32 guest_es_limit;
279 u32 guest_cs_limit;
280 u32 guest_ss_limit;
281 u32 guest_ds_limit;
282 u32 guest_fs_limit;
283 u32 guest_gs_limit;
284 u32 guest_ldtr_limit;
285 u32 guest_tr_limit;
286 u32 guest_gdtr_limit;
287 u32 guest_idtr_limit;
288 u32 guest_es_ar_bytes;
289 u32 guest_cs_ar_bytes;
290 u32 guest_ss_ar_bytes;
291 u32 guest_ds_ar_bytes;
292 u32 guest_fs_ar_bytes;
293 u32 guest_gs_ar_bytes;
294 u32 guest_ldtr_ar_bytes;
295 u32 guest_tr_ar_bytes;
296 u32 guest_interruptibility_info;
297 u32 guest_activity_state;
298 u32 guest_sysenter_cs;
299 u32 host_ia32_sysenter_cs;
300 u32 padding32[8]; /* room for future expansion */
301 u16 virtual_processor_id;
302 u16 guest_es_selector;
303 u16 guest_cs_selector;
304 u16 guest_ss_selector;
305 u16 guest_ds_selector;
306 u16 guest_fs_selector;
307 u16 guest_gs_selector;
308 u16 guest_ldtr_selector;
309 u16 guest_tr_selector;
310 u16 host_es_selector;
311 u16 host_cs_selector;
312 u16 host_ss_selector;
313 u16 host_ds_selector;
314 u16 host_fs_selector;
315 u16 host_gs_selector;
316 u16 host_tr_selector;
a9d30f33
NHE		 317};
318
319/*
320 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
323 */
324#define VMCS12_REVISION 0x11e57ed0
325
326/*
327 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329 * current implementation, 4K are reserved to avoid future complications.
330 */
331#define VMCS12_SIZE 0x1000
332
ff2f6fe9
NHE		 333/* Used to remember the last vmcs02 used for some recently used vmcs12s */
334struct vmcs02_list {
335 struct list_head list;
336 gpa_t vmptr;
337 struct loaded_vmcs vmcs02;
338};
339
ec378aee
NHE		 340/*
341 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
343 */
344struct nested_vmx {
345 /* Has the level1 guest done vmxon? */
346 bool vmxon;
a9d30f33
NHE		 347
348 /* The guest-physical address of the current VMCS L1 keeps for L2 */
349 gpa_t current_vmptr;
350 /* The host-usable pointer to the above */
351 struct page *current_vmcs12_page;
352 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 353
354 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355 struct list_head vmcs02_pool;
356 int vmcs02_num;
fe3ef05c 357 u64 vmcs01_tsc_offset;
644d711a
NHE		 358 /* L2 must run next, and mustn't decide to exit to L1. */
359 bool nested_run_pending;
fe3ef05c
NHE		 360 /*
361 * Guest pages referred to in vmcs02 with host-physical pointers, so
362 * we must keep them pinned while L2 runs.
363 */
364 struct page *apic_access_page;
ec378aee
NHE		 365};
366
a2fa3e9f 367struct vcpu_vmx {
fb3f0f51 368 struct kvm_vcpu vcpu;
313dbd49 369 unsigned long host_rsp;
29bd8a78 370 u8 fail;
69c73028 371 u8 cpl;
9d58b931 372 bool nmi_known_unmasked;
51aa01d1 373 u32 exit_intr_info;
1155f76a 374 u32 idt_vectoring_info;
6de12732 375 ulong rflags;
26bb0981 376 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 377 int nmsrs;
378 int save_nmsrs;
a2fa3e9f 379#ifdef CONFIG_X86_64
44ea2b17
AK		 380 u64 msr_host_kernel_gs_base;
381 u64 msr_guest_kernel_gs_base;
a2fa3e9f 382#endif
d462b819
NHE		 383 /*
384 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385 * non-nested (L1) guest, it always points to vmcs01. For a nested
386 * guest (L2), it points to a different VMCS.
387 */
388 struct loaded_vmcs vmcs01;
389 struct loaded_vmcs *loaded_vmcs;
390 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 391 struct msr_autoload {
392 unsigned nr;
393 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
394 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
395 } msr_autoload;
a2fa3e9f
GH		 396 struct {
397 int loaded;
398 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 399#ifdef CONFIG_X86_64
400 u16 ds_sel, es_sel;
401#endif
152d3f2f
LV		 402 int gs_ldt_reload_needed;
403 int fs_reload_needed;
d77c26fc 404 } host_state;
9c8cba37 405 struct {
7ffd92c5 406 int vm86_active;
78ac8b47 407 ulong save_rflags;
7ffd92c5
AK		 408 struct kvm_save_segment {
409 u16 selector;
410 unsigned long base;
411 u32 limit;
412 u32 ar;
413 } tr, es, ds, fs, gs;
9c8cba37 414 } rmode;
2fb92db1
AK		 415 struct {
416 u32 bitmask; /* 4 bits per segment (1 bit per field) */
417 struct kvm_save_segment seg[8];
418 } segment_cache;
2384d2b3 419 int vpid;
04fa4d32 420 bool emulation_required;
3b86cd99
JK		 421
422 /* Support for vnmi-less CPUs */
423 int soft_vnmi_blocked;
424 ktime_t entry_time;
425 s64 vnmi_blocked_time;
a0861c02 426 u32 exit_reason;
4e47c7a6
SY		 427
428 bool rdtscp_enabled;
ec378aee
NHE		 429
430 /* Support for a guest hypervisor (nested VMX) */
431 struct nested_vmx nested;
a2fa3e9f
GH		 432};
433
2fb92db1
AK		 434enum segment_cache_field {
435 SEG_FIELD_SEL = 0,
436 SEG_FIELD_BASE = 1,
437 SEG_FIELD_LIMIT = 2,
438 SEG_FIELD_AR = 3,
439
440 SEG_FIELD_NR = 4
441};
442
a2fa3e9f
GH		 443static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
444{
fb3f0f51 445 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 446}
447
22bd0358
NHE		 448#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
450#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
451 [number##_HIGH] = VMCS12_OFFSET(name)+4
452
453static unsigned short vmcs_field_to_offset_table[] = {
454 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
455 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
456 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
457 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
458 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
459 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
460 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
461 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
462 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
463 FIELD(HOST_ES_SELECTOR, host_es_selector),
464 FIELD(HOST_CS_SELECTOR, host_cs_selector),
465 FIELD(HOST_SS_SELECTOR, host_ss_selector),
466 FIELD(HOST_DS_SELECTOR, host_ds_selector),
467 FIELD(HOST_FS_SELECTOR, host_fs_selector),
468 FIELD(HOST_GS_SELECTOR, host_gs_selector),
469 FIELD(HOST_TR_SELECTOR, host_tr_selector),
470 FIELD64(IO_BITMAP_A, io_bitmap_a),
471 FIELD64(IO_BITMAP_B, io_bitmap_b),
472 FIELD64(MSR_BITMAP, msr_bitmap),
473 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
474 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
475 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
476 FIELD64(TSC_OFFSET, tsc_offset),
477 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
478 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
479 FIELD64(EPT_POINTER, ept_pointer),
480 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
481 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
482 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
483 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
484 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
485 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
486 FIELD64(GUEST_PDPTR0, guest_pdptr0),
487 FIELD64(GUEST_PDPTR1, guest_pdptr1),
488 FIELD64(GUEST_PDPTR2, guest_pdptr2),
489 FIELD64(GUEST_PDPTR3, guest_pdptr3),
490 FIELD64(HOST_IA32_PAT, host_ia32_pat),
491 FIELD64(HOST_IA32_EFER, host_ia32_efer),
492 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
493 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
494 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
495 FIELD(EXCEPTION_BITMAP, exception_bitmap),
496 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
497 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
498 FIELD(CR3_TARGET_COUNT, cr3_target_count),
499 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
500 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
501 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
502 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
503 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
504 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
505 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
506 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
507 FIELD(TPR_THRESHOLD, tpr_threshold),
508 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
509 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
510 FIELD(VM_EXIT_REASON, vm_exit_reason),
511 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
512 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
513 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
514 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
515 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
516 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
517 FIELD(GUEST_ES_LIMIT, guest_es_limit),
518 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
519 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
520 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
521 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
522 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
523 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
524 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
525 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
526 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
527 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
528 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
529 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
530 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
531 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
532 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
533 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
534 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
535 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
536 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
537 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
538 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
539 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
540 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
541 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
542 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
543 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
544 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
545 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
546 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
547 FIELD(EXIT_QUALIFICATION, exit_qualification),
548 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
549 FIELD(GUEST_CR0, guest_cr0),
550 FIELD(GUEST_CR3, guest_cr3),
551 FIELD(GUEST_CR4, guest_cr4),
552 FIELD(GUEST_ES_BASE, guest_es_base),
553 FIELD(GUEST_CS_BASE, guest_cs_base),
554 FIELD(GUEST_SS_BASE, guest_ss_base),
555 FIELD(GUEST_DS_BASE, guest_ds_base),
556 FIELD(GUEST_FS_BASE, guest_fs_base),
557 FIELD(GUEST_GS_BASE, guest_gs_base),
558 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
559 FIELD(GUEST_TR_BASE, guest_tr_base),
560 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
561 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
562 FIELD(GUEST_DR7, guest_dr7),
563 FIELD(GUEST_RSP, guest_rsp),
564 FIELD(GUEST_RIP, guest_rip),
565 FIELD(GUEST_RFLAGS, guest_rflags),
566 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
567 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
568 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
569 FIELD(HOST_CR0, host_cr0),
570 FIELD(HOST_CR3, host_cr3),
571 FIELD(HOST_CR4, host_cr4),
572 FIELD(HOST_FS_BASE, host_fs_base),
573 FIELD(HOST_GS_BASE, host_gs_base),
574 FIELD(HOST_TR_BASE, host_tr_base),
575 FIELD(HOST_GDTR_BASE, host_gdtr_base),
576 FIELD(HOST_IDTR_BASE, host_idtr_base),
577 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
578 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
579 FIELD(HOST_RSP, host_rsp),
580 FIELD(HOST_RIP, host_rip),
581};
582static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
583
584static inline short vmcs_field_to_offset(unsigned long field)
585{
586 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
587 return -1;
588 return vmcs_field_to_offset_table[field];
589}
590
a9d30f33
NHE		 591static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
592{
593 return to_vmx(vcpu)->nested.current_vmcs12;
594}
595
596static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
597{
598 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
599 if (is_error_page(page)) {
600 kvm_release_page_clean(page);
601 return NULL;
602 }
603 return page;
604}
605
606static void nested_release_page(struct page *page)
607{
608 kvm_release_page_dirty(page);
609}
610
611static void nested_release_page_clean(struct page *page)
612{
613 kvm_release_page_clean(page);
614}
615
4e1096d2 616static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 617static void kvm_cpu_vmxon(u64 addr);
618static void kvm_cpu_vmxoff(void);
aff48baa 619static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 620static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 621
6aa8b732
AK		 622static DEFINE_PER_CPU(struct vmcs *, vmxarea);
623static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 624/*
625 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
626 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
627 */
628static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 629static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 630
3e7c73e9
AK		 631static unsigned long *vmx_io_bitmap_a;
632static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 633static unsigned long *vmx_msr_bitmap_legacy;
634static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 635
110312c8 636static bool cpu_has_load_ia32_efer;
8bf00a52 637static bool cpu_has_load_perf_global_ctrl;
110312c8 638
2384d2b3
SY		 639static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
640static DEFINE_SPINLOCK(vmx_vpid_lock);
641
1c3d14fe 642static struct vmcs_config {
6aa8b732
AK		 643 int size;
644 int order;
645 u32 revision_id;
1c3d14fe
YS		 646 u32 pin_based_exec_ctrl;
647 u32 cpu_based_exec_ctrl;
f78e0e2e 648 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 649 u32 vmexit_ctrl;
650 u32 vmentry_ctrl;
651} vmcs_config;
6aa8b732 652
efff9e53 653static struct vmx_capability {
d56f546d
SY		 654 u32 ept;
655 u32 vpid;
656} vmx_capability;
657
6aa8b732
AK		 658#define VMX_SEGMENT_FIELD(seg) \
659 [VCPU_SREG_##seg] = { \
660 .selector = GUEST_##seg##_SELECTOR, \
661 .base = GUEST_##seg##_BASE, \
662 .limit = GUEST_##seg##_LIMIT, \
663 .ar_bytes = GUEST_##seg##_AR_BYTES, \
664 }
665
666static struct kvm_vmx_segment_field {
667 unsigned selector;
668 unsigned base;
669 unsigned limit;
670 unsigned ar_bytes;
671} kvm_vmx_segment_fields[] = {
672 VMX_SEGMENT_FIELD(CS),
673 VMX_SEGMENT_FIELD(DS),
674 VMX_SEGMENT_FIELD(ES),
675 VMX_SEGMENT_FIELD(FS),
676 VMX_SEGMENT_FIELD(GS),
677 VMX_SEGMENT_FIELD(SS),
678 VMX_SEGMENT_FIELD(TR),
679 VMX_SEGMENT_FIELD(LDTR),
680};
681
26bb0981
AK		 682static u64 host_efer;
683
6de4f3ad
AK		 684static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
685
4d56c8a7 686/*
8c06585d 687 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 688 * away by decrementing the array size.
689 */
6aa8b732 690static const u32 vmx_msr_index[] = {
05b3e0c2 691#ifdef CONFIG_X86_64
44ea2b17 692 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 693#endif
8c06585d 694 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 695};
9d8f549d 696#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 697
31299944 698static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 699{
700 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
701 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 702 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 703}
704
31299944 705static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 706{
707 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
708 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 709 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 710}
711
31299944 712static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 713{
714 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 716 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 717}
718
31299944 719static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 720{
721 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
722 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
723}
724
31299944 725static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 726{
727 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
728 INTR_INFO_VALID_MASK)) ==
729 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
730}
731
31299944 732static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 733{
04547156 734 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 735}
736
31299944 737static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 738{
04547156 739 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 740}
741
31299944 742static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 743{
04547156 744 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 745}
746
31299944 747static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 748{
04547156
SY		 749 return vmcs_config.cpu_based_exec_ctrl &
750 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 751}
752
774ead3a 753static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 754{
04547156
SY		 755 return vmcs_config.cpu_based_2nd_exec_ctrl &
756 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
757}
758
759static inline bool cpu_has_vmx_flexpriority(void)
760{
761 return cpu_has_vmx_tpr_shadow() &&
762 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 763}
764
e799794e
MT		 765static inline bool cpu_has_vmx_ept_execute_only(void)
766{
31299944 767 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 768}
769
770static inline bool cpu_has_vmx_eptp_uncacheable(void)
771{
31299944 772 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 773}
774
775static inline bool cpu_has_vmx_eptp_writeback(void)
776{
31299944 777 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 778}
779
780static inline bool cpu_has_vmx_ept_2m_page(void)
781{
31299944 782 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 783}
784
878403b7
SY		 785static inline bool cpu_has_vmx_ept_1g_page(void)
786{
31299944 787 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 788}
789
4bc9b982
SY		 790static inline bool cpu_has_vmx_ept_4levels(void)
791{
792 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
793}
794
83c3a331
XH		 795static inline bool cpu_has_vmx_ept_ad_bits(void)
796{
797 return vmx_capability.ept & VMX_EPT_AD_BIT;
798}
799
31299944 800static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 801{
31299944 802 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 803}
804
31299944 805static inline bool cpu_has_vmx_invept_context(void)
d56f546d 806{
31299944 807 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 808}
809
31299944 810static inline bool cpu_has_vmx_invept_global(void)
d56f546d 811{
31299944 812 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 813}
814
518c8aee
GJ		 815static inline bool cpu_has_vmx_invvpid_single(void)
816{
817 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
818}
819
b9d762fa
GJ		 820static inline bool cpu_has_vmx_invvpid_global(void)
821{
822 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
823}
824
31299944 825static inline bool cpu_has_vmx_ept(void)
d56f546d 826{
04547156
SY		 827 return vmcs_config.cpu_based_2nd_exec_ctrl &
828 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 829}
830
31299944 831static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 832{
833 return vmcs_config.cpu_based_2nd_exec_ctrl &
834 SECONDARY_EXEC_UNRESTRICTED_GUEST;
835}
836
31299944 837static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 838{
839 return vmcs_config.cpu_based_2nd_exec_ctrl &
840 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
841}
842
31299944 843static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 844{
6d3e435e 845 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 846}
847
31299944 848static inline bool cpu_has_vmx_vpid(void)
2384d2b3 849{
04547156
SY		 850 return vmcs_config.cpu_based_2nd_exec_ctrl &
851 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 852}
853
31299944 854static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 855{
856 return vmcs_config.cpu_based_2nd_exec_ctrl &
857 SECONDARY_EXEC_RDTSCP;
858}
859
31299944 860static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 861{
862 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
863}
864
f5f48ee1
SY		 865static inline bool cpu_has_vmx_wbinvd_exit(void)
866{
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_WBINVD_EXITING;
869}
870
04547156
SY		 871static inline bool report_flexpriority(void)
872{
873 return flexpriority_enabled;
874}
875
fe3ef05c
NHE		 876static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
877{
878 return vmcs12->cpu_based_vm_exec_control & bit;
879}
880
881static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
882{
883 return (vmcs12->cpu_based_vm_exec_control &
884 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
885 (vmcs12->secondary_vm_exec_control & bit);
886}
887
644d711a
NHE		 888static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
889 struct kvm_vcpu *vcpu)
890{
891 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
892}
893
894static inline bool is_exception(u32 intr_info)
895{
896 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
897 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
898}
899
900static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 901static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
902 struct vmcs12 *vmcs12,
903 u32 reason, unsigned long qualification);
904
8b9cf98c 905static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 906{
907 int i;
908
a2fa3e9f 909 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 910 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 911 return i;
912 return -1;
913}
914
2384d2b3
SY		 915static inline void __invvpid(int ext, u16 vpid, gva_t gva)
916{
917 struct {
918 u64 vpid : 16;
919 u64 rsvd : 48;
920 u64 gva;
921 } operand = { vpid, 0, gva };
922
4ecac3fd 923 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 924 /* CF==1 or ZF==1 --> rc = -1 */
925 "; ja 1f ; ud2 ; 1:"
926 : : "a"(&operand), "c"(ext) : "cc", "memory");
927}
928
1439442c
SY		 929static inline void __invept(int ext, u64 eptp, gpa_t gpa)
930{
931 struct {
932 u64 eptp, gpa;
933 } operand = {eptp, gpa};
934
4ecac3fd 935 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 936 /* CF==1 or ZF==1 --> rc = -1 */
937 "; ja 1f ; ud2 ; 1:\n"
938 : : "a" (&operand), "c" (ext) : "cc", "memory");
939}
940
26bb0981 941static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 942{
943 int i;
944
8b9cf98c 945 i = __find_msr_index(vmx, msr);
a75beee6 946 if (i >= 0)
a2fa3e9f 947 return &vmx->guest_msrs[i];
8b6d44c7 948 return NULL;
7725f0ba
AK		 949}
950
6aa8b732
AK		 951static void vmcs_clear(struct vmcs *vmcs)
952{
953 u64 phys_addr = __pa(vmcs);
954 u8 error;
955
4ecac3fd 956 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 957 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 958 : "cc", "memory");
959 if (error)
960 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
961 vmcs, phys_addr);
962}
963
d462b819
NHE		 964static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
965{
966 vmcs_clear(loaded_vmcs->vmcs);
967 loaded_vmcs->cpu = -1;
968 loaded_vmcs->launched = 0;
969}
970
7725b894
DX		 971static void vmcs_load(struct vmcs *vmcs)
972{
973 u64 phys_addr = __pa(vmcs);
974 u8 error;
975
976 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 977 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 978 : "cc", "memory");
979 if (error)
2844d849 980 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 981 vmcs, phys_addr);
982}
983
d462b819 984static void __loaded_vmcs_clear(void *arg)
6aa8b732 985{
d462b819 986 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 987 int cpu = raw_smp_processor_id();
6aa8b732 988
d462b819
NHE		 989 if (loaded_vmcs->cpu != cpu)
990 return; /* vcpu migration can race with cpu offline */
991 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 992 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 993 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
994 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 995}
996
d462b819 997static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 998{
d462b819
NHE		 999 if (loaded_vmcs->cpu != -1)
1000 smp_call_function_single(
1001 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1002}
1003
1760dd49 1004static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1005{
1006 if (vmx->vpid == 0)
1007 return;
1008
518c8aee
GJ		 1009 if (cpu_has_vmx_invvpid_single())
1010 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1011}
1012
b9d762fa
GJ		 1013static inline void vpid_sync_vcpu_global(void)
1014{
1015 if (cpu_has_vmx_invvpid_global())
1016 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1017}
1018
1019static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1020{
1021 if (cpu_has_vmx_invvpid_single())
1760dd49 1022 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1023 else
1024 vpid_sync_vcpu_global();
1025}
1026
1439442c
SY		 1027static inline void ept_sync_global(void)
1028{
1029 if (cpu_has_vmx_invept_global())
1030 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1031}
1032
1033static inline void ept_sync_context(u64 eptp)
1034{
089d034e 1035 if (enable_ept) {
1439442c
SY		 1036 if (cpu_has_vmx_invept_context())
1037 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1038 else
1039 ept_sync_global();
1040 }
1041}
1042
1043static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1044{
089d034e 1045 if (enable_ept) {
1439442c
SY		 1046 if (cpu_has_vmx_invept_individual_addr())
1047 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1048 eptp, gpa);
1049 else
1050 ept_sync_context(eptp);
1051 }
1052}
1053
96304217 1054static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1055{
5e520e62 1056 unsigned long value;
6aa8b732 1057
5e520e62
AK		 1058 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1059 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1060 return value;
1061}
1062
96304217 1063static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1064{
1065 return vmcs_readl(field);
1066}
1067
96304217 1068static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1069{
1070 return vmcs_readl(field);
1071}
1072
96304217 1073static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1074{
05b3e0c2 1075#ifdef CONFIG_X86_64
6aa8b732
AK		 1076 return vmcs_readl(field);
1077#else
1078 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1079#endif
1080}
1081
e52de1b8
AK		 1082static noinline void vmwrite_error(unsigned long field, unsigned long value)
1083{
1084 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1085 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1086 dump_stack();
1087}
1088
6aa8b732
AK		 1089static void vmcs_writel(unsigned long field, unsigned long value)
1090{
1091 u8 error;
1092
4ecac3fd 1093 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1094 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1095 if (unlikely(error))
1096 vmwrite_error(field, value);
6aa8b732
AK		 1097}
1098
1099static void vmcs_write16(unsigned long field, u16 value)
1100{
1101 vmcs_writel(field, value);
1102}
1103
1104static void vmcs_write32(unsigned long field, u32 value)
1105{
1106 vmcs_writel(field, value);
1107}
1108
1109static void vmcs_write64(unsigned long field, u64 value)
1110{
6aa8b732 1111 vmcs_writel(field, value);
7682f2d0 1112#ifndef CONFIG_X86_64
6aa8b732
AK		 1113 asm volatile ("");
1114 vmcs_writel(field+1, value >> 32);
1115#endif
1116}
1117
2ab455cc
AL		 1118static void vmcs_clear_bits(unsigned long field, u32 mask)
1119{
1120 vmcs_writel(field, vmcs_readl(field) & ~mask);
1121}
1122
1123static void vmcs_set_bits(unsigned long field, u32 mask)
1124{
1125 vmcs_writel(field, vmcs_readl(field) | mask);
1126}
1127
2fb92db1
AK		 1128static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1129{
1130 vmx->segment_cache.bitmask = 0;
1131}
1132
1133static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1134 unsigned field)
1135{
1136 bool ret;
1137 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1138
1139 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1140 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1141 vmx->segment_cache.bitmask = 0;
1142 }
1143 ret = vmx->segment_cache.bitmask & mask;
1144 vmx->segment_cache.bitmask |= mask;
1145 return ret;
1146}
1147
1148static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1149{
1150 u16 *p = &vmx->segment_cache.seg[seg].selector;
1151
1152 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1153 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1154 return *p;
1155}
1156
1157static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1158{
1159 ulong *p = &vmx->segment_cache.seg[seg].base;
1160
1161 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1162 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1163 return *p;
1164}
1165
1166static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1167{
1168 u32 *p = &vmx->segment_cache.seg[seg].limit;
1169
1170 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1171 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1172 return *p;
1173}
1174
1175static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1176{
1177 u32 *p = &vmx->segment_cache.seg[seg].ar;
1178
1179 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1180 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1181 return *p;
1182}
1183
abd3f2d6
AK		 1184static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1185{
1186 u32 eb;
1187
fd7373cc
JK		 1188 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1189 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1190 if ((vcpu->guest_debug &
1191 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1192 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1193 eb |= 1u << BP_VECTOR;
7ffd92c5 1194 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1195 eb = ~0;
089d034e 1196 if (enable_ept)
1439442c 1197 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1198 if (vcpu->fpu_active)
1199 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1200
1201 /* When we are running a nested L2 guest and L1 specified for it a
1202 * certain exception bitmap, we must trap the same exceptions and pass
1203 * them to L1. When running L2, we will only handle the exceptions
1204 * specified above if L1 did not want them.
1205 */
1206 if (is_guest_mode(vcpu))
1207 eb |= get_vmcs12(vcpu)->exception_bitmap;
1208
abd3f2d6
AK		 1209 vmcs_write32(EXCEPTION_BITMAP, eb);
1210}
1211
8bf00a52
GN		 1212static void clear_atomic_switch_msr_special(unsigned long entry,
1213 unsigned long exit)
1214{
1215 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1216 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1217}
1218
61d2ef2c
AK		 1219static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1220{
1221 unsigned i;
1222 struct msr_autoload *m = &vmx->msr_autoload;
1223
8bf00a52
GN		 1224 switch (msr) {
1225 case MSR_EFER:
1226 if (cpu_has_load_ia32_efer) {
1227 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1228 VM_EXIT_LOAD_IA32_EFER);
1229 return;
1230 }
1231 break;
1232 case MSR_CORE_PERF_GLOBAL_CTRL:
1233 if (cpu_has_load_perf_global_ctrl) {
1234 clear_atomic_switch_msr_special(
1235 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1236 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1237 return;
1238 }
1239 break;
110312c8
AK		 1240 }
1241
61d2ef2c
AK		 1242 for (i = 0; i < m->nr; ++i)
1243 if (m->guest[i].index == msr)
1244 break;
1245
1246 if (i == m->nr)
1247 return;
1248 --m->nr;
1249 m->guest[i] = m->guest[m->nr];
1250 m->host[i] = m->host[m->nr];
1251 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1252 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1253}
1254
8bf00a52
GN		 1255static void add_atomic_switch_msr_special(unsigned long entry,
1256 unsigned long exit, unsigned long guest_val_vmcs,
1257 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1258{
1259 vmcs_write64(guest_val_vmcs, guest_val);
1260 vmcs_write64(host_val_vmcs, host_val);
1261 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1262 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1263}
1264
61d2ef2c
AK		 1265static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1266 u64 guest_val, u64 host_val)
1267{
1268 unsigned i;
1269 struct msr_autoload *m = &vmx->msr_autoload;
1270
8bf00a52
GN		 1271 switch (msr) {
1272 case MSR_EFER:
1273 if (cpu_has_load_ia32_efer) {
1274 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1275 VM_EXIT_LOAD_IA32_EFER,
1276 GUEST_IA32_EFER,
1277 HOST_IA32_EFER,
1278 guest_val, host_val);
1279 return;
1280 }
1281 break;
1282 case MSR_CORE_PERF_GLOBAL_CTRL:
1283 if (cpu_has_load_perf_global_ctrl) {
1284 add_atomic_switch_msr_special(
1285 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1286 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1287 GUEST_IA32_PERF_GLOBAL_CTRL,
1288 HOST_IA32_PERF_GLOBAL_CTRL,
1289 guest_val, host_val);
1290 return;
1291 }
1292 break;
110312c8
AK		 1293 }
1294
61d2ef2c
AK		 1295 for (i = 0; i < m->nr; ++i)
1296 if (m->guest[i].index == msr)
1297 break;
1298
e7fc6f93
GN		 1299 if (i == NR_AUTOLOAD_MSRS) {
1300 printk_once(KERN_WARNING"Not enough mst switch entries. "
1301 "Can't add msr %x\n", msr);
1302 return;
1303 } else if (i == m->nr) {
61d2ef2c
AK		 1304 ++m->nr;
1305 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1306 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1307 }
1308
1309 m->guest[i].index = msr;
1310 m->guest[i].value = guest_val;
1311 m->host[i].index = msr;
1312 m->host[i].value = host_val;
1313}
1314
33ed6329
AK		 1315static void reload_tss(void)
1316{
33ed6329
AK		 1317 /*
1318 * VT restores TR but not its size. Useless.
1319 */
d359192f 1320 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1321 struct desc_struct *descs;
33ed6329 1322
d359192f 1323 descs = (void *)gdt->address;
33ed6329
AK		 1324 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1325 load_TR_desc();
33ed6329
AK		 1326}
1327
92c0d900 1328static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1329{
3a34a881 1330 u64 guest_efer;
51c6cf66
AK		 1331 u64 ignore_bits;
1332
f6801dff 1333 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1334
51c6cf66
AK		 1335 /*
1336 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1337 * outside long mode
1338 */
1339 ignore_bits = EFER_NX | EFER_SCE;
1340#ifdef CONFIG_X86_64
1341 ignore_bits |= EFER_LMA | EFER_LME;
1342 /* SCE is meaningful only in long mode on Intel */
1343 if (guest_efer & EFER_LMA)
1344 ignore_bits &= ~(u64)EFER_SCE;
1345#endif
51c6cf66
AK		 1346 guest_efer &= ~ignore_bits;
1347 guest_efer |= host_efer & ignore_bits;
26bb0981 1348 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1349 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1350
1351 clear_atomic_switch_msr(vmx, MSR_EFER);
1352 /* On ept, can't emulate nx, and must switch nx atomically */
1353 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1354 guest_efer = vmx->vcpu.arch.efer;
1355 if (!(guest_efer & EFER_LMA))
1356 guest_efer &= ~EFER_LME;
1357 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1358 return false;
1359 }
1360
26bb0981 1361 return true;
51c6cf66
AK		 1362}
1363
2d49ec72
GN		 1364static unsigned long segment_base(u16 selector)
1365{
d359192f 1366 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1367 struct desc_struct *d;
1368 unsigned long table_base;
1369 unsigned long v;
1370
1371 if (!(selector & ~3))
1372 return 0;
1373
d359192f 1374 table_base = gdt->address;
2d49ec72
GN		 1375
1376 if (selector & 4) { /* from ldt */
1377 u16 ldt_selector = kvm_read_ldt();
1378
1379 if (!(ldt_selector & ~3))
1380 return 0;
1381
1382 table_base = segment_base(ldt_selector);
1383 }
1384 d = (struct desc_struct *)(table_base + (selector & ~7));
1385 v = get_desc_base(d);
1386#ifdef CONFIG_X86_64
1387 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1388 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1389#endif
1390 return v;
1391}
1392
1393static inline unsigned long kvm_read_tr_base(void)
1394{
1395 u16 tr;
1396 asm("str %0" : "=g"(tr));
1397 return segment_base(tr);
1398}
1399
04d2cc77 1400static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1401{
04d2cc77 1402 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1403 int i;
04d2cc77 1404
a2fa3e9f 1405 if (vmx->host_state.loaded)
33ed6329
AK		 1406 return;
1407
a2fa3e9f 1408 vmx->host_state.loaded = 1;
33ed6329
AK		 1409 /*
1410 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1411 * allow segment selectors with cpl > 0 or ti == 1.
1412 */
d6e88aec 1413 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1414 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1415 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1416 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1417 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1418 vmx->host_state.fs_reload_needed = 0;
1419 } else {
33ed6329 1420 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1421 vmx->host_state.fs_reload_needed = 1;
33ed6329 1422 }
9581d442 1423 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1424 if (!(vmx->host_state.gs_sel & 7))
1425 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1426 else {
1427 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1428 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1429 }
1430
b2da15ac
AK		 1431#ifdef CONFIG_X86_64
1432 savesegment(ds, vmx->host_state.ds_sel);
1433 savesegment(es, vmx->host_state.es_sel);
1434#endif
1435
33ed6329
AK		 1436#ifdef CONFIG_X86_64
1437 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1438 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1439#else
a2fa3e9f
GH		 1440 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1441 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1442#endif
707c0874
AK		 1443
1444#ifdef CONFIG_X86_64
c8770e7b
AK		 1445 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1446 if (is_long_mode(&vmx->vcpu))
44ea2b17 1447 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1448#endif
26bb0981
AK		 1449 for (i = 0; i < vmx->save_nmsrs; ++i)
1450 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1451 vmx->guest_msrs[i].data,
1452 vmx->guest_msrs[i].mask);
33ed6329
AK		 1453}
1454
a9b21b62 1455static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1456{
a2fa3e9f 1457 if (!vmx->host_state.loaded)
33ed6329
AK		 1458 return;
1459
e1beb1d3 1460 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1461 vmx->host_state.loaded = 0;
c8770e7b
AK		 1462#ifdef CONFIG_X86_64
1463 if (is_long_mode(&vmx->vcpu))
1464 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1465#endif
152d3f2f 1466 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1467 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1468#ifdef CONFIG_X86_64
9581d442 1469 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1470#else
1471 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1472#endif
33ed6329 1473 }
0a77fe4c
AK		 1474 if (vmx->host_state.fs_reload_needed)
1475 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1476#ifdef CONFIG_X86_64
1477 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1478 loadsegment(ds, vmx->host_state.ds_sel);
1479 loadsegment(es, vmx->host_state.es_sel);
1480 }
1481#else
1482 /*
1483 * The sysexit path does not restore ds/es, so we must set them to
1484 * a reasonable value ourselves.
1485 */
1486 loadsegment(ds, __USER_DS);
1487 loadsegment(es, __USER_DS);
1488#endif
152d3f2f 1489 reload_tss();
44ea2b17 1490#ifdef CONFIG_X86_64
c8770e7b 1491 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1492#endif
1361b83a 1493 if (user_has_fpu())
1c11e713 1494 clts();
3444d7da 1495 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1496}
1497
a9b21b62
AK		 1498static void vmx_load_host_state(struct vcpu_vmx *vmx)
1499{
1500 preempt_disable();
1501 __vmx_load_host_state(vmx);
1502 preempt_enable();
1503}
1504
6aa8b732
AK		 1505/*
1506 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1507 * vcpu mutex is already taken.
1508 */
15ad7146 1509static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1510{
a2fa3e9f 1511 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1512 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1513
4610c9cc
DX		 1514 if (!vmm_exclusive)
1515 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1516 else if (vmx->loaded_vmcs->cpu != cpu)
1517 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1518
d462b819
NHE		 1519 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1520 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1521 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1522 }
1523
d462b819 1524 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1525 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1526 unsigned long sysenter_esp;
1527
a8eeb04a 1528 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1529 local_irq_disable();
d462b819
NHE		 1530 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1531 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1532 local_irq_enable();
1533
6aa8b732
AK		 1534 /*
1535 * Linux uses per-cpu TSS and GDT, so set these when switching
1536 * processors.
1537 */
d6e88aec 1538 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1539 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1540
1541 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1542 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1543 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1544 }
6aa8b732
AK		 1545}
1546
1547static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1548{
a9b21b62 1549 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1550 if (!vmm_exclusive) {
d462b819
NHE		 1551 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1552 vcpu->cpu = -1;
4610c9cc
DX		 1553 kvm_cpu_vmxoff();
1554 }
6aa8b732
AK		 1555}
1556
5fd86fcf
AK		 1557static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1558{
81231c69
AK		 1559 ulong cr0;
1560
5fd86fcf
AK		 1561 if (vcpu->fpu_active)
1562 return;
1563 vcpu->fpu_active = 1;
81231c69
AK		 1564 cr0 = vmcs_readl(GUEST_CR0);
1565 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1566 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1567 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1568 update_exception_bitmap(vcpu);
edcafe3c 1569 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1570 if (is_guest_mode(vcpu))
1571 vcpu->arch.cr0_guest_owned_bits &=
1572 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1573 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1574}
1575
edcafe3c
AK		 1576static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1577
fe3ef05c
NHE		 1578/*
1579 * Return the cr0 value that a nested guest would read. This is a combination
1580 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1581 * its hypervisor (cr0_read_shadow).
1582 */
1583static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1584{
1585 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1586 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1587}
1588static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1589{
1590 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1591 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1592}
1593
5fd86fcf
AK		 1594static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1595{
36cf24e0
NHE		 1596 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1597 * set this *before* calling this function.
1598 */
edcafe3c 1599 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1600 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1601 update_exception_bitmap(vcpu);
edcafe3c
AK		 1602 vcpu->arch.cr0_guest_owned_bits = 0;
1603 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1604 if (is_guest_mode(vcpu)) {
1605 /*
1606 * L1's specified read shadow might not contain the TS bit,
1607 * so now that we turned on shadowing of this bit, we need to
1608 * set this bit of the shadow. Like in nested_vmx_run we need
1609 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1610 * up-to-date here because we just decached cr0.TS (and we'll
1611 * only update vmcs12->guest_cr0 on nested exit).
1612 */
1613 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1614 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1615 (vcpu->arch.cr0 & X86_CR0_TS);
1616 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1617 } else
1618 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1619}
1620
6aa8b732
AK		 1621static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1622{
78ac8b47 1623 unsigned long rflags, save_rflags;
345dcaa8 1624
6de12732
AK		 1625 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1626 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1627 rflags = vmcs_readl(GUEST_RFLAGS);
1628 if (to_vmx(vcpu)->rmode.vm86_active) {
1629 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1630 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1631 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1632 }
1633 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1634 }
6de12732 1635 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1636}
1637
1638static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1639{
6de12732 1640 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1641 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1642 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1643 if (to_vmx(vcpu)->rmode.vm86_active) {
1644 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1645 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1646 }
6aa8b732
AK		 1647 vmcs_writel(GUEST_RFLAGS, rflags);
1648}
1649
2809f5d2
GC		 1650static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1651{
1652 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1653 int ret = 0;
1654
1655 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1656 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1657 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1658 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1659
1660 return ret & mask;
1661}
1662
1663static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1664{
1665 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1666 u32 interruptibility = interruptibility_old;
1667
1668 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1669
48005f64 1670 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1671 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1672 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1673 interruptibility |= GUEST_INTR_STATE_STI;
1674
1675 if ((interruptibility != interruptibility_old))
1676 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1677}
1678
6aa8b732
AK		 1679static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1680{
1681 unsigned long rip;
6aa8b732 1682
5fdbf976 1683 rip = kvm_rip_read(vcpu);
6aa8b732 1684 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1685 kvm_rip_write(vcpu, rip);
6aa8b732 1686
2809f5d2
GC		 1687 /* skipping an emulated instruction also counts */
1688 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1689}
1690
0b6ac343
NHE		 1691/*
1692 * KVM wants to inject page-faults which it got to the guest. This function
1693 * checks whether in a nested guest, we need to inject them to L1 or L2.
1694 * This function assumes it is called with the exit reason in vmcs02 being
1695 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1696 * is running).
1697 */
1698static int nested_pf_handled(struct kvm_vcpu *vcpu)
1699{
1700 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1701
1702 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1703 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1704 return 0;
1705
1706 nested_vmx_vmexit(vcpu);
1707 return 1;
1708}
1709
298101da 1710static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1711 bool has_error_code, u32 error_code,
1712 bool reinject)
298101da 1713{
77ab6db0 1714 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1715 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1716
0b6ac343
NHE		 1717 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1718 nested_pf_handled(vcpu))
1719 return;
1720
8ab2d2e2 1721 if (has_error_code) {
77ab6db0 1722 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1723 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1724 }
77ab6db0 1725
7ffd92c5 1726 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1727 int inc_eip = 0;
1728 if (kvm_exception_is_soft(nr))
1729 inc_eip = vcpu->arch.event_exit_inst_len;
1730 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1731 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1732 return;
1733 }
1734
66fd3f7f
GN		 1735 if (kvm_exception_is_soft(nr)) {
1736 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1737 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1738 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1739 } else
1740 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1741
1742 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1743}
1744
4e47c7a6
SY		 1745static bool vmx_rdtscp_supported(void)
1746{
1747 return cpu_has_vmx_rdtscp();
1748}
1749
a75beee6
ED		 1750/*
1751 * Swap MSR entry in host/guest MSR entry array.
1752 */
8b9cf98c 1753static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1754{
26bb0981 1755 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1756
1757 tmp = vmx->guest_msrs[to];
1758 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1759 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1760}
1761
e38aea3e
AK		 1762/*
1763 * Set up the vmcs to automatically save and restore system
1764 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1765 * mode, as fiddling with msrs is very expensive.
1766 */
8b9cf98c 1767static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1768{
26bb0981 1769 int save_nmsrs, index;
5897297b 1770 unsigned long *msr_bitmap;
e38aea3e 1771
a75beee6
ED		 1772 save_nmsrs = 0;
1773#ifdef CONFIG_X86_64
8b9cf98c 1774 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1775 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1776 if (index >= 0)
8b9cf98c
RR		 1777 move_msr_up(vmx, index, save_nmsrs++);
1778 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1779 if (index >= 0)
8b9cf98c
RR		 1780 move_msr_up(vmx, index, save_nmsrs++);
1781 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1782 if (index >= 0)
8b9cf98c 1783 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1784 index = __find_msr_index(vmx, MSR_TSC_AUX);
1785 if (index >= 0 && vmx->rdtscp_enabled)
1786 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1787 /*
8c06585d 1788 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1789 * if efer.sce is enabled.
1790 */
8c06585d 1791 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1792 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1793 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1794 }
1795#endif
92c0d900
AK		 1796 index = __find_msr_index(vmx, MSR_EFER);
1797 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1798 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1799
26bb0981 1800 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1801
1802 if (cpu_has_vmx_msr_bitmap()) {
1803 if (is_long_mode(&vmx->vcpu))
1804 msr_bitmap = vmx_msr_bitmap_longmode;
1805 else
1806 msr_bitmap = vmx_msr_bitmap_legacy;
1807
1808 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1809 }
e38aea3e
AK		 1810}
1811
6aa8b732
AK		 1812/*
1813 * reads and returns guest's timestamp counter "register"
1814 * guest_tsc = host_tsc + tsc_offset -- 21.3
1815 */
1816static u64 guest_read_tsc(void)
1817{
1818 u64 host_tsc, tsc_offset;
1819
1820 rdtscll(host_tsc);
1821 tsc_offset = vmcs_read64(TSC_OFFSET);
1822 return host_tsc + tsc_offset;
1823}
1824
d5c1785d
NHE		 1825/*
1826 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1827 * counter, even if a nested guest (L2) is currently running.
1828 */
1829u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1830{
1831 u64 host_tsc, tsc_offset;
1832
1833 rdtscll(host_tsc);
1834 tsc_offset = is_guest_mode(vcpu) ?
1835 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1836 vmcs_read64(TSC_OFFSET);
1837 return host_tsc + tsc_offset;
1838}
1839
4051b188 1840/*
cc578287
ZA		 1841 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1842 * software catchup for faster rates on slower CPUs.
4051b188 1843 */
cc578287 1844static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1845{
cc578287
ZA		 1846 if (!scale)
1847 return;
1848
1849 if (user_tsc_khz > tsc_khz) {
1850 vcpu->arch.tsc_catchup = 1;
1851 vcpu->arch.tsc_always_catchup = 1;
1852 } else
1853 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1854}
1855
6aa8b732 1856/*
99e3e30a 1857 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1858 */
99e3e30a 1859static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1860{
27fc51b2 1861 if (is_guest_mode(vcpu)) {
7991825b 1862 /*
27fc51b2
NHE		 1863 * We're here if L1 chose not to trap WRMSR to TSC. According
1864 * to the spec, this should set L1's TSC; The offset that L1
1865 * set for L2 remains unchanged, and still needs to be added
1866 * to the newly set TSC to get L2's TSC.
7991825b 1867 */
27fc51b2
NHE		 1868 struct vmcs12 *vmcs12;
1869 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1870 /* recalculate vmcs02.TSC_OFFSET: */
1871 vmcs12 = get_vmcs12(vcpu);
1872 vmcs_write64(TSC_OFFSET, offset +
1873 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1874 vmcs12->tsc_offset : 0));
1875 } else {
1876 vmcs_write64(TSC_OFFSET, offset);
1877 }
6aa8b732
AK		 1878}
1879
f1e2b260 1880static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1881{
1882 u64 offset = vmcs_read64(TSC_OFFSET);
1883 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1884 if (is_guest_mode(vcpu)) {
1885 /* Even when running L2, the adjustment needs to apply to L1 */
1886 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1887 }
e48672fa
ZA		 1888}
1889
857e4099
JR		 1890static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1891{
1892 return target_tsc - native_read_tsc();
1893}
1894
801d3424
NHE		 1895static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1896{
1897 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1898 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1899}
1900
1901/*
1902 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1903 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1904 * all guests if the "nested" module option is off, and can also be disabled
1905 * for a single guest by disabling its VMX cpuid bit.
1906 */
1907static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1908{
1909 return nested && guest_cpuid_has_vmx(vcpu);
1910}
1911
b87a51ae
NHE		 1912/*
1913 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1914 * returned for the various VMX controls MSRs when nested VMX is enabled.
1915 * The same values should also be used to verify that vmcs12 control fields are
1916 * valid during nested entry from L1 to L2.
1917 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1918 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1919 * bit in the high half is on if the corresponding bit in the control field
1920 * may be on. See also vmx_control_verify().
1921 * TODO: allow these variables to be modified (downgraded) by module options
1922 * or other means.
1923 */
1924static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1925static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1926static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1927static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1928static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1929static __init void nested_vmx_setup_ctls_msrs(void)
1930{
1931 /*
1932 * Note that as a general rule, the high half of the MSRs (bits in
1933 * the control fields which may be 1) should be initialized by the
1934 * intersection of the underlying hardware's MSR (i.e., features which
1935 * can be supported) and the list of features we want to expose -
1936 * because they are known to be properly supported in our code.
1937 * Also, usually, the low half of the MSRs (bits which must be 1) can
1938 * be set to 0, meaning that L1 may turn off any of these bits. The
1939 * reason is that if one of these bits is necessary, it will appear
1940 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1941 * fields of vmcs01 and vmcs02, will turn these bits off - and
1942 * nested_vmx_exit_handled() will not pass related exits to L1.
1943 * These rules have exceptions below.
1944 */
1945
1946 /* pin-based controls */
1947 /*
1948 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1949 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1950 */
1951 nested_vmx_pinbased_ctls_low = 0x16 ;
1952 nested_vmx_pinbased_ctls_high = 0x16 |
1953 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1954 PIN_BASED_VIRTUAL_NMIS;
1955
1956 /* exit controls */
1957 nested_vmx_exit_ctls_low = 0;
b6f1250e 1958 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1959#ifdef CONFIG_X86_64
1960 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1961#else
1962 nested_vmx_exit_ctls_high = 0;
1963#endif
1964
1965 /* entry controls */
1966 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1967 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1968 nested_vmx_entry_ctls_low = 0;
1969 nested_vmx_entry_ctls_high &=
1970 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1971
1972 /* cpu-based controls */
1973 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1974 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1975 nested_vmx_procbased_ctls_low = 0;
1976 nested_vmx_procbased_ctls_high &=
1977 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1978 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1979 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1980 CPU_BASED_CR3_STORE_EXITING |
1981#ifdef CONFIG_X86_64
1982 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1983#endif
1984 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1985 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
fee84b07 1986 CPU_BASED_RDPMC_EXITING |
b87a51ae
NHE		 1987 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1988 /*
1989 * We can allow some features even when not supported by the
1990 * hardware. For example, L1 can specify an MSR bitmap - and we
1991 * can use it to avoid exits to L1 - even when L0 runs L2
1992 * without MSR bitmaps.
1993 */
1994 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1995
1996 /* secondary cpu-based controls */
1997 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1998 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1999 nested_vmx_secondary_ctls_low = 0;
2000 nested_vmx_secondary_ctls_high &=
2001 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2002}
2003
2004static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2005{
2006 /*
2007 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2008 */
2009 return ((control & high) | low) == control;
2010}
2011
2012static inline u64 vmx_control_msr(u32 low, u32 high)
2013{
2014 return low | ((u64)high << 32);
2015}
2016
2017/*
2018 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2019 * also let it use VMX-specific MSRs.
2020 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2021 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2022 * like all other MSRs).
2023 */
2024static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2025{
2026 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2027 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2028 /*
2029 * According to the spec, processors which do not support VMX
2030 * should throw a #GP(0) when VMX capability MSRs are read.
2031 */
2032 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2033 return 1;
2034 }
2035
2036 switch (msr_index) {
2037 case MSR_IA32_FEATURE_CONTROL:
2038 *pdata = 0;
2039 break;
2040 case MSR_IA32_VMX_BASIC:
2041 /*
2042 * This MSR reports some information about VMX support. We
2043 * should return information about the VMX we emulate for the
2044 * guest, and the VMCS structure we give it - not about the
2045 * VMX support of the underlying hardware.
2046 */
2047 *pdata = VMCS12_REVISION |
2048 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2049 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2050 break;
2051 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2052 case MSR_IA32_VMX_PINBASED_CTLS:
2053 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2054 nested_vmx_pinbased_ctls_high);
2055 break;
2056 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2057 case MSR_IA32_VMX_PROCBASED_CTLS:
2058 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2059 nested_vmx_procbased_ctls_high);
2060 break;
2061 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2062 case MSR_IA32_VMX_EXIT_CTLS:
2063 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2064 nested_vmx_exit_ctls_high);
2065 break;
2066 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2067 case MSR_IA32_VMX_ENTRY_CTLS:
2068 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2069 nested_vmx_entry_ctls_high);
2070 break;
2071 case MSR_IA32_VMX_MISC:
2072 *pdata = 0;
2073 break;
2074 /*
2075 * These MSRs specify bits which the guest must keep fixed (on or off)
2076 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2077 * We picked the standard core2 setting.
2078 */
2079#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2080#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2081 case MSR_IA32_VMX_CR0_FIXED0:
2082 *pdata = VMXON_CR0_ALWAYSON;
2083 break;
2084 case MSR_IA32_VMX_CR0_FIXED1:
2085 *pdata = -1ULL;
2086 break;
2087 case MSR_IA32_VMX_CR4_FIXED0:
2088 *pdata = VMXON_CR4_ALWAYSON;
2089 break;
2090 case MSR_IA32_VMX_CR4_FIXED1:
2091 *pdata = -1ULL;
2092 break;
2093 case MSR_IA32_VMX_VMCS_ENUM:
2094 *pdata = 0x1f;
2095 break;
2096 case MSR_IA32_VMX_PROCBASED_CTLS2:
2097 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2098 nested_vmx_secondary_ctls_high);
2099 break;
2100 case MSR_IA32_VMX_EPT_VPID_CAP:
2101 /* Currently, no nested ept or nested vpid */
2102 *pdata = 0;
2103 break;
2104 default:
2105 return 0;
2106 }
2107
2108 return 1;
2109}
2110
2111static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2112{
2113 if (!nested_vmx_allowed(vcpu))
2114 return 0;
2115
2116 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2117 /* TODO: the right thing. */
2118 return 1;
2119 /*
2120 * No need to treat VMX capability MSRs specially: If we don't handle
2121 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2122 */
2123 return 0;
2124}
2125
6aa8b732
AK		 2126/*
2127 * Reads an msr value (of 'msr_index') into 'pdata'.
2128 * Returns 0 on success, non-0 otherwise.
2129 * Assumes vcpu_load() was already called.
2130 */
2131static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2132{
2133 u64 data;
26bb0981 2134 struct shared_msr_entry *msr;
6aa8b732
AK		 2135
2136 if (!pdata) {
2137 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2138 return -EINVAL;
2139 }
2140
2141 switch (msr_index) {
05b3e0c2 2142#ifdef CONFIG_X86_64
6aa8b732
AK		 2143 case MSR_FS_BASE:
2144 data = vmcs_readl(GUEST_FS_BASE);
2145 break;
2146 case MSR_GS_BASE:
2147 data = vmcs_readl(GUEST_GS_BASE);
2148 break;
44ea2b17
AK		 2149 case MSR_KERNEL_GS_BASE:
2150 vmx_load_host_state(to_vmx(vcpu));
2151 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2152 break;
26bb0981 2153#endif
6aa8b732 2154 case MSR_EFER:
3bab1f5d 2155 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2156 case MSR_IA32_TSC:
6aa8b732
AK		 2157 data = guest_read_tsc();
2158 break;
2159 case MSR_IA32_SYSENTER_CS:
2160 data = vmcs_read32(GUEST_SYSENTER_CS);
2161 break;
2162 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2163 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2164 break;
2165 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2166 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2167 break;
4e47c7a6
SY		 2168 case MSR_TSC_AUX:
2169 if (!to_vmx(vcpu)->rdtscp_enabled)
2170 return 1;
2171 /* Otherwise falls through */
6aa8b732 2172 default:
b87a51ae
NHE		 2173 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2174 return 0;
8b9cf98c 2175 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2176 if (msr) {
2177 data = msr->data;
2178 break;
6aa8b732 2179 }
3bab1f5d 2180 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2181 }
2182
2183 *pdata = data;
2184 return 0;
2185}
2186
2187/*
2188 * Writes msr value into into the appropriate "register".
2189 * Returns 0 on success, non-0 otherwise.
2190 * Assumes vcpu_load() was already called.
2191 */
2192static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2193{
a2fa3e9f 2194 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2195 struct shared_msr_entry *msr;
2cc51560
ED		 2196 int ret = 0;
2197
6aa8b732 2198 switch (msr_index) {
3bab1f5d 2199 case MSR_EFER:
2cc51560 2200 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2201 break;
16175a79 2202#ifdef CONFIG_X86_64
6aa8b732 2203 case MSR_FS_BASE:
2fb92db1 2204 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2205 vmcs_writel(GUEST_FS_BASE, data);
2206 break;
2207 case MSR_GS_BASE:
2fb92db1 2208 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2209 vmcs_writel(GUEST_GS_BASE, data);
2210 break;
44ea2b17
AK		 2211 case MSR_KERNEL_GS_BASE:
2212 vmx_load_host_state(vmx);
2213 vmx->msr_guest_kernel_gs_base = data;
2214 break;
6aa8b732
AK		 2215#endif
2216 case MSR_IA32_SYSENTER_CS:
2217 vmcs_write32(GUEST_SYSENTER_CS, data);
2218 break;
2219 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2220 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2221 break;
2222 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2223 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2224 break;
af24a4e4 2225 case MSR_IA32_TSC:
99e3e30a 2226 kvm_write_tsc(vcpu, data);
6aa8b732 2227 break;
468d472f
SY		 2228 case MSR_IA32_CR_PAT:
2229 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2230 vmcs_write64(GUEST_IA32_PAT, data);
2231 vcpu->arch.pat = data;
2232 break;
2233 }
4e47c7a6
SY		 2234 ret = kvm_set_msr_common(vcpu, msr_index, data);
2235 break;
2236 case MSR_TSC_AUX:
2237 if (!vmx->rdtscp_enabled)
2238 return 1;
2239 /* Check reserved bit, higher 32 bits should be zero */
2240 if ((data >> 32) != 0)
2241 return 1;
2242 /* Otherwise falls through */
6aa8b732 2243 default:
b87a51ae
NHE		 2244 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2245 break;
8b9cf98c 2246 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2247 if (msr) {
2248 msr->data = data;
2225fd56
AK		 2249 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2250 preempt_disable();
9ee73970
AK		 2251 kvm_set_shared_msr(msr->index, msr->data,
2252 msr->mask);
2225fd56
AK		 2253 preempt_enable();
2254 }
3bab1f5d 2255 break;
6aa8b732 2256 }
2cc51560 2257 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2258 }
2259
2cc51560 2260 return ret;
6aa8b732
AK		 2261}
2262
5fdbf976 2263static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2264{
5fdbf976
MT		 2265 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2266 switch (reg) {
2267 case VCPU_REGS_RSP:
2268 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2269 break;
2270 case VCPU_REGS_RIP:
2271 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2272 break;
6de4f3ad
AK		 2273 case VCPU_EXREG_PDPTR:
2274 if (enable_ept)
2275 ept_save_pdptrs(vcpu);
2276 break;
5fdbf976
MT		 2277 default:
2278 break;
2279 }
6aa8b732
AK		 2280}
2281
355be0b9 2282static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2283{
ae675ef0
JK		 2284 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2285 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2286 else
2287 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2288
abd3f2d6 2289 update_exception_bitmap(vcpu);
6aa8b732
AK		 2290}
2291
2292static __init int cpu_has_kvm_support(void)
2293{
6210e37b 2294 return cpu_has_vmx();
6aa8b732
AK		 2295}
2296
2297static __init int vmx_disabled_by_bios(void)
2298{
2299 u64 msr;
2300
2301 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2302 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2303 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2304 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2305 && tboot_enabled())
2306 return 1;
23f3e991 2307 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2308 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2309 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2310 && !tboot_enabled()) {
2311 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2312 "activate TXT before enabling KVM\n");
cafd6659 2313 return 1;
f9335afe 2314 }
23f3e991
JC		 2315 /* launched w/o TXT and VMX disabled */
2316 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2317 && !tboot_enabled())
2318 return 1;
cafd6659
SW		 2319 }
2320
2321 return 0;
6aa8b732
AK		 2322}
2323
7725b894
DX		 2324static void kvm_cpu_vmxon(u64 addr)
2325{
2326 asm volatile (ASM_VMX_VMXON_RAX
2327 : : "a"(&addr), "m"(addr)
2328 : "memory", "cc");
2329}
2330
10474ae8 2331static int hardware_enable(void *garbage)
6aa8b732
AK		 2332{
2333 int cpu = raw_smp_processor_id();
2334 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2335 u64 old, test_bits;
6aa8b732 2336
10474ae8
AG		 2337 if (read_cr4() & X86_CR4_VMXE)
2338 return -EBUSY;
2339
d462b819 2340 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2341 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2342
2343 test_bits = FEATURE_CONTROL_LOCKED;
2344 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2345 if (tboot_enabled())
2346 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2347
2348 if ((old & test_bits) != test_bits) {
6aa8b732 2349 /* enable and lock */
cafd6659
SW		 2350 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2351 }
66aee91a 2352 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2353
4610c9cc
DX		 2354 if (vmm_exclusive) {
2355 kvm_cpu_vmxon(phys_addr);
2356 ept_sync_global();
2357 }
10474ae8 2358
3444d7da
AK		 2359 store_gdt(&__get_cpu_var(host_gdt));
2360
10474ae8 2361 return 0;
6aa8b732
AK		 2362}
2363
d462b819 2364static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2365{
2366 int cpu = raw_smp_processor_id();
d462b819 2367 struct loaded_vmcs *v, *n;
543e4243 2368
d462b819
NHE		 2369 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2370 loaded_vmcss_on_cpu_link)
2371 __loaded_vmcs_clear(v);
543e4243
AK		 2372}
2373
710ff4a8
EH		 2374
2375/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2376 * tricks.
2377 */
2378static void kvm_cpu_vmxoff(void)
6aa8b732 2379{
4ecac3fd 2380 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2381}
2382
710ff4a8
EH		 2383static void hardware_disable(void *garbage)
2384{
4610c9cc 2385 if (vmm_exclusive) {
d462b819 2386 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2387 kvm_cpu_vmxoff();
2388 }
7725b894 2389 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2390}
2391
1c3d14fe 2392static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2393 u32 msr, u32 *result)
1c3d14fe
YS		 2394{
2395 u32 vmx_msr_low, vmx_msr_high;
2396 u32 ctl = ctl_min | ctl_opt;
2397
2398 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2399
2400 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2401 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2402
2403 /* Ensure minimum (required) set of control bits are supported. */
2404 if (ctl_min & ~ctl)
002c7f7c 2405 return -EIO;
1c3d14fe
YS		 2406
2407 *result = ctl;
2408 return 0;
2409}
2410
110312c8
AK		 2411static __init bool allow_1_setting(u32 msr, u32 ctl)
2412{
2413 u32 vmx_msr_low, vmx_msr_high;
2414
2415 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2416 return vmx_msr_high & ctl;
2417}
2418
002c7f7c 2419static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2420{
2421 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2422 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2423 u32 _pin_based_exec_control = 0;
2424 u32 _cpu_based_exec_control = 0;
f78e0e2e 2425 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2426 u32 _vmexit_control = 0;
2427 u32 _vmentry_control = 0;
2428
2429 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2430 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2431 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2432 &_pin_based_exec_control) < 0)
002c7f7c 2433 return -EIO;
1c3d14fe 2434
10166744 2435 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2436#ifdef CONFIG_X86_64
2437 CPU_BASED_CR8_LOAD_EXITING |
2438 CPU_BASED_CR8_STORE_EXITING |
2439#endif
d56f546d
SY		 2440 CPU_BASED_CR3_LOAD_EXITING |
2441 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2442 CPU_BASED_USE_IO_BITMAPS |
2443 CPU_BASED_MOV_DR_EXITING |
a7052897 2444 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2445 CPU_BASED_MWAIT_EXITING |
2446 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2447 CPU_BASED_INVLPG_EXITING |
2448 CPU_BASED_RDPMC_EXITING;
443381a8 2449
f78e0e2e 2450 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2451 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2452 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2453 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2454 &_cpu_based_exec_control) < 0)
002c7f7c 2455 return -EIO;
6e5d865c
YS		 2456#ifdef CONFIG_X86_64
2457 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2458 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2459 ~CPU_BASED_CR8_STORE_EXITING;
2460#endif
f78e0e2e 2461 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2462 min2 = 0;
2463 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2464 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2465 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2466 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2467 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2468 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2469 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2470 if (adjust_vmx_controls(min2, opt2,
2471 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2472 &_cpu_based_2nd_exec_control) < 0)
2473 return -EIO;
2474 }
2475#ifndef CONFIG_X86_64
2476 if (!(_cpu_based_2nd_exec_control &
2477 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2478 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2479#endif
d56f546d 2480 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2481 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2482 enabled */
5fff7d27
GN		 2483 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2484 CPU_BASED_CR3_STORE_EXITING |
2485 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2486 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2487 vmx_capability.ept, vmx_capability.vpid);
2488 }
1c3d14fe
YS		 2489
2490 min = 0;
2491#ifdef CONFIG_X86_64
2492 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2493#endif
468d472f 2494 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2495 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2496 &_vmexit_control) < 0)
002c7f7c 2497 return -EIO;
1c3d14fe 2498
468d472f
SY		 2499 min = 0;
2500 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2501 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2502 &_vmentry_control) < 0)
002c7f7c 2503 return -EIO;
6aa8b732 2504
c68876fd 2505 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2506
2507 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2508 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2509 return -EIO;
1c3d14fe
YS		 2510
2511#ifdef CONFIG_X86_64
2512 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2513 if (vmx_msr_high & (1u<<16))
002c7f7c 2514 return -EIO;
1c3d14fe
YS		 2515#endif
2516
2517 /* Require Write-Back (WB) memory type for VMCS accesses. */
2518 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2519 return -EIO;
1c3d14fe 2520
002c7f7c
YS		 2521 vmcs_conf->size = vmx_msr_high & 0x1fff;
2522 vmcs_conf->order = get_order(vmcs_config.size);
2523 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2524
002c7f7c
YS		 2525 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2526 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2527 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2528 vmcs_conf->vmexit_ctrl = _vmexit_control;
2529 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2530
110312c8
AK		 2531 cpu_has_load_ia32_efer =
2532 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2533 VM_ENTRY_LOAD_IA32_EFER)
2534 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2535 VM_EXIT_LOAD_IA32_EFER);
2536
8bf00a52
GN		 2537 cpu_has_load_perf_global_ctrl =
2538 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2539 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2540 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2541 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2542
2543 /*
2544 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2545 * but due to arrata below it can't be used. Workaround is to use
2546 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2547 *
2548 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2549 *
2550 * AAK155 (model 26)
2551 * AAP115 (model 30)
2552 * AAT100 (model 37)
2553 * BC86,AAY89,BD102 (model 44)
2554 * BA97 (model 46)
2555 *
2556 */
2557 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2558 switch (boot_cpu_data.x86_model) {
2559 case 26:
2560 case 30:
2561 case 37:
2562 case 44:
2563 case 46:
2564 cpu_has_load_perf_global_ctrl = false;
2565 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2566 "does not work properly. Using workaround\n");
2567 break;
2568 default:
2569 break;
2570 }
2571 }
2572
1c3d14fe 2573 return 0;
c68876fd 2574}
6aa8b732
AK		 2575
2576static struct vmcs *alloc_vmcs_cpu(int cpu)
2577{
2578 int node = cpu_to_node(cpu);
2579 struct page *pages;
2580 struct vmcs *vmcs;
2581
6484eb3e 2582 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2583 if (!pages)
2584 return NULL;
2585 vmcs = page_address(pages);
1c3d14fe
YS		 2586 memset(vmcs, 0, vmcs_config.size);
2587 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2588 return vmcs;
2589}
2590
2591static struct vmcs *alloc_vmcs(void)
2592{
d3b2c338 2593 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2594}
2595
2596static void free_vmcs(struct vmcs *vmcs)
2597{
1c3d14fe 2598 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2599}
2600
d462b819
NHE		 2601/*
2602 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2603 */
2604static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2605{
2606 if (!loaded_vmcs->vmcs)
2607 return;
2608 loaded_vmcs_clear(loaded_vmcs);
2609 free_vmcs(loaded_vmcs->vmcs);
2610 loaded_vmcs->vmcs = NULL;
2611}
2612
39959588 2613static void free_kvm_area(void)
6aa8b732
AK		 2614{
2615 int cpu;
2616
3230bb47 2617 for_each_possible_cpu(cpu) {
6aa8b732 2618 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2619 per_cpu(vmxarea, cpu) = NULL;
2620 }
6aa8b732
AK		 2621}
2622
6aa8b732
AK		 2623static __init int alloc_kvm_area(void)
2624{
2625 int cpu;
2626
3230bb47 2627 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2628 struct vmcs *vmcs;
2629
2630 vmcs = alloc_vmcs_cpu(cpu);
2631 if (!vmcs) {
2632 free_kvm_area();
2633 return -ENOMEM;
2634 }
2635
2636 per_cpu(vmxarea, cpu) = vmcs;
2637 }
2638 return 0;
2639}
2640
2641static __init int hardware_setup(void)
2642{
002c7f7c
YS		 2643 if (setup_vmcs_config(&vmcs_config) < 0)
2644 return -EIO;
50a37eb4
JR		 2645
2646 if (boot_cpu_has(X86_FEATURE_NX))
2647 kvm_enable_efer_bits(EFER_NX);
2648
93ba03c2
SY		 2649 if (!cpu_has_vmx_vpid())
2650 enable_vpid = 0;
2651
4bc9b982
SY		 2652 if (!cpu_has_vmx_ept() ||
2653 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2654 enable_ept = 0;
3a624e29 2655 enable_unrestricted_guest = 0;
83c3a331 2656 enable_ept_ad_bits = 0;
3a624e29
NK		 2657 }
2658
83c3a331
XH		 2659 if (!cpu_has_vmx_ept_ad_bits())
2660 enable_ept_ad_bits = 0;
2661
3a624e29
NK		 2662 if (!cpu_has_vmx_unrestricted_guest())
2663 enable_unrestricted_guest = 0;
93ba03c2
SY		 2664
2665 if (!cpu_has_vmx_flexpriority())
2666 flexpriority_enabled = 0;
2667
95ba8273
GN		 2668 if (!cpu_has_vmx_tpr_shadow())
2669 kvm_x86_ops->update_cr8_intercept = NULL;
2670
54dee993
MT		 2671 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2672 kvm_disable_largepages();
2673
4b8d54f9
ZE		 2674 if (!cpu_has_vmx_ple())
2675 ple_gap = 0;
2676
b87a51ae
NHE		 2677 if (nested)
2678 nested_vmx_setup_ctls_msrs();
2679
6aa8b732
AK		 2680 return alloc_kvm_area();
2681}
2682
2683static __exit void hardware_unsetup(void)
2684{
2685 free_kvm_area();
2686}
2687
6aa8b732
AK		 2688static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2689{
2690 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2691
6af11b9e 2692 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2693 vmcs_write16(sf->selector, save->selector);
2694 vmcs_writel(sf->base, save->base);
2695 vmcs_write32(sf->limit, save->limit);
2696 vmcs_write32(sf->ar_bytes, save->ar);
2697 } else {
2698 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2699 << AR_DPL_SHIFT;
2700 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2701 }
2702}
2703
2704static void enter_pmode(struct kvm_vcpu *vcpu)
2705{
2706 unsigned long flags;
a89a8fb9 2707 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2708
a89a8fb9 2709 vmx->emulation_required = 1;
7ffd92c5 2710 vmx->rmode.vm86_active = 0;
6aa8b732 2711
2fb92db1
AK		 2712 vmx_segment_cache_clear(vmx);
2713
d0ba64f9 2714 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2715 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2716 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2717 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2718
2719 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2720 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2721 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2722 vmcs_writel(GUEST_RFLAGS, flags);
2723
66aee91a
RR		 2724 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2725 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2726
2727 update_exception_bitmap(vcpu);
2728
a89a8fb9
MG		 2729 if (emulate_invalid_guest_state)
2730 return;
2731
7ffd92c5
AK		 2732 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2733 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2734 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2735 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2736
2fb92db1
AK		 2737 vmx_segment_cache_clear(vmx);
2738
6aa8b732
AK		 2739 vmcs_write16(GUEST_SS_SELECTOR, 0);
2740 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2741
2742 vmcs_write16(GUEST_CS_SELECTOR,
2743 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2744 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2745}
2746
d77c26fc 2747static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2748{
bfc6d222 2749 if (!kvm->arch.tss_addr) {
bc6678a3 2750 struct kvm_memslots *slots;
28a37544 2751 struct kvm_memory_slot *slot;
bc6678a3
MT		 2752 gfn_t base_gfn;
2753
90d83dc3 2754 slots = kvm_memslots(kvm);
28a37544
XG		 2755 slot = id_to_memslot(slots, 0);
2756 base_gfn = slot->base_gfn + slot->npages - 3;
2757
cbc94022
IE		 2758 return base_gfn << PAGE_SHIFT;
2759 }
bfc6d222 2760 return kvm->arch.tss_addr;
6aa8b732
AK		 2761}
2762
2763static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2764{
2765 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2766
2767 save->selector = vmcs_read16(sf->selector);
2768 save->base = vmcs_readl(sf->base);
2769 save->limit = vmcs_read32(sf->limit);
2770 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2771 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2772 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2773 vmcs_write32(sf->limit, 0xffff);
2774 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2775 if (save->base & 0xf)
2776 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2777 " aligned when entering protected mode (seg=%d)",
2778 seg);
6aa8b732
AK		 2779}
2780
2781static void enter_rmode(struct kvm_vcpu *vcpu)
2782{
2783 unsigned long flags;
a89a8fb9 2784 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2785
3a624e29
NK		 2786 if (enable_unrestricted_guest)
2787 return;
2788
a89a8fb9 2789 vmx->emulation_required = 1;
7ffd92c5 2790 vmx->rmode.vm86_active = 1;
6aa8b732 2791
776e58ea
GN		 2792 /*
2793 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2794 * vcpu. Call it here with phys address pointing 16M below 4G.
2795 */
2796 if (!vcpu->kvm->arch.tss_addr) {
2797 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2798 "called before entering vcpu\n");
2799 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2800 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2801 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2802 }
2803
2fb92db1
AK		 2804 vmx_segment_cache_clear(vmx);
2805
d0ba64f9 2806 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2807 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2808 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2809
7ffd92c5 2810 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2811 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2812
7ffd92c5 2813 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2814 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2815
2816 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2817 vmx->rmode.save_rflags = flags;
6aa8b732 2818
053de044 2819 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2820
2821 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2822 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2823 update_exception_bitmap(vcpu);
2824
a89a8fb9
MG		 2825 if (emulate_invalid_guest_state)
2826 goto continue_rmode;
2827
6aa8b732
AK		 2828 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2829 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2830 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2831
2832 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2833 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2834 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2835 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2836 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2837
7ffd92c5
AK		 2838 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2839 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2840 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2841 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2842
a89a8fb9 2843continue_rmode:
8668a3c4 2844 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2845}
2846
401d10de
AS		 2847static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2848{
2849 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2850 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2851
2852 if (!msr)
2853 return;
401d10de 2854
44ea2b17
AK		 2855 /*
2856 * Force kernel_gs_base reloading before EFER changes, as control
2857 * of this msr depends on is_long_mode().
2858 */
2859 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2860 vcpu->arch.efer = efer;
401d10de
AS		 2861 if (efer & EFER_LMA) {
2862 vmcs_write32(VM_ENTRY_CONTROLS,
2863 vmcs_read32(VM_ENTRY_CONTROLS) |
2864 VM_ENTRY_IA32E_MODE);
2865 msr->data = efer;
2866 } else {
2867 vmcs_write32(VM_ENTRY_CONTROLS,
2868 vmcs_read32(VM_ENTRY_CONTROLS) &
2869 ~VM_ENTRY_IA32E_MODE);
2870
2871 msr->data = efer & ~EFER_LME;
2872 }
2873 setup_msrs(vmx);
2874}
2875
05b3e0c2 2876#ifdef CONFIG_X86_64
6aa8b732
AK		 2877
2878static void enter_lmode(struct kvm_vcpu *vcpu)
2879{
2880 u32 guest_tr_ar;
2881
2fb92db1
AK		 2882 vmx_segment_cache_clear(to_vmx(vcpu));
2883
6aa8b732
AK		 2884 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2885 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2886 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2887 __func__);
6aa8b732
AK		 2888 vmcs_write32(GUEST_TR_AR_BYTES,
2889 (guest_tr_ar & ~AR_TYPE_MASK)
2890 | AR_TYPE_BUSY_64_TSS);
2891 }
da38f438 2892 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2893}
2894
2895static void exit_lmode(struct kvm_vcpu *vcpu)
2896{
6aa8b732
AK		 2897 vmcs_write32(VM_ENTRY_CONTROLS,
2898 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2899 & ~VM_ENTRY_IA32E_MODE);
da38f438 2900 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2901}
2902
2903#endif
2904
2384d2b3
SY		 2905static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2906{
b9d762fa 2907 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2908 if (enable_ept) {
2909 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2910 return;
4e1096d2 2911 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2912 }
2384d2b3
SY		 2913}
2914
e8467fda
AK		 2915static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2916{
2917 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2918
2919 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2920 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2921}
2922
aff48baa
AK		 2923static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2924{
2925 if (enable_ept && is_paging(vcpu))
2926 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2927 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2928}
2929
25c4c276 2930static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2931{
fc78f519
AK		 2932 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2933
2934 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2935 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2936}
2937
1439442c
SY		 2938static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2939{
6de4f3ad
AK		 2940 if (!test_bit(VCPU_EXREG_PDPTR,
2941 (unsigned long *)&vcpu->arch.regs_dirty))
2942 return;
2943
1439442c 2944 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2945 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2946 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2947 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2948 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2949 }
2950}
2951
8f5d549f
AK		 2952static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2953{
2954 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2955 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2956 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2957 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2958 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2959 }
6de4f3ad
AK		 2960
2961 __set_bit(VCPU_EXREG_PDPTR,
2962 (unsigned long *)&vcpu->arch.regs_avail);
2963 __set_bit(VCPU_EXREG_PDPTR,
2964 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2965}
2966
5e1746d6 2967static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2968
2969static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2970 unsigned long cr0,
2971 struct kvm_vcpu *vcpu)
2972{
5233dd51
MT		 2973 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2974 vmx_decache_cr3(vcpu);
1439442c
SY		 2975 if (!(cr0 & X86_CR0_PG)) {
2976 /* From paging/starting to nonpaging */
2977 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2978 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2979 (CPU_BASED_CR3_LOAD_EXITING |
2980 CPU_BASED_CR3_STORE_EXITING));
2981 vcpu->arch.cr0 = cr0;
fc78f519 2982 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2983 } else if (!is_paging(vcpu)) {
2984 /* From nonpaging to paging */
2985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2986 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2987 ~(CPU_BASED_CR3_LOAD_EXITING |
2988 CPU_BASED_CR3_STORE_EXITING));
2989 vcpu->arch.cr0 = cr0;
fc78f519 2990 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2991 }
95eb84a7
SY		 2992
2993 if (!(cr0 & X86_CR0_WP))
2994 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2995}
2996
6aa8b732
AK		 2997static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2998{
7ffd92c5 2999 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3000 unsigned long hw_cr0;
3001
3002 if (enable_unrestricted_guest)
3003 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3004 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3005 else
3006 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3007
7ffd92c5 3008 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3009 enter_pmode(vcpu);
3010
7ffd92c5 3011 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3012 enter_rmode(vcpu);
3013
05b3e0c2 3014#ifdef CONFIG_X86_64
f6801dff 3015 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3016 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3017 enter_lmode(vcpu);
707d92fa 3018 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3019 exit_lmode(vcpu);
3020 }
3021#endif
3022
089d034e 3023 if (enable_ept)
1439442c
SY		 3024 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3025
02daab21 3026 if (!vcpu->fpu_active)
81231c69 3027 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3028
6aa8b732 3029 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3030 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3031 vcpu->arch.cr0 = cr0;
69c73028 3032 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3033}
3034
1439442c
SY		 3035static u64 construct_eptp(unsigned long root_hpa)
3036{
3037 u64 eptp;
3038
3039 /* TODO write the value reading from MSR */
3040 eptp = VMX_EPT_DEFAULT_MT |
3041 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3042 if (enable_ept_ad_bits)
3043 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3044 eptp |= (root_hpa & PAGE_MASK);
3045
3046 return eptp;
3047}
3048
6aa8b732
AK		 3049static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3050{
1439442c
SY		 3051 unsigned long guest_cr3;
3052 u64 eptp;
3053
3054 guest_cr3 = cr3;
089d034e 3055 if (enable_ept) {
1439442c
SY		 3056 eptp = construct_eptp(cr3);
3057 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3058 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3059 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3060 ept_load_pdptrs(vcpu);
1439442c
SY		 3061 }
3062
2384d2b3 3063 vmx_flush_tlb(vcpu);
1439442c 3064 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3065}
3066
5e1746d6 3067static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3068{
7ffd92c5 3069 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3070 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3071
5e1746d6
NHE		 3072 if (cr4 & X86_CR4_VMXE) {
3073 /*
3074 * To use VMXON (and later other VMX instructions), a guest
3075 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3076 * So basically the check on whether to allow nested VMX
3077 * is here.
3078 */
3079 if (!nested_vmx_allowed(vcpu))
3080 return 1;
3081 } else if (to_vmx(vcpu)->nested.vmxon)
3082 return 1;
3083
ad312c7c 3084 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3085 if (enable_ept) {
3086 if (!is_paging(vcpu)) {
3087 hw_cr4 &= ~X86_CR4_PAE;
3088 hw_cr4 |= X86_CR4_PSE;
3089 } else if (!(cr4 & X86_CR4_PAE)) {
3090 hw_cr4 &= ~X86_CR4_PAE;
3091 }
3092 }
1439442c
SY		 3093
3094 vmcs_writel(CR4_READ_SHADOW, cr4);
3095 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3096 return 0;
6aa8b732
AK		 3097}
3098
6aa8b732
AK		 3099static void vmx_get_segment(struct kvm_vcpu *vcpu,
3100 struct kvm_segment *var, int seg)
3101{
a9179499 3102 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3103 struct kvm_save_segment *save;
6aa8b732
AK		 3104 u32 ar;
3105
a9179499
AK		 3106 if (vmx->rmode.vm86_active
3107 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3108 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3109 || seg == VCPU_SREG_GS)
3110 && !emulate_invalid_guest_state) {
3111 switch (seg) {
3112 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3113 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3114 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3115 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3116 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3117 default: BUG();
3118 }
3119 var->selector = save->selector;
3120 var->base = save->base;
3121 var->limit = save->limit;
3122 ar = save->ar;
3123 if (seg == VCPU_SREG_TR
2fb92db1 3124 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3125 goto use_saved_rmode_seg;
3126 }
2fb92db1
AK		 3127 var->base = vmx_read_guest_seg_base(vmx, seg);
3128 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3129 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3130 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3131use_saved_rmode_seg:
9fd4a3b7 3132 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3133 ar = 0;
3134 var->type = ar & 15;
3135 var->s = (ar >> 4) & 1;
3136 var->dpl = (ar >> 5) & 3;
3137 var->present = (ar >> 7) & 1;
3138 var->avl = (ar >> 12) & 1;
3139 var->l = (ar >> 13) & 1;
3140 var->db = (ar >> 14) & 1;
3141 var->g = (ar >> 15) & 1;
3142 var->unusable = (ar >> 16) & 1;
3143}
3144
a9179499
AK		 3145static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3146{
a9179499
AK		 3147 struct kvm_segment s;
3148
3149 if (to_vmx(vcpu)->rmode.vm86_active) {
3150 vmx_get_segment(vcpu, &s, seg);
3151 return s.base;
3152 }
2fb92db1 3153 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3154}
3155
69c73028 3156static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3157{
3eeb3288 3158 if (!is_protmode(vcpu))
2e4d2653
IE		 3159 return 0;
3160
f4c63e5d
AK		 3161 if (!is_long_mode(vcpu)
3162 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3163 return 3;
3164
2fb92db1 3165 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3166}
3167
69c73028
AK		 3168static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3169{
3170 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3171 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3172 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3173 }
3174 return to_vmx(vcpu)->cpl;
3175}
3176
3177
653e3108 3178static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3179{
6aa8b732
AK		 3180 u32 ar;
3181
653e3108 3182 if (var->unusable)
6aa8b732
AK		 3183 ar = 1 << 16;
3184 else {
3185 ar = var->type & 15;
3186 ar |= (var->s & 1) << 4;
3187 ar |= (var->dpl & 3) << 5;
3188 ar |= (var->present & 1) << 7;
3189 ar |= (var->avl & 1) << 12;
3190 ar |= (var->l & 1) << 13;
3191 ar |= (var->db & 1) << 14;
3192 ar |= (var->g & 1) << 15;
3193 }
f7fbf1fd
UL		 3194 if (ar == 0) /* a 0 value means unusable */
3195 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3196
3197 return ar;
3198}
3199
3200static void vmx_set_segment(struct kvm_vcpu *vcpu,
3201 struct kvm_segment *var, int seg)
3202{
7ffd92c5 3203 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3204 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3205 u32 ar;
3206
2fb92db1
AK		 3207 vmx_segment_cache_clear(vmx);
3208
7ffd92c5 3209 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3210 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3211 vmx->rmode.tr.selector = var->selector;
3212 vmx->rmode.tr.base = var->base;
3213 vmx->rmode.tr.limit = var->limit;
3214 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3215 return;
3216 }
3217 vmcs_writel(sf->base, var->base);
3218 vmcs_write32(sf->limit, var->limit);
3219 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3220 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3221 /*
3222 * Hack real-mode segments into vm86 compatibility.
3223 */
3224 if (var->base == 0xffff0000 && var->selector == 0xf000)
3225 vmcs_writel(sf->base, 0xf0000);
3226 ar = 0xf3;
3227 } else
3228 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3229
3230 /*
3231 * Fix the "Accessed" bit in AR field of segment registers for older
3232 * qemu binaries.
3233 * IA32 arch specifies that at the time of processor reset the
3234 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3235 * is setting it to 0 in the usedland code. This causes invalid guest
3236 * state vmexit when "unrestricted guest" mode is turned on.
3237 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3238 * tree. Newer qemu binaries with that qemu fix would not need this
3239 * kvm hack.
3240 */
3241 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3242 ar |= 0x1; /* Accessed */
3243
6aa8b732 3244 vmcs_write32(sf->ar_bytes, ar);
69c73028 3245 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3246}
3247
6aa8b732
AK		 3248static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3249{
2fb92db1 3250 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3251
3252 *db = (ar >> 14) & 1;
3253 *l = (ar >> 13) & 1;
3254}
3255
89a27f4d 3256static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3257{
89a27f4d
GN		 3258 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3259 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3260}
3261
89a27f4d 3262static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3263{
89a27f4d
GN		 3264 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3265 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3266}
3267
89a27f4d 3268static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3269{
89a27f4d
GN		 3270 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3271 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3272}
3273
89a27f4d 3274static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3275{
89a27f4d
GN		 3276 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3277 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3278}
3279
648dfaa7
MG		 3280static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3281{
3282 struct kvm_segment var;
3283 u32 ar;
3284
3285 vmx_get_segment(vcpu, &var, seg);
3286 ar = vmx_segment_access_rights(&var);
3287
3288 if (var.base != (var.selector << 4))
3289 return false;
3290 if (var.limit != 0xffff)
3291 return false;
3292 if (ar != 0xf3)
3293 return false;
3294
3295 return true;
3296}
3297
3298static bool code_segment_valid(struct kvm_vcpu *vcpu)
3299{
3300 struct kvm_segment cs;
3301 unsigned int cs_rpl;
3302
3303 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3304 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3305
1872a3f4
AK		 3306 if (cs.unusable)
3307 return false;
648dfaa7
MG		 3308 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3309 return false;
3310 if (!cs.s)
3311 return false;
1872a3f4 3312 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3313 if (cs.dpl > cs_rpl)
3314 return false;
1872a3f4 3315 } else {
648dfaa7
MG		 3316 if (cs.dpl != cs_rpl)
3317 return false;
3318 }
3319 if (!cs.present)
3320 return false;
3321
3322 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3323 return true;
3324}
3325
3326static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3327{
3328 struct kvm_segment ss;
3329 unsigned int ss_rpl;
3330
3331 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3332 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3333
1872a3f4
AK		 3334 if (ss.unusable)
3335 return true;
3336 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3337 return false;
3338 if (!ss.s)
3339 return false;
3340 if (ss.dpl != ss_rpl) /* DPL != RPL */
3341 return false;
3342 if (!ss.present)
3343 return false;
3344
3345 return true;
3346}
3347
3348static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3349{
3350 struct kvm_segment var;
3351 unsigned int rpl;
3352
3353 vmx_get_segment(vcpu, &var, seg);
3354 rpl = var.selector & SELECTOR_RPL_MASK;
3355
1872a3f4
AK		 3356 if (var.unusable)
3357 return true;
648dfaa7
MG		 3358 if (!var.s)
3359 return false;
3360 if (!var.present)
3361 return false;
3362 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3363 if (var.dpl < rpl) /* DPL < RPL */
3364 return false;
3365 }
3366
3367 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3368 * rights flags
3369 */
3370 return true;
3371}
3372
3373static bool tr_valid(struct kvm_vcpu *vcpu)
3374{
3375 struct kvm_segment tr;
3376
3377 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3378
1872a3f4
AK		 3379 if (tr.unusable)
3380 return false;
648dfaa7
MG		 3381 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3382 return false;
1872a3f4 3383 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3384 return false;
3385 if (!tr.present)
3386 return false;
3387
3388 return true;
3389}
3390
3391static bool ldtr_valid(struct kvm_vcpu *vcpu)
3392{
3393 struct kvm_segment ldtr;
3394
3395 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3396
1872a3f4
AK		 3397 if (ldtr.unusable)
3398 return true;
648dfaa7
MG		 3399 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3400 return false;
3401 if (ldtr.type != 2)
3402 return false;
3403 if (!ldtr.present)
3404 return false;
3405
3406 return true;
3407}
3408
3409static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3410{
3411 struct kvm_segment cs, ss;
3412
3413 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3414 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3415
3416 return ((cs.selector & SELECTOR_RPL_MASK) ==
3417 (ss.selector & SELECTOR_RPL_MASK));
3418}
3419
3420/*
3421 * Check if guest state is valid. Returns true if valid, false if
3422 * not.
3423 * We assume that registers are always usable
3424 */
3425static bool guest_state_valid(struct kvm_vcpu *vcpu)
3426{
3427 /* real mode guest state checks */
3eeb3288 3428 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3429 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3430 return false;
3431 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3432 return false;
3433 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3434 return false;
3435 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3436 return false;
3437 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3438 return false;
3439 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3440 return false;
3441 } else {
3442 /* protected mode guest state checks */
3443 if (!cs_ss_rpl_check(vcpu))
3444 return false;
3445 if (!code_segment_valid(vcpu))
3446 return false;
3447 if (!stack_segment_valid(vcpu))
3448 return false;
3449 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3450 return false;
3451 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3452 return false;
3453 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3454 return false;
3455 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3456 return false;
3457 if (!tr_valid(vcpu))
3458 return false;
3459 if (!ldtr_valid(vcpu))
3460 return false;
3461 }
3462 /* TODO:
3463 * - Add checks on RIP
3464 * - Add checks on RFLAGS
3465 */
3466
3467 return true;
3468}
3469
d77c26fc 3470static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3471{
40dcaa9f 3472 gfn_t fn;
195aefde 3473 u16 data = 0;
40dcaa9f 3474 int r, idx, ret = 0;
6aa8b732 3475
40dcaa9f
XG		 3476 idx = srcu_read_lock(&kvm->srcu);
3477 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3478 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3479 if (r < 0)
10589a46 3480 goto out;
195aefde 3481 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3482 r = kvm_write_guest_page(kvm, fn++, &data,
3483 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3484 if (r < 0)
10589a46 3485 goto out;
195aefde
IE		 3486 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3487 if (r < 0)
10589a46 3488 goto out;
195aefde
IE		 3489 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3490 if (r < 0)
10589a46 3491 goto out;
195aefde 3492 data = ~0;
10589a46
MT		 3493 r = kvm_write_guest_page(kvm, fn, &data,
3494 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3495 sizeof(u8));
195aefde 3496 if (r < 0)
10589a46
MT		 3497 goto out;
3498
3499 ret = 1;
3500out:
40dcaa9f 3501 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3502 return ret;
6aa8b732
AK		 3503}
3504
b7ebfb05
SY		 3505static int init_rmode_identity_map(struct kvm *kvm)
3506{
40dcaa9f 3507 int i, idx, r, ret;
b7ebfb05
SY		 3508 pfn_t identity_map_pfn;
3509 u32 tmp;
3510
089d034e 3511 if (!enable_ept)
b7ebfb05
SY		 3512 return 1;
3513 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3514 printk(KERN_ERR "EPT: identity-mapping pagetable "
3515 "haven't been allocated!\n");
3516 return 0;
3517 }
3518 if (likely(kvm->arch.ept_identity_pagetable_done))
3519 return 1;
3520 ret = 0;
b927a3ce 3521 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3522 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3523 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3524 if (r < 0)
3525 goto out;
3526 /* Set up identity-mapping pagetable for EPT in real mode */
3527 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3528 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3529 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3530 r = kvm_write_guest_page(kvm, identity_map_pfn,
3531 &tmp, i * sizeof(tmp), sizeof(tmp));
3532 if (r < 0)
3533 goto out;
3534 }
3535 kvm->arch.ept_identity_pagetable_done = true;
3536 ret = 1;
3537out:
40dcaa9f 3538 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3539 return ret;
3540}
3541
6aa8b732
AK		 3542static void seg_setup(int seg)
3543{
3544 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3545 unsigned int ar;
6aa8b732
AK		 3546
3547 vmcs_write16(sf->selector, 0);
3548 vmcs_writel(sf->base, 0);
3549 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3550 if (enable_unrestricted_guest) {
3551 ar = 0x93;
3552 if (seg == VCPU_SREG_CS)
3553 ar |= 0x08; /* code segment */
3554 } else
3555 ar = 0xf3;
3556
3557 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3558}
3559
f78e0e2e
SY		 3560static int alloc_apic_access_page(struct kvm *kvm)
3561{
3562 struct kvm_userspace_memory_region kvm_userspace_mem;
3563 int r = 0;
3564
79fac95e 3565 mutex_lock(&kvm->slots_lock);
bfc6d222 3566 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3567 goto out;
3568 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3569 kvm_userspace_mem.flags = 0;
3570 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3571 kvm_userspace_mem.memory_size = PAGE_SIZE;
3572 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3573 if (r)
3574 goto out;
72dc67a6 3575
bfc6d222 3576 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3577out:
79fac95e 3578 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3579 return r;
3580}
3581
b7ebfb05
SY		 3582static int alloc_identity_pagetable(struct kvm *kvm)
3583{
3584 struct kvm_userspace_memory_region kvm_userspace_mem;
3585 int r = 0;
3586
79fac95e 3587 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3588 if (kvm->arch.ept_identity_pagetable)
3589 goto out;
3590 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3591 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3592 kvm_userspace_mem.guest_phys_addr =
3593 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3594 kvm_userspace_mem.memory_size = PAGE_SIZE;
3595 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3596 if (r)
3597 goto out;
3598
b7ebfb05 3599 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3600 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3601out:
79fac95e 3602 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3603 return r;
3604}
3605
2384d2b3
SY		 3606static void allocate_vpid(struct vcpu_vmx *vmx)
3607{
3608 int vpid;
3609
3610 vmx->vpid = 0;
919818ab 3611 if (!enable_vpid)
2384d2b3
SY		 3612 return;
3613 spin_lock(&vmx_vpid_lock);
3614 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3615 if (vpid < VMX_NR_VPIDS) {
3616 vmx->vpid = vpid;
3617 __set_bit(vpid, vmx_vpid_bitmap);
3618 }
3619 spin_unlock(&vmx_vpid_lock);
3620}
3621
cdbecfc3
LJ		 3622static void free_vpid(struct vcpu_vmx *vmx)
3623{
3624 if (!enable_vpid)
3625 return;
3626 spin_lock(&vmx_vpid_lock);
3627 if (vmx->vpid != 0)
3628 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3629 spin_unlock(&vmx_vpid_lock);
3630}
3631
5897297b 3632static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3633{
3e7c73e9 3634 int f = sizeof(unsigned long);
25c5f225
SY		 3635
3636 if (!cpu_has_vmx_msr_bitmap())
3637 return;
3638
3639 /*
3640 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3641 * have the write-low and read-high bitmap offsets the wrong way round.
3642 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3643 */
25c5f225 3644 if (msr <= 0x1fff) {
3e7c73e9
AK		 3645 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3646 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3647 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3648 msr &= 0x1fff;
3e7c73e9
AK		 3649 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3650 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3651 }
25c5f225
SY		 3652}
3653
5897297b
AK		 3654static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3655{
3656 if (!longmode_only)
3657 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3658 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3659}
3660
a3a8ff8e
NHE		 3661/*
3662 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3663 * will not change in the lifetime of the guest.
3664 * Note that host-state that does change is set elsewhere. E.g., host-state
3665 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3666 */
3667static void vmx_set_constant_host_state(void)
3668{
3669 u32 low32, high32;
3670 unsigned long tmpl;
3671 struct desc_ptr dt;
3672
3673 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3674 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3675 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3676
3677 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3678#ifdef CONFIG_X86_64
3679 /*
3680 * Load null selectors, so we can avoid reloading them in
3681 * __vmx_load_host_state(), in case userspace uses the null selectors
3682 * too (the expected case).
3683 */
3684 vmcs_write16(HOST_DS_SELECTOR, 0);
3685 vmcs_write16(HOST_ES_SELECTOR, 0);
3686#else
a3a8ff8e
NHE		 3687 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3688 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3689#endif
a3a8ff8e
NHE		 3690 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3691 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3692
3693 native_store_idt(&dt);
3694 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3695
3696 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3697 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3698
3699 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3700 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3701 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3702 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3703
3704 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3705 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3706 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3707 }
3708}
3709
bf8179a0
NHE		 3710static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3711{
3712 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3713 if (enable_ept)
3714 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3715 if (is_guest_mode(&vmx->vcpu))
3716 vmx->vcpu.arch.cr4_guest_owned_bits &=
3717 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3718 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3719}
3720
3721static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3722{
3723 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3724 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3725 exec_control &= ~CPU_BASED_TPR_SHADOW;
3726#ifdef CONFIG_X86_64
3727 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3728 CPU_BASED_CR8_LOAD_EXITING;
3729#endif
3730 }
3731 if (!enable_ept)
3732 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3733 CPU_BASED_CR3_LOAD_EXITING |
3734 CPU_BASED_INVLPG_EXITING;
3735 return exec_control;
3736}
3737
3738static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3739{
3740 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3741 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3742 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3743 if (vmx->vpid == 0)
3744 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3745 if (!enable_ept) {
3746 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3747 enable_unrestricted_guest = 0;
3748 }
3749 if (!enable_unrestricted_guest)
3750 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3751 if (!ple_gap)
3752 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3753 return exec_control;
3754}
3755
ce88decf
XG		 3756static void ept_set_mmio_spte_mask(void)
3757{
3758 /*
3759 * EPT Misconfigurations can be generated if the value of bits 2:0
3760 * of an EPT paging-structure entry is 110b (write/execute).
3761 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3762 * spte.
3763 */
3764 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3765}
3766
6aa8b732
AK		 3767/*
3768 * Sets up the vmcs for emulated real mode.
3769 */
8b9cf98c 3770static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3771{
2e4ce7f5 3772#ifdef CONFIG_X86_64
6aa8b732 3773 unsigned long a;
2e4ce7f5 3774#endif
6aa8b732 3775 int i;
6aa8b732 3776
6aa8b732 3777 /* I/O */
3e7c73e9
AK		 3778 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3779 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3780
25c5f225 3781 if (cpu_has_vmx_msr_bitmap())
5897297b 3782 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3783
6aa8b732
AK		 3784 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3785
6aa8b732 3786 /* Control */
1c3d14fe
YS		 3787 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3788 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3789
bf8179a0 3790 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3791
83ff3b9d 3792 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3793 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3794 vmx_secondary_exec_control(vmx));
83ff3b9d 3795 }
f78e0e2e 3796
4b8d54f9
ZE		 3797 if (ple_gap) {
3798 vmcs_write32(PLE_GAP, ple_gap);
3799 vmcs_write32(PLE_WINDOW, ple_window);
3800 }
3801
c3707958
XG		 3802 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3803 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3804 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3805
9581d442
AK		 3806 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3807 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3808 vmx_set_constant_host_state();
05b3e0c2 3809#ifdef CONFIG_X86_64
6aa8b732
AK		 3810 rdmsrl(MSR_FS_BASE, a);
3811 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3812 rdmsrl(MSR_GS_BASE, a);
3813 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3814#else
3815 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3816 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3817#endif
3818
2cc51560
ED		 3819 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3820 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3821 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3822 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3823 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3824
468d472f 3825 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3826 u32 msr_low, msr_high;
3827 u64 host_pat;
468d472f
SY		 3828 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3829 host_pat = msr_low | ((u64) msr_high << 32);
3830 /* Write the default value follow host pat */
3831 vmcs_write64(GUEST_IA32_PAT, host_pat);
3832 /* Keep arch.pat sync with GUEST_IA32_PAT */
3833 vmx->vcpu.arch.pat = host_pat;
3834 }
3835
6aa8b732
AK		 3836 for (i = 0; i < NR_VMX_MSR; ++i) {
3837 u32 index = vmx_msr_index[i];
3838 u32 data_low, data_high;
a2fa3e9f 3839 int j = vmx->nmsrs;
6aa8b732
AK		 3840
3841 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3842 continue;
432bd6cb
AK		 3843 if (wrmsr_safe(index, data_low, data_high) < 0)
3844 continue;
26bb0981
AK		 3845 vmx->guest_msrs[j].index = i;
3846 vmx->guest_msrs[j].data = 0;
d5696725 3847 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3848 ++vmx->nmsrs;
6aa8b732 3849 }
6aa8b732 3850
1c3d14fe 3851 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3852
3853 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3854 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3855
e00c8cf2 3856 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3857 set_cr4_guest_host_mask(vmx);
e00c8cf2 3858
99e3e30a 3859 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3860
e00c8cf2
AK		 3861 return 0;
3862}
3863
3864static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3865{
3866 struct vcpu_vmx *vmx = to_vmx(vcpu);
3867 u64 msr;
4b9d3a04 3868 int ret;
e00c8cf2 3869
5fdbf976 3870 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3871
7ffd92c5 3872 vmx->rmode.vm86_active = 0;
e00c8cf2 3873
3b86cd99
JK		 3874 vmx->soft_vnmi_blocked = 0;
3875
ad312c7c 3876 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3877 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3878 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3879 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3880 msr |= MSR_IA32_APICBASE_BSP;
3881 kvm_set_apic_base(&vmx->vcpu, msr);
3882
10ab25cd
JK		 3883 ret = fx_init(&vmx->vcpu);
3884 if (ret != 0)
3885 goto out;
e00c8cf2 3886
2fb92db1
AK		 3887 vmx_segment_cache_clear(vmx);
3888
5706be0d 3889 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3890 /*
3891 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3892 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3893 */
c5af89b6 3894 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3895 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3896 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3897 } else {
ad312c7c
ZX		 3898 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3899 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3900 }
e00c8cf2
AK		 3901
3902 seg_setup(VCPU_SREG_DS);
3903 seg_setup(VCPU_SREG_ES);
3904 seg_setup(VCPU_SREG_FS);
3905 seg_setup(VCPU_SREG_GS);
3906 seg_setup(VCPU_SREG_SS);
3907
3908 vmcs_write16(GUEST_TR_SELECTOR, 0);
3909 vmcs_writel(GUEST_TR_BASE, 0);
3910 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3911 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3912
3913 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3914 vmcs_writel(GUEST_LDTR_BASE, 0);
3915 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3916 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3917
3918 vmcs_write32(GUEST_SYSENTER_CS, 0);
3919 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3920 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3921
3922 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3923 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3924 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3925 else
5fdbf976
MT		 3926 kvm_rip_write(vcpu, 0);
3927 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3928
e00c8cf2
AK		 3929 vmcs_writel(GUEST_DR7, 0x400);
3930
3931 vmcs_writel(GUEST_GDTR_BASE, 0);
3932 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3933
3934 vmcs_writel(GUEST_IDTR_BASE, 0);
3935 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3936
443381a8 3937 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3938 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3939 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3940
e00c8cf2
AK		 3941 /* Special registers */
3942 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3943
3944 setup_msrs(vmx);
3945
6aa8b732
AK		 3946 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3947
f78e0e2e
SY		 3948 if (cpu_has_vmx_tpr_shadow()) {
3949 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3950 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3951 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3952 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3953 vmcs_write32(TPR_THRESHOLD, 0);
3954 }
3955
3956 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3957 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3958 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3959
2384d2b3
SY		 3960 if (vmx->vpid != 0)
3961 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3962
fa40052c 3963 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 3964 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 3965 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 3966 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 3967 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3968 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3969 vmx_fpu_activate(&vmx->vcpu);
3970 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3971
b9d762fa 3972 vpid_sync_context(vmx);
2384d2b3 3973
3200f405 3974 ret = 0;
6aa8b732 3975
a89a8fb9
MG		 3976 /* HACK: Don't enable emulation on guest boot/reset */
3977 vmx->emulation_required = 0;
3978
6aa8b732
AK		 3979out:
3980 return ret;
3981}
3982
b6f1250e
NHE		 3983/*
3984 * In nested virtualization, check if L1 asked to exit on external interrupts.
3985 * For most existing hypervisors, this will always return true.
3986 */
3987static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3988{
3989 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3990 PIN_BASED_EXT_INTR_MASK;
3991}
3992
3b86cd99
JK		 3993static void enable_irq_window(struct kvm_vcpu *vcpu)
3994{
3995 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 3996 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3997 /*
3998 * We get here if vmx_interrupt_allowed() said we can't
3999 * inject to L1 now because L2 must run. Ask L2 to exit
4000 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4001 */
d6185f20 4002 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4003 return;
d6185f20 4004 }
3b86cd99
JK		 4005
4006 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4007 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4008 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4009}
4010
4011static void enable_nmi_window(struct kvm_vcpu *vcpu)
4012{
4013 u32 cpu_based_vm_exec_control;
4014
4015 if (!cpu_has_virtual_nmis()) {
4016 enable_irq_window(vcpu);
4017 return;
4018 }
4019
30bd0c4c
AK		 4020 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4021 enable_irq_window(vcpu);
4022 return;
4023 }
3b86cd99
JK		 4024 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4025 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4026 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4027}
4028
66fd3f7f 4029static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4030{
9c8cba37 4031 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4032 uint32_t intr;
4033 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4034
229456fc 4035 trace_kvm_inj_virq(irq);
2714d1d3 4036
fa89a817 4037 ++vcpu->stat.irq_injections;
7ffd92c5 4038 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4039 int inc_eip = 0;
4040 if (vcpu->arch.interrupt.soft)
4041 inc_eip = vcpu->arch.event_exit_inst_len;
4042 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4043 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4044 return;
4045 }
66fd3f7f
GN		 4046 intr = irq | INTR_INFO_VALID_MASK;
4047 if (vcpu->arch.interrupt.soft) {
4048 intr |= INTR_TYPE_SOFT_INTR;
4049 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4050 vmx->vcpu.arch.event_exit_inst_len);
4051 } else
4052 intr |= INTR_TYPE_EXT_INTR;
4053 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4054}
4055
f08864b4
SY		 4056static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4057{
66a5a347
JK		 4058 struct vcpu_vmx *vmx = to_vmx(vcpu);
4059
0b6ac343
NHE		 4060 if (is_guest_mode(vcpu))
4061 return;
4062
3b86cd99
JK		 4063 if (!cpu_has_virtual_nmis()) {
4064 /*
4065 * Tracking the NMI-blocked state in software is built upon
4066 * finding the next open IRQ window. This, in turn, depends on
4067 * well-behaving guests: They have to keep IRQs disabled at
4068 * least as long as the NMI handler runs. Otherwise we may
4069 * cause NMI nesting, maybe breaking the guest. But as this is
4070 * highly unlikely, we can live with the residual risk.
4071 */
4072 vmx->soft_vnmi_blocked = 1;
4073 vmx->vnmi_blocked_time = 0;
4074 }
4075
487b391d 4076 ++vcpu->stat.nmi_injections;
9d58b931 4077 vmx->nmi_known_unmasked = false;
7ffd92c5 4078 if (vmx->rmode.vm86_active) {
71f9833b 4079 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4080 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4081 return;
4082 }
f08864b4
SY		 4083 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4084 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4085}
4086
c4282df9 4087static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4088{
3b86cd99 4089 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4090 return 0;
33f089ca 4091
c4282df9 4092 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4093 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4094 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4095}
4096
3cfc3092
JK		 4097static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4098{
4099 if (!cpu_has_virtual_nmis())
4100 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4101 if (to_vmx(vcpu)->nmi_known_unmasked)
4102 return false;
c332c83a 4103 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4104}
4105
4106static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4107{
4108 struct vcpu_vmx *vmx = to_vmx(vcpu);
4109
4110 if (!cpu_has_virtual_nmis()) {
4111 if (vmx->soft_vnmi_blocked != masked) {
4112 vmx->soft_vnmi_blocked = masked;
4113 vmx->vnmi_blocked_time = 0;
4114 }
4115 } else {
9d58b931 4116 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4117 if (masked)
4118 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4119 GUEST_INTR_STATE_NMI);
4120 else
4121 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4122 GUEST_INTR_STATE_NMI);
4123 }
4124}
4125
78646121
GN		 4126static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4127{
b6f1250e 4128 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4129 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4130 if (to_vmx(vcpu)->nested.nested_run_pending ||
4131 (vmcs12->idt_vectoring_info_field &
4132 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4133 return 0;
4134 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4135 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4136 vmcs12->vm_exit_intr_info = 0;
4137 /* fall through to normal code, but now in L1, not L2 */
4138 }
4139
c4282df9
GN		 4140 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4141 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4142 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4143}
4144
cbc94022
IE		 4145static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4146{
4147 int ret;
4148 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4149 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4150 .guest_phys_addr = addr,
4151 .memory_size = PAGE_SIZE * 3,
4152 .flags = 0,
4153 };
4154
4155 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4156 if (ret)
4157 return ret;
bfc6d222 4158 kvm->arch.tss_addr = addr;
93ea5388
GN		 4159 if (!init_rmode_tss(kvm))
4160 return -ENOMEM;
4161
cbc94022
IE		 4162 return 0;
4163}
4164
6aa8b732
AK		 4165static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4166 int vec, u32 err_code)
4167{
b3f37707
NK		 4168 /*
4169 * Instruction with address size override prefix opcode 0x67
4170 * Cause the #SS fault with 0 error code in VM86 mode.
4171 */
4172 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4173 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4174 return 1;
77ab6db0
JK		 4175 /*
4176 * Forward all other exceptions that are valid in real mode.
4177 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4178 * the required debugging infrastructure rework.
4179 */
4180 switch (vec) {
77ab6db0 4181 case DB_VECTOR:
d0bfb940
JK		 4182 if (vcpu->guest_debug &
4183 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4184 return 0;
4185 kvm_queue_exception(vcpu, vec);
4186 return 1;
77ab6db0 4187 case BP_VECTOR:
c573cd22
JK		 4188 /*
4189 * Update instruction length as we may reinject the exception
4190 * from user space while in guest debugging mode.
4191 */
4192 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4193 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4194 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4195 return 0;
4196 /* fall through */
4197 case DE_VECTOR:
77ab6db0
JK		 4198 case OF_VECTOR:
4199 case BR_VECTOR:
4200 case UD_VECTOR:
4201 case DF_VECTOR:
4202 case SS_VECTOR:
4203 case GP_VECTOR:
4204 case MF_VECTOR:
4205 kvm_queue_exception(vcpu, vec);
4206 return 1;
4207 }
6aa8b732
AK		 4208 return 0;
4209}
4210
a0861c02
AK		 4211/*
4212 * Trigger machine check on the host. We assume all the MSRs are already set up
4213 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4214 * We pass a fake environment to the machine check handler because we want
4215 * the guest to be always treated like user space, no matter what context
4216 * it used internally.
4217 */
4218static void kvm_machine_check(void)
4219{
4220#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4221 struct pt_regs regs = {
4222 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4223 .flags = X86_EFLAGS_IF,
4224 };
4225
4226 do_machine_check(&regs, 0);
4227#endif
4228}
4229
851ba692 4230static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4231{
4232 /* already handled by vcpu_run */
4233 return 1;
4234}
4235
851ba692 4236static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4237{
1155f76a 4238 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4239 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4240 u32 intr_info, ex_no, error_code;
42dbaa5a 4241 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4242 u32 vect_info;
4243 enum emulation_result er;
4244
1155f76a 4245 vect_info = vmx->idt_vectoring_info;
88786475 4246 intr_info = vmx->exit_intr_info;
6aa8b732 4247
a0861c02 4248 if (is_machine_check(intr_info))
851ba692 4249 return handle_machine_check(vcpu);
a0861c02 4250
6aa8b732 4251 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4252 !is_page_fault(intr_info)) {
4253 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4254 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4255 vcpu->run->internal.ndata = 2;
4256 vcpu->run->internal.data[0] = vect_info;
4257 vcpu->run->internal.data[1] = intr_info;
4258 return 0;
4259 }
6aa8b732 4260
e4a41889 4261 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4262 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4263
4264 if (is_no_device(intr_info)) {
5fd86fcf 4265 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4266 return 1;
4267 }
4268
7aa81cc0 4269 if (is_invalid_opcode(intr_info)) {
51d8b661 4270 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4271 if (er != EMULATE_DONE)
7ee5d940 4272 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4273 return 1;
4274 }
4275
6aa8b732 4276 error_code = 0;
2e11384c 4277 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4278 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4279 if (is_page_fault(intr_info)) {
1439442c 4280 /* EPT won't cause page fault directly */
cf3ace79 4281 BUG_ON(enable_ept);
6aa8b732 4282 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4283 trace_kvm_page_fault(cr2, error_code);
4284
3298b75c 4285 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4286 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4287 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4288 }
4289
7ffd92c5 4290 if (vmx->rmode.vm86_active &&
6aa8b732 4291 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4292 error_code)) {
ad312c7c
ZX		 4293 if (vcpu->arch.halt_request) {
4294 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4295 return kvm_emulate_halt(vcpu);
4296 }
6aa8b732 4297 return 1;
72d6e5a0 4298 }
6aa8b732 4299
d0bfb940 4300 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4301 switch (ex_no) {
4302 case DB_VECTOR:
4303 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4304 if (!(vcpu->guest_debug &
4305 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4306 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4307 kvm_queue_exception(vcpu, DB_VECTOR);
4308 return 1;
4309 }
4310 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4311 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4312 /* fall through */
4313 case BP_VECTOR:
c573cd22
JK		 4314 /*
4315 * Update instruction length as we may reinject #BP from
4316 * user space while in guest debugging mode. Reading it for
4317 * #DB as well causes no harm, it is not used in that case.
4318 */
4319 vmx->vcpu.arch.event_exit_inst_len =
4320 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4321 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4322 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4323 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4324 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4325 break;
4326 default:
d0bfb940
JK		 4327 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4328 kvm_run->ex.exception = ex_no;
4329 kvm_run->ex.error_code = error_code;
42dbaa5a 4330 break;
6aa8b732 4331 }
6aa8b732
AK		 4332 return 0;
4333}
4334
851ba692 4335static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4336{
1165f5fe 4337 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4338 return 1;
4339}
4340
851ba692 4341static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4342{
851ba692 4343 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4344 return 0;
4345}
6aa8b732 4346
851ba692 4347static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4348{
bfdaab09 4349 unsigned long exit_qualification;
34c33d16 4350 int size, in, string;
039576c0 4351 unsigned port;
6aa8b732 4352
bfdaab09 4353 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4354 string = (exit_qualification & 16) != 0;
cf8f70bf 4355 in = (exit_qualification & 8) != 0;
e70669ab 4356
cf8f70bf 4357 ++vcpu->stat.io_exits;
e70669ab 4358
cf8f70bf 4359 if (string || in)
51d8b661 4360 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4361
cf8f70bf
GN		 4362 port = exit_qualification >> 16;
4363 size = (exit_qualification & 7) + 1;
e93f36bc 4364 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4365
4366 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4367}
4368
102d8325
IM		 4369static void
4370vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4371{
4372 /*
4373 * Patch in the VMCALL instruction:
4374 */
4375 hypercall[0] = 0x0f;
4376 hypercall[1] = 0x01;
4377 hypercall[2] = 0xc1;
102d8325
IM		 4378}
4379
eeadf9e7
NHE		 4380/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4381static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4382{
4383 if (to_vmx(vcpu)->nested.vmxon &&
4384 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4385 return 1;
4386
4387 if (is_guest_mode(vcpu)) {
4388 /*
4389 * We get here when L2 changed cr0 in a way that did not change
4390 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4391 * but did change L0 shadowed bits. This can currently happen
4392 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4393 * loading) while pretending to allow the guest to change it.
4394 */
4395 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4396 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4397 return 1;
4398 vmcs_writel(CR0_READ_SHADOW, val);
4399 return 0;
4400 } else
4401 return kvm_set_cr0(vcpu, val);
4402}
4403
4404static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4405{
4406 if (is_guest_mode(vcpu)) {
4407 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4408 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4409 return 1;
4410 vmcs_writel(CR4_READ_SHADOW, val);
4411 return 0;
4412 } else
4413 return kvm_set_cr4(vcpu, val);
4414}
4415
4416/* called to set cr0 as approriate for clts instruction exit. */
4417static void handle_clts(struct kvm_vcpu *vcpu)
4418{
4419 if (is_guest_mode(vcpu)) {
4420 /*
4421 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4422 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4423 * just pretend it's off (also in arch.cr0 for fpu_activate).
4424 */
4425 vmcs_writel(CR0_READ_SHADOW,
4426 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4427 vcpu->arch.cr0 &= ~X86_CR0_TS;
4428 } else
4429 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4430}
4431
851ba692 4432static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4433{
229456fc 4434 unsigned long exit_qualification, val;
6aa8b732
AK		 4435 int cr;
4436 int reg;
49a9b07e 4437 int err;
6aa8b732 4438
bfdaab09 4439 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4440 cr = exit_qualification & 15;
4441 reg = (exit_qualification >> 8) & 15;
4442 switch ((exit_qualification >> 4) & 3) {
4443 case 0: /* mov to cr */
229456fc
MT		 4444 val = kvm_register_read(vcpu, reg);
4445 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4446 switch (cr) {
4447 case 0:
eeadf9e7 4448 err = handle_set_cr0(vcpu, val);
db8fcefa 4449 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4450 return 1;
4451 case 3:
2390218b 4452 err = kvm_set_cr3(vcpu, val);
db8fcefa 4453 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4454 return 1;
4455 case 4:
eeadf9e7 4456 err = handle_set_cr4(vcpu, val);
db8fcefa 4457 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4458 return 1;
0a5fff19
GN		 4459 case 8: {
4460 u8 cr8_prev = kvm_get_cr8(vcpu);
4461 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4462 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4463 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4464 if (irqchip_in_kernel(vcpu->kvm))
4465 return 1;
4466 if (cr8_prev <= cr8)
4467 return 1;
851ba692 4468 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4469 return 0;
4470 }
6aa8b732
AK		 4471 };
4472 break;
25c4c276 4473 case 2: /* clts */
eeadf9e7 4474 handle_clts(vcpu);
4d4ec087 4475 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4476 skip_emulated_instruction(vcpu);
6b52d186 4477 vmx_fpu_activate(vcpu);
25c4c276 4478 return 1;
6aa8b732
AK		 4479 case 1: /*mov from cr*/
4480 switch (cr) {
4481 case 3:
9f8fe504
AK		 4482 val = kvm_read_cr3(vcpu);
4483 kvm_register_write(vcpu, reg, val);
4484 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4485 skip_emulated_instruction(vcpu);
4486 return 1;
4487 case 8:
229456fc
MT		 4488 val = kvm_get_cr8(vcpu);
4489 kvm_register_write(vcpu, reg, val);
4490 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4491 skip_emulated_instruction(vcpu);
4492 return 1;
4493 }
4494 break;
4495 case 3: /* lmsw */
a1f83a74 4496 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4497 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4498 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4499
4500 skip_emulated_instruction(vcpu);
4501 return 1;
4502 default:
4503 break;
4504 }
851ba692 4505 vcpu->run->exit_reason = 0;
f0242478 4506 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4507 (int)(exit_qualification >> 4) & 3, cr);
4508 return 0;
4509}
4510
851ba692 4511static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4512{
bfdaab09 4513 unsigned long exit_qualification;
6aa8b732
AK		 4514 int dr, reg;
4515
f2483415 4516 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4517 if (!kvm_require_cpl(vcpu, 0))
4518 return 1;
42dbaa5a
JK		 4519 dr = vmcs_readl(GUEST_DR7);
4520 if (dr & DR7_GD) {
4521 /*
4522 * As the vm-exit takes precedence over the debug trap, we
4523 * need to emulate the latter, either for the host or the
4524 * guest debugging itself.
4525 */
4526 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4527 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4528 vcpu->run->debug.arch.dr7 = dr;
4529 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4530 vmcs_readl(GUEST_CS_BASE) +
4531 vmcs_readl(GUEST_RIP);
851ba692
AK		 4532 vcpu->run->debug.arch.exception = DB_VECTOR;
4533 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4534 return 0;
4535 } else {
4536 vcpu->arch.dr7 &= ~DR7_GD;
4537 vcpu->arch.dr6 |= DR6_BD;
4538 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4539 kvm_queue_exception(vcpu, DB_VECTOR);
4540 return 1;
4541 }
4542 }
4543
bfdaab09 4544 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4545 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4546 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4547 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4548 unsigned long val;
4549 if (!kvm_get_dr(vcpu, dr, &val))
4550 kvm_register_write(vcpu, reg, val);
4551 } else
4552 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4553 skip_emulated_instruction(vcpu);
4554 return 1;
4555}
4556
020df079
GN		 4557static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4558{
4559 vmcs_writel(GUEST_DR7, val);
4560}
4561
851ba692 4562static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4563{
06465c5a
AK		 4564 kvm_emulate_cpuid(vcpu);
4565 return 1;
6aa8b732
AK		 4566}
4567
851ba692 4568static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4569{
ad312c7c 4570 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4571 u64 data;
4572
4573 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4574 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4575 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4576 return 1;
4577 }
4578
229456fc 4579 trace_kvm_msr_read(ecx, data);
2714d1d3 4580
6aa8b732 4581 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4582 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4583 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4584 skip_emulated_instruction(vcpu);
4585 return 1;
4586}
4587
851ba692 4588static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4589{
ad312c7c
ZX		 4590 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4591 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4592 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4593
4594 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4595 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4596 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4597 return 1;
4598 }
4599
59200273 4600 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4601 skip_emulated_instruction(vcpu);
4602 return 1;
4603}
4604
851ba692 4605static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4606{
3842d135 4607 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4608 return 1;
4609}
4610
851ba692 4611static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4612{
85f455f7
ED		 4613 u32 cpu_based_vm_exec_control;
4614
4615 /* clear pending irq */
4616 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4617 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4618 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4619
3842d135
AK		 4620 kvm_make_request(KVM_REQ_EVENT, vcpu);
4621
a26bf12a 4622 ++vcpu->stat.irq_window_exits;
2714d1d3 4623
c1150d8c
DL		 4624 /*
4625 * If the user space waits to inject interrupts, exit as soon as
4626 * possible
4627 */
8061823a 4628 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4629 vcpu->run->request_interrupt_window &&
8061823a 4630 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4631 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4632 return 0;
4633 }
6aa8b732
AK		 4634 return 1;
4635}
4636
851ba692 4637static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4638{
4639 skip_emulated_instruction(vcpu);
d3bef15f 4640 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4641}
4642
851ba692 4643static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4644{
510043da 4645 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4646 kvm_emulate_hypercall(vcpu);
4647 return 1;
c21415e8
IM		 4648}
4649
ec25d5e6
GN		 4650static int handle_invd(struct kvm_vcpu *vcpu)
4651{
51d8b661 4652 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4653}
4654
851ba692 4655static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4656{
f9c617f6 4657 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4658
4659 kvm_mmu_invlpg(vcpu, exit_qualification);
4660 skip_emulated_instruction(vcpu);
4661 return 1;
4662}
4663
fee84b07
AK		 4664static int handle_rdpmc(struct kvm_vcpu *vcpu)
4665{
4666 int err;
4667
4668 err = kvm_rdpmc(vcpu);
4669 kvm_complete_insn_gp(vcpu, err);
4670
4671 return 1;
4672}
4673
851ba692 4674static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4675{
4676 skip_emulated_instruction(vcpu);
f5f48ee1 4677 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4678 return 1;
4679}
4680
2acf923e
DC		 4681static int handle_xsetbv(struct kvm_vcpu *vcpu)
4682{
4683 u64 new_bv = kvm_read_edx_eax(vcpu);
4684 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4685
4686 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4687 skip_emulated_instruction(vcpu);
4688 return 1;
4689}
4690
851ba692 4691static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4692{
58fbbf26
KT		 4693 if (likely(fasteoi)) {
4694 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4695 int access_type, offset;
4696
4697 access_type = exit_qualification & APIC_ACCESS_TYPE;
4698 offset = exit_qualification & APIC_ACCESS_OFFSET;
4699 /*
4700 * Sane guest uses MOV to write EOI, with written value
4701 * not cared. So make a short-circuit here by avoiding
4702 * heavy instruction emulation.
4703 */
4704 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4705 (offset == APIC_EOI)) {
4706 kvm_lapic_set_eoi(vcpu);
4707 skip_emulated_instruction(vcpu);
4708 return 1;
4709 }
4710 }
51d8b661 4711 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4712}
4713
851ba692 4714static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4715{
60637aac 4716 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4717 unsigned long exit_qualification;
e269fb21
JK		 4718 bool has_error_code = false;
4719 u32 error_code = 0;
37817f29 4720 u16 tss_selector;
7f3d35fd 4721 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4722
4723 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4724 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4725 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4726
4727 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4728
4729 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4730 if (reason == TASK_SWITCH_GATE && idt_v) {
4731 switch (type) {
4732 case INTR_TYPE_NMI_INTR:
4733 vcpu->arch.nmi_injected = false;
654f06fc 4734 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4735 break;
4736 case INTR_TYPE_EXT_INTR:
66fd3f7f 4737 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4738 kvm_clear_interrupt_queue(vcpu);
4739 break;
4740 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4741 if (vmx->idt_vectoring_info &
4742 VECTORING_INFO_DELIVER_CODE_MASK) {
4743 has_error_code = true;
4744 error_code =
4745 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4746 }
4747 /* fall through */
64a7ec06
GN		 4748 case INTR_TYPE_SOFT_EXCEPTION:
4749 kvm_clear_exception_queue(vcpu);
4750 break;
4751 default:
4752 break;
4753 }
60637aac 4754 }
37817f29
IE		 4755 tss_selector = exit_qualification;
4756
64a7ec06
GN		 4757 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4758 type != INTR_TYPE_EXT_INTR &&
4759 type != INTR_TYPE_NMI_INTR))
4760 skip_emulated_instruction(vcpu);
4761
7f3d35fd
KW		 4762 if (kvm_task_switch(vcpu, tss_selector,
4763 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4764 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4765 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4766 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4767 vcpu->run->internal.ndata = 0;
42dbaa5a 4768 return 0;
acb54517 4769 }
42dbaa5a
JK		 4770
4771 /* clear all local breakpoint enable flags */
4772 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4773
4774 /*
4775 * TODO: What about debug traps on tss switch?
4776 * Are we supposed to inject them and update dr6?
4777 */
4778
4779 return 1;
37817f29
IE		 4780}
4781
851ba692 4782static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4783{
f9c617f6 4784 unsigned long exit_qualification;
1439442c 4785 gpa_t gpa;
1439442c 4786 int gla_validity;
1439442c 4787
f9c617f6 4788 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4789
4790 if (exit_qualification & (1 << 6)) {
4791 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4792 return -EINVAL;
1439442c
SY		 4793 }
4794
4795 gla_validity = (exit_qualification >> 7) & 0x3;
4796 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4797 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4798 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4799 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4800 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4801 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4802 (long unsigned int)exit_qualification);
851ba692
AK		 4803 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4804 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4805 return 0;
1439442c
SY		 4806 }
4807
4808 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4809 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4810 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4811}
4812
68f89400
MT		 4813static u64 ept_rsvd_mask(u64 spte, int level)
4814{
4815 int i;
4816 u64 mask = 0;
4817
4818 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4819 mask |= (1ULL << i);
4820
4821 if (level > 2)
4822 /* bits 7:3 reserved */
4823 mask |= 0xf8;
4824 else if (level == 2) {
4825 if (spte & (1ULL << 7))
4826 /* 2MB ref, bits 20:12 reserved */
4827 mask |= 0x1ff000;
4828 else
4829 /* bits 6:3 reserved */
4830 mask |= 0x78;
4831 }
4832
4833 return mask;
4834}
4835
4836static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4837 int level)
4838{
4839 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4840
4841 /* 010b (write-only) */
4842 WARN_ON((spte & 0x7) == 0x2);
4843
4844 /* 110b (write/execute) */
4845 WARN_ON((spte & 0x7) == 0x6);
4846
4847 /* 100b (execute-only) and value not supported by logical processor */
4848 if (!cpu_has_vmx_ept_execute_only())
4849 WARN_ON((spte & 0x7) == 0x4);
4850
4851 /* not 000b */
4852 if ((spte & 0x7)) {
4853 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4854
4855 if (rsvd_bits != 0) {
4856 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4857 __func__, rsvd_bits);
4858 WARN_ON(1);
4859 }
4860
4861 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4862 u64 ept_mem_type = (spte & 0x38) >> 3;
4863
4864 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4865 ept_mem_type == 7) {
4866 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4867 __func__, ept_mem_type);
4868 WARN_ON(1);
4869 }
4870 }
4871 }
4872}
4873
851ba692 4874static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4875{
4876 u64 sptes[4];
ce88decf 4877 int nr_sptes, i, ret;
68f89400
MT		 4878 gpa_t gpa;
4879
4880 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4881
ce88decf
XG		 4882 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4883 if (likely(ret == 1))
4884 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4885 EMULATE_DONE;
4886 if (unlikely(!ret))
4887 return 1;
4888
4889 /* It is the real ept misconfig */
68f89400
MT		 4890 printk(KERN_ERR "EPT: Misconfiguration.\n");
4891 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4892
4893 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4894
4895 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4896 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4897
851ba692
AK		 4898 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4899 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4900
4901 return 0;
4902}
4903
851ba692 4904static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4905{
4906 u32 cpu_based_vm_exec_control;
4907
4908 /* clear pending NMI */
4909 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4910 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4911 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4912 ++vcpu->stat.nmi_window_exits;
3842d135 4913 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4914
4915 return 1;
4916}
4917
80ced186 4918static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4919{
8b3079a5
AK		 4920 struct vcpu_vmx *vmx = to_vmx(vcpu);
4921 enum emulation_result err = EMULATE_DONE;
80ced186 4922 int ret = 1;
49e9d557
AK		 4923 u32 cpu_exec_ctrl;
4924 bool intr_window_requested;
4925
4926 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4927 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4928
4929 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4930 if (intr_window_requested
4931 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4932 return handle_interrupt_window(&vmx->vcpu);
4933
51d8b661 4934 err = emulate_instruction(vcpu, 0);
ea953ef0 4935
80ced186
MG		 4936 if (err == EMULATE_DO_MMIO) {
4937 ret = 0;
4938 goto out;
4939 }
1d5a4d9b 4940
6d77dbfc
GN		 4941 if (err != EMULATE_DONE)
4942 return 0;
ea953ef0
MG		 4943
4944 if (signal_pending(current))
80ced186 4945 goto out;
ea953ef0
MG		 4946 if (need_resched())
4947 schedule();
4948 }
4949
80ced186
MG		 4950 vmx->emulation_required = 0;
4951out:
4952 return ret;
ea953ef0
MG		 4953}
4954
4b8d54f9
ZE		 4955/*
4956 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4957 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4958 */
9fb41ba8 4959static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4960{
4961 skip_emulated_instruction(vcpu);
4962 kvm_vcpu_on_spin(vcpu);
4963
4964 return 1;
4965}
4966
59708670
SY		 4967static int handle_invalid_op(struct kvm_vcpu *vcpu)
4968{
4969 kvm_queue_exception(vcpu, UD_VECTOR);
4970 return 1;
4971}
4972
ff2f6fe9
NHE		 4973/*
4974 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4975 * We could reuse a single VMCS for all the L2 guests, but we also want the
4976 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4977 * allows keeping them loaded on the processor, and in the future will allow
4978 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4979 * every entry if they never change.
4980 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4981 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4982 *
4983 * The following functions allocate and free a vmcs02 in this pool.
4984 */
4985
4986/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4987static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4988{
4989 struct vmcs02_list *item;
4990 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4991 if (item->vmptr == vmx->nested.current_vmptr) {
4992 list_move(&item->list, &vmx->nested.vmcs02_pool);
4993 return &item->vmcs02;
4994 }
4995
4996 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4997 /* Recycle the least recently used VMCS. */
4998 item = list_entry(vmx->nested.vmcs02_pool.prev,
4999 struct vmcs02_list, list);
5000 item->vmptr = vmx->nested.current_vmptr;
5001 list_move(&item->list, &vmx->nested.vmcs02_pool);
5002 return &item->vmcs02;
5003 }
5004
5005 /* Create a new VMCS */
5006 item = (struct vmcs02_list *)
5007 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5008 if (!item)
5009 return NULL;
5010 item->vmcs02.vmcs = alloc_vmcs();
5011 if (!item->vmcs02.vmcs) {
5012 kfree(item);
5013 return NULL;
5014 }
5015 loaded_vmcs_init(&item->vmcs02);
5016 item->vmptr = vmx->nested.current_vmptr;
5017 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5018 vmx->nested.vmcs02_num++;
5019 return &item->vmcs02;
5020}
5021
5022/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5023static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5024{
5025 struct vmcs02_list *item;
5026 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5027 if (item->vmptr == vmptr) {
5028 free_loaded_vmcs(&item->vmcs02);
5029 list_del(&item->list);
5030 kfree(item);
5031 vmx->nested.vmcs02_num--;
5032 return;
5033 }
5034}
5035
5036/*
5037 * Free all VMCSs saved for this vcpu, except the one pointed by
5038 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5039 * currently used, if running L2), and vmcs01 when running L2.
5040 */
5041static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5042{
5043 struct vmcs02_list *item, *n;
5044 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5045 if (vmx->loaded_vmcs != &item->vmcs02)
5046 free_loaded_vmcs(&item->vmcs02);
5047 list_del(&item->list);
5048 kfree(item);
5049 }
5050 vmx->nested.vmcs02_num = 0;
5051
5052 if (vmx->loaded_vmcs != &vmx->vmcs01)
5053 free_loaded_vmcs(&vmx->vmcs01);
5054}
5055
ec378aee
NHE		 5056/*
5057 * Emulate the VMXON instruction.
5058 * Currently, we just remember that VMX is active, and do not save or even
5059 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5060 * do not currently need to store anything in that guest-allocated memory
5061 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5062 * argument is different from the VMXON pointer (which the spec says they do).
5063 */
5064static int handle_vmon(struct kvm_vcpu *vcpu)
5065{
5066 struct kvm_segment cs;
5067 struct vcpu_vmx *vmx = to_vmx(vcpu);
5068
5069 /* The Intel VMX Instruction Reference lists a bunch of bits that
5070 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5071 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5072 * Otherwise, we should fail with #UD. We test these now:
5073 */
5074 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5075 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5076 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5077 kvm_queue_exception(vcpu, UD_VECTOR);
5078 return 1;
5079 }
5080
5081 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5082 if (is_long_mode(vcpu) && !cs.l) {
5083 kvm_queue_exception(vcpu, UD_VECTOR);
5084 return 1;
5085 }
5086
5087 if (vmx_get_cpl(vcpu)) {
5088 kvm_inject_gp(vcpu, 0);
5089 return 1;
5090 }
5091
ff2f6fe9
NHE		 5092 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5093 vmx->nested.vmcs02_num = 0;
5094
ec378aee
NHE		 5095 vmx->nested.vmxon = true;
5096
5097 skip_emulated_instruction(vcpu);
5098 return 1;
5099}
5100
5101/*
5102 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5103 * for running VMX instructions (except VMXON, whose prerequisites are
5104 * slightly different). It also specifies what exception to inject otherwise.
5105 */
5106static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5107{
5108 struct kvm_segment cs;
5109 struct vcpu_vmx *vmx = to_vmx(vcpu);
5110
5111 if (!vmx->nested.vmxon) {
5112 kvm_queue_exception(vcpu, UD_VECTOR);
5113 return 0;
5114 }
5115
5116 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5117 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5118 (is_long_mode(vcpu) && !cs.l)) {
5119 kvm_queue_exception(vcpu, UD_VECTOR);
5120 return 0;
5121 }
5122
5123 if (vmx_get_cpl(vcpu)) {
5124 kvm_inject_gp(vcpu, 0);
5125 return 0;
5126 }
5127
5128 return 1;
5129}
5130
5131/*
5132 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5133 * just stops using VMX.
5134 */
5135static void free_nested(struct vcpu_vmx *vmx)
5136{
5137 if (!vmx->nested.vmxon)
5138 return;
5139 vmx->nested.vmxon = false;
a9d30f33
NHE		 5140 if (vmx->nested.current_vmptr != -1ull) {
5141 kunmap(vmx->nested.current_vmcs12_page);
5142 nested_release_page(vmx->nested.current_vmcs12_page);
5143 vmx->nested.current_vmptr = -1ull;
5144 vmx->nested.current_vmcs12 = NULL;
5145 }
fe3ef05c
NHE		 5146 /* Unpin physical memory we referred to in current vmcs02 */
5147 if (vmx->nested.apic_access_page) {
5148 nested_release_page(vmx->nested.apic_access_page);
5149 vmx->nested.apic_access_page = 0;
5150 }
ff2f6fe9
NHE		 5151
5152 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5153}
5154
5155/* Emulate the VMXOFF instruction */
5156static int handle_vmoff(struct kvm_vcpu *vcpu)
5157{
5158 if (!nested_vmx_check_permission(vcpu))
5159 return 1;
5160 free_nested(to_vmx(vcpu));
5161 skip_emulated_instruction(vcpu);
5162 return 1;
5163}
5164
064aea77
NHE		 5165/*
5166 * Decode the memory-address operand of a vmx instruction, as recorded on an
5167 * exit caused by such an instruction (run by a guest hypervisor).
5168 * On success, returns 0. When the operand is invalid, returns 1 and throws
5169 * #UD or #GP.
5170 */
5171static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5172 unsigned long exit_qualification,
5173 u32 vmx_instruction_info, gva_t *ret)
5174{
5175 /*
5176 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5177 * Execution", on an exit, vmx_instruction_info holds most of the
5178 * addressing components of the operand. Only the displacement part
5179 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5180 * For how an actual address is calculated from all these components,
5181 * refer to Vol. 1, "Operand Addressing".
5182 */
5183 int scaling = vmx_instruction_info & 3;
5184 int addr_size = (vmx_instruction_info >> 7) & 7;
5185 bool is_reg = vmx_instruction_info & (1u << 10);
5186 int seg_reg = (vmx_instruction_info >> 15) & 7;
5187 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5188 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5189 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5190 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5191
5192 if (is_reg) {
5193 kvm_queue_exception(vcpu, UD_VECTOR);
5194 return 1;
5195 }
5196
5197 /* Addr = segment_base + offset */
5198 /* offset = base + [index * scale] + displacement */
5199 *ret = vmx_get_segment_base(vcpu, seg_reg);
5200 if (base_is_valid)
5201 *ret += kvm_register_read(vcpu, base_reg);
5202 if (index_is_valid)
5203 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5204 *ret += exit_qualification; /* holds the displacement */
5205
5206 if (addr_size == 1) /* 32 bit */
5207 *ret &= 0xffffffff;
5208
5209 /*
5210 * TODO: throw #GP (and return 1) in various cases that the VM*
5211 * instructions require it - e.g., offset beyond segment limit,
5212 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5213 * address, and so on. Currently these are not checked.
5214 */
5215 return 0;
5216}
5217
0140caea
NHE		 5218/*
5219 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5220 * set the success or error code of an emulated VMX instruction, as specified
5221 * by Vol 2B, VMX Instruction Reference, "Conventions".
5222 */
5223static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5224{
5225 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5226 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5227 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5228}
5229
5230static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5231{
5232 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5233 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5234 X86_EFLAGS_SF | X86_EFLAGS_OF))
5235 | X86_EFLAGS_CF);
5236}
5237
5238static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5239 u32 vm_instruction_error)
5240{
5241 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5242 /*
5243 * failValid writes the error number to the current VMCS, which
5244 * can't be done there isn't a current VMCS.
5245 */
5246 nested_vmx_failInvalid(vcpu);
5247 return;
5248 }
5249 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5250 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5251 X86_EFLAGS_SF | X86_EFLAGS_OF))
5252 | X86_EFLAGS_ZF);
5253 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5254}
5255
27d6c865
NHE		 5256/* Emulate the VMCLEAR instruction */
5257static int handle_vmclear(struct kvm_vcpu *vcpu)
5258{
5259 struct vcpu_vmx *vmx = to_vmx(vcpu);
5260 gva_t gva;
5261 gpa_t vmptr;
5262 struct vmcs12 *vmcs12;
5263 struct page *page;
5264 struct x86_exception e;
5265
5266 if (!nested_vmx_check_permission(vcpu))
5267 return 1;
5268
5269 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5270 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5271 return 1;
5272
5273 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5274 sizeof(vmptr), &e)) {
5275 kvm_inject_page_fault(vcpu, &e);
5276 return 1;
5277 }
5278
5279 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5280 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5281 skip_emulated_instruction(vcpu);
5282 return 1;
5283 }
5284
5285 if (vmptr == vmx->nested.current_vmptr) {
5286 kunmap(vmx->nested.current_vmcs12_page);
5287 nested_release_page(vmx->nested.current_vmcs12_page);
5288 vmx->nested.current_vmptr = -1ull;
5289 vmx->nested.current_vmcs12 = NULL;
5290 }
5291
5292 page = nested_get_page(vcpu, vmptr);
5293 if (page == NULL) {
5294 /*
5295 * For accurate processor emulation, VMCLEAR beyond available
5296 * physical memory should do nothing at all. However, it is
5297 * possible that a nested vmx bug, not a guest hypervisor bug,
5298 * resulted in this case, so let's shut down before doing any
5299 * more damage:
5300 */
5301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5302 return 1;
5303 }
5304 vmcs12 = kmap(page);
5305 vmcs12->launch_state = 0;
5306 kunmap(page);
5307 nested_release_page(page);
5308
5309 nested_free_vmcs02(vmx, vmptr);
5310
5311 skip_emulated_instruction(vcpu);
5312 nested_vmx_succeed(vcpu);
5313 return 1;
5314}
5315
cd232ad0
NHE		 5316static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5317
5318/* Emulate the VMLAUNCH instruction */
5319static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5320{
5321 return nested_vmx_run(vcpu, true);
5322}
5323
5324/* Emulate the VMRESUME instruction */
5325static int handle_vmresume(struct kvm_vcpu *vcpu)
5326{
5327
5328 return nested_vmx_run(vcpu, false);
5329}
5330
49f705c5
NHE		 5331enum vmcs_field_type {
5332 VMCS_FIELD_TYPE_U16 = 0,
5333 VMCS_FIELD_TYPE_U64 = 1,
5334 VMCS_FIELD_TYPE_U32 = 2,
5335 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5336};
5337
5338static inline int vmcs_field_type(unsigned long field)
5339{
5340 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5341 return VMCS_FIELD_TYPE_U32;
5342 return (field >> 13) & 0x3 ;
5343}
5344
5345static inline int vmcs_field_readonly(unsigned long field)
5346{
5347 return (((field >> 10) & 0x3) == 1);
5348}
5349
5350/*
5351 * Read a vmcs12 field. Since these can have varying lengths and we return
5352 * one type, we chose the biggest type (u64) and zero-extend the return value
5353 * to that size. Note that the caller, handle_vmread, might need to use only
5354 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5355 * 64-bit fields are to be returned).
5356 */
5357static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5358 unsigned long field, u64 *ret)
5359{
5360 short offset = vmcs_field_to_offset(field);
5361 char *p;
5362
5363 if (offset < 0)
5364 return 0;
5365
5366 p = ((char *)(get_vmcs12(vcpu))) + offset;
5367
5368 switch (vmcs_field_type(field)) {
5369 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5370 *ret = *((natural_width *)p);
5371 return 1;
5372 case VMCS_FIELD_TYPE_U16:
5373 *ret = *((u16 *)p);
5374 return 1;
5375 case VMCS_FIELD_TYPE_U32:
5376 *ret = *((u32 *)p);
5377 return 1;
5378 case VMCS_FIELD_TYPE_U64:
5379 *ret = *((u64 *)p);
5380 return 1;
5381 default:
5382 return 0; /* can never happen. */
5383 }
5384}
5385
5386/*
5387 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5388 * used before) all generate the same failure when it is missing.
5389 */
5390static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5391{
5392 struct vcpu_vmx *vmx = to_vmx(vcpu);
5393 if (vmx->nested.current_vmptr == -1ull) {
5394 nested_vmx_failInvalid(vcpu);
5395 skip_emulated_instruction(vcpu);
5396 return 0;
5397 }
5398 return 1;
5399}
5400
5401static int handle_vmread(struct kvm_vcpu *vcpu)
5402{
5403 unsigned long field;
5404 u64 field_value;
5405 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5406 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5407 gva_t gva = 0;
5408
5409 if (!nested_vmx_check_permission(vcpu) ||
5410 !nested_vmx_check_vmcs12(vcpu))
5411 return 1;
5412
5413 /* Decode instruction info and find the field to read */
5414 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5415 /* Read the field, zero-extended to a u64 field_value */
5416 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5417 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5418 skip_emulated_instruction(vcpu);
5419 return 1;
5420 }
5421 /*
5422 * Now copy part of this value to register or memory, as requested.
5423 * Note that the number of bits actually copied is 32 or 64 depending
5424 * on the guest's mode (32 or 64 bit), not on the given field's length.
5425 */
5426 if (vmx_instruction_info & (1u << 10)) {
5427 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5428 field_value);
5429 } else {
5430 if (get_vmx_mem_address(vcpu, exit_qualification,
5431 vmx_instruction_info, &gva))
5432 return 1;
5433 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5434 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5435 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5436 }
5437
5438 nested_vmx_succeed(vcpu);
5439 skip_emulated_instruction(vcpu);
5440 return 1;
5441}
5442
5443
5444static int handle_vmwrite(struct kvm_vcpu *vcpu)
5445{
5446 unsigned long field;
5447 gva_t gva;
5448 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5449 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5450 char *p;
5451 short offset;
5452 /* The value to write might be 32 or 64 bits, depending on L1's long
5453 * mode, and eventually we need to write that into a field of several
5454 * possible lengths. The code below first zero-extends the value to 64
5455 * bit (field_value), and then copies only the approriate number of
5456 * bits into the vmcs12 field.
5457 */
5458 u64 field_value = 0;
5459 struct x86_exception e;
5460
5461 if (!nested_vmx_check_permission(vcpu) ||
5462 !nested_vmx_check_vmcs12(vcpu))
5463 return 1;
5464
5465 if (vmx_instruction_info & (1u << 10))
5466 field_value = kvm_register_read(vcpu,
5467 (((vmx_instruction_info) >> 3) & 0xf));
5468 else {
5469 if (get_vmx_mem_address(vcpu, exit_qualification,
5470 vmx_instruction_info, &gva))
5471 return 1;
5472 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5473 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5474 kvm_inject_page_fault(vcpu, &e);
5475 return 1;
5476 }
5477 }
5478
5479
5480 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5481 if (vmcs_field_readonly(field)) {
5482 nested_vmx_failValid(vcpu,
5483 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5484 skip_emulated_instruction(vcpu);
5485 return 1;
5486 }
5487
5488 offset = vmcs_field_to_offset(field);
5489 if (offset < 0) {
5490 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5491 skip_emulated_instruction(vcpu);
5492 return 1;
5493 }
5494 p = ((char *) get_vmcs12(vcpu)) + offset;
5495
5496 switch (vmcs_field_type(field)) {
5497 case VMCS_FIELD_TYPE_U16:
5498 *(u16 *)p = field_value;
5499 break;
5500 case VMCS_FIELD_TYPE_U32:
5501 *(u32 *)p = field_value;
5502 break;
5503 case VMCS_FIELD_TYPE_U64:
5504 *(u64 *)p = field_value;
5505 break;
5506 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5507 *(natural_width *)p = field_value;
5508 break;
5509 default:
5510 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5511 skip_emulated_instruction(vcpu);
5512 return 1;
5513 }
5514
5515 nested_vmx_succeed(vcpu);
5516 skip_emulated_instruction(vcpu);
5517 return 1;
5518}
5519
63846663
NHE		 5520/* Emulate the VMPTRLD instruction */
5521static int handle_vmptrld(struct kvm_vcpu *vcpu)
5522{
5523 struct vcpu_vmx *vmx = to_vmx(vcpu);
5524 gva_t gva;
5525 gpa_t vmptr;
5526 struct x86_exception e;
5527
5528 if (!nested_vmx_check_permission(vcpu))
5529 return 1;
5530
5531 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5532 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5533 return 1;
5534
5535 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5536 sizeof(vmptr), &e)) {
5537 kvm_inject_page_fault(vcpu, &e);
5538 return 1;
5539 }
5540
5541 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5542 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5543 skip_emulated_instruction(vcpu);
5544 return 1;
5545 }
5546
5547 if (vmx->nested.current_vmptr != vmptr) {
5548 struct vmcs12 *new_vmcs12;
5549 struct page *page;
5550 page = nested_get_page(vcpu, vmptr);
5551 if (page == NULL) {
5552 nested_vmx_failInvalid(vcpu);
5553 skip_emulated_instruction(vcpu);
5554 return 1;
5555 }
5556 new_vmcs12 = kmap(page);
5557 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5558 kunmap(page);
5559 nested_release_page_clean(page);
5560 nested_vmx_failValid(vcpu,
5561 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5562 skip_emulated_instruction(vcpu);
5563 return 1;
5564 }
5565 if (vmx->nested.current_vmptr != -1ull) {
5566 kunmap(vmx->nested.current_vmcs12_page);
5567 nested_release_page(vmx->nested.current_vmcs12_page);
5568 }
5569
5570 vmx->nested.current_vmptr = vmptr;
5571 vmx->nested.current_vmcs12 = new_vmcs12;
5572 vmx->nested.current_vmcs12_page = page;
5573 }
5574
5575 nested_vmx_succeed(vcpu);
5576 skip_emulated_instruction(vcpu);
5577 return 1;
5578}
5579
6a4d7550
NHE		 5580/* Emulate the VMPTRST instruction */
5581static int handle_vmptrst(struct kvm_vcpu *vcpu)
5582{
5583 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5584 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5585 gva_t vmcs_gva;
5586 struct x86_exception e;
5587
5588 if (!nested_vmx_check_permission(vcpu))
5589 return 1;
5590
5591 if (get_vmx_mem_address(vcpu, exit_qualification,
5592 vmx_instruction_info, &vmcs_gva))
5593 return 1;
5594 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5595 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5596 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5597 sizeof(u64), &e)) {
5598 kvm_inject_page_fault(vcpu, &e);
5599 return 1;
5600 }
5601 nested_vmx_succeed(vcpu);
5602 skip_emulated_instruction(vcpu);
5603 return 1;
5604}
5605
6aa8b732
AK		 5606/*
5607 * The exit handlers return 1 if the exit was handled fully and guest execution
5608 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5609 * to be done to userspace and return 0.
5610 */
851ba692 5611static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5612 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5613 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5614 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5615 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5616 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5617 [EXIT_REASON_CR_ACCESS] = handle_cr,
5618 [EXIT_REASON_DR_ACCESS] = handle_dr,
5619 [EXIT_REASON_CPUID] = handle_cpuid,
5620 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5621 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5622 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5623 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5624 [EXIT_REASON_INVD] = handle_invd,
a7052897 5625 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5626 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5627 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5628 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5629 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5630 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5631 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5632 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5633 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5634 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5635 [EXIT_REASON_VMOFF] = handle_vmoff,
5636 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5637 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5638 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5639 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5640 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5641 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5642 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5643 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5644 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5645 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5646 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5647 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5648};
5649
5650static const int kvm_vmx_max_exit_handlers =
50a3485c 5651 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5652
644d711a
NHE		 5653/*
5654 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5655 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5656 * disinterest in the current event (read or write a specific MSR) by using an
5657 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5658 */
5659static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5660 struct vmcs12 *vmcs12, u32 exit_reason)
5661{
5662 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5663 gpa_t bitmap;
5664
5665 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5666 return 1;
5667
5668 /*
5669 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5670 * for the four combinations of read/write and low/high MSR numbers.
5671 * First we need to figure out which of the four to use:
5672 */
5673 bitmap = vmcs12->msr_bitmap;
5674 if (exit_reason == EXIT_REASON_MSR_WRITE)
5675 bitmap += 2048;
5676 if (msr_index >= 0xc0000000) {
5677 msr_index -= 0xc0000000;
5678 bitmap += 1024;
5679 }
5680
5681 /* Then read the msr_index'th bit from this bitmap: */
5682 if (msr_index < 1024*8) {
5683 unsigned char b;
5684 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5685 return 1 & (b >> (msr_index & 7));
5686 } else
5687 return 1; /* let L1 handle the wrong parameter */
5688}
5689
5690/*
5691 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5692 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5693 * intercept (via guest_host_mask etc.) the current event.
5694 */
5695static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5696 struct vmcs12 *vmcs12)
5697{
5698 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5699 int cr = exit_qualification & 15;
5700 int reg = (exit_qualification >> 8) & 15;
5701 unsigned long val = kvm_register_read(vcpu, reg);
5702
5703 switch ((exit_qualification >> 4) & 3) {
5704 case 0: /* mov to cr */
5705 switch (cr) {
5706 case 0:
5707 if (vmcs12->cr0_guest_host_mask &
5708 (val ^ vmcs12->cr0_read_shadow))
5709 return 1;
5710 break;
5711 case 3:
5712 if ((vmcs12->cr3_target_count >= 1 &&
5713 vmcs12->cr3_target_value0 == val) ||
5714 (vmcs12->cr3_target_count >= 2 &&
5715 vmcs12->cr3_target_value1 == val) ||
5716 (vmcs12->cr3_target_count >= 3 &&
5717 vmcs12->cr3_target_value2 == val) ||
5718 (vmcs12->cr3_target_count >= 4 &&
5719 vmcs12->cr3_target_value3 == val))
5720 return 0;
5721 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5722 return 1;
5723 break;
5724 case 4:
5725 if (vmcs12->cr4_guest_host_mask &
5726 (vmcs12->cr4_read_shadow ^ val))
5727 return 1;
5728 break;
5729 case 8:
5730 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5731 return 1;
5732 break;
5733 }
5734 break;
5735 case 2: /* clts */
5736 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5737 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5738 return 1;
5739 break;
5740 case 1: /* mov from cr */
5741 switch (cr) {
5742 case 3:
5743 if (vmcs12->cpu_based_vm_exec_control &
5744 CPU_BASED_CR3_STORE_EXITING)
5745 return 1;
5746 break;
5747 case 8:
5748 if (vmcs12->cpu_based_vm_exec_control &
5749 CPU_BASED_CR8_STORE_EXITING)
5750 return 1;
5751 break;
5752 }
5753 break;
5754 case 3: /* lmsw */
5755 /*
5756 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5757 * cr0. Other attempted changes are ignored, with no exit.
5758 */
5759 if (vmcs12->cr0_guest_host_mask & 0xe &
5760 (val ^ vmcs12->cr0_read_shadow))
5761 return 1;
5762 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5763 !(vmcs12->cr0_read_shadow & 0x1) &&
5764 (val & 0x1))
5765 return 1;
5766 break;
5767 }
5768 return 0;
5769}
5770
5771/*
5772 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5773 * should handle it ourselves in L0 (and then continue L2). Only call this
5774 * when in is_guest_mode (L2).
5775 */
5776static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5777{
5778 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5779 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5780 struct vcpu_vmx *vmx = to_vmx(vcpu);
5781 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5782
5783 if (vmx->nested.nested_run_pending)
5784 return 0;
5785
5786 if (unlikely(vmx->fail)) {
bd80158a
JK		 5787 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5788 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5789 return 1;
5790 }
5791
5792 switch (exit_reason) {
5793 case EXIT_REASON_EXCEPTION_NMI:
5794 if (!is_exception(intr_info))
5795 return 0;
5796 else if (is_page_fault(intr_info))
5797 return enable_ept;
5798 return vmcs12->exception_bitmap &
5799 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5800 case EXIT_REASON_EXTERNAL_INTERRUPT:
5801 return 0;
5802 case EXIT_REASON_TRIPLE_FAULT:
5803 return 1;
5804 case EXIT_REASON_PENDING_INTERRUPT:
5805 case EXIT_REASON_NMI_WINDOW:
5806 /*
5807 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5808 * (aka Interrupt Window Exiting) only when L1 turned it on,
5809 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5810 * Same for NMI Window Exiting.
5811 */
5812 return 1;
5813 case EXIT_REASON_TASK_SWITCH:
5814 return 1;
5815 case EXIT_REASON_CPUID:
5816 return 1;
5817 case EXIT_REASON_HLT:
5818 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5819 case EXIT_REASON_INVD:
5820 return 1;
5821 case EXIT_REASON_INVLPG:
5822 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5823 case EXIT_REASON_RDPMC:
5824 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5825 case EXIT_REASON_RDTSC:
5826 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5827 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5828 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5829 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5830 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5831 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5832 /*
5833 * VMX instructions trap unconditionally. This allows L1 to
5834 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5835 */
5836 return 1;
5837 case EXIT_REASON_CR_ACCESS:
5838 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5839 case EXIT_REASON_DR_ACCESS:
5840 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5841 case EXIT_REASON_IO_INSTRUCTION:
5842 /* TODO: support IO bitmaps */
5843 return 1;
5844 case EXIT_REASON_MSR_READ:
5845 case EXIT_REASON_MSR_WRITE:
5846 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5847 case EXIT_REASON_INVALID_STATE:
5848 return 1;
5849 case EXIT_REASON_MWAIT_INSTRUCTION:
5850 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5851 case EXIT_REASON_MONITOR_INSTRUCTION:
5852 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5853 case EXIT_REASON_PAUSE_INSTRUCTION:
5854 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5855 nested_cpu_has2(vmcs12,
5856 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5857 case EXIT_REASON_MCE_DURING_VMENTRY:
5858 return 0;
5859 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5860 return 1;
5861 case EXIT_REASON_APIC_ACCESS:
5862 return nested_cpu_has2(vmcs12,
5863 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5864 case EXIT_REASON_EPT_VIOLATION:
5865 case EXIT_REASON_EPT_MISCONFIG:
5866 return 0;
5867 case EXIT_REASON_WBINVD:
5868 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5869 case EXIT_REASON_XSETBV:
5870 return 1;
5871 default:
5872 return 1;
5873 }
5874}
5875
586f9607
AK		 5876static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5877{
5878 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5879 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5880}
5881
6aa8b732
AK		 5882/*
5883 * The guest has exited. See if we can fix it or if we need userspace
5884 * assistance.
5885 */
851ba692 5886static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5887{
29bd8a78 5888 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5889 u32 exit_reason = vmx->exit_reason;
1155f76a 5890 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5891
80ced186
MG		 5892 /* If guest state is invalid, start emulating */
5893 if (vmx->emulation_required && emulate_invalid_guest_state)
5894 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5895
b6f1250e
NHE		 5896 /*
5897 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5898 * we did not inject a still-pending event to L1 now because of
5899 * nested_run_pending, we need to re-enable this bit.
5900 */
5901 if (vmx->nested.nested_run_pending)
5902 kvm_make_request(KVM_REQ_EVENT, vcpu);
5903
509c75ea
NHE		 5904 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5905 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5906 vmx->nested.nested_run_pending = 1;
5907 else
5908 vmx->nested.nested_run_pending = 0;
5909
5910 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5911 nested_vmx_vmexit(vcpu);
5912 return 1;
5913 }
5914
5120702e
MG		 5915 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5916 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5917 vcpu->run->fail_entry.hardware_entry_failure_reason
5918 = exit_reason;
5919 return 0;
5920 }
5921
29bd8a78 5922 if (unlikely(vmx->fail)) {
851ba692
AK		 5923 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5924 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5925 = vmcs_read32(VM_INSTRUCTION_ERROR);
5926 return 0;
5927 }
6aa8b732 5928
d77c26fc 5929 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5930 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5931 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5932 exit_reason != EXIT_REASON_TASK_SWITCH))
5933 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5934 "(0x%x) and exit reason is 0x%x\n",
5935 __func__, vectoring_info, exit_reason);
3b86cd99 5936
644d711a
NHE		 5937 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5938 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5939 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5940 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5941 vmx->soft_vnmi_blocked = 0;
3b86cd99 5942 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5943 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5944 /*
5945 * This CPU don't support us in finding the end of an
5946 * NMI-blocked window if the guest runs with IRQs
5947 * disabled. So we pull the trigger after 1 s of
5948 * futile waiting, but inform the user about this.
5949 */
5950 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5951 "state on VCPU %d after 1 s timeout\n",
5952 __func__, vcpu->vcpu_id);
5953 vmx->soft_vnmi_blocked = 0;
3b86cd99 5954 }
3b86cd99
JK		 5955 }
5956
6aa8b732
AK		 5957 if (exit_reason < kvm_vmx_max_exit_handlers
5958 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5959 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5960 else {
851ba692
AK		 5961 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5962 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5963 }
5964 return 0;
5965}
5966
95ba8273 5967static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5968{
95ba8273 5969 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5970 vmcs_write32(TPR_THRESHOLD, 0);
5971 return;
5972 }
5973
95ba8273 5974 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5975}
5976
51aa01d1 5977static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5978{
00eba012
AK		 5979 u32 exit_intr_info;
5980
5981 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5982 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5983 return;
5984
c5ca8e57 5985 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5986 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5987
5988 /* Handle machine checks before interrupts are enabled */
00eba012 5989 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5990 kvm_machine_check();
5991
20f65983 5992 /* We need to handle NMIs before interrupts are enabled */
00eba012 5993 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5994 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5995 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5996 asm("int $2");
ff9d07a0
ZY		 5997 kvm_after_handle_nmi(&vmx->vcpu);
5998 }
51aa01d1 5999}
20f65983 6000
51aa01d1
AK		 6001static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6002{
c5ca8e57 6003 u32 exit_intr_info;
51aa01d1
AK		 6004 bool unblock_nmi;
6005 u8 vector;
6006 bool idtv_info_valid;
6007
6008 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6009
cf393f75 6010 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6011 if (vmx->nmi_known_unmasked)
6012 return;
c5ca8e57
AK		 6013 /*
6014 * Can't use vmx->exit_intr_info since we're not sure what
6015 * the exit reason is.
6016 */
6017 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6018 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6019 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6020 /*
7b4a25cb 6021 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6022 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6023 * a guest IRET fault.
7b4a25cb
GN		 6024 * SDM 3: 23.2.2 (September 2008)
6025 * Bit 12 is undefined in any of the following cases:
6026 * If the VM exit sets the valid bit in the IDT-vectoring
6027 * information field.
6028 * If the VM exit is due to a double fault.
cf393f75 6029 */
7b4a25cb
GN		 6030 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6031 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6032 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6033 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6034 else
6035 vmx->nmi_known_unmasked =
6036 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6037 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6038 } else if (unlikely(vmx->soft_vnmi_blocked))
6039 vmx->vnmi_blocked_time +=
6040 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6041}
6042
83422e17
AK		 6043static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6044 u32 idt_vectoring_info,
6045 int instr_len_field,
6046 int error_code_field)
51aa01d1 6047{
51aa01d1
AK		 6048 u8 vector;
6049 int type;
6050 bool idtv_info_valid;
6051
6052 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6053
37b96e98
GN		 6054 vmx->vcpu.arch.nmi_injected = false;
6055 kvm_clear_exception_queue(&vmx->vcpu);
6056 kvm_clear_interrupt_queue(&vmx->vcpu);
6057
6058 if (!idtv_info_valid)
6059 return;
6060
3842d135
AK		 6061 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6062
668f612f
AK		 6063 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6064 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6065
64a7ec06 6066 switch (type) {
37b96e98
GN		 6067 case INTR_TYPE_NMI_INTR:
6068 vmx->vcpu.arch.nmi_injected = true;
668f612f 6069 /*
7b4a25cb 6070 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6071 * Clear bit "block by NMI" before VM entry if a NMI
6072 * delivery faulted.
668f612f 6073 */
654f06fc 6074 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6075 break;
37b96e98 6076 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6077 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6078 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6079 /* fall through */
6080 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6081 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6082 u32 err = vmcs_read32(error_code_field);
37b96e98 6083 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6084 } else
6085 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6086 break;
66fd3f7f
GN		 6087 case INTR_TYPE_SOFT_INTR:
6088 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6089 vmcs_read32(instr_len_field);
66fd3f7f 6090 /* fall through */
37b96e98 6091 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6092 kvm_queue_interrupt(&vmx->vcpu, vector,
6093 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6094 break;
6095 default:
6096 break;
f7d9238f 6097 }
cf393f75
AK		 6098}
6099
83422e17
AK		 6100static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6101{
66c78ae4
NHE		 6102 if (is_guest_mode(&vmx->vcpu))
6103 return;
83422e17
AK		 6104 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6105 VM_EXIT_INSTRUCTION_LEN,
6106 IDT_VECTORING_ERROR_CODE);
6107}
6108
b463a6f7
AK		 6109static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6110{
66c78ae4
NHE		 6111 if (is_guest_mode(vcpu))
6112 return;
b463a6f7
AK		 6113 __vmx_complete_interrupts(to_vmx(vcpu),
6114 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6115 VM_ENTRY_INSTRUCTION_LEN,
6116 VM_ENTRY_EXCEPTION_ERROR_CODE);
6117
6118 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6119}
6120
d7cd9796
GN		 6121static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6122{
6123 int i, nr_msrs;
6124 struct perf_guest_switch_msr *msrs;
6125
6126 msrs = perf_guest_get_msrs(&nr_msrs);
6127
6128 if (!msrs)
6129 return;
6130
6131 for (i = 0; i < nr_msrs; i++)
6132 if (msrs[i].host == msrs[i].guest)
6133 clear_atomic_switch_msr(vmx, msrs[i].msr);
6134 else
6135 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6136 msrs[i].host);
6137}
6138
c801949d
AK		 6139#ifdef CONFIG_X86_64
6140#define R "r"
6141#define Q "q"
6142#else
6143#define R "e"
6144#define Q "l"
6145#endif
6146
a3b5ba49 6147static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6148{
a2fa3e9f 6149 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6150
66c78ae4
NHE		 6151 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6152 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6153 if (vmcs12->idt_vectoring_info_field &
6154 VECTORING_INFO_VALID_MASK) {
6155 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6156 vmcs12->idt_vectoring_info_field);
6157 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6158 vmcs12->vm_exit_instruction_len);
6159 if (vmcs12->idt_vectoring_info_field &
6160 VECTORING_INFO_DELIVER_CODE_MASK)
6161 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6162 vmcs12->idt_vectoring_error_code);
6163 }
6164 }
6165
104f226b
AK		 6166 /* Record the guest's net vcpu time for enforced NMI injections. */
6167 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6168 vmx->entry_time = ktime_get();
6169
6170 /* Don't enter VMX if guest state is invalid, let the exit handler
6171 start emulation until we arrive back to a valid state */
6172 if (vmx->emulation_required && emulate_invalid_guest_state)
6173 return;
6174
6175 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6176 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6177 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6178 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6179
6180 /* When single-stepping over STI and MOV SS, we must clear the
6181 * corresponding interruptibility bits in the guest state. Otherwise
6182 * vmentry fails as it then expects bit 14 (BS) in pending debug
6183 * exceptions being set, but that's not correct for the guest debugging
6184 * case. */
6185 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6186 vmx_set_interrupt_shadow(vcpu, 0);
6187
d7cd9796
GN		 6188 atomic_switch_perf_msrs(vmx);
6189
d462b819 6190 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6191 asm(
6aa8b732 6192 /* Store host registers */
c801949d 6193 "push %%"R"dx; push %%"R"bp;"
40712fae 6194 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6195 "push %%"R"cx \n\t"
313dbd49
AK		 6196 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6197 "je 1f \n\t"
6198 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6199 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6200 "1: \n\t"
d3edefc0
AK		 6201 /* Reload cr2 if changed */
6202 "mov %c[cr2](%0), %%"R"ax \n\t"
6203 "mov %%cr2, %%"R"dx \n\t"
6204 "cmp %%"R"ax, %%"R"dx \n\t"
6205 "je 2f \n\t"
6206 "mov %%"R"ax, %%cr2 \n\t"
6207 "2: \n\t"
6aa8b732 6208 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6209 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6210 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6211 "mov %c[rax](%0), %%"R"ax \n\t"
6212 "mov %c[rbx](%0), %%"R"bx \n\t"
6213 "mov %c[rdx](%0), %%"R"dx \n\t"
6214 "mov %c[rsi](%0), %%"R"si \n\t"
6215 "mov %c[rdi](%0), %%"R"di \n\t"
6216 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6217#ifdef CONFIG_X86_64
e08aa78a
AK		 6218 "mov %c[r8](%0), %%r8 \n\t"
6219 "mov %c[r9](%0), %%r9 \n\t"
6220 "mov %c[r10](%0), %%r10 \n\t"
6221 "mov %c[r11](%0), %%r11 \n\t"
6222 "mov %c[r12](%0), %%r12 \n\t"
6223 "mov %c[r13](%0), %%r13 \n\t"
6224 "mov %c[r14](%0), %%r14 \n\t"
6225 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6226#endif
c801949d
AK		 6227 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6228
6aa8b732 6229 /* Enter guest mode */
cd2276a7 6230 "jne .Llaunched \n\t"
4ecac3fd 6231 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6232 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6233 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6234 ".Lkvm_vmx_return: "
6aa8b732 6235 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6236 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6237 "pop %0 \n\t"
c801949d
AK		 6238 "mov %%"R"ax, %c[rax](%0) \n\t"
6239 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6240 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6241 "mov %%"R"dx, %c[rdx](%0) \n\t"
6242 "mov %%"R"si, %c[rsi](%0) \n\t"
6243 "mov %%"R"di, %c[rdi](%0) \n\t"
6244 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6245#ifdef CONFIG_X86_64
e08aa78a
AK		 6246 "mov %%r8, %c[r8](%0) \n\t"
6247 "mov %%r9, %c[r9](%0) \n\t"
6248 "mov %%r10, %c[r10](%0) \n\t"
6249 "mov %%r11, %c[r11](%0) \n\t"
6250 "mov %%r12, %c[r12](%0) \n\t"
6251 "mov %%r13, %c[r13](%0) \n\t"
6252 "mov %%r14, %c[r14](%0) \n\t"
6253 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6254#endif
c801949d
AK		 6255 "mov %%cr2, %%"R"ax \n\t"
6256 "mov %%"R"ax, %c[cr2](%0) \n\t"
6257
1c696d0e 6258 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6259 "setbe %c[fail](%0) \n\t"
6260 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6261 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6262 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6263 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6264 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6265 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6266 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6267 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6268 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6269 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6270 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6271#ifdef CONFIG_X86_64
ad312c7c
ZX		 6272 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6273 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6274 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6275 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6276 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6277 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6278 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6279 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6280#endif
40712fae
AK		 6281 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6282 [wordsize]"i"(sizeof(ulong))
c2036300 6283 : "cc", "memory"
07d6f555 6284 , R"ax", R"bx", R"di", R"si"
c2036300 6285#ifdef CONFIG_X86_64
c2036300
LV		 6286 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6287#endif
6288 );
6aa8b732 6289
6de4f3ad 6290 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6291 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6292 | (1 << VCPU_EXREG_CPL)
aff48baa 6293 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6294 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6295 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6296 vcpu->arch.regs_dirty = 0;
6297
1155f76a
AK		 6298 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6299
66c78ae4
NHE		 6300 if (is_guest_mode(vcpu)) {
6301 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6302 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6303 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6304 vmcs12->idt_vectoring_error_code =
6305 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6306 vmcs12->vm_exit_instruction_len =
6307 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6308 }
6309 }
6310
d462b819 6311 vmx->loaded_vmcs->launched = 1;
1b6269db 6312
51aa01d1 6313 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6314 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6315
6316 vmx_complete_atomic_exit(vmx);
6317 vmx_recover_nmi_blocking(vmx);
cf393f75 6318 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6319}
6320
c801949d
AK		 6321#undef R
6322#undef Q
6323
6aa8b732
AK		 6324static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6325{
fb3f0f51
RR		 6326 struct vcpu_vmx *vmx = to_vmx(vcpu);
6327
cdbecfc3 6328 free_vpid(vmx);
ec378aee 6329 free_nested(vmx);
d462b819 6330 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6331 kfree(vmx->guest_msrs);
6332 kvm_vcpu_uninit(vcpu);
a4770347 6333 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6334}
6335
fb3f0f51 6336static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6337{
fb3f0f51 6338 int err;
c16f862d 6339 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6340 int cpu;
6aa8b732 6341
a2fa3e9f 6342 if (!vmx)
fb3f0f51
RR		 6343 return ERR_PTR(-ENOMEM);
6344
2384d2b3
SY		 6345 allocate_vpid(vmx);
6346
fb3f0f51
RR		 6347 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6348 if (err)
6349 goto free_vcpu;
965b58a5 6350
a2fa3e9f 6351 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6352 err = -ENOMEM;
fb3f0f51 6353 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6354 goto uninit_vcpu;
6355 }
965b58a5 6356
d462b819
NHE		 6357 vmx->loaded_vmcs = &vmx->vmcs01;
6358 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6359 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6360 goto free_msrs;
d462b819
NHE		 6361 if (!vmm_exclusive)
6362 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6363 loaded_vmcs_init(vmx->loaded_vmcs);
6364 if (!vmm_exclusive)
6365 kvm_cpu_vmxoff();
a2fa3e9f 6366
15ad7146
AK		 6367 cpu = get_cpu();
6368 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6369 vmx->vcpu.cpu = cpu;
8b9cf98c 6370 err = vmx_vcpu_setup(vmx);
fb3f0f51 6371 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6372 put_cpu();
fb3f0f51
RR		 6373 if (err)
6374 goto free_vmcs;
5e4a0b3c 6375 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6376 err = alloc_apic_access_page(kvm);
6377 if (err)
5e4a0b3c 6378 goto free_vmcs;
fb3f0f51 6379
b927a3ce
SY		 6380 if (enable_ept) {
6381 if (!kvm->arch.ept_identity_map_addr)
6382 kvm->arch.ept_identity_map_addr =
6383 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6384 err = -ENOMEM;
b7ebfb05
SY		 6385 if (alloc_identity_pagetable(kvm) != 0)
6386 goto free_vmcs;
93ea5388
GN		 6387 if (!init_rmode_identity_map(kvm))
6388 goto free_vmcs;
b927a3ce 6389 }
b7ebfb05 6390
a9d30f33
NHE		 6391 vmx->nested.current_vmptr = -1ull;
6392 vmx->nested.current_vmcs12 = NULL;
6393
fb3f0f51
RR		 6394 return &vmx->vcpu;
6395
6396free_vmcs:
5f3fbc34 6397 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6398free_msrs:
fb3f0f51
RR		 6399 kfree(vmx->guest_msrs);
6400uninit_vcpu:
6401 kvm_vcpu_uninit(&vmx->vcpu);
6402free_vcpu:
cdbecfc3 6403 free_vpid(vmx);
a4770347 6404 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6405 return ERR_PTR(err);
6aa8b732
AK		 6406}
6407
002c7f7c
YS		 6408static void __init vmx_check_processor_compat(void *rtn)
6409{
6410 struct vmcs_config vmcs_conf;
6411
6412 *(int *)rtn = 0;
6413 if (setup_vmcs_config(&vmcs_conf) < 0)
6414 *(int *)rtn = -EIO;
6415 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6416 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6417 smp_processor_id());
6418 *(int *)rtn = -EIO;
6419 }
6420}
6421
67253af5
SY		 6422static int get_ept_level(void)
6423{
6424 return VMX_EPT_DEFAULT_GAW + 1;
6425}
6426
4b12f0de 6427static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6428{
4b12f0de
SY		 6429 u64 ret;
6430
522c68c4
SY		 6431 /* For VT-d and EPT combination
6432 * 1. MMIO: always map as UC
6433 * 2. EPT with VT-d:
6434 * a. VT-d without snooping control feature: can't guarantee the
6435 * result, try to trust guest.
6436 * b. VT-d with snooping control feature: snooping control feature of
6437 * VT-d engine can guarantee the cache correctness. Just set it
6438 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6439 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6440 * consistent with host MTRR
6441 */
4b12f0de
SY		 6442 if (is_mmio)
6443 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6444 else if (vcpu->kvm->arch.iommu_domain &&
6445 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6446 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6447 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6448 else
522c68c4 6449 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6450 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6451
6452 return ret;
64d4d521
SY		 6453}
6454
17cc3935 6455static int vmx_get_lpage_level(void)
344f414f 6456{
878403b7
SY		 6457 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6458 return PT_DIRECTORY_LEVEL;
6459 else
6460 /* For shadow and EPT supported 1GB page */
6461 return PT_PDPE_LEVEL;
344f414f
JR		 6462}
6463
0e851880
SY		 6464static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6465{
4e47c7a6
SY		 6466 struct kvm_cpuid_entry2 *best;
6467 struct vcpu_vmx *vmx = to_vmx(vcpu);
6468 u32 exec_control;
6469
6470 vmx->rdtscp_enabled = false;
6471 if (vmx_rdtscp_supported()) {
6472 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6473 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6474 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6475 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6476 vmx->rdtscp_enabled = true;
6477 else {
6478 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6479 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6480 exec_control);
6481 }
6482 }
6483 }
0e851880
SY		 6484}
6485
d4330ef2
JR		 6486static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6487{
7b8050f5
NHE		 6488 if (func == 1 && nested)
6489 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6490}
6491
fe3ef05c
NHE		 6492/*
6493 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6494 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6495 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6496 * guest in a way that will both be appropriate to L1's requests, and our
6497 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6498 * function also has additional necessary side-effects, like setting various
6499 * vcpu->arch fields.
6500 */
6501static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6502{
6503 struct vcpu_vmx *vmx = to_vmx(vcpu);
6504 u32 exec_control;
6505
6506 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6507 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6508 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6509 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6510 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6511 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6512 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6513 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6514 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6515 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6516 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6517 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6518 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6519 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6520 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6521 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6522 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6523 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6524 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6525 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6526 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6527 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6528 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6529 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6530 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6531 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6532 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6533 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6534 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6535 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6536 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6537 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6538 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6539 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6540 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6541 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6542
6543 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6544 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6545 vmcs12->vm_entry_intr_info_field);
6546 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6547 vmcs12->vm_entry_exception_error_code);
6548 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6549 vmcs12->vm_entry_instruction_len);
6550 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6551 vmcs12->guest_interruptibility_info);
6552 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6553 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6554 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6555 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6556 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6557 vmcs12->guest_pending_dbg_exceptions);
6558 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6559 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6560
6561 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6562
6563 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6564 (vmcs_config.pin_based_exec_ctrl |
6565 vmcs12->pin_based_vm_exec_control));
6566
6567 /*
6568 * Whether page-faults are trapped is determined by a combination of
6569 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6570 * If enable_ept, L0 doesn't care about page faults and we should
6571 * set all of these to L1's desires. However, if !enable_ept, L0 does
6572 * care about (at least some) page faults, and because it is not easy
6573 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6574 * to exit on each and every L2 page fault. This is done by setting
6575 * MASK=MATCH=0 and (see below) EB.PF=1.
6576 * Note that below we don't need special code to set EB.PF beyond the
6577 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6578 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6579 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6580 *
6581 * A problem with this approach (when !enable_ept) is that L1 may be
6582 * injected with more page faults than it asked for. This could have
6583 * caused problems, but in practice existing hypervisors don't care.
6584 * To fix this, we will need to emulate the PFEC checking (on the L1
6585 * page tables), using walk_addr(), when injecting PFs to L1.
6586 */
6587 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6588 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6589 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6590 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6591
6592 if (cpu_has_secondary_exec_ctrls()) {
6593 u32 exec_control = vmx_secondary_exec_control(vmx);
6594 if (!vmx->rdtscp_enabled)
6595 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6596 /* Take the following fields only from vmcs12 */
6597 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6598 if (nested_cpu_has(vmcs12,
6599 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6600 exec_control |= vmcs12->secondary_vm_exec_control;
6601
6602 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6603 /*
6604 * Translate L1 physical address to host physical
6605 * address for vmcs02. Keep the page pinned, so this
6606 * physical address remains valid. We keep a reference
6607 * to it so we can release it later.
6608 */
6609 if (vmx->nested.apic_access_page) /* shouldn't happen */
6610 nested_release_page(vmx->nested.apic_access_page);
6611 vmx->nested.apic_access_page =
6612 nested_get_page(vcpu, vmcs12->apic_access_addr);
6613 /*
6614 * If translation failed, no matter: This feature asks
6615 * to exit when accessing the given address, and if it
6616 * can never be accessed, this feature won't do
6617 * anything anyway.
6618 */
6619 if (!vmx->nested.apic_access_page)
6620 exec_control &=
6621 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6622 else
6623 vmcs_write64(APIC_ACCESS_ADDR,
6624 page_to_phys(vmx->nested.apic_access_page));
6625 }
6626
6627 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6628 }
6629
6630
6631 /*
6632 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6633 * Some constant fields are set here by vmx_set_constant_host_state().
6634 * Other fields are different per CPU, and will be set later when
6635 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6636 */
6637 vmx_set_constant_host_state();
6638
6639 /*
6640 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6641 * entry, but only if the current (host) sp changed from the value
6642 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6643 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6644 * here we just force the write to happen on entry.
6645 */
6646 vmx->host_rsp = 0;
6647
6648 exec_control = vmx_exec_control(vmx); /* L0's desires */
6649 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6650 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6651 exec_control &= ~CPU_BASED_TPR_SHADOW;
6652 exec_control |= vmcs12->cpu_based_vm_exec_control;
6653 /*
6654 * Merging of IO and MSR bitmaps not currently supported.
6655 * Rather, exit every time.
6656 */
6657 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6658 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6659 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6660
6661 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6662
6663 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6664 * bitwise-or of what L1 wants to trap for L2, and what we want to
6665 * trap. Note that CR0.TS also needs updating - we do this later.
6666 */
6667 update_exception_bitmap(vcpu);
6668 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6669 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6670
6671 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6672 vmcs_write32(VM_EXIT_CONTROLS,
6673 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6674 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6675 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6676
6677 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6678 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6679 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6680 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6681
6682
6683 set_cr4_guest_host_mask(vmx);
6684
27fc51b2
NHE		 6685 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6686 vmcs_write64(TSC_OFFSET,
6687 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6688 else
6689 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6690
6691 if (enable_vpid) {
6692 /*
6693 * Trivially support vpid by letting L2s share their parent
6694 * L1's vpid. TODO: move to a more elaborate solution, giving
6695 * each L2 its own vpid and exposing the vpid feature to L1.
6696 */
6697 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6698 vmx_flush_tlb(vcpu);
6699 }
6700
6701 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6702 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6703 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6704 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6705 else
6706 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6707 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6708 vmx_set_efer(vcpu, vcpu->arch.efer);
6709
6710 /*
6711 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6712 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6713 * The CR0_READ_SHADOW is what L2 should have expected to read given
6714 * the specifications by L1; It's not enough to take
6715 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6716 * have more bits than L1 expected.
6717 */
6718 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6719 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6720
6721 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6722 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6723
6724 /* shadow page tables on either EPT or shadow page tables */
6725 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6726 kvm_mmu_reset_context(vcpu);
6727
6728 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6729 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6730}
6731
cd232ad0
NHE		 6732/*
6733 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6734 * for running an L2 nested guest.
6735 */
6736static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6737{
6738 struct vmcs12 *vmcs12;
6739 struct vcpu_vmx *vmx = to_vmx(vcpu);
6740 int cpu;
6741 struct loaded_vmcs *vmcs02;
6742
6743 if (!nested_vmx_check_permission(vcpu) ||
6744 !nested_vmx_check_vmcs12(vcpu))
6745 return 1;
6746
6747 skip_emulated_instruction(vcpu);
6748 vmcs12 = get_vmcs12(vcpu);
6749
7c177938
NHE		 6750 /*
6751 * The nested entry process starts with enforcing various prerequisites
6752 * on vmcs12 as required by the Intel SDM, and act appropriately when
6753 * they fail: As the SDM explains, some conditions should cause the
6754 * instruction to fail, while others will cause the instruction to seem
6755 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6756 * To speed up the normal (success) code path, we should avoid checking
6757 * for misconfigurations which will anyway be caught by the processor
6758 * when using the merged vmcs02.
6759 */
6760 if (vmcs12->launch_state == launch) {
6761 nested_vmx_failValid(vcpu,
6762 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6763 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6764 return 1;
6765 }
6766
6767 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6768 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6769 /*TODO: Also verify bits beyond physical address width are 0*/
6770 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6771 return 1;
6772 }
6773
6774 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6775 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6776 /*TODO: Also verify bits beyond physical address width are 0*/
6777 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6778 return 1;
6779 }
6780
6781 if (vmcs12->vm_entry_msr_load_count > 0 ||
6782 vmcs12->vm_exit_msr_load_count > 0 ||
6783 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6784 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6785 __func__);
7c177938
NHE		 6786 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6787 return 1;
6788 }
6789
6790 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6791 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6792 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6793 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6794 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6795 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6796 !vmx_control_verify(vmcs12->vm_exit_controls,
6797 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6798 !vmx_control_verify(vmcs12->vm_entry_controls,
6799 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6800 {
6801 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6802 return 1;
6803 }
6804
6805 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6806 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6807 nested_vmx_failValid(vcpu,
6808 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6809 return 1;
6810 }
6811
6812 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6813 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6814 nested_vmx_entry_failure(vcpu, vmcs12,
6815 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6816 return 1;
6817 }
6818 if (vmcs12->vmcs_link_pointer != -1ull) {
6819 nested_vmx_entry_failure(vcpu, vmcs12,
6820 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6821 return 1;
6822 }
6823
6824 /*
6825 * We're finally done with prerequisite checking, and can start with
6826 * the nested entry.
6827 */
6828
cd232ad0
NHE		 6829 vmcs02 = nested_get_current_vmcs02(vmx);
6830 if (!vmcs02)
6831 return -ENOMEM;
6832
6833 enter_guest_mode(vcpu);
6834
6835 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6836
6837 cpu = get_cpu();
6838 vmx->loaded_vmcs = vmcs02;
6839 vmx_vcpu_put(vcpu);
6840 vmx_vcpu_load(vcpu, cpu);
6841 vcpu->cpu = cpu;
6842 put_cpu();
6843
6844 vmcs12->launch_state = 1;
6845
6846 prepare_vmcs02(vcpu, vmcs12);
6847
6848 /*
6849 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6850 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6851 * returned as far as L1 is concerned. It will only return (and set
6852 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6853 */
6854 return 1;
6855}
6856
4704d0be
NHE		 6857/*
6858 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6859 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6860 * This function returns the new value we should put in vmcs12.guest_cr0.
6861 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6862 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6863 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6864 * didn't trap the bit, because if L1 did, so would L0).
6865 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6866 * been modified by L2, and L1 knows it. So just leave the old value of
6867 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6868 * isn't relevant, because if L0 traps this bit it can set it to anything.
6869 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6870 * changed these bits, and therefore they need to be updated, but L0
6871 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6872 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6873 */
6874static inline unsigned long
6875vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6876{
6877 return
6878 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6879 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6880 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6881 vcpu->arch.cr0_guest_owned_bits));
6882}
6883
6884static inline unsigned long
6885vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6886{
6887 return
6888 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6889 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6890 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6891 vcpu->arch.cr4_guest_owned_bits));
6892}
6893
6894/*
6895 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6896 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6897 * and this function updates it to reflect the changes to the guest state while
6898 * L2 was running (and perhaps made some exits which were handled directly by L0
6899 * without going back to L1), and to reflect the exit reason.
6900 * Note that we do not have to copy here all VMCS fields, just those that
6901 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6902 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6903 * which already writes to vmcs12 directly.
6904 */
6905void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6906{
6907 /* update guest state fields: */
6908 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6909 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6910
6911 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6912 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6913 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6914 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6915
6916 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6917 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6918 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6919 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6920 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6921 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6922 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6923 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6924 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6925 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6926 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6927 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6928 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6929 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6930 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6931 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6932 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6933 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6934 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6935 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6936 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6937 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6938 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6939 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6940 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6941 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6942 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6943 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6944 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6945 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6946 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6947 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6948 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6949 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6950 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6951 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6952
6953 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6954 vmcs12->guest_interruptibility_info =
6955 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6956 vmcs12->guest_pending_dbg_exceptions =
6957 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6958
6959 /* TODO: These cannot have changed unless we have MSR bitmaps and
6960 * the relevant bit asks not to trap the change */
6961 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6962 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6963 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6964 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6965 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6966 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6967
6968 /* update exit information fields: */
6969
6970 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6971 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6972
6973 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6974 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6975 vmcs12->idt_vectoring_info_field =
6976 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6977 vmcs12->idt_vectoring_error_code =
6978 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6979 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6980 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6981
6982 /* clear vm-entry fields which are to be cleared on exit */
6983 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6984 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6985}
6986
6987/*
6988 * A part of what we need to when the nested L2 guest exits and we want to
6989 * run its L1 parent, is to reset L1's guest state to the host state specified
6990 * in vmcs12.
6991 * This function is to be called not only on normal nested exit, but also on
6992 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6993 * Failures During or After Loading Guest State").
6994 * This function should be called when the active VMCS is L1's (vmcs01).
6995 */
6996void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6997{
6998 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6999 vcpu->arch.efer = vmcs12->host_ia32_efer;
7000 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7001 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7002 else
7003 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7004 vmx_set_efer(vcpu, vcpu->arch.efer);
7005
7006 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7007 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7008 /*
7009 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7010 * actually changed, because it depends on the current state of
7011 * fpu_active (which may have changed).
7012 * Note that vmx_set_cr0 refers to efer set above.
7013 */
7014 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7015 /*
7016 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7017 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7018 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7019 */
7020 update_exception_bitmap(vcpu);
7021 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7022 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7023
7024 /*
7025 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7026 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7027 */
7028 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7029 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7030
7031 /* shadow page tables on either EPT or shadow page tables */
7032 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7033 kvm_mmu_reset_context(vcpu);
7034
7035 if (enable_vpid) {
7036 /*
7037 * Trivially support vpid by letting L2s share their parent
7038 * L1's vpid. TODO: move to a more elaborate solution, giving
7039 * each L2 its own vpid and exposing the vpid feature to L1.
7040 */
7041 vmx_flush_tlb(vcpu);
7042 }
7043
7044
7045 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7046 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7047 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7048 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7049 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7050 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7051 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7052 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7053 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7054 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7055 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7056 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7057 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7058 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7059 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7060
7061 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7062 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7063 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7064 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7065 vmcs12->host_ia32_perf_global_ctrl);
7066}
7067
7068/*
7069 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7070 * and modify vmcs12 to make it see what it would expect to see there if
7071 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7072 */
7073static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7074{
7075 struct vcpu_vmx *vmx = to_vmx(vcpu);
7076 int cpu;
7077 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7078
7079 leave_guest_mode(vcpu);
7080 prepare_vmcs12(vcpu, vmcs12);
7081
7082 cpu = get_cpu();
7083 vmx->loaded_vmcs = &vmx->vmcs01;
7084 vmx_vcpu_put(vcpu);
7085 vmx_vcpu_load(vcpu, cpu);
7086 vcpu->cpu = cpu;
7087 put_cpu();
7088
7089 /* if no vmcs02 cache requested, remove the one we used */
7090 if (VMCS02_POOL_SIZE == 0)
7091 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7092
7093 load_vmcs12_host_state(vcpu, vmcs12);
7094
27fc51b2 7095 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7096 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7097
7098 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7099 vmx->host_rsp = 0;
7100
7101 /* Unpin physical memory we referred to in vmcs02 */
7102 if (vmx->nested.apic_access_page) {
7103 nested_release_page(vmx->nested.apic_access_page);
7104 vmx->nested.apic_access_page = 0;
7105 }
7106
7107 /*
7108 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7109 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7110 * success or failure flag accordingly.
7111 */
7112 if (unlikely(vmx->fail)) {
7113 vmx->fail = 0;
7114 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7115 } else
7116 nested_vmx_succeed(vcpu);
7117}
7118
7c177938
NHE		 7119/*
7120 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7121 * 23.7 "VM-entry failures during or after loading guest state" (this also
7122 * lists the acceptable exit-reason and exit-qualification parameters).
7123 * It should only be called before L2 actually succeeded to run, and when
7124 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7125 */
7126static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7127 struct vmcs12 *vmcs12,
7128 u32 reason, unsigned long qualification)
7129{
7130 load_vmcs12_host_state(vcpu, vmcs12);
7131 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7132 vmcs12->exit_qualification = qualification;
7133 nested_vmx_succeed(vcpu);
7134}
7135
8a76d7f2
JR		 7136static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7137 struct x86_instruction_info *info,
7138 enum x86_intercept_stage stage)
7139{
7140 return X86EMUL_CONTINUE;
7141}
7142
cbdd1bea 7143static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7144 .cpu_has_kvm_support = cpu_has_kvm_support,
7145 .disabled_by_bios = vmx_disabled_by_bios,
7146 .hardware_setup = hardware_setup,
7147 .hardware_unsetup = hardware_unsetup,
002c7f7c 7148 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7149 .hardware_enable = hardware_enable,
7150 .hardware_disable = hardware_disable,
04547156 7151 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7152
7153 .vcpu_create = vmx_create_vcpu,
7154 .vcpu_free = vmx_free_vcpu,
04d2cc77 7155 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7156
04d2cc77 7157 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7158 .vcpu_load = vmx_vcpu_load,
7159 .vcpu_put = vmx_vcpu_put,
7160
7161 .set_guest_debug = set_guest_debug,
7162 .get_msr = vmx_get_msr,
7163 .set_msr = vmx_set_msr,
7164 .get_segment_base = vmx_get_segment_base,
7165 .get_segment = vmx_get_segment,
7166 .set_segment = vmx_set_segment,
2e4d2653 7167 .get_cpl = vmx_get_cpl,
6aa8b732 7168 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7169 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7170 .decache_cr3 = vmx_decache_cr3,
25c4c276 7171 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7172 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7173 .set_cr3 = vmx_set_cr3,
7174 .set_cr4 = vmx_set_cr4,
6aa8b732 7175 .set_efer = vmx_set_efer,
6aa8b732
AK		 7176 .get_idt = vmx_get_idt,
7177 .set_idt = vmx_set_idt,
7178 .get_gdt = vmx_get_gdt,
7179 .set_gdt = vmx_set_gdt,
020df079 7180 .set_dr7 = vmx_set_dr7,
5fdbf976 7181 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7182 .get_rflags = vmx_get_rflags,
7183 .set_rflags = vmx_set_rflags,
ebcbab4c 7184 .fpu_activate = vmx_fpu_activate,
02daab21 7185 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7186
7187 .tlb_flush = vmx_flush_tlb,
6aa8b732 7188
6aa8b732 7189 .run = vmx_vcpu_run,
6062d012 7190 .handle_exit = vmx_handle_exit,
6aa8b732 7191 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7192 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7193 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7194 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7195 .set_irq = vmx_inject_irq,
95ba8273 7196 .set_nmi = vmx_inject_nmi,
298101da 7197 .queue_exception = vmx_queue_exception,
b463a6f7 7198 .cancel_injection = vmx_cancel_injection,
78646121 7199 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7200 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7201 .get_nmi_mask = vmx_get_nmi_mask,
7202 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7203 .enable_nmi_window = enable_nmi_window,
7204 .enable_irq_window = enable_irq_window,
7205 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7206
cbc94022 7207 .set_tss_addr = vmx_set_tss_addr,
67253af5 7208 .get_tdp_level = get_ept_level,
4b12f0de 7209 .get_mt_mask = vmx_get_mt_mask,
229456fc 7210
586f9607 7211 .get_exit_info = vmx_get_exit_info,
586f9607 7212
17cc3935 7213 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7214
7215 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7216
7217 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7218
7219 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7220
7221 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7222
4051b188 7223 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7224 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7225 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7226 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7227 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7228
7229 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7230
7231 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7232};
7233
7234static int __init vmx_init(void)
7235{
26bb0981
AK		 7236 int r, i;
7237
7238 rdmsrl_safe(MSR_EFER, &host_efer);
7239
7240 for (i = 0; i < NR_VMX_MSR; ++i)
7241 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7242
3e7c73e9 7243 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7244 if (!vmx_io_bitmap_a)
7245 return -ENOMEM;
7246
3e7c73e9 7247 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7248 if (!vmx_io_bitmap_b) {
7249 r = -ENOMEM;
7250 goto out;
7251 }
7252
5897297b
AK		 7253 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7254 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7255 r = -ENOMEM;
7256 goto out1;
7257 }
7258
5897297b
AK		 7259 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7260 if (!vmx_msr_bitmap_longmode) {
7261 r = -ENOMEM;
7262 goto out2;
7263 }
7264
fdef3ad1
HQ		 7265 /*
7266 * Allow direct access to the PC debug port (it is often used for I/O
7267 * delays, but the vmexits simply slow things down).
7268 */
3e7c73e9
AK		 7269 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7270 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7271
3e7c73e9 7272 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7273
5897297b
AK		 7274 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7275 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7276
2384d2b3
SY		 7277 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7278
0ee75bea
AK		 7279 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7280 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7281 if (r)
5897297b 7282 goto out3;
25c5f225 7283
5897297b
AK		 7284 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7285 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7286 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7287 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7288 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7289 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7290
089d034e 7291 if (enable_ept) {
3f6d8c8a
XH		 7292 kvm_mmu_set_mask_ptes(0ull,
7293 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7294 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7295 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7296 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7297 kvm_enable_tdp();
7298 } else
7299 kvm_disable_tdp();
1439442c 7300
fdef3ad1
HQ		 7301 return 0;
7302
5897297b
AK		 7303out3:
7304 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7305out2:
5897297b 7306 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7307out1:
3e7c73e9 7308 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7309out:
3e7c73e9 7310 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7311 return r;
6aa8b732
AK		 7312}
7313
7314static void __exit vmx_exit(void)
7315{
5897297b
AK		 7316 free_page((unsigned long)vmx_msr_bitmap_legacy);
7317 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7318 free_page((unsigned long)vmx_io_bitmap_b);
7319 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7320
cb498ea2 7321 kvm_exit();
6aa8b732
AK		 7322}
7323
7324module_init(vmx_init)
7325module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)