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KVM: Move #endif KVM_CAP_IRQ_ROUTING to correct place
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
a2fa3e9f
GH		 64struct vmcs {
65 u32 revision_id;
66 u32 abort;
67 char data[0];
68};
69
70struct vcpu_vmx {
fb3f0f51 71 struct kvm_vcpu vcpu;
543e4243 72 struct list_head local_vcpus_link;
313dbd49 73 unsigned long host_rsp;
a2fa3e9f 74 int launched;
29bd8a78 75 u8 fail;
1155f76a 76 u32 idt_vectoring_info;
a2fa3e9f
GH		 77 struct kvm_msr_entry *guest_msrs;
78 struct kvm_msr_entry *host_msrs;
79 int nmsrs;
80 int save_nmsrs;
81 int msr_offset_efer;
82#ifdef CONFIG_X86_64
83 int msr_offset_kernel_gs_base;
84#endif
85 struct vmcs *vmcs;
86 struct {
87 int loaded;
88 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 89 int gs_ldt_reload_needed;
90 int fs_reload_needed;
51c6cf66 91 int guest_efer_loaded;
d77c26fc 92 } host_state;
9c8cba37 93 struct {
7ffd92c5
AK		 94 int vm86_active;
95 u8 save_iopl;
96 struct kvm_save_segment {
97 u16 selector;
98 unsigned long base;
99 u32 limit;
100 u32 ar;
101 } tr, es, ds, fs, gs;
9c8cba37
AK		 102 struct {
103 bool pending;
104 u8 vector;
105 unsigned rip;
106 } irq;
107 } rmode;
2384d2b3 108 int vpid;
04fa4d32 109 bool emulation_required;
8b3079a5 110 enum emulation_result invalid_state_emulation_result;
3b86cd99
JK		 111
112 /* Support for vnmi-less CPUs */
113 int soft_vnmi_blocked;
114 ktime_t entry_time;
115 s64 vnmi_blocked_time;
a0861c02 116 u32 exit_reason;
a2fa3e9f
GH		 117};
118
119static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
120{
fb3f0f51 121 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 122}
123
b7ebfb05 124static int init_rmode(struct kvm *kvm);
4e1096d2 125static u64 construct_eptp(unsigned long root_hpa);
75880a01 126
6aa8b732
AK		 127static DEFINE_PER_CPU(struct vmcs *, vmxarea);
128static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 129static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 130
3e7c73e9
AK		 131static unsigned long *vmx_io_bitmap_a;
132static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 133static unsigned long *vmx_msr_bitmap_legacy;
134static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 135
2384d2b3
SY		 136static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
137static DEFINE_SPINLOCK(vmx_vpid_lock);
138
1c3d14fe 139static struct vmcs_config {
6aa8b732
AK		 140 int size;
141 int order;
142 u32 revision_id;
1c3d14fe
YS		 143 u32 pin_based_exec_ctrl;
144 u32 cpu_based_exec_ctrl;
f78e0e2e 145 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 146 u32 vmexit_ctrl;
147 u32 vmentry_ctrl;
148} vmcs_config;
6aa8b732 149
efff9e53 150static struct vmx_capability {
d56f546d
SY		 151 u32 ept;
152 u32 vpid;
153} vmx_capability;
154
6aa8b732
AK		 155#define VMX_SEGMENT_FIELD(seg) \
156 [VCPU_SREG_##seg] = { \
157 .selector = GUEST_##seg##_SELECTOR, \
158 .base = GUEST_##seg##_BASE, \
159 .limit = GUEST_##seg##_LIMIT, \
160 .ar_bytes = GUEST_##seg##_AR_BYTES, \
161 }
162
163static struct kvm_vmx_segment_field {
164 unsigned selector;
165 unsigned base;
166 unsigned limit;
167 unsigned ar_bytes;
168} kvm_vmx_segment_fields[] = {
169 VMX_SEGMENT_FIELD(CS),
170 VMX_SEGMENT_FIELD(DS),
171 VMX_SEGMENT_FIELD(ES),
172 VMX_SEGMENT_FIELD(FS),
173 VMX_SEGMENT_FIELD(GS),
174 VMX_SEGMENT_FIELD(SS),
175 VMX_SEGMENT_FIELD(TR),
176 VMX_SEGMENT_FIELD(LDTR),
177};
178
6de4f3ad
AK		 179static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
180
4d56c8a7
AK		 181/*
182 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
183 * away by decrementing the array size.
184 */
6aa8b732 185static const u32 vmx_msr_index[] = {
05b3e0c2 186#ifdef CONFIG_X86_64
6aa8b732
AK		 187 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
188#endif
189 MSR_EFER, MSR_K6_STAR,
190};
9d8f549d 191#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 192
a2fa3e9f
GH		 193static void load_msrs(struct kvm_msr_entry *e, int n)
194{
195 int i;
196
197 for (i = 0; i < n; ++i)
198 wrmsrl(e[i].index, e[i].data);
199}
200
201static void save_msrs(struct kvm_msr_entry *e, int n)
202{
203 int i;
204
205 for (i = 0; i < n; ++i)
206 rdmsrl(e[i].index, e[i].data);
207}
208
6aa8b732
AK		 209static inline int is_page_fault(u32 intr_info)
210{
211 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
212 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 213 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 214}
215
2ab455cc
AL		 216static inline int is_no_device(u32 intr_info)
217{
218 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
219 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 220 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 221}
222
7aa81cc0
AL		 223static inline int is_invalid_opcode(u32 intr_info)
224{
225 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
226 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 227 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 228}
229
6aa8b732
AK		 230static inline int is_external_interrupt(u32 intr_info)
231{
232 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
233 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
234}
235
a0861c02
AK		 236static inline int is_machine_check(u32 intr_info)
237{
238 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
239 INTR_INFO_VALID_MASK)) ==
240 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
241}
242
25c5f225
SY		 243static inline int cpu_has_vmx_msr_bitmap(void)
244{
04547156 245 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 246}
247
6e5d865c
YS		 248static inline int cpu_has_vmx_tpr_shadow(void)
249{
04547156 250 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 251}
252
253static inline int vm_need_tpr_shadow(struct kvm *kvm)
254{
04547156 255 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 256}
257
f78e0e2e
SY		 258static inline int cpu_has_secondary_exec_ctrls(void)
259{
04547156
SY		 260 return vmcs_config.cpu_based_exec_ctrl &
261 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 262}
263
774ead3a 264static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 265{
04547156
SY		 266 return vmcs_config.cpu_based_2nd_exec_ctrl &
267 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
268}
269
270static inline bool cpu_has_vmx_flexpriority(void)
271{
272 return cpu_has_vmx_tpr_shadow() &&
273 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 274}
275
e799794e
MT		 276static inline bool cpu_has_vmx_ept_execute_only(void)
277{
278 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
279}
280
281static inline bool cpu_has_vmx_eptp_uncacheable(void)
282{
283 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
284}
285
286static inline bool cpu_has_vmx_eptp_writeback(void)
287{
288 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
289}
290
291static inline bool cpu_has_vmx_ept_2m_page(void)
292{
293 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
294}
295
d56f546d
SY		 296static inline int cpu_has_vmx_invept_individual_addr(void)
297{
04547156 298 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 299}
300
301static inline int cpu_has_vmx_invept_context(void)
302{
04547156 303 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 304}
305
306static inline int cpu_has_vmx_invept_global(void)
307{
04547156 308 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 309}
310
311static inline int cpu_has_vmx_ept(void)
312{
04547156
SY		 313 return vmcs_config.cpu_based_2nd_exec_ctrl &
314 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 315}
316
3a624e29
NK		 317static inline int cpu_has_vmx_unrestricted_guest(void)
318{
319 return vmcs_config.cpu_based_2nd_exec_ctrl &
320 SECONDARY_EXEC_UNRESTRICTED_GUEST;
321}
322
f78e0e2e
SY		 323static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
324{
04547156
SY		 325 return flexpriority_enabled &&
326 (cpu_has_vmx_virtualize_apic_accesses()) &&
327 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 328}
329
2384d2b3
SY		 330static inline int cpu_has_vmx_vpid(void)
331{
04547156
SY		 332 return vmcs_config.cpu_based_2nd_exec_ctrl &
333 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 334}
335
f08864b4
SY		 336static inline int cpu_has_virtual_nmis(void)
337{
338 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
339}
340
04547156
SY		 341static inline bool report_flexpriority(void)
342{
343 return flexpriority_enabled;
344}
345
8b9cf98c 346static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 347{
348 int i;
349
a2fa3e9f
GH		 350 for (i = 0; i < vmx->nmsrs; ++i)
351 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 352 return i;
353 return -1;
354}
355
2384d2b3
SY		 356static inline void __invvpid(int ext, u16 vpid, gva_t gva)
357{
358 struct {
359 u64 vpid : 16;
360 u64 rsvd : 48;
361 u64 gva;
362 } operand = { vpid, 0, gva };
363
4ecac3fd 364 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 365 /* CF==1 or ZF==1 --> rc = -1 */
366 "; ja 1f ; ud2 ; 1:"
367 : : "a"(&operand), "c"(ext) : "cc", "memory");
368}
369
1439442c
SY		 370static inline void __invept(int ext, u64 eptp, gpa_t gpa)
371{
372 struct {
373 u64 eptp, gpa;
374 } operand = {eptp, gpa};
375
4ecac3fd 376 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 377 /* CF==1 or ZF==1 --> rc = -1 */
378 "; ja 1f ; ud2 ; 1:\n"
379 : : "a" (&operand), "c" (ext) : "cc", "memory");
380}
381
8b9cf98c 382static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 383{
384 int i;
385
8b9cf98c 386 i = __find_msr_index(vmx, msr);
a75beee6 387 if (i >= 0)
a2fa3e9f 388 return &vmx->guest_msrs[i];
8b6d44c7 389 return NULL;
7725f0ba
AK		 390}
391
6aa8b732
AK		 392static void vmcs_clear(struct vmcs *vmcs)
393{
394 u64 phys_addr = __pa(vmcs);
395 u8 error;
396
4ecac3fd 397 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 398 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
399 : "cc", "memory");
400 if (error)
401 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
402 vmcs, phys_addr);
403}
404
405static void __vcpu_clear(void *arg)
406{
8b9cf98c 407 struct vcpu_vmx *vmx = arg;
d3b2c338 408 int cpu = raw_smp_processor_id();
6aa8b732 409
8b9cf98c 410 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 411 vmcs_clear(vmx->vmcs);
412 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 413 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 414 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 415 list_del(&vmx->local_vcpus_link);
416 vmx->vcpu.cpu = -1;
417 vmx->launched = 0;
6aa8b732
AK		 418}
419
8b9cf98c 420static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 421{
eae5ecb5
AK		 422 if (vmx->vcpu.cpu == -1)
423 return;
8691e5a8 424 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 425}
426
2384d2b3
SY		 427static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
428{
429 if (vmx->vpid == 0)
430 return;
431
432 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
433}
434
1439442c
SY		 435static inline void ept_sync_global(void)
436{
437 if (cpu_has_vmx_invept_global())
438 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
439}
440
441static inline void ept_sync_context(u64 eptp)
442{
089d034e 443 if (enable_ept) {
1439442c
SY		 444 if (cpu_has_vmx_invept_context())
445 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
446 else
447 ept_sync_global();
448 }
449}
450
451static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
452{
089d034e 453 if (enable_ept) {
1439442c
SY		 454 if (cpu_has_vmx_invept_individual_addr())
455 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
456 eptp, gpa);
457 else
458 ept_sync_context(eptp);
459 }
460}
461
6aa8b732
AK		 462static unsigned long vmcs_readl(unsigned long field)
463{
464 unsigned long value;
465
4ecac3fd 466 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 467 : "=a"(value) : "d"(field) : "cc");
468 return value;
469}
470
471static u16 vmcs_read16(unsigned long field)
472{
473 return vmcs_readl(field);
474}
475
476static u32 vmcs_read32(unsigned long field)
477{
478 return vmcs_readl(field);
479}
480
481static u64 vmcs_read64(unsigned long field)
482{
05b3e0c2 483#ifdef CONFIG_X86_64
6aa8b732
AK		 484 return vmcs_readl(field);
485#else
486 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
487#endif
488}
489
e52de1b8
AK		 490static noinline void vmwrite_error(unsigned long field, unsigned long value)
491{
492 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
493 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
494 dump_stack();
495}
496
6aa8b732
AK		 497static void vmcs_writel(unsigned long field, unsigned long value)
498{
499 u8 error;
500
4ecac3fd 501 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 502 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 503 if (unlikely(error))
504 vmwrite_error(field, value);
6aa8b732
AK		 505}
506
507static void vmcs_write16(unsigned long field, u16 value)
508{
509 vmcs_writel(field, value);
510}
511
512static void vmcs_write32(unsigned long field, u32 value)
513{
514 vmcs_writel(field, value);
515}
516
517static void vmcs_write64(unsigned long field, u64 value)
518{
6aa8b732 519 vmcs_writel(field, value);
7682f2d0 520#ifndef CONFIG_X86_64
6aa8b732
AK		 521 asm volatile ("");
522 vmcs_writel(field+1, value >> 32);
523#endif
524}
525
2ab455cc
AL		 526static void vmcs_clear_bits(unsigned long field, u32 mask)
527{
528 vmcs_writel(field, vmcs_readl(field) & ~mask);
529}
530
531static void vmcs_set_bits(unsigned long field, u32 mask)
532{
533 vmcs_writel(field, vmcs_readl(field) | mask);
534}
535
abd3f2d6
AK		 536static void update_exception_bitmap(struct kvm_vcpu *vcpu)
537{
538 u32 eb;
539
a0861c02 540 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 541 if (!vcpu->fpu_active)
542 eb |= 1u << NM_VECTOR;
d0bfb940
JK		 543 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
544 if (vcpu->guest_debug &
545 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
546 eb |= 1u << DB_VECTOR;
547 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
548 eb |= 1u << BP_VECTOR;
549 }
7ffd92c5 550 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 551 eb = ~0;
089d034e 552 if (enable_ept)
1439442c 553 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 554 vmcs_write32(EXCEPTION_BITMAP, eb);
555}
556
33ed6329
AK		 557static void reload_tss(void)
558{
33ed6329
AK		 559 /*
560 * VT restores TR but not its size. Useless.
561 */
562 struct descriptor_table gdt;
a5f61300 563 struct desc_struct *descs;
33ed6329 564
d6e88aec 565 kvm_get_gdt(&gdt);
33ed6329
AK		 566 descs = (void *)gdt.base;
567 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
568 load_TR_desc();
33ed6329
AK		 569}
570
8b9cf98c 571static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 572{
a2fa3e9f 573 int efer_offset = vmx->msr_offset_efer;
3a34a881
RK		 574 u64 host_efer;
575 u64 guest_efer;
51c6cf66
AK		 576 u64 ignore_bits;
577
578 if (efer_offset < 0)
579 return;
3a34a881
RK		 580 host_efer = vmx->host_msrs[efer_offset].data;
581 guest_efer = vmx->guest_msrs[efer_offset].data;
582
51c6cf66
AK		 583 /*
584 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
585 * outside long mode
586 */
587 ignore_bits = EFER_NX | EFER_SCE;
588#ifdef CONFIG_X86_64
589 ignore_bits |= EFER_LMA | EFER_LME;
590 /* SCE is meaningful only in long mode on Intel */
591 if (guest_efer & EFER_LMA)
592 ignore_bits &= ~(u64)EFER_SCE;
593#endif
594 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
595 return;
2cc51560 596
51c6cf66
AK		 597 vmx->host_state.guest_efer_loaded = 1;
598 guest_efer &= ~ignore_bits;
599 guest_efer |= host_efer & ignore_bits;
600 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 601 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 602}
603
51c6cf66
AK		 604static void reload_host_efer(struct vcpu_vmx *vmx)
605{
606 if (vmx->host_state.guest_efer_loaded) {
607 vmx->host_state.guest_efer_loaded = 0;
608 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
609 }
610}
611
04d2cc77 612static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 613{
04d2cc77
AK		 614 struct vcpu_vmx *vmx = to_vmx(vcpu);
615
a2fa3e9f 616 if (vmx->host_state.loaded)
33ed6329
AK		 617 return;
618
a2fa3e9f 619 vmx->host_state.loaded = 1;
33ed6329
AK		 620 /*
621 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
622 * allow segment selectors with cpl > 0 or ti == 1.
623 */
d6e88aec 624 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 625 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 626 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 627 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 628 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 629 vmx->host_state.fs_reload_needed = 0;
630 } else {
33ed6329 631 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 632 vmx->host_state.fs_reload_needed = 1;
33ed6329 633 }
d6e88aec 634 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 635 if (!(vmx->host_state.gs_sel & 7))
636 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 637 else {
638 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 639 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 640 }
641
642#ifdef CONFIG_X86_64
643 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
644 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
645#else
a2fa3e9f
GH		 646 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
647 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 648#endif
707c0874
AK		 649
650#ifdef CONFIG_X86_64
d77c26fc 651 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 652 save_msrs(vmx->host_msrs +
653 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 654
707c0874 655#endif
a2fa3e9f 656 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 657 load_transition_efer(vmx);
33ed6329
AK		 658}
659
a9b21b62 660static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 661{
15ad7146 662 unsigned long flags;
33ed6329 663
a2fa3e9f 664 if (!vmx->host_state.loaded)
33ed6329
AK		 665 return;
666
e1beb1d3 667 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 668 vmx->host_state.loaded = 0;
152d3f2f 669 if (vmx->host_state.fs_reload_needed)
d6e88aec 670 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 671 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 672 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 673 /*
674 * If we have to reload gs, we must take care to
675 * preserve our gs base.
676 */
15ad7146 677 local_irq_save(flags);
d6e88aec 678 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 679#ifdef CONFIG_X86_64
680 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
681#endif
15ad7146 682 local_irq_restore(flags);
33ed6329 683 }
152d3f2f 684 reload_tss();
a2fa3e9f
GH		 685 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
686 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 687 reload_host_efer(vmx);
33ed6329
AK		 688}
689
a9b21b62
AK		 690static void vmx_load_host_state(struct vcpu_vmx *vmx)
691{
692 preempt_disable();
693 __vmx_load_host_state(vmx);
694 preempt_enable();
695}
696
6aa8b732
AK		 697/*
698 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
699 * vcpu mutex is already taken.
700 */
15ad7146 701static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 702{
a2fa3e9f
GH		 703 struct vcpu_vmx *vmx = to_vmx(vcpu);
704 u64 phys_addr = __pa(vmx->vmcs);
019960ae 705 u64 tsc_this, delta, new_offset;
6aa8b732 706
a3d7f85f 707 if (vcpu->cpu != cpu) {
8b9cf98c 708 vcpu_clear(vmx);
2f599714 709 kvm_migrate_timers(vcpu);
2384d2b3 710 vpid_sync_vcpu_all(vmx);
543e4243
AK		 711 local_irq_disable();
712 list_add(&vmx->local_vcpus_link,
713 &per_cpu(vcpus_on_cpu, cpu));
714 local_irq_enable();
a3d7f85f 715 }
6aa8b732 716
a2fa3e9f 717 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 718 u8 error;
719
a2fa3e9f 720 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 721 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 722 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
723 : "cc");
724 if (error)
725 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 726 vmx->vmcs, phys_addr);
6aa8b732
AK		 727 }
728
729 if (vcpu->cpu != cpu) {
730 struct descriptor_table dt;
731 unsigned long sysenter_esp;
732
733 vcpu->cpu = cpu;
734 /*
735 * Linux uses per-cpu TSS and GDT, so set these when switching
736 * processors.
737 */
d6e88aec
AK		 738 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
739 kvm_get_gdt(&dt);
6aa8b732
AK		 740 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
741
742 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
743 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 744
745 /*
746 * Make sure the time stamp counter is monotonous.
747 */
748 rdtscll(tsc_this);
019960ae
AK		 749 if (tsc_this < vcpu->arch.host_tsc) {
750 delta = vcpu->arch.host_tsc - tsc_this;
751 new_offset = vmcs_read64(TSC_OFFSET) + delta;
752 vmcs_write64(TSC_OFFSET, new_offset);
753 }
6aa8b732 754 }
6aa8b732
AK		 755}
756
757static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
758{
a9b21b62 759 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 760}
761
5fd86fcf
AK		 762static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
763{
764 if (vcpu->fpu_active)
765 return;
766 vcpu->fpu_active = 1;
707d92fa 767 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 768 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 769 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 770 update_exception_bitmap(vcpu);
771}
772
773static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
774{
775 if (!vcpu->fpu_active)
776 return;
777 vcpu->fpu_active = 0;
707d92fa 778 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 779 update_exception_bitmap(vcpu);
780}
781
6aa8b732
AK		 782static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
783{
784 return vmcs_readl(GUEST_RFLAGS);
785}
786
787static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
788{
7ffd92c5 789 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 790 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 791 vmcs_writel(GUEST_RFLAGS, rflags);
792}
793
2809f5d2
GC		 794static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
795{
796 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
797 int ret = 0;
798
799 if (interruptibility & GUEST_INTR_STATE_STI)
800 ret |= X86_SHADOW_INT_STI;
801 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
802 ret |= X86_SHADOW_INT_MOV_SS;
803
804 return ret & mask;
805}
806
807static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
808{
809 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
810 u32 interruptibility = interruptibility_old;
811
812 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
813
814 if (mask & X86_SHADOW_INT_MOV_SS)
815 interruptibility |= GUEST_INTR_STATE_MOV_SS;
816 if (mask & X86_SHADOW_INT_STI)
817 interruptibility |= GUEST_INTR_STATE_STI;
818
819 if ((interruptibility != interruptibility_old))
820 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
821}
822
6aa8b732
AK		 823static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
824{
825 unsigned long rip;
6aa8b732 826
5fdbf976 827 rip = kvm_rip_read(vcpu);
6aa8b732 828 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 829 kvm_rip_write(vcpu, rip);
6aa8b732 830
2809f5d2
GC		 831 /* skipping an emulated instruction also counts */
832 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 833}
834
298101da
AK		 835static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
836 bool has_error_code, u32 error_code)
837{
77ab6db0 838 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 839 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 840
8ab2d2e2 841 if (has_error_code) {
77ab6db0 842 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 843 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
844 }
77ab6db0 845
7ffd92c5 846 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 847 vmx->rmode.irq.pending = true;
848 vmx->rmode.irq.vector = nr;
849 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 850 if (kvm_exception_is_soft(nr))
851 vmx->rmode.irq.rip +=
852 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 853 intr_info |= INTR_TYPE_SOFT_INTR;
854 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 855 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
856 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
857 return;
858 }
859
66fd3f7f
GN		 860 if (kvm_exception_is_soft(nr)) {
861 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
862 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 863 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
864 } else
865 intr_info |= INTR_TYPE_HARD_EXCEPTION;
866
867 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 868}
869
a75beee6
ED		 870/*
871 * Swap MSR entry in host/guest MSR entry array.
872 */
54e11fa1 873#ifdef CONFIG_X86_64
8b9cf98c 874static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 875{
a2fa3e9f
GH		 876 struct kvm_msr_entry tmp;
877
878 tmp = vmx->guest_msrs[to];
879 vmx->guest_msrs[to] = vmx->guest_msrs[from];
880 vmx->guest_msrs[from] = tmp;
881 tmp = vmx->host_msrs[to];
882 vmx->host_msrs[to] = vmx->host_msrs[from];
883 vmx->host_msrs[from] = tmp;
a75beee6 884}
54e11fa1 885#endif
a75beee6 886
e38aea3e
AK		 887/*
888 * Set up the vmcs to automatically save and restore system
889 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
890 * mode, as fiddling with msrs is very expensive.
891 */
8b9cf98c 892static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 893{
2cc51560 894 int save_nmsrs;
5897297b 895 unsigned long *msr_bitmap;
e38aea3e 896
33f9c505 897 vmx_load_host_state(vmx);
a75beee6
ED		 898 save_nmsrs = 0;
899#ifdef CONFIG_X86_64
8b9cf98c 900 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 901 int index;
902
8b9cf98c 903 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 904 if (index >= 0)
8b9cf98c
RR		 905 move_msr_up(vmx, index, save_nmsrs++);
906 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 907 if (index >= 0)
8b9cf98c
RR		 908 move_msr_up(vmx, index, save_nmsrs++);
909 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 910 if (index >= 0)
8b9cf98c
RR		 911 move_msr_up(vmx, index, save_nmsrs++);
912 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 913 if (index >= 0)
8b9cf98c 914 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 915 /*
916 * MSR_K6_STAR is only needed on long mode guests, and only
917 * if efer.sce is enabled.
918 */
8b9cf98c 919 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 920 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 921 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 922 }
923#endif
a2fa3e9f 924 vmx->save_nmsrs = save_nmsrs;
e38aea3e 925
4d56c8a7 926#ifdef CONFIG_X86_64
a2fa3e9f 927 vmx->msr_offset_kernel_gs_base =
8b9cf98c 928 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 929#endif
8b9cf98c 930 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
5897297b
AK		 931
932 if (cpu_has_vmx_msr_bitmap()) {
933 if (is_long_mode(&vmx->vcpu))
934 msr_bitmap = vmx_msr_bitmap_longmode;
935 else
936 msr_bitmap = vmx_msr_bitmap_legacy;
937
938 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
939 }
e38aea3e
AK		 940}
941
6aa8b732
AK		 942/*
943 * reads and returns guest's timestamp counter "register"
944 * guest_tsc = host_tsc + tsc_offset -- 21.3
945 */
946static u64 guest_read_tsc(void)
947{
948 u64 host_tsc, tsc_offset;
949
950 rdtscll(host_tsc);
951 tsc_offset = vmcs_read64(TSC_OFFSET);
952 return host_tsc + tsc_offset;
953}
954
955/*
956 * writes 'guest_tsc' into guest's timestamp counter "register"
957 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
958 */
53f658b3 959static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 960{
6aa8b732
AK		 961 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
962}
963
6aa8b732
AK		 964/*
965 * Reads an msr value (of 'msr_index') into 'pdata'.
966 * Returns 0 on success, non-0 otherwise.
967 * Assumes vcpu_load() was already called.
968 */
969static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
970{
971 u64 data;
a2fa3e9f 972 struct kvm_msr_entry *msr;
6aa8b732
AK		 973
974 if (!pdata) {
975 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
976 return -EINVAL;
977 }
978
979 switch (msr_index) {
05b3e0c2 980#ifdef CONFIG_X86_64
6aa8b732
AK		 981 case MSR_FS_BASE:
982 data = vmcs_readl(GUEST_FS_BASE);
983 break;
984 case MSR_GS_BASE:
985 data = vmcs_readl(GUEST_GS_BASE);
986 break;
987 case MSR_EFER:
3bab1f5d 988 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732 989#endif
af24a4e4 990 case MSR_IA32_TSC:
6aa8b732
AK		 991 data = guest_read_tsc();
992 break;
993 case MSR_IA32_SYSENTER_CS:
994 data = vmcs_read32(GUEST_SYSENTER_CS);
995 break;
996 case MSR_IA32_SYSENTER_EIP:
f5b42c33 997 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 998 break;
999 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1000 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1001 break;
6aa8b732 1002 default:
516a1a7e 1003 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1004 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 1005 if (msr) {
1006 data = msr->data;
1007 break;
6aa8b732 1008 }
3bab1f5d 1009 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1010 }
1011
1012 *pdata = data;
1013 return 0;
1014}
1015
1016/*
1017 * Writes msr value into into the appropriate "register".
1018 * Returns 0 on success, non-0 otherwise.
1019 * Assumes vcpu_load() was already called.
1020 */
1021static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1022{
a2fa3e9f
GH		 1023 struct vcpu_vmx *vmx = to_vmx(vcpu);
1024 struct kvm_msr_entry *msr;
53f658b3 1025 u64 host_tsc;
2cc51560
ED		 1026 int ret = 0;
1027
6aa8b732 1028 switch (msr_index) {
3bab1f5d 1029 case MSR_EFER:
a9b21b62 1030 vmx_load_host_state(vmx);
2cc51560 1031 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1032 break;
16175a79 1033#ifdef CONFIG_X86_64
6aa8b732
AK		 1034 case MSR_FS_BASE:
1035 vmcs_writel(GUEST_FS_BASE, data);
1036 break;
1037 case MSR_GS_BASE:
1038 vmcs_writel(GUEST_GS_BASE, data);
1039 break;
1040#endif
1041 case MSR_IA32_SYSENTER_CS:
1042 vmcs_write32(GUEST_SYSENTER_CS, data);
1043 break;
1044 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1045 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1046 break;
1047 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1048 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1049 break;
af24a4e4 1050 case MSR_IA32_TSC:
53f658b3
MT		 1051 rdtscll(host_tsc);
1052 guest_write_tsc(data, host_tsc);
6aa8b732 1053 break;
468d472f
SY		 1054 case MSR_IA32_CR_PAT:
1055 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1056 vmcs_write64(GUEST_IA32_PAT, data);
1057 vcpu->arch.pat = data;
1058 break;
1059 }
1060 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1061 default:
a9b21b62 1062 vmx_load_host_state(vmx);
8b9cf98c 1063 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 1064 if (msr) {
1065 msr->data = data;
1066 break;
6aa8b732 1067 }
2cc51560 1068 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1069 }
1070
2cc51560 1071 return ret;
6aa8b732
AK		 1072}
1073
5fdbf976 1074static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1075{
5fdbf976
MT		 1076 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1077 switch (reg) {
1078 case VCPU_REGS_RSP:
1079 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1080 break;
1081 case VCPU_REGS_RIP:
1082 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1083 break;
6de4f3ad
AK		 1084 case VCPU_EXREG_PDPTR:
1085 if (enable_ept)
1086 ept_save_pdptrs(vcpu);
1087 break;
5fdbf976
MT		 1088 default:
1089 break;
1090 }
6aa8b732
AK		 1091}
1092
d0bfb940 1093static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1094{
d0bfb940
JK		 1095 int old_debug = vcpu->guest_debug;
1096 unsigned long flags;
6aa8b732 1097
d0bfb940
JK		 1098 vcpu->guest_debug = dbg->control;
1099 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1100 vcpu->guest_debug = 0;
6aa8b732 1101
ae675ef0
JK		 1102 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1103 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1104 else
1105 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1106
d0bfb940
JK		 1107 flags = vmcs_readl(GUEST_RFLAGS);
1108 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1109 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1110 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1111 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1112 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1113
abd3f2d6 1114 update_exception_bitmap(vcpu);
6aa8b732
AK		 1115
1116 return 0;
1117}
1118
1119static __init int cpu_has_kvm_support(void)
1120{
6210e37b 1121 return cpu_has_vmx();
6aa8b732
AK		 1122}
1123
1124static __init int vmx_disabled_by_bios(void)
1125{
1126 u64 msr;
1127
1128 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1129 return (msr & (FEATURE_CONTROL_LOCKED |
1130 FEATURE_CONTROL_VMXON_ENABLED))
1131 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1132 /* locked but not enabled */
6aa8b732
AK		 1133}
1134
774c47f1 1135static void hardware_enable(void *garbage)
6aa8b732
AK		 1136{
1137 int cpu = raw_smp_processor_id();
1138 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1139 u64 old;
1140
543e4243 1141 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1142 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1143 if ((old & (FEATURE_CONTROL_LOCKED |
1144 FEATURE_CONTROL_VMXON_ENABLED))
1145 != (FEATURE_CONTROL_LOCKED |
1146 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1147 /* enable and lock */
62b3ffb8 1148 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1149 FEATURE_CONTROL_LOCKED |
1150 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1151 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1152 asm volatile (ASM_VMX_VMXON_RAX
1153 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1154 : "memory", "cc");
1155}
1156
543e4243
AK		 1157static void vmclear_local_vcpus(void)
1158{
1159 int cpu = raw_smp_processor_id();
1160 struct vcpu_vmx *vmx, *n;
1161
1162 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1163 local_vcpus_link)
1164 __vcpu_clear(vmx);
1165}
1166
710ff4a8
EH		 1167
1168/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1169 * tricks.
1170 */
1171static void kvm_cpu_vmxoff(void)
6aa8b732 1172{
4ecac3fd 1173 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1174 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1175}
1176
710ff4a8
EH		 1177static void hardware_disable(void *garbage)
1178{
1179 vmclear_local_vcpus();
1180 kvm_cpu_vmxoff();
1181}
1182
1c3d14fe 1183static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1184 u32 msr, u32 *result)
1c3d14fe
YS		 1185{
1186 u32 vmx_msr_low, vmx_msr_high;
1187 u32 ctl = ctl_min | ctl_opt;
1188
1189 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1190
1191 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1192 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1193
1194 /* Ensure minimum (required) set of control bits are supported. */
1195 if (ctl_min & ~ctl)
002c7f7c 1196 return -EIO;
1c3d14fe
YS		 1197
1198 *result = ctl;
1199 return 0;
1200}
1201
002c7f7c 1202static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1203{
1204 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1205 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1206 u32 _pin_based_exec_control = 0;
1207 u32 _cpu_based_exec_control = 0;
f78e0e2e 1208 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1209 u32 _vmexit_control = 0;
1210 u32 _vmentry_control = 0;
1211
1212 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1213 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1214 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1215 &_pin_based_exec_control) < 0)
002c7f7c 1216 return -EIO;
1c3d14fe
YS		 1217
1218 min = CPU_BASED_HLT_EXITING |
1219#ifdef CONFIG_X86_64
1220 CPU_BASED_CR8_LOAD_EXITING |
1221 CPU_BASED_CR8_STORE_EXITING |
1222#endif
d56f546d
SY		 1223 CPU_BASED_CR3_LOAD_EXITING |
1224 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1225 CPU_BASED_USE_IO_BITMAPS |
1226 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1227 CPU_BASED_USE_TSC_OFFSETING |
1228 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1229 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1230 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1231 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1232 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1233 &_cpu_based_exec_control) < 0)
002c7f7c 1234 return -EIO;
6e5d865c
YS		 1235#ifdef CONFIG_X86_64
1236 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1237 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1238 ~CPU_BASED_CR8_STORE_EXITING;
1239#endif
f78e0e2e 1240 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1241 min2 = 0;
1242 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1243 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1244 SECONDARY_EXEC_ENABLE_VPID |
3a624e29
NK		 1245 SECONDARY_EXEC_ENABLE_EPT |
1246 SECONDARY_EXEC_UNRESTRICTED_GUEST;
d56f546d
SY		 1247 if (adjust_vmx_controls(min2, opt2,
1248 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1249 &_cpu_based_2nd_exec_control) < 0)
1250 return -EIO;
1251 }
1252#ifndef CONFIG_X86_64
1253 if (!(_cpu_based_2nd_exec_control &
1254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1255 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1256#endif
d56f546d 1257 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1258 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1259 enabled */
d56f546d 1260 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1261 CPU_BASED_CR3_STORE_EXITING |
1262 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1263 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1264 &_cpu_based_exec_control) < 0)
1265 return -EIO;
1266 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1267 vmx_capability.ept, vmx_capability.vpid);
1268 }
1c3d14fe
YS		 1269
1270 min = 0;
1271#ifdef CONFIG_X86_64
1272 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1273#endif
468d472f 1274 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1275 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1276 &_vmexit_control) < 0)
002c7f7c 1277 return -EIO;
1c3d14fe 1278
468d472f
SY		 1279 min = 0;
1280 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1281 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1282 &_vmentry_control) < 0)
002c7f7c 1283 return -EIO;
6aa8b732 1284
c68876fd 1285 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1286
1287 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1288 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1289 return -EIO;
1c3d14fe
YS		 1290
1291#ifdef CONFIG_X86_64
1292 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1293 if (vmx_msr_high & (1u<<16))
002c7f7c 1294 return -EIO;
1c3d14fe
YS		 1295#endif
1296
1297 /* Require Write-Back (WB) memory type for VMCS accesses. */
1298 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1299 return -EIO;
1c3d14fe 1300
002c7f7c
YS		 1301 vmcs_conf->size = vmx_msr_high & 0x1fff;
1302 vmcs_conf->order = get_order(vmcs_config.size);
1303 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1304
002c7f7c
YS		 1305 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1306 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1307 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1308 vmcs_conf->vmexit_ctrl = _vmexit_control;
1309 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1310
1311 return 0;
c68876fd 1312}
6aa8b732
AK		 1313
1314static struct vmcs *alloc_vmcs_cpu(int cpu)
1315{
1316 int node = cpu_to_node(cpu);
1317 struct page *pages;
1318 struct vmcs *vmcs;
1319
6484eb3e 1320 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1321 if (!pages)
1322 return NULL;
1323 vmcs = page_address(pages);
1c3d14fe
YS		 1324 memset(vmcs, 0, vmcs_config.size);
1325 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1326 return vmcs;
1327}
1328
1329static struct vmcs *alloc_vmcs(void)
1330{
d3b2c338 1331 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1332}
1333
1334static void free_vmcs(struct vmcs *vmcs)
1335{
1c3d14fe 1336 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1337}
1338
39959588 1339static void free_kvm_area(void)
6aa8b732
AK		 1340{
1341 int cpu;
1342
1343 for_each_online_cpu(cpu)
1344 free_vmcs(per_cpu(vmxarea, cpu));
1345}
1346
6aa8b732
AK		 1347static __init int alloc_kvm_area(void)
1348{
1349 int cpu;
1350
1351 for_each_online_cpu(cpu) {
1352 struct vmcs *vmcs;
1353
1354 vmcs = alloc_vmcs_cpu(cpu);
1355 if (!vmcs) {
1356 free_kvm_area();
1357 return -ENOMEM;
1358 }
1359
1360 per_cpu(vmxarea, cpu) = vmcs;
1361 }
1362 return 0;
1363}
1364
1365static __init int hardware_setup(void)
1366{
002c7f7c
YS		 1367 if (setup_vmcs_config(&vmcs_config) < 0)
1368 return -EIO;
50a37eb4
JR		 1369
1370 if (boot_cpu_has(X86_FEATURE_NX))
1371 kvm_enable_efer_bits(EFER_NX);
1372
93ba03c2
SY		 1373 if (!cpu_has_vmx_vpid())
1374 enable_vpid = 0;
1375
3a624e29 1376 if (!cpu_has_vmx_ept()) {
93ba03c2 1377 enable_ept = 0;
3a624e29
NK		 1378 enable_unrestricted_guest = 0;
1379 }
1380
1381 if (!cpu_has_vmx_unrestricted_guest())
1382 enable_unrestricted_guest = 0;
93ba03c2
SY		 1383
1384 if (!cpu_has_vmx_flexpriority())
1385 flexpriority_enabled = 0;
1386
95ba8273
GN		 1387 if (!cpu_has_vmx_tpr_shadow())
1388 kvm_x86_ops->update_cr8_intercept = NULL;
1389
54dee993
MT		 1390 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1391 kvm_disable_largepages();
1392
6aa8b732
AK		 1393 return alloc_kvm_area();
1394}
1395
1396static __exit void hardware_unsetup(void)
1397{
1398 free_kvm_area();
1399}
1400
6aa8b732
AK		 1401static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1402{
1403 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1404
6af11b9e 1405 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1406 vmcs_write16(sf->selector, save->selector);
1407 vmcs_writel(sf->base, save->base);
1408 vmcs_write32(sf->limit, save->limit);
1409 vmcs_write32(sf->ar_bytes, save->ar);
1410 } else {
1411 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1412 << AR_DPL_SHIFT;
1413 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1414 }
1415}
1416
1417static void enter_pmode(struct kvm_vcpu *vcpu)
1418{
1419 unsigned long flags;
a89a8fb9 1420 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1421
a89a8fb9 1422 vmx->emulation_required = 1;
7ffd92c5 1423 vmx->rmode.vm86_active = 0;
6aa8b732 1424
7ffd92c5
AK		 1425 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1426 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1427 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1428
1429 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1430 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1431 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1432 vmcs_writel(GUEST_RFLAGS, flags);
1433
66aee91a
RR		 1434 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1435 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1436
1437 update_exception_bitmap(vcpu);
1438
a89a8fb9
MG		 1439 if (emulate_invalid_guest_state)
1440 return;
1441
7ffd92c5
AK		 1442 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1443 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1444 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1445 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1446
1447 vmcs_write16(GUEST_SS_SELECTOR, 0);
1448 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1449
1450 vmcs_write16(GUEST_CS_SELECTOR,
1451 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1452 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1453}
1454
d77c26fc 1455static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1456{
bfc6d222 1457 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1458 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1459 kvm->memslots[0].npages - 3;
1460 return base_gfn << PAGE_SHIFT;
1461 }
bfc6d222 1462 return kvm->arch.tss_addr;
6aa8b732
AK		 1463}
1464
1465static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1466{
1467 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1468
1469 save->selector = vmcs_read16(sf->selector);
1470 save->base = vmcs_readl(sf->base);
1471 save->limit = vmcs_read32(sf->limit);
1472 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1473 vmcs_write16(sf->selector, save->base >> 4);
1474 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1475 vmcs_write32(sf->limit, 0xffff);
1476 vmcs_write32(sf->ar_bytes, 0xf3);
1477}
1478
1479static void enter_rmode(struct kvm_vcpu *vcpu)
1480{
1481 unsigned long flags;
a89a8fb9 1482 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1483
3a624e29
NK		 1484 if (enable_unrestricted_guest)
1485 return;
1486
a89a8fb9 1487 vmx->emulation_required = 1;
7ffd92c5 1488 vmx->rmode.vm86_active = 1;
6aa8b732 1489
7ffd92c5 1490 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1491 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1492
7ffd92c5 1493 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1494 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1495
7ffd92c5 1496 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1497 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1498
1499 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1500 vmx->rmode.save_iopl
ad312c7c 1501 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1502
053de044 1503 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1504
1505 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1506 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1507 update_exception_bitmap(vcpu);
1508
a89a8fb9
MG		 1509 if (emulate_invalid_guest_state)
1510 goto continue_rmode;
1511
6aa8b732
AK		 1512 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1513 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1514 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1515
1516 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1517 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1518 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1519 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1520 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1521
7ffd92c5
AK		 1522 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1523 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1524 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1525 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1526
a89a8fb9 1527continue_rmode:
8668a3c4 1528 kvm_mmu_reset_context(vcpu);
b7ebfb05 1529 init_rmode(vcpu->kvm);
6aa8b732
AK		 1530}
1531
401d10de
AS		 1532static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1533{
1534 struct vcpu_vmx *vmx = to_vmx(vcpu);
1535 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1536
1537 vcpu->arch.shadow_efer = efer;
1538 if (!msr)
1539 return;
1540 if (efer & EFER_LMA) {
1541 vmcs_write32(VM_ENTRY_CONTROLS,
1542 vmcs_read32(VM_ENTRY_CONTROLS) |
1543 VM_ENTRY_IA32E_MODE);
1544 msr->data = efer;
1545 } else {
1546 vmcs_write32(VM_ENTRY_CONTROLS,
1547 vmcs_read32(VM_ENTRY_CONTROLS) &
1548 ~VM_ENTRY_IA32E_MODE);
1549
1550 msr->data = efer & ~EFER_LME;
1551 }
1552 setup_msrs(vmx);
1553}
1554
05b3e0c2 1555#ifdef CONFIG_X86_64
6aa8b732
AK		 1556
1557static void enter_lmode(struct kvm_vcpu *vcpu)
1558{
1559 u32 guest_tr_ar;
1560
1561 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1562 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1563 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1564 __func__);
6aa8b732
AK		 1565 vmcs_write32(GUEST_TR_AR_BYTES,
1566 (guest_tr_ar & ~AR_TYPE_MASK)
1567 | AR_TYPE_BUSY_64_TSS);
1568 }
ad312c7c 1569 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1570 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1571}
1572
1573static void exit_lmode(struct kvm_vcpu *vcpu)
1574{
ad312c7c 1575 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1576
1577 vmcs_write32(VM_ENTRY_CONTROLS,
1578 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1579 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1580}
1581
1582#endif
1583
2384d2b3
SY		 1584static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1585{
1586 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1587 if (enable_ept)
4e1096d2 1588 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1589}
1590
25c4c276 1591static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1592{
ad312c7c
ZX		 1593 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1594 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1595}
1596
1439442c
SY		 1597static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1598{
6de4f3ad
AK		 1599 if (!test_bit(VCPU_EXREG_PDPTR,
1600 (unsigned long *)&vcpu->arch.regs_dirty))
1601 return;
1602
1439442c 1603 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1604 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1605 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1606 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1607 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1608 }
1609}
1610
8f5d549f
AK		 1611static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1612{
1613 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1614 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1615 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1616 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1617 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1618 }
6de4f3ad
AK		 1619
1620 __set_bit(VCPU_EXREG_PDPTR,
1621 (unsigned long *)&vcpu->arch.regs_avail);
1622 __set_bit(VCPU_EXREG_PDPTR,
1623 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1624}
1625
1439442c
SY		 1626static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1627
1628static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1629 unsigned long cr0,
1630 struct kvm_vcpu *vcpu)
1631{
1632 if (!(cr0 & X86_CR0_PG)) {
1633 /* From paging/starting to nonpaging */
1634 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1635 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1636 (CPU_BASED_CR3_LOAD_EXITING |
1637 CPU_BASED_CR3_STORE_EXITING));
1638 vcpu->arch.cr0 = cr0;
1639 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c
SY		 1640 *hw_cr0 &= ~X86_CR0_WP;
1641 } else if (!is_paging(vcpu)) {
1642 /* From nonpaging to paging */
1643 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1644 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1645 ~(CPU_BASED_CR3_LOAD_EXITING |
1646 CPU_BASED_CR3_STORE_EXITING));
1647 vcpu->arch.cr0 = cr0;
1648 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1649 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1650 *hw_cr0 &= ~X86_CR0_WP;
1651 }
1652}
1653
1654static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1655 struct kvm_vcpu *vcpu)
1656{
1657 if (!is_paging(vcpu)) {
1658 *hw_cr4 &= ~X86_CR4_PAE;
1659 *hw_cr4 |= X86_CR4_PSE;
1660 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1661 *hw_cr4 &= ~X86_CR4_PAE;
1662}
1663
6aa8b732
AK		 1664static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1665{
7ffd92c5 1666 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1667 unsigned long hw_cr0;
1668
1669 if (enable_unrestricted_guest)
1670 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1671 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1672 else
1673 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1674
5fd86fcf
AK		 1675 vmx_fpu_deactivate(vcpu);
1676
7ffd92c5 1677 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1678 enter_pmode(vcpu);
1679
7ffd92c5 1680 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1681 enter_rmode(vcpu);
1682
05b3e0c2 1683#ifdef CONFIG_X86_64
ad312c7c 1684 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1685 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1686 enter_lmode(vcpu);
707d92fa 1687 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1688 exit_lmode(vcpu);
1689 }
1690#endif
1691
089d034e 1692 if (enable_ept)
1439442c
SY		 1693 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1694
6aa8b732 1695 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1696 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1697 vcpu->arch.cr0 = cr0;
5fd86fcf 1698
707d92fa 1699 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1700 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1701}
1702
1439442c
SY		 1703static u64 construct_eptp(unsigned long root_hpa)
1704{
1705 u64 eptp;
1706
1707 /* TODO write the value reading from MSR */
1708 eptp = VMX_EPT_DEFAULT_MT |
1709 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1710 eptp |= (root_hpa & PAGE_MASK);
1711
1712 return eptp;
1713}
1714
6aa8b732
AK		 1715static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1716{
1439442c
SY		 1717 unsigned long guest_cr3;
1718 u64 eptp;
1719
1720 guest_cr3 = cr3;
089d034e 1721 if (enable_ept) {
1439442c
SY		 1722 eptp = construct_eptp(cr3);
1723 vmcs_write64(EPT_POINTER, eptp);
1439442c 1724 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1725 vcpu->kvm->arch.ept_identity_map_addr;
1439442c
SY		 1726 }
1727
2384d2b3 1728 vmx_flush_tlb(vcpu);
1439442c 1729 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1730 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1731 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1732}
1733
1734static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1735{
7ffd92c5 1736 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1737 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1738
ad312c7c 1739 vcpu->arch.cr4 = cr4;
089d034e 1740 if (enable_ept)
1439442c
SY		 1741 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1742
1743 vmcs_writel(CR4_READ_SHADOW, cr4);
1744 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1745}
1746
6aa8b732
AK		 1747static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1748{
1749 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1750
1751 return vmcs_readl(sf->base);
1752}
1753
1754static void vmx_get_segment(struct kvm_vcpu *vcpu,
1755 struct kvm_segment *var, int seg)
1756{
1757 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1758 u32 ar;
1759
1760 var->base = vmcs_readl(sf->base);
1761 var->limit = vmcs_read32(sf->limit);
1762 var->selector = vmcs_read16(sf->selector);
1763 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1764 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1765 ar = 0;
1766 var->type = ar & 15;
1767 var->s = (ar >> 4) & 1;
1768 var->dpl = (ar >> 5) & 3;
1769 var->present = (ar >> 7) & 1;
1770 var->avl = (ar >> 12) & 1;
1771 var->l = (ar >> 13) & 1;
1772 var->db = (ar >> 14) & 1;
1773 var->g = (ar >> 15) & 1;
1774 var->unusable = (ar >> 16) & 1;
1775}
1776
2e4d2653
IE		 1777static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1778{
2e4d2653
IE		 1779 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1780 return 0;
1781
1782 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1783 return 3;
1784
eab4b8aa 1785 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1786}
1787
653e3108 1788static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1789{
6aa8b732
AK		 1790 u32 ar;
1791
653e3108 1792 if (var->unusable)
6aa8b732
AK		 1793 ar = 1 << 16;
1794 else {
1795 ar = var->type & 15;
1796 ar |= (var->s & 1) << 4;
1797 ar |= (var->dpl & 3) << 5;
1798 ar |= (var->present & 1) << 7;
1799 ar |= (var->avl & 1) << 12;
1800 ar |= (var->l & 1) << 13;
1801 ar |= (var->db & 1) << 14;
1802 ar |= (var->g & 1) << 15;
1803 }
f7fbf1fd
UL		 1804 if (ar == 0) /* a 0 value means unusable */
1805 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1806
1807 return ar;
1808}
1809
1810static void vmx_set_segment(struct kvm_vcpu *vcpu,
1811 struct kvm_segment *var, int seg)
1812{
7ffd92c5 1813 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1814 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1815 u32 ar;
1816
7ffd92c5
AK		 1817 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1818 vmx->rmode.tr.selector = var->selector;
1819 vmx->rmode.tr.base = var->base;
1820 vmx->rmode.tr.limit = var->limit;
1821 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1822 return;
1823 }
1824 vmcs_writel(sf->base, var->base);
1825 vmcs_write32(sf->limit, var->limit);
1826 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1827 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1828 /*
1829 * Hack real-mode segments into vm86 compatibility.
1830 */
1831 if (var->base == 0xffff0000 && var->selector == 0xf000)
1832 vmcs_writel(sf->base, 0xf0000);
1833 ar = 0xf3;
1834 } else
1835 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1836
1837 /*
1838 * Fix the "Accessed" bit in AR field of segment registers for older
1839 * qemu binaries.
1840 * IA32 arch specifies that at the time of processor reset the
1841 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1842 * is setting it to 0 in the usedland code. This causes invalid guest
1843 * state vmexit when "unrestricted guest" mode is turned on.
1844 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1845 * tree. Newer qemu binaries with that qemu fix would not need this
1846 * kvm hack.
1847 */
1848 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1849 ar |= 0x1; /* Accessed */
1850
6aa8b732
AK		 1851 vmcs_write32(sf->ar_bytes, ar);
1852}
1853
6aa8b732
AK		 1854static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1855{
1856 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1857
1858 *db = (ar >> 14) & 1;
1859 *l = (ar >> 13) & 1;
1860}
1861
1862static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1863{
1864 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1865 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1866}
1867
1868static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1869{
1870 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1871 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1872}
1873
1874static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1875{
1876 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1877 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1878}
1879
1880static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1881{
1882 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1883 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1884}
1885
648dfaa7
MG		 1886static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1887{
1888 struct kvm_segment var;
1889 u32 ar;
1890
1891 vmx_get_segment(vcpu, &var, seg);
1892 ar = vmx_segment_access_rights(&var);
1893
1894 if (var.base != (var.selector << 4))
1895 return false;
1896 if (var.limit != 0xffff)
1897 return false;
1898 if (ar != 0xf3)
1899 return false;
1900
1901 return true;
1902}
1903
1904static bool code_segment_valid(struct kvm_vcpu *vcpu)
1905{
1906 struct kvm_segment cs;
1907 unsigned int cs_rpl;
1908
1909 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1910 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1911
1872a3f4
AK		 1912 if (cs.unusable)
1913 return false;
648dfaa7
MG		 1914 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1915 return false;
1916 if (!cs.s)
1917 return false;
1872a3f4 1918 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1919 if (cs.dpl > cs_rpl)
1920 return false;
1872a3f4 1921 } else {
648dfaa7
MG		 1922 if (cs.dpl != cs_rpl)
1923 return false;
1924 }
1925 if (!cs.present)
1926 return false;
1927
1928 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1929 return true;
1930}
1931
1932static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1933{
1934 struct kvm_segment ss;
1935 unsigned int ss_rpl;
1936
1937 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1938 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1939
1872a3f4
AK		 1940 if (ss.unusable)
1941 return true;
1942 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1943 return false;
1944 if (!ss.s)
1945 return false;
1946 if (ss.dpl != ss_rpl) /* DPL != RPL */
1947 return false;
1948 if (!ss.present)
1949 return false;
1950
1951 return true;
1952}
1953
1954static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1955{
1956 struct kvm_segment var;
1957 unsigned int rpl;
1958
1959 vmx_get_segment(vcpu, &var, seg);
1960 rpl = var.selector & SELECTOR_RPL_MASK;
1961
1872a3f4
AK		 1962 if (var.unusable)
1963 return true;
648dfaa7
MG		 1964 if (!var.s)
1965 return false;
1966 if (!var.present)
1967 return false;
1968 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1969 if (var.dpl < rpl) /* DPL < RPL */
1970 return false;
1971 }
1972
1973 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1974 * rights flags
1975 */
1976 return true;
1977}
1978
1979static bool tr_valid(struct kvm_vcpu *vcpu)
1980{
1981 struct kvm_segment tr;
1982
1983 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1984
1872a3f4
AK		 1985 if (tr.unusable)
1986 return false;
648dfaa7
MG		 1987 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1988 return false;
1872a3f4 1989 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 1990 return false;
1991 if (!tr.present)
1992 return false;
1993
1994 return true;
1995}
1996
1997static bool ldtr_valid(struct kvm_vcpu *vcpu)
1998{
1999 struct kvm_segment ldtr;
2000
2001 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2002
1872a3f4
AK		 2003 if (ldtr.unusable)
2004 return true;
648dfaa7
MG		 2005 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2006 return false;
2007 if (ldtr.type != 2)
2008 return false;
2009 if (!ldtr.present)
2010 return false;
2011
2012 return true;
2013}
2014
2015static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2016{
2017 struct kvm_segment cs, ss;
2018
2019 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2020 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2021
2022 return ((cs.selector & SELECTOR_RPL_MASK) ==
2023 (ss.selector & SELECTOR_RPL_MASK));
2024}
2025
2026/*
2027 * Check if guest state is valid. Returns true if valid, false if
2028 * not.
2029 * We assume that registers are always usable
2030 */
2031static bool guest_state_valid(struct kvm_vcpu *vcpu)
2032{
2033 /* real mode guest state checks */
2034 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2035 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2036 return false;
2037 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2038 return false;
2039 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2040 return false;
2041 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2042 return false;
2043 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2044 return false;
2045 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2046 return false;
2047 } else {
2048 /* protected mode guest state checks */
2049 if (!cs_ss_rpl_check(vcpu))
2050 return false;
2051 if (!code_segment_valid(vcpu))
2052 return false;
2053 if (!stack_segment_valid(vcpu))
2054 return false;
2055 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2056 return false;
2057 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2058 return false;
2059 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2060 return false;
2061 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2062 return false;
2063 if (!tr_valid(vcpu))
2064 return false;
2065 if (!ldtr_valid(vcpu))
2066 return false;
2067 }
2068 /* TODO:
2069 * - Add checks on RIP
2070 * - Add checks on RFLAGS
2071 */
2072
2073 return true;
2074}
2075
d77c26fc 2076static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2077{
6aa8b732 2078 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2079 u16 data = 0;
10589a46 2080 int ret = 0;
195aefde 2081 int r;
6aa8b732 2082
195aefde
IE		 2083 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2084 if (r < 0)
10589a46 2085 goto out;
195aefde 2086 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2087 r = kvm_write_guest_page(kvm, fn++, &data,
2088 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2089 if (r < 0)
10589a46 2090 goto out;
195aefde
IE		 2091 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2092 if (r < 0)
10589a46 2093 goto out;
195aefde
IE		 2094 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2095 if (r < 0)
10589a46 2096 goto out;
195aefde 2097 data = ~0;
10589a46
MT		 2098 r = kvm_write_guest_page(kvm, fn, &data,
2099 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2100 sizeof(u8));
195aefde 2101 if (r < 0)
10589a46
MT		 2102 goto out;
2103
2104 ret = 1;
2105out:
10589a46 2106 return ret;
6aa8b732
AK		 2107}
2108
b7ebfb05
SY		 2109static int init_rmode_identity_map(struct kvm *kvm)
2110{
2111 int i, r, ret;
2112 pfn_t identity_map_pfn;
2113 u32 tmp;
2114
089d034e 2115 if (!enable_ept)
b7ebfb05
SY		 2116 return 1;
2117 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2118 printk(KERN_ERR "EPT: identity-mapping pagetable "
2119 "haven't been allocated!\n");
2120 return 0;
2121 }
2122 if (likely(kvm->arch.ept_identity_pagetable_done))
2123 return 1;
2124 ret = 0;
b927a3ce 2125 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2126 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2127 if (r < 0)
2128 goto out;
2129 /* Set up identity-mapping pagetable for EPT in real mode */
2130 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2131 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2132 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2133 r = kvm_write_guest_page(kvm, identity_map_pfn,
2134 &tmp, i * sizeof(tmp), sizeof(tmp));
2135 if (r < 0)
2136 goto out;
2137 }
2138 kvm->arch.ept_identity_pagetable_done = true;
2139 ret = 1;
2140out:
2141 return ret;
2142}
2143
6aa8b732
AK		 2144static void seg_setup(int seg)
2145{
2146 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2147 unsigned int ar;
6aa8b732
AK		 2148
2149 vmcs_write16(sf->selector, 0);
2150 vmcs_writel(sf->base, 0);
2151 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2152 if (enable_unrestricted_guest) {
2153 ar = 0x93;
2154 if (seg == VCPU_SREG_CS)
2155 ar |= 0x08; /* code segment */
2156 } else
2157 ar = 0xf3;
2158
2159 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2160}
2161
f78e0e2e
SY		 2162static int alloc_apic_access_page(struct kvm *kvm)
2163{
2164 struct kvm_userspace_memory_region kvm_userspace_mem;
2165 int r = 0;
2166
72dc67a6 2167 down_write(&kvm->slots_lock);
bfc6d222 2168 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2169 goto out;
2170 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2171 kvm_userspace_mem.flags = 0;
2172 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2173 kvm_userspace_mem.memory_size = PAGE_SIZE;
2174 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2175 if (r)
2176 goto out;
72dc67a6 2177
bfc6d222 2178 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2179out:
72dc67a6 2180 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2181 return r;
2182}
2183
b7ebfb05
SY		 2184static int alloc_identity_pagetable(struct kvm *kvm)
2185{
2186 struct kvm_userspace_memory_region kvm_userspace_mem;
2187 int r = 0;
2188
2189 down_write(&kvm->slots_lock);
2190 if (kvm->arch.ept_identity_pagetable)
2191 goto out;
2192 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2193 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2194 kvm_userspace_mem.guest_phys_addr =
2195 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2196 kvm_userspace_mem.memory_size = PAGE_SIZE;
2197 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2198 if (r)
2199 goto out;
2200
b7ebfb05 2201 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2202 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2203out:
2204 up_write(&kvm->slots_lock);
2205 return r;
2206}
2207
2384d2b3
SY		 2208static void allocate_vpid(struct vcpu_vmx *vmx)
2209{
2210 int vpid;
2211
2212 vmx->vpid = 0;
919818ab 2213 if (!enable_vpid)
2384d2b3
SY		 2214 return;
2215 spin_lock(&vmx_vpid_lock);
2216 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2217 if (vpid < VMX_NR_VPIDS) {
2218 vmx->vpid = vpid;
2219 __set_bit(vpid, vmx_vpid_bitmap);
2220 }
2221 spin_unlock(&vmx_vpid_lock);
2222}
2223
5897297b 2224static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2225{
3e7c73e9 2226 int f = sizeof(unsigned long);
25c5f225
SY		 2227
2228 if (!cpu_has_vmx_msr_bitmap())
2229 return;
2230
2231 /*
2232 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2233 * have the write-low and read-high bitmap offsets the wrong way round.
2234 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2235 */
25c5f225 2236 if (msr <= 0x1fff) {
3e7c73e9
AK		 2237 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2238 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2239 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2240 msr &= 0x1fff;
3e7c73e9
AK		 2241 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2242 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2243 }
25c5f225
SY		 2244}
2245
5897297b
AK		 2246static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2247{
2248 if (!longmode_only)
2249 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2250 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2251}
2252
6aa8b732
AK		 2253/*
2254 * Sets up the vmcs for emulated real mode.
2255 */
8b9cf98c 2256static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2257{
468d472f 2258 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2259 u32 junk;
53f658b3 2260 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2261 unsigned long a;
2262 struct descriptor_table dt;
2263 int i;
cd2276a7 2264 unsigned long kvm_vmx_return;
6e5d865c 2265 u32 exec_control;
6aa8b732 2266
6aa8b732 2267 /* I/O */
3e7c73e9
AK		 2268 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2269 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2270
25c5f225 2271 if (cpu_has_vmx_msr_bitmap())
5897297b 2272 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2273
6aa8b732
AK		 2274 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2275
6aa8b732 2276 /* Control */
1c3d14fe
YS		 2277 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2278 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2279
2280 exec_control = vmcs_config.cpu_based_exec_ctrl;
2281 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2282 exec_control &= ~CPU_BASED_TPR_SHADOW;
2283#ifdef CONFIG_X86_64
2284 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2285 CPU_BASED_CR8_LOAD_EXITING;
2286#endif
2287 }
089d034e 2288 if (!enable_ept)
d56f546d 2289 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2290 CPU_BASED_CR3_LOAD_EXITING |
2291 CPU_BASED_INVLPG_EXITING;
6e5d865c 2292 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2293
83ff3b9d
SY		 2294 if (cpu_has_secondary_exec_ctrls()) {
2295 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2296 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2297 exec_control &=
2298 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2299 if (vmx->vpid == 0)
2300 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
089d034e 2301 if (!enable_ept)
d56f546d 2302 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3a624e29
NK		 2303 if (!enable_unrestricted_guest)
2304 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
83ff3b9d
SY		 2305 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2306 }
f78e0e2e 2307
c7addb90
AK		 2308 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2309 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2310 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2311
2312 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2313 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2314 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2315
2316 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2317 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2318 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2319 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2320 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2321 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2322#ifdef CONFIG_X86_64
6aa8b732
AK		 2323 rdmsrl(MSR_FS_BASE, a);
2324 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2325 rdmsrl(MSR_GS_BASE, a);
2326 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2327#else
2328 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2329 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2330#endif
2331
2332 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2333
d6e88aec 2334 kvm_get_idt(&dt);
6aa8b732
AK		 2335 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2336
d77c26fc 2337 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2338 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2339 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2340 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2341 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2342
2343 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2344 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2345 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2346 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2347 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2348 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2349
468d472f
SY		 2350 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2351 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2352 host_pat = msr_low | ((u64) msr_high << 32);
2353 vmcs_write64(HOST_IA32_PAT, host_pat);
2354 }
2355 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2356 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2357 host_pat = msr_low | ((u64) msr_high << 32);
2358 /* Write the default value follow host pat */
2359 vmcs_write64(GUEST_IA32_PAT, host_pat);
2360 /* Keep arch.pat sync with GUEST_IA32_PAT */
2361 vmx->vcpu.arch.pat = host_pat;
2362 }
2363
6aa8b732
AK		 2364 for (i = 0; i < NR_VMX_MSR; ++i) {
2365 u32 index = vmx_msr_index[i];
2366 u32 data_low, data_high;
2367 u64 data;
a2fa3e9f 2368 int j = vmx->nmsrs;
6aa8b732
AK		 2369
2370 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2371 continue;
432bd6cb
AK		 2372 if (wrmsr_safe(index, data_low, data_high) < 0)
2373 continue;
6aa8b732 2374 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2375 vmx->host_msrs[j].index = index;
2376 vmx->host_msrs[j].reserved = 0;
2377 vmx->host_msrs[j].data = data;
2378 vmx->guest_msrs[j] = vmx->host_msrs[j];
2379 ++vmx->nmsrs;
6aa8b732 2380 }
6aa8b732 2381
1c3d14fe 2382 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2383
2384 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2385 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2386
e00c8cf2
AK		 2387 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2388 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2389
53f658b3
MT		 2390 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2391 rdtscll(tsc_this);
2392 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2393 tsc_base = tsc_this;
2394
2395 guest_write_tsc(0, tsc_base);
f78e0e2e 2396
e00c8cf2
AK		 2397 return 0;
2398}
2399
b7ebfb05
SY		 2400static int init_rmode(struct kvm *kvm)
2401{
2402 if (!init_rmode_tss(kvm))
2403 return 0;
2404 if (!init_rmode_identity_map(kvm))
2405 return 0;
2406 return 1;
2407}
2408
e00c8cf2
AK		 2409static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2410{
2411 struct vcpu_vmx *vmx = to_vmx(vcpu);
2412 u64 msr;
2413 int ret;
2414
5fdbf976 2415 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2416 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2417 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2418 ret = -ENOMEM;
2419 goto out;
2420 }
2421
7ffd92c5 2422 vmx->rmode.vm86_active = 0;
e00c8cf2 2423
3b86cd99
JK		 2424 vmx->soft_vnmi_blocked = 0;
2425
ad312c7c 2426 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2427 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2428 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2429 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2430 msr |= MSR_IA32_APICBASE_BSP;
2431 kvm_set_apic_base(&vmx->vcpu, msr);
2432
2433 fx_init(&vmx->vcpu);
2434
5706be0d 2435 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2436 /*
2437 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2438 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2439 */
c5af89b6 2440 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2441 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2442 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2443 } else {
ad312c7c
ZX		 2444 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2445 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2446 }
e00c8cf2
AK		 2447
2448 seg_setup(VCPU_SREG_DS);
2449 seg_setup(VCPU_SREG_ES);
2450 seg_setup(VCPU_SREG_FS);
2451 seg_setup(VCPU_SREG_GS);
2452 seg_setup(VCPU_SREG_SS);
2453
2454 vmcs_write16(GUEST_TR_SELECTOR, 0);
2455 vmcs_writel(GUEST_TR_BASE, 0);
2456 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2457 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2458
2459 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2460 vmcs_writel(GUEST_LDTR_BASE, 0);
2461 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2462 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2463
2464 vmcs_write32(GUEST_SYSENTER_CS, 0);
2465 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2466 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2467
2468 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2469 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2470 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2471 else
5fdbf976
MT		 2472 kvm_rip_write(vcpu, 0);
2473 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2474
e00c8cf2
AK		 2475 vmcs_writel(GUEST_DR7, 0x400);
2476
2477 vmcs_writel(GUEST_GDTR_BASE, 0);
2478 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2479
2480 vmcs_writel(GUEST_IDTR_BASE, 0);
2481 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2482
2483 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2484 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2485 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2486
e00c8cf2
AK		 2487 /* Special registers */
2488 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2489
2490 setup_msrs(vmx);
2491
6aa8b732
AK		 2492 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2493
f78e0e2e
SY		 2494 if (cpu_has_vmx_tpr_shadow()) {
2495 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2496 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2497 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2498 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2499 vmcs_write32(TPR_THRESHOLD, 0);
2500 }
2501
2502 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2503 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2504 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2505
2384d2b3
SY		 2506 if (vmx->vpid != 0)
2507 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2508
ad312c7c
ZX		 2509 vmx->vcpu.arch.cr0 = 0x60000010;
2510 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2511 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2512 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2513 vmx_fpu_activate(&vmx->vcpu);
2514 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2515
2384d2b3
SY		 2516 vpid_sync_vcpu_all(vmx);
2517
3200f405 2518 ret = 0;
6aa8b732 2519
a89a8fb9
MG		 2520 /* HACK: Don't enable emulation on guest boot/reset */
2521 vmx->emulation_required = 0;
2522
6aa8b732 2523out:
3200f405 2524 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2525 return ret;
2526}
2527
3b86cd99
JK		 2528static void enable_irq_window(struct kvm_vcpu *vcpu)
2529{
2530 u32 cpu_based_vm_exec_control;
2531
2532 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2533 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2534 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2535}
2536
2537static void enable_nmi_window(struct kvm_vcpu *vcpu)
2538{
2539 u32 cpu_based_vm_exec_control;
2540
2541 if (!cpu_has_virtual_nmis()) {
2542 enable_irq_window(vcpu);
2543 return;
2544 }
2545
2546 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2547 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2548 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2549}
2550
66fd3f7f 2551static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2552{
9c8cba37 2553 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2554 uint32_t intr;
2555 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2556
229456fc 2557 trace_kvm_inj_virq(irq);
2714d1d3 2558
fa89a817 2559 ++vcpu->stat.irq_injections;
7ffd92c5 2560 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2561 vmx->rmode.irq.pending = true;
2562 vmx->rmode.irq.vector = irq;
5fdbf976 2563 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2564 if (vcpu->arch.interrupt.soft)
2565 vmx->rmode.irq.rip +=
2566 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2567 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2568 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2569 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2570 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2571 return;
2572 }
66fd3f7f
GN		 2573 intr = irq | INTR_INFO_VALID_MASK;
2574 if (vcpu->arch.interrupt.soft) {
2575 intr |= INTR_TYPE_SOFT_INTR;
2576 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2577 vmx->vcpu.arch.event_exit_inst_len);
2578 } else
2579 intr |= INTR_TYPE_EXT_INTR;
2580 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2581}
2582
f08864b4
SY		 2583static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2584{
66a5a347
JK		 2585 struct vcpu_vmx *vmx = to_vmx(vcpu);
2586
3b86cd99
JK		 2587 if (!cpu_has_virtual_nmis()) {
2588 /*
2589 * Tracking the NMI-blocked state in software is built upon
2590 * finding the next open IRQ window. This, in turn, depends on
2591 * well-behaving guests: They have to keep IRQs disabled at
2592 * least as long as the NMI handler runs. Otherwise we may
2593 * cause NMI nesting, maybe breaking the guest. But as this is
2594 * highly unlikely, we can live with the residual risk.
2595 */
2596 vmx->soft_vnmi_blocked = 1;
2597 vmx->vnmi_blocked_time = 0;
2598 }
2599
487b391d 2600 ++vcpu->stat.nmi_injections;
7ffd92c5 2601 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2602 vmx->rmode.irq.pending = true;
2603 vmx->rmode.irq.vector = NMI_VECTOR;
2604 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2605 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2606 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2607 INTR_INFO_VALID_MASK);
2608 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2609 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2610 return;
2611 }
f08864b4
SY		 2612 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2613 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2614}
2615
c4282df9 2616static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2617{
3b86cd99 2618 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2619 return 0;
33f089ca 2620
c4282df9
GN		 2621 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2622 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2623 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2624}
2625
78646121
GN		 2626static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2627{
c4282df9
GN		 2628 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2629 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2630 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2631}
2632
cbc94022
IE		 2633static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2634{
2635 int ret;
2636 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2637 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2638 .guest_phys_addr = addr,
2639 .memory_size = PAGE_SIZE * 3,
2640 .flags = 0,
2641 };
2642
2643 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2644 if (ret)
2645 return ret;
bfc6d222 2646 kvm->arch.tss_addr = addr;
cbc94022
IE		 2647 return 0;
2648}
2649
6aa8b732
AK		 2650static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2651 int vec, u32 err_code)
2652{
b3f37707
NK		 2653 /*
2654 * Instruction with address size override prefix opcode 0x67
2655 * Cause the #SS fault with 0 error code in VM86 mode.
2656 */
2657 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2658 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2659 return 1;
77ab6db0
JK		 2660 /*
2661 * Forward all other exceptions that are valid in real mode.
2662 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2663 * the required debugging infrastructure rework.
2664 */
2665 switch (vec) {
77ab6db0 2666 case DB_VECTOR:
d0bfb940
JK		 2667 if (vcpu->guest_debug &
2668 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2669 return 0;
2670 kvm_queue_exception(vcpu, vec);
2671 return 1;
77ab6db0 2672 case BP_VECTOR:
d0bfb940
JK		 2673 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2674 return 0;
2675 /* fall through */
2676 case DE_VECTOR:
77ab6db0
JK		 2677 case OF_VECTOR:
2678 case BR_VECTOR:
2679 case UD_VECTOR:
2680 case DF_VECTOR:
2681 case SS_VECTOR:
2682 case GP_VECTOR:
2683 case MF_VECTOR:
2684 kvm_queue_exception(vcpu, vec);
2685 return 1;
2686 }
6aa8b732
AK		 2687 return 0;
2688}
2689
a0861c02
AK		 2690/*
2691 * Trigger machine check on the host. We assume all the MSRs are already set up
2692 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2693 * We pass a fake environment to the machine check handler because we want
2694 * the guest to be always treated like user space, no matter what context
2695 * it used internally.
2696 */
2697static void kvm_machine_check(void)
2698{
2699#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2700 struct pt_regs regs = {
2701 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2702 .flags = X86_EFLAGS_IF,
2703 };
2704
2705 do_machine_check(&regs, 0);
2706#endif
2707}
2708
2709static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2710{
2711 /* already handled by vcpu_run */
2712 return 1;
2713}
2714
6aa8b732
AK		 2715static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2716{
1155f76a 2717 struct vcpu_vmx *vmx = to_vmx(vcpu);
d0bfb940 2718 u32 intr_info, ex_no, error_code;
42dbaa5a 2719 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2720 u32 vect_info;
2721 enum emulation_result er;
2722
1155f76a 2723 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2724 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2725
a0861c02
AK		 2726 if (is_machine_check(intr_info))
2727 return handle_machine_check(vcpu, kvm_run);
2728
6aa8b732 2729 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2730 !is_page_fault(intr_info))
6aa8b732 2731 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2732 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2733
e4a41889 2734 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2735 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2736
2737 if (is_no_device(intr_info)) {
5fd86fcf 2738 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2739 return 1;
2740 }
2741
7aa81cc0 2742 if (is_invalid_opcode(intr_info)) {
571008da 2743 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2744 if (er != EMULATE_DONE)
7ee5d940 2745 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2746 return 1;
2747 }
2748
6aa8b732 2749 error_code = 0;
5fdbf976 2750 rip = kvm_rip_read(vcpu);
2e11384c 2751 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2752 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2753 if (is_page_fault(intr_info)) {
1439442c 2754 /* EPT won't cause page fault directly */
089d034e 2755 if (enable_ept)
1439442c 2756 BUG();
6aa8b732 2757 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2758 trace_kvm_page_fault(cr2, error_code);
2759
3298b75c 2760 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2761 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2762 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2763 }
2764
7ffd92c5 2765 if (vmx->rmode.vm86_active &&
6aa8b732 2766 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2767 error_code)) {
ad312c7c
ZX		 2768 if (vcpu->arch.halt_request) {
2769 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2770 return kvm_emulate_halt(vcpu);
2771 }
6aa8b732 2772 return 1;
72d6e5a0 2773 }
6aa8b732 2774
d0bfb940 2775 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2776 switch (ex_no) {
2777 case DB_VECTOR:
2778 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2779 if (!(vcpu->guest_debug &
2780 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2781 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2782 kvm_queue_exception(vcpu, DB_VECTOR);
2783 return 1;
2784 }
2785 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2786 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2787 /* fall through */
2788 case BP_VECTOR:
6aa8b732 2789 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2790 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2791 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2792 break;
2793 default:
d0bfb940
JK		 2794 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2795 kvm_run->ex.exception = ex_no;
2796 kvm_run->ex.error_code = error_code;
42dbaa5a 2797 break;
6aa8b732 2798 }
6aa8b732
AK		 2799 return 0;
2800}
2801
2802static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2803 struct kvm_run *kvm_run)
2804{
1165f5fe 2805 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2806 return 1;
2807}
2808
988ad74f
AK		 2809static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2810{
2811 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2812 return 0;
2813}
6aa8b732 2814
6aa8b732
AK		 2815static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2816{
bfdaab09 2817 unsigned long exit_qualification;
34c33d16 2818 int size, in, string;
039576c0 2819 unsigned port;
6aa8b732 2820
1165f5fe 2821 ++vcpu->stat.io_exits;
bfdaab09 2822 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2823 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2824
2825 if (string) {
3427318f
LV		 2826 if (emulate_instruction(vcpu,
2827 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2828 return 0;
2829 return 1;
2830 }
2831
2832 size = (exit_qualification & 7) + 1;
2833 in = (exit_qualification & 8) != 0;
039576c0 2834 port = exit_qualification >> 16;
e70669ab 2835
e93f36bc 2836 skip_emulated_instruction(vcpu);
3090dd73 2837 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2838}
2839
102d8325
IM		 2840static void
2841vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2842{
2843 /*
2844 * Patch in the VMCALL instruction:
2845 */
2846 hypercall[0] = 0x0f;
2847 hypercall[1] = 0x01;
2848 hypercall[2] = 0xc1;
102d8325
IM		 2849}
2850
6aa8b732
AK		 2851static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2852{
229456fc 2853 unsigned long exit_qualification, val;
6aa8b732
AK		 2854 int cr;
2855 int reg;
2856
bfdaab09 2857 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2858 cr = exit_qualification & 15;
2859 reg = (exit_qualification >> 8) & 15;
2860 switch ((exit_qualification >> 4) & 3) {
2861 case 0: /* mov to cr */
229456fc
MT		 2862 val = kvm_register_read(vcpu, reg);
2863 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2864 switch (cr) {
2865 case 0:
229456fc 2866 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2867 skip_emulated_instruction(vcpu);
2868 return 1;
2869 case 3:
229456fc 2870 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2871 skip_emulated_instruction(vcpu);
2872 return 1;
2873 case 4:
229456fc 2874 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2875 skip_emulated_instruction(vcpu);
2876 return 1;
0a5fff19
GN		 2877 case 8: {
2878 u8 cr8_prev = kvm_get_cr8(vcpu);
2879 u8 cr8 = kvm_register_read(vcpu, reg);
2880 kvm_set_cr8(vcpu, cr8);
2881 skip_emulated_instruction(vcpu);
2882 if (irqchip_in_kernel(vcpu->kvm))
2883 return 1;
2884 if (cr8_prev <= cr8)
2885 return 1;
2886 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2887 return 0;
2888 }
6aa8b732
AK		 2889 };
2890 break;
25c4c276 2891 case 2: /* clts */
5fd86fcf 2892 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2893 vcpu->arch.cr0 &= ~X86_CR0_TS;
2894 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2895 vmx_fpu_activate(vcpu);
25c4c276
AL		 2896 skip_emulated_instruction(vcpu);
2897 return 1;
6aa8b732
AK		 2898 case 1: /*mov from cr*/
2899 switch (cr) {
2900 case 3:
5fdbf976 2901 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2902 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2903 skip_emulated_instruction(vcpu);
2904 return 1;
2905 case 8:
229456fc
MT		 2906 val = kvm_get_cr8(vcpu);
2907 kvm_register_write(vcpu, reg, val);
2908 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2909 skip_emulated_instruction(vcpu);
2910 return 1;
2911 }
2912 break;
2913 case 3: /* lmsw */
2d3ad1f4 2914 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2915
2916 skip_emulated_instruction(vcpu);
2917 return 1;
2918 default:
2919 break;
2920 }
2921 kvm_run->exit_reason = 0;
f0242478 2922 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2923 (int)(exit_qualification >> 4) & 3, cr);
2924 return 0;
2925}
2926
2927static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2928{
bfdaab09 2929 unsigned long exit_qualification;
6aa8b732
AK		 2930 unsigned long val;
2931 int dr, reg;
2932
42dbaa5a
JK		 2933 dr = vmcs_readl(GUEST_DR7);
2934 if (dr & DR7_GD) {
2935 /*
2936 * As the vm-exit takes precedence over the debug trap, we
2937 * need to emulate the latter, either for the host or the
2938 * guest debugging itself.
2939 */
2940 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2941 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2942 kvm_run->debug.arch.dr7 = dr;
2943 kvm_run->debug.arch.pc =
2944 vmcs_readl(GUEST_CS_BASE) +
2945 vmcs_readl(GUEST_RIP);
2946 kvm_run->debug.arch.exception = DB_VECTOR;
2947 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2948 return 0;
2949 } else {
2950 vcpu->arch.dr7 &= ~DR7_GD;
2951 vcpu->arch.dr6 |= DR6_BD;
2952 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2953 kvm_queue_exception(vcpu, DB_VECTOR);
2954 return 1;
2955 }
2956 }
2957
bfdaab09 2958 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2959 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2960 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2961 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2962 switch (dr) {
42dbaa5a
JK		 2963 case 0 ... 3:
2964 val = vcpu->arch.db[dr];
2965 break;
6aa8b732 2966 case 6:
42dbaa5a 2967 val = vcpu->arch.dr6;
6aa8b732
AK		 2968 break;
2969 case 7:
42dbaa5a 2970 val = vcpu->arch.dr7;
6aa8b732
AK		 2971 break;
2972 default:
2973 val = 0;
2974 }
5fdbf976 2975 kvm_register_write(vcpu, reg, val);
6aa8b732 2976 } else {
42dbaa5a
JK		 2977 val = vcpu->arch.regs[reg];
2978 switch (dr) {
2979 case 0 ... 3:
2980 vcpu->arch.db[dr] = val;
2981 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2982 vcpu->arch.eff_db[dr] = val;
2983 break;
2984 case 4 ... 5:
2985 if (vcpu->arch.cr4 & X86_CR4_DE)
2986 kvm_queue_exception(vcpu, UD_VECTOR);
2987 break;
2988 case 6:
2989 if (val & 0xffffffff00000000ULL) {
2990 kvm_queue_exception(vcpu, GP_VECTOR);
2991 break;
2992 }
2993 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2994 break;
2995 case 7:
2996 if (val & 0xffffffff00000000ULL) {
2997 kvm_queue_exception(vcpu, GP_VECTOR);
2998 break;
2999 }
3000 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3001 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3002 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3003 vcpu->arch.switch_db_regs =
3004 (val & DR7_BP_EN_MASK);
3005 }
3006 break;
3007 }
6aa8b732 3008 }
6aa8b732
AK		 3009 skip_emulated_instruction(vcpu);
3010 return 1;
3011}
3012
3013static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3014{
06465c5a
AK		 3015 kvm_emulate_cpuid(vcpu);
3016 return 1;
6aa8b732
AK		 3017}
3018
3019static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3020{
ad312c7c 3021 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3022 u64 data;
3023
3024 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3025 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3026 return 1;
3027 }
3028
229456fc 3029 trace_kvm_msr_read(ecx, data);
2714d1d3 3030
6aa8b732 3031 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3032 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3033 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3034 skip_emulated_instruction(vcpu);
3035 return 1;
3036}
3037
3038static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3039{
ad312c7c
ZX		 3040 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3041 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3042 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3043
229456fc 3044 trace_kvm_msr_write(ecx, data);
2714d1d3 3045
6aa8b732 3046 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3047 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3048 return 1;
3049 }
3050
3051 skip_emulated_instruction(vcpu);
3052 return 1;
3053}
3054
6e5d865c
YS		 3055static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
3056 struct kvm_run *kvm_run)
3057{
3058 return 1;
3059}
3060
6aa8b732
AK		 3061static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3062 struct kvm_run *kvm_run)
3063{
85f455f7
ED		 3064 u32 cpu_based_vm_exec_control;
3065
3066 /* clear pending irq */
3067 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3068 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3069 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3070
a26bf12a 3071 ++vcpu->stat.irq_window_exits;
2714d1d3 3072
c1150d8c
DL		 3073 /*
3074 * If the user space waits to inject interrupts, exit as soon as
3075 * possible
3076 */
8061823a
GN		 3077 if (!irqchip_in_kernel(vcpu->kvm) &&
3078 kvm_run->request_interrupt_window &&
3079 !kvm_cpu_has_interrupt(vcpu)) {
c1150d8c 3080 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3081 return 0;
3082 }
6aa8b732
AK		 3083 return 1;
3084}
3085
3086static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3087{
3088 skip_emulated_instruction(vcpu);
d3bef15f 3089 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3090}
3091
c21415e8
IM		 3092static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3093{
510043da 3094 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3095 kvm_emulate_hypercall(vcpu);
3096 return 1;
c21415e8
IM		 3097}
3098
e3c7cb6a
AK		 3099static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3100{
3101 kvm_queue_exception(vcpu, UD_VECTOR);
3102 return 1;
3103}
3104
a7052897
MT		 3105static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3106{
f9c617f6 3107 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3108
3109 kvm_mmu_invlpg(vcpu, exit_qualification);
3110 skip_emulated_instruction(vcpu);
3111 return 1;
3112}
3113
e5edaa01
ED		 3114static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3115{
3116 skip_emulated_instruction(vcpu);
3117 /* TODO: Add support for VT-d/pass-through device */
3118 return 1;
3119}
3120
f78e0e2e
SY		 3121static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3122{
f9c617f6 3123 unsigned long exit_qualification;
f78e0e2e
SY		 3124 enum emulation_result er;
3125 unsigned long offset;
3126
f9c617f6 3127 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3128 offset = exit_qualification & 0xffful;
3129
3130 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3131
3132 if (er != EMULATE_DONE) {
3133 printk(KERN_ERR
3134 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3135 offset);
7f582ab6 3136 return -ENOEXEC;
f78e0e2e
SY		 3137 }
3138 return 1;
3139}
3140
37817f29
IE		 3141static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3142{
60637aac 3143 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3144 unsigned long exit_qualification;
3145 u16 tss_selector;
64a7ec06
GN		 3146 int reason, type, idt_v;
3147
3148 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3149 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3150
3151 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3152
3153 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3154 if (reason == TASK_SWITCH_GATE && idt_v) {
3155 switch (type) {
3156 case INTR_TYPE_NMI_INTR:
3157 vcpu->arch.nmi_injected = false;
3158 if (cpu_has_virtual_nmis())
3159 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3160 GUEST_INTR_STATE_NMI);
3161 break;
3162 case INTR_TYPE_EXT_INTR:
66fd3f7f 3163 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3164 kvm_clear_interrupt_queue(vcpu);
3165 break;
3166 case INTR_TYPE_HARD_EXCEPTION:
3167 case INTR_TYPE_SOFT_EXCEPTION:
3168 kvm_clear_exception_queue(vcpu);
3169 break;
3170 default:
3171 break;
3172 }
60637aac 3173 }
37817f29
IE		 3174 tss_selector = exit_qualification;
3175
64a7ec06
GN		 3176 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3177 type != INTR_TYPE_EXT_INTR &&
3178 type != INTR_TYPE_NMI_INTR))
3179 skip_emulated_instruction(vcpu);
3180
42dbaa5a
JK		 3181 if (!kvm_task_switch(vcpu, tss_selector, reason))
3182 return 0;
3183
3184 /* clear all local breakpoint enable flags */
3185 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3186
3187 /*
3188 * TODO: What about debug traps on tss switch?
3189 * Are we supposed to inject them and update dr6?
3190 */
3191
3192 return 1;
37817f29
IE		 3193}
3194
1439442c
SY		 3195static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3196{
f9c617f6 3197 unsigned long exit_qualification;
1439442c 3198 gpa_t gpa;
1439442c 3199 int gla_validity;
1439442c 3200
f9c617f6 3201 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3202
3203 if (exit_qualification & (1 << 6)) {
3204 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3205 return -EINVAL;
1439442c
SY		 3206 }
3207
3208 gla_validity = (exit_qualification >> 7) & 0x3;
3209 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3210 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3211 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3212 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3213 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3214 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3215 (long unsigned int)exit_qualification);
3216 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
596ae895
AK		 3217 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3218 return 0;
1439442c
SY		 3219 }
3220
3221 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3222 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3223 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3224}
3225
68f89400
MT		 3226static u64 ept_rsvd_mask(u64 spte, int level)
3227{
3228 int i;
3229 u64 mask = 0;
3230
3231 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3232 mask |= (1ULL << i);
3233
3234 if (level > 2)
3235 /* bits 7:3 reserved */
3236 mask |= 0xf8;
3237 else if (level == 2) {
3238 if (spte & (1ULL << 7))
3239 /* 2MB ref, bits 20:12 reserved */
3240 mask |= 0x1ff000;
3241 else
3242 /* bits 6:3 reserved */
3243 mask |= 0x78;
3244 }
3245
3246 return mask;
3247}
3248
3249static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3250 int level)
3251{
3252 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3253
3254 /* 010b (write-only) */
3255 WARN_ON((spte & 0x7) == 0x2);
3256
3257 /* 110b (write/execute) */
3258 WARN_ON((spte & 0x7) == 0x6);
3259
3260 /* 100b (execute-only) and value not supported by logical processor */
3261 if (!cpu_has_vmx_ept_execute_only())
3262 WARN_ON((spte & 0x7) == 0x4);
3263
3264 /* not 000b */
3265 if ((spte & 0x7)) {
3266 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3267
3268 if (rsvd_bits != 0) {
3269 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3270 __func__, rsvd_bits);
3271 WARN_ON(1);
3272 }
3273
3274 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3275 u64 ept_mem_type = (spte & 0x38) >> 3;
3276
3277 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3278 ept_mem_type == 7) {
3279 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3280 __func__, ept_mem_type);
3281 WARN_ON(1);
3282 }
3283 }
3284 }
3285}
3286
3287static int handle_ept_misconfig(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3288{
3289 u64 sptes[4];
3290 int nr_sptes, i;
3291 gpa_t gpa;
3292
3293 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3294
3295 printk(KERN_ERR "EPT: Misconfiguration.\n");
3296 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3297
3298 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3299
3300 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3301 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3302
3303 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3304 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3305
3306 return 0;
3307}
3308
f08864b4
SY		 3309static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3310{
3311 u32 cpu_based_vm_exec_control;
3312
3313 /* clear pending NMI */
3314 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3315 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3316 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3317 ++vcpu->stat.nmi_window_exits;
3318
3319 return 1;
3320}
3321
ea953ef0
MG		 3322static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3323 struct kvm_run *kvm_run)
3324{
8b3079a5
AK		 3325 struct vcpu_vmx *vmx = to_vmx(vcpu);
3326 enum emulation_result err = EMULATE_DONE;
ea953ef0 3327
ea953ef0 3328 local_irq_enable();
34f0c1ad 3329 preempt_enable();
ea953ef0
MG		 3330
3331 while (!guest_state_valid(vcpu)) {
3332 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3333
1d5a4d9b
GT		 3334 if (err == EMULATE_DO_MMIO)
3335 break;
3336
3337 if (err != EMULATE_DONE) {
3338 kvm_report_emulation_failure(vcpu, "emulation failure");
263799a3 3339 break;
ea953ef0
MG		 3340 }
3341
3342 if (signal_pending(current))
3343 break;
3344 if (need_resched())
3345 schedule();
3346 }
3347
ea953ef0 3348 preempt_disable();
34f0c1ad 3349 local_irq_disable();
8b3079a5
AK		 3350
3351 vmx->invalid_state_emulation_result = err;
ea953ef0
MG		 3352}
3353
6aa8b732
AK		 3354/*
3355 * The exit handlers return 1 if the exit was handled fully and guest execution
3356 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3357 * to be done to userspace and return 0.
3358 */
3359static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3360 struct kvm_run *kvm_run) = {
3361 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3362 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3363 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3364 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3365 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3366 [EXIT_REASON_CR_ACCESS] = handle_cr,
3367 [EXIT_REASON_DR_ACCESS] = handle_dr,
3368 [EXIT_REASON_CPUID] = handle_cpuid,
3369 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3370 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3371 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3372 [EXIT_REASON_HLT] = handle_halt,
a7052897 3373 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3374 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3375 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3376 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3377 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3378 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3379 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3380 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3381 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3382 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3383 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3384 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3385 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3386 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3387 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3388 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3389 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3390 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
6aa8b732
AK		 3391};
3392
3393static const int kvm_vmx_max_exit_handlers =
50a3485c 3394 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3395
3396/*
3397 * The guest has exited. See if we can fix it or if we need userspace
3398 * assistance.
3399 */
6062d012 3400static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 3401{
29bd8a78 3402 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3403 u32 exit_reason = vmx->exit_reason;
1155f76a 3404 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3405
229456fc 3406 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3407
1d5a4d9b
GT		 3408 /* If we need to emulate an MMIO from handle_invalid_guest_state
3409 * we just return 0 */
10f32d84
AK		 3410 if (vmx->emulation_required && emulate_invalid_guest_state) {
3411 if (guest_state_valid(vcpu))
3412 vmx->emulation_required = 0;
8b3079a5 3413 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
10f32d84 3414 }
1d5a4d9b 3415
1439442c
SY		 3416 /* Access CR3 don't cause VMExit in paging mode, so we need
3417 * to sync with guest real CR3. */
6de4f3ad 3418 if (enable_ept && is_paging(vcpu))
1439442c 3419 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3420
29bd8a78
AK		 3421 if (unlikely(vmx->fail)) {
3422 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3423 kvm_run->fail_entry.hardware_entry_failure_reason
3424 = vmcs_read32(VM_INSTRUCTION_ERROR);
3425 return 0;
3426 }
6aa8b732 3427
d77c26fc 3428 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3429 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3430 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3431 exit_reason != EXIT_REASON_TASK_SWITCH))
3432 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3433 "(0x%x) and exit reason is 0x%x\n",
3434 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3435
3436 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3437 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3438 vmx->soft_vnmi_blocked = 0;
3b86cd99 3439 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3440 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3441 /*
3442 * This CPU don't support us in finding the end of an
3443 * NMI-blocked window if the guest runs with IRQs
3444 * disabled. So we pull the trigger after 1 s of
3445 * futile waiting, but inform the user about this.
3446 */
3447 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3448 "state on VCPU %d after 1 s timeout\n",
3449 __func__, vcpu->vcpu_id);
3450 vmx->soft_vnmi_blocked = 0;
3b86cd99 3451 }
3b86cd99
JK		 3452 }
3453
6aa8b732
AK		 3454 if (exit_reason < kvm_vmx_max_exit_handlers
3455 && kvm_vmx_exit_handlers[exit_reason])
3456 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3457 else {
3458 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3459 kvm_run->hw.hardware_exit_reason = exit_reason;
3460 }
3461 return 0;
3462}
3463
95ba8273 3464static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3465{
95ba8273 3466 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3467 vmcs_write32(TPR_THRESHOLD, 0);
3468 return;
3469 }
3470
95ba8273 3471 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3472}
3473
cf393f75
AK		 3474static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3475{
3476 u32 exit_intr_info;
7b4a25cb 3477 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3478 bool unblock_nmi;
3479 u8 vector;
668f612f
AK		 3480 int type;
3481 bool idtv_info_valid;
cf393f75
AK		 3482
3483 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3484
a0861c02
AK		 3485 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3486
3487 /* Handle machine checks before interrupts are enabled */
3488 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3489 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3490 && is_machine_check(exit_intr_info)))
3491 kvm_machine_check();
3492
20f65983
GN		 3493 /* We need to handle NMIs before interrupts are enabled */
3494 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3495 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3496 asm("int $2");
20f65983
GN		 3497
3498 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3499
cf393f75
AK		 3500 if (cpu_has_virtual_nmis()) {
3501 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3502 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3503 /*
7b4a25cb 3504 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3505 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3506 * a guest IRET fault.
7b4a25cb
GN		 3507 * SDM 3: 23.2.2 (September 2008)
3508 * Bit 12 is undefined in any of the following cases:
3509 * If the VM exit sets the valid bit in the IDT-vectoring
3510 * information field.
3511 * If the VM exit is due to a double fault.
cf393f75 3512 */
7b4a25cb
GN		 3513 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3514 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3515 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3516 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3517 } else if (unlikely(vmx->soft_vnmi_blocked))
3518 vmx->vnmi_blocked_time +=
3519 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3520
37b96e98
GN		 3521 vmx->vcpu.arch.nmi_injected = false;
3522 kvm_clear_exception_queue(&vmx->vcpu);
3523 kvm_clear_interrupt_queue(&vmx->vcpu);
3524
3525 if (!idtv_info_valid)
3526 return;
3527
668f612f
AK		 3528 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3529 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3530
64a7ec06 3531 switch (type) {
37b96e98
GN		 3532 case INTR_TYPE_NMI_INTR:
3533 vmx->vcpu.arch.nmi_injected = true;
668f612f 3534 /*
7b4a25cb 3535 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3536 * Clear bit "block by NMI" before VM entry if a NMI
3537 * delivery faulted.
668f612f 3538 */
37b96e98
GN		 3539 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3540 GUEST_INTR_STATE_NMI);
3541 break;
37b96e98 3542 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3543 vmx->vcpu.arch.event_exit_inst_len =
3544 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3545 /* fall through */
3546 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3547 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3548 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3549 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3550 } else
3551 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3552 break;
66fd3f7f
GN		 3553 case INTR_TYPE_SOFT_INTR:
3554 vmx->vcpu.arch.event_exit_inst_len =
3555 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3556 /* fall through */
37b96e98 3557 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3558 kvm_queue_interrupt(&vmx->vcpu, vector,
3559 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3560 break;
3561 default:
3562 break;
f7d9238f 3563 }
cf393f75
AK		 3564}
3565
9c8cba37
AK		 3566/*
3567 * Failure to inject an interrupt should give us the information
3568 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3569 * when fetching the interrupt redirection bitmap in the real-mode
3570 * tss, this doesn't happen. So we do it ourselves.
3571 */
3572static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3573{
3574 vmx->rmode.irq.pending = 0;
5fdbf976 3575 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3576 return;
5fdbf976 3577 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3578 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3579 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3580 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3581 return;
3582 }
3583 vmx->idt_vectoring_info =
3584 VECTORING_INFO_VALID_MASK
3585 | INTR_TYPE_EXT_INTR
3586 | vmx->rmode.irq.vector;
3587}
3588
c801949d
AK		 3589#ifdef CONFIG_X86_64
3590#define R "r"
3591#define Q "q"
3592#else
3593#define R "e"
3594#define Q "l"
3595#endif
3596
04d2cc77 3597static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3598{
a2fa3e9f 3599 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3600
8f5d549f
AK		 3601 if (enable_ept && is_paging(vcpu)) {
3602 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3603 ept_load_pdptrs(vcpu);
3604 }
3b86cd99
JK		 3605 /* Record the guest's net vcpu time for enforced NMI injections. */
3606 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3607 vmx->entry_time = ktime_get();
3608
a89a8fb9
MG		 3609 /* Handle invalid guest state instead of entering VMX */
3610 if (vmx->emulation_required && emulate_invalid_guest_state) {
3611 handle_invalid_guest_state(vcpu, kvm_run);
3612 return;
3613 }
3614
5fdbf976
MT		 3615 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3616 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3617 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3618 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3619
787ff736
GN		 3620 /* When single-stepping over STI and MOV SS, we must clear the
3621 * corresponding interruptibility bits in the guest state. Otherwise
3622 * vmentry fails as it then expects bit 14 (BS) in pending debug
3623 * exceptions being set, but that's not correct for the guest debugging
3624 * case. */
3625 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3626 vmx_set_interrupt_shadow(vcpu, 0);
3627
e6adf283
AK		 3628 /*
3629 * Loading guest fpu may have cleared host cr0.ts
3630 */
3631 vmcs_writel(HOST_CR0, read_cr0());
3632
42dbaa5a
JK		 3633 set_debugreg(vcpu->arch.dr6, 6);
3634
d77c26fc 3635 asm(
6aa8b732 3636 /* Store host registers */
c801949d
AK		 3637 "push %%"R"dx; push %%"R"bp;"
3638 "push %%"R"cx \n\t"
313dbd49
AK		 3639 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3640 "je 1f \n\t"
3641 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3642 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3643 "1: \n\t"
d3edefc0
AK		 3644 /* Reload cr2 if changed */
3645 "mov %c[cr2](%0), %%"R"ax \n\t"
3646 "mov %%cr2, %%"R"dx \n\t"
3647 "cmp %%"R"ax, %%"R"dx \n\t"
3648 "je 2f \n\t"
3649 "mov %%"R"ax, %%cr2 \n\t"
3650 "2: \n\t"
6aa8b732 3651 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3652 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3653 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3654 "mov %c[rax](%0), %%"R"ax \n\t"
3655 "mov %c[rbx](%0), %%"R"bx \n\t"
3656 "mov %c[rdx](%0), %%"R"dx \n\t"
3657 "mov %c[rsi](%0), %%"R"si \n\t"
3658 "mov %c[rdi](%0), %%"R"di \n\t"
3659 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3660#ifdef CONFIG_X86_64
e08aa78a
AK		 3661 "mov %c[r8](%0), %%r8 \n\t"
3662 "mov %c[r9](%0), %%r9 \n\t"
3663 "mov %c[r10](%0), %%r10 \n\t"
3664 "mov %c[r11](%0), %%r11 \n\t"
3665 "mov %c[r12](%0), %%r12 \n\t"
3666 "mov %c[r13](%0), %%r13 \n\t"
3667 "mov %c[r14](%0), %%r14 \n\t"
3668 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3669#endif
c801949d
AK		 3670 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3671
6aa8b732 3672 /* Enter guest mode */
cd2276a7 3673 "jne .Llaunched \n\t"
4ecac3fd 3674 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3675 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3676 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3677 ".Lkvm_vmx_return: "
6aa8b732 3678 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3679 "xchg %0, (%%"R"sp) \n\t"
3680 "mov %%"R"ax, %c[rax](%0) \n\t"
3681 "mov %%"R"bx, %c[rbx](%0) \n\t"
3682 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3683 "mov %%"R"dx, %c[rdx](%0) \n\t"
3684 "mov %%"R"si, %c[rsi](%0) \n\t"
3685 "mov %%"R"di, %c[rdi](%0) \n\t"
3686 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3687#ifdef CONFIG_X86_64
e08aa78a
AK		 3688 "mov %%r8, %c[r8](%0) \n\t"
3689 "mov %%r9, %c[r9](%0) \n\t"
3690 "mov %%r10, %c[r10](%0) \n\t"
3691 "mov %%r11, %c[r11](%0) \n\t"
3692 "mov %%r12, %c[r12](%0) \n\t"
3693 "mov %%r13, %c[r13](%0) \n\t"
3694 "mov %%r14, %c[r14](%0) \n\t"
3695 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3696#endif
c801949d
AK		 3697 "mov %%cr2, %%"R"ax \n\t"
3698 "mov %%"R"ax, %c[cr2](%0) \n\t"
3699
3700 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3701 "setbe %c[fail](%0) \n\t"
3702 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3703 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3704 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3705 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3706 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3707 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3708 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3709 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3710 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3711 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3712 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3713#ifdef CONFIG_X86_64
ad312c7c
ZX		 3714 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3715 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3716 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3717 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3718 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3719 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3720 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3721 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3722#endif
ad312c7c 3723 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3724 : "cc", "memory"
c801949d 3725 , R"bx", R"di", R"si"
c2036300 3726#ifdef CONFIG_X86_64
c2036300
LV		 3727 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3728#endif
3729 );
6aa8b732 3730
6de4f3ad
AK		 3731 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3732 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3733 vcpu->arch.regs_dirty = 0;
3734
42dbaa5a
JK		 3735 get_debugreg(vcpu->arch.dr6, 6);
3736
1155f76a 3737 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3738 if (vmx->rmode.irq.pending)
3739 fixup_rmode_irq(vmx);
1155f76a 3740
d77c26fc 3741 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3742 vmx->launched = 1;
1b6269db 3743
cf393f75 3744 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3745}
3746
c801949d
AK		 3747#undef R
3748#undef Q
3749
6aa8b732
AK		 3750static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3751{
a2fa3e9f
GH		 3752 struct vcpu_vmx *vmx = to_vmx(vcpu);
3753
3754 if (vmx->vmcs) {
543e4243 3755 vcpu_clear(vmx);
a2fa3e9f
GH		 3756 free_vmcs(vmx->vmcs);
3757 vmx->vmcs = NULL;
6aa8b732
AK		 3758 }
3759}
3760
3761static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3762{
fb3f0f51
RR		 3763 struct vcpu_vmx *vmx = to_vmx(vcpu);
3764
2384d2b3
SY		 3765 spin_lock(&vmx_vpid_lock);
3766 if (vmx->vpid != 0)
3767 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3768 spin_unlock(&vmx_vpid_lock);
6aa8b732 3769 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3770 kfree(vmx->host_msrs);
3771 kfree(vmx->guest_msrs);
3772 kvm_vcpu_uninit(vcpu);
a4770347 3773 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3774}
3775
fb3f0f51 3776static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3777{
fb3f0f51 3778 int err;
c16f862d 3779 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3780 int cpu;
6aa8b732 3781
a2fa3e9f 3782 if (!vmx)
fb3f0f51
RR		 3783 return ERR_PTR(-ENOMEM);
3784
2384d2b3
SY		 3785 allocate_vpid(vmx);
3786
fb3f0f51
RR		 3787 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3788 if (err)
3789 goto free_vcpu;
965b58a5 3790
a2fa3e9f 3791 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3792 if (!vmx->guest_msrs) {
3793 err = -ENOMEM;
3794 goto uninit_vcpu;
3795 }
965b58a5 3796
a2fa3e9f
GH		 3797 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3798 if (!vmx->host_msrs)
fb3f0f51 3799 goto free_guest_msrs;
965b58a5 3800
a2fa3e9f
GH		 3801 vmx->vmcs = alloc_vmcs();
3802 if (!vmx->vmcs)
fb3f0f51 3803 goto free_msrs;
a2fa3e9f
GH		 3804
3805 vmcs_clear(vmx->vmcs);
3806
15ad7146
AK		 3807 cpu = get_cpu();
3808 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3809 err = vmx_vcpu_setup(vmx);
fb3f0f51 3810 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3811 put_cpu();
fb3f0f51
RR		 3812 if (err)
3813 goto free_vmcs;
5e4a0b3c
MT		 3814 if (vm_need_virtualize_apic_accesses(kvm))
3815 if (alloc_apic_access_page(kvm) != 0)
3816 goto free_vmcs;
fb3f0f51 3817
b927a3ce
SY		 3818 if (enable_ept) {
3819 if (!kvm->arch.ept_identity_map_addr)
3820 kvm->arch.ept_identity_map_addr =
3821 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3822 if (alloc_identity_pagetable(kvm) != 0)
3823 goto free_vmcs;
b927a3ce 3824 }
b7ebfb05 3825
fb3f0f51
RR		 3826 return &vmx->vcpu;
3827
3828free_vmcs:
3829 free_vmcs(vmx->vmcs);
3830free_msrs:
3831 kfree(vmx->host_msrs);
3832free_guest_msrs:
3833 kfree(vmx->guest_msrs);
3834uninit_vcpu:
3835 kvm_vcpu_uninit(&vmx->vcpu);
3836free_vcpu:
a4770347 3837 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3838 return ERR_PTR(err);
6aa8b732
AK		 3839}
3840
002c7f7c
YS		 3841static void __init vmx_check_processor_compat(void *rtn)
3842{
3843 struct vmcs_config vmcs_conf;
3844
3845 *(int *)rtn = 0;
3846 if (setup_vmcs_config(&vmcs_conf) < 0)
3847 *(int *)rtn = -EIO;
3848 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3849 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3850 smp_processor_id());
3851 *(int *)rtn = -EIO;
3852 }
3853}
3854
67253af5
SY		 3855static int get_ept_level(void)
3856{
3857 return VMX_EPT_DEFAULT_GAW + 1;
3858}
3859
4b12f0de 3860static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3861{
4b12f0de
SY		 3862 u64 ret;
3863
522c68c4
SY		 3864 /* For VT-d and EPT combination
3865 * 1. MMIO: always map as UC
3866 * 2. EPT with VT-d:
3867 * a. VT-d without snooping control feature: can't guarantee the
3868 * result, try to trust guest.
3869 * b. VT-d with snooping control feature: snooping control feature of
3870 * VT-d engine can guarantee the cache correctness. Just set it
3871 * to WB to keep consistent with host. So the same as item 3.
3872 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3873 * consistent with host MTRR
3874 */
4b12f0de
SY		 3875 if (is_mmio)
3876 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3877 else if (vcpu->kvm->arch.iommu_domain &&
3878 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3879 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3880 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3881 else
522c68c4
SY		 3882 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3883 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3884
3885 return ret;
64d4d521
SY		 3886}
3887
229456fc
MT		 3888static const struct trace_print_flags vmx_exit_reasons_str[] = {
3889 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3890 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3891 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3892 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3893 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3894 { EXIT_REASON_CR_ACCESS, "cr_access" },
3895 { EXIT_REASON_DR_ACCESS, "dr_access" },
3896 { EXIT_REASON_CPUID, "cpuid" },
3897 { EXIT_REASON_MSR_READ, "rdmsr" },
3898 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3899 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3900 { EXIT_REASON_HLT, "halt" },
3901 { EXIT_REASON_INVLPG, "invlpg" },
3902 { EXIT_REASON_VMCALL, "hypercall" },
3903 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3904 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3905 { EXIT_REASON_WBINVD, "wbinvd" },
3906 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3907 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3908 { -1, NULL }
3909};
3910
344f414f
JR		 3911static bool vmx_gb_page_enable(void)
3912{
3913 return false;
3914}
3915
cbdd1bea 3916static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3917 .cpu_has_kvm_support = cpu_has_kvm_support,
3918 .disabled_by_bios = vmx_disabled_by_bios,
3919 .hardware_setup = hardware_setup,
3920 .hardware_unsetup = hardware_unsetup,
002c7f7c 3921 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3922 .hardware_enable = hardware_enable,
3923 .hardware_disable = hardware_disable,
04547156 3924 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3925
3926 .vcpu_create = vmx_create_vcpu,
3927 .vcpu_free = vmx_free_vcpu,
04d2cc77 3928 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3929
04d2cc77 3930 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3931 .vcpu_load = vmx_vcpu_load,
3932 .vcpu_put = vmx_vcpu_put,
3933
3934 .set_guest_debug = set_guest_debug,
3935 .get_msr = vmx_get_msr,
3936 .set_msr = vmx_set_msr,
3937 .get_segment_base = vmx_get_segment_base,
3938 .get_segment = vmx_get_segment,
3939 .set_segment = vmx_set_segment,
2e4d2653 3940 .get_cpl = vmx_get_cpl,
6aa8b732 3941 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3942 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3943 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3944 .set_cr3 = vmx_set_cr3,
3945 .set_cr4 = vmx_set_cr4,
6aa8b732 3946 .set_efer = vmx_set_efer,
6aa8b732
AK		 3947 .get_idt = vmx_get_idt,
3948 .set_idt = vmx_set_idt,
3949 .get_gdt = vmx_get_gdt,
3950 .set_gdt = vmx_set_gdt,
5fdbf976 3951 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3952 .get_rflags = vmx_get_rflags,
3953 .set_rflags = vmx_set_rflags,
3954
3955 .tlb_flush = vmx_flush_tlb,
6aa8b732 3956
6aa8b732 3957 .run = vmx_vcpu_run,
6062d012 3958 .handle_exit = vmx_handle_exit,
6aa8b732 3959 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3960 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3961 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 3962 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 3963 .set_irq = vmx_inject_irq,
95ba8273 3964 .set_nmi = vmx_inject_nmi,
298101da 3965 .queue_exception = vmx_queue_exception,
78646121 3966 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273
GN		 3967 .nmi_allowed = vmx_nmi_allowed,
3968 .enable_nmi_window = enable_nmi_window,
3969 .enable_irq_window = enable_irq_window,
3970 .update_cr8_intercept = update_cr8_intercept,
95ba8273 3971
cbc94022 3972 .set_tss_addr = vmx_set_tss_addr,
67253af5 3973 .get_tdp_level = get_ept_level,
4b12f0de 3974 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 3975
3976 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 3977 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 3978};
3979
3980static int __init vmx_init(void)
3981{
fdef3ad1
HQ		 3982 int r;
3983
3e7c73e9 3984 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3985 if (!vmx_io_bitmap_a)
3986 return -ENOMEM;
3987
3e7c73e9 3988 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3989 if (!vmx_io_bitmap_b) {
3990 r = -ENOMEM;
3991 goto out;
3992 }
3993
5897297b
AK		 3994 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3995 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 3996 r = -ENOMEM;
3997 goto out1;
3998 }
3999
5897297b
AK		 4000 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4001 if (!vmx_msr_bitmap_longmode) {
4002 r = -ENOMEM;
4003 goto out2;
4004 }
4005
fdef3ad1
HQ		 4006 /*
4007 * Allow direct access to the PC debug port (it is often used for I/O
4008 * delays, but the vmexits simply slow things down).
4009 */
3e7c73e9
AK		 4010 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4011 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4012
3e7c73e9 4013 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4014
5897297b
AK		 4015 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4016 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4017
2384d2b3
SY		 4018 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4019
cb498ea2 4020 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4021 if (r)
5897297b 4022 goto out3;
25c5f225 4023
5897297b
AK		 4024 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4025 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4026 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4027 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4028 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4029 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4030
089d034e 4031 if (enable_ept) {
1439442c 4032 bypass_guest_pf = 0;
5fdbcb9d 4033 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4034 VMX_EPT_WRITABLE_MASK);
534e38b4 4035 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4036 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4037 kvm_enable_tdp();
4038 } else
4039 kvm_disable_tdp();
1439442c 4040
c7addb90
AK		 4041 if (bypass_guest_pf)
4042 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4043
1439442c
SY		 4044 ept_sync_global();
4045
fdef3ad1
HQ		 4046 return 0;
4047
5897297b
AK		 4048out3:
4049 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4050out2:
5897297b 4051 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4052out1:
3e7c73e9 4053 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4054out:
3e7c73e9 4055 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4056 return r;
6aa8b732
AK		 4057}
4058
4059static void __exit vmx_exit(void)
4060{
5897297b
AK		 4061 free_page((unsigned long)vmx_msr_bitmap_legacy);
4062 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4063 free_page((unsigned long)vmx_io_bitmap_b);
4064 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4065
cb498ea2 4066 kvm_exit();
6aa8b732
AK		 4067}
4068
4069module_init(vmx_init)
4070module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)