projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: VMX: fix invalid cpu passed to smp_call_function_single
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
a27685c3 77static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
83287ea4
AK		 130extern const ulong vmx_return;
131
8bf00a52 132#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 133#define VMCS02_POOL_SIZE 1
61d2ef2c 134
a2fa3e9f
GH		 135struct vmcs {
136 u32 revision_id;
137 u32 abort;
138 char data[0];
139};
140
d462b819
NHE		 141/*
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
145 */
146struct loaded_vmcs {
147 struct vmcs *vmcs;
148 int cpu;
149 int launched;
150 struct list_head loaded_vmcss_on_cpu_link;
151};
152
26bb0981
AK		 153struct shared_msr_entry {
154 unsigned index;
155 u64 data;
d5696725 156 u64 mask;
26bb0981
AK		 157};
158
a9d30f33
NHE		 159/*
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 */
22bd0358 172typedef u64 natural_width;
a9d30f33
NHE		 173struct __packed vmcs12 {
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
176 */
177 u32 revision_id;
178 u32 abort;
22bd0358 179
27d6c865
NHE		 180 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding[7]; /* room for future expansion */
182
22bd0358
NHE		 183 u64 io_bitmap_a;
184 u64 io_bitmap_b;
185 u64 msr_bitmap;
186 u64 vm_exit_msr_store_addr;
187 u64 vm_exit_msr_load_addr;
188 u64 vm_entry_msr_load_addr;
189 u64 tsc_offset;
190 u64 virtual_apic_page_addr;
191 u64 apic_access_addr;
192 u64 ept_pointer;
193 u64 guest_physical_address;
194 u64 vmcs_link_pointer;
195 u64 guest_ia32_debugctl;
196 u64 guest_ia32_pat;
197 u64 guest_ia32_efer;
198 u64 guest_ia32_perf_global_ctrl;
199 u64 guest_pdptr0;
200 u64 guest_pdptr1;
201 u64 guest_pdptr2;
202 u64 guest_pdptr3;
203 u64 host_ia32_pat;
204 u64 host_ia32_efer;
205 u64 host_ia32_perf_global_ctrl;
206 u64 padding64[8]; /* room for future expansion */
207 /*
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
212 */
213 natural_width cr0_guest_host_mask;
214 natural_width cr4_guest_host_mask;
215 natural_width cr0_read_shadow;
216 natural_width cr4_read_shadow;
217 natural_width cr3_target_value0;
218 natural_width cr3_target_value1;
219 natural_width cr3_target_value2;
220 natural_width cr3_target_value3;
221 natural_width exit_qualification;
222 natural_width guest_linear_address;
223 natural_width guest_cr0;
224 natural_width guest_cr3;
225 natural_width guest_cr4;
226 natural_width guest_es_base;
227 natural_width guest_cs_base;
228 natural_width guest_ss_base;
229 natural_width guest_ds_base;
230 natural_width guest_fs_base;
231 natural_width guest_gs_base;
232 natural_width guest_ldtr_base;
233 natural_width guest_tr_base;
234 natural_width guest_gdtr_base;
235 natural_width guest_idtr_base;
236 natural_width guest_dr7;
237 natural_width guest_rsp;
238 natural_width guest_rip;
239 natural_width guest_rflags;
240 natural_width guest_pending_dbg_exceptions;
241 natural_width guest_sysenter_esp;
242 natural_width guest_sysenter_eip;
243 natural_width host_cr0;
244 natural_width host_cr3;
245 natural_width host_cr4;
246 natural_width host_fs_base;
247 natural_width host_gs_base;
248 natural_width host_tr_base;
249 natural_width host_gdtr_base;
250 natural_width host_idtr_base;
251 natural_width host_ia32_sysenter_esp;
252 natural_width host_ia32_sysenter_eip;
253 natural_width host_rsp;
254 natural_width host_rip;
255 natural_width paddingl[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control;
257 u32 cpu_based_vm_exec_control;
258 u32 exception_bitmap;
259 u32 page_fault_error_code_mask;
260 u32 page_fault_error_code_match;
261 u32 cr3_target_count;
262 u32 vm_exit_controls;
263 u32 vm_exit_msr_store_count;
264 u32 vm_exit_msr_load_count;
265 u32 vm_entry_controls;
266 u32 vm_entry_msr_load_count;
267 u32 vm_entry_intr_info_field;
268 u32 vm_entry_exception_error_code;
269 u32 vm_entry_instruction_len;
270 u32 tpr_threshold;
271 u32 secondary_vm_exec_control;
272 u32 vm_instruction_error;
273 u32 vm_exit_reason;
274 u32 vm_exit_intr_info;
275 u32 vm_exit_intr_error_code;
276 u32 idt_vectoring_info_field;
277 u32 idt_vectoring_error_code;
278 u32 vm_exit_instruction_len;
279 u32 vmx_instruction_info;
280 u32 guest_es_limit;
281 u32 guest_cs_limit;
282 u32 guest_ss_limit;
283 u32 guest_ds_limit;
284 u32 guest_fs_limit;
285 u32 guest_gs_limit;
286 u32 guest_ldtr_limit;
287 u32 guest_tr_limit;
288 u32 guest_gdtr_limit;
289 u32 guest_idtr_limit;
290 u32 guest_es_ar_bytes;
291 u32 guest_cs_ar_bytes;
292 u32 guest_ss_ar_bytes;
293 u32 guest_ds_ar_bytes;
294 u32 guest_fs_ar_bytes;
295 u32 guest_gs_ar_bytes;
296 u32 guest_ldtr_ar_bytes;
297 u32 guest_tr_ar_bytes;
298 u32 guest_interruptibility_info;
299 u32 guest_activity_state;
300 u32 guest_sysenter_cs;
301 u32 host_ia32_sysenter_cs;
302 u32 padding32[8]; /* room for future expansion */
303 u16 virtual_processor_id;
304 u16 guest_es_selector;
305 u16 guest_cs_selector;
306 u16 guest_ss_selector;
307 u16 guest_ds_selector;
308 u16 guest_fs_selector;
309 u16 guest_gs_selector;
310 u16 guest_ldtr_selector;
311 u16 guest_tr_selector;
312 u16 host_es_selector;
313 u16 host_cs_selector;
314 u16 host_ss_selector;
315 u16 host_ds_selector;
316 u16 host_fs_selector;
317 u16 host_gs_selector;
318 u16 host_tr_selector;
a9d30f33
NHE		 319};
320
321/*
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 */
326#define VMCS12_REVISION 0x11e57ed0
327
328/*
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
332 */
333#define VMCS12_SIZE 0x1000
334
ff2f6fe9
NHE		 335/* Used to remember the last vmcs02 used for some recently used vmcs12s */
336struct vmcs02_list {
337 struct list_head list;
338 gpa_t vmptr;
339 struct loaded_vmcs vmcs02;
340};
341
ec378aee
NHE		 342/*
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 */
346struct nested_vmx {
347 /* Has the level1 guest done vmxon? */
348 bool vmxon;
a9d30f33
NHE		 349
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 gpa_t current_vmptr;
352 /* The host-usable pointer to the above */
353 struct page *current_vmcs12_page;
354 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 355
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool;
358 int vmcs02_num;
fe3ef05c 359 u64 vmcs01_tsc_offset;
644d711a
NHE		 360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending;
fe3ef05c
NHE		 362 /*
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
365 */
366 struct page *apic_access_page;
ec378aee
NHE		 367};
368
a2fa3e9f 369struct vcpu_vmx {
fb3f0f51 370 struct kvm_vcpu vcpu;
313dbd49 371 unsigned long host_rsp;
29bd8a78 372 u8 fail;
69c73028 373 u8 cpl;
9d58b931 374 bool nmi_known_unmasked;
51aa01d1 375 u32 exit_intr_info;
1155f76a 376 u32 idt_vectoring_info;
6de12732 377 ulong rflags;
26bb0981 378 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 379 int nmsrs;
380 int save_nmsrs;
a2fa3e9f 381#ifdef CONFIG_X86_64
44ea2b17
AK		 382 u64 msr_host_kernel_gs_base;
383 u64 msr_guest_kernel_gs_base;
a2fa3e9f 384#endif
d462b819
NHE		 385 /*
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
389 */
390 struct loaded_vmcs vmcs01;
391 struct loaded_vmcs *loaded_vmcs;
392 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 393 struct msr_autoload {
394 unsigned nr;
395 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
396 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
397 } msr_autoload;
a2fa3e9f
GH		 398 struct {
399 int loaded;
400 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 401#ifdef CONFIG_X86_64
402 u16 ds_sel, es_sel;
403#endif
152d3f2f
LV		 404 int gs_ldt_reload_needed;
405 int fs_reload_needed;
d77c26fc 406 } host_state;
9c8cba37 407 struct {
7ffd92c5 408 int vm86_active;
78ac8b47 409 ulong save_rflags;
f5f7b2fe
AK		 410 struct kvm_segment segs[8];
411 } rmode;
412 struct {
413 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 414 struct kvm_save_segment {
415 u16 selector;
416 unsigned long base;
417 u32 limit;
418 u32 ar;
f5f7b2fe 419 } seg[8];
2fb92db1 420 } segment_cache;
2384d2b3 421 int vpid;
04fa4d32 422 bool emulation_required;
3b86cd99
JK		 423
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked;
426 ktime_t entry_time;
427 s64 vnmi_blocked_time;
a0861c02 428 u32 exit_reason;
4e47c7a6
SY		 429
430 bool rdtscp_enabled;
ec378aee
NHE		 431
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested;
a2fa3e9f
GH		 434};
435
2fb92db1
AK		 436enum segment_cache_field {
437 SEG_FIELD_SEL = 0,
438 SEG_FIELD_BASE = 1,
439 SEG_FIELD_LIMIT = 2,
440 SEG_FIELD_AR = 3,
441
442 SEG_FIELD_NR = 4
443};
444
a2fa3e9f
GH		 445static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
446{
fb3f0f51 447 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 448}
449
22bd0358
NHE		 450#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
454
772e0318 455static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 456 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
457 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
458 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
459 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
460 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
461 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
462 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
463 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
464 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
465 FIELD(HOST_ES_SELECTOR, host_es_selector),
466 FIELD(HOST_CS_SELECTOR, host_cs_selector),
467 FIELD(HOST_SS_SELECTOR, host_ss_selector),
468 FIELD(HOST_DS_SELECTOR, host_ds_selector),
469 FIELD(HOST_FS_SELECTOR, host_fs_selector),
470 FIELD(HOST_GS_SELECTOR, host_gs_selector),
471 FIELD(HOST_TR_SELECTOR, host_tr_selector),
472 FIELD64(IO_BITMAP_A, io_bitmap_a),
473 FIELD64(IO_BITMAP_B, io_bitmap_b),
474 FIELD64(MSR_BITMAP, msr_bitmap),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
478 FIELD64(TSC_OFFSET, tsc_offset),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
480 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
481 FIELD64(EPT_POINTER, ept_pointer),
482 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
483 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
484 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
485 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
486 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
488 FIELD64(GUEST_PDPTR0, guest_pdptr0),
489 FIELD64(GUEST_PDPTR1, guest_pdptr1),
490 FIELD64(GUEST_PDPTR2, guest_pdptr2),
491 FIELD64(GUEST_PDPTR3, guest_pdptr3),
492 FIELD64(HOST_IA32_PAT, host_ia32_pat),
493 FIELD64(HOST_IA32_EFER, host_ia32_efer),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
497 FIELD(EXCEPTION_BITMAP, exception_bitmap),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
500 FIELD(CR3_TARGET_COUNT, cr3_target_count),
501 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
502 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
504 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
509 FIELD(TPR_THRESHOLD, tpr_threshold),
510 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
511 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
512 FIELD(VM_EXIT_REASON, vm_exit_reason),
513 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
514 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
515 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
516 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
517 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
518 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
519 FIELD(GUEST_ES_LIMIT, guest_es_limit),
520 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
521 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
522 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
523 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
524 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
525 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
526 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
527 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
528 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
529 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
530 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
531 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
532 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
533 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
534 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
535 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
536 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
538 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
539 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
540 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
541 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
542 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
543 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
544 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
545 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
546 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
547 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
548 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
549 FIELD(EXIT_QUALIFICATION, exit_qualification),
550 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
551 FIELD(GUEST_CR0, guest_cr0),
552 FIELD(GUEST_CR3, guest_cr3),
553 FIELD(GUEST_CR4, guest_cr4),
554 FIELD(GUEST_ES_BASE, guest_es_base),
555 FIELD(GUEST_CS_BASE, guest_cs_base),
556 FIELD(GUEST_SS_BASE, guest_ss_base),
557 FIELD(GUEST_DS_BASE, guest_ds_base),
558 FIELD(GUEST_FS_BASE, guest_fs_base),
559 FIELD(GUEST_GS_BASE, guest_gs_base),
560 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
561 FIELD(GUEST_TR_BASE, guest_tr_base),
562 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
563 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
564 FIELD(GUEST_DR7, guest_dr7),
565 FIELD(GUEST_RSP, guest_rsp),
566 FIELD(GUEST_RIP, guest_rip),
567 FIELD(GUEST_RFLAGS, guest_rflags),
568 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
569 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
570 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
571 FIELD(HOST_CR0, host_cr0),
572 FIELD(HOST_CR3, host_cr3),
573 FIELD(HOST_CR4, host_cr4),
574 FIELD(HOST_FS_BASE, host_fs_base),
575 FIELD(HOST_GS_BASE, host_gs_base),
576 FIELD(HOST_TR_BASE, host_tr_base),
577 FIELD(HOST_GDTR_BASE, host_gdtr_base),
578 FIELD(HOST_IDTR_BASE, host_idtr_base),
579 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
580 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
581 FIELD(HOST_RSP, host_rsp),
582 FIELD(HOST_RIP, host_rip),
583};
584static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
585
586static inline short vmcs_field_to_offset(unsigned long field)
587{
588 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
589 return -1;
590 return vmcs_field_to_offset_table[field];
591}
592
a9d30f33
NHE		 593static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
594{
595 return to_vmx(vcpu)->nested.current_vmcs12;
596}
597
598static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
599{
600 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 601 if (is_error_page(page))
a9d30f33 602 return NULL;
32cad84f 603
a9d30f33
NHE		 604 return page;
605}
606
607static void nested_release_page(struct page *page)
608{
609 kvm_release_page_dirty(page);
610}
611
612static void nested_release_page_clean(struct page *page)
613{
614 kvm_release_page_clean(page);
615}
616
4e1096d2 617static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 618static void kvm_cpu_vmxon(u64 addr);
619static void kvm_cpu_vmxoff(void);
aff48baa 620static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 621static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 622static void vmx_set_segment(struct kvm_vcpu *vcpu,
623 struct kvm_segment *var, int seg);
624static void vmx_get_segment(struct kvm_vcpu *vcpu,
625 struct kvm_segment *var, int seg);
75880a01 626
6aa8b732
AK		 627static DEFINE_PER_CPU(struct vmcs *, vmxarea);
628static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 629/*
630 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
631 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 */
633static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 634static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 635
3e7c73e9
AK		 636static unsigned long *vmx_io_bitmap_a;
637static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 638static unsigned long *vmx_msr_bitmap_legacy;
639static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 640
110312c8 641static bool cpu_has_load_ia32_efer;
8bf00a52 642static bool cpu_has_load_perf_global_ctrl;
110312c8 643
2384d2b3
SY		 644static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
645static DEFINE_SPINLOCK(vmx_vpid_lock);
646
1c3d14fe 647static struct vmcs_config {
6aa8b732
AK		 648 int size;
649 int order;
650 u32 revision_id;
1c3d14fe
YS		 651 u32 pin_based_exec_ctrl;
652 u32 cpu_based_exec_ctrl;
f78e0e2e 653 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 654 u32 vmexit_ctrl;
655 u32 vmentry_ctrl;
656} vmcs_config;
6aa8b732 657
efff9e53 658static struct vmx_capability {
d56f546d
SY		 659 u32 ept;
660 u32 vpid;
661} vmx_capability;
662
6aa8b732
AK		 663#define VMX_SEGMENT_FIELD(seg) \
664 [VCPU_SREG_##seg] = { \
665 .selector = GUEST_##seg##_SELECTOR, \
666 .base = GUEST_##seg##_BASE, \
667 .limit = GUEST_##seg##_LIMIT, \
668 .ar_bytes = GUEST_##seg##_AR_BYTES, \
669 }
670
772e0318 671static const struct kvm_vmx_segment_field {
6aa8b732
AK		 672 unsigned selector;
673 unsigned base;
674 unsigned limit;
675 unsigned ar_bytes;
676} kvm_vmx_segment_fields[] = {
677 VMX_SEGMENT_FIELD(CS),
678 VMX_SEGMENT_FIELD(DS),
679 VMX_SEGMENT_FIELD(ES),
680 VMX_SEGMENT_FIELD(FS),
681 VMX_SEGMENT_FIELD(GS),
682 VMX_SEGMENT_FIELD(SS),
683 VMX_SEGMENT_FIELD(TR),
684 VMX_SEGMENT_FIELD(LDTR),
685};
686
26bb0981
AK		 687static u64 host_efer;
688
6de4f3ad
AK		 689static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
690
4d56c8a7 691/*
8c06585d 692 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 693 * away by decrementing the array size.
694 */
6aa8b732 695static const u32 vmx_msr_index[] = {
05b3e0c2 696#ifdef CONFIG_X86_64
44ea2b17 697 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 698#endif
8c06585d 699 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 700};
9d8f549d 701#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 702
31299944 703static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 704{
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
706 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 707 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 708}
709
31299944 710static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 711{
712 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
713 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 714 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 715}
716
31299944 717static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 718{
719 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
720 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 721 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 722}
723
31299944 724static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 725{
726 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
727 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
728}
729
31299944 730static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 731{
732 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
733 INTR_INFO_VALID_MASK)) ==
734 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
735}
736
31299944 737static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 738{
04547156 739 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 740}
741
31299944 742static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 743{
04547156 744 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 745}
746
31299944 747static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 748{
04547156 749 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 750}
751
31299944 752static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 753{
04547156
SY		 754 return vmcs_config.cpu_based_exec_ctrl &
755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 756}
757
774ead3a 758static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 759{
04547156
SY		 760 return vmcs_config.cpu_based_2nd_exec_ctrl &
761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
762}
763
764static inline bool cpu_has_vmx_flexpriority(void)
765{
766 return cpu_has_vmx_tpr_shadow() &&
767 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 768}
769
e799794e
MT		 770static inline bool cpu_has_vmx_ept_execute_only(void)
771{
31299944 772 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 773}
774
775static inline bool cpu_has_vmx_eptp_uncacheable(void)
776{
31299944 777 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 778}
779
780static inline bool cpu_has_vmx_eptp_writeback(void)
781{
31299944 782 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 783}
784
785static inline bool cpu_has_vmx_ept_2m_page(void)
786{
31299944 787 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 788}
789
878403b7
SY		 790static inline bool cpu_has_vmx_ept_1g_page(void)
791{
31299944 792 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 793}
794
4bc9b982
SY		 795static inline bool cpu_has_vmx_ept_4levels(void)
796{
797 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
798}
799
83c3a331
XH		 800static inline bool cpu_has_vmx_ept_ad_bits(void)
801{
802 return vmx_capability.ept & VMX_EPT_AD_BIT;
803}
804
31299944 805static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 806{
31299944 807 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 808}
809
31299944 810static inline bool cpu_has_vmx_invept_context(void)
d56f546d 811{
31299944 812 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 813}
814
31299944 815static inline bool cpu_has_vmx_invept_global(void)
d56f546d 816{
31299944 817 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 818}
819
518c8aee
GJ		 820static inline bool cpu_has_vmx_invvpid_single(void)
821{
822 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
823}
824
b9d762fa
GJ		 825static inline bool cpu_has_vmx_invvpid_global(void)
826{
827 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
828}
829
31299944 830static inline bool cpu_has_vmx_ept(void)
d56f546d 831{
04547156
SY		 832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 834}
835
31299944 836static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 837{
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_UNRESTRICTED_GUEST;
840}
841
31299944 842static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 843{
844 return vmcs_config.cpu_based_2nd_exec_ctrl &
845 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
846}
847
31299944 848static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 849{
6d3e435e 850 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 851}
852
31299944 853static inline bool cpu_has_vmx_vpid(void)
2384d2b3 854{
04547156
SY		 855 return vmcs_config.cpu_based_2nd_exec_ctrl &
856 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 857}
858
31299944 859static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 860{
861 return vmcs_config.cpu_based_2nd_exec_ctrl &
862 SECONDARY_EXEC_RDTSCP;
863}
864
ad756a16
MJ		 865static inline bool cpu_has_vmx_invpcid(void)
866{
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_ENABLE_INVPCID;
869}
870
31299944 871static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 872{
873 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
874}
875
f5f48ee1
SY		 876static inline bool cpu_has_vmx_wbinvd_exit(void)
877{
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_WBINVD_EXITING;
880}
881
04547156
SY		 882static inline bool report_flexpriority(void)
883{
884 return flexpriority_enabled;
885}
886
fe3ef05c
NHE		 887static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
888{
889 return vmcs12->cpu_based_vm_exec_control & bit;
890}
891
892static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
893{
894 return (vmcs12->cpu_based_vm_exec_control &
895 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
896 (vmcs12->secondary_vm_exec_control & bit);
897}
898
644d711a
NHE		 899static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
900 struct kvm_vcpu *vcpu)
901{
902 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
903}
904
905static inline bool is_exception(u32 intr_info)
906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
908 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
909}
910
911static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 912static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
913 struct vmcs12 *vmcs12,
914 u32 reason, unsigned long qualification);
915
8b9cf98c 916static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 917{
918 int i;
919
a2fa3e9f 920 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 921 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 922 return i;
923 return -1;
924}
925
2384d2b3
SY		 926static inline void __invvpid(int ext, u16 vpid, gva_t gva)
927{
928 struct {
929 u64 vpid : 16;
930 u64 rsvd : 48;
931 u64 gva;
932 } operand = { vpid, 0, gva };
933
4ecac3fd 934 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 935 /* CF==1 or ZF==1 --> rc = -1 */
936 "; ja 1f ; ud2 ; 1:"
937 : : "a"(&operand), "c"(ext) : "cc", "memory");
938}
939
1439442c
SY		 940static inline void __invept(int ext, u64 eptp, gpa_t gpa)
941{
942 struct {
943 u64 eptp, gpa;
944 } operand = {eptp, gpa};
945
4ecac3fd 946 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 947 /* CF==1 or ZF==1 --> rc = -1 */
948 "; ja 1f ; ud2 ; 1:\n"
949 : : "a" (&operand), "c" (ext) : "cc", "memory");
950}
951
26bb0981 952static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 953{
954 int i;
955
8b9cf98c 956 i = __find_msr_index(vmx, msr);
a75beee6 957 if (i >= 0)
a2fa3e9f 958 return &vmx->guest_msrs[i];
8b6d44c7 959 return NULL;
7725f0ba
AK		 960}
961
6aa8b732
AK		 962static void vmcs_clear(struct vmcs *vmcs)
963{
964 u64 phys_addr = __pa(vmcs);
965 u8 error;
966
4ecac3fd 967 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 968 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 969 : "cc", "memory");
970 if (error)
971 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
972 vmcs, phys_addr);
973}
974
d462b819
NHE		 975static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
976{
977 vmcs_clear(loaded_vmcs->vmcs);
978 loaded_vmcs->cpu = -1;
979 loaded_vmcs->launched = 0;
980}
981
7725b894
DX		 982static void vmcs_load(struct vmcs *vmcs)
983{
984 u64 phys_addr = __pa(vmcs);
985 u8 error;
986
987 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 988 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 989 : "cc", "memory");
990 if (error)
2844d849 991 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 992 vmcs, phys_addr);
993}
994
d462b819 995static void __loaded_vmcs_clear(void *arg)
6aa8b732 996{
d462b819 997 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 998 int cpu = raw_smp_processor_id();
6aa8b732 999
d462b819
NHE		 1000 if (loaded_vmcs->cpu != cpu)
1001 return; /* vcpu migration can race with cpu offline */
1002 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1003 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 1004 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1005 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 1006}
1007
d462b819 1008static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1009{
e6c7d321
XG		 1010 int cpu = loaded_vmcs->cpu;
1011
1012 if (cpu != -1)
1013 smp_call_function_single(cpu,
1014 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1015}
1016
1760dd49 1017static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1018{
1019 if (vmx->vpid == 0)
1020 return;
1021
518c8aee
GJ		 1022 if (cpu_has_vmx_invvpid_single())
1023 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1024}
1025
b9d762fa
GJ		 1026static inline void vpid_sync_vcpu_global(void)
1027{
1028 if (cpu_has_vmx_invvpid_global())
1029 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1030}
1031
1032static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1033{
1034 if (cpu_has_vmx_invvpid_single())
1760dd49 1035 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1036 else
1037 vpid_sync_vcpu_global();
1038}
1039
1439442c
SY		 1040static inline void ept_sync_global(void)
1041{
1042 if (cpu_has_vmx_invept_global())
1043 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1044}
1045
1046static inline void ept_sync_context(u64 eptp)
1047{
089d034e 1048 if (enable_ept) {
1439442c
SY		 1049 if (cpu_has_vmx_invept_context())
1050 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1051 else
1052 ept_sync_global();
1053 }
1054}
1055
1056static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1057{
089d034e 1058 if (enable_ept) {
1439442c
SY		 1059 if (cpu_has_vmx_invept_individual_addr())
1060 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1061 eptp, gpa);
1062 else
1063 ept_sync_context(eptp);
1064 }
1065}
1066
96304217 1067static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1068{
5e520e62 1069 unsigned long value;
6aa8b732 1070
5e520e62
AK		 1071 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1072 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1073 return value;
1074}
1075
96304217 1076static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1077{
1078 return vmcs_readl(field);
1079}
1080
96304217 1081static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1082{
1083 return vmcs_readl(field);
1084}
1085
96304217 1086static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1087{
05b3e0c2 1088#ifdef CONFIG_X86_64
6aa8b732
AK		 1089 return vmcs_readl(field);
1090#else
1091 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1092#endif
1093}
1094
e52de1b8
AK		 1095static noinline void vmwrite_error(unsigned long field, unsigned long value)
1096{
1097 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1098 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1099 dump_stack();
1100}
1101
6aa8b732
AK		 1102static void vmcs_writel(unsigned long field, unsigned long value)
1103{
1104 u8 error;
1105
4ecac3fd 1106 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1107 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1108 if (unlikely(error))
1109 vmwrite_error(field, value);
6aa8b732
AK		 1110}
1111
1112static void vmcs_write16(unsigned long field, u16 value)
1113{
1114 vmcs_writel(field, value);
1115}
1116
1117static void vmcs_write32(unsigned long field, u32 value)
1118{
1119 vmcs_writel(field, value);
1120}
1121
1122static void vmcs_write64(unsigned long field, u64 value)
1123{
6aa8b732 1124 vmcs_writel(field, value);
7682f2d0 1125#ifndef CONFIG_X86_64
6aa8b732
AK		 1126 asm volatile ("");
1127 vmcs_writel(field+1, value >> 32);
1128#endif
1129}
1130
2ab455cc
AL		 1131static void vmcs_clear_bits(unsigned long field, u32 mask)
1132{
1133 vmcs_writel(field, vmcs_readl(field) & ~mask);
1134}
1135
1136static void vmcs_set_bits(unsigned long field, u32 mask)
1137{
1138 vmcs_writel(field, vmcs_readl(field) | mask);
1139}
1140
2fb92db1
AK		 1141static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1142{
1143 vmx->segment_cache.bitmask = 0;
1144}
1145
1146static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1147 unsigned field)
1148{
1149 bool ret;
1150 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1151
1152 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1153 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1154 vmx->segment_cache.bitmask = 0;
1155 }
1156 ret = vmx->segment_cache.bitmask & mask;
1157 vmx->segment_cache.bitmask |= mask;
1158 return ret;
1159}
1160
1161static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1162{
1163 u16 *p = &vmx->segment_cache.seg[seg].selector;
1164
1165 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1166 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1167 return *p;
1168}
1169
1170static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1171{
1172 ulong *p = &vmx->segment_cache.seg[seg].base;
1173
1174 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1175 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1176 return *p;
1177}
1178
1179static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1180{
1181 u32 *p = &vmx->segment_cache.seg[seg].limit;
1182
1183 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1184 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1185 return *p;
1186}
1187
1188static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1189{
1190 u32 *p = &vmx->segment_cache.seg[seg].ar;
1191
1192 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1193 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1194 return *p;
1195}
1196
abd3f2d6
AK		 1197static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1198{
1199 u32 eb;
1200
fd7373cc
JK		 1201 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1202 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1203 if ((vcpu->guest_debug &
1204 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1205 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1206 eb |= 1u << BP_VECTOR;
7ffd92c5 1207 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1208 eb = ~0;
089d034e 1209 if (enable_ept)
1439442c 1210 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1211 if (vcpu->fpu_active)
1212 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1213
1214 /* When we are running a nested L2 guest and L1 specified for it a
1215 * certain exception bitmap, we must trap the same exceptions and pass
1216 * them to L1. When running L2, we will only handle the exceptions
1217 * specified above if L1 did not want them.
1218 */
1219 if (is_guest_mode(vcpu))
1220 eb |= get_vmcs12(vcpu)->exception_bitmap;
1221
abd3f2d6
AK		 1222 vmcs_write32(EXCEPTION_BITMAP, eb);
1223}
1224
8bf00a52
GN		 1225static void clear_atomic_switch_msr_special(unsigned long entry,
1226 unsigned long exit)
1227{
1228 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1229 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1230}
1231
61d2ef2c
AK		 1232static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1233{
1234 unsigned i;
1235 struct msr_autoload *m = &vmx->msr_autoload;
1236
8bf00a52
GN		 1237 switch (msr) {
1238 case MSR_EFER:
1239 if (cpu_has_load_ia32_efer) {
1240 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1241 VM_EXIT_LOAD_IA32_EFER);
1242 return;
1243 }
1244 break;
1245 case MSR_CORE_PERF_GLOBAL_CTRL:
1246 if (cpu_has_load_perf_global_ctrl) {
1247 clear_atomic_switch_msr_special(
1248 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1249 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1250 return;
1251 }
1252 break;
110312c8
AK		 1253 }
1254
61d2ef2c
AK		 1255 for (i = 0; i < m->nr; ++i)
1256 if (m->guest[i].index == msr)
1257 break;
1258
1259 if (i == m->nr)
1260 return;
1261 --m->nr;
1262 m->guest[i] = m->guest[m->nr];
1263 m->host[i] = m->host[m->nr];
1264 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1265 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1266}
1267
8bf00a52
GN		 1268static void add_atomic_switch_msr_special(unsigned long entry,
1269 unsigned long exit, unsigned long guest_val_vmcs,
1270 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1271{
1272 vmcs_write64(guest_val_vmcs, guest_val);
1273 vmcs_write64(host_val_vmcs, host_val);
1274 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1275 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1276}
1277
61d2ef2c
AK		 1278static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1279 u64 guest_val, u64 host_val)
1280{
1281 unsigned i;
1282 struct msr_autoload *m = &vmx->msr_autoload;
1283
8bf00a52
GN		 1284 switch (msr) {
1285 case MSR_EFER:
1286 if (cpu_has_load_ia32_efer) {
1287 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1288 VM_EXIT_LOAD_IA32_EFER,
1289 GUEST_IA32_EFER,
1290 HOST_IA32_EFER,
1291 guest_val, host_val);
1292 return;
1293 }
1294 break;
1295 case MSR_CORE_PERF_GLOBAL_CTRL:
1296 if (cpu_has_load_perf_global_ctrl) {
1297 add_atomic_switch_msr_special(
1298 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1299 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1300 GUEST_IA32_PERF_GLOBAL_CTRL,
1301 HOST_IA32_PERF_GLOBAL_CTRL,
1302 guest_val, host_val);
1303 return;
1304 }
1305 break;
110312c8
AK		 1306 }
1307
61d2ef2c
AK		 1308 for (i = 0; i < m->nr; ++i)
1309 if (m->guest[i].index == msr)
1310 break;
1311
e7fc6f93
GN		 1312 if (i == NR_AUTOLOAD_MSRS) {
1313 printk_once(KERN_WARNING"Not enough mst switch entries. "
1314 "Can't add msr %x\n", msr);
1315 return;
1316 } else if (i == m->nr) {
61d2ef2c
AK		 1317 ++m->nr;
1318 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1319 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1320 }
1321
1322 m->guest[i].index = msr;
1323 m->guest[i].value = guest_val;
1324 m->host[i].index = msr;
1325 m->host[i].value = host_val;
1326}
1327
33ed6329
AK		 1328static void reload_tss(void)
1329{
33ed6329
AK		 1330 /*
1331 * VT restores TR but not its size. Useless.
1332 */
d359192f 1333 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1334 struct desc_struct *descs;
33ed6329 1335
d359192f 1336 descs = (void *)gdt->address;
33ed6329
AK		 1337 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1338 load_TR_desc();
33ed6329
AK		 1339}
1340
92c0d900 1341static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1342{
3a34a881 1343 u64 guest_efer;
51c6cf66
AK		 1344 u64 ignore_bits;
1345
f6801dff 1346 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1347
51c6cf66 1348 /*
0fa06071 1349 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1350 * outside long mode
1351 */
1352 ignore_bits = EFER_NX | EFER_SCE;
1353#ifdef CONFIG_X86_64
1354 ignore_bits |= EFER_LMA | EFER_LME;
1355 /* SCE is meaningful only in long mode on Intel */
1356 if (guest_efer & EFER_LMA)
1357 ignore_bits &= ~(u64)EFER_SCE;
1358#endif
51c6cf66
AK		 1359 guest_efer &= ~ignore_bits;
1360 guest_efer |= host_efer & ignore_bits;
26bb0981 1361 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1362 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1363
1364 clear_atomic_switch_msr(vmx, MSR_EFER);
1365 /* On ept, can't emulate nx, and must switch nx atomically */
1366 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1367 guest_efer = vmx->vcpu.arch.efer;
1368 if (!(guest_efer & EFER_LMA))
1369 guest_efer &= ~EFER_LME;
1370 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1371 return false;
1372 }
1373
26bb0981 1374 return true;
51c6cf66
AK		 1375}
1376
2d49ec72
GN		 1377static unsigned long segment_base(u16 selector)
1378{
d359192f 1379 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1380 struct desc_struct *d;
1381 unsigned long table_base;
1382 unsigned long v;
1383
1384 if (!(selector & ~3))
1385 return 0;
1386
d359192f 1387 table_base = gdt->address;
2d49ec72
GN		 1388
1389 if (selector & 4) { /* from ldt */
1390 u16 ldt_selector = kvm_read_ldt();
1391
1392 if (!(ldt_selector & ~3))
1393 return 0;
1394
1395 table_base = segment_base(ldt_selector);
1396 }
1397 d = (struct desc_struct *)(table_base + (selector & ~7));
1398 v = get_desc_base(d);
1399#ifdef CONFIG_X86_64
1400 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1401 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1402#endif
1403 return v;
1404}
1405
1406static inline unsigned long kvm_read_tr_base(void)
1407{
1408 u16 tr;
1409 asm("str %0" : "=g"(tr));
1410 return segment_base(tr);
1411}
1412
04d2cc77 1413static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1414{
04d2cc77 1415 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1416 int i;
04d2cc77 1417
a2fa3e9f 1418 if (vmx->host_state.loaded)
33ed6329
AK		 1419 return;
1420
a2fa3e9f 1421 vmx->host_state.loaded = 1;
33ed6329
AK		 1422 /*
1423 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1424 * allow segment selectors with cpl > 0 or ti == 1.
1425 */
d6e88aec 1426 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1427 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1428 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1429 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1430 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1431 vmx->host_state.fs_reload_needed = 0;
1432 } else {
33ed6329 1433 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1434 vmx->host_state.fs_reload_needed = 1;
33ed6329 1435 }
9581d442 1436 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1437 if (!(vmx->host_state.gs_sel & 7))
1438 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1439 else {
1440 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1441 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1442 }
1443
b2da15ac
AK		 1444#ifdef CONFIG_X86_64
1445 savesegment(ds, vmx->host_state.ds_sel);
1446 savesegment(es, vmx->host_state.es_sel);
1447#endif
1448
33ed6329
AK		 1449#ifdef CONFIG_X86_64
1450 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1451 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1452#else
a2fa3e9f
GH		 1453 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1454 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1455#endif
707c0874
AK		 1456
1457#ifdef CONFIG_X86_64
c8770e7b
AK		 1458 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1459 if (is_long_mode(&vmx->vcpu))
44ea2b17 1460 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1461#endif
26bb0981
AK		 1462 for (i = 0; i < vmx->save_nmsrs; ++i)
1463 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1464 vmx->guest_msrs[i].data,
1465 vmx->guest_msrs[i].mask);
33ed6329
AK		 1466}
1467
a9b21b62 1468static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1469{
a2fa3e9f 1470 if (!vmx->host_state.loaded)
33ed6329
AK		 1471 return;
1472
e1beb1d3 1473 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1474 vmx->host_state.loaded = 0;
c8770e7b
AK		 1475#ifdef CONFIG_X86_64
1476 if (is_long_mode(&vmx->vcpu))
1477 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1478#endif
152d3f2f 1479 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1480 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1481#ifdef CONFIG_X86_64
9581d442 1482 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1483#else
1484 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1485#endif
33ed6329 1486 }
0a77fe4c
AK		 1487 if (vmx->host_state.fs_reload_needed)
1488 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1489#ifdef CONFIG_X86_64
1490 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1491 loadsegment(ds, vmx->host_state.ds_sel);
1492 loadsegment(es, vmx->host_state.es_sel);
1493 }
b2da15ac 1494#endif
152d3f2f 1495 reload_tss();
44ea2b17 1496#ifdef CONFIG_X86_64
c8770e7b 1497 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1498#endif
b1a74bf8
SS		 1499 /*
1500 * If the FPU is not active (through the host task or
1501 * the guest vcpu), then restore the cr0.TS bit.
1502 */
1503 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1504 stts();
3444d7da 1505 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1506}
1507
a9b21b62
AK		 1508static void vmx_load_host_state(struct vcpu_vmx *vmx)
1509{
1510 preempt_disable();
1511 __vmx_load_host_state(vmx);
1512 preempt_enable();
1513}
1514
6aa8b732
AK		 1515/*
1516 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1517 * vcpu mutex is already taken.
1518 */
15ad7146 1519static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1520{
a2fa3e9f 1521 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1522 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1523
4610c9cc
DX		 1524 if (!vmm_exclusive)
1525 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1526 else if (vmx->loaded_vmcs->cpu != cpu)
1527 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1528
d462b819
NHE		 1529 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1530 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1531 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1532 }
1533
d462b819 1534 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1535 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1536 unsigned long sysenter_esp;
1537
a8eeb04a 1538 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1539 local_irq_disable();
d462b819
NHE		 1540 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1541 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1542 local_irq_enable();
1543
6aa8b732
AK		 1544 /*
1545 * Linux uses per-cpu TSS and GDT, so set these when switching
1546 * processors.
1547 */
d6e88aec 1548 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1549 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1550
1551 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1552 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1553 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1554 }
6aa8b732
AK		 1555}
1556
1557static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1558{
a9b21b62 1559 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1560 if (!vmm_exclusive) {
d462b819
NHE		 1561 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1562 vcpu->cpu = -1;
4610c9cc
DX		 1563 kvm_cpu_vmxoff();
1564 }
6aa8b732
AK		 1565}
1566
5fd86fcf
AK		 1567static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1568{
81231c69
AK		 1569 ulong cr0;
1570
5fd86fcf
AK		 1571 if (vcpu->fpu_active)
1572 return;
1573 vcpu->fpu_active = 1;
81231c69
AK		 1574 cr0 = vmcs_readl(GUEST_CR0);
1575 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1576 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1577 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1578 update_exception_bitmap(vcpu);
edcafe3c 1579 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1580 if (is_guest_mode(vcpu))
1581 vcpu->arch.cr0_guest_owned_bits &=
1582 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1583 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1584}
1585
edcafe3c
AK		 1586static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1587
fe3ef05c
NHE		 1588/*
1589 * Return the cr0 value that a nested guest would read. This is a combination
1590 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1591 * its hypervisor (cr0_read_shadow).
1592 */
1593static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1594{
1595 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1596 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1597}
1598static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1599{
1600 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1601 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1602}
1603
5fd86fcf
AK		 1604static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1605{
36cf24e0
NHE		 1606 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1607 * set this *before* calling this function.
1608 */
edcafe3c 1609 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1610 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1611 update_exception_bitmap(vcpu);
edcafe3c
AK		 1612 vcpu->arch.cr0_guest_owned_bits = 0;
1613 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1614 if (is_guest_mode(vcpu)) {
1615 /*
1616 * L1's specified read shadow might not contain the TS bit,
1617 * so now that we turned on shadowing of this bit, we need to
1618 * set this bit of the shadow. Like in nested_vmx_run we need
1619 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1620 * up-to-date here because we just decached cr0.TS (and we'll
1621 * only update vmcs12->guest_cr0 on nested exit).
1622 */
1623 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1624 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1625 (vcpu->arch.cr0 & X86_CR0_TS);
1626 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1627 } else
1628 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1629}
1630
6aa8b732
AK		 1631static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1632{
78ac8b47 1633 unsigned long rflags, save_rflags;
345dcaa8 1634
6de12732
AK		 1635 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1636 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1637 rflags = vmcs_readl(GUEST_RFLAGS);
1638 if (to_vmx(vcpu)->rmode.vm86_active) {
1639 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1640 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1641 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1642 }
1643 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1644 }
6de12732 1645 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1646}
1647
1648static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1649{
6de12732 1650 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1651 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1652 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1653 if (to_vmx(vcpu)->rmode.vm86_active) {
1654 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1655 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1656 }
6aa8b732
AK		 1657 vmcs_writel(GUEST_RFLAGS, rflags);
1658}
1659
2809f5d2
GC		 1660static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1661{
1662 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1663 int ret = 0;
1664
1665 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1666 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1667 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1668 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1669
1670 return ret & mask;
1671}
1672
1673static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1674{
1675 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1676 u32 interruptibility = interruptibility_old;
1677
1678 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1679
48005f64 1680 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1681 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1682 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1683 interruptibility |= GUEST_INTR_STATE_STI;
1684
1685 if ((interruptibility != interruptibility_old))
1686 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1687}
1688
6aa8b732
AK		 1689static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1690{
1691 unsigned long rip;
6aa8b732 1692
5fdbf976 1693 rip = kvm_rip_read(vcpu);
6aa8b732 1694 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1695 kvm_rip_write(vcpu, rip);
6aa8b732 1696
2809f5d2
GC		 1697 /* skipping an emulated instruction also counts */
1698 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1699}
1700
0b6ac343
NHE		 1701/*
1702 * KVM wants to inject page-faults which it got to the guest. This function
1703 * checks whether in a nested guest, we need to inject them to L1 or L2.
1704 * This function assumes it is called with the exit reason in vmcs02 being
1705 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1706 * is running).
1707 */
1708static int nested_pf_handled(struct kvm_vcpu *vcpu)
1709{
1710 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1711
1712 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1713 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1714 return 0;
1715
1716 nested_vmx_vmexit(vcpu);
1717 return 1;
1718}
1719
298101da 1720static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1721 bool has_error_code, u32 error_code,
1722 bool reinject)
298101da 1723{
77ab6db0 1724 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1725 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1726
0b6ac343
NHE		 1727 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1728 nested_pf_handled(vcpu))
1729 return;
1730
8ab2d2e2 1731 if (has_error_code) {
77ab6db0 1732 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1733 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1734 }
77ab6db0 1735
7ffd92c5 1736 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1737 int inc_eip = 0;
1738 if (kvm_exception_is_soft(nr))
1739 inc_eip = vcpu->arch.event_exit_inst_len;
1740 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1741 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1742 return;
1743 }
1744
66fd3f7f
GN		 1745 if (kvm_exception_is_soft(nr)) {
1746 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1747 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1748 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1749 } else
1750 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1751
1752 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1753}
1754
4e47c7a6
SY		 1755static bool vmx_rdtscp_supported(void)
1756{
1757 return cpu_has_vmx_rdtscp();
1758}
1759
ad756a16
MJ		 1760static bool vmx_invpcid_supported(void)
1761{
1762 return cpu_has_vmx_invpcid() && enable_ept;
1763}
1764
a75beee6
ED		 1765/*
1766 * Swap MSR entry in host/guest MSR entry array.
1767 */
8b9cf98c 1768static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1769{
26bb0981 1770 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1771
1772 tmp = vmx->guest_msrs[to];
1773 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1774 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1775}
1776
e38aea3e
AK		 1777/*
1778 * Set up the vmcs to automatically save and restore system
1779 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1780 * mode, as fiddling with msrs is very expensive.
1781 */
8b9cf98c 1782static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1783{
26bb0981 1784 int save_nmsrs, index;
5897297b 1785 unsigned long *msr_bitmap;
e38aea3e 1786
a75beee6
ED		 1787 save_nmsrs = 0;
1788#ifdef CONFIG_X86_64
8b9cf98c 1789 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1790 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1791 if (index >= 0)
8b9cf98c
RR		 1792 move_msr_up(vmx, index, save_nmsrs++);
1793 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1794 if (index >= 0)
8b9cf98c
RR		 1795 move_msr_up(vmx, index, save_nmsrs++);
1796 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1797 if (index >= 0)
8b9cf98c 1798 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1799 index = __find_msr_index(vmx, MSR_TSC_AUX);
1800 if (index >= 0 && vmx->rdtscp_enabled)
1801 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1802 /*
8c06585d 1803 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1804 * if efer.sce is enabled.
1805 */
8c06585d 1806 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1807 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1808 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1809 }
1810#endif
92c0d900
AK		 1811 index = __find_msr_index(vmx, MSR_EFER);
1812 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1813 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1814
26bb0981 1815 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1816
1817 if (cpu_has_vmx_msr_bitmap()) {
1818 if (is_long_mode(&vmx->vcpu))
1819 msr_bitmap = vmx_msr_bitmap_longmode;
1820 else
1821 msr_bitmap = vmx_msr_bitmap_legacy;
1822
1823 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1824 }
e38aea3e
AK		 1825}
1826
6aa8b732
AK		 1827/*
1828 * reads and returns guest's timestamp counter "register"
1829 * guest_tsc = host_tsc + tsc_offset -- 21.3
1830 */
1831static u64 guest_read_tsc(void)
1832{
1833 u64 host_tsc, tsc_offset;
1834
1835 rdtscll(host_tsc);
1836 tsc_offset = vmcs_read64(TSC_OFFSET);
1837 return host_tsc + tsc_offset;
1838}
1839
d5c1785d
NHE		 1840/*
1841 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1842 * counter, even if a nested guest (L2) is currently running.
1843 */
886b470c 1844u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1845{
886b470c 1846 u64 tsc_offset;
d5c1785d 1847
d5c1785d
NHE		 1848 tsc_offset = is_guest_mode(vcpu) ?
1849 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1850 vmcs_read64(TSC_OFFSET);
1851 return host_tsc + tsc_offset;
1852}
1853
4051b188 1854/*
cc578287
ZA		 1855 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1856 * software catchup for faster rates on slower CPUs.
4051b188 1857 */
cc578287 1858static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1859{
cc578287
ZA		 1860 if (!scale)
1861 return;
1862
1863 if (user_tsc_khz > tsc_khz) {
1864 vcpu->arch.tsc_catchup = 1;
1865 vcpu->arch.tsc_always_catchup = 1;
1866 } else
1867 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1868}
1869
6aa8b732 1870/*
99e3e30a 1871 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1872 */
99e3e30a 1873static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1874{
27fc51b2 1875 if (is_guest_mode(vcpu)) {
7991825b 1876 /*
27fc51b2
NHE		 1877 * We're here if L1 chose not to trap WRMSR to TSC. According
1878 * to the spec, this should set L1's TSC; The offset that L1
1879 * set for L2 remains unchanged, and still needs to be added
1880 * to the newly set TSC to get L2's TSC.
7991825b 1881 */
27fc51b2
NHE		 1882 struct vmcs12 *vmcs12;
1883 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1884 /* recalculate vmcs02.TSC_OFFSET: */
1885 vmcs12 = get_vmcs12(vcpu);
1886 vmcs_write64(TSC_OFFSET, offset +
1887 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1888 vmcs12->tsc_offset : 0));
1889 } else {
1890 vmcs_write64(TSC_OFFSET, offset);
1891 }
6aa8b732
AK		 1892}
1893
f1e2b260 1894static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1895{
1896 u64 offset = vmcs_read64(TSC_OFFSET);
1897 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1898 if (is_guest_mode(vcpu)) {
1899 /* Even when running L2, the adjustment needs to apply to L1 */
1900 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1901 }
e48672fa
ZA		 1902}
1903
857e4099
JR		 1904static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1905{
1906 return target_tsc - native_read_tsc();
1907}
1908
801d3424
NHE		 1909static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1910{
1911 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1912 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1913}
1914
1915/*
1916 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1917 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1918 * all guests if the "nested" module option is off, and can also be disabled
1919 * for a single guest by disabling its VMX cpuid bit.
1920 */
1921static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1922{
1923 return nested && guest_cpuid_has_vmx(vcpu);
1924}
1925
b87a51ae
NHE		 1926/*
1927 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1928 * returned for the various VMX controls MSRs when nested VMX is enabled.
1929 * The same values should also be used to verify that vmcs12 control fields are
1930 * valid during nested entry from L1 to L2.
1931 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1932 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1933 * bit in the high half is on if the corresponding bit in the control field
1934 * may be on. See also vmx_control_verify().
1935 * TODO: allow these variables to be modified (downgraded) by module options
1936 * or other means.
1937 */
1938static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1939static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1940static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1941static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1942static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1943static __init void nested_vmx_setup_ctls_msrs(void)
1944{
1945 /*
1946 * Note that as a general rule, the high half of the MSRs (bits in
1947 * the control fields which may be 1) should be initialized by the
1948 * intersection of the underlying hardware's MSR (i.e., features which
1949 * can be supported) and the list of features we want to expose -
1950 * because they are known to be properly supported in our code.
1951 * Also, usually, the low half of the MSRs (bits which must be 1) can
1952 * be set to 0, meaning that L1 may turn off any of these bits. The
1953 * reason is that if one of these bits is necessary, it will appear
1954 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1955 * fields of vmcs01 and vmcs02, will turn these bits off - and
1956 * nested_vmx_exit_handled() will not pass related exits to L1.
1957 * These rules have exceptions below.
1958 */
1959
1960 /* pin-based controls */
1961 /*
1962 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1963 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1964 */
1965 nested_vmx_pinbased_ctls_low = 0x16 ;
1966 nested_vmx_pinbased_ctls_high = 0x16 |
1967 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1968 PIN_BASED_VIRTUAL_NMIS;
1969
1970 /* exit controls */
1971 nested_vmx_exit_ctls_low = 0;
b6f1250e 1972 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1973#ifdef CONFIG_X86_64
1974 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1975#else
1976 nested_vmx_exit_ctls_high = 0;
1977#endif
1978
1979 /* entry controls */
1980 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1981 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1982 nested_vmx_entry_ctls_low = 0;
1983 nested_vmx_entry_ctls_high &=
1984 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1985
1986 /* cpu-based controls */
1987 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1988 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1989 nested_vmx_procbased_ctls_low = 0;
1990 nested_vmx_procbased_ctls_high &=
1991 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1992 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1993 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1994 CPU_BASED_CR3_STORE_EXITING |
1995#ifdef CONFIG_X86_64
1996 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1997#endif
1998 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1999 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2000 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2001 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2002 /*
2003 * We can allow some features even when not supported by the
2004 * hardware. For example, L1 can specify an MSR bitmap - and we
2005 * can use it to avoid exits to L1 - even when L0 runs L2
2006 * without MSR bitmaps.
2007 */
2008 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2009
2010 /* secondary cpu-based controls */
2011 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2012 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2013 nested_vmx_secondary_ctls_low = 0;
2014 nested_vmx_secondary_ctls_high &=
2015 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2016}
2017
2018static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2019{
2020 /*
2021 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2022 */
2023 return ((control & high) | low) == control;
2024}
2025
2026static inline u64 vmx_control_msr(u32 low, u32 high)
2027{
2028 return low | ((u64)high << 32);
2029}
2030
2031/*
2032 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2033 * also let it use VMX-specific MSRs.
2034 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2035 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2036 * like all other MSRs).
2037 */
2038static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2039{
2040 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2041 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2042 /*
2043 * According to the spec, processors which do not support VMX
2044 * should throw a #GP(0) when VMX capability MSRs are read.
2045 */
2046 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2047 return 1;
2048 }
2049
2050 switch (msr_index) {
2051 case MSR_IA32_FEATURE_CONTROL:
2052 *pdata = 0;
2053 break;
2054 case MSR_IA32_VMX_BASIC:
2055 /*
2056 * This MSR reports some information about VMX support. We
2057 * should return information about the VMX we emulate for the
2058 * guest, and the VMCS structure we give it - not about the
2059 * VMX support of the underlying hardware.
2060 */
2061 *pdata = VMCS12_REVISION |
2062 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2063 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2064 break;
2065 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2066 case MSR_IA32_VMX_PINBASED_CTLS:
2067 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2068 nested_vmx_pinbased_ctls_high);
2069 break;
2070 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2071 case MSR_IA32_VMX_PROCBASED_CTLS:
2072 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2073 nested_vmx_procbased_ctls_high);
2074 break;
2075 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2076 case MSR_IA32_VMX_EXIT_CTLS:
2077 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2078 nested_vmx_exit_ctls_high);
2079 break;
2080 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2081 case MSR_IA32_VMX_ENTRY_CTLS:
2082 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2083 nested_vmx_entry_ctls_high);
2084 break;
2085 case MSR_IA32_VMX_MISC:
2086 *pdata = 0;
2087 break;
2088 /*
2089 * These MSRs specify bits which the guest must keep fixed (on or off)
2090 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2091 * We picked the standard core2 setting.
2092 */
2093#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2094#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2095 case MSR_IA32_VMX_CR0_FIXED0:
2096 *pdata = VMXON_CR0_ALWAYSON;
2097 break;
2098 case MSR_IA32_VMX_CR0_FIXED1:
2099 *pdata = -1ULL;
2100 break;
2101 case MSR_IA32_VMX_CR4_FIXED0:
2102 *pdata = VMXON_CR4_ALWAYSON;
2103 break;
2104 case MSR_IA32_VMX_CR4_FIXED1:
2105 *pdata = -1ULL;
2106 break;
2107 case MSR_IA32_VMX_VMCS_ENUM:
2108 *pdata = 0x1f;
2109 break;
2110 case MSR_IA32_VMX_PROCBASED_CTLS2:
2111 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2112 nested_vmx_secondary_ctls_high);
2113 break;
2114 case MSR_IA32_VMX_EPT_VPID_CAP:
2115 /* Currently, no nested ept or nested vpid */
2116 *pdata = 0;
2117 break;
2118 default:
2119 return 0;
2120 }
2121
2122 return 1;
2123}
2124
2125static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2126{
2127 if (!nested_vmx_allowed(vcpu))
2128 return 0;
2129
2130 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2131 /* TODO: the right thing. */
2132 return 1;
2133 /*
2134 * No need to treat VMX capability MSRs specially: If we don't handle
2135 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2136 */
2137 return 0;
2138}
2139
6aa8b732
AK		 2140/*
2141 * Reads an msr value (of 'msr_index') into 'pdata'.
2142 * Returns 0 on success, non-0 otherwise.
2143 * Assumes vcpu_load() was already called.
2144 */
2145static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2146{
2147 u64 data;
26bb0981 2148 struct shared_msr_entry *msr;
6aa8b732
AK		 2149
2150 if (!pdata) {
2151 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2152 return -EINVAL;
2153 }
2154
2155 switch (msr_index) {
05b3e0c2 2156#ifdef CONFIG_X86_64
6aa8b732
AK		 2157 case MSR_FS_BASE:
2158 data = vmcs_readl(GUEST_FS_BASE);
2159 break;
2160 case MSR_GS_BASE:
2161 data = vmcs_readl(GUEST_GS_BASE);
2162 break;
44ea2b17
AK		 2163 case MSR_KERNEL_GS_BASE:
2164 vmx_load_host_state(to_vmx(vcpu));
2165 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2166 break;
26bb0981 2167#endif
6aa8b732 2168 case MSR_EFER:
3bab1f5d 2169 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2170 case MSR_IA32_TSC:
6aa8b732
AK		 2171 data = guest_read_tsc();
2172 break;
2173 case MSR_IA32_SYSENTER_CS:
2174 data = vmcs_read32(GUEST_SYSENTER_CS);
2175 break;
2176 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2177 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2178 break;
2179 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2180 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2181 break;
4e47c7a6
SY		 2182 case MSR_TSC_AUX:
2183 if (!to_vmx(vcpu)->rdtscp_enabled)
2184 return 1;
2185 /* Otherwise falls through */
6aa8b732 2186 default:
b87a51ae
NHE		 2187 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2188 return 0;
8b9cf98c 2189 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2190 if (msr) {
2191 data = msr->data;
2192 break;
6aa8b732 2193 }
3bab1f5d 2194 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2195 }
2196
2197 *pdata = data;
2198 return 0;
2199}
2200
2201/*
2202 * Writes msr value into into the appropriate "register".
2203 * Returns 0 on success, non-0 otherwise.
2204 * Assumes vcpu_load() was already called.
2205 */
2206static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2207{
a2fa3e9f 2208 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2209 struct shared_msr_entry *msr;
2cc51560
ED		 2210 int ret = 0;
2211
6aa8b732 2212 switch (msr_index) {
3bab1f5d 2213 case MSR_EFER:
2cc51560 2214 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2215 break;
16175a79 2216#ifdef CONFIG_X86_64
6aa8b732 2217 case MSR_FS_BASE:
2fb92db1 2218 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2219 vmcs_writel(GUEST_FS_BASE, data);
2220 break;
2221 case MSR_GS_BASE:
2fb92db1 2222 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2223 vmcs_writel(GUEST_GS_BASE, data);
2224 break;
44ea2b17
AK		 2225 case MSR_KERNEL_GS_BASE:
2226 vmx_load_host_state(vmx);
2227 vmx->msr_guest_kernel_gs_base = data;
2228 break;
6aa8b732
AK		 2229#endif
2230 case MSR_IA32_SYSENTER_CS:
2231 vmcs_write32(GUEST_SYSENTER_CS, data);
2232 break;
2233 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2234 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2235 break;
2236 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2237 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2238 break;
af24a4e4 2239 case MSR_IA32_TSC:
99e3e30a 2240 kvm_write_tsc(vcpu, data);
6aa8b732 2241 break;
468d472f
SY		 2242 case MSR_IA32_CR_PAT:
2243 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2244 vmcs_write64(GUEST_IA32_PAT, data);
2245 vcpu->arch.pat = data;
2246 break;
2247 }
4e47c7a6
SY		 2248 ret = kvm_set_msr_common(vcpu, msr_index, data);
2249 break;
2250 case MSR_TSC_AUX:
2251 if (!vmx->rdtscp_enabled)
2252 return 1;
2253 /* Check reserved bit, higher 32 bits should be zero */
2254 if ((data >> 32) != 0)
2255 return 1;
2256 /* Otherwise falls through */
6aa8b732 2257 default:
b87a51ae
NHE		 2258 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2259 break;
8b9cf98c 2260 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2261 if (msr) {
2262 msr->data = data;
2225fd56
AK		 2263 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2264 preempt_disable();
9ee73970
AK		 2265 kvm_set_shared_msr(msr->index, msr->data,
2266 msr->mask);
2225fd56
AK		 2267 preempt_enable();
2268 }
3bab1f5d 2269 break;
6aa8b732 2270 }
2cc51560 2271 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2272 }
2273
2cc51560 2274 return ret;
6aa8b732
AK		 2275}
2276
5fdbf976 2277static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2278{
5fdbf976
MT		 2279 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2280 switch (reg) {
2281 case VCPU_REGS_RSP:
2282 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2283 break;
2284 case VCPU_REGS_RIP:
2285 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2286 break;
6de4f3ad
AK		 2287 case VCPU_EXREG_PDPTR:
2288 if (enable_ept)
2289 ept_save_pdptrs(vcpu);
2290 break;
5fdbf976
MT		 2291 default:
2292 break;
2293 }
6aa8b732
AK		 2294}
2295
6aa8b732
AK		 2296static __init int cpu_has_kvm_support(void)
2297{
6210e37b 2298 return cpu_has_vmx();
6aa8b732
AK		 2299}
2300
2301static __init int vmx_disabled_by_bios(void)
2302{
2303 u64 msr;
2304
2305 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2306 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2307 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2308 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2309 && tboot_enabled())
2310 return 1;
23f3e991 2311 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2312 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2313 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2314 && !tboot_enabled()) {
2315 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2316 "activate TXT before enabling KVM\n");
cafd6659 2317 return 1;
f9335afe 2318 }
23f3e991
JC		 2319 /* launched w/o TXT and VMX disabled */
2320 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2321 && !tboot_enabled())
2322 return 1;
cafd6659
SW		 2323 }
2324
2325 return 0;
6aa8b732
AK		 2326}
2327
7725b894
DX		 2328static void kvm_cpu_vmxon(u64 addr)
2329{
2330 asm volatile (ASM_VMX_VMXON_RAX
2331 : : "a"(&addr), "m"(addr)
2332 : "memory", "cc");
2333}
2334
10474ae8 2335static int hardware_enable(void *garbage)
6aa8b732
AK		 2336{
2337 int cpu = raw_smp_processor_id();
2338 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2339 u64 old, test_bits;
6aa8b732 2340
10474ae8
AG		 2341 if (read_cr4() & X86_CR4_VMXE)
2342 return -EBUSY;
2343
d462b819 2344 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2345 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2346
2347 test_bits = FEATURE_CONTROL_LOCKED;
2348 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2349 if (tboot_enabled())
2350 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2351
2352 if ((old & test_bits) != test_bits) {
6aa8b732 2353 /* enable and lock */
cafd6659
SW		 2354 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2355 }
66aee91a 2356 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2357
4610c9cc
DX		 2358 if (vmm_exclusive) {
2359 kvm_cpu_vmxon(phys_addr);
2360 ept_sync_global();
2361 }
10474ae8 2362
3444d7da
AK		 2363 store_gdt(&__get_cpu_var(host_gdt));
2364
10474ae8 2365 return 0;
6aa8b732
AK		 2366}
2367
d462b819 2368static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2369{
2370 int cpu = raw_smp_processor_id();
d462b819 2371 struct loaded_vmcs *v, *n;
543e4243 2372
d462b819
NHE		 2373 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2374 loaded_vmcss_on_cpu_link)
2375 __loaded_vmcs_clear(v);
543e4243
AK		 2376}
2377
710ff4a8
EH		 2378
2379/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2380 * tricks.
2381 */
2382static void kvm_cpu_vmxoff(void)
6aa8b732 2383{
4ecac3fd 2384 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2385}
2386
710ff4a8
EH		 2387static void hardware_disable(void *garbage)
2388{
4610c9cc 2389 if (vmm_exclusive) {
d462b819 2390 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2391 kvm_cpu_vmxoff();
2392 }
7725b894 2393 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2394}
2395
1c3d14fe 2396static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2397 u32 msr, u32 *result)
1c3d14fe
YS		 2398{
2399 u32 vmx_msr_low, vmx_msr_high;
2400 u32 ctl = ctl_min | ctl_opt;
2401
2402 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2403
2404 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2405 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2406
2407 /* Ensure minimum (required) set of control bits are supported. */
2408 if (ctl_min & ~ctl)
002c7f7c 2409 return -EIO;
1c3d14fe
YS		 2410
2411 *result = ctl;
2412 return 0;
2413}
2414
110312c8
AK		 2415static __init bool allow_1_setting(u32 msr, u32 ctl)
2416{
2417 u32 vmx_msr_low, vmx_msr_high;
2418
2419 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2420 return vmx_msr_high & ctl;
2421}
2422
002c7f7c 2423static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2424{
2425 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2426 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2427 u32 _pin_based_exec_control = 0;
2428 u32 _cpu_based_exec_control = 0;
f78e0e2e 2429 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2430 u32 _vmexit_control = 0;
2431 u32 _vmentry_control = 0;
2432
2433 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2434 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2435 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2436 &_pin_based_exec_control) < 0)
002c7f7c 2437 return -EIO;
1c3d14fe 2438
10166744 2439 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2440#ifdef CONFIG_X86_64
2441 CPU_BASED_CR8_LOAD_EXITING |
2442 CPU_BASED_CR8_STORE_EXITING |
2443#endif
d56f546d
SY		 2444 CPU_BASED_CR3_LOAD_EXITING |
2445 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2446 CPU_BASED_USE_IO_BITMAPS |
2447 CPU_BASED_MOV_DR_EXITING |
a7052897 2448 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2449 CPU_BASED_MWAIT_EXITING |
2450 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2451 CPU_BASED_INVLPG_EXITING |
2452 CPU_BASED_RDPMC_EXITING;
443381a8 2453
f78e0e2e 2454 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2455 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2456 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2457 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2458 &_cpu_based_exec_control) < 0)
002c7f7c 2459 return -EIO;
6e5d865c
YS		 2460#ifdef CONFIG_X86_64
2461 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2462 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2463 ~CPU_BASED_CR8_STORE_EXITING;
2464#endif
f78e0e2e 2465 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2466 min2 = 0;
2467 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2468 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2469 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2470 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2471 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2472 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2473 SECONDARY_EXEC_RDTSCP |
2474 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2475 if (adjust_vmx_controls(min2, opt2,
2476 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2477 &_cpu_based_2nd_exec_control) < 0)
2478 return -EIO;
2479 }
2480#ifndef CONFIG_X86_64
2481 if (!(_cpu_based_2nd_exec_control &
2482 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2483 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2484#endif
d56f546d 2485 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2486 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2487 enabled */
5fff7d27
GN		 2488 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2489 CPU_BASED_CR3_STORE_EXITING |
2490 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2491 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2492 vmx_capability.ept, vmx_capability.vpid);
2493 }
1c3d14fe
YS		 2494
2495 min = 0;
2496#ifdef CONFIG_X86_64
2497 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2498#endif
468d472f 2499 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2500 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2501 &_vmexit_control) < 0)
002c7f7c 2502 return -EIO;
1c3d14fe 2503
468d472f
SY		 2504 min = 0;
2505 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2506 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2507 &_vmentry_control) < 0)
002c7f7c 2508 return -EIO;
6aa8b732 2509
c68876fd 2510 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2511
2512 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2513 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2514 return -EIO;
1c3d14fe
YS		 2515
2516#ifdef CONFIG_X86_64
2517 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2518 if (vmx_msr_high & (1u<<16))
002c7f7c 2519 return -EIO;
1c3d14fe
YS		 2520#endif
2521
2522 /* Require Write-Back (WB) memory type for VMCS accesses. */
2523 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2524 return -EIO;
1c3d14fe 2525
002c7f7c
YS		 2526 vmcs_conf->size = vmx_msr_high & 0x1fff;
2527 vmcs_conf->order = get_order(vmcs_config.size);
2528 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2529
002c7f7c
YS		 2530 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2531 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2532 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2533 vmcs_conf->vmexit_ctrl = _vmexit_control;
2534 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2535
110312c8
AK		 2536 cpu_has_load_ia32_efer =
2537 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2538 VM_ENTRY_LOAD_IA32_EFER)
2539 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2540 VM_EXIT_LOAD_IA32_EFER);
2541
8bf00a52
GN		 2542 cpu_has_load_perf_global_ctrl =
2543 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2544 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2545 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2546 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2547
2548 /*
2549 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2550 * but due to arrata below it can't be used. Workaround is to use
2551 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2552 *
2553 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2554 *
2555 * AAK155 (model 26)
2556 * AAP115 (model 30)
2557 * AAT100 (model 37)
2558 * BC86,AAY89,BD102 (model 44)
2559 * BA97 (model 46)
2560 *
2561 */
2562 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2563 switch (boot_cpu_data.x86_model) {
2564 case 26:
2565 case 30:
2566 case 37:
2567 case 44:
2568 case 46:
2569 cpu_has_load_perf_global_ctrl = false;
2570 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2571 "does not work properly. Using workaround\n");
2572 break;
2573 default:
2574 break;
2575 }
2576 }
2577
1c3d14fe 2578 return 0;
c68876fd 2579}
6aa8b732
AK		 2580
2581static struct vmcs *alloc_vmcs_cpu(int cpu)
2582{
2583 int node = cpu_to_node(cpu);
2584 struct page *pages;
2585 struct vmcs *vmcs;
2586
6484eb3e 2587 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2588 if (!pages)
2589 return NULL;
2590 vmcs = page_address(pages);
1c3d14fe
YS		 2591 memset(vmcs, 0, vmcs_config.size);
2592 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2593 return vmcs;
2594}
2595
2596static struct vmcs *alloc_vmcs(void)
2597{
d3b2c338 2598 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2599}
2600
2601static void free_vmcs(struct vmcs *vmcs)
2602{
1c3d14fe 2603 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2604}
2605
d462b819
NHE		 2606/*
2607 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2608 */
2609static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2610{
2611 if (!loaded_vmcs->vmcs)
2612 return;
2613 loaded_vmcs_clear(loaded_vmcs);
2614 free_vmcs(loaded_vmcs->vmcs);
2615 loaded_vmcs->vmcs = NULL;
2616}
2617
39959588 2618static void free_kvm_area(void)
6aa8b732
AK		 2619{
2620 int cpu;
2621
3230bb47 2622 for_each_possible_cpu(cpu) {
6aa8b732 2623 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2624 per_cpu(vmxarea, cpu) = NULL;
2625 }
6aa8b732
AK		 2626}
2627
6aa8b732
AK		 2628static __init int alloc_kvm_area(void)
2629{
2630 int cpu;
2631
3230bb47 2632 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2633 struct vmcs *vmcs;
2634
2635 vmcs = alloc_vmcs_cpu(cpu);
2636 if (!vmcs) {
2637 free_kvm_area();
2638 return -ENOMEM;
2639 }
2640
2641 per_cpu(vmxarea, cpu) = vmcs;
2642 }
2643 return 0;
2644}
2645
2646static __init int hardware_setup(void)
2647{
002c7f7c
YS		 2648 if (setup_vmcs_config(&vmcs_config) < 0)
2649 return -EIO;
50a37eb4
JR		 2650
2651 if (boot_cpu_has(X86_FEATURE_NX))
2652 kvm_enable_efer_bits(EFER_NX);
2653
93ba03c2
SY		 2654 if (!cpu_has_vmx_vpid())
2655 enable_vpid = 0;
2656
4bc9b982
SY		 2657 if (!cpu_has_vmx_ept() ||
2658 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2659 enable_ept = 0;
3a624e29 2660 enable_unrestricted_guest = 0;
83c3a331 2661 enable_ept_ad_bits = 0;
3a624e29
NK		 2662 }
2663
83c3a331
XH		 2664 if (!cpu_has_vmx_ept_ad_bits())
2665 enable_ept_ad_bits = 0;
2666
3a624e29
NK		 2667 if (!cpu_has_vmx_unrestricted_guest())
2668 enable_unrestricted_guest = 0;
93ba03c2
SY		 2669
2670 if (!cpu_has_vmx_flexpriority())
2671 flexpriority_enabled = 0;
2672
95ba8273
GN		 2673 if (!cpu_has_vmx_tpr_shadow())
2674 kvm_x86_ops->update_cr8_intercept = NULL;
2675
54dee993
MT		 2676 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2677 kvm_disable_largepages();
2678
4b8d54f9
ZE		 2679 if (!cpu_has_vmx_ple())
2680 ple_gap = 0;
2681
b87a51ae
NHE		 2682 if (nested)
2683 nested_vmx_setup_ctls_msrs();
2684
6aa8b732
AK		 2685 return alloc_kvm_area();
2686}
2687
2688static __exit void hardware_unsetup(void)
2689{
2690 free_kvm_area();
2691}
2692
f5f7b2fe 2693static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
6aa8b732 2694{
772e0318 2695 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
c865c43d 2696 struct kvm_segment tmp = *save;
6aa8b732 2697
c865c43d
AK		 2698 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2699 tmp.base = vmcs_readl(sf->base);
2700 tmp.selector = vmcs_read16(sf->selector);
2701 tmp.s = 1;
6aa8b732 2702 }
c865c43d 2703 vmx_set_segment(vcpu, &tmp, seg);
6aa8b732
AK		 2704}
2705
2706static void enter_pmode(struct kvm_vcpu *vcpu)
2707{
2708 unsigned long flags;
a89a8fb9 2709 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2710
a89a8fb9 2711 vmx->emulation_required = 1;
7ffd92c5 2712 vmx->rmode.vm86_active = 0;
6aa8b732 2713
2fb92db1
AK		 2714 vmx_segment_cache_clear(vmx);
2715
f5f7b2fe 2716 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2717
2718 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2719 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2720 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2721 vmcs_writel(GUEST_RFLAGS, flags);
2722
66aee91a
RR		 2723 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2724 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2725
2726 update_exception_bitmap(vcpu);
2727
a89a8fb9
MG		 2728 if (emulate_invalid_guest_state)
2729 return;
2730
f5f7b2fe
AK		 2731 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2732 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2733 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2734 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732 2735
2fb92db1
AK		 2736 vmx_segment_cache_clear(vmx);
2737
6aa8b732
AK		 2738 vmcs_write16(GUEST_SS_SELECTOR, 0);
2739 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2740
2741 vmcs_write16(GUEST_CS_SELECTOR,
2742 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2743 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2744}
2745
d77c26fc 2746static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2747{
bfc6d222 2748 if (!kvm->arch.tss_addr) {
bc6678a3 2749 struct kvm_memslots *slots;
28a37544 2750 struct kvm_memory_slot *slot;
bc6678a3
MT		 2751 gfn_t base_gfn;
2752
90d83dc3 2753 slots = kvm_memslots(kvm);
28a37544
XG		 2754 slot = id_to_memslot(slots, 0);
2755 base_gfn = slot->base_gfn + slot->npages - 3;
2756
cbc94022
IE		 2757 return base_gfn << PAGE_SHIFT;
2758 }
bfc6d222 2759 return kvm->arch.tss_addr;
6aa8b732
AK		 2760}
2761
f5f7b2fe 2762static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2763{
772e0318 2764 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
6aa8b732 2765
15b00f32 2766 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2767 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2768 vmcs_write32(sf->limit, 0xffff);
2769 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2770 if (save->base & 0xf)
2771 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2772 " aligned when entering protected mode (seg=%d)",
2773 seg);
6aa8b732
AK		 2774}
2775
2776static void enter_rmode(struct kvm_vcpu *vcpu)
2777{
2778 unsigned long flags;
a89a8fb9 2779 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2780 struct kvm_segment var;
6aa8b732 2781
3a624e29
NK		 2782 if (enable_unrestricted_guest)
2783 return;
2784
f5f7b2fe
AK		 2785 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2786 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2787 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2788 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2789 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2790
a89a8fb9 2791 vmx->emulation_required = 1;
7ffd92c5 2792 vmx->rmode.vm86_active = 1;
6aa8b732 2793
baa7e81e 2794
776e58ea
GN		 2795 /*
2796 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2797 * vcpu. Call it here with phys address pointing 16M below 4G.
2798 */
2799 if (!vcpu->kvm->arch.tss_addr) {
2800 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2801 "called before entering vcpu\n");
2802 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2803 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2804 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2805 }
2806
2fb92db1
AK		 2807 vmx_segment_cache_clear(vmx);
2808
6aa8b732 2809 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2810 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2811 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2812
2813 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2814 vmx->rmode.save_rflags = flags;
6aa8b732 2815
053de044 2816 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2817
2818 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2819 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2820 update_exception_bitmap(vcpu);
2821
a89a8fb9
MG		 2822 if (emulate_invalid_guest_state)
2823 goto continue_rmode;
2824
b246dd5d
OW		 2825 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2826 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2827
2828 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2829 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2830
2831 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2832 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2833
2834 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2835 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2836
b246dd5d
OW		 2837 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2838 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2839
b246dd5d
OW		 2840 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2841 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2842
a89a8fb9 2843continue_rmode:
8668a3c4 2844 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2845}
2846
401d10de
AS		 2847static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2848{
2849 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2850 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2851
2852 if (!msr)
2853 return;
401d10de 2854
44ea2b17
AK		 2855 /*
2856 * Force kernel_gs_base reloading before EFER changes, as control
2857 * of this msr depends on is_long_mode().
2858 */
2859 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2860 vcpu->arch.efer = efer;
401d10de
AS		 2861 if (efer & EFER_LMA) {
2862 vmcs_write32(VM_ENTRY_CONTROLS,
2863 vmcs_read32(VM_ENTRY_CONTROLS) |
2864 VM_ENTRY_IA32E_MODE);
2865 msr->data = efer;
2866 } else {
2867 vmcs_write32(VM_ENTRY_CONTROLS,
2868 vmcs_read32(VM_ENTRY_CONTROLS) &
2869 ~VM_ENTRY_IA32E_MODE);
2870
2871 msr->data = efer & ~EFER_LME;
2872 }
2873 setup_msrs(vmx);
2874}
2875
05b3e0c2 2876#ifdef CONFIG_X86_64
6aa8b732
AK		 2877
2878static void enter_lmode(struct kvm_vcpu *vcpu)
2879{
2880 u32 guest_tr_ar;
2881
2fb92db1
AK		 2882 vmx_segment_cache_clear(to_vmx(vcpu));
2883
6aa8b732
AK		 2884 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2885 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2886 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2887 __func__);
6aa8b732
AK		 2888 vmcs_write32(GUEST_TR_AR_BYTES,
2889 (guest_tr_ar & ~AR_TYPE_MASK)
2890 | AR_TYPE_BUSY_64_TSS);
2891 }
da38f438 2892 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2893}
2894
2895static void exit_lmode(struct kvm_vcpu *vcpu)
2896{
6aa8b732
AK		 2897 vmcs_write32(VM_ENTRY_CONTROLS,
2898 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2899 & ~VM_ENTRY_IA32E_MODE);
da38f438 2900 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2901}
2902
2903#endif
2904
2384d2b3
SY		 2905static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2906{
b9d762fa 2907 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2908 if (enable_ept) {
2909 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2910 return;
4e1096d2 2911 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2912 }
2384d2b3
SY		 2913}
2914
e8467fda
AK		 2915static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2916{
2917 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2918
2919 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2920 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2921}
2922
aff48baa
AK		 2923static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2924{
2925 if (enable_ept && is_paging(vcpu))
2926 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2927 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2928}
2929
25c4c276 2930static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2931{
fc78f519
AK		 2932 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2933
2934 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2935 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2936}
2937
1439442c
SY		 2938static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2939{
6de4f3ad
AK		 2940 if (!test_bit(VCPU_EXREG_PDPTR,
2941 (unsigned long *)&vcpu->arch.regs_dirty))
2942 return;
2943
1439442c 2944 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2945 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2946 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2947 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2948 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2949 }
2950}
2951
8f5d549f
AK		 2952static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2953{
2954 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2955 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2956 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2957 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2958 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2959 }
6de4f3ad
AK		 2960
2961 __set_bit(VCPU_EXREG_PDPTR,
2962 (unsigned long *)&vcpu->arch.regs_avail);
2963 __set_bit(VCPU_EXREG_PDPTR,
2964 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2965}
2966
5e1746d6 2967static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2968
2969static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2970 unsigned long cr0,
2971 struct kvm_vcpu *vcpu)
2972{
5233dd51
MT		 2973 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2974 vmx_decache_cr3(vcpu);
1439442c
SY		 2975 if (!(cr0 & X86_CR0_PG)) {
2976 /* From paging/starting to nonpaging */
2977 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2978 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2979 (CPU_BASED_CR3_LOAD_EXITING |
2980 CPU_BASED_CR3_STORE_EXITING));
2981 vcpu->arch.cr0 = cr0;
fc78f519 2982 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2983 } else if (!is_paging(vcpu)) {
2984 /* From nonpaging to paging */
2985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2986 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2987 ~(CPU_BASED_CR3_LOAD_EXITING |
2988 CPU_BASED_CR3_STORE_EXITING));
2989 vcpu->arch.cr0 = cr0;
fc78f519 2990 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2991 }
95eb84a7
SY		 2992
2993 if (!(cr0 & X86_CR0_WP))
2994 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2995}
2996
6aa8b732
AK		 2997static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2998{
7ffd92c5 2999 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3000 unsigned long hw_cr0;
3001
3002 if (enable_unrestricted_guest)
3003 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3004 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3005 else
3006 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3007
7ffd92c5 3008 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3009 enter_pmode(vcpu);
3010
7ffd92c5 3011 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3012 enter_rmode(vcpu);
3013
05b3e0c2 3014#ifdef CONFIG_X86_64
f6801dff 3015 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3016 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3017 enter_lmode(vcpu);
707d92fa 3018 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3019 exit_lmode(vcpu);
3020 }
3021#endif
3022
089d034e 3023 if (enable_ept)
1439442c
SY		 3024 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3025
02daab21 3026 if (!vcpu->fpu_active)
81231c69 3027 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3028
6aa8b732 3029 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3030 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3031 vcpu->arch.cr0 = cr0;
69c73028 3032 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3033}
3034
1439442c
SY		 3035static u64 construct_eptp(unsigned long root_hpa)
3036{
3037 u64 eptp;
3038
3039 /* TODO write the value reading from MSR */
3040 eptp = VMX_EPT_DEFAULT_MT |
3041 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3042 if (enable_ept_ad_bits)
3043 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3044 eptp |= (root_hpa & PAGE_MASK);
3045
3046 return eptp;
3047}
3048
6aa8b732
AK		 3049static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3050{
1439442c
SY		 3051 unsigned long guest_cr3;
3052 u64 eptp;
3053
3054 guest_cr3 = cr3;
089d034e 3055 if (enable_ept) {
1439442c
SY		 3056 eptp = construct_eptp(cr3);
3057 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3058 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3059 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3060 ept_load_pdptrs(vcpu);
1439442c
SY		 3061 }
3062
2384d2b3 3063 vmx_flush_tlb(vcpu);
1439442c 3064 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3065}
3066
5e1746d6 3067static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3068{
7ffd92c5 3069 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3070 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3071
5e1746d6
NHE		 3072 if (cr4 & X86_CR4_VMXE) {
3073 /*
3074 * To use VMXON (and later other VMX instructions), a guest
3075 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3076 * So basically the check on whether to allow nested VMX
3077 * is here.
3078 */
3079 if (!nested_vmx_allowed(vcpu))
3080 return 1;
3081 } else if (to_vmx(vcpu)->nested.vmxon)
3082 return 1;
3083
ad312c7c 3084 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3085 if (enable_ept) {
3086 if (!is_paging(vcpu)) {
3087 hw_cr4 &= ~X86_CR4_PAE;
3088 hw_cr4 |= X86_CR4_PSE;
3089 } else if (!(cr4 & X86_CR4_PAE)) {
3090 hw_cr4 &= ~X86_CR4_PAE;
3091 }
3092 }
1439442c
SY		 3093
3094 vmcs_writel(CR4_READ_SHADOW, cr4);
3095 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3096 return 0;
6aa8b732
AK		 3097}
3098
6aa8b732
AK		 3099static void vmx_get_segment(struct kvm_vcpu *vcpu,
3100 struct kvm_segment *var, int seg)
3101{
a9179499 3102 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3103 u32 ar;
3104
a9179499
AK		 3105 if (vmx->rmode.vm86_active
3106 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3107 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
72636420 3108 || seg == VCPU_SREG_GS)) {
f5f7b2fe 3109 *var = vmx->rmode.segs[seg];
a9179499 3110 if (seg == VCPU_SREG_TR
2fb92db1 3111 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3112 return;
1390a28b
AK		 3113 var->base = vmx_read_guest_seg_base(vmx, seg);
3114 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3115 return;
a9179499 3116 }
2fb92db1
AK		 3117 var->base = vmx_read_guest_seg_base(vmx, seg);
3118 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3119 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3120 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3121 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3122 ar = 0;
3123 var->type = ar & 15;
3124 var->s = (ar >> 4) & 1;
3125 var->dpl = (ar >> 5) & 3;
3126 var->present = (ar >> 7) & 1;
3127 var->avl = (ar >> 12) & 1;
3128 var->l = (ar >> 13) & 1;
3129 var->db = (ar >> 14) & 1;
3130 var->g = (ar >> 15) & 1;
3131 var->unusable = (ar >> 16) & 1;
3132}
3133
a9179499
AK		 3134static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3135{
a9179499
AK		 3136 struct kvm_segment s;
3137
3138 if (to_vmx(vcpu)->rmode.vm86_active) {
3139 vmx_get_segment(vcpu, &s, seg);
3140 return s.base;
3141 }
2fb92db1 3142 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3143}
3144
69c73028 3145static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3146{
3eeb3288 3147 if (!is_protmode(vcpu))
2e4d2653
IE		 3148 return 0;
3149
f4c63e5d
AK		 3150 if (!is_long_mode(vcpu)
3151 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3152 return 3;
3153
2fb92db1 3154 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3155}
3156
69c73028
AK		 3157static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3158{
d881e6f6
AK		 3159 struct vcpu_vmx *vmx = to_vmx(vcpu);
3160
3161 /*
3162 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3163 * fail; use the cache instead.
3164 */
3165 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3166 return vmx->cpl;
3167 }
3168
69c73028
AK		 3169 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3170 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3171 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3172 }
d881e6f6
AK		 3173
3174 return vmx->cpl;
69c73028
AK		 3175}
3176
3177
653e3108 3178static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3179{
6aa8b732
AK		 3180 u32 ar;
3181
f0495f9b 3182 if (var->unusable || !var->present)
6aa8b732
AK		 3183 ar = 1 << 16;
3184 else {
3185 ar = var->type & 15;
3186 ar |= (var->s & 1) << 4;
3187 ar |= (var->dpl & 3) << 5;
3188 ar |= (var->present & 1) << 7;
3189 ar |= (var->avl & 1) << 12;
3190 ar |= (var->l & 1) << 13;
3191 ar |= (var->db & 1) << 14;
3192 ar |= (var->g & 1) << 15;
3193 }
653e3108
AK		 3194
3195 return ar;
3196}
3197
3198static void vmx_set_segment(struct kvm_vcpu *vcpu,
3199 struct kvm_segment *var, int seg)
3200{
7ffd92c5 3201 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3202 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108
AK		 3203 u32 ar;
3204
2fb92db1
AK		 3205 vmx_segment_cache_clear(vmx);
3206
7ffd92c5 3207 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3208 vmcs_write16(sf->selector, var->selector);
f5f7b2fe 3209 vmx->rmode.segs[VCPU_SREG_TR] = *var;
653e3108
AK		 3210 return;
3211 }
3212 vmcs_writel(sf->base, var->base);
3213 vmcs_write32(sf->limit, var->limit);
3214 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3215 if (vmx->rmode.vm86_active && var->s) {
ce566803 3216 vmx->rmode.segs[seg] = *var;
653e3108
AK		 3217 /*
3218 * Hack real-mode segments into vm86 compatibility.
3219 */
3220 if (var->base == 0xffff0000 && var->selector == 0xf000)
3221 vmcs_writel(sf->base, 0xf0000);
3222 ar = 0xf3;
3223 } else
3224 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3225
3226 /*
3227 * Fix the "Accessed" bit in AR field of segment registers for older
3228 * qemu binaries.
3229 * IA32 arch specifies that at the time of processor reset the
3230 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3231 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3232 * state vmexit when "unrestricted guest" mode is turned on.
3233 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3234 * tree. Newer qemu binaries with that qemu fix would not need this
3235 * kvm hack.
3236 */
3237 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3238 ar |= 0x1; /* Accessed */
3239
6aa8b732 3240 vmcs_write32(sf->ar_bytes, ar);
69c73028 3241 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3242
3243 /*
3244 * Fix segments for real mode guest in hosts that don't have
3245 * "unrestricted_mode" or it was disabled.
3246 * This is done to allow migration of the guests from hosts with
3247 * unrestricted guest like Westmere to older host that don't have
3248 * unrestricted guest like Nehelem.
3249 */
3250 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3251 switch (seg) {
3252 case VCPU_SREG_CS:
3253 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3254 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3255 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3256 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3257 vmcs_write16(GUEST_CS_SELECTOR,
3258 vmcs_readl(GUEST_CS_BASE) >> 4);
3259 break;
3260 case VCPU_SREG_ES:
b246dd5d 3261 case VCPU_SREG_DS:
b246dd5d 3262 case VCPU_SREG_GS:
b246dd5d 3263 case VCPU_SREG_FS:
f5f7b2fe 3264 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
b246dd5d
OW		 3265 break;
3266 case VCPU_SREG_SS:
3267 vmcs_write16(GUEST_SS_SELECTOR,
3268 vmcs_readl(GUEST_SS_BASE) >> 4);
3269 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3270 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3271 break;
3272 }
3273 }
6aa8b732
AK		 3274}
3275
6aa8b732
AK		 3276static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3277{
2fb92db1 3278 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3279
3280 *db = (ar >> 14) & 1;
3281 *l = (ar >> 13) & 1;
3282}
3283
89a27f4d 3284static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3285{
89a27f4d
GN		 3286 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3287 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3288}
3289
89a27f4d 3290static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3291{
89a27f4d
GN		 3292 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3293 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3294}
3295
89a27f4d 3296static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3297{
89a27f4d
GN		 3298 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3299 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3300}
3301
89a27f4d 3302static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3303{
89a27f4d
GN		 3304 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3305 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3306}
3307
648dfaa7
MG		 3308static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3309{
3310 struct kvm_segment var;
3311 u32 ar;
3312
3313 vmx_get_segment(vcpu, &var, seg);
3314 ar = vmx_segment_access_rights(&var);
3315
3316 if (var.base != (var.selector << 4))
3317 return false;
e2a610d7 3318 if (var.limit < 0xffff)
648dfaa7 3319 return false;
a81aba14 3320 if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
648dfaa7
MG		 3321 return false;
3322
3323 return true;
3324}
3325
3326static bool code_segment_valid(struct kvm_vcpu *vcpu)
3327{
3328 struct kvm_segment cs;
3329 unsigned int cs_rpl;
3330
3331 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3332 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3333
1872a3f4
AK		 3334 if (cs.unusable)
3335 return false;
648dfaa7
MG		 3336 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3337 return false;
3338 if (!cs.s)
3339 return false;
1872a3f4 3340 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3341 if (cs.dpl > cs_rpl)
3342 return false;
1872a3f4 3343 } else {
648dfaa7
MG		 3344 if (cs.dpl != cs_rpl)
3345 return false;
3346 }
3347 if (!cs.present)
3348 return false;
3349
3350 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3351 return true;
3352}
3353
3354static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3355{
3356 struct kvm_segment ss;
3357 unsigned int ss_rpl;
3358
3359 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3360 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3361
1872a3f4
AK		 3362 if (ss.unusable)
3363 return true;
3364 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3365 return false;
3366 if (!ss.s)
3367 return false;
3368 if (ss.dpl != ss_rpl) /* DPL != RPL */
3369 return false;
3370 if (!ss.present)
3371 return false;
3372
3373 return true;
3374}
3375
3376static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3377{
3378 struct kvm_segment var;
3379 unsigned int rpl;
3380
3381 vmx_get_segment(vcpu, &var, seg);
3382 rpl = var.selector & SELECTOR_RPL_MASK;
3383
1872a3f4
AK		 3384 if (var.unusable)
3385 return true;
648dfaa7
MG		 3386 if (!var.s)
3387 return false;
3388 if (!var.present)
3389 return false;
3390 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3391 if (var.dpl < rpl) /* DPL < RPL */
3392 return false;
3393 }
3394
3395 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3396 * rights flags
3397 */
3398 return true;
3399}
3400
3401static bool tr_valid(struct kvm_vcpu *vcpu)
3402{
3403 struct kvm_segment tr;
3404
3405 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3406
1872a3f4
AK		 3407 if (tr.unusable)
3408 return false;
648dfaa7
MG		 3409 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3410 return false;
1872a3f4 3411 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3412 return false;
3413 if (!tr.present)
3414 return false;
3415
3416 return true;
3417}
3418
3419static bool ldtr_valid(struct kvm_vcpu *vcpu)
3420{
3421 struct kvm_segment ldtr;
3422
3423 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3424
1872a3f4
AK		 3425 if (ldtr.unusable)
3426 return true;
648dfaa7
MG		 3427 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3428 return false;
3429 if (ldtr.type != 2)
3430 return false;
3431 if (!ldtr.present)
3432 return false;
3433
3434 return true;
3435}
3436
3437static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3438{
3439 struct kvm_segment cs, ss;
3440
3441 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3442 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3443
3444 return ((cs.selector & SELECTOR_RPL_MASK) ==
3445 (ss.selector & SELECTOR_RPL_MASK));
3446}
3447
3448/*
3449 * Check if guest state is valid. Returns true if valid, false if
3450 * not.
3451 * We assume that registers are always usable
3452 */
3453static bool guest_state_valid(struct kvm_vcpu *vcpu)
3454{
3455 /* real mode guest state checks */
3eeb3288 3456 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3457 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3458 return false;
3459 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3460 return false;
3461 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3462 return false;
3463 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3464 return false;
3465 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3466 return false;
3467 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3468 return false;
3469 } else {
3470 /* protected mode guest state checks */
3471 if (!cs_ss_rpl_check(vcpu))
3472 return false;
3473 if (!code_segment_valid(vcpu))
3474 return false;
3475 if (!stack_segment_valid(vcpu))
3476 return false;
3477 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3478 return false;
3479 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3480 return false;
3481 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3482 return false;
3483 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3484 return false;
3485 if (!tr_valid(vcpu))
3486 return false;
3487 if (!ldtr_valid(vcpu))
3488 return false;
3489 }
3490 /* TODO:
3491 * - Add checks on RIP
3492 * - Add checks on RFLAGS
3493 */
3494
3495 return true;
3496}
3497
d77c26fc 3498static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3499{
40dcaa9f 3500 gfn_t fn;
195aefde 3501 u16 data = 0;
40dcaa9f 3502 int r, idx, ret = 0;
6aa8b732 3503
40dcaa9f
XG		 3504 idx = srcu_read_lock(&kvm->srcu);
3505 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3506 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3507 if (r < 0)
10589a46 3508 goto out;
195aefde 3509 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3510 r = kvm_write_guest_page(kvm, fn++, &data,
3511 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3512 if (r < 0)
10589a46 3513 goto out;
195aefde
IE		 3514 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3515 if (r < 0)
10589a46 3516 goto out;
195aefde
IE		 3517 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3518 if (r < 0)
10589a46 3519 goto out;
195aefde 3520 data = ~0;
10589a46
MT		 3521 r = kvm_write_guest_page(kvm, fn, &data,
3522 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3523 sizeof(u8));
195aefde 3524 if (r < 0)
10589a46
MT		 3525 goto out;
3526
3527 ret = 1;
3528out:
40dcaa9f 3529 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3530 return ret;
6aa8b732
AK		 3531}
3532
b7ebfb05
SY		 3533static int init_rmode_identity_map(struct kvm *kvm)
3534{
40dcaa9f 3535 int i, idx, r, ret;
b7ebfb05
SY		 3536 pfn_t identity_map_pfn;
3537 u32 tmp;
3538
089d034e 3539 if (!enable_ept)
b7ebfb05
SY		 3540 return 1;
3541 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3542 printk(KERN_ERR "EPT: identity-mapping pagetable "
3543 "haven't been allocated!\n");
3544 return 0;
3545 }
3546 if (likely(kvm->arch.ept_identity_pagetable_done))
3547 return 1;
3548 ret = 0;
b927a3ce 3549 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3550 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3551 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3552 if (r < 0)
3553 goto out;
3554 /* Set up identity-mapping pagetable for EPT in real mode */
3555 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3556 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3557 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3558 r = kvm_write_guest_page(kvm, identity_map_pfn,
3559 &tmp, i * sizeof(tmp), sizeof(tmp));
3560 if (r < 0)
3561 goto out;
3562 }
3563 kvm->arch.ept_identity_pagetable_done = true;
3564 ret = 1;
3565out:
40dcaa9f 3566 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3567 return ret;
3568}
3569
6aa8b732
AK		 3570static void seg_setup(int seg)
3571{
772e0318 3572 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3573 unsigned int ar;
6aa8b732
AK		 3574
3575 vmcs_write16(sf->selector, 0);
3576 vmcs_writel(sf->base, 0);
3577 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3578 if (enable_unrestricted_guest) {
3579 ar = 0x93;
3580 if (seg == VCPU_SREG_CS)
3581 ar |= 0x08; /* code segment */
3582 } else
3583 ar = 0xf3;
3584
3585 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3586}
3587
f78e0e2e
SY		 3588static int alloc_apic_access_page(struct kvm *kvm)
3589{
4484141a 3590 struct page *page;
f78e0e2e
SY		 3591 struct kvm_userspace_memory_region kvm_userspace_mem;
3592 int r = 0;
3593
79fac95e 3594 mutex_lock(&kvm->slots_lock);
bfc6d222 3595 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3596 goto out;
3597 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3598 kvm_userspace_mem.flags = 0;
3599 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3600 kvm_userspace_mem.memory_size = PAGE_SIZE;
3601 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3602 if (r)
3603 goto out;
72dc67a6 3604
4484141a
XG		 3605 page = gfn_to_page(kvm, 0xfee00);
3606 if (is_error_page(page)) {
3607 r = -EFAULT;
3608 goto out;
3609 }
3610
3611 kvm->arch.apic_access_page = page;
f78e0e2e 3612out:
79fac95e 3613 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3614 return r;
3615}
3616
b7ebfb05
SY		 3617static int alloc_identity_pagetable(struct kvm *kvm)
3618{
4484141a 3619 struct page *page;
b7ebfb05
SY		 3620 struct kvm_userspace_memory_region kvm_userspace_mem;
3621 int r = 0;
3622
79fac95e 3623 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3624 if (kvm->arch.ept_identity_pagetable)
3625 goto out;
3626 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3627 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3628 kvm_userspace_mem.guest_phys_addr =
3629 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3630 kvm_userspace_mem.memory_size = PAGE_SIZE;
3631 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3632 if (r)
3633 goto out;
3634
4484141a
XG		 3635 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3636 if (is_error_page(page)) {
3637 r = -EFAULT;
3638 goto out;
3639 }
3640
3641 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3642out:
79fac95e 3643 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3644 return r;
3645}
3646
2384d2b3
SY		 3647static void allocate_vpid(struct vcpu_vmx *vmx)
3648{
3649 int vpid;
3650
3651 vmx->vpid = 0;
919818ab 3652 if (!enable_vpid)
2384d2b3
SY		 3653 return;
3654 spin_lock(&vmx_vpid_lock);
3655 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3656 if (vpid < VMX_NR_VPIDS) {
3657 vmx->vpid = vpid;
3658 __set_bit(vpid, vmx_vpid_bitmap);
3659 }
3660 spin_unlock(&vmx_vpid_lock);
3661}
3662
cdbecfc3
LJ		 3663static void free_vpid(struct vcpu_vmx *vmx)
3664{
3665 if (!enable_vpid)
3666 return;
3667 spin_lock(&vmx_vpid_lock);
3668 if (vmx->vpid != 0)
3669 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3670 spin_unlock(&vmx_vpid_lock);
3671}
3672
5897297b 3673static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3674{
3e7c73e9 3675 int f = sizeof(unsigned long);
25c5f225
SY		 3676
3677 if (!cpu_has_vmx_msr_bitmap())
3678 return;
3679
3680 /*
3681 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3682 * have the write-low and read-high bitmap offsets the wrong way round.
3683 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3684 */
25c5f225 3685 if (msr <= 0x1fff) {
3e7c73e9
AK		 3686 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3687 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3688 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3689 msr &= 0x1fff;
3e7c73e9
AK		 3690 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3691 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3692 }
25c5f225
SY		 3693}
3694
5897297b
AK		 3695static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3696{
3697 if (!longmode_only)
3698 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3699 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3700}
3701
a3a8ff8e
NHE		 3702/*
3703 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3704 * will not change in the lifetime of the guest.
3705 * Note that host-state that does change is set elsewhere. E.g., host-state
3706 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3707 */
3708static void vmx_set_constant_host_state(void)
3709{
3710 u32 low32, high32;
3711 unsigned long tmpl;
3712 struct desc_ptr dt;
3713
b1a74bf8 3714 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3715 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3716 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3717
3718 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3719#ifdef CONFIG_X86_64
3720 /*
3721 * Load null selectors, so we can avoid reloading them in
3722 * __vmx_load_host_state(), in case userspace uses the null selectors
3723 * too (the expected case).
3724 */
3725 vmcs_write16(HOST_DS_SELECTOR, 0);
3726 vmcs_write16(HOST_ES_SELECTOR, 0);
3727#else
a3a8ff8e
NHE		 3728 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3729 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3730#endif
a3a8ff8e
NHE		 3731 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3732 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3733
3734 native_store_idt(&dt);
3735 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3736
83287ea4 3737 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3738
3739 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3740 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3741 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3742 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3743
3744 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3745 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3746 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3747 }
3748}
3749
bf8179a0
NHE		 3750static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3751{
3752 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3753 if (enable_ept)
3754 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3755 if (is_guest_mode(&vmx->vcpu))
3756 vmx->vcpu.arch.cr4_guest_owned_bits &=
3757 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3758 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3759}
3760
3761static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3762{
3763 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3764 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3765 exec_control &= ~CPU_BASED_TPR_SHADOW;
3766#ifdef CONFIG_X86_64
3767 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3768 CPU_BASED_CR8_LOAD_EXITING;
3769#endif
3770 }
3771 if (!enable_ept)
3772 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3773 CPU_BASED_CR3_LOAD_EXITING |
3774 CPU_BASED_INVLPG_EXITING;
3775 return exec_control;
3776}
3777
3778static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3779{
3780 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3781 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3782 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3783 if (vmx->vpid == 0)
3784 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3785 if (!enable_ept) {
3786 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3787 enable_unrestricted_guest = 0;
ad756a16
MJ		 3788 /* Enable INVPCID for non-ept guests may cause performance regression. */
3789 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3790 }
3791 if (!enable_unrestricted_guest)
3792 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3793 if (!ple_gap)
3794 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3795 return exec_control;
3796}
3797
ce88decf
XG		 3798static void ept_set_mmio_spte_mask(void)
3799{
3800 /*
3801 * EPT Misconfigurations can be generated if the value of bits 2:0
3802 * of an EPT paging-structure entry is 110b (write/execute).
3803 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3804 * spte.
3805 */
3806 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3807}
3808
6aa8b732
AK		 3809/*
3810 * Sets up the vmcs for emulated real mode.
3811 */
8b9cf98c 3812static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3813{
2e4ce7f5 3814#ifdef CONFIG_X86_64
6aa8b732 3815 unsigned long a;
2e4ce7f5 3816#endif
6aa8b732 3817 int i;
6aa8b732 3818
6aa8b732 3819 /* I/O */
3e7c73e9
AK		 3820 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3821 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3822
25c5f225 3823 if (cpu_has_vmx_msr_bitmap())
5897297b 3824 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3825
6aa8b732
AK		 3826 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3827
6aa8b732 3828 /* Control */
1c3d14fe
YS		 3829 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3830 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3831
bf8179a0 3832 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3833
83ff3b9d 3834 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3835 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3836 vmx_secondary_exec_control(vmx));
83ff3b9d 3837 }
f78e0e2e 3838
4b8d54f9
ZE		 3839 if (ple_gap) {
3840 vmcs_write32(PLE_GAP, ple_gap);
3841 vmcs_write32(PLE_WINDOW, ple_window);
3842 }
3843
c3707958
XG		 3844 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3845 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3846 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3847
9581d442
AK		 3848 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3849 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3850 vmx_set_constant_host_state();
05b3e0c2 3851#ifdef CONFIG_X86_64
6aa8b732
AK		 3852 rdmsrl(MSR_FS_BASE, a);
3853 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3854 rdmsrl(MSR_GS_BASE, a);
3855 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3856#else
3857 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3858 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3859#endif
3860
2cc51560
ED		 3861 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3862 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3863 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3864 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3865 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3866
468d472f 3867 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3868 u32 msr_low, msr_high;
3869 u64 host_pat;
468d472f
SY		 3870 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3871 host_pat = msr_low | ((u64) msr_high << 32);
3872 /* Write the default value follow host pat */
3873 vmcs_write64(GUEST_IA32_PAT, host_pat);
3874 /* Keep arch.pat sync with GUEST_IA32_PAT */
3875 vmx->vcpu.arch.pat = host_pat;
3876 }
3877
6aa8b732
AK		 3878 for (i = 0; i < NR_VMX_MSR; ++i) {
3879 u32 index = vmx_msr_index[i];
3880 u32 data_low, data_high;
a2fa3e9f 3881 int j = vmx->nmsrs;
6aa8b732
AK		 3882
3883 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3884 continue;
432bd6cb
AK		 3885 if (wrmsr_safe(index, data_low, data_high) < 0)
3886 continue;
26bb0981
AK		 3887 vmx->guest_msrs[j].index = i;
3888 vmx->guest_msrs[j].data = 0;
d5696725 3889 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3890 ++vmx->nmsrs;
6aa8b732 3891 }
6aa8b732 3892
1c3d14fe 3893 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3894
3895 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3896 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3897
e00c8cf2 3898 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3899 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 3900
3901 return 0;
3902}
3903
3904static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3905{
3906 struct vcpu_vmx *vmx = to_vmx(vcpu);
3907 u64 msr;
4b9d3a04 3908 int ret;
e00c8cf2 3909
5fdbf976 3910 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3911
7ffd92c5 3912 vmx->rmode.vm86_active = 0;
e00c8cf2 3913
3b86cd99
JK		 3914 vmx->soft_vnmi_blocked = 0;
3915
ad312c7c 3916 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3917 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3918 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3919 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3920 msr |= MSR_IA32_APICBASE_BSP;
3921 kvm_set_apic_base(&vmx->vcpu, msr);
3922
10ab25cd
JK		 3923 ret = fx_init(&vmx->vcpu);
3924 if (ret != 0)
3925 goto out;
e00c8cf2 3926
2fb92db1
AK		 3927 vmx_segment_cache_clear(vmx);
3928
5706be0d 3929 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3930 /*
3931 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3932 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3933 */
c5af89b6 3934 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3935 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3936 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3937 } else {
ad312c7c
ZX		 3938 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3939 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3940 }
e00c8cf2
AK		 3941
3942 seg_setup(VCPU_SREG_DS);
3943 seg_setup(VCPU_SREG_ES);
3944 seg_setup(VCPU_SREG_FS);
3945 seg_setup(VCPU_SREG_GS);
3946 seg_setup(VCPU_SREG_SS);
3947
3948 vmcs_write16(GUEST_TR_SELECTOR, 0);
3949 vmcs_writel(GUEST_TR_BASE, 0);
3950 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3951 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3952
3953 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3954 vmcs_writel(GUEST_LDTR_BASE, 0);
3955 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3956 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3957
3958 vmcs_write32(GUEST_SYSENTER_CS, 0);
3959 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3960 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3961
3962 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3963 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3964 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3965 else
5fdbf976
MT		 3966 kvm_rip_write(vcpu, 0);
3967 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3968
e00c8cf2
AK		 3969 vmcs_writel(GUEST_GDTR_BASE, 0);
3970 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3971
3972 vmcs_writel(GUEST_IDTR_BASE, 0);
3973 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3974
443381a8 3975 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3976 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3977 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3978
e00c8cf2
AK		 3979 /* Special registers */
3980 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3981
3982 setup_msrs(vmx);
3983
6aa8b732
AK		 3984 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3985
f78e0e2e
SY		 3986 if (cpu_has_vmx_tpr_shadow()) {
3987 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3988 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3989 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3990 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3991 vmcs_write32(TPR_THRESHOLD, 0);
3992 }
3993
3994 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3995 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3996 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3997
2384d2b3
SY		 3998 if (vmx->vpid != 0)
3999 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4000
fa40052c 4001 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4002 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4003 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4004 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4005 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4006 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4007 vmx_fpu_activate(&vmx->vcpu);
4008 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4009
b9d762fa 4010 vpid_sync_context(vmx);
2384d2b3 4011
3200f405 4012 ret = 0;
6aa8b732 4013
a89a8fb9
MG		 4014 /* HACK: Don't enable emulation on guest boot/reset */
4015 vmx->emulation_required = 0;
4016
6aa8b732
AK		 4017out:
4018 return ret;
4019}
4020
b6f1250e
NHE		 4021/*
4022 * In nested virtualization, check if L1 asked to exit on external interrupts.
4023 * For most existing hypervisors, this will always return true.
4024 */
4025static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4026{
4027 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4028 PIN_BASED_EXT_INTR_MASK;
4029}
4030
3b86cd99
JK		 4031static void enable_irq_window(struct kvm_vcpu *vcpu)
4032{
4033 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4034 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4035 /*
4036 * We get here if vmx_interrupt_allowed() said we can't
4037 * inject to L1 now because L2 must run. Ask L2 to exit
4038 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4039 */
d6185f20 4040 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4041 return;
d6185f20 4042 }
3b86cd99
JK		 4043
4044 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4045 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4046 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4047}
4048
4049static void enable_nmi_window(struct kvm_vcpu *vcpu)
4050{
4051 u32 cpu_based_vm_exec_control;
4052
4053 if (!cpu_has_virtual_nmis()) {
4054 enable_irq_window(vcpu);
4055 return;
4056 }
4057
30bd0c4c
AK		 4058 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4059 enable_irq_window(vcpu);
4060 return;
4061 }
3b86cd99
JK		 4062 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4063 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4064 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4065}
4066
66fd3f7f 4067static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4068{
9c8cba37 4069 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4070 uint32_t intr;
4071 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4072
229456fc 4073 trace_kvm_inj_virq(irq);
2714d1d3 4074
fa89a817 4075 ++vcpu->stat.irq_injections;
7ffd92c5 4076 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4077 int inc_eip = 0;
4078 if (vcpu->arch.interrupt.soft)
4079 inc_eip = vcpu->arch.event_exit_inst_len;
4080 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4081 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4082 return;
4083 }
66fd3f7f
GN		 4084 intr = irq | INTR_INFO_VALID_MASK;
4085 if (vcpu->arch.interrupt.soft) {
4086 intr |= INTR_TYPE_SOFT_INTR;
4087 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4088 vmx->vcpu.arch.event_exit_inst_len);
4089 } else
4090 intr |= INTR_TYPE_EXT_INTR;
4091 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4092}
4093
f08864b4
SY		 4094static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4095{
66a5a347
JK		 4096 struct vcpu_vmx *vmx = to_vmx(vcpu);
4097
0b6ac343
NHE		 4098 if (is_guest_mode(vcpu))
4099 return;
4100
3b86cd99
JK		 4101 if (!cpu_has_virtual_nmis()) {
4102 /*
4103 * Tracking the NMI-blocked state in software is built upon
4104 * finding the next open IRQ window. This, in turn, depends on
4105 * well-behaving guests: They have to keep IRQs disabled at
4106 * least as long as the NMI handler runs. Otherwise we may
4107 * cause NMI nesting, maybe breaking the guest. But as this is
4108 * highly unlikely, we can live with the residual risk.
4109 */
4110 vmx->soft_vnmi_blocked = 1;
4111 vmx->vnmi_blocked_time = 0;
4112 }
4113
487b391d 4114 ++vcpu->stat.nmi_injections;
9d58b931 4115 vmx->nmi_known_unmasked = false;
7ffd92c5 4116 if (vmx->rmode.vm86_active) {
71f9833b 4117 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4118 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4119 return;
4120 }
f08864b4
SY		 4121 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4122 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4123}
4124
c4282df9 4125static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4126{
3b86cd99 4127 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4128 return 0;
33f089ca 4129
c4282df9 4130 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4131 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4132 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4133}
4134
3cfc3092
JK		 4135static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4136{
4137 if (!cpu_has_virtual_nmis())
4138 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4139 if (to_vmx(vcpu)->nmi_known_unmasked)
4140 return false;
c332c83a 4141 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4142}
4143
4144static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4145{
4146 struct vcpu_vmx *vmx = to_vmx(vcpu);
4147
4148 if (!cpu_has_virtual_nmis()) {
4149 if (vmx->soft_vnmi_blocked != masked) {
4150 vmx->soft_vnmi_blocked = masked;
4151 vmx->vnmi_blocked_time = 0;
4152 }
4153 } else {
9d58b931 4154 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4155 if (masked)
4156 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4157 GUEST_INTR_STATE_NMI);
4158 else
4159 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4160 GUEST_INTR_STATE_NMI);
4161 }
4162}
4163
78646121
GN		 4164static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4165{
b6f1250e 4166 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4167 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4168 if (to_vmx(vcpu)->nested.nested_run_pending ||
4169 (vmcs12->idt_vectoring_info_field &
4170 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4171 return 0;
4172 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4173 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4174 vmcs12->vm_exit_intr_info = 0;
4175 /* fall through to normal code, but now in L1, not L2 */
4176 }
4177
c4282df9
GN		 4178 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4179 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4180 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4181}
4182
cbc94022
IE		 4183static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4184{
4185 int ret;
4186 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4187 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4188 .guest_phys_addr = addr,
4189 .memory_size = PAGE_SIZE * 3,
4190 .flags = 0,
4191 };
4192
4193 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4194 if (ret)
4195 return ret;
bfc6d222 4196 kvm->arch.tss_addr = addr;
93ea5388
GN		 4197 if (!init_rmode_tss(kvm))
4198 return -ENOMEM;
4199
cbc94022
IE		 4200 return 0;
4201}
4202
6aa8b732
AK		 4203static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4204 int vec, u32 err_code)
4205{
b3f37707
NK		 4206 /*
4207 * Instruction with address size override prefix opcode 0x67
4208 * Cause the #SS fault with 0 error code in VM86 mode.
4209 */
4210 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4211 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4212 return 1;
77ab6db0
JK		 4213 /*
4214 * Forward all other exceptions that are valid in real mode.
4215 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4216 * the required debugging infrastructure rework.
4217 */
4218 switch (vec) {
77ab6db0 4219 case DB_VECTOR:
d0bfb940
JK		 4220 if (vcpu->guest_debug &
4221 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4222 return 0;
4223 kvm_queue_exception(vcpu, vec);
4224 return 1;
77ab6db0 4225 case BP_VECTOR:
c573cd22
JK		 4226 /*
4227 * Update instruction length as we may reinject the exception
4228 * from user space while in guest debugging mode.
4229 */
4230 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4231 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4232 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4233 return 0;
4234 /* fall through */
4235 case DE_VECTOR:
77ab6db0
JK		 4236 case OF_VECTOR:
4237 case BR_VECTOR:
4238 case UD_VECTOR:
4239 case DF_VECTOR:
4240 case SS_VECTOR:
4241 case GP_VECTOR:
4242 case MF_VECTOR:
4243 kvm_queue_exception(vcpu, vec);
4244 return 1;
4245 }
6aa8b732
AK		 4246 return 0;
4247}
4248
a0861c02
AK		 4249/*
4250 * Trigger machine check on the host. We assume all the MSRs are already set up
4251 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4252 * We pass a fake environment to the machine check handler because we want
4253 * the guest to be always treated like user space, no matter what context
4254 * it used internally.
4255 */
4256static void kvm_machine_check(void)
4257{
4258#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4259 struct pt_regs regs = {
4260 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4261 .flags = X86_EFLAGS_IF,
4262 };
4263
4264 do_machine_check(&regs, 0);
4265#endif
4266}
4267
851ba692 4268static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4269{
4270 /* already handled by vcpu_run */
4271 return 1;
4272}
4273
851ba692 4274static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4275{
1155f76a 4276 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4277 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4278 u32 intr_info, ex_no, error_code;
42dbaa5a 4279 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4280 u32 vect_info;
4281 enum emulation_result er;
4282
1155f76a 4283 vect_info = vmx->idt_vectoring_info;
88786475 4284 intr_info = vmx->exit_intr_info;
6aa8b732 4285
a0861c02 4286 if (is_machine_check(intr_info))
851ba692 4287 return handle_machine_check(vcpu);
a0861c02 4288
e4a41889 4289 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4290 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4291
4292 if (is_no_device(intr_info)) {
5fd86fcf 4293 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4294 return 1;
4295 }
4296
7aa81cc0 4297 if (is_invalid_opcode(intr_info)) {
51d8b661 4298 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4299 if (er != EMULATE_DONE)
7ee5d940 4300 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4301 return 1;
4302 }
4303
6aa8b732 4304 error_code = 0;
2e11384c 4305 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4306 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4307
4308 /*
4309 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4310 * MMIO, it is better to report an internal error.
4311 * See the comments in vmx_handle_exit.
4312 */
4313 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4314 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4315 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4316 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4317 vcpu->run->internal.ndata = 2;
4318 vcpu->run->internal.data[0] = vect_info;
4319 vcpu->run->internal.data[1] = intr_info;
4320 return 0;
4321 }
4322
6aa8b732 4323 if (is_page_fault(intr_info)) {
1439442c 4324 /* EPT won't cause page fault directly */
cf3ace79 4325 BUG_ON(enable_ept);
6aa8b732 4326 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4327 trace_kvm_page_fault(cr2, error_code);
4328
3298b75c 4329 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4330 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4331 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4332 }
4333
7ffd92c5 4334 if (vmx->rmode.vm86_active &&
6aa8b732 4335 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4336 error_code)) {
ad312c7c
ZX		 4337 if (vcpu->arch.halt_request) {
4338 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4339 return kvm_emulate_halt(vcpu);
4340 }
6aa8b732 4341 return 1;
72d6e5a0 4342 }
6aa8b732 4343
d0bfb940 4344 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4345 switch (ex_no) {
4346 case DB_VECTOR:
4347 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4348 if (!(vcpu->guest_debug &
4349 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4350 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4351 kvm_queue_exception(vcpu, DB_VECTOR);
4352 return 1;
4353 }
4354 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4355 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4356 /* fall through */
4357 case BP_VECTOR:
c573cd22
JK		 4358 /*
4359 * Update instruction length as we may reinject #BP from
4360 * user space while in guest debugging mode. Reading it for
4361 * #DB as well causes no harm, it is not used in that case.
4362 */
4363 vmx->vcpu.arch.event_exit_inst_len =
4364 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4365 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4366 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4367 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4368 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4369 break;
4370 default:
d0bfb940
JK		 4371 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4372 kvm_run->ex.exception = ex_no;
4373 kvm_run->ex.error_code = error_code;
42dbaa5a 4374 break;
6aa8b732 4375 }
6aa8b732
AK		 4376 return 0;
4377}
4378
851ba692 4379static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4380{
1165f5fe 4381 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4382 return 1;
4383}
4384
851ba692 4385static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4386{
851ba692 4387 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4388 return 0;
4389}
6aa8b732 4390
851ba692 4391static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4392{
bfdaab09 4393 unsigned long exit_qualification;
34c33d16 4394 int size, in, string;
039576c0 4395 unsigned port;
6aa8b732 4396
bfdaab09 4397 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4398 string = (exit_qualification & 16) != 0;
cf8f70bf 4399 in = (exit_qualification & 8) != 0;
e70669ab 4400
cf8f70bf 4401 ++vcpu->stat.io_exits;
e70669ab 4402
cf8f70bf 4403 if (string || in)
51d8b661 4404 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4405
cf8f70bf
GN		 4406 port = exit_qualification >> 16;
4407 size = (exit_qualification & 7) + 1;
e93f36bc 4408 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4409
4410 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4411}
4412
102d8325
IM		 4413static void
4414vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4415{
4416 /*
4417 * Patch in the VMCALL instruction:
4418 */
4419 hypercall[0] = 0x0f;
4420 hypercall[1] = 0x01;
4421 hypercall[2] = 0xc1;
102d8325
IM		 4422}
4423
0fa06071 4424/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4425static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4426{
4427 if (to_vmx(vcpu)->nested.vmxon &&
4428 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4429 return 1;
4430
4431 if (is_guest_mode(vcpu)) {
4432 /*
4433 * We get here when L2 changed cr0 in a way that did not change
4434 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4435 * but did change L0 shadowed bits. This can currently happen
4436 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4437 * loading) while pretending to allow the guest to change it.
4438 */
4439 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4440 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4441 return 1;
4442 vmcs_writel(CR0_READ_SHADOW, val);
4443 return 0;
4444 } else
4445 return kvm_set_cr0(vcpu, val);
4446}
4447
4448static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4449{
4450 if (is_guest_mode(vcpu)) {
4451 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4452 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4453 return 1;
4454 vmcs_writel(CR4_READ_SHADOW, val);
4455 return 0;
4456 } else
4457 return kvm_set_cr4(vcpu, val);
4458}
4459
4460/* called to set cr0 as approriate for clts instruction exit. */
4461static void handle_clts(struct kvm_vcpu *vcpu)
4462{
4463 if (is_guest_mode(vcpu)) {
4464 /*
4465 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4466 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4467 * just pretend it's off (also in arch.cr0 for fpu_activate).
4468 */
4469 vmcs_writel(CR0_READ_SHADOW,
4470 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4471 vcpu->arch.cr0 &= ~X86_CR0_TS;
4472 } else
4473 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4474}
4475
851ba692 4476static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4477{
229456fc 4478 unsigned long exit_qualification, val;
6aa8b732
AK		 4479 int cr;
4480 int reg;
49a9b07e 4481 int err;
6aa8b732 4482
bfdaab09 4483 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4484 cr = exit_qualification & 15;
4485 reg = (exit_qualification >> 8) & 15;
4486 switch ((exit_qualification >> 4) & 3) {
4487 case 0: /* mov to cr */
229456fc
MT		 4488 val = kvm_register_read(vcpu, reg);
4489 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4490 switch (cr) {
4491 case 0:
eeadf9e7 4492 err = handle_set_cr0(vcpu, val);
db8fcefa 4493 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4494 return 1;
4495 case 3:
2390218b 4496 err = kvm_set_cr3(vcpu, val);
db8fcefa 4497 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4498 return 1;
4499 case 4:
eeadf9e7 4500 err = handle_set_cr4(vcpu, val);
db8fcefa 4501 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4502 return 1;
0a5fff19
GN		 4503 case 8: {
4504 u8 cr8_prev = kvm_get_cr8(vcpu);
4505 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4506 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4507 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4508 if (irqchip_in_kernel(vcpu->kvm))
4509 return 1;
4510 if (cr8_prev <= cr8)
4511 return 1;
851ba692 4512 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4513 return 0;
4514 }
4b8073e4 4515 }
6aa8b732 4516 break;
25c4c276 4517 case 2: /* clts */
eeadf9e7 4518 handle_clts(vcpu);
4d4ec087 4519 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4520 skip_emulated_instruction(vcpu);
6b52d186 4521 vmx_fpu_activate(vcpu);
25c4c276 4522 return 1;
6aa8b732
AK		 4523 case 1: /*mov from cr*/
4524 switch (cr) {
4525 case 3:
9f8fe504
AK		 4526 val = kvm_read_cr3(vcpu);
4527 kvm_register_write(vcpu, reg, val);
4528 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4529 skip_emulated_instruction(vcpu);
4530 return 1;
4531 case 8:
229456fc
MT		 4532 val = kvm_get_cr8(vcpu);
4533 kvm_register_write(vcpu, reg, val);
4534 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4535 skip_emulated_instruction(vcpu);
4536 return 1;
4537 }
4538 break;
4539 case 3: /* lmsw */
a1f83a74 4540 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4541 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4542 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4543
4544 skip_emulated_instruction(vcpu);
4545 return 1;
4546 default:
4547 break;
4548 }
851ba692 4549 vcpu->run->exit_reason = 0;
a737f256 4550 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4551 (int)(exit_qualification >> 4) & 3, cr);
4552 return 0;
4553}
4554
851ba692 4555static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4556{
bfdaab09 4557 unsigned long exit_qualification;
6aa8b732
AK		 4558 int dr, reg;
4559
f2483415 4560 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4561 if (!kvm_require_cpl(vcpu, 0))
4562 return 1;
42dbaa5a
JK		 4563 dr = vmcs_readl(GUEST_DR7);
4564 if (dr & DR7_GD) {
4565 /*
4566 * As the vm-exit takes precedence over the debug trap, we
4567 * need to emulate the latter, either for the host or the
4568 * guest debugging itself.
4569 */
4570 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4571 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4572 vcpu->run->debug.arch.dr7 = dr;
4573 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4574 vmcs_readl(GUEST_CS_BASE) +
4575 vmcs_readl(GUEST_RIP);
851ba692
AK		 4576 vcpu->run->debug.arch.exception = DB_VECTOR;
4577 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4578 return 0;
4579 } else {
4580 vcpu->arch.dr7 &= ~DR7_GD;
4581 vcpu->arch.dr6 |= DR6_BD;
4582 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4583 kvm_queue_exception(vcpu, DB_VECTOR);
4584 return 1;
4585 }
4586 }
4587
bfdaab09 4588 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4589 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4590 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4591 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4592 unsigned long val;
4593 if (!kvm_get_dr(vcpu, dr, &val))
4594 kvm_register_write(vcpu, reg, val);
4595 } else
4596 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4597 skip_emulated_instruction(vcpu);
4598 return 1;
4599}
4600
020df079
GN		 4601static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4602{
4603 vmcs_writel(GUEST_DR7, val);
4604}
4605
851ba692 4606static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4607{
06465c5a
AK		 4608 kvm_emulate_cpuid(vcpu);
4609 return 1;
6aa8b732
AK		 4610}
4611
851ba692 4612static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4613{
ad312c7c 4614 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4615 u64 data;
4616
4617 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4618 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4619 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4620 return 1;
4621 }
4622
229456fc 4623 trace_kvm_msr_read(ecx, data);
2714d1d3 4624
6aa8b732 4625 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4626 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4627 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4628 skip_emulated_instruction(vcpu);
4629 return 1;
4630}
4631
851ba692 4632static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4633{
ad312c7c
ZX		 4634 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4635 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4636 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4637
4638 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4639 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4640 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4641 return 1;
4642 }
4643
59200273 4644 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4645 skip_emulated_instruction(vcpu);
4646 return 1;
4647}
4648
851ba692 4649static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4650{
3842d135 4651 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4652 return 1;
4653}
4654
851ba692 4655static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4656{
85f455f7
ED		 4657 u32 cpu_based_vm_exec_control;
4658
4659 /* clear pending irq */
4660 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4661 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4662 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4663
3842d135
AK		 4664 kvm_make_request(KVM_REQ_EVENT, vcpu);
4665
a26bf12a 4666 ++vcpu->stat.irq_window_exits;
2714d1d3 4667
c1150d8c
DL		 4668 /*
4669 * If the user space waits to inject interrupts, exit as soon as
4670 * possible
4671 */
8061823a 4672 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4673 vcpu->run->request_interrupt_window &&
8061823a 4674 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4675 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4676 return 0;
4677 }
6aa8b732
AK		 4678 return 1;
4679}
4680
851ba692 4681static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4682{
4683 skip_emulated_instruction(vcpu);
d3bef15f 4684 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4685}
4686
851ba692 4687static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4688{
510043da 4689 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4690 kvm_emulate_hypercall(vcpu);
4691 return 1;
c21415e8
IM		 4692}
4693
ec25d5e6
GN		 4694static int handle_invd(struct kvm_vcpu *vcpu)
4695{
51d8b661 4696 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4697}
4698
851ba692 4699static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4700{
f9c617f6 4701 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4702
4703 kvm_mmu_invlpg(vcpu, exit_qualification);
4704 skip_emulated_instruction(vcpu);
4705 return 1;
4706}
4707
fee84b07
AK		 4708static int handle_rdpmc(struct kvm_vcpu *vcpu)
4709{
4710 int err;
4711
4712 err = kvm_rdpmc(vcpu);
4713 kvm_complete_insn_gp(vcpu, err);
4714
4715 return 1;
4716}
4717
851ba692 4718static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4719{
4720 skip_emulated_instruction(vcpu);
f5f48ee1 4721 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4722 return 1;
4723}
4724
2acf923e
DC		 4725static int handle_xsetbv(struct kvm_vcpu *vcpu)
4726{
4727 u64 new_bv = kvm_read_edx_eax(vcpu);
4728 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4729
4730 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4731 skip_emulated_instruction(vcpu);
4732 return 1;
4733}
4734
851ba692 4735static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4736{
58fbbf26
KT		 4737 if (likely(fasteoi)) {
4738 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4739 int access_type, offset;
4740
4741 access_type = exit_qualification & APIC_ACCESS_TYPE;
4742 offset = exit_qualification & APIC_ACCESS_OFFSET;
4743 /*
4744 * Sane guest uses MOV to write EOI, with written value
4745 * not cared. So make a short-circuit here by avoiding
4746 * heavy instruction emulation.
4747 */
4748 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4749 (offset == APIC_EOI)) {
4750 kvm_lapic_set_eoi(vcpu);
4751 skip_emulated_instruction(vcpu);
4752 return 1;
4753 }
4754 }
51d8b661 4755 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4756}
4757
851ba692 4758static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4759{
60637aac 4760 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4761 unsigned long exit_qualification;
e269fb21
JK		 4762 bool has_error_code = false;
4763 u32 error_code = 0;
37817f29 4764 u16 tss_selector;
7f3d35fd 4765 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4766
4767 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4768 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4769 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4770
4771 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4772
4773 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4774 if (reason == TASK_SWITCH_GATE && idt_v) {
4775 switch (type) {
4776 case INTR_TYPE_NMI_INTR:
4777 vcpu->arch.nmi_injected = false;
654f06fc 4778 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4779 break;
4780 case INTR_TYPE_EXT_INTR:
66fd3f7f 4781 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4782 kvm_clear_interrupt_queue(vcpu);
4783 break;
4784 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4785 if (vmx->idt_vectoring_info &
4786 VECTORING_INFO_DELIVER_CODE_MASK) {
4787 has_error_code = true;
4788 error_code =
4789 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4790 }
4791 /* fall through */
64a7ec06
GN		 4792 case INTR_TYPE_SOFT_EXCEPTION:
4793 kvm_clear_exception_queue(vcpu);
4794 break;
4795 default:
4796 break;
4797 }
60637aac 4798 }
37817f29
IE		 4799 tss_selector = exit_qualification;
4800
64a7ec06
GN		 4801 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4802 type != INTR_TYPE_EXT_INTR &&
4803 type != INTR_TYPE_NMI_INTR))
4804 skip_emulated_instruction(vcpu);
4805
7f3d35fd
KW		 4806 if (kvm_task_switch(vcpu, tss_selector,
4807 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4808 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4809 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4810 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4811 vcpu->run->internal.ndata = 0;
42dbaa5a 4812 return 0;
acb54517 4813 }
42dbaa5a
JK		 4814
4815 /* clear all local breakpoint enable flags */
4816 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4817
4818 /*
4819 * TODO: What about debug traps on tss switch?
4820 * Are we supposed to inject them and update dr6?
4821 */
4822
4823 return 1;
37817f29
IE		 4824}
4825
851ba692 4826static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4827{
f9c617f6 4828 unsigned long exit_qualification;
1439442c 4829 gpa_t gpa;
4f5982a5 4830 u32 error_code;
1439442c 4831 int gla_validity;
1439442c 4832
f9c617f6 4833 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4834
4835 if (exit_qualification & (1 << 6)) {
4836 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4837 return -EINVAL;
1439442c
SY		 4838 }
4839
4840 gla_validity = (exit_qualification >> 7) & 0x3;
4841 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4842 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4843 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4844 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4845 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4846 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4847 (long unsigned int)exit_qualification);
851ba692
AK		 4848 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4849 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4850 return 0;
1439442c
SY		 4851 }
4852
4853 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4854 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4855
4856 /* It is a write fault? */
4857 error_code = exit_qualification & (1U << 1);
4858 /* ept page table is present? */
4859 error_code |= (exit_qualification >> 3) & 0x1;
4860
4861 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4862}
4863
68f89400
MT		 4864static u64 ept_rsvd_mask(u64 spte, int level)
4865{
4866 int i;
4867 u64 mask = 0;
4868
4869 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4870 mask |= (1ULL << i);
4871
4872 if (level > 2)
4873 /* bits 7:3 reserved */
4874 mask |= 0xf8;
4875 else if (level == 2) {
4876 if (spte & (1ULL << 7))
4877 /* 2MB ref, bits 20:12 reserved */
4878 mask |= 0x1ff000;
4879 else
4880 /* bits 6:3 reserved */
4881 mask |= 0x78;
4882 }
4883
4884 return mask;
4885}
4886
4887static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4888 int level)
4889{
4890 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4891
4892 /* 010b (write-only) */
4893 WARN_ON((spte & 0x7) == 0x2);
4894
4895 /* 110b (write/execute) */
4896 WARN_ON((spte & 0x7) == 0x6);
4897
4898 /* 100b (execute-only) and value not supported by logical processor */
4899 if (!cpu_has_vmx_ept_execute_only())
4900 WARN_ON((spte & 0x7) == 0x4);
4901
4902 /* not 000b */
4903 if ((spte & 0x7)) {
4904 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4905
4906 if (rsvd_bits != 0) {
4907 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4908 __func__, rsvd_bits);
4909 WARN_ON(1);
4910 }
4911
4912 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4913 u64 ept_mem_type = (spte & 0x38) >> 3;
4914
4915 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4916 ept_mem_type == 7) {
4917 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4918 __func__, ept_mem_type);
4919 WARN_ON(1);
4920 }
4921 }
4922 }
4923}
4924
851ba692 4925static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4926{
4927 u64 sptes[4];
ce88decf 4928 int nr_sptes, i, ret;
68f89400
MT		 4929 gpa_t gpa;
4930
4931 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4932
ce88decf
XG		 4933 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4934 if (likely(ret == 1))
4935 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4936 EMULATE_DONE;
4937 if (unlikely(!ret))
4938 return 1;
4939
4940 /* It is the real ept misconfig */
68f89400
MT		 4941 printk(KERN_ERR "EPT: Misconfiguration.\n");
4942 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4943
4944 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4945
4946 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4947 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4948
851ba692
AK		 4949 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4950 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4951
4952 return 0;
4953}
4954
851ba692 4955static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4956{
4957 u32 cpu_based_vm_exec_control;
4958
4959 /* clear pending NMI */
4960 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4961 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4962 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4963 ++vcpu->stat.nmi_window_exits;
3842d135 4964 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4965
4966 return 1;
4967}
4968
80ced186 4969static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4970{
8b3079a5
AK		 4971 struct vcpu_vmx *vmx = to_vmx(vcpu);
4972 enum emulation_result err = EMULATE_DONE;
80ced186 4973 int ret = 1;
49e9d557
AK		 4974 u32 cpu_exec_ctrl;
4975 bool intr_window_requested;
b8405c18 4976 unsigned count = 130;
49e9d557
AK		 4977
4978 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4979 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 4980
b8405c18 4981 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 4982 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 4983 return handle_interrupt_window(&vmx->vcpu);
4984
de87dcdd
AK		 4985 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
4986 return 1;
4987
51d8b661 4988 err = emulate_instruction(vcpu, 0);
ea953ef0 4989
80ced186
MG		 4990 if (err == EMULATE_DO_MMIO) {
4991 ret = 0;
4992 goto out;
4993 }
1d5a4d9b 4994
de5f70e0
AK		 4995 if (err != EMULATE_DONE) {
4996 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4997 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4998 vcpu->run->internal.ndata = 0;
6d77dbfc 4999 return 0;
de5f70e0 5000 }
ea953ef0
MG		 5001
5002 if (signal_pending(current))
80ced186 5003 goto out;
ea953ef0
MG		 5004 if (need_resched())
5005 schedule();
5006 }
5007
7c068e45 5008 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5009out:
5010 return ret;
ea953ef0
MG		 5011}
5012
4b8d54f9
ZE		 5013/*
5014 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5015 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5016 */
9fb41ba8 5017static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5018{
5019 skip_emulated_instruction(vcpu);
5020 kvm_vcpu_on_spin(vcpu);
5021
5022 return 1;
5023}
5024
59708670
SY		 5025static int handle_invalid_op(struct kvm_vcpu *vcpu)
5026{
5027 kvm_queue_exception(vcpu, UD_VECTOR);
5028 return 1;
5029}
5030
ff2f6fe9
NHE		 5031/*
5032 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5033 * We could reuse a single VMCS for all the L2 guests, but we also want the
5034 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5035 * allows keeping them loaded on the processor, and in the future will allow
5036 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5037 * every entry if they never change.
5038 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5039 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5040 *
5041 * The following functions allocate and free a vmcs02 in this pool.
5042 */
5043
5044/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5045static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5046{
5047 struct vmcs02_list *item;
5048 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5049 if (item->vmptr == vmx->nested.current_vmptr) {
5050 list_move(&item->list, &vmx->nested.vmcs02_pool);
5051 return &item->vmcs02;
5052 }
5053
5054 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5055 /* Recycle the least recently used VMCS. */
5056 item = list_entry(vmx->nested.vmcs02_pool.prev,
5057 struct vmcs02_list, list);
5058 item->vmptr = vmx->nested.current_vmptr;
5059 list_move(&item->list, &vmx->nested.vmcs02_pool);
5060 return &item->vmcs02;
5061 }
5062
5063 /* Create a new VMCS */
5064 item = (struct vmcs02_list *)
5065 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5066 if (!item)
5067 return NULL;
5068 item->vmcs02.vmcs = alloc_vmcs();
5069 if (!item->vmcs02.vmcs) {
5070 kfree(item);
5071 return NULL;
5072 }
5073 loaded_vmcs_init(&item->vmcs02);
5074 item->vmptr = vmx->nested.current_vmptr;
5075 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5076 vmx->nested.vmcs02_num++;
5077 return &item->vmcs02;
5078}
5079
5080/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5081static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5082{
5083 struct vmcs02_list *item;
5084 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5085 if (item->vmptr == vmptr) {
5086 free_loaded_vmcs(&item->vmcs02);
5087 list_del(&item->list);
5088 kfree(item);
5089 vmx->nested.vmcs02_num--;
5090 return;
5091 }
5092}
5093
5094/*
5095 * Free all VMCSs saved for this vcpu, except the one pointed by
5096 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5097 * currently used, if running L2), and vmcs01 when running L2.
5098 */
5099static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5100{
5101 struct vmcs02_list *item, *n;
5102 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5103 if (vmx->loaded_vmcs != &item->vmcs02)
5104 free_loaded_vmcs(&item->vmcs02);
5105 list_del(&item->list);
5106 kfree(item);
5107 }
5108 vmx->nested.vmcs02_num = 0;
5109
5110 if (vmx->loaded_vmcs != &vmx->vmcs01)
5111 free_loaded_vmcs(&vmx->vmcs01);
5112}
5113
ec378aee
NHE		 5114/*
5115 * Emulate the VMXON instruction.
5116 * Currently, we just remember that VMX is active, and do not save or even
5117 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5118 * do not currently need to store anything in that guest-allocated memory
5119 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5120 * argument is different from the VMXON pointer (which the spec says they do).
5121 */
5122static int handle_vmon(struct kvm_vcpu *vcpu)
5123{
5124 struct kvm_segment cs;
5125 struct vcpu_vmx *vmx = to_vmx(vcpu);
5126
5127 /* The Intel VMX Instruction Reference lists a bunch of bits that
5128 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5129 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5130 * Otherwise, we should fail with #UD. We test these now:
5131 */
5132 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5133 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5134 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5135 kvm_queue_exception(vcpu, UD_VECTOR);
5136 return 1;
5137 }
5138
5139 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5140 if (is_long_mode(vcpu) && !cs.l) {
5141 kvm_queue_exception(vcpu, UD_VECTOR);
5142 return 1;
5143 }
5144
5145 if (vmx_get_cpl(vcpu)) {
5146 kvm_inject_gp(vcpu, 0);
5147 return 1;
5148 }
5149
ff2f6fe9
NHE		 5150 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5151 vmx->nested.vmcs02_num = 0;
5152
ec378aee
NHE		 5153 vmx->nested.vmxon = true;
5154
5155 skip_emulated_instruction(vcpu);
5156 return 1;
5157}
5158
5159/*
5160 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5161 * for running VMX instructions (except VMXON, whose prerequisites are
5162 * slightly different). It also specifies what exception to inject otherwise.
5163 */
5164static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5165{
5166 struct kvm_segment cs;
5167 struct vcpu_vmx *vmx = to_vmx(vcpu);
5168
5169 if (!vmx->nested.vmxon) {
5170 kvm_queue_exception(vcpu, UD_VECTOR);
5171 return 0;
5172 }
5173
5174 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5175 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5176 (is_long_mode(vcpu) && !cs.l)) {
5177 kvm_queue_exception(vcpu, UD_VECTOR);
5178 return 0;
5179 }
5180
5181 if (vmx_get_cpl(vcpu)) {
5182 kvm_inject_gp(vcpu, 0);
5183 return 0;
5184 }
5185
5186 return 1;
5187}
5188
5189/*
5190 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5191 * just stops using VMX.
5192 */
5193static void free_nested(struct vcpu_vmx *vmx)
5194{
5195 if (!vmx->nested.vmxon)
5196 return;
5197 vmx->nested.vmxon = false;
a9d30f33
NHE		 5198 if (vmx->nested.current_vmptr != -1ull) {
5199 kunmap(vmx->nested.current_vmcs12_page);
5200 nested_release_page(vmx->nested.current_vmcs12_page);
5201 vmx->nested.current_vmptr = -1ull;
5202 vmx->nested.current_vmcs12 = NULL;
5203 }
fe3ef05c
NHE		 5204 /* Unpin physical memory we referred to in current vmcs02 */
5205 if (vmx->nested.apic_access_page) {
5206 nested_release_page(vmx->nested.apic_access_page);
5207 vmx->nested.apic_access_page = 0;
5208 }
ff2f6fe9
NHE		 5209
5210 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5211}
5212
5213/* Emulate the VMXOFF instruction */
5214static int handle_vmoff(struct kvm_vcpu *vcpu)
5215{
5216 if (!nested_vmx_check_permission(vcpu))
5217 return 1;
5218 free_nested(to_vmx(vcpu));
5219 skip_emulated_instruction(vcpu);
5220 return 1;
5221}
5222
064aea77
NHE		 5223/*
5224 * Decode the memory-address operand of a vmx instruction, as recorded on an
5225 * exit caused by such an instruction (run by a guest hypervisor).
5226 * On success, returns 0. When the operand is invalid, returns 1 and throws
5227 * #UD or #GP.
5228 */
5229static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5230 unsigned long exit_qualification,
5231 u32 vmx_instruction_info, gva_t *ret)
5232{
5233 /*
5234 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5235 * Execution", on an exit, vmx_instruction_info holds most of the
5236 * addressing components of the operand. Only the displacement part
5237 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5238 * For how an actual address is calculated from all these components,
5239 * refer to Vol. 1, "Operand Addressing".
5240 */
5241 int scaling = vmx_instruction_info & 3;
5242 int addr_size = (vmx_instruction_info >> 7) & 7;
5243 bool is_reg = vmx_instruction_info & (1u << 10);
5244 int seg_reg = (vmx_instruction_info >> 15) & 7;
5245 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5246 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5247 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5248 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5249
5250 if (is_reg) {
5251 kvm_queue_exception(vcpu, UD_VECTOR);
5252 return 1;
5253 }
5254
5255 /* Addr = segment_base + offset */
5256 /* offset = base + [index * scale] + displacement */
5257 *ret = vmx_get_segment_base(vcpu, seg_reg);
5258 if (base_is_valid)
5259 *ret += kvm_register_read(vcpu, base_reg);
5260 if (index_is_valid)
5261 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5262 *ret += exit_qualification; /* holds the displacement */
5263
5264 if (addr_size == 1) /* 32 bit */
5265 *ret &= 0xffffffff;
5266
5267 /*
5268 * TODO: throw #GP (and return 1) in various cases that the VM*
5269 * instructions require it - e.g., offset beyond segment limit,
5270 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5271 * address, and so on. Currently these are not checked.
5272 */
5273 return 0;
5274}
5275
0140caea
NHE		 5276/*
5277 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5278 * set the success or error code of an emulated VMX instruction, as specified
5279 * by Vol 2B, VMX Instruction Reference, "Conventions".
5280 */
5281static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5282{
5283 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5284 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5285 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5286}
5287
5288static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5289{
5290 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5291 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5292 X86_EFLAGS_SF | X86_EFLAGS_OF))
5293 | X86_EFLAGS_CF);
5294}
5295
5296static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5297 u32 vm_instruction_error)
5298{
5299 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5300 /*
5301 * failValid writes the error number to the current VMCS, which
5302 * can't be done there isn't a current VMCS.
5303 */
5304 nested_vmx_failInvalid(vcpu);
5305 return;
5306 }
5307 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5308 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5309 X86_EFLAGS_SF | X86_EFLAGS_OF))
5310 | X86_EFLAGS_ZF);
5311 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5312}
5313
27d6c865
NHE		 5314/* Emulate the VMCLEAR instruction */
5315static int handle_vmclear(struct kvm_vcpu *vcpu)
5316{
5317 struct vcpu_vmx *vmx = to_vmx(vcpu);
5318 gva_t gva;
5319 gpa_t vmptr;
5320 struct vmcs12 *vmcs12;
5321 struct page *page;
5322 struct x86_exception e;
5323
5324 if (!nested_vmx_check_permission(vcpu))
5325 return 1;
5326
5327 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5328 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5329 return 1;
5330
5331 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5332 sizeof(vmptr), &e)) {
5333 kvm_inject_page_fault(vcpu, &e);
5334 return 1;
5335 }
5336
5337 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5338 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5339 skip_emulated_instruction(vcpu);
5340 return 1;
5341 }
5342
5343 if (vmptr == vmx->nested.current_vmptr) {
5344 kunmap(vmx->nested.current_vmcs12_page);
5345 nested_release_page(vmx->nested.current_vmcs12_page);
5346 vmx->nested.current_vmptr = -1ull;
5347 vmx->nested.current_vmcs12 = NULL;
5348 }
5349
5350 page = nested_get_page(vcpu, vmptr);
5351 if (page == NULL) {
5352 /*
5353 * For accurate processor emulation, VMCLEAR beyond available
5354 * physical memory should do nothing at all. However, it is
5355 * possible that a nested vmx bug, not a guest hypervisor bug,
5356 * resulted in this case, so let's shut down before doing any
5357 * more damage:
5358 */
5359 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5360 return 1;
5361 }
5362 vmcs12 = kmap(page);
5363 vmcs12->launch_state = 0;
5364 kunmap(page);
5365 nested_release_page(page);
5366
5367 nested_free_vmcs02(vmx, vmptr);
5368
5369 skip_emulated_instruction(vcpu);
5370 nested_vmx_succeed(vcpu);
5371 return 1;
5372}
5373
cd232ad0
NHE		 5374static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5375
5376/* Emulate the VMLAUNCH instruction */
5377static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5378{
5379 return nested_vmx_run(vcpu, true);
5380}
5381
5382/* Emulate the VMRESUME instruction */
5383static int handle_vmresume(struct kvm_vcpu *vcpu)
5384{
5385
5386 return nested_vmx_run(vcpu, false);
5387}
5388
49f705c5
NHE		 5389enum vmcs_field_type {
5390 VMCS_FIELD_TYPE_U16 = 0,
5391 VMCS_FIELD_TYPE_U64 = 1,
5392 VMCS_FIELD_TYPE_U32 = 2,
5393 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5394};
5395
5396static inline int vmcs_field_type(unsigned long field)
5397{
5398 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5399 return VMCS_FIELD_TYPE_U32;
5400 return (field >> 13) & 0x3 ;
5401}
5402
5403static inline int vmcs_field_readonly(unsigned long field)
5404{
5405 return (((field >> 10) & 0x3) == 1);
5406}
5407
5408/*
5409 * Read a vmcs12 field. Since these can have varying lengths and we return
5410 * one type, we chose the biggest type (u64) and zero-extend the return value
5411 * to that size. Note that the caller, handle_vmread, might need to use only
5412 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5413 * 64-bit fields are to be returned).
5414 */
5415static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5416 unsigned long field, u64 *ret)
5417{
5418 short offset = vmcs_field_to_offset(field);
5419 char *p;
5420
5421 if (offset < 0)
5422 return 0;
5423
5424 p = ((char *)(get_vmcs12(vcpu))) + offset;
5425
5426 switch (vmcs_field_type(field)) {
5427 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5428 *ret = *((natural_width *)p);
5429 return 1;
5430 case VMCS_FIELD_TYPE_U16:
5431 *ret = *((u16 *)p);
5432 return 1;
5433 case VMCS_FIELD_TYPE_U32:
5434 *ret = *((u32 *)p);
5435 return 1;
5436 case VMCS_FIELD_TYPE_U64:
5437 *ret = *((u64 *)p);
5438 return 1;
5439 default:
5440 return 0; /* can never happen. */
5441 }
5442}
5443
5444/*
5445 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5446 * used before) all generate the same failure when it is missing.
5447 */
5448static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5449{
5450 struct vcpu_vmx *vmx = to_vmx(vcpu);
5451 if (vmx->nested.current_vmptr == -1ull) {
5452 nested_vmx_failInvalid(vcpu);
5453 skip_emulated_instruction(vcpu);
5454 return 0;
5455 }
5456 return 1;
5457}
5458
5459static int handle_vmread(struct kvm_vcpu *vcpu)
5460{
5461 unsigned long field;
5462 u64 field_value;
5463 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5464 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5465 gva_t gva = 0;
5466
5467 if (!nested_vmx_check_permission(vcpu) ||
5468 !nested_vmx_check_vmcs12(vcpu))
5469 return 1;
5470
5471 /* Decode instruction info and find the field to read */
5472 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5473 /* Read the field, zero-extended to a u64 field_value */
5474 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5475 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5476 skip_emulated_instruction(vcpu);
5477 return 1;
5478 }
5479 /*
5480 * Now copy part of this value to register or memory, as requested.
5481 * Note that the number of bits actually copied is 32 or 64 depending
5482 * on the guest's mode (32 or 64 bit), not on the given field's length.
5483 */
5484 if (vmx_instruction_info & (1u << 10)) {
5485 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5486 field_value);
5487 } else {
5488 if (get_vmx_mem_address(vcpu, exit_qualification,
5489 vmx_instruction_info, &gva))
5490 return 1;
5491 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5492 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5493 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5494 }
5495
5496 nested_vmx_succeed(vcpu);
5497 skip_emulated_instruction(vcpu);
5498 return 1;
5499}
5500
5501
5502static int handle_vmwrite(struct kvm_vcpu *vcpu)
5503{
5504 unsigned long field;
5505 gva_t gva;
5506 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5507 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5508 char *p;
5509 short offset;
5510 /* The value to write might be 32 or 64 bits, depending on L1's long
5511 * mode, and eventually we need to write that into a field of several
5512 * possible lengths. The code below first zero-extends the value to 64
5513 * bit (field_value), and then copies only the approriate number of
5514 * bits into the vmcs12 field.
5515 */
5516 u64 field_value = 0;
5517 struct x86_exception e;
5518
5519 if (!nested_vmx_check_permission(vcpu) ||
5520 !nested_vmx_check_vmcs12(vcpu))
5521 return 1;
5522
5523 if (vmx_instruction_info & (1u << 10))
5524 field_value = kvm_register_read(vcpu,
5525 (((vmx_instruction_info) >> 3) & 0xf));
5526 else {
5527 if (get_vmx_mem_address(vcpu, exit_qualification,
5528 vmx_instruction_info, &gva))
5529 return 1;
5530 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5531 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5532 kvm_inject_page_fault(vcpu, &e);
5533 return 1;
5534 }
5535 }
5536
5537
5538 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5539 if (vmcs_field_readonly(field)) {
5540 nested_vmx_failValid(vcpu,
5541 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5542 skip_emulated_instruction(vcpu);
5543 return 1;
5544 }
5545
5546 offset = vmcs_field_to_offset(field);
5547 if (offset < 0) {
5548 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5549 skip_emulated_instruction(vcpu);
5550 return 1;
5551 }
5552 p = ((char *) get_vmcs12(vcpu)) + offset;
5553
5554 switch (vmcs_field_type(field)) {
5555 case VMCS_FIELD_TYPE_U16:
5556 *(u16 *)p = field_value;
5557 break;
5558 case VMCS_FIELD_TYPE_U32:
5559 *(u32 *)p = field_value;
5560 break;
5561 case VMCS_FIELD_TYPE_U64:
5562 *(u64 *)p = field_value;
5563 break;
5564 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5565 *(natural_width *)p = field_value;
5566 break;
5567 default:
5568 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5569 skip_emulated_instruction(vcpu);
5570 return 1;
5571 }
5572
5573 nested_vmx_succeed(vcpu);
5574 skip_emulated_instruction(vcpu);
5575 return 1;
5576}
5577
63846663
NHE		 5578/* Emulate the VMPTRLD instruction */
5579static int handle_vmptrld(struct kvm_vcpu *vcpu)
5580{
5581 struct vcpu_vmx *vmx = to_vmx(vcpu);
5582 gva_t gva;
5583 gpa_t vmptr;
5584 struct x86_exception e;
5585
5586 if (!nested_vmx_check_permission(vcpu))
5587 return 1;
5588
5589 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5590 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5591 return 1;
5592
5593 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5594 sizeof(vmptr), &e)) {
5595 kvm_inject_page_fault(vcpu, &e);
5596 return 1;
5597 }
5598
5599 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5600 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5601 skip_emulated_instruction(vcpu);
5602 return 1;
5603 }
5604
5605 if (vmx->nested.current_vmptr != vmptr) {
5606 struct vmcs12 *new_vmcs12;
5607 struct page *page;
5608 page = nested_get_page(vcpu, vmptr);
5609 if (page == NULL) {
5610 nested_vmx_failInvalid(vcpu);
5611 skip_emulated_instruction(vcpu);
5612 return 1;
5613 }
5614 new_vmcs12 = kmap(page);
5615 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5616 kunmap(page);
5617 nested_release_page_clean(page);
5618 nested_vmx_failValid(vcpu,
5619 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5620 skip_emulated_instruction(vcpu);
5621 return 1;
5622 }
5623 if (vmx->nested.current_vmptr != -1ull) {
5624 kunmap(vmx->nested.current_vmcs12_page);
5625 nested_release_page(vmx->nested.current_vmcs12_page);
5626 }
5627
5628 vmx->nested.current_vmptr = vmptr;
5629 vmx->nested.current_vmcs12 = new_vmcs12;
5630 vmx->nested.current_vmcs12_page = page;
5631 }
5632
5633 nested_vmx_succeed(vcpu);
5634 skip_emulated_instruction(vcpu);
5635 return 1;
5636}
5637
6a4d7550
NHE		 5638/* Emulate the VMPTRST instruction */
5639static int handle_vmptrst(struct kvm_vcpu *vcpu)
5640{
5641 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5642 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5643 gva_t vmcs_gva;
5644 struct x86_exception e;
5645
5646 if (!nested_vmx_check_permission(vcpu))
5647 return 1;
5648
5649 if (get_vmx_mem_address(vcpu, exit_qualification,
5650 vmx_instruction_info, &vmcs_gva))
5651 return 1;
5652 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5653 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5654 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5655 sizeof(u64), &e)) {
5656 kvm_inject_page_fault(vcpu, &e);
5657 return 1;
5658 }
5659 nested_vmx_succeed(vcpu);
5660 skip_emulated_instruction(vcpu);
5661 return 1;
5662}
5663
6aa8b732
AK		 5664/*
5665 * The exit handlers return 1 if the exit was handled fully and guest execution
5666 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5667 * to be done to userspace and return 0.
5668 */
772e0318 5669static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5670 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5671 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5672 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5673 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5674 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5675 [EXIT_REASON_CR_ACCESS] = handle_cr,
5676 [EXIT_REASON_DR_ACCESS] = handle_dr,
5677 [EXIT_REASON_CPUID] = handle_cpuid,
5678 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5679 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5680 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5681 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5682 [EXIT_REASON_INVD] = handle_invd,
a7052897 5683 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5684 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5685 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5686 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5687 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5688 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5689 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5690 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5691 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5692 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5693 [EXIT_REASON_VMOFF] = handle_vmoff,
5694 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5695 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5696 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5697 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5698 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5699 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5700 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5701 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5702 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5703 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5704 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5705 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5706};
5707
5708static const int kvm_vmx_max_exit_handlers =
50a3485c 5709 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5710
644d711a
NHE		 5711/*
5712 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5713 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5714 * disinterest in the current event (read or write a specific MSR) by using an
5715 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5716 */
5717static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5718 struct vmcs12 *vmcs12, u32 exit_reason)
5719{
5720 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5721 gpa_t bitmap;
5722
5723 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5724 return 1;
5725
5726 /*
5727 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5728 * for the four combinations of read/write and low/high MSR numbers.
5729 * First we need to figure out which of the four to use:
5730 */
5731 bitmap = vmcs12->msr_bitmap;
5732 if (exit_reason == EXIT_REASON_MSR_WRITE)
5733 bitmap += 2048;
5734 if (msr_index >= 0xc0000000) {
5735 msr_index -= 0xc0000000;
5736 bitmap += 1024;
5737 }
5738
5739 /* Then read the msr_index'th bit from this bitmap: */
5740 if (msr_index < 1024*8) {
5741 unsigned char b;
5742 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5743 return 1 & (b >> (msr_index & 7));
5744 } else
5745 return 1; /* let L1 handle the wrong parameter */
5746}
5747
5748/*
5749 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5750 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5751 * intercept (via guest_host_mask etc.) the current event.
5752 */
5753static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5754 struct vmcs12 *vmcs12)
5755{
5756 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5757 int cr = exit_qualification & 15;
5758 int reg = (exit_qualification >> 8) & 15;
5759 unsigned long val = kvm_register_read(vcpu, reg);
5760
5761 switch ((exit_qualification >> 4) & 3) {
5762 case 0: /* mov to cr */
5763 switch (cr) {
5764 case 0:
5765 if (vmcs12->cr0_guest_host_mask &
5766 (val ^ vmcs12->cr0_read_shadow))
5767 return 1;
5768 break;
5769 case 3:
5770 if ((vmcs12->cr3_target_count >= 1 &&
5771 vmcs12->cr3_target_value0 == val) ||
5772 (vmcs12->cr3_target_count >= 2 &&
5773 vmcs12->cr3_target_value1 == val) ||
5774 (vmcs12->cr3_target_count >= 3 &&
5775 vmcs12->cr3_target_value2 == val) ||
5776 (vmcs12->cr3_target_count >= 4 &&
5777 vmcs12->cr3_target_value3 == val))
5778 return 0;
5779 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5780 return 1;
5781 break;
5782 case 4:
5783 if (vmcs12->cr4_guest_host_mask &
5784 (vmcs12->cr4_read_shadow ^ val))
5785 return 1;
5786 break;
5787 case 8:
5788 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5789 return 1;
5790 break;
5791 }
5792 break;
5793 case 2: /* clts */
5794 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5795 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5796 return 1;
5797 break;
5798 case 1: /* mov from cr */
5799 switch (cr) {
5800 case 3:
5801 if (vmcs12->cpu_based_vm_exec_control &
5802 CPU_BASED_CR3_STORE_EXITING)
5803 return 1;
5804 break;
5805 case 8:
5806 if (vmcs12->cpu_based_vm_exec_control &
5807 CPU_BASED_CR8_STORE_EXITING)
5808 return 1;
5809 break;
5810 }
5811 break;
5812 case 3: /* lmsw */
5813 /*
5814 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5815 * cr0. Other attempted changes are ignored, with no exit.
5816 */
5817 if (vmcs12->cr0_guest_host_mask & 0xe &
5818 (val ^ vmcs12->cr0_read_shadow))
5819 return 1;
5820 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5821 !(vmcs12->cr0_read_shadow & 0x1) &&
5822 (val & 0x1))
5823 return 1;
5824 break;
5825 }
5826 return 0;
5827}
5828
5829/*
5830 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5831 * should handle it ourselves in L0 (and then continue L2). Only call this
5832 * when in is_guest_mode (L2).
5833 */
5834static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5835{
5836 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5837 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5838 struct vcpu_vmx *vmx = to_vmx(vcpu);
5839 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5840
5841 if (vmx->nested.nested_run_pending)
5842 return 0;
5843
5844 if (unlikely(vmx->fail)) {
bd80158a
JK		 5845 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5846 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5847 return 1;
5848 }
5849
5850 switch (exit_reason) {
5851 case EXIT_REASON_EXCEPTION_NMI:
5852 if (!is_exception(intr_info))
5853 return 0;
5854 else if (is_page_fault(intr_info))
5855 return enable_ept;
5856 return vmcs12->exception_bitmap &
5857 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5858 case EXIT_REASON_EXTERNAL_INTERRUPT:
5859 return 0;
5860 case EXIT_REASON_TRIPLE_FAULT:
5861 return 1;
5862 case EXIT_REASON_PENDING_INTERRUPT:
5863 case EXIT_REASON_NMI_WINDOW:
5864 /*
5865 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5866 * (aka Interrupt Window Exiting) only when L1 turned it on,
5867 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5868 * Same for NMI Window Exiting.
5869 */
5870 return 1;
5871 case EXIT_REASON_TASK_SWITCH:
5872 return 1;
5873 case EXIT_REASON_CPUID:
5874 return 1;
5875 case EXIT_REASON_HLT:
5876 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5877 case EXIT_REASON_INVD:
5878 return 1;
5879 case EXIT_REASON_INVLPG:
5880 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5881 case EXIT_REASON_RDPMC:
5882 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5883 case EXIT_REASON_RDTSC:
5884 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5885 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5886 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5887 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5888 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5889 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5890 /*
5891 * VMX instructions trap unconditionally. This allows L1 to
5892 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5893 */
5894 return 1;
5895 case EXIT_REASON_CR_ACCESS:
5896 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5897 case EXIT_REASON_DR_ACCESS:
5898 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5899 case EXIT_REASON_IO_INSTRUCTION:
5900 /* TODO: support IO bitmaps */
5901 return 1;
5902 case EXIT_REASON_MSR_READ:
5903 case EXIT_REASON_MSR_WRITE:
5904 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5905 case EXIT_REASON_INVALID_STATE:
5906 return 1;
5907 case EXIT_REASON_MWAIT_INSTRUCTION:
5908 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5909 case EXIT_REASON_MONITOR_INSTRUCTION:
5910 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5911 case EXIT_REASON_PAUSE_INSTRUCTION:
5912 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5913 nested_cpu_has2(vmcs12,
5914 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5915 case EXIT_REASON_MCE_DURING_VMENTRY:
5916 return 0;
5917 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5918 return 1;
5919 case EXIT_REASON_APIC_ACCESS:
5920 return nested_cpu_has2(vmcs12,
5921 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5922 case EXIT_REASON_EPT_VIOLATION:
5923 case EXIT_REASON_EPT_MISCONFIG:
5924 return 0;
5925 case EXIT_REASON_WBINVD:
5926 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5927 case EXIT_REASON_XSETBV:
5928 return 1;
5929 default:
5930 return 1;
5931 }
5932}
5933
586f9607
AK		 5934static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5935{
5936 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5937 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5938}
5939
6aa8b732
AK		 5940/*
5941 * The guest has exited. See if we can fix it or if we need userspace
5942 * assistance.
5943 */
851ba692 5944static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5945{
29bd8a78 5946 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5947 u32 exit_reason = vmx->exit_reason;
1155f76a 5948 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5949
80ced186
MG		 5950 /* If guest state is invalid, start emulating */
5951 if (vmx->emulation_required && emulate_invalid_guest_state)
5952 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5953
b6f1250e
NHE		 5954 /*
5955 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5956 * we did not inject a still-pending event to L1 now because of
5957 * nested_run_pending, we need to re-enable this bit.
5958 */
5959 if (vmx->nested.nested_run_pending)
5960 kvm_make_request(KVM_REQ_EVENT, vcpu);
5961
509c75ea
NHE		 5962 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5963 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5964 vmx->nested.nested_run_pending = 1;
5965 else
5966 vmx->nested.nested_run_pending = 0;
5967
5968 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5969 nested_vmx_vmexit(vcpu);
5970 return 1;
5971 }
5972
5120702e
MG		 5973 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5974 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5975 vcpu->run->fail_entry.hardware_entry_failure_reason
5976 = exit_reason;
5977 return 0;
5978 }
5979
29bd8a78 5980 if (unlikely(vmx->fail)) {
851ba692
AK		 5981 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5982 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5983 = vmcs_read32(VM_INSTRUCTION_ERROR);
5984 return 0;
5985 }
6aa8b732 5986
b9bf6882
XG		 5987 /*
5988 * Note:
5989 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5990 * delivery event since it indicates guest is accessing MMIO.
5991 * The vm-exit can be triggered again after return to guest that
5992 * will cause infinite loop.
5993 */
d77c26fc 5994 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5995 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 5996 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 5997 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5998 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5999 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6000 vcpu->run->internal.ndata = 2;
6001 vcpu->run->internal.data[0] = vectoring_info;
6002 vcpu->run->internal.data[1] = exit_reason;
6003 return 0;
6004 }
3b86cd99 6005
644d711a
NHE		 6006 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6007 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6008 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6009 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6010 vmx->soft_vnmi_blocked = 0;
3b86cd99 6011 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6012 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6013 /*
6014 * This CPU don't support us in finding the end of an
6015 * NMI-blocked window if the guest runs with IRQs
6016 * disabled. So we pull the trigger after 1 s of
6017 * futile waiting, but inform the user about this.
6018 */
6019 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6020 "state on VCPU %d after 1 s timeout\n",
6021 __func__, vcpu->vcpu_id);
6022 vmx->soft_vnmi_blocked = 0;
3b86cd99 6023 }
3b86cd99
JK		 6024 }
6025
6aa8b732
AK		 6026 if (exit_reason < kvm_vmx_max_exit_handlers
6027 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6028 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6029 else {
851ba692
AK		 6030 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6031 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6032 }
6033 return 0;
6034}
6035
95ba8273 6036static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6037{
95ba8273 6038 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6039 vmcs_write32(TPR_THRESHOLD, 0);
6040 return;
6041 }
6042
95ba8273 6043 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6044}
6045
51aa01d1 6046static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6047{
00eba012
AK		 6048 u32 exit_intr_info;
6049
6050 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6051 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6052 return;
6053
c5ca8e57 6054 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6055 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6056
6057 /* Handle machine checks before interrupts are enabled */
00eba012 6058 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6059 kvm_machine_check();
6060
20f65983 6061 /* We need to handle NMIs before interrupts are enabled */
00eba012 6062 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6063 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6064 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6065 asm("int $2");
ff9d07a0
ZY		 6066 kvm_after_handle_nmi(&vmx->vcpu);
6067 }
51aa01d1 6068}
20f65983 6069
51aa01d1
AK		 6070static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6071{
c5ca8e57 6072 u32 exit_intr_info;
51aa01d1
AK		 6073 bool unblock_nmi;
6074 u8 vector;
6075 bool idtv_info_valid;
6076
6077 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6078
cf393f75 6079 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6080 if (vmx->nmi_known_unmasked)
6081 return;
c5ca8e57
AK		 6082 /*
6083 * Can't use vmx->exit_intr_info since we're not sure what
6084 * the exit reason is.
6085 */
6086 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6087 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6088 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6089 /*
7b4a25cb 6090 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6091 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6092 * a guest IRET fault.
7b4a25cb
GN		 6093 * SDM 3: 23.2.2 (September 2008)
6094 * Bit 12 is undefined in any of the following cases:
6095 * If the VM exit sets the valid bit in the IDT-vectoring
6096 * information field.
6097 * If the VM exit is due to a double fault.
cf393f75 6098 */
7b4a25cb
GN		 6099 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6100 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6101 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6102 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6103 else
6104 vmx->nmi_known_unmasked =
6105 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6106 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6107 } else if (unlikely(vmx->soft_vnmi_blocked))
6108 vmx->vnmi_blocked_time +=
6109 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6110}
6111
83422e17
AK		 6112static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6113 u32 idt_vectoring_info,
6114 int instr_len_field,
6115 int error_code_field)
51aa01d1 6116{
51aa01d1
AK		 6117 u8 vector;
6118 int type;
6119 bool idtv_info_valid;
6120
6121 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6122
37b96e98
GN		 6123 vmx->vcpu.arch.nmi_injected = false;
6124 kvm_clear_exception_queue(&vmx->vcpu);
6125 kvm_clear_interrupt_queue(&vmx->vcpu);
6126
6127 if (!idtv_info_valid)
6128 return;
6129
3842d135
AK		 6130 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6131
668f612f
AK		 6132 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6133 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6134
64a7ec06 6135 switch (type) {
37b96e98
GN		 6136 case INTR_TYPE_NMI_INTR:
6137 vmx->vcpu.arch.nmi_injected = true;
668f612f 6138 /*
7b4a25cb 6139 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6140 * Clear bit "block by NMI" before VM entry if a NMI
6141 * delivery faulted.
668f612f 6142 */
654f06fc 6143 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6144 break;
37b96e98 6145 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6146 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6147 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6148 /* fall through */
6149 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6150 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6151 u32 err = vmcs_read32(error_code_field);
37b96e98 6152 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6153 } else
6154 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6155 break;
66fd3f7f
GN		 6156 case INTR_TYPE_SOFT_INTR:
6157 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6158 vmcs_read32(instr_len_field);
66fd3f7f 6159 /* fall through */
37b96e98 6160 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6161 kvm_queue_interrupt(&vmx->vcpu, vector,
6162 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6163 break;
6164 default:
6165 break;
f7d9238f 6166 }
cf393f75
AK		 6167}
6168
83422e17
AK		 6169static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6170{
66c78ae4
NHE		 6171 if (is_guest_mode(&vmx->vcpu))
6172 return;
83422e17
AK		 6173 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6174 VM_EXIT_INSTRUCTION_LEN,
6175 IDT_VECTORING_ERROR_CODE);
6176}
6177
b463a6f7
AK		 6178static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6179{
66c78ae4
NHE		 6180 if (is_guest_mode(vcpu))
6181 return;
b463a6f7
AK		 6182 __vmx_complete_interrupts(to_vmx(vcpu),
6183 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6184 VM_ENTRY_INSTRUCTION_LEN,
6185 VM_ENTRY_EXCEPTION_ERROR_CODE);
6186
6187 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6188}
6189
d7cd9796
GN		 6190static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6191{
6192 int i, nr_msrs;
6193 struct perf_guest_switch_msr *msrs;
6194
6195 msrs = perf_guest_get_msrs(&nr_msrs);
6196
6197 if (!msrs)
6198 return;
6199
6200 for (i = 0; i < nr_msrs; i++)
6201 if (msrs[i].host == msrs[i].guest)
6202 clear_atomic_switch_msr(vmx, msrs[i].msr);
6203 else
6204 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6205 msrs[i].host);
6206}
6207
a3b5ba49 6208static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6209{
a2fa3e9f 6210 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6211 unsigned long debugctlmsr;
104f226b 6212
66c78ae4
NHE		 6213 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6214 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6215 if (vmcs12->idt_vectoring_info_field &
6216 VECTORING_INFO_VALID_MASK) {
6217 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6218 vmcs12->idt_vectoring_info_field);
6219 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6220 vmcs12->vm_exit_instruction_len);
6221 if (vmcs12->idt_vectoring_info_field &
6222 VECTORING_INFO_DELIVER_CODE_MASK)
6223 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6224 vmcs12->idt_vectoring_error_code);
6225 }
6226 }
6227
104f226b
AK		 6228 /* Record the guest's net vcpu time for enforced NMI injections. */
6229 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6230 vmx->entry_time = ktime_get();
6231
6232 /* Don't enter VMX if guest state is invalid, let the exit handler
6233 start emulation until we arrive back to a valid state */
6234 if (vmx->emulation_required && emulate_invalid_guest_state)
6235 return;
6236
6237 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6238 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6239 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6240 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6241
6242 /* When single-stepping over STI and MOV SS, we must clear the
6243 * corresponding interruptibility bits in the guest state. Otherwise
6244 * vmentry fails as it then expects bit 14 (BS) in pending debug
6245 * exceptions being set, but that's not correct for the guest debugging
6246 * case. */
6247 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6248 vmx_set_interrupt_shadow(vcpu, 0);
6249
d7cd9796 6250 atomic_switch_perf_msrs(vmx);
2a7921b7 6251 debugctlmsr = get_debugctlmsr();
d7cd9796 6252
d462b819 6253 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6254 asm(
6aa8b732 6255 /* Store host registers */
b188c81f
AK		 6256 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6257 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6258 "push %%" _ASM_CX " \n\t"
6259 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6260 "je 1f \n\t"
b188c81f 6261 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6262 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6263 "1: \n\t"
d3edefc0 6264 /* Reload cr2 if changed */
b188c81f
AK		 6265 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6266 "mov %%cr2, %%" _ASM_DX " \n\t"
6267 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6268 "je 2f \n\t"
b188c81f 6269 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6270 "2: \n\t"
6aa8b732 6271 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6272 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6273 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6274 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6275 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6276 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6277 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6278 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6279 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6280#ifdef CONFIG_X86_64
e08aa78a
AK		 6281 "mov %c[r8](%0), %%r8 \n\t"
6282 "mov %c[r9](%0), %%r9 \n\t"
6283 "mov %c[r10](%0), %%r10 \n\t"
6284 "mov %c[r11](%0), %%r11 \n\t"
6285 "mov %c[r12](%0), %%r12 \n\t"
6286 "mov %c[r13](%0), %%r13 \n\t"
6287 "mov %c[r14](%0), %%r14 \n\t"
6288 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6289#endif
b188c81f 6290 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6291
6aa8b732 6292 /* Enter guest mode */
83287ea4 6293 "jne 1f \n\t"
4ecac3fd 6294 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6295 "jmp 2f \n\t"
6296 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6297 "2: "
6aa8b732 6298 /* Save guest registers, load host registers, keep flags */
b188c81f 6299 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6300 "pop %0 \n\t"
b188c81f
AK		 6301 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6302 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6303 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6304 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6305 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6306 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6307 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6308#ifdef CONFIG_X86_64
e08aa78a
AK		 6309 "mov %%r8, %c[r8](%0) \n\t"
6310 "mov %%r9, %c[r9](%0) \n\t"
6311 "mov %%r10, %c[r10](%0) \n\t"
6312 "mov %%r11, %c[r11](%0) \n\t"
6313 "mov %%r12, %c[r12](%0) \n\t"
6314 "mov %%r13, %c[r13](%0) \n\t"
6315 "mov %%r14, %c[r14](%0) \n\t"
6316 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6317#endif
b188c81f
AK		 6318 "mov %%cr2, %%" _ASM_AX " \n\t"
6319 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6320
b188c81f 6321 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6322 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6323 ".pushsection .rodata \n\t"
6324 ".global vmx_return \n\t"
6325 "vmx_return: " _ASM_PTR " 2b \n\t"
6326 ".popsection"
e08aa78a 6327 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6328 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6329 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6330 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6331 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6332 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6333 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6334 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6335 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6336 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6337 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6338#ifdef CONFIG_X86_64
ad312c7c
ZX		 6339 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6340 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6341 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6342 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6343 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6344 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6345 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6346 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6347#endif
40712fae
AK		 6348 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6349 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6350 : "cc", "memory"
6351#ifdef CONFIG_X86_64
b188c81f 6352 , "rax", "rbx", "rdi", "rsi"
c2036300 6353 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6354#else
6355 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6356#endif
6357 );
6aa8b732 6358
2a7921b7
GN		 6359 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6360 if (debugctlmsr)
6361 update_debugctlmsr(debugctlmsr);
6362
aa67f609
AK		 6363#ifndef CONFIG_X86_64
6364 /*
6365 * The sysexit path does not restore ds/es, so we must set them to
6366 * a reasonable value ourselves.
6367 *
6368 * We can't defer this to vmx_load_host_state() since that function
6369 * may be executed in interrupt context, which saves and restore segments
6370 * around it, nullifying its effect.
6371 */
6372 loadsegment(ds, __USER_DS);
6373 loadsegment(es, __USER_DS);
6374#endif
6375
6de4f3ad 6376 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6377 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6378 | (1 << VCPU_EXREG_CPL)
aff48baa 6379 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6380 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6381 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6382 vcpu->arch.regs_dirty = 0;
6383
1155f76a
AK		 6384 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6385
66c78ae4
NHE		 6386 if (is_guest_mode(vcpu)) {
6387 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6388 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6389 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6390 vmcs12->idt_vectoring_error_code =
6391 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6392 vmcs12->vm_exit_instruction_len =
6393 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6394 }
6395 }
6396
d462b819 6397 vmx->loaded_vmcs->launched = 1;
1b6269db 6398
51aa01d1 6399 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6400 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6401
6402 vmx_complete_atomic_exit(vmx);
6403 vmx_recover_nmi_blocking(vmx);
cf393f75 6404 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6405}
6406
6aa8b732
AK		 6407static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6408{
fb3f0f51
RR		 6409 struct vcpu_vmx *vmx = to_vmx(vcpu);
6410
cdbecfc3 6411 free_vpid(vmx);
ec378aee 6412 free_nested(vmx);
d462b819 6413 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6414 kfree(vmx->guest_msrs);
6415 kvm_vcpu_uninit(vcpu);
a4770347 6416 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6417}
6418
fb3f0f51 6419static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6420{
fb3f0f51 6421 int err;
c16f862d 6422 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6423 int cpu;
6aa8b732 6424
a2fa3e9f 6425 if (!vmx)
fb3f0f51
RR		 6426 return ERR_PTR(-ENOMEM);
6427
2384d2b3
SY		 6428 allocate_vpid(vmx);
6429
fb3f0f51
RR		 6430 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6431 if (err)
6432 goto free_vcpu;
965b58a5 6433
a2fa3e9f 6434 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6435 err = -ENOMEM;
fb3f0f51 6436 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6437 goto uninit_vcpu;
6438 }
965b58a5 6439
d462b819
NHE		 6440 vmx->loaded_vmcs = &vmx->vmcs01;
6441 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6442 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6443 goto free_msrs;
d462b819
NHE		 6444 if (!vmm_exclusive)
6445 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6446 loaded_vmcs_init(vmx->loaded_vmcs);
6447 if (!vmm_exclusive)
6448 kvm_cpu_vmxoff();
a2fa3e9f 6449
15ad7146
AK		 6450 cpu = get_cpu();
6451 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6452 vmx->vcpu.cpu = cpu;
8b9cf98c 6453 err = vmx_vcpu_setup(vmx);
fb3f0f51 6454 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6455 put_cpu();
fb3f0f51
RR		 6456 if (err)
6457 goto free_vmcs;
5e4a0b3c 6458 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6459 err = alloc_apic_access_page(kvm);
6460 if (err)
5e4a0b3c 6461 goto free_vmcs;
fb3f0f51 6462
b927a3ce
SY		 6463 if (enable_ept) {
6464 if (!kvm->arch.ept_identity_map_addr)
6465 kvm->arch.ept_identity_map_addr =
6466 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6467 err = -ENOMEM;
b7ebfb05
SY		 6468 if (alloc_identity_pagetable(kvm) != 0)
6469 goto free_vmcs;
93ea5388
GN		 6470 if (!init_rmode_identity_map(kvm))
6471 goto free_vmcs;
b927a3ce 6472 }
b7ebfb05 6473
a9d30f33
NHE		 6474 vmx->nested.current_vmptr = -1ull;
6475 vmx->nested.current_vmcs12 = NULL;
6476
fb3f0f51
RR		 6477 return &vmx->vcpu;
6478
6479free_vmcs:
5f3fbc34 6480 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6481free_msrs:
fb3f0f51
RR		 6482 kfree(vmx->guest_msrs);
6483uninit_vcpu:
6484 kvm_vcpu_uninit(&vmx->vcpu);
6485free_vcpu:
cdbecfc3 6486 free_vpid(vmx);
a4770347 6487 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6488 return ERR_PTR(err);
6aa8b732
AK		 6489}
6490
002c7f7c
YS		 6491static void __init vmx_check_processor_compat(void *rtn)
6492{
6493 struct vmcs_config vmcs_conf;
6494
6495 *(int *)rtn = 0;
6496 if (setup_vmcs_config(&vmcs_conf) < 0)
6497 *(int *)rtn = -EIO;
6498 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6499 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6500 smp_processor_id());
6501 *(int *)rtn = -EIO;
6502 }
6503}
6504
67253af5
SY		 6505static int get_ept_level(void)
6506{
6507 return VMX_EPT_DEFAULT_GAW + 1;
6508}
6509
4b12f0de 6510static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6511{
4b12f0de
SY		 6512 u64 ret;
6513
522c68c4
SY		 6514 /* For VT-d and EPT combination
6515 * 1. MMIO: always map as UC
6516 * 2. EPT with VT-d:
6517 * a. VT-d without snooping control feature: can't guarantee the
6518 * result, try to trust guest.
6519 * b. VT-d with snooping control feature: snooping control feature of
6520 * VT-d engine can guarantee the cache correctness. Just set it
6521 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6522 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6523 * consistent with host MTRR
6524 */
4b12f0de
SY		 6525 if (is_mmio)
6526 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6527 else if (vcpu->kvm->arch.iommu_domain &&
6528 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6529 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6530 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6531 else
522c68c4 6532 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6533 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6534
6535 return ret;
64d4d521
SY		 6536}
6537
17cc3935 6538static int vmx_get_lpage_level(void)
344f414f 6539{
878403b7
SY		 6540 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6541 return PT_DIRECTORY_LEVEL;
6542 else
6543 /* For shadow and EPT supported 1GB page */
6544 return PT_PDPE_LEVEL;
344f414f
JR		 6545}
6546
0e851880
SY		 6547static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6548{
4e47c7a6
SY		 6549 struct kvm_cpuid_entry2 *best;
6550 struct vcpu_vmx *vmx = to_vmx(vcpu);
6551 u32 exec_control;
6552
6553 vmx->rdtscp_enabled = false;
6554 if (vmx_rdtscp_supported()) {
6555 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6556 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6557 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6558 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6559 vmx->rdtscp_enabled = true;
6560 else {
6561 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6562 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6563 exec_control);
6564 }
6565 }
6566 }
ad756a16
MJ		 6567
6568 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6569 /* Exposing INVPCID only when PCID is exposed */
6570 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6571 if (vmx_invpcid_supported() &&
4f977045 6572 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16
MJ		 6573 guest_cpuid_has_pcid(vcpu)) {
6574 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6575 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6576 exec_control);
6577 } else {
6578 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6579 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6580 exec_control);
6581 if (best)
4f977045 6582 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6583 }
0e851880
SY		 6584}
6585
d4330ef2
JR		 6586static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6587{
7b8050f5
NHE		 6588 if (func == 1 && nested)
6589 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6590}
6591
fe3ef05c
NHE		 6592/*
6593 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6594 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6595 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6596 * guest in a way that will both be appropriate to L1's requests, and our
6597 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6598 * function also has additional necessary side-effects, like setting various
6599 * vcpu->arch fields.
6600 */
6601static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6602{
6603 struct vcpu_vmx *vmx = to_vmx(vcpu);
6604 u32 exec_control;
6605
6606 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6607 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6608 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6609 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6610 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6611 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6612 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6613 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6614 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6615 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6616 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6617 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6618 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6619 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6620 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6621 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6622 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6623 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6624 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6625 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6626 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6627 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6628 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6629 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6630 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6631 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6632 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6633 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6634 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6635 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6636 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6637 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6638 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6639 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6640 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6641 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6642
6643 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6644 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6645 vmcs12->vm_entry_intr_info_field);
6646 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6647 vmcs12->vm_entry_exception_error_code);
6648 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6649 vmcs12->vm_entry_instruction_len);
6650 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6651 vmcs12->guest_interruptibility_info);
6652 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6653 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6654 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6655 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6656 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6657 vmcs12->guest_pending_dbg_exceptions);
6658 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6659 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6660
6661 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6662
6663 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6664 (vmcs_config.pin_based_exec_ctrl |
6665 vmcs12->pin_based_vm_exec_control));
6666
6667 /*
6668 * Whether page-faults are trapped is determined by a combination of
6669 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6670 * If enable_ept, L0 doesn't care about page faults and we should
6671 * set all of these to L1's desires. However, if !enable_ept, L0 does
6672 * care about (at least some) page faults, and because it is not easy
6673 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6674 * to exit on each and every L2 page fault. This is done by setting
6675 * MASK=MATCH=0 and (see below) EB.PF=1.
6676 * Note that below we don't need special code to set EB.PF beyond the
6677 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6678 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6679 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6680 *
6681 * A problem with this approach (when !enable_ept) is that L1 may be
6682 * injected with more page faults than it asked for. This could have
6683 * caused problems, but in practice existing hypervisors don't care.
6684 * To fix this, we will need to emulate the PFEC checking (on the L1
6685 * page tables), using walk_addr(), when injecting PFs to L1.
6686 */
6687 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6688 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6689 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6690 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6691
6692 if (cpu_has_secondary_exec_ctrls()) {
6693 u32 exec_control = vmx_secondary_exec_control(vmx);
6694 if (!vmx->rdtscp_enabled)
6695 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6696 /* Take the following fields only from vmcs12 */
6697 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6698 if (nested_cpu_has(vmcs12,
6699 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6700 exec_control |= vmcs12->secondary_vm_exec_control;
6701
6702 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6703 /*
6704 * Translate L1 physical address to host physical
6705 * address for vmcs02. Keep the page pinned, so this
6706 * physical address remains valid. We keep a reference
6707 * to it so we can release it later.
6708 */
6709 if (vmx->nested.apic_access_page) /* shouldn't happen */
6710 nested_release_page(vmx->nested.apic_access_page);
6711 vmx->nested.apic_access_page =
6712 nested_get_page(vcpu, vmcs12->apic_access_addr);
6713 /*
6714 * If translation failed, no matter: This feature asks
6715 * to exit when accessing the given address, and if it
6716 * can never be accessed, this feature won't do
6717 * anything anyway.
6718 */
6719 if (!vmx->nested.apic_access_page)
6720 exec_control &=
6721 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6722 else
6723 vmcs_write64(APIC_ACCESS_ADDR,
6724 page_to_phys(vmx->nested.apic_access_page));
6725 }
6726
6727 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6728 }
6729
6730
6731 /*
6732 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6733 * Some constant fields are set here by vmx_set_constant_host_state().
6734 * Other fields are different per CPU, and will be set later when
6735 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6736 */
6737 vmx_set_constant_host_state();
6738
6739 /*
6740 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6741 * entry, but only if the current (host) sp changed from the value
6742 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6743 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6744 * here we just force the write to happen on entry.
6745 */
6746 vmx->host_rsp = 0;
6747
6748 exec_control = vmx_exec_control(vmx); /* L0's desires */
6749 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6750 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6751 exec_control &= ~CPU_BASED_TPR_SHADOW;
6752 exec_control |= vmcs12->cpu_based_vm_exec_control;
6753 /*
6754 * Merging of IO and MSR bitmaps not currently supported.
6755 * Rather, exit every time.
6756 */
6757 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6758 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6759 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6760
6761 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6762
6763 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6764 * bitwise-or of what L1 wants to trap for L2, and what we want to
6765 * trap. Note that CR0.TS also needs updating - we do this later.
6766 */
6767 update_exception_bitmap(vcpu);
6768 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6769 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6770
6771 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6772 vmcs_write32(VM_EXIT_CONTROLS,
6773 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6774 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6775 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6776
6777 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6778 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6779 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6780 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6781
6782
6783 set_cr4_guest_host_mask(vmx);
6784
27fc51b2
NHE		 6785 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6786 vmcs_write64(TSC_OFFSET,
6787 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6788 else
6789 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6790
6791 if (enable_vpid) {
6792 /*
6793 * Trivially support vpid by letting L2s share their parent
6794 * L1's vpid. TODO: move to a more elaborate solution, giving
6795 * each L2 its own vpid and exposing the vpid feature to L1.
6796 */
6797 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6798 vmx_flush_tlb(vcpu);
6799 }
6800
6801 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6802 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6803 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6804 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6805 else
6806 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6807 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6808 vmx_set_efer(vcpu, vcpu->arch.efer);
6809
6810 /*
6811 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6812 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6813 * The CR0_READ_SHADOW is what L2 should have expected to read given
6814 * the specifications by L1; It's not enough to take
6815 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6816 * have more bits than L1 expected.
6817 */
6818 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6819 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6820
6821 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6822 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6823
6824 /* shadow page tables on either EPT or shadow page tables */
6825 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6826 kvm_mmu_reset_context(vcpu);
6827
6828 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6829 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6830}
6831
cd232ad0
NHE		 6832/*
6833 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6834 * for running an L2 nested guest.
6835 */
6836static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6837{
6838 struct vmcs12 *vmcs12;
6839 struct vcpu_vmx *vmx = to_vmx(vcpu);
6840 int cpu;
6841 struct loaded_vmcs *vmcs02;
6842
6843 if (!nested_vmx_check_permission(vcpu) ||
6844 !nested_vmx_check_vmcs12(vcpu))
6845 return 1;
6846
6847 skip_emulated_instruction(vcpu);
6848 vmcs12 = get_vmcs12(vcpu);
6849
7c177938
NHE		 6850 /*
6851 * The nested entry process starts with enforcing various prerequisites
6852 * on vmcs12 as required by the Intel SDM, and act appropriately when
6853 * they fail: As the SDM explains, some conditions should cause the
6854 * instruction to fail, while others will cause the instruction to seem
6855 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6856 * To speed up the normal (success) code path, we should avoid checking
6857 * for misconfigurations which will anyway be caught by the processor
6858 * when using the merged vmcs02.
6859 */
6860 if (vmcs12->launch_state == launch) {
6861 nested_vmx_failValid(vcpu,
6862 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6863 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6864 return 1;
6865 }
6866
6867 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6868 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6869 /*TODO: Also verify bits beyond physical address width are 0*/
6870 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6871 return 1;
6872 }
6873
6874 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6875 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6876 /*TODO: Also verify bits beyond physical address width are 0*/
6877 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6878 return 1;
6879 }
6880
6881 if (vmcs12->vm_entry_msr_load_count > 0 ||
6882 vmcs12->vm_exit_msr_load_count > 0 ||
6883 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6884 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6885 __func__);
7c177938
NHE		 6886 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6887 return 1;
6888 }
6889
6890 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6891 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6892 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6893 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6894 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6895 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6896 !vmx_control_verify(vmcs12->vm_exit_controls,
6897 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6898 !vmx_control_verify(vmcs12->vm_entry_controls,
6899 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6900 {
6901 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6902 return 1;
6903 }
6904
6905 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6906 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6907 nested_vmx_failValid(vcpu,
6908 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6909 return 1;
6910 }
6911
6912 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6913 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6914 nested_vmx_entry_failure(vcpu, vmcs12,
6915 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6916 return 1;
6917 }
6918 if (vmcs12->vmcs_link_pointer != -1ull) {
6919 nested_vmx_entry_failure(vcpu, vmcs12,
6920 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6921 return 1;
6922 }
6923
6924 /*
6925 * We're finally done with prerequisite checking, and can start with
6926 * the nested entry.
6927 */
6928
cd232ad0
NHE		 6929 vmcs02 = nested_get_current_vmcs02(vmx);
6930 if (!vmcs02)
6931 return -ENOMEM;
6932
6933 enter_guest_mode(vcpu);
6934
6935 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6936
6937 cpu = get_cpu();
6938 vmx->loaded_vmcs = vmcs02;
6939 vmx_vcpu_put(vcpu);
6940 vmx_vcpu_load(vcpu, cpu);
6941 vcpu->cpu = cpu;
6942 put_cpu();
6943
6944 vmcs12->launch_state = 1;
6945
6946 prepare_vmcs02(vcpu, vmcs12);
6947
6948 /*
6949 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6950 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6951 * returned as far as L1 is concerned. It will only return (and set
6952 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6953 */
6954 return 1;
6955}
6956
4704d0be
NHE		 6957/*
6958 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6959 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6960 * This function returns the new value we should put in vmcs12.guest_cr0.
6961 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6962 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6963 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6964 * didn't trap the bit, because if L1 did, so would L0).
6965 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6966 * been modified by L2, and L1 knows it. So just leave the old value of
6967 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6968 * isn't relevant, because if L0 traps this bit it can set it to anything.
6969 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6970 * changed these bits, and therefore they need to be updated, but L0
6971 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6972 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6973 */
6974static inline unsigned long
6975vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6976{
6977 return
6978 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6979 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6980 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6981 vcpu->arch.cr0_guest_owned_bits));
6982}
6983
6984static inline unsigned long
6985vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6986{
6987 return
6988 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6989 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6990 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6991 vcpu->arch.cr4_guest_owned_bits));
6992}
6993
6994/*
6995 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6996 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6997 * and this function updates it to reflect the changes to the guest state while
6998 * L2 was running (and perhaps made some exits which were handled directly by L0
6999 * without going back to L1), and to reflect the exit reason.
7000 * Note that we do not have to copy here all VMCS fields, just those that
7001 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7002 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7003 * which already writes to vmcs12 directly.
7004 */
7005void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7006{
7007 /* update guest state fields: */
7008 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7009 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7010
7011 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7012 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7013 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7014 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7015
7016 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7017 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7018 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7019 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7020 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7021 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7022 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7023 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7024 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7025 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7026 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7027 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7028 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7029 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7030 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7031 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7032 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7033 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7034 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7035 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7036 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7037 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7038 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7039 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7040 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7041 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7042 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7043 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7044 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7045 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7046 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7047 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7048 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7049 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7050 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7051 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7052
7053 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7054 vmcs12->guest_interruptibility_info =
7055 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7056 vmcs12->guest_pending_dbg_exceptions =
7057 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7058
7059 /* TODO: These cannot have changed unless we have MSR bitmaps and
7060 * the relevant bit asks not to trap the change */
7061 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7062 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7063 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7064 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7065 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7066 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7067
7068 /* update exit information fields: */
7069
7070 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7071 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7072
7073 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7074 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7075 vmcs12->idt_vectoring_info_field =
7076 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7077 vmcs12->idt_vectoring_error_code =
7078 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7079 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7080 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7081
7082 /* clear vm-entry fields which are to be cleared on exit */
7083 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7084 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7085}
7086
7087/*
7088 * A part of what we need to when the nested L2 guest exits and we want to
7089 * run its L1 parent, is to reset L1's guest state to the host state specified
7090 * in vmcs12.
7091 * This function is to be called not only on normal nested exit, but also on
7092 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7093 * Failures During or After Loading Guest State").
7094 * This function should be called when the active VMCS is L1's (vmcs01).
7095 */
7096void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7097{
7098 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7099 vcpu->arch.efer = vmcs12->host_ia32_efer;
7100 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7101 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7102 else
7103 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7104 vmx_set_efer(vcpu, vcpu->arch.efer);
7105
7106 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7107 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7108 /*
7109 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7110 * actually changed, because it depends on the current state of
7111 * fpu_active (which may have changed).
7112 * Note that vmx_set_cr0 refers to efer set above.
7113 */
7114 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7115 /*
7116 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7117 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7118 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7119 */
7120 update_exception_bitmap(vcpu);
7121 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7122 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7123
7124 /*
7125 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7126 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7127 */
7128 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7129 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7130
7131 /* shadow page tables on either EPT or shadow page tables */
7132 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7133 kvm_mmu_reset_context(vcpu);
7134
7135 if (enable_vpid) {
7136 /*
7137 * Trivially support vpid by letting L2s share their parent
7138 * L1's vpid. TODO: move to a more elaborate solution, giving
7139 * each L2 its own vpid and exposing the vpid feature to L1.
7140 */
7141 vmx_flush_tlb(vcpu);
7142 }
7143
7144
7145 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7146 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7147 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7148 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7149 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7150 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7151 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7152 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7153 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7154 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7155 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7156 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7157 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7158 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7159 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7160
7161 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7162 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7163 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7164 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7165 vmcs12->host_ia32_perf_global_ctrl);
7166}
7167
7168/*
7169 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7170 * and modify vmcs12 to make it see what it would expect to see there if
7171 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7172 */
7173static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7174{
7175 struct vcpu_vmx *vmx = to_vmx(vcpu);
7176 int cpu;
7177 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7178
7179 leave_guest_mode(vcpu);
7180 prepare_vmcs12(vcpu, vmcs12);
7181
7182 cpu = get_cpu();
7183 vmx->loaded_vmcs = &vmx->vmcs01;
7184 vmx_vcpu_put(vcpu);
7185 vmx_vcpu_load(vcpu, cpu);
7186 vcpu->cpu = cpu;
7187 put_cpu();
7188
7189 /* if no vmcs02 cache requested, remove the one we used */
7190 if (VMCS02_POOL_SIZE == 0)
7191 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7192
7193 load_vmcs12_host_state(vcpu, vmcs12);
7194
27fc51b2 7195 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7196 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7197
7198 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7199 vmx->host_rsp = 0;
7200
7201 /* Unpin physical memory we referred to in vmcs02 */
7202 if (vmx->nested.apic_access_page) {
7203 nested_release_page(vmx->nested.apic_access_page);
7204 vmx->nested.apic_access_page = 0;
7205 }
7206
7207 /*
7208 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7209 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7210 * success or failure flag accordingly.
7211 */
7212 if (unlikely(vmx->fail)) {
7213 vmx->fail = 0;
7214 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7215 } else
7216 nested_vmx_succeed(vcpu);
7217}
7218
7c177938
NHE		 7219/*
7220 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7221 * 23.7 "VM-entry failures during or after loading guest state" (this also
7222 * lists the acceptable exit-reason and exit-qualification parameters).
7223 * It should only be called before L2 actually succeeded to run, and when
7224 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7225 */
7226static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7227 struct vmcs12 *vmcs12,
7228 u32 reason, unsigned long qualification)
7229{
7230 load_vmcs12_host_state(vcpu, vmcs12);
7231 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7232 vmcs12->exit_qualification = qualification;
7233 nested_vmx_succeed(vcpu);
7234}
7235
8a76d7f2
JR		 7236static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7237 struct x86_instruction_info *info,
7238 enum x86_intercept_stage stage)
7239{
7240 return X86EMUL_CONTINUE;
7241}
7242
cbdd1bea 7243static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7244 .cpu_has_kvm_support = cpu_has_kvm_support,
7245 .disabled_by_bios = vmx_disabled_by_bios,
7246 .hardware_setup = hardware_setup,
7247 .hardware_unsetup = hardware_unsetup,
002c7f7c 7248 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7249 .hardware_enable = hardware_enable,
7250 .hardware_disable = hardware_disable,
04547156 7251 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7252
7253 .vcpu_create = vmx_create_vcpu,
7254 .vcpu_free = vmx_free_vcpu,
04d2cc77 7255 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7256
04d2cc77 7257 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7258 .vcpu_load = vmx_vcpu_load,
7259 .vcpu_put = vmx_vcpu_put,
7260
c8639010 7261 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7262 .get_msr = vmx_get_msr,
7263 .set_msr = vmx_set_msr,
7264 .get_segment_base = vmx_get_segment_base,
7265 .get_segment = vmx_get_segment,
7266 .set_segment = vmx_set_segment,
2e4d2653 7267 .get_cpl = vmx_get_cpl,
6aa8b732 7268 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7269 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7270 .decache_cr3 = vmx_decache_cr3,
25c4c276 7271 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7272 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7273 .set_cr3 = vmx_set_cr3,
7274 .set_cr4 = vmx_set_cr4,
6aa8b732 7275 .set_efer = vmx_set_efer,
6aa8b732
AK		 7276 .get_idt = vmx_get_idt,
7277 .set_idt = vmx_set_idt,
7278 .get_gdt = vmx_get_gdt,
7279 .set_gdt = vmx_set_gdt,
020df079 7280 .set_dr7 = vmx_set_dr7,
5fdbf976 7281 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7282 .get_rflags = vmx_get_rflags,
7283 .set_rflags = vmx_set_rflags,
ebcbab4c 7284 .fpu_activate = vmx_fpu_activate,
02daab21 7285 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7286
7287 .tlb_flush = vmx_flush_tlb,
6aa8b732 7288
6aa8b732 7289 .run = vmx_vcpu_run,
6062d012 7290 .handle_exit = vmx_handle_exit,
6aa8b732 7291 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7292 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7293 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7294 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7295 .set_irq = vmx_inject_irq,
95ba8273 7296 .set_nmi = vmx_inject_nmi,
298101da 7297 .queue_exception = vmx_queue_exception,
b463a6f7 7298 .cancel_injection = vmx_cancel_injection,
78646121 7299 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7300 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7301 .get_nmi_mask = vmx_get_nmi_mask,
7302 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7303 .enable_nmi_window = enable_nmi_window,
7304 .enable_irq_window = enable_irq_window,
7305 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7306
cbc94022 7307 .set_tss_addr = vmx_set_tss_addr,
67253af5 7308 .get_tdp_level = get_ept_level,
4b12f0de 7309 .get_mt_mask = vmx_get_mt_mask,
229456fc 7310
586f9607 7311 .get_exit_info = vmx_get_exit_info,
586f9607 7312
17cc3935 7313 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7314
7315 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7316
7317 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7318 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7319
7320 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7321
7322 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7323
4051b188 7324 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7325 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7326 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7327 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7328 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7329
7330 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7331
7332 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7333};
7334
7335static int __init vmx_init(void)
7336{
26bb0981
AK		 7337 int r, i;
7338
7339 rdmsrl_safe(MSR_EFER, &host_efer);
7340
7341 for (i = 0; i < NR_VMX_MSR; ++i)
7342 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7343
3e7c73e9 7344 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7345 if (!vmx_io_bitmap_a)
7346 return -ENOMEM;
7347
2106a548
GC		 7348 r = -ENOMEM;
7349
3e7c73e9 7350 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7351 if (!vmx_io_bitmap_b)
fdef3ad1 7352 goto out;
fdef3ad1 7353
5897297b 7354 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7355 if (!vmx_msr_bitmap_legacy)
25c5f225 7356 goto out1;
2106a548 7357
25c5f225 7358
5897297b 7359 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7360 if (!vmx_msr_bitmap_longmode)
5897297b 7361 goto out2;
2106a548 7362
5897297b 7363
fdef3ad1
HQ		 7364 /*
7365 * Allow direct access to the PC debug port (it is often used for I/O
7366 * delays, but the vmexits simply slow things down).
7367 */
3e7c73e9
AK		 7368 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7369 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7370
3e7c73e9 7371 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7372
5897297b
AK		 7373 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7374 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7375
2384d2b3
SY		 7376 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7377
0ee75bea
AK		 7378 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7379 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7380 if (r)
5897297b 7381 goto out3;
25c5f225 7382
5897297b
AK		 7383 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7384 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7385 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7386 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7387 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7388 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7389
089d034e 7390 if (enable_ept) {
3f6d8c8a
XH		 7391 kvm_mmu_set_mask_ptes(0ull,
7392 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7393 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7394 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7395 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7396 kvm_enable_tdp();
7397 } else
7398 kvm_disable_tdp();
1439442c 7399
fdef3ad1
HQ		 7400 return 0;
7401
5897297b
AK		 7402out3:
7403 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7404out2:
5897297b 7405 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7406out1:
3e7c73e9 7407 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7408out:
3e7c73e9 7409 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7410 return r;
6aa8b732
AK		 7411}
7412
7413static void __exit vmx_exit(void)
7414{
5897297b
AK		 7415 free_page((unsigned long)vmx_msr_bitmap_legacy);
7416 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7417 free_page((unsigned long)vmx_io_bitmap_b);
7418 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7419
cb498ea2 7420 kvm_exit();
6aa8b732
AK		 7421}
7422
7423module_init(vmx_init)
7424module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)