powerpc/pseries/eeh: Fix crash when error happens during device probe
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / process.c
CommitLineData
14cf11af 1/*
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2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
4 *
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
7 *
8 * PowerPC version
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
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17#include <linux/errno.h>
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
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22#include <linux/stddef.h>
23#include <linux/unistd.h>
24#include <linux/ptrace.h>
25#include <linux/slab.h>
26#include <linux/user.h>
27#include <linux/elf.h>
28#include <linux/init.h>
29#include <linux/prctl.h>
30#include <linux/init_task.h>
4b16f8e2 31#include <linux/export.h>
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32#include <linux/kallsyms.h>
33#include <linux/mqueue.h>
34#include <linux/hardirq.h>
06d67d54 35#include <linux/utsname.h>
6794c782 36#include <linux/ftrace.h>
79741dd3 37#include <linux/kernel_stat.h>
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38#include <linux/personality.h>
39#include <linux/random.h>
5aae8a53 40#include <linux/hw_breakpoint.h>
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41
42#include <asm/pgtable.h>
43#include <asm/uaccess.h>
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/processor.h>
47#include <asm/mmu.h>
48#include <asm/prom.h>
76032de8 49#include <asm/machdep.h>
c6622f63 50#include <asm/time.h>
a7f31841 51#include <asm/syscalls.h>
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52#ifdef CONFIG_PPC64
53#include <asm/firmware.h>
06d67d54 54#endif
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55#include <linux/kprobes.h>
56#include <linux/kdebug.h>
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57
58extern unsigned long _get_SP(void);
59
60#ifndef CONFIG_SMP
61struct task_struct *last_task_used_math = NULL;
62struct task_struct *last_task_used_altivec = NULL;
ce48b210 63struct task_struct *last_task_used_vsx = NULL;
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64struct task_struct *last_task_used_spe = NULL;
65#endif
66
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67/*
68 * Make sure the floating-point register state in the
69 * the thread_struct is up to date for task tsk.
70 */
71void flush_fp_to_thread(struct task_struct *tsk)
72{
73 if (tsk->thread.regs) {
74 /*
75 * We need to disable preemption here because if we didn't,
76 * another process could get scheduled after the regs->msr
77 * test but before we have finished saving the FP registers
78 * to the thread_struct. That process could take over the
79 * FPU, and then when we get scheduled again we would store
80 * bogus values for the remaining FP registers.
81 */
82 preempt_disable();
83 if (tsk->thread.regs->msr & MSR_FP) {
84#ifdef CONFIG_SMP
85 /*
86 * This should only ever be called for current or
87 * for a stopped child process. Since we save away
88 * the FP register state on context switch on SMP,
89 * there is something wrong if a stopped child appears
90 * to still have its FP state in the CPU registers.
91 */
92 BUG_ON(tsk != current);
93#endif
0ee6c15e 94 giveup_fpu(tsk);
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95 }
96 preempt_enable();
97 }
98}
de56a948 99EXPORT_SYMBOL_GPL(flush_fp_to_thread);
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100
101void enable_kernel_fp(void)
102{
103 WARN_ON(preemptible());
104
105#ifdef CONFIG_SMP
106 if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
107 giveup_fpu(current);
108 else
109 giveup_fpu(NULL); /* just enables FP for kernel */
110#else
111 giveup_fpu(last_task_used_math);
112#endif /* CONFIG_SMP */
113}
114EXPORT_SYMBOL(enable_kernel_fp);
115
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116#ifdef CONFIG_ALTIVEC
117void enable_kernel_altivec(void)
118{
119 WARN_ON(preemptible());
120
121#ifdef CONFIG_SMP
122 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
123 giveup_altivec(current);
124 else
125 giveup_altivec(NULL); /* just enable AltiVec for kernel - force */
126#else
127 giveup_altivec(last_task_used_altivec);
128#endif /* CONFIG_SMP */
129}
130EXPORT_SYMBOL(enable_kernel_altivec);
131
132/*
133 * Make sure the VMX/Altivec register state in the
134 * the thread_struct is up to date for task tsk.
135 */
136void flush_altivec_to_thread(struct task_struct *tsk)
137{
138 if (tsk->thread.regs) {
139 preempt_disable();
140 if (tsk->thread.regs->msr & MSR_VEC) {
141#ifdef CONFIG_SMP
142 BUG_ON(tsk != current);
143#endif
0ee6c15e 144 giveup_altivec(tsk);
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145 }
146 preempt_enable();
147 }
148}
de56a948 149EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
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150#endif /* CONFIG_ALTIVEC */
151
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152#ifdef CONFIG_VSX
153#if 0
154/* not currently used, but some crazy RAID module might want to later */
155void enable_kernel_vsx(void)
156{
157 WARN_ON(preemptible());
158
159#ifdef CONFIG_SMP
160 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
161 giveup_vsx(current);
162 else
163 giveup_vsx(NULL); /* just enable vsx for kernel - force */
164#else
165 giveup_vsx(last_task_used_vsx);
166#endif /* CONFIG_SMP */
167}
168EXPORT_SYMBOL(enable_kernel_vsx);
169#endif
170
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171void giveup_vsx(struct task_struct *tsk)
172{
173 giveup_fpu(tsk);
174 giveup_altivec(tsk);
175 __giveup_vsx(tsk);
176}
177
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178void flush_vsx_to_thread(struct task_struct *tsk)
179{
180 if (tsk->thread.regs) {
181 preempt_disable();
182 if (tsk->thread.regs->msr & MSR_VSX) {
183#ifdef CONFIG_SMP
184 BUG_ON(tsk != current);
185#endif
186 giveup_vsx(tsk);
187 }
188 preempt_enable();
189 }
190}
de56a948 191EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
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192#endif /* CONFIG_VSX */
193
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194#ifdef CONFIG_SPE
195
196void enable_kernel_spe(void)
197{
198 WARN_ON(preemptible());
199
200#ifdef CONFIG_SMP
201 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
202 giveup_spe(current);
203 else
204 giveup_spe(NULL); /* just enable SPE for kernel - force */
205#else
206 giveup_spe(last_task_used_spe);
207#endif /* __SMP __ */
208}
209EXPORT_SYMBOL(enable_kernel_spe);
210
211void flush_spe_to_thread(struct task_struct *tsk)
212{
213 if (tsk->thread.regs) {
214 preempt_disable();
215 if (tsk->thread.regs->msr & MSR_SPE) {
216#ifdef CONFIG_SMP
217 BUG_ON(tsk != current);
218#endif
685659ee 219 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
0ee6c15e 220 giveup_spe(tsk);
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221 }
222 preempt_enable();
223 }
224}
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225#endif /* CONFIG_SPE */
226
5388fb10 227#ifndef CONFIG_SMP
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228/*
229 * If we are doing lazy switching of CPU state (FP, altivec or SPE),
230 * and the current task has some state, discard it.
231 */
5388fb10 232void discard_lazy_cpu_state(void)
48abec07 233{
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234 preempt_disable();
235 if (last_task_used_math == current)
236 last_task_used_math = NULL;
237#ifdef CONFIG_ALTIVEC
238 if (last_task_used_altivec == current)
239 last_task_used_altivec = NULL;
240#endif /* CONFIG_ALTIVEC */
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241#ifdef CONFIG_VSX
242 if (last_task_used_vsx == current)
243 last_task_used_vsx = NULL;
244#endif /* CONFIG_VSX */
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245#ifdef CONFIG_SPE
246 if (last_task_used_spe == current)
247 last_task_used_spe = NULL;
248#endif
249 preempt_enable();
48abec07 250}
5388fb10 251#endif /* CONFIG_SMP */
48abec07 252
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253#ifdef CONFIG_PPC_ADV_DEBUG_REGS
254void do_send_trap(struct pt_regs *regs, unsigned long address,
255 unsigned long error_code, int signal_code, int breakpt)
256{
257 siginfo_t info;
258
259 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
260 11, SIGSEGV) == NOTIFY_STOP)
261 return;
262
263 /* Deliver the signal to userspace */
264 info.si_signo = SIGTRAP;
265 info.si_errno = breakpt; /* breakpoint or watchpoint id */
266 info.si_code = signal_code;
267 info.si_addr = (void __user *)address;
268 force_sig_info(SIGTRAP, &info, current);
269}
270#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
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271void do_dabr(struct pt_regs *regs, unsigned long address,
272 unsigned long error_code)
273{
274 siginfo_t info;
275
276 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
277 11, SIGSEGV) == NOTIFY_STOP)
278 return;
279
280 if (debugger_dabr_match(regs))
281 return;
282
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283 /* Clear the DABR */
284 set_dabr(0);
285
286 /* Deliver the signal to userspace */
287 info.si_signo = SIGTRAP;
288 info.si_errno = 0;
289 info.si_code = TRAP_HWBKPT;
290 info.si_addr = (void __user *)address;
291 force_sig_info(SIGTRAP, &info, current);
292}
3bffb652 293#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
d6a61bfc 294
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295static DEFINE_PER_CPU(unsigned long, current_dabr);
296
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297#ifdef CONFIG_PPC_ADV_DEBUG_REGS
298/*
299 * Set the debug registers back to their default "safe" values.
300 */
301static void set_debug_reg_defaults(struct thread_struct *thread)
302{
303 thread->iac1 = thread->iac2 = 0;
304#if CONFIG_PPC_ADV_DEBUG_IACS > 2
305 thread->iac3 = thread->iac4 = 0;
306#endif
307 thread->dac1 = thread->dac2 = 0;
308#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
309 thread->dvc1 = thread->dvc2 = 0;
310#endif
311 thread->dbcr0 = 0;
312#ifdef CONFIG_BOOKE
313 /*
314 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
315 */
316 thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
317 DBCR1_IAC3US | DBCR1_IAC4US;
318 /*
319 * Force Data Address Compare User/Supervisor bits to be User-only
320 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
321 */
322 thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
323#else
324 thread->dbcr1 = 0;
325#endif
326}
327
328static void prime_debug_regs(struct thread_struct *thread)
329{
330 mtspr(SPRN_IAC1, thread->iac1);
331 mtspr(SPRN_IAC2, thread->iac2);
332#if CONFIG_PPC_ADV_DEBUG_IACS > 2
333 mtspr(SPRN_IAC3, thread->iac3);
334 mtspr(SPRN_IAC4, thread->iac4);
335#endif
336 mtspr(SPRN_DAC1, thread->dac1);
337 mtspr(SPRN_DAC2, thread->dac2);
338#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
339 mtspr(SPRN_DVC1, thread->dvc1);
340 mtspr(SPRN_DVC2, thread->dvc2);
341#endif
342 mtspr(SPRN_DBCR0, thread->dbcr0);
343 mtspr(SPRN_DBCR1, thread->dbcr1);
344#ifdef CONFIG_BOOKE
345 mtspr(SPRN_DBCR2, thread->dbcr2);
346#endif
347}
348/*
349 * Unless neither the old or new thread are making use of the
350 * debug registers, set the debug registers from the values
351 * stored in the new thread.
352 */
353static void switch_booke_debug_regs(struct thread_struct *new_thread)
354{
355 if ((current->thread.dbcr0 & DBCR0_IDM)
356 || (new_thread->dbcr0 & DBCR0_IDM))
357 prime_debug_regs(new_thread);
358}
359#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
e0780b72 360#ifndef CONFIG_HAVE_HW_BREAKPOINT
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361static void set_debug_reg_defaults(struct thread_struct *thread)
362{
363 if (thread->dabr) {
364 thread->dabr = 0;
365 set_dabr(0);
366 }
367}
e0780b72 368#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
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369#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
370
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371int set_dabr(unsigned long dabr)
372{
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373 __get_cpu_var(current_dabr) = dabr;
374
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375 if (ppc_md.set_dabr)
376 return ppc_md.set_dabr(dabr);
14cf11af 377
791cc501 378 /* XXX should we have a CPU_FTR_HAS_DABR ? */
172ae2e7 379#ifdef CONFIG_PPC_ADV_DEBUG_REGS
d6a61bfc 380 mtspr(SPRN_DAC1, dabr);
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381#ifdef CONFIG_PPC_47x
382 isync();
383#endif
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384#elif defined(CONFIG_PPC_BOOK3S)
385 mtspr(SPRN_DABR, dabr);
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386#endif
387
c6c9eace 388
cab0af98 389 return 0;
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390}
391
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392#ifdef CONFIG_PPC64
393DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
06d67d54 394#endif
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395
396struct task_struct *__switch_to(struct task_struct *prev,
397 struct task_struct *new)
398{
399 struct thread_struct *new_thread, *old_thread;
400 unsigned long flags;
401 struct task_struct *last;
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402#ifdef CONFIG_PPC_BOOK3S_64
403 struct ppc64_tlb_batch *batch;
404#endif
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405
406#ifdef CONFIG_SMP
407 /* avoid complexity of lazy save/restore of fpu
408 * by just saving it every time we switch out if
409 * this task used the fpu during the last quantum.
410 *
411 * If it tries to use the fpu again, it'll trap and
412 * reload its fp regs. So we don't have to do a restore
413 * every switch, just a save.
414 * -- Cort
415 */
416 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
417 giveup_fpu(prev);
418#ifdef CONFIG_ALTIVEC
419 /*
420 * If the previous thread used altivec in the last quantum
421 * (thus changing altivec regs) then save them.
422 * We used to check the VRSAVE register but not all apps
423 * set it, so we don't rely on it now (and in fact we need
424 * to save & restore VSCR even if VRSAVE == 0). -- paulus
425 *
426 * On SMP we always save/restore altivec regs just to avoid the
427 * complexity of changing processors.
428 * -- Cort
429 */
430 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
431 giveup_altivec(prev);
14cf11af 432#endif /* CONFIG_ALTIVEC */
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433#ifdef CONFIG_VSX
434 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
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435 /* VMX and FPU registers are already save here */
436 __giveup_vsx(prev);
ce48b210 437#endif /* CONFIG_VSX */
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438#ifdef CONFIG_SPE
439 /*
440 * If the previous thread used spe in the last quantum
441 * (thus changing spe regs) then save them.
442 *
443 * On SMP we always save/restore spe regs just to avoid the
444 * complexity of changing processors.
445 */
446 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
447 giveup_spe(prev);
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448#endif /* CONFIG_SPE */
449
450#else /* CONFIG_SMP */
451#ifdef CONFIG_ALTIVEC
452 /* Avoid the trap. On smp this this never happens since
453 * we don't set last_task_used_altivec -- Cort
454 */
455 if (new->thread.regs && last_task_used_altivec == new)
456 new->thread.regs->msr |= MSR_VEC;
457#endif /* CONFIG_ALTIVEC */
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458#ifdef CONFIG_VSX
459 if (new->thread.regs && last_task_used_vsx == new)
460 new->thread.regs->msr |= MSR_VSX;
461#endif /* CONFIG_VSX */
c0c0d996 462#ifdef CONFIG_SPE
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463 /* Avoid the trap. On smp this this never happens since
464 * we don't set last_task_used_spe
465 */
466 if (new->thread.regs && last_task_used_spe == new)
467 new->thread.regs->msr |= MSR_SPE;
468#endif /* CONFIG_SPE */
c0c0d996 469
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470#endif /* CONFIG_SMP */
471
172ae2e7 472#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3bffb652 473 switch_booke_debug_regs(&new->thread);
c6c9eace 474#else
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475/*
476 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
477 * schedule DABR
478 */
479#ifndef CONFIG_HAVE_HW_BREAKPOINT
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480 if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
481 set_dabr(new->thread.dabr);
5aae8a53 482#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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483#endif
484
c6c9eace 485
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486 new_thread = &new->thread;
487 old_thread = &current->thread;
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488
489#ifdef CONFIG_PPC64
490 /*
491 * Collect processor utilization data per process
492 */
493 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
494 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
495 long unsigned start_tb, current_tb;
496 start_tb = old_thread->start_tb;
497 cu->current_tb = current_tb = mfspr(SPRN_PURR);
498 old_thread->accum_tb += (current_tb - start_tb);
499 new_thread->start_tb = current_tb;
500 }
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501#endif /* CONFIG_PPC64 */
502
503#ifdef CONFIG_PPC_BOOK3S_64
504 batch = &__get_cpu_var(ppc64_tlb_batch);
505 if (batch->active) {
506 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
507 if (batch->index)
508 __flush_tlb_pending(batch);
509 batch->active = 0;
510 }
511#endif /* CONFIG_PPC_BOOK3S_64 */
06d67d54 512
14cf11af 513 local_irq_save(flags);
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514
515 account_system_vtime(current);
81a3843f 516 account_process_vtime(current);
c6622f63 517
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518 /*
519 * We can't take a PMU exception inside _switch() since there is a
520 * window where the kernel stack SLB and the kernel stack are out
521 * of sync. Hard disable here.
522 */
523 hard_irq_disable();
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524 last = _switch(old_thread, new_thread);
525
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526#ifdef CONFIG_PPC_BOOK3S_64
527 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
528 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
529 batch = &__get_cpu_var(ppc64_tlb_batch);
530 batch->active = 1;
531 }
532#endif /* CONFIG_PPC_BOOK3S_64 */
533
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534 local_irq_restore(flags);
535
536 return last;
537}
538
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539static int instructions_to_print = 16;
540
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541static void show_instructions(struct pt_regs *regs)
542{
543 int i;
544 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
545 sizeof(int));
546
547 printk("Instruction dump:");
548
549 for (i = 0; i < instructions_to_print; i++) {
550 int instr;
551
552 if (!(i % 8))
553 printk("\n");
554
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555#if !defined(CONFIG_BOOKE)
556 /* If executing with the IMMU off, adjust pc rather
557 * than print XXXXXXXX.
558 */
559 if (!(regs->msr & MSR_IR))
560 pc = (unsigned long)phys_to_virt(pc);
561#endif
562
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563 /* We use __get_user here *only* to avoid an OOPS on a
564 * bad address because the pc *should* only be a
565 * kernel address.
566 */
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567 if (!__kernel_text_address(pc) ||
568 __get_user(instr, (unsigned int __user *)pc)) {
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569 printk("XXXXXXXX ");
570 } else {
571 if (regs->nip == pc)
572 printk("<%08x> ", instr);
573 else
574 printk("%08x ", instr);
575 }
576
577 pc += sizeof(int);
578 }
579
580 printk("\n");
581}
582
583static struct regbit {
584 unsigned long bit;
585 const char *name;
586} msr_bits[] = {
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587#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
588 {MSR_SF, "SF"},
589 {MSR_HV, "HV"},
590#endif
591 {MSR_VEC, "VEC"},
592 {MSR_VSX, "VSX"},
593#ifdef CONFIG_BOOKE
594 {MSR_CE, "CE"},
595#endif
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596 {MSR_EE, "EE"},
597 {MSR_PR, "PR"},
598 {MSR_FP, "FP"},
599 {MSR_ME, "ME"},
3bfd0c9c 600#ifdef CONFIG_BOOKE
1b98326b 601 {MSR_DE, "DE"},
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602#else
603 {MSR_SE, "SE"},
604 {MSR_BE, "BE"},
605#endif
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606 {MSR_IR, "IR"},
607 {MSR_DR, "DR"},
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608 {MSR_PMM, "PMM"},
609#ifndef CONFIG_BOOKE
610 {MSR_RI, "RI"},
611 {MSR_LE, "LE"},
612#endif
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613 {0, NULL}
614};
615
616static void printbits(unsigned long val, struct regbit *bits)
617{
618 const char *sep = "";
619
620 printk("<");
621 for (; bits->bit; ++bits)
622 if (val & bits->bit) {
623 printk("%s%s", sep, bits->name);
624 sep = ",";
625 }
626 printk(">");
627}
628
629#ifdef CONFIG_PPC64
f6f7dde3 630#define REG "%016lx"
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631#define REGS_PER_LINE 4
632#define LAST_VOLATILE 13
633#else
f6f7dde3 634#define REG "%08lx"
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635#define REGS_PER_LINE 8
636#define LAST_VOLATILE 12
637#endif
638
14cf11af
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639void show_regs(struct pt_regs * regs)
640{
641 int i, trap;
642
06d67d54
PM
643 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
644 regs->nip, regs->link, regs->ctr);
645 printk("REGS: %p TRAP: %04lx %s (%s)\n",
96b644bd 646 regs, regs->trap, print_tainted(), init_utsname()->release);
06d67d54
PM
647 printk("MSR: "REG" ", regs->msr);
648 printbits(regs->msr, msr_bits);
f6f7dde3 649 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
14cf11af 650 trap = TRAP(regs);
5115a026
MN
651 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
652 printk("CFAR: "REG"\n", regs->orig_gpr3);
14cf11af 653 if (trap == 0x300 || trap == 0x600)
ba28c9aa 654#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
14170789
KG
655 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
656#else
7071854b 657 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
14170789 658#endif
06d67d54 659 printk("TASK = %p[%d] '%s' THREAD: %p",
19c5870c 660 current, task_pid_nr(current), current->comm, task_thread_info(current));
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661
662#ifdef CONFIG_SMP
79ccd1be 663 printk(" CPU: %d", raw_smp_processor_id());
14cf11af
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664#endif /* CONFIG_SMP */
665
666 for (i = 0; i < 32; i++) {
06d67d54 667 if ((i % REGS_PER_LINE) == 0)
a2367194 668 printk("\nGPR%02d: ", i);
06d67d54
PM
669 printk(REG " ", regs->gpr[i]);
670 if (i == LAST_VOLATILE && !FULL_REGS(regs))
14cf11af
PM
671 break;
672 }
673 printk("\n");
674#ifdef CONFIG_KALLSYMS
675 /*
676 * Lookup NIP late so we have the best change of getting the
677 * above info out without failing
678 */
058c78f4
BH
679 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
680 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
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681#endif
682 show_stack(current, (unsigned long *) regs->gpr[1]);
06d67d54
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683 if (!user_mode(regs))
684 show_instructions(regs);
14cf11af
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685}
686
687void exit_thread(void)
688{
48abec07 689 discard_lazy_cpu_state();
14cf11af
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690}
691
692void flush_thread(void)
693{
48abec07 694 discard_lazy_cpu_state();
14cf11af 695
e0780b72 696#ifdef CONFIG_HAVE_HW_BREAKPOINT
5aae8a53 697 flush_ptrace_hw_breakpoint(current);
e0780b72 698#else /* CONFIG_HAVE_HW_BREAKPOINT */
3bffb652 699 set_debug_reg_defaults(&current->thread);
e0780b72 700#endif /* CONFIG_HAVE_HW_BREAKPOINT */
14cf11af
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701}
702
703void
704release_thread(struct task_struct *t)
705{
706}
707
708/*
709 * This gets called before we allocate a new thread and copy
710 * the current task into it.
711 */
712void prepare_to_copy(struct task_struct *tsk)
713{
714 flush_fp_to_thread(current);
715 flush_altivec_to_thread(current);
ce48b210 716 flush_vsx_to_thread(current);
14cf11af 717 flush_spe_to_thread(current);
5aae8a53
P
718#ifdef CONFIG_HAVE_HW_BREAKPOINT
719 flush_ptrace_hw_breakpoint(tsk);
720#endif /* CONFIG_HAVE_HW_BREAKPOINT */
14cf11af
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721}
722
723/*
724 * Copy a thread..
725 */
efcac658
AK
726extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
727
6f2c55b8 728int copy_thread(unsigned long clone_flags, unsigned long usp,
06d67d54
PM
729 unsigned long unused, struct task_struct *p,
730 struct pt_regs *regs)
14cf11af
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731{
732 struct pt_regs *childregs, *kregs;
733 extern void ret_from_fork(void);
0cec6fd1 734 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
14cf11af
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735
736 CHECK_FULL_REGS(regs);
737 /* Copy registers */
738 sp -= sizeof(struct pt_regs);
739 childregs = (struct pt_regs *) sp;
740 *childregs = *regs;
741 if ((childregs->msr & MSR_PR) == 0) {
742 /* for kernel thread, set `current' and stackptr in new task */
743 childregs->gpr[1] = sp + sizeof(struct pt_regs);
06d67d54 744#ifdef CONFIG_PPC32
14cf11af 745 childregs->gpr[2] = (unsigned long) p;
06d67d54 746#else
b5e2fc1c 747 clear_tsk_thread_flag(p, TIF_32BIT);
06d67d54 748#endif
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749 p->thread.regs = NULL; /* no user register state */
750 } else {
751 childregs->gpr[1] = usp;
752 p->thread.regs = childregs;
06d67d54
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753 if (clone_flags & CLONE_SETTLS) {
754#ifdef CONFIG_PPC64
9904b005 755 if (!is_32bit_task())
06d67d54
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756 childregs->gpr[13] = childregs->gpr[6];
757 else
758#endif
759 childregs->gpr[2] = childregs->gpr[6];
760 }
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761 }
762 childregs->gpr[3] = 0; /* Result from fork() */
763 sp -= STACK_FRAME_OVERHEAD;
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764
765 /*
766 * The way this works is that at some point in the future
767 * some task will call _switch to switch to the new task.
768 * That will pop off the stack frame created below and start
769 * the new task running at ret_from_fork. The new task will
770 * do some house keeping and then return from the fork or clone
771 * system call, using the stack frame created above.
772 */
773 sp -= sizeof(struct pt_regs);
774 kregs = (struct pt_regs *) sp;
775 sp -= STACK_FRAME_OVERHEAD;
776 p->thread.ksp = sp;
85218827
KG
777 p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
778 _ALIGN_UP(sizeof(struct thread_info), 16);
14cf11af 779
94491685 780#ifdef CONFIG_PPC_STD_MMU_64
44ae3ab3 781 if (mmu_has_feature(MMU_FTR_SLB)) {
1189be65 782 unsigned long sp_vsid;
3c726f8d 783 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
06d67d54 784
44ae3ab3 785 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1189be65
PM
786 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
787 << SLB_VSID_SHIFT_1T;
788 else
789 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
790 << SLB_VSID_SHIFT;
3c726f8d 791 sp_vsid |= SLB_VSID_KERNEL | llp;
06d67d54
PM
792 p->thread.ksp_vsid = sp_vsid;
793 }
747bea91 794#endif /* CONFIG_PPC_STD_MMU_64 */
efcac658
AK
795#ifdef CONFIG_PPC64
796 if (cpu_has_feature(CPU_FTR_DSCR)) {
797 if (current->thread.dscr_inherit) {
798 p->thread.dscr_inherit = 1;
799 p->thread.dscr = current->thread.dscr;
800 } else if (0 != dscr_default) {
801 p->thread.dscr_inherit = 1;
802 p->thread.dscr = dscr_default;
803 } else {
804 p->thread.dscr_inherit = 0;
805 p->thread.dscr = 0;
806 }
807 }
808#endif
06d67d54
PM
809
810 /*
811 * The PPC64 ABI makes use of a TOC to contain function
812 * pointers. The function (ret_from_except) is actually a pointer
813 * to the TOC entry. The first entry is a pointer to the actual
814 * function.
815 */
747bea91 816#ifdef CONFIG_PPC64
06d67d54
PM
817 kregs->nip = *((unsigned long *)ret_from_fork);
818#else
819 kregs->nip = (unsigned long)ret_from_fork;
06d67d54 820#endif
14cf11af
PM
821
822 return 0;
823}
824
825/*
826 * Set up a thread for executing a new program
827 */
06d67d54 828void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
14cf11af 829{
90eac727
ME
830#ifdef CONFIG_PPC64
831 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
832#endif
833
06d67d54
PM
834 /*
835 * If we exec out of a kernel thread then thread.regs will not be
836 * set. Do it now.
837 */
838 if (!current->thread.regs) {
0cec6fd1
AV
839 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
840 current->thread.regs = regs - 1;
06d67d54
PM
841 }
842
14cf11af
PM
843 memset(regs->gpr, 0, sizeof(regs->gpr));
844 regs->ctr = 0;
845 regs->link = 0;
846 regs->xer = 0;
847 regs->ccr = 0;
14cf11af 848 regs->gpr[1] = sp;
06d67d54 849
474f8196
RM
850 /*
851 * We have just cleared all the nonvolatile GPRs, so make
852 * FULL_REGS(regs) return true. This is necessary to allow
853 * ptrace to examine the thread immediately after exec.
854 */
855 regs->trap &= ~1UL;
856
06d67d54
PM
857#ifdef CONFIG_PPC32
858 regs->mq = 0;
859 regs->nip = start;
14cf11af 860 regs->msr = MSR_USER;
06d67d54 861#else
9904b005 862 if (!is_32bit_task()) {
90eac727 863 unsigned long entry, toc;
06d67d54
PM
864
865 /* start is a relocated pointer to the function descriptor for
866 * the elf _start routine. The first entry in the function
867 * descriptor is the entry address of _start and the second
868 * entry is the TOC value we need to use.
869 */
870 __get_user(entry, (unsigned long __user *)start);
871 __get_user(toc, (unsigned long __user *)start+1);
872
873 /* Check whether the e_entry function descriptor entries
874 * need to be relocated before we can use them.
875 */
876 if (load_addr != 0) {
877 entry += load_addr;
878 toc += load_addr;
879 }
880 regs->nip = entry;
881 regs->gpr[2] = toc;
882 regs->msr = MSR_USER64;
d4bf9a78
SR
883 } else {
884 regs->nip = start;
885 regs->gpr[2] = 0;
886 regs->msr = MSR_USER32;
06d67d54
PM
887 }
888#endif
889
48abec07 890 discard_lazy_cpu_state();
ce48b210
MN
891#ifdef CONFIG_VSX
892 current->thread.used_vsr = 0;
893#endif
14cf11af 894 memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
25c8a78b 895 current->thread.fpscr.val = 0;
14cf11af
PM
896#ifdef CONFIG_ALTIVEC
897 memset(current->thread.vr, 0, sizeof(current->thread.vr));
898 memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
06d67d54 899 current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */
14cf11af
PM
900 current->thread.vrsave = 0;
901 current->thread.used_vr = 0;
902#endif /* CONFIG_ALTIVEC */
903#ifdef CONFIG_SPE
904 memset(current->thread.evr, 0, sizeof(current->thread.evr));
905 current->thread.acc = 0;
906 current->thread.spefscr = 0;
907 current->thread.used_spe = 0;
908#endif /* CONFIG_SPE */
909}
910
911#define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
912 | PR_FP_EXC_RES | PR_FP_EXC_INV)
913
914int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
915{
916 struct pt_regs *regs = tsk->thread.regs;
917
918 /* This is a bit hairy. If we are an SPE enabled processor
919 * (have embedded fp) we store the IEEE exception enable flags in
920 * fpexc_mode. fpexc_mode is also used for setting FP exception
921 * mode (asyn, precise, disabled) for 'Classic' FP. */
922 if (val & PR_FP_EXC_SW_ENABLE) {
923#ifdef CONFIG_SPE
5e14d21e
KG
924 if (cpu_has_feature(CPU_FTR_SPE)) {
925 tsk->thread.fpexc_mode = val &
926 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
927 return 0;
928 } else {
929 return -EINVAL;
930 }
14cf11af
PM
931#else
932 return -EINVAL;
933#endif
14cf11af 934 }
06d67d54
PM
935
936 /* on a CONFIG_SPE this does not hurt us. The bits that
937 * __pack_fe01 use do not overlap with bits used for
938 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
939 * on CONFIG_SPE implementations are reserved so writing to
940 * them does not change anything */
941 if (val > PR_FP_EXC_PRECISE)
942 return -EINVAL;
943 tsk->thread.fpexc_mode = __pack_fe01(val);
944 if (regs != NULL && (regs->msr & MSR_FP) != 0)
945 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
946 | tsk->thread.fpexc_mode;
14cf11af
PM
947 return 0;
948}
949
950int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
951{
952 unsigned int val;
953
954 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
955#ifdef CONFIG_SPE
5e14d21e
KG
956 if (cpu_has_feature(CPU_FTR_SPE))
957 val = tsk->thread.fpexc_mode;
958 else
959 return -EINVAL;
14cf11af
PM
960#else
961 return -EINVAL;
962#endif
963 else
964 val = __unpack_fe01(tsk->thread.fpexc_mode);
965 return put_user(val, (unsigned int __user *) adr);
966}
967
fab5db97
PM
968int set_endian(struct task_struct *tsk, unsigned int val)
969{
970 struct pt_regs *regs = tsk->thread.regs;
971
972 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
973 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
974 return -EINVAL;
975
976 if (regs == NULL)
977 return -EINVAL;
978
979 if (val == PR_ENDIAN_BIG)
980 regs->msr &= ~MSR_LE;
981 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
982 regs->msr |= MSR_LE;
983 else
984 return -EINVAL;
985
986 return 0;
987}
988
989int get_endian(struct task_struct *tsk, unsigned long adr)
990{
991 struct pt_regs *regs = tsk->thread.regs;
992 unsigned int val;
993
994 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
995 !cpu_has_feature(CPU_FTR_REAL_LE))
996 return -EINVAL;
997
998 if (regs == NULL)
999 return -EINVAL;
1000
1001 if (regs->msr & MSR_LE) {
1002 if (cpu_has_feature(CPU_FTR_REAL_LE))
1003 val = PR_ENDIAN_LITTLE;
1004 else
1005 val = PR_ENDIAN_PPC_LITTLE;
1006 } else
1007 val = PR_ENDIAN_BIG;
1008
1009 return put_user(val, (unsigned int __user *)adr);
1010}
1011
e9370ae1
PM
1012int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1013{
1014 tsk->thread.align_ctl = val;
1015 return 0;
1016}
1017
1018int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1019{
1020 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1021}
1022
06d67d54
PM
1023#define TRUNC_PTR(x) ((typeof(x))(((unsigned long)(x)) & 0xffffffff))
1024
14cf11af
PM
1025int sys_clone(unsigned long clone_flags, unsigned long usp,
1026 int __user *parent_tidp, void __user *child_threadptr,
1027 int __user *child_tidp, int p6,
1028 struct pt_regs *regs)
1029{
1030 CHECK_FULL_REGS(regs);
1031 if (usp == 0)
1032 usp = regs->gpr[1]; /* stack pointer for child */
06d67d54 1033#ifdef CONFIG_PPC64
9904b005 1034 if (is_32bit_task()) {
06d67d54
PM
1035 parent_tidp = TRUNC_PTR(parent_tidp);
1036 child_tidp = TRUNC_PTR(child_tidp);
1037 }
1038#endif
14cf11af
PM
1039 return do_fork(clone_flags, usp, regs, 0, parent_tidp, child_tidp);
1040}
1041
1042int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
1043 unsigned long p4, unsigned long p5, unsigned long p6,
1044 struct pt_regs *regs)
1045{
1046 CHECK_FULL_REGS(regs);
1047 return do_fork(SIGCHLD, regs->gpr[1], regs, 0, NULL, NULL);
1048}
1049
1050int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
1051 unsigned long p4, unsigned long p5, unsigned long p6,
1052 struct pt_regs *regs)
1053{
1054 CHECK_FULL_REGS(regs);
1055 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->gpr[1],
1056 regs, 0, NULL, NULL);
1057}
1058
1059int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
1060 unsigned long a3, unsigned long a4, unsigned long a5,
1061 struct pt_regs *regs)
1062{
1063 int error;
06d67d54 1064 char *filename;
14cf11af 1065
c7887325 1066 filename = getname((const char __user *) a0);
14cf11af
PM
1067 error = PTR_ERR(filename);
1068 if (IS_ERR(filename))
1069 goto out;
1070 flush_fp_to_thread(current);
1071 flush_altivec_to_thread(current);
1072 flush_spe_to_thread(current);
d7627467
DH
1073 error = do_execve(filename,
1074 (const char __user *const __user *) a1,
1075 (const char __user *const __user *) a2, regs);
14cf11af
PM
1076 putname(filename);
1077out:
1078 return error;
1079}
1080
bb72c481
PM
1081static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1082 unsigned long nbytes)
1083{
1084 unsigned long stack_page;
1085 unsigned long cpu = task_cpu(p);
1086
1087 /*
1088 * Avoid crashing if the stack has overflowed and corrupted
1089 * task_cpu(p), which is in the thread_info struct.
1090 */
1091 if (cpu < NR_CPUS && cpu_possible(cpu)) {
1092 stack_page = (unsigned long) hardirq_ctx[cpu];
1093 if (sp >= stack_page + sizeof(struct thread_struct)
1094 && sp <= stack_page + THREAD_SIZE - nbytes)
1095 return 1;
1096
1097 stack_page = (unsigned long) softirq_ctx[cpu];
1098 if (sp >= stack_page + sizeof(struct thread_struct)
1099 && sp <= stack_page + THREAD_SIZE - nbytes)
1100 return 1;
1101 }
1102 return 0;
1103}
1104
2f25194d 1105int validate_sp(unsigned long sp, struct task_struct *p,
14cf11af
PM
1106 unsigned long nbytes)
1107{
0cec6fd1 1108 unsigned long stack_page = (unsigned long)task_stack_page(p);
14cf11af
PM
1109
1110 if (sp >= stack_page + sizeof(struct thread_struct)
1111 && sp <= stack_page + THREAD_SIZE - nbytes)
1112 return 1;
1113
bb72c481 1114 return valid_irq_stack(sp, p, nbytes);
14cf11af
PM
1115}
1116
2f25194d
AB
1117EXPORT_SYMBOL(validate_sp);
1118
14cf11af
PM
1119unsigned long get_wchan(struct task_struct *p)
1120{
1121 unsigned long ip, sp;
1122 int count = 0;
1123
1124 if (!p || p == current || p->state == TASK_RUNNING)
1125 return 0;
1126
1127 sp = p->thread.ksp;
ec2b36b9 1128 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
14cf11af
PM
1129 return 0;
1130
1131 do {
1132 sp = *(unsigned long *)sp;
ec2b36b9 1133 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
14cf11af
PM
1134 return 0;
1135 if (count > 0) {
ec2b36b9 1136 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
14cf11af
PM
1137 if (!in_sched_functions(ip))
1138 return ip;
1139 }
1140 } while (count++ < 16);
1141 return 0;
1142}
06d67d54 1143
c4d04be1 1144static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
06d67d54
PM
1145
1146void show_stack(struct task_struct *tsk, unsigned long *stack)
1147{
1148 unsigned long sp, ip, lr, newsp;
1149 int count = 0;
1150 int firstframe = 1;
6794c782
SR
1151#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1152 int curr_frame = current->curr_ret_stack;
1153 extern void return_to_handler(void);
9135c3cc
SR
1154 unsigned long rth = (unsigned long)return_to_handler;
1155 unsigned long mrth = -1;
6794c782 1156#ifdef CONFIG_PPC64
9135c3cc
SR
1157 extern void mod_return_to_handler(void);
1158 rth = *(unsigned long *)rth;
1159 mrth = (unsigned long)mod_return_to_handler;
1160 mrth = *(unsigned long *)mrth;
6794c782
SR
1161#endif
1162#endif
06d67d54
PM
1163
1164 sp = (unsigned long) stack;
1165 if (tsk == NULL)
1166 tsk = current;
1167 if (sp == 0) {
1168 if (tsk == current)
1169 asm("mr %0,1" : "=r" (sp));
1170 else
1171 sp = tsk->thread.ksp;
1172 }
1173
1174 lr = 0;
1175 printk("Call Trace:\n");
1176 do {
ec2b36b9 1177 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
06d67d54
PM
1178 return;
1179
1180 stack = (unsigned long *) sp;
1181 newsp = stack[0];
ec2b36b9 1182 ip = stack[STACK_FRAME_LR_SAVE];
06d67d54 1183 if (!firstframe || ip != lr) {
058c78f4 1184 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
6794c782 1185#ifdef CONFIG_FUNCTION_GRAPH_TRACER
9135c3cc 1186 if ((ip == rth || ip == mrth) && curr_frame >= 0) {
6794c782
SR
1187 printk(" (%pS)",
1188 (void *)current->ret_stack[curr_frame].ret);
1189 curr_frame--;
1190 }
1191#endif
06d67d54
PM
1192 if (firstframe)
1193 printk(" (unreliable)");
1194 printk("\n");
1195 }
1196 firstframe = 0;
1197
1198 /*
1199 * See if this is an exception frame.
1200 * We look for the "regshere" marker in the current frame.
1201 */
ec2b36b9
BH
1202 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1203 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
06d67d54
PM
1204 struct pt_regs *regs = (struct pt_regs *)
1205 (sp + STACK_FRAME_OVERHEAD);
06d67d54 1206 lr = regs->link;
058c78f4
BH
1207 printk("--- Exception: %lx at %pS\n LR = %pS\n",
1208 regs->trap, (void *)regs->nip, (void *)lr);
06d67d54
PM
1209 firstframe = 1;
1210 }
1211
1212 sp = newsp;
1213 } while (count++ < kstack_depth_to_print);
1214}
1215
1216void dump_stack(void)
1217{
1218 show_stack(current, NULL);
1219}
1220EXPORT_SYMBOL(dump_stack);
cb2c9b27
AB
1221
1222#ifdef CONFIG_PPC64
1223void ppc64_runlatch_on(void)
1224{
1225 unsigned long ctrl;
1226
1227 if (cpu_has_feature(CPU_FTR_CTRL) && !test_thread_flag(TIF_RUNLATCH)) {
1228 HMT_medium();
1229
1230 ctrl = mfspr(SPRN_CTRLF);
1231 ctrl |= CTRL_RUNLATCH;
1232 mtspr(SPRN_CTRLT, ctrl);
1233
1234 set_thread_flag(TIF_RUNLATCH);
1235 }
1236}
1237
4138d653 1238void __ppc64_runlatch_off(void)
cb2c9b27
AB
1239{
1240 unsigned long ctrl;
1241
4138d653 1242 HMT_medium();
cb2c9b27 1243
4138d653 1244 clear_thread_flag(TIF_RUNLATCH);
cb2c9b27 1245
4138d653
AB
1246 ctrl = mfspr(SPRN_CTRLF);
1247 ctrl &= ~CTRL_RUNLATCH;
1248 mtspr(SPRN_CTRLT, ctrl);
cb2c9b27
AB
1249}
1250#endif
f6a61680
BH
1251
1252#if THREAD_SHIFT < PAGE_SHIFT
1253
1254static struct kmem_cache *thread_info_cache;
1255
b6a84016 1256struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
f6a61680
BH
1257{
1258 struct thread_info *ti;
1259
b6a84016 1260 ti = kmem_cache_alloc_node(thread_info_cache, GFP_KERNEL, node);
f6a61680
BH
1261 if (unlikely(ti == NULL))
1262 return NULL;
1263#ifdef CONFIG_DEBUG_STACK_USAGE
1264 memset(ti, 0, THREAD_SIZE);
1265#endif
1266 return ti;
1267}
1268
1269void free_thread_info(struct thread_info *ti)
1270{
1271 kmem_cache_free(thread_info_cache, ti);
1272}
1273
1274void thread_info_cache_init(void)
1275{
1276 thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
1277 THREAD_SIZE, 0, NULL);
1278 BUG_ON(thread_info_cache == NULL);
1279}
1280
1281#endif /* THREAD_SHIFT < PAGE_SHIFT */
d839088c
AB
1282
1283unsigned long arch_align_stack(unsigned long sp)
1284{
1285 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1286 sp -= get_random_int() & ~PAGE_MASK;
1287 return sp & ~0xf;
1288}
912f9ee2
AB
1289
1290static inline unsigned long brk_rnd(void)
1291{
1292 unsigned long rnd = 0;
1293
1294 /* 8MB for 32bit, 1GB for 64bit */
1295 if (is_32bit_task())
1296 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1297 else
1298 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1299
1300 return rnd << PAGE_SHIFT;
1301}
1302
1303unsigned long arch_randomize_brk(struct mm_struct *mm)
1304{
8bbde7a7
AB
1305 unsigned long base = mm->brk;
1306 unsigned long ret;
1307
ce7a35c7 1308#ifdef CONFIG_PPC_STD_MMU_64
8bbde7a7
AB
1309 /*
1310 * If we are using 1TB segments and we are allowed to randomise
1311 * the heap, we can put it above 1TB so it is backed by a 1TB
1312 * segment. Otherwise the heap will be in the bottom 1TB
1313 * which always uses 256MB segments and this may result in a
1314 * performance penalty.
1315 */
1316 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1317 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1318#endif
1319
1320 ret = PAGE_ALIGN(base + brk_rnd());
912f9ee2
AB
1321
1322 if (ret < mm->brk)
1323 return mm->brk;
1324
1325 return ret;
1326}
501cb16d
AB
1327
1328unsigned long randomize_et_dyn(unsigned long base)
1329{
1330 unsigned long ret = PAGE_ALIGN(base + brk_rnd());
1331
1332 if (ret < base)
1333 return base;
1334
1335 return ret;
1336}