powerpc: convert hvconsole.c to export.h ; fix implicit use of errno.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / process.c
CommitLineData
14cf11af 1/*
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2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
4 *
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
7 *
8 * PowerPC version
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
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17#include <linux/errno.h>
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
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22#include <linux/stddef.h>
23#include <linux/unistd.h>
24#include <linux/ptrace.h>
25#include <linux/slab.h>
26#include <linux/user.h>
27#include <linux/elf.h>
28#include <linux/init.h>
29#include <linux/prctl.h>
30#include <linux/init_task.h>
31#include <linux/module.h>
32#include <linux/kallsyms.h>
33#include <linux/mqueue.h>
34#include <linux/hardirq.h>
06d67d54 35#include <linux/utsname.h>
6794c782 36#include <linux/ftrace.h>
79741dd3 37#include <linux/kernel_stat.h>
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38#include <linux/personality.h>
39#include <linux/random.h>
5aae8a53 40#include <linux/hw_breakpoint.h>
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41
42#include <asm/pgtable.h>
43#include <asm/uaccess.h>
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/processor.h>
47#include <asm/mmu.h>
48#include <asm/prom.h>
76032de8 49#include <asm/machdep.h>
c6622f63 50#include <asm/time.h>
a7f31841 51#include <asm/syscalls.h>
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52#ifdef CONFIG_PPC64
53#include <asm/firmware.h>
06d67d54 54#endif
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55#include <linux/kprobes.h>
56#include <linux/kdebug.h>
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57
58extern unsigned long _get_SP(void);
59
60#ifndef CONFIG_SMP
61struct task_struct *last_task_used_math = NULL;
62struct task_struct *last_task_used_altivec = NULL;
ce48b210 63struct task_struct *last_task_used_vsx = NULL;
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64struct task_struct *last_task_used_spe = NULL;
65#endif
66
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67/*
68 * Make sure the floating-point register state in the
69 * the thread_struct is up to date for task tsk.
70 */
71void flush_fp_to_thread(struct task_struct *tsk)
72{
73 if (tsk->thread.regs) {
74 /*
75 * We need to disable preemption here because if we didn't,
76 * another process could get scheduled after the regs->msr
77 * test but before we have finished saving the FP registers
78 * to the thread_struct. That process could take over the
79 * FPU, and then when we get scheduled again we would store
80 * bogus values for the remaining FP registers.
81 */
82 preempt_disable();
83 if (tsk->thread.regs->msr & MSR_FP) {
84#ifdef CONFIG_SMP
85 /*
86 * This should only ever be called for current or
87 * for a stopped child process. Since we save away
88 * the FP register state on context switch on SMP,
89 * there is something wrong if a stopped child appears
90 * to still have its FP state in the CPU registers.
91 */
92 BUG_ON(tsk != current);
93#endif
0ee6c15e 94 giveup_fpu(tsk);
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95 }
96 preempt_enable();
97 }
98}
de56a948 99EXPORT_SYMBOL_GPL(flush_fp_to_thread);
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100
101void enable_kernel_fp(void)
102{
103 WARN_ON(preemptible());
104
105#ifdef CONFIG_SMP
106 if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
107 giveup_fpu(current);
108 else
109 giveup_fpu(NULL); /* just enables FP for kernel */
110#else
111 giveup_fpu(last_task_used_math);
112#endif /* CONFIG_SMP */
113}
114EXPORT_SYMBOL(enable_kernel_fp);
115
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116#ifdef CONFIG_ALTIVEC
117void enable_kernel_altivec(void)
118{
119 WARN_ON(preemptible());
120
121#ifdef CONFIG_SMP
122 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
123 giveup_altivec(current);
124 else
125 giveup_altivec(NULL); /* just enable AltiVec for kernel - force */
126#else
127 giveup_altivec(last_task_used_altivec);
128#endif /* CONFIG_SMP */
129}
130EXPORT_SYMBOL(enable_kernel_altivec);
131
132/*
133 * Make sure the VMX/Altivec register state in the
134 * the thread_struct is up to date for task tsk.
135 */
136void flush_altivec_to_thread(struct task_struct *tsk)
137{
138 if (tsk->thread.regs) {
139 preempt_disable();
140 if (tsk->thread.regs->msr & MSR_VEC) {
141#ifdef CONFIG_SMP
142 BUG_ON(tsk != current);
143#endif
0ee6c15e 144 giveup_altivec(tsk);
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145 }
146 preempt_enable();
147 }
148}
de56a948 149EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
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150#endif /* CONFIG_ALTIVEC */
151
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152#ifdef CONFIG_VSX
153#if 0
154/* not currently used, but some crazy RAID module might want to later */
155void enable_kernel_vsx(void)
156{
157 WARN_ON(preemptible());
158
159#ifdef CONFIG_SMP
160 if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
161 giveup_vsx(current);
162 else
163 giveup_vsx(NULL); /* just enable vsx for kernel - force */
164#else
165 giveup_vsx(last_task_used_vsx);
166#endif /* CONFIG_SMP */
167}
168EXPORT_SYMBOL(enable_kernel_vsx);
169#endif
170
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171void giveup_vsx(struct task_struct *tsk)
172{
173 giveup_fpu(tsk);
174 giveup_altivec(tsk);
175 __giveup_vsx(tsk);
176}
177
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178void flush_vsx_to_thread(struct task_struct *tsk)
179{
180 if (tsk->thread.regs) {
181 preempt_disable();
182 if (tsk->thread.regs->msr & MSR_VSX) {
183#ifdef CONFIG_SMP
184 BUG_ON(tsk != current);
185#endif
186 giveup_vsx(tsk);
187 }
188 preempt_enable();
189 }
190}
de56a948 191EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
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192#endif /* CONFIG_VSX */
193
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194#ifdef CONFIG_SPE
195
196void enable_kernel_spe(void)
197{
198 WARN_ON(preemptible());
199
200#ifdef CONFIG_SMP
201 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
202 giveup_spe(current);
203 else
204 giveup_spe(NULL); /* just enable SPE for kernel - force */
205#else
206 giveup_spe(last_task_used_spe);
207#endif /* __SMP __ */
208}
209EXPORT_SYMBOL(enable_kernel_spe);
210
211void flush_spe_to_thread(struct task_struct *tsk)
212{
213 if (tsk->thread.regs) {
214 preempt_disable();
215 if (tsk->thread.regs->msr & MSR_SPE) {
216#ifdef CONFIG_SMP
217 BUG_ON(tsk != current);
218#endif
685659ee 219 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
0ee6c15e 220 giveup_spe(tsk);
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221 }
222 preempt_enable();
223 }
224}
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225#endif /* CONFIG_SPE */
226
5388fb10 227#ifndef CONFIG_SMP
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228/*
229 * If we are doing lazy switching of CPU state (FP, altivec or SPE),
230 * and the current task has some state, discard it.
231 */
5388fb10 232void discard_lazy_cpu_state(void)
48abec07 233{
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234 preempt_disable();
235 if (last_task_used_math == current)
236 last_task_used_math = NULL;
237#ifdef CONFIG_ALTIVEC
238 if (last_task_used_altivec == current)
239 last_task_used_altivec = NULL;
240#endif /* CONFIG_ALTIVEC */
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241#ifdef CONFIG_VSX
242 if (last_task_used_vsx == current)
243 last_task_used_vsx = NULL;
244#endif /* CONFIG_VSX */
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245#ifdef CONFIG_SPE
246 if (last_task_used_spe == current)
247 last_task_used_spe = NULL;
248#endif
249 preempt_enable();
48abec07 250}
5388fb10 251#endif /* CONFIG_SMP */
48abec07 252
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253#ifdef CONFIG_PPC_ADV_DEBUG_REGS
254void do_send_trap(struct pt_regs *regs, unsigned long address,
255 unsigned long error_code, int signal_code, int breakpt)
256{
257 siginfo_t info;
258
259 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
260 11, SIGSEGV) == NOTIFY_STOP)
261 return;
262
263 /* Deliver the signal to userspace */
264 info.si_signo = SIGTRAP;
265 info.si_errno = breakpt; /* breakpoint or watchpoint id */
266 info.si_code = signal_code;
267 info.si_addr = (void __user *)address;
268 force_sig_info(SIGTRAP, &info, current);
269}
270#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
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271void do_dabr(struct pt_regs *regs, unsigned long address,
272 unsigned long error_code)
273{
274 siginfo_t info;
275
276 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
277 11, SIGSEGV) == NOTIFY_STOP)
278 return;
279
280 if (debugger_dabr_match(regs))
281 return;
282
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283 /* Clear the DABR */
284 set_dabr(0);
285
286 /* Deliver the signal to userspace */
287 info.si_signo = SIGTRAP;
288 info.si_errno = 0;
289 info.si_code = TRAP_HWBKPT;
290 info.si_addr = (void __user *)address;
291 force_sig_info(SIGTRAP, &info, current);
292}
3bffb652 293#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
d6a61bfc 294
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295static DEFINE_PER_CPU(unsigned long, current_dabr);
296
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297#ifdef CONFIG_PPC_ADV_DEBUG_REGS
298/*
299 * Set the debug registers back to their default "safe" values.
300 */
301static void set_debug_reg_defaults(struct thread_struct *thread)
302{
303 thread->iac1 = thread->iac2 = 0;
304#if CONFIG_PPC_ADV_DEBUG_IACS > 2
305 thread->iac3 = thread->iac4 = 0;
306#endif
307 thread->dac1 = thread->dac2 = 0;
308#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
309 thread->dvc1 = thread->dvc2 = 0;
310#endif
311 thread->dbcr0 = 0;
312#ifdef CONFIG_BOOKE
313 /*
314 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
315 */
316 thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \
317 DBCR1_IAC3US | DBCR1_IAC4US;
318 /*
319 * Force Data Address Compare User/Supervisor bits to be User-only
320 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
321 */
322 thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
323#else
324 thread->dbcr1 = 0;
325#endif
326}
327
328static void prime_debug_regs(struct thread_struct *thread)
329{
330 mtspr(SPRN_IAC1, thread->iac1);
331 mtspr(SPRN_IAC2, thread->iac2);
332#if CONFIG_PPC_ADV_DEBUG_IACS > 2
333 mtspr(SPRN_IAC3, thread->iac3);
334 mtspr(SPRN_IAC4, thread->iac4);
335#endif
336 mtspr(SPRN_DAC1, thread->dac1);
337 mtspr(SPRN_DAC2, thread->dac2);
338#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
339 mtspr(SPRN_DVC1, thread->dvc1);
340 mtspr(SPRN_DVC2, thread->dvc2);
341#endif
342 mtspr(SPRN_DBCR0, thread->dbcr0);
343 mtspr(SPRN_DBCR1, thread->dbcr1);
344#ifdef CONFIG_BOOKE
345 mtspr(SPRN_DBCR2, thread->dbcr2);
346#endif
347}
348/*
349 * Unless neither the old or new thread are making use of the
350 * debug registers, set the debug registers from the values
351 * stored in the new thread.
352 */
353static void switch_booke_debug_regs(struct thread_struct *new_thread)
354{
355 if ((current->thread.dbcr0 & DBCR0_IDM)
356 || (new_thread->dbcr0 & DBCR0_IDM))
357 prime_debug_regs(new_thread);
358}
359#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
e0780b72 360#ifndef CONFIG_HAVE_HW_BREAKPOINT
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361static void set_debug_reg_defaults(struct thread_struct *thread)
362{
363 if (thread->dabr) {
364 thread->dabr = 0;
365 set_dabr(0);
366 }
367}
e0780b72 368#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
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369#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
370
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371int set_dabr(unsigned long dabr)
372{
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373 __get_cpu_var(current_dabr) = dabr;
374
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375 if (ppc_md.set_dabr)
376 return ppc_md.set_dabr(dabr);
14cf11af 377
791cc501 378 /* XXX should we have a CPU_FTR_HAS_DABR ? */
172ae2e7 379#ifdef CONFIG_PPC_ADV_DEBUG_REGS
d6a61bfc 380 mtspr(SPRN_DAC1, dabr);
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381#ifdef CONFIG_PPC_47x
382 isync();
383#endif
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384#elif defined(CONFIG_PPC_BOOK3S)
385 mtspr(SPRN_DABR, dabr);
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386#endif
387
c6c9eace 388
cab0af98 389 return 0;
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390}
391
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392#ifdef CONFIG_PPC64
393DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
06d67d54 394#endif
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395
396struct task_struct *__switch_to(struct task_struct *prev,
397 struct task_struct *new)
398{
399 struct thread_struct *new_thread, *old_thread;
400 unsigned long flags;
401 struct task_struct *last;
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402#ifdef CONFIG_PPC_BOOK3S_64
403 struct ppc64_tlb_batch *batch;
404#endif
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405
406#ifdef CONFIG_SMP
407 /* avoid complexity of lazy save/restore of fpu
408 * by just saving it every time we switch out if
409 * this task used the fpu during the last quantum.
410 *
411 * If it tries to use the fpu again, it'll trap and
412 * reload its fp regs. So we don't have to do a restore
413 * every switch, just a save.
414 * -- Cort
415 */
416 if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
417 giveup_fpu(prev);
418#ifdef CONFIG_ALTIVEC
419 /*
420 * If the previous thread used altivec in the last quantum
421 * (thus changing altivec regs) then save them.
422 * We used to check the VRSAVE register but not all apps
423 * set it, so we don't rely on it now (and in fact we need
424 * to save & restore VSCR even if VRSAVE == 0). -- paulus
425 *
426 * On SMP we always save/restore altivec regs just to avoid the
427 * complexity of changing processors.
428 * -- Cort
429 */
430 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
431 giveup_altivec(prev);
14cf11af 432#endif /* CONFIG_ALTIVEC */
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433#ifdef CONFIG_VSX
434 if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
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435 /* VMX and FPU registers are already save here */
436 __giveup_vsx(prev);
ce48b210 437#endif /* CONFIG_VSX */
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438#ifdef CONFIG_SPE
439 /*
440 * If the previous thread used spe in the last quantum
441 * (thus changing spe regs) then save them.
442 *
443 * On SMP we always save/restore spe regs just to avoid the
444 * complexity of changing processors.
445 */
446 if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
447 giveup_spe(prev);
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448#endif /* CONFIG_SPE */
449
450#else /* CONFIG_SMP */
451#ifdef CONFIG_ALTIVEC
452 /* Avoid the trap. On smp this this never happens since
453 * we don't set last_task_used_altivec -- Cort
454 */
455 if (new->thread.regs && last_task_used_altivec == new)
456 new->thread.regs->msr |= MSR_VEC;
457#endif /* CONFIG_ALTIVEC */
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458#ifdef CONFIG_VSX
459 if (new->thread.regs && last_task_used_vsx == new)
460 new->thread.regs->msr |= MSR_VSX;
461#endif /* CONFIG_VSX */
c0c0d996 462#ifdef CONFIG_SPE
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463 /* Avoid the trap. On smp this this never happens since
464 * we don't set last_task_used_spe
465 */
466 if (new->thread.regs && last_task_used_spe == new)
467 new->thread.regs->msr |= MSR_SPE;
468#endif /* CONFIG_SPE */
c0c0d996 469
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470#endif /* CONFIG_SMP */
471
172ae2e7 472#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3bffb652 473 switch_booke_debug_regs(&new->thread);
c6c9eace 474#else
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475/*
476 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
477 * schedule DABR
478 */
479#ifndef CONFIG_HAVE_HW_BREAKPOINT
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480 if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
481 set_dabr(new->thread.dabr);
5aae8a53 482#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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483#endif
484
c6c9eace 485
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486 new_thread = &new->thread;
487 old_thread = &current->thread;
06d67d54 488
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489#if defined(CONFIG_PPC_BOOK3E_64)
490 /* XXX Current Book3E code doesn't deal with kernel side DBCR0,
491 * we always hold the user values, so we set it now.
492 *
493 * However, we ensure the kernel MSR:DE is appropriately cleared too
494 * to avoid spurrious single step exceptions in the kernel.
495 *
496 * This will have to change to merge with the ppc32 code at some point,
497 * but I don't like much what ppc32 is doing today so there's some
498 * thinking needed there
499 */
500 if ((new_thread->dbcr0 | old_thread->dbcr0) & DBCR0_IDM) {
501 u32 dbcr0;
502
503 mtmsr(mfmsr() & ~MSR_DE);
504 isync();
505 dbcr0 = mfspr(SPRN_DBCR0);
506 dbcr0 = (dbcr0 & DBCR0_EDM) | new_thread->dbcr0;
507 mtspr(SPRN_DBCR0, dbcr0);
508 }
509#endif /* CONFIG_PPC64_BOOK3E */
510
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511#ifdef CONFIG_PPC64
512 /*
513 * Collect processor utilization data per process
514 */
515 if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
516 struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
517 long unsigned start_tb, current_tb;
518 start_tb = old_thread->start_tb;
519 cu->current_tb = current_tb = mfspr(SPRN_PURR);
520 old_thread->accum_tb += (current_tb - start_tb);
521 new_thread->start_tb = current_tb;
522 }
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523#endif /* CONFIG_PPC64 */
524
525#ifdef CONFIG_PPC_BOOK3S_64
526 batch = &__get_cpu_var(ppc64_tlb_batch);
527 if (batch->active) {
528 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
529 if (batch->index)
530 __flush_tlb_pending(batch);
531 batch->active = 0;
532 }
533#endif /* CONFIG_PPC_BOOK3S_64 */
06d67d54 534
14cf11af 535 local_irq_save(flags);
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536
537 account_system_vtime(current);
81a3843f 538 account_process_vtime(current);
c6622f63 539
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540 /*
541 * We can't take a PMU exception inside _switch() since there is a
542 * window where the kernel stack SLB and the kernel stack are out
543 * of sync. Hard disable here.
544 */
545 hard_irq_disable();
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546 last = _switch(old_thread, new_thread);
547
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548#ifdef CONFIG_PPC_BOOK3S_64
549 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
550 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
551 batch = &__get_cpu_var(ppc64_tlb_batch);
552 batch->active = 1;
553 }
554#endif /* CONFIG_PPC_BOOK3S_64 */
555
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556 local_irq_restore(flags);
557
558 return last;
559}
560
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561static int instructions_to_print = 16;
562
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563static void show_instructions(struct pt_regs *regs)
564{
565 int i;
566 unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
567 sizeof(int));
568
569 printk("Instruction dump:");
570
571 for (i = 0; i < instructions_to_print; i++) {
572 int instr;
573
574 if (!(i % 8))
575 printk("\n");
576
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577#if !defined(CONFIG_BOOKE)
578 /* If executing with the IMMU off, adjust pc rather
579 * than print XXXXXXXX.
580 */
581 if (!(regs->msr & MSR_IR))
582 pc = (unsigned long)phys_to_virt(pc);
583#endif
584
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585 /* We use __get_user here *only* to avoid an OOPS on a
586 * bad address because the pc *should* only be a
587 * kernel address.
588 */
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589 if (!__kernel_text_address(pc) ||
590 __get_user(instr, (unsigned int __user *)pc)) {
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591 printk("XXXXXXXX ");
592 } else {
593 if (regs->nip == pc)
594 printk("<%08x> ", instr);
595 else
596 printk("%08x ", instr);
597 }
598
599 pc += sizeof(int);
600 }
601
602 printk("\n");
603}
604
605static struct regbit {
606 unsigned long bit;
607 const char *name;
608} msr_bits[] = {
609 {MSR_EE, "EE"},
610 {MSR_PR, "PR"},
611 {MSR_FP, "FP"},
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612 {MSR_VEC, "VEC"},
613 {MSR_VSX, "VSX"},
06d67d54 614 {MSR_ME, "ME"},
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615 {MSR_CE, "CE"},
616 {MSR_DE, "DE"},
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617 {MSR_IR, "IR"},
618 {MSR_DR, "DR"},
619 {0, NULL}
620};
621
622static void printbits(unsigned long val, struct regbit *bits)
623{
624 const char *sep = "";
625
626 printk("<");
627 for (; bits->bit; ++bits)
628 if (val & bits->bit) {
629 printk("%s%s", sep, bits->name);
630 sep = ",";
631 }
632 printk(">");
633}
634
635#ifdef CONFIG_PPC64
f6f7dde3 636#define REG "%016lx"
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637#define REGS_PER_LINE 4
638#define LAST_VOLATILE 13
639#else
f6f7dde3 640#define REG "%08lx"
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641#define REGS_PER_LINE 8
642#define LAST_VOLATILE 12
643#endif
644
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645void show_regs(struct pt_regs * regs)
646{
647 int i, trap;
648
06d67d54
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649 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
650 regs->nip, regs->link, regs->ctr);
651 printk("REGS: %p TRAP: %04lx %s (%s)\n",
96b644bd 652 regs, regs->trap, print_tainted(), init_utsname()->release);
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653 printk("MSR: "REG" ", regs->msr);
654 printbits(regs->msr, msr_bits);
f6f7dde3 655 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
14cf11af 656 trap = TRAP(regs);
5115a026
MN
657 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
658 printk("CFAR: "REG"\n", regs->orig_gpr3);
14cf11af 659 if (trap == 0x300 || trap == 0x600)
172ae2e7 660#ifdef CONFIG_PPC_ADV_DEBUG_REGS
14170789
KG
661 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
662#else
7071854b 663 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
14170789 664#endif
06d67d54 665 printk("TASK = %p[%d] '%s' THREAD: %p",
19c5870c 666 current, task_pid_nr(current), current->comm, task_thread_info(current));
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667
668#ifdef CONFIG_SMP
79ccd1be 669 printk(" CPU: %d", raw_smp_processor_id());
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670#endif /* CONFIG_SMP */
671
672 for (i = 0; i < 32; i++) {
06d67d54 673 if ((i % REGS_PER_LINE) == 0)
a2367194 674 printk("\nGPR%02d: ", i);
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675 printk(REG " ", regs->gpr[i]);
676 if (i == LAST_VOLATILE && !FULL_REGS(regs))
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677 break;
678 }
679 printk("\n");
680#ifdef CONFIG_KALLSYMS
681 /*
682 * Lookup NIP late so we have the best change of getting the
683 * above info out without failing
684 */
058c78f4
BH
685 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
686 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
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687#endif
688 show_stack(current, (unsigned long *) regs->gpr[1]);
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689 if (!user_mode(regs))
690 show_instructions(regs);
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691}
692
693void exit_thread(void)
694{
48abec07 695 discard_lazy_cpu_state();
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696}
697
698void flush_thread(void)
699{
48abec07 700 discard_lazy_cpu_state();
14cf11af 701
e0780b72 702#ifdef CONFIG_HAVE_HW_BREAKPOINT
5aae8a53 703 flush_ptrace_hw_breakpoint(current);
e0780b72 704#else /* CONFIG_HAVE_HW_BREAKPOINT */
3bffb652 705 set_debug_reg_defaults(&current->thread);
e0780b72 706#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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707}
708
709void
710release_thread(struct task_struct *t)
711{
712}
713
714/*
715 * This gets called before we allocate a new thread and copy
716 * the current task into it.
717 */
718void prepare_to_copy(struct task_struct *tsk)
719{
720 flush_fp_to_thread(current);
721 flush_altivec_to_thread(current);
ce48b210 722 flush_vsx_to_thread(current);
14cf11af 723 flush_spe_to_thread(current);
5aae8a53
P
724#ifdef CONFIG_HAVE_HW_BREAKPOINT
725 flush_ptrace_hw_breakpoint(tsk);
726#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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727}
728
729/*
730 * Copy a thread..
731 */
efcac658
AK
732extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */
733
6f2c55b8 734int copy_thread(unsigned long clone_flags, unsigned long usp,
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735 unsigned long unused, struct task_struct *p,
736 struct pt_regs *regs)
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737{
738 struct pt_regs *childregs, *kregs;
739 extern void ret_from_fork(void);
0cec6fd1 740 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
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741
742 CHECK_FULL_REGS(regs);
743 /* Copy registers */
744 sp -= sizeof(struct pt_regs);
745 childregs = (struct pt_regs *) sp;
746 *childregs = *regs;
747 if ((childregs->msr & MSR_PR) == 0) {
748 /* for kernel thread, set `current' and stackptr in new task */
749 childregs->gpr[1] = sp + sizeof(struct pt_regs);
06d67d54 750#ifdef CONFIG_PPC32
14cf11af 751 childregs->gpr[2] = (unsigned long) p;
06d67d54 752#else
b5e2fc1c 753 clear_tsk_thread_flag(p, TIF_32BIT);
06d67d54 754#endif
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755 p->thread.regs = NULL; /* no user register state */
756 } else {
757 childregs->gpr[1] = usp;
758 p->thread.regs = childregs;
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759 if (clone_flags & CLONE_SETTLS) {
760#ifdef CONFIG_PPC64
9904b005 761 if (!is_32bit_task())
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762 childregs->gpr[13] = childregs->gpr[6];
763 else
764#endif
765 childregs->gpr[2] = childregs->gpr[6];
766 }
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767 }
768 childregs->gpr[3] = 0; /* Result from fork() */
769 sp -= STACK_FRAME_OVERHEAD;
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770
771 /*
772 * The way this works is that at some point in the future
773 * some task will call _switch to switch to the new task.
774 * That will pop off the stack frame created below and start
775 * the new task running at ret_from_fork. The new task will
776 * do some house keeping and then return from the fork or clone
777 * system call, using the stack frame created above.
778 */
779 sp -= sizeof(struct pt_regs);
780 kregs = (struct pt_regs *) sp;
781 sp -= STACK_FRAME_OVERHEAD;
782 p->thread.ksp = sp;
85218827
KG
783 p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
784 _ALIGN_UP(sizeof(struct thread_info), 16);
14cf11af 785
94491685 786#ifdef CONFIG_PPC_STD_MMU_64
44ae3ab3 787 if (mmu_has_feature(MMU_FTR_SLB)) {
1189be65 788 unsigned long sp_vsid;
3c726f8d 789 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
06d67d54 790
44ae3ab3 791 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1189be65
PM
792 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
793 << SLB_VSID_SHIFT_1T;
794 else
795 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
796 << SLB_VSID_SHIFT;
3c726f8d 797 sp_vsid |= SLB_VSID_KERNEL | llp;
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798 p->thread.ksp_vsid = sp_vsid;
799 }
747bea91 800#endif /* CONFIG_PPC_STD_MMU_64 */
efcac658
AK
801#ifdef CONFIG_PPC64
802 if (cpu_has_feature(CPU_FTR_DSCR)) {
803 if (current->thread.dscr_inherit) {
804 p->thread.dscr_inherit = 1;
805 p->thread.dscr = current->thread.dscr;
806 } else if (0 != dscr_default) {
807 p->thread.dscr_inherit = 1;
808 p->thread.dscr = dscr_default;
809 } else {
810 p->thread.dscr_inherit = 0;
811 p->thread.dscr = 0;
812 }
813 }
814#endif
06d67d54
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815
816 /*
817 * The PPC64 ABI makes use of a TOC to contain function
818 * pointers. The function (ret_from_except) is actually a pointer
819 * to the TOC entry. The first entry is a pointer to the actual
820 * function.
821 */
747bea91 822#ifdef CONFIG_PPC64
06d67d54
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823 kregs->nip = *((unsigned long *)ret_from_fork);
824#else
825 kregs->nip = (unsigned long)ret_from_fork;
06d67d54 826#endif
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827
828 return 0;
829}
830
831/*
832 * Set up a thread for executing a new program
833 */
06d67d54 834void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
14cf11af 835{
90eac727
ME
836#ifdef CONFIG_PPC64
837 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
838#endif
839
06d67d54
PM
840 /*
841 * If we exec out of a kernel thread then thread.regs will not be
842 * set. Do it now.
843 */
844 if (!current->thread.regs) {
0cec6fd1
AV
845 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
846 current->thread.regs = regs - 1;
06d67d54
PM
847 }
848
14cf11af
PM
849 memset(regs->gpr, 0, sizeof(regs->gpr));
850 regs->ctr = 0;
851 regs->link = 0;
852 regs->xer = 0;
853 regs->ccr = 0;
14cf11af 854 regs->gpr[1] = sp;
06d67d54 855
474f8196
RM
856 /*
857 * We have just cleared all the nonvolatile GPRs, so make
858 * FULL_REGS(regs) return true. This is necessary to allow
859 * ptrace to examine the thread immediately after exec.
860 */
861 regs->trap &= ~1UL;
862
06d67d54
PM
863#ifdef CONFIG_PPC32
864 regs->mq = 0;
865 regs->nip = start;
14cf11af 866 regs->msr = MSR_USER;
06d67d54 867#else
9904b005 868 if (!is_32bit_task()) {
90eac727 869 unsigned long entry, toc;
06d67d54
PM
870
871 /* start is a relocated pointer to the function descriptor for
872 * the elf _start routine. The first entry in the function
873 * descriptor is the entry address of _start and the second
874 * entry is the TOC value we need to use.
875 */
876 __get_user(entry, (unsigned long __user *)start);
877 __get_user(toc, (unsigned long __user *)start+1);
878
879 /* Check whether the e_entry function descriptor entries
880 * need to be relocated before we can use them.
881 */
882 if (load_addr != 0) {
883 entry += load_addr;
884 toc += load_addr;
885 }
886 regs->nip = entry;
887 regs->gpr[2] = toc;
888 regs->msr = MSR_USER64;
d4bf9a78
SR
889 } else {
890 regs->nip = start;
891 regs->gpr[2] = 0;
892 regs->msr = MSR_USER32;
06d67d54
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893 }
894#endif
895
48abec07 896 discard_lazy_cpu_state();
ce48b210
MN
897#ifdef CONFIG_VSX
898 current->thread.used_vsr = 0;
899#endif
14cf11af 900 memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
25c8a78b 901 current->thread.fpscr.val = 0;
14cf11af
PM
902#ifdef CONFIG_ALTIVEC
903 memset(current->thread.vr, 0, sizeof(current->thread.vr));
904 memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
06d67d54 905 current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */
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906 current->thread.vrsave = 0;
907 current->thread.used_vr = 0;
908#endif /* CONFIG_ALTIVEC */
909#ifdef CONFIG_SPE
910 memset(current->thread.evr, 0, sizeof(current->thread.evr));
911 current->thread.acc = 0;
912 current->thread.spefscr = 0;
913 current->thread.used_spe = 0;
914#endif /* CONFIG_SPE */
915}
916
917#define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
918 | PR_FP_EXC_RES | PR_FP_EXC_INV)
919
920int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
921{
922 struct pt_regs *regs = tsk->thread.regs;
923
924 /* This is a bit hairy. If we are an SPE enabled processor
925 * (have embedded fp) we store the IEEE exception enable flags in
926 * fpexc_mode. fpexc_mode is also used for setting FP exception
927 * mode (asyn, precise, disabled) for 'Classic' FP. */
928 if (val & PR_FP_EXC_SW_ENABLE) {
929#ifdef CONFIG_SPE
5e14d21e
KG
930 if (cpu_has_feature(CPU_FTR_SPE)) {
931 tsk->thread.fpexc_mode = val &
932 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
933 return 0;
934 } else {
935 return -EINVAL;
936 }
14cf11af
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937#else
938 return -EINVAL;
939#endif
14cf11af 940 }
06d67d54
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941
942 /* on a CONFIG_SPE this does not hurt us. The bits that
943 * __pack_fe01 use do not overlap with bits used for
944 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
945 * on CONFIG_SPE implementations are reserved so writing to
946 * them does not change anything */
947 if (val > PR_FP_EXC_PRECISE)
948 return -EINVAL;
949 tsk->thread.fpexc_mode = __pack_fe01(val);
950 if (regs != NULL && (regs->msr & MSR_FP) != 0)
951 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
952 | tsk->thread.fpexc_mode;
14cf11af
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953 return 0;
954}
955
956int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
957{
958 unsigned int val;
959
960 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
961#ifdef CONFIG_SPE
5e14d21e
KG
962 if (cpu_has_feature(CPU_FTR_SPE))
963 val = tsk->thread.fpexc_mode;
964 else
965 return -EINVAL;
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966#else
967 return -EINVAL;
968#endif
969 else
970 val = __unpack_fe01(tsk->thread.fpexc_mode);
971 return put_user(val, (unsigned int __user *) adr);
972}
973
fab5db97
PM
974int set_endian(struct task_struct *tsk, unsigned int val)
975{
976 struct pt_regs *regs = tsk->thread.regs;
977
978 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
979 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
980 return -EINVAL;
981
982 if (regs == NULL)
983 return -EINVAL;
984
985 if (val == PR_ENDIAN_BIG)
986 regs->msr &= ~MSR_LE;
987 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
988 regs->msr |= MSR_LE;
989 else
990 return -EINVAL;
991
992 return 0;
993}
994
995int get_endian(struct task_struct *tsk, unsigned long adr)
996{
997 struct pt_regs *regs = tsk->thread.regs;
998 unsigned int val;
999
1000 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1001 !cpu_has_feature(CPU_FTR_REAL_LE))
1002 return -EINVAL;
1003
1004 if (regs == NULL)
1005 return -EINVAL;
1006
1007 if (regs->msr & MSR_LE) {
1008 if (cpu_has_feature(CPU_FTR_REAL_LE))
1009 val = PR_ENDIAN_LITTLE;
1010 else
1011 val = PR_ENDIAN_PPC_LITTLE;
1012 } else
1013 val = PR_ENDIAN_BIG;
1014
1015 return put_user(val, (unsigned int __user *)adr);
1016}
1017
e9370ae1
PM
1018int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1019{
1020 tsk->thread.align_ctl = val;
1021 return 0;
1022}
1023
1024int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1025{
1026 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1027}
1028
06d67d54
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1029#define TRUNC_PTR(x) ((typeof(x))(((unsigned long)(x)) & 0xffffffff))
1030
14cf11af
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1031int sys_clone(unsigned long clone_flags, unsigned long usp,
1032 int __user *parent_tidp, void __user *child_threadptr,
1033 int __user *child_tidp, int p6,
1034 struct pt_regs *regs)
1035{
1036 CHECK_FULL_REGS(regs);
1037 if (usp == 0)
1038 usp = regs->gpr[1]; /* stack pointer for child */
06d67d54 1039#ifdef CONFIG_PPC64
9904b005 1040 if (is_32bit_task()) {
06d67d54
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1041 parent_tidp = TRUNC_PTR(parent_tidp);
1042 child_tidp = TRUNC_PTR(child_tidp);
1043 }
1044#endif
14cf11af
PM
1045 return do_fork(clone_flags, usp, regs, 0, parent_tidp, child_tidp);
1046}
1047
1048int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
1049 unsigned long p4, unsigned long p5, unsigned long p6,
1050 struct pt_regs *regs)
1051{
1052 CHECK_FULL_REGS(regs);
1053 return do_fork(SIGCHLD, regs->gpr[1], regs, 0, NULL, NULL);
1054}
1055
1056int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
1057 unsigned long p4, unsigned long p5, unsigned long p6,
1058 struct pt_regs *regs)
1059{
1060 CHECK_FULL_REGS(regs);
1061 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->gpr[1],
1062 regs, 0, NULL, NULL);
1063}
1064
1065int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
1066 unsigned long a3, unsigned long a4, unsigned long a5,
1067 struct pt_regs *regs)
1068{
1069 int error;
06d67d54 1070 char *filename;
14cf11af 1071
c7887325 1072 filename = getname((const char __user *) a0);
14cf11af
PM
1073 error = PTR_ERR(filename);
1074 if (IS_ERR(filename))
1075 goto out;
1076 flush_fp_to_thread(current);
1077 flush_altivec_to_thread(current);
1078 flush_spe_to_thread(current);
d7627467
DH
1079 error = do_execve(filename,
1080 (const char __user *const __user *) a1,
1081 (const char __user *const __user *) a2, regs);
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1082 putname(filename);
1083out:
1084 return error;
1085}
1086
bb72c481
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1087static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1088 unsigned long nbytes)
1089{
1090 unsigned long stack_page;
1091 unsigned long cpu = task_cpu(p);
1092
1093 /*
1094 * Avoid crashing if the stack has overflowed and corrupted
1095 * task_cpu(p), which is in the thread_info struct.
1096 */
1097 if (cpu < NR_CPUS && cpu_possible(cpu)) {
1098 stack_page = (unsigned long) hardirq_ctx[cpu];
1099 if (sp >= stack_page + sizeof(struct thread_struct)
1100 && sp <= stack_page + THREAD_SIZE - nbytes)
1101 return 1;
1102
1103 stack_page = (unsigned long) softirq_ctx[cpu];
1104 if (sp >= stack_page + sizeof(struct thread_struct)
1105 && sp <= stack_page + THREAD_SIZE - nbytes)
1106 return 1;
1107 }
1108 return 0;
1109}
1110
2f25194d 1111int validate_sp(unsigned long sp, struct task_struct *p,
14cf11af
PM
1112 unsigned long nbytes)
1113{
0cec6fd1 1114 unsigned long stack_page = (unsigned long)task_stack_page(p);
14cf11af
PM
1115
1116 if (sp >= stack_page + sizeof(struct thread_struct)
1117 && sp <= stack_page + THREAD_SIZE - nbytes)
1118 return 1;
1119
bb72c481 1120 return valid_irq_stack(sp, p, nbytes);
14cf11af
PM
1121}
1122
2f25194d
AB
1123EXPORT_SYMBOL(validate_sp);
1124
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1125unsigned long get_wchan(struct task_struct *p)
1126{
1127 unsigned long ip, sp;
1128 int count = 0;
1129
1130 if (!p || p == current || p->state == TASK_RUNNING)
1131 return 0;
1132
1133 sp = p->thread.ksp;
ec2b36b9 1134 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
14cf11af
PM
1135 return 0;
1136
1137 do {
1138 sp = *(unsigned long *)sp;
ec2b36b9 1139 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
14cf11af
PM
1140 return 0;
1141 if (count > 0) {
ec2b36b9 1142 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
14cf11af
PM
1143 if (!in_sched_functions(ip))
1144 return ip;
1145 }
1146 } while (count++ < 16);
1147 return 0;
1148}
06d67d54 1149
c4d04be1 1150static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
06d67d54
PM
1151
1152void show_stack(struct task_struct *tsk, unsigned long *stack)
1153{
1154 unsigned long sp, ip, lr, newsp;
1155 int count = 0;
1156 int firstframe = 1;
6794c782
SR
1157#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1158 int curr_frame = current->curr_ret_stack;
1159 extern void return_to_handler(void);
9135c3cc
SR
1160 unsigned long rth = (unsigned long)return_to_handler;
1161 unsigned long mrth = -1;
6794c782 1162#ifdef CONFIG_PPC64
9135c3cc
SR
1163 extern void mod_return_to_handler(void);
1164 rth = *(unsigned long *)rth;
1165 mrth = (unsigned long)mod_return_to_handler;
1166 mrth = *(unsigned long *)mrth;
6794c782
SR
1167#endif
1168#endif
06d67d54
PM
1169
1170 sp = (unsigned long) stack;
1171 if (tsk == NULL)
1172 tsk = current;
1173 if (sp == 0) {
1174 if (tsk == current)
1175 asm("mr %0,1" : "=r" (sp));
1176 else
1177 sp = tsk->thread.ksp;
1178 }
1179
1180 lr = 0;
1181 printk("Call Trace:\n");
1182 do {
ec2b36b9 1183 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
06d67d54
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1184 return;
1185
1186 stack = (unsigned long *) sp;
1187 newsp = stack[0];
ec2b36b9 1188 ip = stack[STACK_FRAME_LR_SAVE];
06d67d54 1189 if (!firstframe || ip != lr) {
058c78f4 1190 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
6794c782 1191#ifdef CONFIG_FUNCTION_GRAPH_TRACER
9135c3cc 1192 if ((ip == rth || ip == mrth) && curr_frame >= 0) {
6794c782
SR
1193 printk(" (%pS)",
1194 (void *)current->ret_stack[curr_frame].ret);
1195 curr_frame--;
1196 }
1197#endif
06d67d54
PM
1198 if (firstframe)
1199 printk(" (unreliable)");
1200 printk("\n");
1201 }
1202 firstframe = 0;
1203
1204 /*
1205 * See if this is an exception frame.
1206 * We look for the "regshere" marker in the current frame.
1207 */
ec2b36b9
BH
1208 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1209 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
06d67d54
PM
1210 struct pt_regs *regs = (struct pt_regs *)
1211 (sp + STACK_FRAME_OVERHEAD);
06d67d54 1212 lr = regs->link;
058c78f4
BH
1213 printk("--- Exception: %lx at %pS\n LR = %pS\n",
1214 regs->trap, (void *)regs->nip, (void *)lr);
06d67d54
PM
1215 firstframe = 1;
1216 }
1217
1218 sp = newsp;
1219 } while (count++ < kstack_depth_to_print);
1220}
1221
1222void dump_stack(void)
1223{
1224 show_stack(current, NULL);
1225}
1226EXPORT_SYMBOL(dump_stack);
cb2c9b27
AB
1227
1228#ifdef CONFIG_PPC64
1229void ppc64_runlatch_on(void)
1230{
1231 unsigned long ctrl;
1232
1233 if (cpu_has_feature(CPU_FTR_CTRL) && !test_thread_flag(TIF_RUNLATCH)) {
1234 HMT_medium();
1235
1236 ctrl = mfspr(SPRN_CTRLF);
1237 ctrl |= CTRL_RUNLATCH;
1238 mtspr(SPRN_CTRLT, ctrl);
1239
1240 set_thread_flag(TIF_RUNLATCH);
1241 }
1242}
1243
4138d653 1244void __ppc64_runlatch_off(void)
cb2c9b27
AB
1245{
1246 unsigned long ctrl;
1247
4138d653 1248 HMT_medium();
cb2c9b27 1249
4138d653 1250 clear_thread_flag(TIF_RUNLATCH);
cb2c9b27 1251
4138d653
AB
1252 ctrl = mfspr(SPRN_CTRLF);
1253 ctrl &= ~CTRL_RUNLATCH;
1254 mtspr(SPRN_CTRLT, ctrl);
cb2c9b27
AB
1255}
1256#endif
f6a61680
BH
1257
1258#if THREAD_SHIFT < PAGE_SHIFT
1259
1260static struct kmem_cache *thread_info_cache;
1261
b6a84016 1262struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
f6a61680
BH
1263{
1264 struct thread_info *ti;
1265
b6a84016 1266 ti = kmem_cache_alloc_node(thread_info_cache, GFP_KERNEL, node);
f6a61680
BH
1267 if (unlikely(ti == NULL))
1268 return NULL;
1269#ifdef CONFIG_DEBUG_STACK_USAGE
1270 memset(ti, 0, THREAD_SIZE);
1271#endif
1272 return ti;
1273}
1274
1275void free_thread_info(struct thread_info *ti)
1276{
1277 kmem_cache_free(thread_info_cache, ti);
1278}
1279
1280void thread_info_cache_init(void)
1281{
1282 thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
1283 THREAD_SIZE, 0, NULL);
1284 BUG_ON(thread_info_cache == NULL);
1285}
1286
1287#endif /* THREAD_SHIFT < PAGE_SHIFT */
d839088c
AB
1288
1289unsigned long arch_align_stack(unsigned long sp)
1290{
1291 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1292 sp -= get_random_int() & ~PAGE_MASK;
1293 return sp & ~0xf;
1294}
912f9ee2
AB
1295
1296static inline unsigned long brk_rnd(void)
1297{
1298 unsigned long rnd = 0;
1299
1300 /* 8MB for 32bit, 1GB for 64bit */
1301 if (is_32bit_task())
1302 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1303 else
1304 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1305
1306 return rnd << PAGE_SHIFT;
1307}
1308
1309unsigned long arch_randomize_brk(struct mm_struct *mm)
1310{
8bbde7a7
AB
1311 unsigned long base = mm->brk;
1312 unsigned long ret;
1313
ce7a35c7 1314#ifdef CONFIG_PPC_STD_MMU_64
8bbde7a7
AB
1315 /*
1316 * If we are using 1TB segments and we are allowed to randomise
1317 * the heap, we can put it above 1TB so it is backed by a 1TB
1318 * segment. Otherwise the heap will be in the bottom 1TB
1319 * which always uses 256MB segments and this may result in a
1320 * performance penalty.
1321 */
1322 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1323 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1324#endif
1325
1326 ret = PAGE_ALIGN(base + brk_rnd());
912f9ee2
AB
1327
1328 if (ret < mm->brk)
1329 return mm->brk;
1330
1331 return ret;
1332}
501cb16d
AB
1333
1334unsigned long randomize_et_dyn(unsigned long base)
1335{
1336 unsigned long ret = PAGE_ALIGN(base + brk_rnd());
1337
1338 if (ret < base)
1339 return base;
1340
1341 return ret;
1342}