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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
5a0e3ad6 19#include <linux/slab.h>
1b340bd7
MB		 20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23
0664678a
PZ		 24#include <asm/irq.h>
25
1b340bd7
MB		 26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/initval.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/pxa2xx-lib.h>
32
33#include <mach/hardware.h>
7ebc8d56 34#include <mach/dma.h>
1b340bd7
MB		 35#include <mach/regs-ssp.h>
36#include <mach/audio.h>
37#include <mach/ssp.h>
38
39#include "pxa2xx-pcm.h"
40#include "pxa-ssp.h"
41
42/*
43 * SSP audio private data
44 */
45struct ssp_priv {
f9efc9df 46 struct ssp_device *ssp;
1b340bd7
MB		 47 unsigned int sysclk;
48 int dai_fmt;
49#ifdef CONFIG_PM
f9efc9df
EM		 50 uint32_t cr0;
51 uint32_t cr1;
52 uint32_t to;
53 uint32_t psp;
1b340bd7
MB		 54#endif
55};
56
1b340bd7
MB		 57static void dump_registers(struct ssp_device *ssp)
58{
59 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
60 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
61 ssp_read_reg(ssp, SSTO));
62
63 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
64 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
65 ssp_read_reg(ssp, SSACD));
66}
67
f9efc9df
EM		 68static void ssp_enable(struct ssp_device *ssp)
69{
70 uint32_t sscr0;
71
72 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
73 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
74}
75
76static void ssp_disable(struct ssp_device *ssp)
77{
78 uint32_t sscr0;
79
80 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
81 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
82}
83
2d7e71fa
EM		 84struct pxa2xx_pcm_dma_data {
85 struct pxa2xx_pcm_dma_params params;
86 char name[20];
1b340bd7
MB		 87};
88
2d7e71fa 89static struct pxa2xx_pcm_dma_params *
8eb9feab 90ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
2d7e71fa
EM		 91{
92 struct pxa2xx_pcm_dma_data *dma;
93
94 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
95 if (dma == NULL)
96 return NULL;
97
98 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
8eb9feab 99 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
2d7e71fa
EM		 100
101 dma->params.name = dma->name;
102 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
103 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
104 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
8eb9feab 105 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
2d7e71fa
EM		 106 dma->params.dev_addr = ssp->phys_base + SSDR;
107
108 return &dma->params;
109}
110
dee89c4d
MB		 111static int pxa_ssp_startup(struct snd_pcm_substream *substream,
112 struct snd_soc_dai *dai)
1b340bd7
MB		 113{
114 struct snd_soc_pcm_runtime *rtd = substream->private_data;
115 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
116 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 117 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 118 int ret = 0;
119
120 if (!cpu_dai->active) {
f9efc9df
EM		 121 clk_enable(ssp->clk);
122 ssp_disable(ssp);
1b340bd7 123 }
2d7e71fa
EM		 124
125 if (cpu_dai->dma_data) {
126 kfree(cpu_dai->dma_data);
127 cpu_dai->dma_data = NULL;
128 }
1b340bd7
MB		 129 return ret;
130}
131
dee89c4d
MB		 132static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
133 struct snd_soc_dai *dai)
1b340bd7
MB		 134{
135 struct snd_soc_pcm_runtime *rtd = substream->private_data;
136 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
137 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 138 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 139
140 if (!cpu_dai->active) {
f9efc9df
EM		 141 ssp_disable(ssp);
142 clk_disable(ssp->clk);
1b340bd7 143 }
2d7e71fa
EM		 144
145 if (cpu_dai->dma_data) {
146 kfree(cpu_dai->dma_data);
147 cpu_dai->dma_data = NULL;
148 }
1b340bd7
MB		 149}
150
151#ifdef CONFIG_PM
152
dc7d7b83 153static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 154{
155 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 156 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 157
158 if (!cpu_dai->active)
988addf8 159 clk_enable(ssp->clk);
1b340bd7 160
f9efc9df
EM		 161 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
162 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
163 priv->to = __raw_readl(ssp->mmio_base + SSTO);
164 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
165
166 ssp_disable(ssp);
167 clk_disable(ssp->clk);
1b340bd7
MB		 168 return 0;
169}
170
dc7d7b83 171static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 172{
173 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df
EM		 174 struct ssp_device *ssp = priv->ssp;
175 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
1b340bd7 176
f9efc9df
EM		 177 clk_enable(ssp->clk);
178
179 __raw_writel(sssr, ssp->mmio_base + SSSR);
f9efc9df
EM		 180 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
181 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
182 __raw_writel(priv->to, ssp->mmio_base + SSTO);
183 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
026384d6
DM		 184
185 if (cpu_dai->active)
988addf8 186 ssp_enable(ssp);
026384d6 187 else
988addf8 188 clk_disable(ssp->clk);
1b340bd7
MB		 189
190 return 0;
191}
192
193#else
194#define pxa_ssp_suspend NULL
195#define pxa_ssp_resume NULL
196#endif
197
198/**
199 * ssp_set_clkdiv - set SSP clock divider
200 * @div: serial clock rate divider
201 */
1a297286 202static void ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 203{
1a297286
PZ		 204 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
205
206 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
207 sscr0 &= ~0x0000ff00;
208 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
209 } else {
210 sscr0 &= ~0x000fff00;
211 sscr0 |= (div - 1) << 8; /* 1..4096 */
212 }
213 ssp_write_reg(ssp, SSCR0, sscr0);
214}
215
216/**
217 * ssp_get_clkdiv - get SSP clock divider
218 */
219static u32 ssp_get_scr(struct ssp_device *ssp)
220{
221 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
222 u32 div;
1b340bd7 223
1a297286
PZ		 224 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
225 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
226 else
227 div = ((sscr0 >> 8) & 0xfff) + 1;
228 return div;
1b340bd7
MB		 229}
230
231/*
232 * Set the SSP ports SYSCLK.
233 */
234static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
235 int clk_id, unsigned int freq, int dir)
236{
237 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 238 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 239 int val;
240
241 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 242 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 243
244 dev_dbg(&ssp->pdev->dev,
449bd54d 245 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 246 cpu_dai->id, clk_id, freq);
247
248 switch (clk_id) {
249 case PXA_SSP_CLK_NET_PLL:
250 sscr0 |= SSCR0_MOD;
251 break;
252 case PXA_SSP_CLK_PLL:
253 /* Internal PLL is fixed */
254 if (cpu_is_pxa25x())
255 priv->sysclk = 1843200;
256 else
257 priv->sysclk = 13000000;
258 break;
259 case PXA_SSP_CLK_EXT:
260 priv->sysclk = freq;
261 sscr0 |= SSCR0_ECS;
262 break;
263 case PXA_SSP_CLK_NET:
264 priv->sysclk = freq;
265 sscr0 |= SSCR0_NCS | SSCR0_MOD;
266 break;
267 case PXA_SSP_CLK_AUDIO:
268 priv->sysclk = 0;
1a297286 269 ssp_set_scr(ssp, 1);
20a41eac 270 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 271 break;
272 default:
273 return -ENODEV;
274 }
275
276 /* The SSP clock must be disabled when changing SSP clock mode
277 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
278 if (!cpu_is_pxa3xx())
f9efc9df 279 clk_disable(ssp->clk);
1b340bd7
MB		 280 val = ssp_read_reg(ssp, SSCR0) | sscr0;
281 ssp_write_reg(ssp, SSCR0, val);
282 if (!cpu_is_pxa3xx())
f9efc9df 283 clk_enable(ssp->clk);
1b340bd7
MB		 284
285 return 0;
286}
287
288/*
289 * Set the SSP clock dividers.
290 */
291static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
292 int div_id, int div)
293{
294 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 295 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 296 int val;
297
298 switch (div_id) {
299 case PXA_SSP_AUDIO_DIV_ACDS:
300 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
301 ssp_write_reg(ssp, SSACD, val);
302 break;
303 case PXA_SSP_AUDIO_DIV_SCDB:
304 val = ssp_read_reg(ssp, SSACD);
305 val &= ~SSACD_SCDB;
306#if defined(CONFIG_PXA3xx)
307 if (cpu_is_pxa3xx())
308 val &= ~SSACD_SCDX8;
309#endif
310 switch (div) {
311 case PXA_SSP_CLK_SCDB_1:
312 val |= SSACD_SCDB;
313 break;
314 case PXA_SSP_CLK_SCDB_4:
315 break;
316#if defined(CONFIG_PXA3xx)
317 case PXA_SSP_CLK_SCDB_8:
318 if (cpu_is_pxa3xx())
319 val |= SSACD_SCDX8;
320 else
321 return -EINVAL;
322 break;
323#endif
324 default:
325 return -EINVAL;
326 }
327 ssp_write_reg(ssp, SSACD, val);
328 break;
329 case PXA_SSP_DIV_SCR:
1a297286 330 ssp_set_scr(ssp, div);
1b340bd7
MB		 331 break;
332 default:
333 return -ENODEV;
334 }
335
336 return 0;
337}
338
339/*
340 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
341 */
85488037
MB		 342static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
343 int source, unsigned int freq_in, unsigned int freq_out)
1b340bd7
MB		 344{
345 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 346 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 347 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
348
349#if defined(CONFIG_PXA3xx)
350 if (cpu_is_pxa3xx())
351 ssp_write_reg(ssp, SSACDD, 0);
352#endif
353
354 switch (freq_out) {
355 case 5622000:
356 break;
357 case 11345000:
358 ssacd |= (0x1 << 4);
359 break;
360 case 12235000:
361 ssacd |= (0x2 << 4);
362 break;
363 case 14857000:
364 ssacd |= (0x3 << 4);
365 break;
366 case 32842000:
367 ssacd |= (0x4 << 4);
368 break;
369 case 48000000:
370 ssacd |= (0x5 << 4);
371 break;
372 case 0:
373 /* Disable */
374 break;
375
376 default:
377#ifdef CONFIG_PXA3xx
378 /* PXA3xx has a clock ditherer which can be used to generate
379 * a wider range of frequencies - calculate a value for it.
380 */
381 if (cpu_is_pxa3xx()) {
382 u32 val;
383 u64 tmp = 19968;
384 tmp *= 1000000;
385 do_div(tmp, freq_out);
386 val = tmp;
387
a419aef8 388 val = (val << 16) | 64;
1b340bd7
MB		 389 ssp_write_reg(ssp, SSACDD, val);
390
391 ssacd |= (0x6 << 4);
392
393 dev_dbg(&ssp->pdev->dev,
449bd54d 394 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 395 val, freq_out);
396 break;
397 }
398#endif
399
400 return -EINVAL;
401 }
402
403 ssp_write_reg(ssp, SSACD, ssacd);
404
405 return 0;
406}
407
408/*
409 * Set the active slots in TDM/Network mode
410 */
411static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
a5479e38 412 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1b340bd7
MB		 413{
414 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 415 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 416 u32 sscr0;
417
a5479e38
DR		 418 sscr0 = ssp_read_reg(ssp, SSCR0);
419 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
1b340bd7 420
a5479e38
DR		 421 /* set slot width */
422 if (slot_width > 16)
423 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
424 else
425 sscr0 |= SSCR0_DataSize(slot_width);
426
427 if (slots > 1) {
428 /* enable network mode */
429 sscr0 |= SSCR0_MOD;
430
431 /* set number of active slots */
432 sscr0 |= SSCR0_SlotsPerFrm(slots);
433
434 /* set active slot mask */
435 ssp_write_reg(ssp, SSTSA, tx_mask);
436 ssp_write_reg(ssp, SSRSA, rx_mask);
437 }
1b340bd7
MB		 438 ssp_write_reg(ssp, SSCR0, sscr0);
439
1b340bd7
MB		 440 return 0;
441}
442
443/*
444 * Tristate the SSP DAI lines
445 */
446static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
447 int tristate)
448{
449 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 450 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 451 u32 sscr1;
452
453 sscr1 = ssp_read_reg(ssp, SSCR1);
454 if (tristate)
455 sscr1 &= ~SSCR1_TTE;
456 else
457 sscr1 |= SSCR1_TTE;
458 ssp_write_reg(ssp, SSCR1, sscr1);
459
460 return 0;
461}
462
463/*
464 * Set up the SSP DAI format.
465 * The SSP Port must be inactive before calling this function as the
466 * physical interface format is changed.
467 */
468static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
469 unsigned int fmt)
470{
471 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 472 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 473 u32 sscr0;
474 u32 sscr1;
475 u32 sspsp;
476
cbf1146d
DM		 477 /* check if we need to change anything at all */
478 if (priv->dai_fmt == fmt)
479 return 0;
480
481 /* we can only change the settings if the port is not in use */
482 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
483 dev_err(&ssp->pdev->dev,
484 "can't change hardware dai format: stream is in use");
485 return -EINVAL;
486 }
487
1b340bd7
MB		 488 /* reset port settings */
489 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 490 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 491 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
492 sspsp = 0;
493
494 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
495 case SND_SOC_DAIFMT_CBM_CFM:
496 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
497 break;
498 case SND_SOC_DAIFMT_CBM_CFS:
499 sscr1 |= SSCR1_SCLKDIR;
500 break;
501 case SND_SOC_DAIFMT_CBS_CFS:
502 break;
503 default:
504 return -EINVAL;
505 }
506
fa44c077
DR		 507 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
508 case SND_SOC_DAIFMT_NB_NF:
509 sspsp |= SSPSP_SFRMP;
510 break;
511 case SND_SOC_DAIFMT_NB_IF:
512 break;
513 case SND_SOC_DAIFMT_IB_IF:
514 sspsp |= SSPSP_SCMODE(2);
515 break;
516 case SND_SOC_DAIFMT_IB_NF:
517 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
518 break;
519 default:
520 return -EINVAL;
521 }
1b340bd7
MB		 522
523 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
524 case SND_SOC_DAIFMT_I2S:
72d74664 525 sscr0 |= SSCR0_PSP;
1b340bd7 526 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0ce36c5f 527 /* See hw_params() */
1b340bd7
MB		 528 break;
529
530 case SND_SOC_DAIFMT_DSP_A:
531 sspsp |= SSPSP_FSRT;
532 case SND_SOC_DAIFMT_DSP_B:
533 sscr0 |= SSCR0_MOD | SSCR0_PSP;
534 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
1b340bd7
MB		 535 break;
536
537 default:
538 return -EINVAL;
539 }
540
541 ssp_write_reg(ssp, SSCR0, sscr0);
542 ssp_write_reg(ssp, SSCR1, sscr1);
543 ssp_write_reg(ssp, SSPSP, sspsp);
544
545 dump_registers(ssp);
546
547 /* Since we are configuring the timings for the format by hand
548 * we have to defer some things until hw_params() where we
549 * know parameters like the sample size.
550 */
551 priv->dai_fmt = fmt;
552
553 return 0;
554}
555
556/*
557 * Set the SSP audio DMA parameters and sample size.
558 * Can be called multiple times by oss emulation.
559 */
560static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 561 struct snd_pcm_hw_params *params,
562 struct snd_soc_dai *dai)
1b340bd7
MB		 563{
564 struct snd_soc_pcm_runtime *rtd = substream->private_data;
565 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
566 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 567 struct ssp_device *ssp = priv->ssp;
2d7e71fa 568 int chn = params_channels(params);
1b340bd7
MB		 569 u32 sscr0;
570 u32 sspsp;
571 int width = snd_pcm_format_physical_width(params_format(params));
92429069 572 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
1b340bd7 573
2d7e71fa
EM		 574 /* generate correct DMA params */
575 if (cpu_dai->dma_data)
576 kfree(cpu_dai->dma_data);
577
92429069
PZ		 578 /* Network mode with one active slot (ttsa == 1) can be used
579 * to force 16-bit frame width on the wire (for S16_LE), even
580 * with two channels. Use 16-bit DMA transfers for this case.
581 */
2d7e71fa
EM		 582 cpu_dai->dma_data = ssp_get_dma_params(ssp,
583 ((chn == 2) && (ttsa != 1)) || (width == 32),
584 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1b340bd7
MB		 585
586 /* we can only change the settings if the port is not in use */
587 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
588 return 0;
589
590 /* clear selected SSP bits */
591 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
592 ssp_write_reg(ssp, SSCR0, sscr0);
593
594 /* bit size */
595 sscr0 = ssp_read_reg(ssp, SSCR0);
596 switch (params_format(params)) {
597 case SNDRV_PCM_FORMAT_S16_LE:
598#ifdef CONFIG_PXA3xx
599 if (cpu_is_pxa3xx())
600 sscr0 |= SSCR0_FPCKE;
601#endif
602 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 603 break;
604 case SNDRV_PCM_FORMAT_S24_LE:
605 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 606 break;
607 case SNDRV_PCM_FORMAT_S32_LE:
608 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 609 break;
610 }
611 ssp_write_reg(ssp, SSCR0, sscr0);
612
613 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
614 case SND_SOC_DAIFMT_I2S:
72d74664
DM		 615 sspsp = ssp_read_reg(ssp, SSPSP);
616
1a297286 617 if ((ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 618 /* This is a special case where the bitclk is 64fs
619 * and we're not dealing with 2*32 bits of audio
620 * samples.
621 *
622 * The SSP values used for that are all found out by
623 * trying and failing a lot; some of the registers
624 * needed for that mode are only available on PXA3xx.
625 */
626
627#ifdef CONFIG_PXA3xx
628 if (!cpu_is_pxa3xx())
629 return -EINVAL;
630
631 sspsp |= SSPSP_SFRMWDTH(width * 2);
632 sspsp |= SSPSP_SFRMDLY(width * 4);
633 sspsp |= SSPSP_EDMYSTOP(3);
634 sspsp |= SSPSP_DMYSTOP(3);
635 sspsp |= SSPSP_DMYSTRT(1);
636#else
637 return -EINVAL;
638#endif
0ce36c5f
MB		 639 } else {
640 /* The frame width is the width the LRCLK is
641 * asserted for; the delay is expressed in
642 * half cycle units. We need the extra cycle
643 * because the data starts clocking out one BCLK
644 * after LRCLK changes polarity.
645 */
646 sspsp |= SSPSP_SFRMWDTH(width + 1);
647 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
648 sspsp |= SSPSP_DMYSTRT(1);
649 }
72d74664 650
1b340bd7
MB		 651 ssp_write_reg(ssp, SSPSP, sspsp);
652 break;
653 default:
654 break;
655 }
656
72d74664 657 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 658 * - complain loudly and fail if they've not been set up yet.
659 */
92429069 660 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 661 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
662 return -EINVAL;
663 }
664
665 dump_registers(ssp);
666
667 return 0;
668}
669
dee89c4d
MB		 670static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
671 struct snd_soc_dai *dai)
1b340bd7
MB		 672{
673 struct snd_soc_pcm_runtime *rtd = substream->private_data;
674 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
675 int ret = 0;
676 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 677 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 678 int val;
679
680 switch (cmd) {
681 case SNDRV_PCM_TRIGGER_RESUME:
f9efc9df 682 ssp_enable(ssp);
1b340bd7
MB		 683 break;
684 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
685 val = ssp_read_reg(ssp, SSCR1);
686 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
687 val |= SSCR1_TSRE;
688 else
689 val |= SSCR1_RSRE;
690 ssp_write_reg(ssp, SSCR1, val);
691 val = ssp_read_reg(ssp, SSSR);
692 ssp_write_reg(ssp, SSSR, val);
693 break;
694 case SNDRV_PCM_TRIGGER_START:
695 val = ssp_read_reg(ssp, SSCR1);
696 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
697 val |= SSCR1_TSRE;
698 else
699 val |= SSCR1_RSRE;
700 ssp_write_reg(ssp, SSCR1, val);
f9efc9df 701 ssp_enable(ssp);
1b340bd7
MB		 702 break;
703 case SNDRV_PCM_TRIGGER_STOP:
704 val = ssp_read_reg(ssp, SSCR1);
705 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
706 val &= ~SSCR1_TSRE;
707 else
708 val &= ~SSCR1_RSRE;
709 ssp_write_reg(ssp, SSCR1, val);
710 break;
711 case SNDRV_PCM_TRIGGER_SUSPEND:
f9efc9df 712 ssp_disable(ssp);
1b340bd7
MB		 713 break;
714 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
715 val = ssp_read_reg(ssp, SSCR1);
716 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
717 val &= ~SSCR1_TSRE;
718 else
719 val &= ~SSCR1_RSRE;
720 ssp_write_reg(ssp, SSCR1, val);
721 break;
722
723 default:
724 ret = -EINVAL;
725 }
726
727 dump_registers(ssp);
728
729 return ret;
730}
731
732static int pxa_ssp_probe(struct platform_device *pdev,
733 struct snd_soc_dai *dai)
734{
735 struct ssp_priv *priv;
736 int ret;
737
738 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
739 if (!priv)
740 return -ENOMEM;
741
f9efc9df
EM		 742 priv->ssp = ssp_request(dai->id + 1, "SoC audio");
743 if (priv->ssp == NULL) {
1b340bd7
MB		 744 ret = -ENODEV;
745 goto err_priv;
746 }
747
a5735b7e 748 priv->dai_fmt = (unsigned int) -1;
1b340bd7
MB		 749 dai->private_data = priv;
750
751 return 0;
752
753err_priv:
754 kfree(priv);
755 return ret;
756}
757
758static void pxa_ssp_remove(struct platform_device *pdev,
759 struct snd_soc_dai *dai)
760{
761 struct ssp_priv *priv = dai->private_data;
f9efc9df 762 ssp_free(priv->ssp);
1b340bd7
MB		 763}
764
765#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
766 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
767 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
768 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
769
770#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
771 SNDRV_PCM_FMTBIT_S24_LE | \
772 SNDRV_PCM_FMTBIT_S32_LE)
773
6335d055
EM		 774static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
775 .startup = pxa_ssp_startup,
776 .shutdown = pxa_ssp_shutdown,
777 .trigger = pxa_ssp_trigger,
778 .hw_params = pxa_ssp_hw_params,
779 .set_sysclk = pxa_ssp_set_dai_sysclk,
780 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
781 .set_pll = pxa_ssp_set_dai_pll,
782 .set_fmt = pxa_ssp_set_dai_fmt,
783 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
784 .set_tristate = pxa_ssp_set_dai_tristate,
785};
786
1b340bd7
MB		 787struct snd_soc_dai pxa_ssp_dai[] = {
788 {
789 .name = "pxa2xx-ssp1",
790 .id = 0,
1b340bd7
MB		 791 .probe = pxa_ssp_probe,
792 .remove = pxa_ssp_remove,
793 .suspend = pxa_ssp_suspend,
794 .resume = pxa_ssp_resume,
795 .playback = {
796 .channels_min = 1,
f34762b6 797 .channels_max = 8,
1b340bd7
MB		 798 .rates = PXA_SSP_RATES,
799 .formats = PXA_SSP_FORMATS,
800 },
801 .capture = {
802 .channels_min = 1,
f34762b6 803 .channels_max = 8,
1b340bd7
MB		 804 .rates = PXA_SSP_RATES,
805 .formats = PXA_SSP_FORMATS,
806 },
6335d055 807 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 808 },
809 { .name = "pxa2xx-ssp2",
810 .id = 1,
1b340bd7
MB		 811 .probe = pxa_ssp_probe,
812 .remove = pxa_ssp_remove,
813 .suspend = pxa_ssp_suspend,
814 .resume = pxa_ssp_resume,
815 .playback = {
816 .channels_min = 1,
f34762b6 817 .channels_max = 8,
1b340bd7
MB		 818 .rates = PXA_SSP_RATES,
819 .formats = PXA_SSP_FORMATS,
820 },
821 .capture = {
822 .channels_min = 1,
f34762b6 823 .channels_max = 8,
1b340bd7
MB		 824 .rates = PXA_SSP_RATES,
825 .formats = PXA_SSP_FORMATS,
826 },
6335d055 827 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 828 },
829 {
830 .name = "pxa2xx-ssp3",
831 .id = 2,
1b340bd7
MB		 832 .probe = pxa_ssp_probe,
833 .remove = pxa_ssp_remove,
834 .suspend = pxa_ssp_suspend,
835 .resume = pxa_ssp_resume,
836 .playback = {
837 .channels_min = 1,
f34762b6 838 .channels_max = 8,
1b340bd7
MB		 839 .rates = PXA_SSP_RATES,
840 .formats = PXA_SSP_FORMATS,
841 },
842 .capture = {
843 .channels_min = 1,
f34762b6 844 .channels_max = 8,
1b340bd7
MB		 845 .rates = PXA_SSP_RATES,
846 .formats = PXA_SSP_FORMATS,
847 },
6335d055 848 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 849 },
850 {
851 .name = "pxa2xx-ssp4",
852 .id = 3,
1b340bd7
MB		 853 .probe = pxa_ssp_probe,
854 .remove = pxa_ssp_remove,
855 .suspend = pxa_ssp_suspend,
856 .resume = pxa_ssp_resume,
857 .playback = {
858 .channels_min = 1,
f34762b6 859 .channels_max = 8,
1b340bd7
MB		 860 .rates = PXA_SSP_RATES,
861 .formats = PXA_SSP_FORMATS,
862 },
863 .capture = {
864 .channels_min = 1,
f34762b6 865 .channels_max = 8,
1b340bd7
MB		 866 .rates = PXA_SSP_RATES,
867 .formats = PXA_SSP_FORMATS,
868 },
6335d055 869 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 870 },
871};
872EXPORT_SYMBOL_GPL(pxa_ssp_dai);
873
c9b3a40f 874static int __init pxa_ssp_init(void)
3f4b783c
MB		 875{
876 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
877}
878module_init(pxa_ssp_init);
879
880static void __exit pxa_ssp_exit(void)
881{
882 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
883}
884module_exit(pxa_ssp_exit);
885
1b340bd7
MB		 886/* Module information */
887MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
888MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
889MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)