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ASoC: Add PXA SSP support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1#define DEBUG
2/*
3 * pxa-ssp.c -- ALSA Soc Audio Layer
4 *
5 * Copyright 2005,2008 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood
7 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * TODO:
15 * o Test network mode for > 16bit sample size
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/initval.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/pxa2xx-lib.h>
30
31#include <mach/hardware.h>
32#include <mach/pxa-regs.h>
33#include <mach/regs-ssp.h>
34#include <mach/audio.h>
35#include <mach/ssp.h>
36
37#include "pxa2xx-pcm.h"
38#include "pxa-ssp.h"
39
40/*
41 * SSP audio private data
42 */
43struct ssp_priv {
44 struct ssp_dev dev;
45 unsigned int sysclk;
46 int dai_fmt;
47#ifdef CONFIG_PM
48 struct ssp_state state;
49#endif
50};
51
52#define PXA2xx_SSP1_BASE 0x41000000
53#define PXA27x_SSP2_BASE 0x41700000
54#define PXA27x_SSP3_BASE 0x41900000
55#define PXA3xx_SSP4_BASE 0x41a00000
56
57static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = {
58 .name = "SSP1 PCM Mono out",
59 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
60 .drcmr = &DRCMR(14),
61 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
62 DCMD_BURST16 | DCMD_WIDTH2,
63};
64
65static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = {
66 .name = "SSP1 PCM Mono in",
67 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
68 .drcmr = &DRCMR(13),
69 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
70 DCMD_BURST16 | DCMD_WIDTH2,
71};
72
73static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = {
74 .name = "SSP1 PCM Stereo out",
75 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
76 .drcmr = &DRCMR(14),
77 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
78 DCMD_BURST16 | DCMD_WIDTH4,
79};
80
81static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = {
82 .name = "SSP1 PCM Stereo in",
83 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
84 .drcmr = &DRCMR(13),
85 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
86 DCMD_BURST16 | DCMD_WIDTH4,
87};
88
89static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = {
90 .name = "SSP2 PCM Mono out",
91 .dev_addr = PXA27x_SSP2_BASE + SSDR,
92 .drcmr = &DRCMR(16),
93 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
94 DCMD_BURST16 | DCMD_WIDTH2,
95};
96
97static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = {
98 .name = "SSP2 PCM Mono in",
99 .dev_addr = PXA27x_SSP2_BASE + SSDR,
100 .drcmr = &DRCMR(15),
101 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
102 DCMD_BURST16 | DCMD_WIDTH2,
103};
104
105static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = {
106 .name = "SSP2 PCM Stereo out",
107 .dev_addr = PXA27x_SSP2_BASE + SSDR,
108 .drcmr = &DRCMR(16),
109 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
110 DCMD_BURST16 | DCMD_WIDTH4,
111};
112
113static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = {
114 .name = "SSP2 PCM Stereo in",
115 .dev_addr = PXA27x_SSP2_BASE + SSDR,
116 .drcmr = &DRCMR(15),
117 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
118 DCMD_BURST16 | DCMD_WIDTH4,
119};
120
121static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = {
122 .name = "SSP3 PCM Mono out",
123 .dev_addr = PXA27x_SSP3_BASE + SSDR,
124 .drcmr = &DRCMR(67),
125 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
126 DCMD_BURST16 | DCMD_WIDTH2,
127};
128
129static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = {
130 .name = "SSP3 PCM Mono in",
131 .dev_addr = PXA27x_SSP3_BASE + SSDR,
132 .drcmr = &DRCMR(66),
133 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
134 DCMD_BURST16 | DCMD_WIDTH2,
135};
136
137static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = {
138 .name = "SSP3 PCM Stereo out",
139 .dev_addr = PXA27x_SSP3_BASE + SSDR,
140 .drcmr = &DRCMR(67),
141 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
142 DCMD_BURST16 | DCMD_WIDTH4,
143};
144
145static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = {
146 .name = "SSP3 PCM Stereo in",
147 .dev_addr = PXA27x_SSP3_BASE + SSDR,
148 .drcmr = &DRCMR(66),
149 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
150 DCMD_BURST16 | DCMD_WIDTH4,
151};
152
153static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = {
154 .name = "SSP4 PCM Mono out",
155 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
156 .drcmr = &DRCMR(67),
157 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
158 DCMD_BURST16 | DCMD_WIDTH2,
159};
160
161static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = {
162 .name = "SSP4 PCM Mono in",
163 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
164 .drcmr = &DRCMR(66),
165 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
166 DCMD_BURST16 | DCMD_WIDTH2,
167};
168
169static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = {
170 .name = "SSP4 PCM Stereo out",
171 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
172 .drcmr = &DRCMR(67),
173 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
174 DCMD_BURST16 | DCMD_WIDTH4,
175};
176
177static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = {
178 .name = "SSP4 PCM Stereo in",
179 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
180 .drcmr = &DRCMR(66),
181 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
182 DCMD_BURST16 | DCMD_WIDTH4,
183};
184
185static void dump_registers(struct ssp_device *ssp)
186{
187 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
188 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
189 ssp_read_reg(ssp, SSTO));
190
191 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
192 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
193 ssp_read_reg(ssp, SSACD));
194}
195
196static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = {
197 {
198 &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in,
199 &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in,
200 },
201 {
202 &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in,
203 &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in,
204 },
205 {
206 &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in,
207 &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in,
208 },
209 {
210 &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in,
211 &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in,
212 },
213};
214
215static int pxa_ssp_startup(struct snd_pcm_substream *substream)
216{
217 struct snd_soc_pcm_runtime *rtd = substream->private_data;
218 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
219 struct ssp_priv *priv = cpu_dai->private_data;
220 int ret = 0;
221
222 if (!cpu_dai->active) {
223 ret = ssp_init(&priv->dev, cpu_dai->id + 1, SSP_NO_IRQ);
224 if (ret < 0)
225 return ret;
226 ssp_disable(&priv->dev);
227 }
228 return ret;
229}
230
231static void pxa_ssp_shutdown(struct snd_pcm_substream *substream)
232{
233 struct snd_soc_pcm_runtime *rtd = substream->private_data;
234 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
235 struct ssp_priv *priv = cpu_dai->private_data;
236
237 if (!cpu_dai->active) {
238 ssp_disable(&priv->dev);
239 ssp_exit(&priv->dev);
240 }
241}
242
243#ifdef CONFIG_PM
244
245static int pxa_ssp_suspend(struct platform_device *pdev,
246 struct snd_soc_dai *cpu_dai)
247{
248 struct ssp_priv *priv = cpu_dai->private_data;
249
250 if (!cpu_dai->active)
251 return 0;
252
253 ssp_save_state(&priv->dev, &priv->state);
254 clk_disable(priv->dev.ssp->clk);
255 return 0;
256}
257
258static int pxa_ssp_resume(struct platform_device *pdev,
259 struct snd_soc_dai *cpu_dai)
260{
261 struct ssp_priv *priv = cpu_dai->private_data;
262
263 if (!cpu_dai->active)
264 return 0;
265
266 clk_enable(priv->dev.ssp->clk);
267 ssp_restore_state(&priv->dev, &priv->state);
268 ssp_enable(&priv->dev);
269
270 return 0;
271}
272
273#else
274#define pxa_ssp_suspend NULL
275#define pxa_ssp_resume NULL
276#endif
277
278/**
279 * ssp_set_clkdiv - set SSP clock divider
280 * @div: serial clock rate divider
281 */
282static void ssp_set_scr(struct ssp_dev *dev, u32 div)
283{
284 struct ssp_device *ssp = dev->ssp;
285 u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR;
286
287 ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div)));
288}
289
290/*
291 * Set the SSP ports SYSCLK.
292 */
293static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
294 int clk_id, unsigned int freq, int dir)
295{
296 struct ssp_priv *priv = cpu_dai->private_data;
297 struct ssp_device *ssp = priv->dev.ssp;
298 int val;
299
300 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
301 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC);
302
303 dev_dbg(&ssp->pdev->dev,
304 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
305 cpu_dai->id, clk_id, freq);
306
307 switch (clk_id) {
308 case PXA_SSP_CLK_NET_PLL:
309 sscr0 |= SSCR0_MOD;
310 break;
311 case PXA_SSP_CLK_PLL:
312 /* Internal PLL is fixed */
313 if (cpu_is_pxa25x())
314 priv->sysclk = 1843200;
315 else
316 priv->sysclk = 13000000;
317 break;
318 case PXA_SSP_CLK_EXT:
319 priv->sysclk = freq;
320 sscr0 |= SSCR0_ECS;
321 break;
322 case PXA_SSP_CLK_NET:
323 priv->sysclk = freq;
324 sscr0 |= SSCR0_NCS | SSCR0_MOD;
325 break;
326 case PXA_SSP_CLK_AUDIO:
327 priv->sysclk = 0;
328 ssp_set_scr(&priv->dev, 1);
329 sscr0 |= SSCR0_ADC;
330 break;
331 default:
332 return -ENODEV;
333 }
334
335 /* The SSP clock must be disabled when changing SSP clock mode
336 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
337 if (!cpu_is_pxa3xx())
338 clk_disable(priv->dev.ssp->clk);
339 val = ssp_read_reg(ssp, SSCR0) | sscr0;
340 ssp_write_reg(ssp, SSCR0, val);
341 if (!cpu_is_pxa3xx())
342 clk_enable(priv->dev.ssp->clk);
343
344 return 0;
345}
346
347/*
348 * Set the SSP clock dividers.
349 */
350static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
351 int div_id, int div)
352{
353 struct ssp_priv *priv = cpu_dai->private_data;
354 struct ssp_device *ssp = priv->dev.ssp;
355 int val;
356
357 switch (div_id) {
358 case PXA_SSP_AUDIO_DIV_ACDS:
359 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
360 ssp_write_reg(ssp, SSACD, val);
361 break;
362 case PXA_SSP_AUDIO_DIV_SCDB:
363 val = ssp_read_reg(ssp, SSACD);
364 val &= ~SSACD_SCDB;
365#if defined(CONFIG_PXA3xx)
366 if (cpu_is_pxa3xx())
367 val &= ~SSACD_SCDX8;
368#endif
369 switch (div) {
370 case PXA_SSP_CLK_SCDB_1:
371 val |= SSACD_SCDB;
372 break;
373 case PXA_SSP_CLK_SCDB_4:
374 break;
375#if defined(CONFIG_PXA3xx)
376 case PXA_SSP_CLK_SCDB_8:
377 if (cpu_is_pxa3xx())
378 val |= SSACD_SCDX8;
379 else
380 return -EINVAL;
381 break;
382#endif
383 default:
384 return -EINVAL;
385 }
386 ssp_write_reg(ssp, SSACD, val);
387 break;
388 case PXA_SSP_DIV_SCR:
389 ssp_set_scr(&priv->dev, div);
390 break;
391 default:
392 return -ENODEV;
393 }
394
395 return 0;
396}
397
398/*
399 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
400 */
401static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
402 int pll_id, unsigned int freq_in, unsigned int freq_out)
403{
404 struct ssp_priv *priv = cpu_dai->private_data;
405 struct ssp_device *ssp = priv->dev.ssp;
406 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
407
408#if defined(CONFIG_PXA3xx)
409 if (cpu_is_pxa3xx())
410 ssp_write_reg(ssp, SSACDD, 0);
411#endif
412
413 switch (freq_out) {
414 case 5622000:
415 break;
416 case 11345000:
417 ssacd |= (0x1 << 4);
418 break;
419 case 12235000:
420 ssacd |= (0x2 << 4);
421 break;
422 case 14857000:
423 ssacd |= (0x3 << 4);
424 break;
425 case 32842000:
426 ssacd |= (0x4 << 4);
427 break;
428 case 48000000:
429 ssacd |= (0x5 << 4);
430 break;
431 case 0:
432 /* Disable */
433 break;
434
435 default:
436#ifdef CONFIG_PXA3xx
437 /* PXA3xx has a clock ditherer which can be used to generate
438 * a wider range of frequencies - calculate a value for it.
439 */
440 if (cpu_is_pxa3xx()) {
441 u32 val;
442 u64 tmp = 19968;
443 tmp *= 1000000;
444 do_div(tmp, freq_out);
445 val = tmp;
446
447 val = (val << 16) | 64;;
448 ssp_write_reg(ssp, SSACDD, val);
449
450 ssacd |= (0x6 << 4);
451
452 dev_dbg(&ssp->pdev->dev,
453 "Using SSACDD %x to supply %dHz\n",
454 val, freq_out);
455 break;
456 }
457#endif
458
459 return -EINVAL;
460 }
461
462 ssp_write_reg(ssp, SSACD, ssacd);
463
464 return 0;
465}
466
467/*
468 * Set the active slots in TDM/Network mode
469 */
470static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
471 unsigned int mask, int slots)
472{
473 struct ssp_priv *priv = cpu_dai->private_data;
474 struct ssp_device *ssp = priv->dev.ssp;
475 u32 sscr0;
476
477 sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
478
479 /* set number of active slots */
480 sscr0 |= SSCR0_SlotsPerFrm(slots);
481 ssp_write_reg(ssp, SSCR0, sscr0);
482
483 /* set active slot mask */
484 ssp_write_reg(ssp, SSTSA, mask);
485 ssp_write_reg(ssp, SSRSA, mask);
486 return 0;
487}
488
489/*
490 * Tristate the SSP DAI lines
491 */
492static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
493 int tristate)
494{
495 struct ssp_priv *priv = cpu_dai->private_data;
496 struct ssp_device *ssp = priv->dev.ssp;
497 u32 sscr1;
498
499 sscr1 = ssp_read_reg(ssp, SSCR1);
500 if (tristate)
501 sscr1 &= ~SSCR1_TTE;
502 else
503 sscr1 |= SSCR1_TTE;
504 ssp_write_reg(ssp, SSCR1, sscr1);
505
506 return 0;
507}
508
509/*
510 * Set up the SSP DAI format.
511 * The SSP Port must be inactive before calling this function as the
512 * physical interface format is changed.
513 */
514static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
515 unsigned int fmt)
516{
517 struct ssp_priv *priv = cpu_dai->private_data;
518 struct ssp_device *ssp = priv->dev.ssp;
519 u32 sscr0;
520 u32 sscr1;
521 u32 sspsp;
522
523 /* reset port settings */
524 sscr0 = ssp_read_reg(ssp, SSCR0) &
525 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC);
526 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
527 sspsp = 0;
528
529 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
530 case SND_SOC_DAIFMT_CBM_CFM:
531 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
532 break;
533 case SND_SOC_DAIFMT_CBM_CFS:
534 sscr1 |= SSCR1_SCLKDIR;
535 break;
536 case SND_SOC_DAIFMT_CBS_CFS:
537 break;
538 default:
539 return -EINVAL;
540 }
541
542 ssp_write_reg(ssp, SSCR0, sscr0);
543 ssp_write_reg(ssp, SSCR1, sscr1);
544 ssp_write_reg(ssp, SSPSP, sspsp);
545
546 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
547 case SND_SOC_DAIFMT_I2S:
548 sscr0 |= SSCR0_MOD | SSCR0_PSP;
549 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
550
551 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
552 case SND_SOC_DAIFMT_NB_NF:
553 sspsp |= SSPSP_FSRT;
554 break;
555 case SND_SOC_DAIFMT_NB_IF:
556 sspsp |= SSPSP_SFRMP | SSPSP_FSRT;
557 break;
558 case SND_SOC_DAIFMT_IB_IF:
559 sspsp |= SSPSP_SFRMP;
560 break;
561 default:
562 return -EINVAL;
563 }
564 break;
565
566 case SND_SOC_DAIFMT_DSP_A:
567 sspsp |= SSPSP_FSRT;
568 case SND_SOC_DAIFMT_DSP_B:
569 sscr0 |= SSCR0_MOD | SSCR0_PSP;
570 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
571
572 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
573 case SND_SOC_DAIFMT_NB_NF:
574 sspsp |= SSPSP_SFRMP;
575 break;
576 case SND_SOC_DAIFMT_IB_IF:
577 break;
578 default:
579 return -EINVAL;
580 }
581 break;
582
583 default:
584 return -EINVAL;
585 }
586
587 ssp_write_reg(ssp, SSCR0, sscr0);
588 ssp_write_reg(ssp, SSCR1, sscr1);
589 ssp_write_reg(ssp, SSPSP, sspsp);
590
591 dump_registers(ssp);
592
593 /* Since we are configuring the timings for the format by hand
594 * we have to defer some things until hw_params() where we
595 * know parameters like the sample size.
596 */
597 priv->dai_fmt = fmt;
598
599 return 0;
600}
601
602/*
603 * Set the SSP audio DMA parameters and sample size.
604 * Can be called multiple times by oss emulation.
605 */
606static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
607 struct snd_pcm_hw_params *params)
608{
609 struct snd_soc_pcm_runtime *rtd = substream->private_data;
610 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
611 struct ssp_priv *priv = cpu_dai->private_data;
612 struct ssp_device *ssp = priv->dev.ssp;
613 int dma = 0, chn = params_channels(params);
614 u32 sscr0;
615 u32 sspsp;
616 int width = snd_pcm_format_physical_width(params_format(params));
617
618 /* select correct DMA params */
619 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
620 dma = 1; /* capture DMA offset is 1,3 */
621 if (chn == 2)
622 dma += 2; /* stereo DMA offset is 2, mono is 0 */
623 cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma];
624
625 dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma);
626
627 /* we can only change the settings if the port is not in use */
628 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
629 return 0;
630
631 /* clear selected SSP bits */
632 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
633 ssp_write_reg(ssp, SSCR0, sscr0);
634
635 /* bit size */
636 sscr0 = ssp_read_reg(ssp, SSCR0);
637 switch (params_format(params)) {
638 case SNDRV_PCM_FORMAT_S16_LE:
639#ifdef CONFIG_PXA3xx
640 if (cpu_is_pxa3xx())
641 sscr0 |= SSCR0_FPCKE;
642#endif
643 sscr0 |= SSCR0_DataSize(16);
644 if (params_channels(params) > 1)
645 sscr0 |= SSCR0_EDSS;
646 break;
647 case SNDRV_PCM_FORMAT_S24_LE:
648 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
649 /* we must be in network mode (2 slots) for 24 bit stereo */
650 break;
651 case SNDRV_PCM_FORMAT_S32_LE:
652 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
653 /* we must be in network mode (2 slots) for 32 bit stereo */
654 break;
655 }
656 ssp_write_reg(ssp, SSCR0, sscr0);
657
658 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
659 case SND_SOC_DAIFMT_I2S:
660 /* Cleared when the DAI format is set */
661 sspsp = ssp_read_reg(ssp, SSPSP) | SSPSP_SFRMWDTH(width);
662 ssp_write_reg(ssp, SSPSP, sspsp);
663 break;
664 default:
665 break;
666 }
667
668 /* We always use a network mode so we always require TDM slots
669 * - complain loudly and fail if they've not been set up yet.
670 */
671 if (!(ssp_read_reg(ssp, SSTSA) & 0xf)) {
672 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
673 return -EINVAL;
674 }
675
676 dump_registers(ssp);
677
678 return 0;
679}
680
681static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd)
682{
683 struct snd_soc_pcm_runtime *rtd = substream->private_data;
684 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
685 int ret = 0;
686 struct ssp_priv *priv = cpu_dai->private_data;
687 struct ssp_device *ssp = priv->dev.ssp;
688 int val;
689
690 switch (cmd) {
691 case SNDRV_PCM_TRIGGER_RESUME:
692 ssp_enable(&priv->dev);
693 break;
694 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
695 val = ssp_read_reg(ssp, SSCR1);
696 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
697 val |= SSCR1_TSRE;
698 else
699 val |= SSCR1_RSRE;
700 ssp_write_reg(ssp, SSCR1, val);
701 val = ssp_read_reg(ssp, SSSR);
702 ssp_write_reg(ssp, SSSR, val);
703 break;
704 case SNDRV_PCM_TRIGGER_START:
705 val = ssp_read_reg(ssp, SSCR1);
706 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
707 val |= SSCR1_TSRE;
708 else
709 val |= SSCR1_RSRE;
710 ssp_write_reg(ssp, SSCR1, val);
711 ssp_enable(&priv->dev);
712 break;
713 case SNDRV_PCM_TRIGGER_STOP:
714 val = ssp_read_reg(ssp, SSCR1);
715 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
716 val &= ~SSCR1_TSRE;
717 else
718 val &= ~SSCR1_RSRE;
719 ssp_write_reg(ssp, SSCR1, val);
720 break;
721 case SNDRV_PCM_TRIGGER_SUSPEND:
722 ssp_disable(&priv->dev);
723 break;
724 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
725 val = ssp_read_reg(ssp, SSCR1);
726 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
727 val &= ~SSCR1_TSRE;
728 else
729 val &= ~SSCR1_RSRE;
730 ssp_write_reg(ssp, SSCR1, val);
731 break;
732
733 default:
734 ret = -EINVAL;
735 }
736
737 dump_registers(ssp);
738
739 return ret;
740}
741
742static int pxa_ssp_probe(struct platform_device *pdev,
743 struct snd_soc_dai *dai)
744{
745 struct ssp_priv *priv;
746 int ret;
747
748 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
749 if (!priv)
750 return -ENOMEM;
751
752 priv->dev.ssp = ssp_request(dai->id, "SoC audio");
753 if (priv->dev.ssp == NULL) {
754 ret = -ENODEV;
755 goto err_priv;
756 }
757
758 dai->private_data = priv;
759
760 return 0;
761
762err_priv:
763 kfree(priv);
764 return ret;
765}
766
767static void pxa_ssp_remove(struct platform_device *pdev,
768 struct snd_soc_dai *dai)
769{
770 struct ssp_priv *priv = dai->private_data;
771 ssp_free(priv->dev.ssp);
772}
773
774#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
775 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
776 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
777 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
778
779#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
780 SNDRV_PCM_FMTBIT_S24_LE | \
781 SNDRV_PCM_FMTBIT_S32_LE)
782
783struct snd_soc_dai pxa_ssp_dai[] = {
784 {
785 .name = "pxa2xx-ssp1",
786 .id = 0,
787 .type = SND_SOC_DAI_PCM,
788 .probe = pxa_ssp_probe,
789 .remove = pxa_ssp_remove,
790 .suspend = pxa_ssp_suspend,
791 .resume = pxa_ssp_resume,
792 .playback = {
793 .channels_min = 1,
794 .channels_max = 2,
795 .rates = PXA_SSP_RATES,
796 .formats = PXA_SSP_FORMATS,
797 },
798 .capture = {
799 .channels_min = 1,
800 .channels_max = 2,
801 .rates = PXA_SSP_RATES,
802 .formats = PXA_SSP_FORMATS,
803 },
804 .ops = {
805 .startup = pxa_ssp_startup,
806 .shutdown = pxa_ssp_shutdown,
807 .trigger = pxa_ssp_trigger,
808 .hw_params = pxa_ssp_hw_params,
809 },
810 .dai_ops = {
811 .set_sysclk = pxa_ssp_set_dai_sysclk,
812 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
813 .set_pll = pxa_ssp_set_dai_pll,
814 .set_fmt = pxa_ssp_set_dai_fmt,
815 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
816 .set_tristate = pxa_ssp_set_dai_tristate,
817 },
818 },
819 { .name = "pxa2xx-ssp2",
820 .id = 1,
821 .type = SND_SOC_DAI_PCM,
822 .probe = pxa_ssp_probe,
823 .remove = pxa_ssp_remove,
824 .suspend = pxa_ssp_suspend,
825 .resume = pxa_ssp_resume,
826 .playback = {
827 .channels_min = 1,
828 .channels_max = 2,
829 .rates = PXA_SSP_RATES,
830 .formats = PXA_SSP_FORMATS,
831 },
832 .capture = {
833 .channels_min = 1,
834 .channels_max = 2,
835 .rates = PXA_SSP_RATES,
836 .formats = PXA_SSP_FORMATS,
837 },
838 .ops = {
839 .startup = pxa_ssp_startup,
840 .shutdown = pxa_ssp_shutdown,
841 .trigger = pxa_ssp_trigger,
842 .hw_params = pxa_ssp_hw_params,
843 },
844 .dai_ops = {
845 .set_sysclk = pxa_ssp_set_dai_sysclk,
846 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
847 .set_pll = pxa_ssp_set_dai_pll,
848 .set_fmt = pxa_ssp_set_dai_fmt,
849 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
850 .set_tristate = pxa_ssp_set_dai_tristate,
851 },
852 },
853 {
854 .name = "pxa2xx-ssp3",
855 .id = 2,
856 .type = SND_SOC_DAI_PCM,
857 .probe = pxa_ssp_probe,
858 .remove = pxa_ssp_remove,
859 .suspend = pxa_ssp_suspend,
860 .resume = pxa_ssp_resume,
861 .playback = {
862 .channels_min = 1,
863 .channels_max = 2,
864 .rates = PXA_SSP_RATES,
865 .formats = PXA_SSP_FORMATS,
866 },
867 .capture = {
868 .channels_min = 1,
869 .channels_max = 2,
870 .rates = PXA_SSP_RATES,
871 .formats = PXA_SSP_FORMATS,
872 },
873 .ops = {
874 .startup = pxa_ssp_startup,
875 .shutdown = pxa_ssp_shutdown,
876 .trigger = pxa_ssp_trigger,
877 .hw_params = pxa_ssp_hw_params,
878 },
879 .dai_ops = {
880 .set_sysclk = pxa_ssp_set_dai_sysclk,
881 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
882 .set_pll = pxa_ssp_set_dai_pll,
883 .set_fmt = pxa_ssp_set_dai_fmt,
884 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
885 .set_tristate = pxa_ssp_set_dai_tristate,
886 },
887 },
888 {
889 .name = "pxa2xx-ssp4",
890 .id = 3,
891 .type = SND_SOC_DAI_PCM,
892 .probe = pxa_ssp_probe,
893 .remove = pxa_ssp_remove,
894 .suspend = pxa_ssp_suspend,
895 .resume = pxa_ssp_resume,
896 .playback = {
897 .channels_min = 1,
898 .channels_max = 2,
899 .rates = PXA_SSP_RATES,
900 .formats = PXA_SSP_FORMATS,
901 },
902 .capture = {
903 .channels_min = 1,
904 .channels_max = 2,
905 .rates = PXA_SSP_RATES,
906 .formats = PXA_SSP_FORMATS,
907 },
908 .ops = {
909 .startup = pxa_ssp_startup,
910 .shutdown = pxa_ssp_shutdown,
911 .trigger = pxa_ssp_trigger,
912 .hw_params = pxa_ssp_hw_params,
913 },
914 .dai_ops = {
915 .set_sysclk = pxa_ssp_set_dai_sysclk,
916 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
917 .set_pll = pxa_ssp_set_dai_pll,
918 .set_fmt = pxa_ssp_set_dai_fmt,
919 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
920 .set_tristate = pxa_ssp_set_dai_tristate,
921 },
922 },
923};
924EXPORT_SYMBOL_GPL(pxa_ssp_dai);
925
926/* Module information */
927MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
928MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
929MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)