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ASoC: OMAP: Fix FS polarity in OSK5912 machine driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
0664678a
PZ		 23#include <asm/irq.h>
24
1b340bd7
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/pxa2xx-lib.h>
31
32#include <mach/hardware.h>
33#include <mach/pxa-regs.h>
34#include <mach/regs-ssp.h>
35#include <mach/audio.h>
36#include <mach/ssp.h>
37
38#include "pxa2xx-pcm.h"
39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
45 struct ssp_dev dev;
46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
49 struct ssp_state state;
50#endif
51};
52
53#define PXA2xx_SSP1_BASE 0x41000000
54#define PXA27x_SSP2_BASE 0x41700000
55#define PXA27x_SSP3_BASE 0x41900000
56#define PXA3xx_SSP4_BASE 0x41a00000
57
58static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = {
59 .name = "SSP1 PCM Mono out",
60 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
61 .drcmr = &DRCMR(14),
62 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
63 DCMD_BURST16 | DCMD_WIDTH2,
64};
65
66static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = {
67 .name = "SSP1 PCM Mono in",
68 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
69 .drcmr = &DRCMR(13),
70 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
71 DCMD_BURST16 | DCMD_WIDTH2,
72};
73
74static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = {
75 .name = "SSP1 PCM Stereo out",
76 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
77 .drcmr = &DRCMR(14),
78 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
79 DCMD_BURST16 | DCMD_WIDTH4,
80};
81
82static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = {
83 .name = "SSP1 PCM Stereo in",
84 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
85 .drcmr = &DRCMR(13),
86 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
87 DCMD_BURST16 | DCMD_WIDTH4,
88};
89
90static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = {
91 .name = "SSP2 PCM Mono out",
92 .dev_addr = PXA27x_SSP2_BASE + SSDR,
93 .drcmr = &DRCMR(16),
94 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
95 DCMD_BURST16 | DCMD_WIDTH2,
96};
97
98static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = {
99 .name = "SSP2 PCM Mono in",
100 .dev_addr = PXA27x_SSP2_BASE + SSDR,
101 .drcmr = &DRCMR(15),
102 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
103 DCMD_BURST16 | DCMD_WIDTH2,
104};
105
106static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = {
107 .name = "SSP2 PCM Stereo out",
108 .dev_addr = PXA27x_SSP2_BASE + SSDR,
109 .drcmr = &DRCMR(16),
110 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
111 DCMD_BURST16 | DCMD_WIDTH4,
112};
113
114static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = {
115 .name = "SSP2 PCM Stereo in",
116 .dev_addr = PXA27x_SSP2_BASE + SSDR,
117 .drcmr = &DRCMR(15),
118 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
119 DCMD_BURST16 | DCMD_WIDTH4,
120};
121
122static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = {
123 .name = "SSP3 PCM Mono out",
124 .dev_addr = PXA27x_SSP3_BASE + SSDR,
125 .drcmr = &DRCMR(67),
126 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
127 DCMD_BURST16 | DCMD_WIDTH2,
128};
129
130static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = {
131 .name = "SSP3 PCM Mono in",
132 .dev_addr = PXA27x_SSP3_BASE + SSDR,
133 .drcmr = &DRCMR(66),
134 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
135 DCMD_BURST16 | DCMD_WIDTH2,
136};
137
138static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = {
139 .name = "SSP3 PCM Stereo out",
140 .dev_addr = PXA27x_SSP3_BASE + SSDR,
141 .drcmr = &DRCMR(67),
142 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
143 DCMD_BURST16 | DCMD_WIDTH4,
144};
145
146static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = {
147 .name = "SSP3 PCM Stereo in",
148 .dev_addr = PXA27x_SSP3_BASE + SSDR,
149 .drcmr = &DRCMR(66),
150 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
151 DCMD_BURST16 | DCMD_WIDTH4,
152};
153
154static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = {
155 .name = "SSP4 PCM Mono out",
156 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
157 .drcmr = &DRCMR(67),
158 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
159 DCMD_BURST16 | DCMD_WIDTH2,
160};
161
162static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = {
163 .name = "SSP4 PCM Mono in",
164 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
165 .drcmr = &DRCMR(66),
166 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
167 DCMD_BURST16 | DCMD_WIDTH2,
168};
169
170static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = {
171 .name = "SSP4 PCM Stereo out",
172 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
173 .drcmr = &DRCMR(67),
174 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
175 DCMD_BURST16 | DCMD_WIDTH4,
176};
177
178static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = {
179 .name = "SSP4 PCM Stereo in",
180 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
181 .drcmr = &DRCMR(66),
182 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
183 DCMD_BURST16 | DCMD_WIDTH4,
184};
185
186static void dump_registers(struct ssp_device *ssp)
187{
188 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
189 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
190 ssp_read_reg(ssp, SSTO));
191
192 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
193 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
194 ssp_read_reg(ssp, SSACD));
195}
196
197static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = {
198 {
199 &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in,
200 &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in,
201 },
202 {
203 &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in,
204 &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in,
205 },
206 {
207 &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in,
208 &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in,
209 },
210 {
211 &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in,
212 &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in,
213 },
214};
215
dee89c4d
MB		 216static int pxa_ssp_startup(struct snd_pcm_substream *substream,
217 struct snd_soc_dai *dai)
1b340bd7
MB		 218{
219 struct snd_soc_pcm_runtime *rtd = substream->private_data;
220 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
221 struct ssp_priv *priv = cpu_dai->private_data;
222 int ret = 0;
223
224 if (!cpu_dai->active) {
0664678a
PZ		 225 priv->dev.port = cpu_dai->id + 1;
226 priv->dev.irq = NO_IRQ;
227 clk_enable(priv->dev.ssp->clk);
1b340bd7
MB		 228 ssp_disable(&priv->dev);
229 }
230 return ret;
231}
232
dee89c4d
MB		 233static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
234 struct snd_soc_dai *dai)
1b340bd7
MB		 235{
236 struct snd_soc_pcm_runtime *rtd = substream->private_data;
237 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
238 struct ssp_priv *priv = cpu_dai->private_data;
239
240 if (!cpu_dai->active) {
241 ssp_disable(&priv->dev);
0664678a 242 clk_disable(priv->dev.ssp->clk);
1b340bd7
MB		 243 }
244}
245
246#ifdef CONFIG_PM
247
dc7d7b83 248static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 249{
250 struct ssp_priv *priv = cpu_dai->private_data;
251
252 if (!cpu_dai->active)
253 return 0;
254
255 ssp_save_state(&priv->dev, &priv->state);
256 clk_disable(priv->dev.ssp->clk);
257 return 0;
258}
259
dc7d7b83 260static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 261{
262 struct ssp_priv *priv = cpu_dai->private_data;
263
264 if (!cpu_dai->active)
265 return 0;
266
267 clk_enable(priv->dev.ssp->clk);
268 ssp_restore_state(&priv->dev, &priv->state);
269 ssp_enable(&priv->dev);
270
271 return 0;
272}
273
274#else
275#define pxa_ssp_suspend NULL
276#define pxa_ssp_resume NULL
277#endif
278
279/**
280 * ssp_set_clkdiv - set SSP clock divider
281 * @div: serial clock rate divider
282 */
283static void ssp_set_scr(struct ssp_dev *dev, u32 div)
284{
285 struct ssp_device *ssp = dev->ssp;
286 u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR;
287
288 ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div)));
289}
290
291/*
292 * Set the SSP ports SYSCLK.
293 */
294static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
295 int clk_id, unsigned int freq, int dir)
296{
297 struct ssp_priv *priv = cpu_dai->private_data;
298 struct ssp_device *ssp = priv->dev.ssp;
299 int val;
300
301 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 302 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 303
304 dev_dbg(&ssp->pdev->dev,
305 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
306 cpu_dai->id, clk_id, freq);
307
308 switch (clk_id) {
309 case PXA_SSP_CLK_NET_PLL:
310 sscr0 |= SSCR0_MOD;
311 break;
312 case PXA_SSP_CLK_PLL:
313 /* Internal PLL is fixed */
314 if (cpu_is_pxa25x())
315 priv->sysclk = 1843200;
316 else
317 priv->sysclk = 13000000;
318 break;
319 case PXA_SSP_CLK_EXT:
320 priv->sysclk = freq;
321 sscr0 |= SSCR0_ECS;
322 break;
323 case PXA_SSP_CLK_NET:
324 priv->sysclk = freq;
325 sscr0 |= SSCR0_NCS | SSCR0_MOD;
326 break;
327 case PXA_SSP_CLK_AUDIO:
328 priv->sysclk = 0;
329 ssp_set_scr(&priv->dev, 1);
20a41eac 330 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 331 break;
332 default:
333 return -ENODEV;
334 }
335
336 /* The SSP clock must be disabled when changing SSP clock mode
337 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
338 if (!cpu_is_pxa3xx())
339 clk_disable(priv->dev.ssp->clk);
340 val = ssp_read_reg(ssp, SSCR0) | sscr0;
341 ssp_write_reg(ssp, SSCR0, val);
342 if (!cpu_is_pxa3xx())
343 clk_enable(priv->dev.ssp->clk);
344
345 return 0;
346}
347
348/*
349 * Set the SSP clock dividers.
350 */
351static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
352 int div_id, int div)
353{
354 struct ssp_priv *priv = cpu_dai->private_data;
355 struct ssp_device *ssp = priv->dev.ssp;
356 int val;
357
358 switch (div_id) {
359 case PXA_SSP_AUDIO_DIV_ACDS:
360 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
361 ssp_write_reg(ssp, SSACD, val);
362 break;
363 case PXA_SSP_AUDIO_DIV_SCDB:
364 val = ssp_read_reg(ssp, SSACD);
365 val &= ~SSACD_SCDB;
366#if defined(CONFIG_PXA3xx)
367 if (cpu_is_pxa3xx())
368 val &= ~SSACD_SCDX8;
369#endif
370 switch (div) {
371 case PXA_SSP_CLK_SCDB_1:
372 val |= SSACD_SCDB;
373 break;
374 case PXA_SSP_CLK_SCDB_4:
375 break;
376#if defined(CONFIG_PXA3xx)
377 case PXA_SSP_CLK_SCDB_8:
378 if (cpu_is_pxa3xx())
379 val |= SSACD_SCDX8;
380 else
381 return -EINVAL;
382 break;
383#endif
384 default:
385 return -EINVAL;
386 }
387 ssp_write_reg(ssp, SSACD, val);
388 break;
389 case PXA_SSP_DIV_SCR:
390 ssp_set_scr(&priv->dev, div);
391 break;
392 default:
393 return -ENODEV;
394 }
395
396 return 0;
397}
398
399/*
400 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
401 */
402static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
403 int pll_id, unsigned int freq_in, unsigned int freq_out)
404{
405 struct ssp_priv *priv = cpu_dai->private_data;
406 struct ssp_device *ssp = priv->dev.ssp;
407 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
408
409#if defined(CONFIG_PXA3xx)
410 if (cpu_is_pxa3xx())
411 ssp_write_reg(ssp, SSACDD, 0);
412#endif
413
414 switch (freq_out) {
415 case 5622000:
416 break;
417 case 11345000:
418 ssacd |= (0x1 << 4);
419 break;
420 case 12235000:
421 ssacd |= (0x2 << 4);
422 break;
423 case 14857000:
424 ssacd |= (0x3 << 4);
425 break;
426 case 32842000:
427 ssacd |= (0x4 << 4);
428 break;
429 case 48000000:
430 ssacd |= (0x5 << 4);
431 break;
432 case 0:
433 /* Disable */
434 break;
435
436 default:
437#ifdef CONFIG_PXA3xx
438 /* PXA3xx has a clock ditherer which can be used to generate
439 * a wider range of frequencies - calculate a value for it.
440 */
441 if (cpu_is_pxa3xx()) {
442 u32 val;
443 u64 tmp = 19968;
444 tmp *= 1000000;
445 do_div(tmp, freq_out);
446 val = tmp;
447
448 val = (val << 16) | 64;;
449 ssp_write_reg(ssp, SSACDD, val);
450
451 ssacd |= (0x6 << 4);
452
453 dev_dbg(&ssp->pdev->dev,
454 "Using SSACDD %x to supply %dHz\n",
455 val, freq_out);
456 break;
457 }
458#endif
459
460 return -EINVAL;
461 }
462
463 ssp_write_reg(ssp, SSACD, ssacd);
464
465 return 0;
466}
467
468/*
469 * Set the active slots in TDM/Network mode
470 */
471static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
472 unsigned int mask, int slots)
473{
474 struct ssp_priv *priv = cpu_dai->private_data;
475 struct ssp_device *ssp = priv->dev.ssp;
476 u32 sscr0;
477
478 sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
479
480 /* set number of active slots */
481 sscr0 |= SSCR0_SlotsPerFrm(slots);
482 ssp_write_reg(ssp, SSCR0, sscr0);
483
484 /* set active slot mask */
485 ssp_write_reg(ssp, SSTSA, mask);
486 ssp_write_reg(ssp, SSRSA, mask);
487 return 0;
488}
489
490/*
491 * Tristate the SSP DAI lines
492 */
493static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
494 int tristate)
495{
496 struct ssp_priv *priv = cpu_dai->private_data;
497 struct ssp_device *ssp = priv->dev.ssp;
498 u32 sscr1;
499
500 sscr1 = ssp_read_reg(ssp, SSCR1);
501 if (tristate)
502 sscr1 &= ~SSCR1_TTE;
503 else
504 sscr1 |= SSCR1_TTE;
505 ssp_write_reg(ssp, SSCR1, sscr1);
506
507 return 0;
508}
509
510/*
511 * Set up the SSP DAI format.
512 * The SSP Port must be inactive before calling this function as the
513 * physical interface format is changed.
514 */
515static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
516 unsigned int fmt)
517{
518 struct ssp_priv *priv = cpu_dai->private_data;
519 struct ssp_device *ssp = priv->dev.ssp;
520 u32 sscr0;
521 u32 sscr1;
522 u32 sspsp;
523
cbf1146d
DM		 524 /* check if we need to change anything at all */
525 if (priv->dai_fmt == fmt)
526 return 0;
527
528 /* we can only change the settings if the port is not in use */
529 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
530 dev_err(&ssp->pdev->dev,
531 "can't change hardware dai format: stream is in use");
532 return -EINVAL;
533 }
534
1b340bd7
MB		 535 /* reset port settings */
536 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 537 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 538 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
539 sspsp = 0;
540
541 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
542 case SND_SOC_DAIFMT_CBM_CFM:
543 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
544 break;
545 case SND_SOC_DAIFMT_CBM_CFS:
546 sscr1 |= SSCR1_SCLKDIR;
547 break;
548 case SND_SOC_DAIFMT_CBS_CFS:
549 break;
550 default:
551 return -EINVAL;
552 }
553
554 ssp_write_reg(ssp, SSCR0, sscr0);
555 ssp_write_reg(ssp, SSCR1, sscr1);
556 ssp_write_reg(ssp, SSPSP, sspsp);
557
558 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
559 case SND_SOC_DAIFMT_I2S:
72d74664 560 sscr0 |= SSCR0_PSP;
1b340bd7
MB		 561 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
562
0ce36c5f 563 /* See hw_params() */
1b340bd7
MB		 564 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
565 case SND_SOC_DAIFMT_NB_NF:
0ce36c5f 566 sspsp |= SSPSP_SFRMP;
1b340bd7
MB		 567 break;
568 case SND_SOC_DAIFMT_NB_IF:
1b340bd7
MB		 569 break;
570 case SND_SOC_DAIFMT_IB_IF:
0ce36c5f 571 sspsp |= SSPSP_SCMODE(3);
1b340bd7
MB		 572 break;
573 default:
574 return -EINVAL;
575 }
576 break;
577
578 case SND_SOC_DAIFMT_DSP_A:
579 sspsp |= SSPSP_FSRT;
580 case SND_SOC_DAIFMT_DSP_B:
581 sscr0 |= SSCR0_MOD | SSCR0_PSP;
582 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
583
584 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
585 case SND_SOC_DAIFMT_NB_NF:
586 sspsp |= SSPSP_SFRMP;
587 break;
588 case SND_SOC_DAIFMT_IB_IF:
589 break;
590 default:
591 return -EINVAL;
592 }
593 break;
594
595 default:
596 return -EINVAL;
597 }
598
599 ssp_write_reg(ssp, SSCR0, sscr0);
600 ssp_write_reg(ssp, SSCR1, sscr1);
601 ssp_write_reg(ssp, SSPSP, sspsp);
602
603 dump_registers(ssp);
604
605 /* Since we are configuring the timings for the format by hand
606 * we have to defer some things until hw_params() where we
607 * know parameters like the sample size.
608 */
609 priv->dai_fmt = fmt;
610
611 return 0;
612}
613
614/*
615 * Set the SSP audio DMA parameters and sample size.
616 * Can be called multiple times by oss emulation.
617 */
618static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 619 struct snd_pcm_hw_params *params,
620 struct snd_soc_dai *dai)
1b340bd7
MB		 621{
622 struct snd_soc_pcm_runtime *rtd = substream->private_data;
623 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
624 struct ssp_priv *priv = cpu_dai->private_data;
625 struct ssp_device *ssp = priv->dev.ssp;
626 int dma = 0, chn = params_channels(params);
627 u32 sscr0;
628 u32 sspsp;
629 int width = snd_pcm_format_physical_width(params_format(params));
92429069 630 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
1b340bd7
MB		 631
632 /* select correct DMA params */
633 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
634 dma = 1; /* capture DMA offset is 1,3 */
92429069
PZ		 635 /* Network mode with one active slot (ttsa == 1) can be used
636 * to force 16-bit frame width on the wire (for S16_LE), even
637 * with two channels. Use 16-bit DMA transfers for this case.
638 */
639 if (((chn == 2) && (ttsa != 1)) || (width == 32))
640 dma += 2; /* 32-bit DMA offset is 2, 16-bit is 0 */
641
1b340bd7
MB		 642 cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma];
643
644 dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma);
645
646 /* we can only change the settings if the port is not in use */
647 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
648 return 0;
649
650 /* clear selected SSP bits */
651 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
652 ssp_write_reg(ssp, SSCR0, sscr0);
653
654 /* bit size */
655 sscr0 = ssp_read_reg(ssp, SSCR0);
656 switch (params_format(params)) {
657 case SNDRV_PCM_FORMAT_S16_LE:
658#ifdef CONFIG_PXA3xx
659 if (cpu_is_pxa3xx())
660 sscr0 |= SSCR0_FPCKE;
661#endif
662 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 663 break;
664 case SNDRV_PCM_FORMAT_S24_LE:
665 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 666 break;
667 case SNDRV_PCM_FORMAT_S32_LE:
668 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 669 break;
670 }
671 ssp_write_reg(ssp, SSCR0, sscr0);
672
673 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
674 case SND_SOC_DAIFMT_I2S:
72d74664
DM		 675 sspsp = ssp_read_reg(ssp, SSPSP);
676
677 if (((sscr0 & SSCR0_SCR) == SSCR0_SerClkDiv(4)) &&
678 (width == 16)) {
679 /* This is a special case where the bitclk is 64fs
680 * and we're not dealing with 2*32 bits of audio
681 * samples.
682 *
683 * The SSP values used for that are all found out by
684 * trying and failing a lot; some of the registers
685 * needed for that mode are only available on PXA3xx.
686 */
687
688#ifdef CONFIG_PXA3xx
689 if (!cpu_is_pxa3xx())
690 return -EINVAL;
691
692 sspsp |= SSPSP_SFRMWDTH(width * 2);
693 sspsp |= SSPSP_SFRMDLY(width * 4);
694 sspsp |= SSPSP_EDMYSTOP(3);
695 sspsp |= SSPSP_DMYSTOP(3);
696 sspsp |= SSPSP_DMYSTRT(1);
697#else
698 return -EINVAL;
699#endif
0ce36c5f
MB		 700 } else {
701 /* The frame width is the width the LRCLK is
702 * asserted for; the delay is expressed in
703 * half cycle units. We need the extra cycle
704 * because the data starts clocking out one BCLK
705 * after LRCLK changes polarity.
706 */
707 sspsp |= SSPSP_SFRMWDTH(width + 1);
708 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
709 sspsp |= SSPSP_DMYSTRT(1);
710 }
72d74664 711
1b340bd7
MB		 712 ssp_write_reg(ssp, SSPSP, sspsp);
713 break;
714 default:
715 break;
716 }
717
72d74664 718 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 719 * - complain loudly and fail if they've not been set up yet.
720 */
92429069 721 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 722 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
723 return -EINVAL;
724 }
725
726 dump_registers(ssp);
727
728 return 0;
729}
730
dee89c4d
MB		 731static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
732 struct snd_soc_dai *dai)
1b340bd7
MB		 733{
734 struct snd_soc_pcm_runtime *rtd = substream->private_data;
735 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
736 int ret = 0;
737 struct ssp_priv *priv = cpu_dai->private_data;
738 struct ssp_device *ssp = priv->dev.ssp;
739 int val;
740
741 switch (cmd) {
742 case SNDRV_PCM_TRIGGER_RESUME:
743 ssp_enable(&priv->dev);
744 break;
745 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
746 val = ssp_read_reg(ssp, SSCR1);
747 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
748 val |= SSCR1_TSRE;
749 else
750 val |= SSCR1_RSRE;
751 ssp_write_reg(ssp, SSCR1, val);
752 val = ssp_read_reg(ssp, SSSR);
753 ssp_write_reg(ssp, SSSR, val);
754 break;
755 case SNDRV_PCM_TRIGGER_START:
756 val = ssp_read_reg(ssp, SSCR1);
757 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
758 val |= SSCR1_TSRE;
759 else
760 val |= SSCR1_RSRE;
761 ssp_write_reg(ssp, SSCR1, val);
762 ssp_enable(&priv->dev);
763 break;
764 case SNDRV_PCM_TRIGGER_STOP:
765 val = ssp_read_reg(ssp, SSCR1);
766 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
767 val &= ~SSCR1_TSRE;
768 else
769 val &= ~SSCR1_RSRE;
770 ssp_write_reg(ssp, SSCR1, val);
771 break;
772 case SNDRV_PCM_TRIGGER_SUSPEND:
773 ssp_disable(&priv->dev);
774 break;
775 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
776 val = ssp_read_reg(ssp, SSCR1);
777 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
778 val &= ~SSCR1_TSRE;
779 else
780 val &= ~SSCR1_RSRE;
781 ssp_write_reg(ssp, SSCR1, val);
782 break;
783
784 default:
785 ret = -EINVAL;
786 }
787
788 dump_registers(ssp);
789
790 return ret;
791}
792
793static int pxa_ssp_probe(struct platform_device *pdev,
794 struct snd_soc_dai *dai)
795{
796 struct ssp_priv *priv;
797 int ret;
798
799 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
800 if (!priv)
801 return -ENOMEM;
802
0664678a 803 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
1b340bd7
MB		 804 if (priv->dev.ssp == NULL) {
805 ret = -ENODEV;
806 goto err_priv;
807 }
808
a5735b7e 809 priv->dai_fmt = (unsigned int) -1;
1b340bd7
MB		 810 dai->private_data = priv;
811
812 return 0;
813
814err_priv:
815 kfree(priv);
816 return ret;
817}
818
819static void pxa_ssp_remove(struct platform_device *pdev,
820 struct snd_soc_dai *dai)
821{
822 struct ssp_priv *priv = dai->private_data;
823 ssp_free(priv->dev.ssp);
824}
825
826#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
827 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
828 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
829 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
830
831#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
832 SNDRV_PCM_FMTBIT_S24_LE | \
833 SNDRV_PCM_FMTBIT_S32_LE)
834
6335d055
EM		 835static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
836 .startup = pxa_ssp_startup,
837 .shutdown = pxa_ssp_shutdown,
838 .trigger = pxa_ssp_trigger,
839 .hw_params = pxa_ssp_hw_params,
840 .set_sysclk = pxa_ssp_set_dai_sysclk,
841 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
842 .set_pll = pxa_ssp_set_dai_pll,
843 .set_fmt = pxa_ssp_set_dai_fmt,
844 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
845 .set_tristate = pxa_ssp_set_dai_tristate,
846};
847
1b340bd7
MB		 848struct snd_soc_dai pxa_ssp_dai[] = {
849 {
850 .name = "pxa2xx-ssp1",
851 .id = 0,
1b340bd7
MB		 852 .probe = pxa_ssp_probe,
853 .remove = pxa_ssp_remove,
854 .suspend = pxa_ssp_suspend,
855 .resume = pxa_ssp_resume,
856 .playback = {
857 .channels_min = 1,
858 .channels_max = 2,
859 .rates = PXA_SSP_RATES,
860 .formats = PXA_SSP_FORMATS,
861 },
862 .capture = {
863 .channels_min = 1,
864 .channels_max = 2,
865 .rates = PXA_SSP_RATES,
866 .formats = PXA_SSP_FORMATS,
867 },
6335d055 868 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 869 },
870 { .name = "pxa2xx-ssp2",
871 .id = 1,
1b340bd7
MB		 872 .probe = pxa_ssp_probe,
873 .remove = pxa_ssp_remove,
874 .suspend = pxa_ssp_suspend,
875 .resume = pxa_ssp_resume,
876 .playback = {
877 .channels_min = 1,
878 .channels_max = 2,
879 .rates = PXA_SSP_RATES,
880 .formats = PXA_SSP_FORMATS,
881 },
882 .capture = {
883 .channels_min = 1,
884 .channels_max = 2,
885 .rates = PXA_SSP_RATES,
886 .formats = PXA_SSP_FORMATS,
887 },
6335d055 888 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 889 },
890 {
891 .name = "pxa2xx-ssp3",
892 .id = 2,
1b340bd7
MB		 893 .probe = pxa_ssp_probe,
894 .remove = pxa_ssp_remove,
895 .suspend = pxa_ssp_suspend,
896 .resume = pxa_ssp_resume,
897 .playback = {
898 .channels_min = 1,
899 .channels_max = 2,
900 .rates = PXA_SSP_RATES,
901 .formats = PXA_SSP_FORMATS,
902 },
903 .capture = {
904 .channels_min = 1,
905 .channels_max = 2,
906 .rates = PXA_SSP_RATES,
907 .formats = PXA_SSP_FORMATS,
908 },
6335d055 909 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 910 },
911 {
912 .name = "pxa2xx-ssp4",
913 .id = 3,
1b340bd7
MB		 914 .probe = pxa_ssp_probe,
915 .remove = pxa_ssp_remove,
916 .suspend = pxa_ssp_suspend,
917 .resume = pxa_ssp_resume,
918 .playback = {
919 .channels_min = 1,
920 .channels_max = 2,
921 .rates = PXA_SSP_RATES,
922 .formats = PXA_SSP_FORMATS,
923 },
924 .capture = {
925 .channels_min = 1,
926 .channels_max = 2,
927 .rates = PXA_SSP_RATES,
928 .formats = PXA_SSP_FORMATS,
929 },
6335d055 930 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 931 },
932};
933EXPORT_SYMBOL_GPL(pxa_ssp_dai);
934
c9b3a40f 935static int __init pxa_ssp_init(void)
3f4b783c
MB		 936{
937 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
938}
939module_init(pxa_ssp_init);
940
941static void __exit pxa_ssp_exit(void)
942{
943 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
944}
945module_exit(pxa_ssp_exit);
946
1b340bd7
MB		 947/* Module information */
948MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
949MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
950MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)