projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: fix typo and removed unneeded switch case for cs4270
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1#define DEBUG
2/*
3 * pxa-ssp.c -- ALSA Soc Audio Layer
4 *
5 * Copyright 2005,2008 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood
7 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * TODO:
15 * o Test network mode for > 16bit sample size
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23
0664678a
PZ		 24#include <asm/irq.h>
25
1b340bd7
MB		 26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/initval.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/pxa2xx-lib.h>
32
33#include <mach/hardware.h>
34#include <mach/pxa-regs.h>
35#include <mach/regs-ssp.h>
36#include <mach/audio.h>
37#include <mach/ssp.h>
38
39#include "pxa2xx-pcm.h"
40#include "pxa-ssp.h"
41
42/*
43 * SSP audio private data
44 */
45struct ssp_priv {
46 struct ssp_dev dev;
47 unsigned int sysclk;
48 int dai_fmt;
49#ifdef CONFIG_PM
50 struct ssp_state state;
51#endif
52};
53
54#define PXA2xx_SSP1_BASE 0x41000000
55#define PXA27x_SSP2_BASE 0x41700000
56#define PXA27x_SSP3_BASE 0x41900000
57#define PXA3xx_SSP4_BASE 0x41a00000
58
59static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = {
60 .name = "SSP1 PCM Mono out",
61 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
62 .drcmr = &DRCMR(14),
63 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
64 DCMD_BURST16 | DCMD_WIDTH2,
65};
66
67static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = {
68 .name = "SSP1 PCM Mono in",
69 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
70 .drcmr = &DRCMR(13),
71 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
72 DCMD_BURST16 | DCMD_WIDTH2,
73};
74
75static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = {
76 .name = "SSP1 PCM Stereo out",
77 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
78 .drcmr = &DRCMR(14),
79 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
80 DCMD_BURST16 | DCMD_WIDTH4,
81};
82
83static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = {
84 .name = "SSP1 PCM Stereo in",
85 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
86 .drcmr = &DRCMR(13),
87 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
88 DCMD_BURST16 | DCMD_WIDTH4,
89};
90
91static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = {
92 .name = "SSP2 PCM Mono out",
93 .dev_addr = PXA27x_SSP2_BASE + SSDR,
94 .drcmr = &DRCMR(16),
95 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
96 DCMD_BURST16 | DCMD_WIDTH2,
97};
98
99static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = {
100 .name = "SSP2 PCM Mono in",
101 .dev_addr = PXA27x_SSP2_BASE + SSDR,
102 .drcmr = &DRCMR(15),
103 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
104 DCMD_BURST16 | DCMD_WIDTH2,
105};
106
107static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = {
108 .name = "SSP2 PCM Stereo out",
109 .dev_addr = PXA27x_SSP2_BASE + SSDR,
110 .drcmr = &DRCMR(16),
111 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
112 DCMD_BURST16 | DCMD_WIDTH4,
113};
114
115static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = {
116 .name = "SSP2 PCM Stereo in",
117 .dev_addr = PXA27x_SSP2_BASE + SSDR,
118 .drcmr = &DRCMR(15),
119 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
120 DCMD_BURST16 | DCMD_WIDTH4,
121};
122
123static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = {
124 .name = "SSP3 PCM Mono out",
125 .dev_addr = PXA27x_SSP3_BASE + SSDR,
126 .drcmr = &DRCMR(67),
127 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
128 DCMD_BURST16 | DCMD_WIDTH2,
129};
130
131static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = {
132 .name = "SSP3 PCM Mono in",
133 .dev_addr = PXA27x_SSP3_BASE + SSDR,
134 .drcmr = &DRCMR(66),
135 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
136 DCMD_BURST16 | DCMD_WIDTH2,
137};
138
139static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = {
140 .name = "SSP3 PCM Stereo out",
141 .dev_addr = PXA27x_SSP3_BASE + SSDR,
142 .drcmr = &DRCMR(67),
143 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
144 DCMD_BURST16 | DCMD_WIDTH4,
145};
146
147static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = {
148 .name = "SSP3 PCM Stereo in",
149 .dev_addr = PXA27x_SSP3_BASE + SSDR,
150 .drcmr = &DRCMR(66),
151 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
152 DCMD_BURST16 | DCMD_WIDTH4,
153};
154
155static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = {
156 .name = "SSP4 PCM Mono out",
157 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
158 .drcmr = &DRCMR(67),
159 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
160 DCMD_BURST16 | DCMD_WIDTH2,
161};
162
163static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = {
164 .name = "SSP4 PCM Mono in",
165 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
166 .drcmr = &DRCMR(66),
167 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
168 DCMD_BURST16 | DCMD_WIDTH2,
169};
170
171static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = {
172 .name = "SSP4 PCM Stereo out",
173 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
174 .drcmr = &DRCMR(67),
175 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
176 DCMD_BURST16 | DCMD_WIDTH4,
177};
178
179static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = {
180 .name = "SSP4 PCM Stereo in",
181 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
182 .drcmr = &DRCMR(66),
183 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
184 DCMD_BURST16 | DCMD_WIDTH4,
185};
186
187static void dump_registers(struct ssp_device *ssp)
188{
189 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
190 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
191 ssp_read_reg(ssp, SSTO));
192
193 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
194 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
195 ssp_read_reg(ssp, SSACD));
196}
197
198static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = {
199 {
200 &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in,
201 &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in,
202 },
203 {
204 &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in,
205 &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in,
206 },
207 {
208 &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in,
209 &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in,
210 },
211 {
212 &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in,
213 &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in,
214 },
215};
216
dee89c4d
MB		 217static int pxa_ssp_startup(struct snd_pcm_substream *substream,
218 struct snd_soc_dai *dai)
1b340bd7
MB		 219{
220 struct snd_soc_pcm_runtime *rtd = substream->private_data;
221 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
222 struct ssp_priv *priv = cpu_dai->private_data;
223 int ret = 0;
224
225 if (!cpu_dai->active) {
0664678a
PZ		 226 priv->dev.port = cpu_dai->id + 1;
227 priv->dev.irq = NO_IRQ;
228 clk_enable(priv->dev.ssp->clk);
1b340bd7
MB		 229 ssp_disable(&priv->dev);
230 }
231 return ret;
232}
233
dee89c4d
MB		 234static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
235 struct snd_soc_dai *dai)
1b340bd7
MB		 236{
237 struct snd_soc_pcm_runtime *rtd = substream->private_data;
238 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
239 struct ssp_priv *priv = cpu_dai->private_data;
240
241 if (!cpu_dai->active) {
242 ssp_disable(&priv->dev);
0664678a 243 clk_disable(priv->dev.ssp->clk);
1b340bd7
MB		 244 }
245}
246
247#ifdef CONFIG_PM
248
dc7d7b83 249static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 250{
251 struct ssp_priv *priv = cpu_dai->private_data;
252
253 if (!cpu_dai->active)
254 return 0;
255
256 ssp_save_state(&priv->dev, &priv->state);
257 clk_disable(priv->dev.ssp->clk);
258 return 0;
259}
260
dc7d7b83 261static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 262{
263 struct ssp_priv *priv = cpu_dai->private_data;
264
265 if (!cpu_dai->active)
266 return 0;
267
268 clk_enable(priv->dev.ssp->clk);
269 ssp_restore_state(&priv->dev, &priv->state);
270 ssp_enable(&priv->dev);
271
272 return 0;
273}
274
275#else
276#define pxa_ssp_suspend NULL
277#define pxa_ssp_resume NULL
278#endif
279
280/**
281 * ssp_set_clkdiv - set SSP clock divider
282 * @div: serial clock rate divider
283 */
284static void ssp_set_scr(struct ssp_dev *dev, u32 div)
285{
286 struct ssp_device *ssp = dev->ssp;
287 u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR;
288
289 ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div)));
290}
291
292/*
293 * Set the SSP ports SYSCLK.
294 */
295static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
296 int clk_id, unsigned int freq, int dir)
297{
298 struct ssp_priv *priv = cpu_dai->private_data;
299 struct ssp_device *ssp = priv->dev.ssp;
300 int val;
301
302 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
303 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC);
304
305 dev_dbg(&ssp->pdev->dev,
306 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
307 cpu_dai->id, clk_id, freq);
308
309 switch (clk_id) {
310 case PXA_SSP_CLK_NET_PLL:
311 sscr0 |= SSCR0_MOD;
312 break;
313 case PXA_SSP_CLK_PLL:
314 /* Internal PLL is fixed */
315 if (cpu_is_pxa25x())
316 priv->sysclk = 1843200;
317 else
318 priv->sysclk = 13000000;
319 break;
320 case PXA_SSP_CLK_EXT:
321 priv->sysclk = freq;
322 sscr0 |= SSCR0_ECS;
323 break;
324 case PXA_SSP_CLK_NET:
325 priv->sysclk = freq;
326 sscr0 |= SSCR0_NCS | SSCR0_MOD;
327 break;
328 case PXA_SSP_CLK_AUDIO:
329 priv->sysclk = 0;
330 ssp_set_scr(&priv->dev, 1);
331 sscr0 |= SSCR0_ADC;
332 break;
333 default:
334 return -ENODEV;
335 }
336
337 /* The SSP clock must be disabled when changing SSP clock mode
338 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
339 if (!cpu_is_pxa3xx())
340 clk_disable(priv->dev.ssp->clk);
341 val = ssp_read_reg(ssp, SSCR0) | sscr0;
342 ssp_write_reg(ssp, SSCR0, val);
343 if (!cpu_is_pxa3xx())
344 clk_enable(priv->dev.ssp->clk);
345
346 return 0;
347}
348
349/*
350 * Set the SSP clock dividers.
351 */
352static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
353 int div_id, int div)
354{
355 struct ssp_priv *priv = cpu_dai->private_data;
356 struct ssp_device *ssp = priv->dev.ssp;
357 int val;
358
359 switch (div_id) {
360 case PXA_SSP_AUDIO_DIV_ACDS:
361 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
362 ssp_write_reg(ssp, SSACD, val);
363 break;
364 case PXA_SSP_AUDIO_DIV_SCDB:
365 val = ssp_read_reg(ssp, SSACD);
366 val &= ~SSACD_SCDB;
367#if defined(CONFIG_PXA3xx)
368 if (cpu_is_pxa3xx())
369 val &= ~SSACD_SCDX8;
370#endif
371 switch (div) {
372 case PXA_SSP_CLK_SCDB_1:
373 val |= SSACD_SCDB;
374 break;
375 case PXA_SSP_CLK_SCDB_4:
376 break;
377#if defined(CONFIG_PXA3xx)
378 case PXA_SSP_CLK_SCDB_8:
379 if (cpu_is_pxa3xx())
380 val |= SSACD_SCDX8;
381 else
382 return -EINVAL;
383 break;
384#endif
385 default:
386 return -EINVAL;
387 }
388 ssp_write_reg(ssp, SSACD, val);
389 break;
390 case PXA_SSP_DIV_SCR:
391 ssp_set_scr(&priv->dev, div);
392 break;
393 default:
394 return -ENODEV;
395 }
396
397 return 0;
398}
399
400/*
401 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
402 */
403static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
404 int pll_id, unsigned int freq_in, unsigned int freq_out)
405{
406 struct ssp_priv *priv = cpu_dai->private_data;
407 struct ssp_device *ssp = priv->dev.ssp;
408 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
409
410#if defined(CONFIG_PXA3xx)
411 if (cpu_is_pxa3xx())
412 ssp_write_reg(ssp, SSACDD, 0);
413#endif
414
415 switch (freq_out) {
416 case 5622000:
417 break;
418 case 11345000:
419 ssacd |= (0x1 << 4);
420 break;
421 case 12235000:
422 ssacd |= (0x2 << 4);
423 break;
424 case 14857000:
425 ssacd |= (0x3 << 4);
426 break;
427 case 32842000:
428 ssacd |= (0x4 << 4);
429 break;
430 case 48000000:
431 ssacd |= (0x5 << 4);
432 break;
433 case 0:
434 /* Disable */
435 break;
436
437 default:
438#ifdef CONFIG_PXA3xx
439 /* PXA3xx has a clock ditherer which can be used to generate
440 * a wider range of frequencies - calculate a value for it.
441 */
442 if (cpu_is_pxa3xx()) {
443 u32 val;
444 u64 tmp = 19968;
445 tmp *= 1000000;
446 do_div(tmp, freq_out);
447 val = tmp;
448
449 val = (val << 16) | 64;;
450 ssp_write_reg(ssp, SSACDD, val);
451
452 ssacd |= (0x6 << 4);
453
454 dev_dbg(&ssp->pdev->dev,
455 "Using SSACDD %x to supply %dHz\n",
456 val, freq_out);
457 break;
458 }
459#endif
460
461 return -EINVAL;
462 }
463
464 ssp_write_reg(ssp, SSACD, ssacd);
465
466 return 0;
467}
468
469/*
470 * Set the active slots in TDM/Network mode
471 */
472static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
473 unsigned int mask, int slots)
474{
475 struct ssp_priv *priv = cpu_dai->private_data;
476 struct ssp_device *ssp = priv->dev.ssp;
477 u32 sscr0;
478
479 sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
480
481 /* set number of active slots */
482 sscr0 |= SSCR0_SlotsPerFrm(slots);
483 ssp_write_reg(ssp, SSCR0, sscr0);
484
485 /* set active slot mask */
486 ssp_write_reg(ssp, SSTSA, mask);
487 ssp_write_reg(ssp, SSRSA, mask);
488 return 0;
489}
490
491/*
492 * Tristate the SSP DAI lines
493 */
494static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
495 int tristate)
496{
497 struct ssp_priv *priv = cpu_dai->private_data;
498 struct ssp_device *ssp = priv->dev.ssp;
499 u32 sscr1;
500
501 sscr1 = ssp_read_reg(ssp, SSCR1);
502 if (tristate)
503 sscr1 &= ~SSCR1_TTE;
504 else
505 sscr1 |= SSCR1_TTE;
506 ssp_write_reg(ssp, SSCR1, sscr1);
507
508 return 0;
509}
510
511/*
512 * Set up the SSP DAI format.
513 * The SSP Port must be inactive before calling this function as the
514 * physical interface format is changed.
515 */
516static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
517 unsigned int fmt)
518{
519 struct ssp_priv *priv = cpu_dai->private_data;
520 struct ssp_device *ssp = priv->dev.ssp;
521 u32 sscr0;
522 u32 sscr1;
523 u32 sspsp;
524
525 /* reset port settings */
526 sscr0 = ssp_read_reg(ssp, SSCR0) &
527 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC);
528 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
529 sspsp = 0;
530
531 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
532 case SND_SOC_DAIFMT_CBM_CFM:
533 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
534 break;
535 case SND_SOC_DAIFMT_CBM_CFS:
536 sscr1 |= SSCR1_SCLKDIR;
537 break;
538 case SND_SOC_DAIFMT_CBS_CFS:
539 break;
540 default:
541 return -EINVAL;
542 }
543
544 ssp_write_reg(ssp, SSCR0, sscr0);
545 ssp_write_reg(ssp, SSCR1, sscr1);
546 ssp_write_reg(ssp, SSPSP, sspsp);
547
548 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
549 case SND_SOC_DAIFMT_I2S:
550 sscr0 |= SSCR0_MOD | SSCR0_PSP;
551 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
552
553 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
554 case SND_SOC_DAIFMT_NB_NF:
555 sspsp |= SSPSP_FSRT;
556 break;
557 case SND_SOC_DAIFMT_NB_IF:
558 sspsp |= SSPSP_SFRMP | SSPSP_FSRT;
559 break;
560 case SND_SOC_DAIFMT_IB_IF:
561 sspsp |= SSPSP_SFRMP;
562 break;
563 default:
564 return -EINVAL;
565 }
566 break;
567
568 case SND_SOC_DAIFMT_DSP_A:
569 sspsp |= SSPSP_FSRT;
570 case SND_SOC_DAIFMT_DSP_B:
571 sscr0 |= SSCR0_MOD | SSCR0_PSP;
572 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
573
574 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
575 case SND_SOC_DAIFMT_NB_NF:
576 sspsp |= SSPSP_SFRMP;
577 break;
578 case SND_SOC_DAIFMT_IB_IF:
579 break;
580 default:
581 return -EINVAL;
582 }
583 break;
584
585 default:
586 return -EINVAL;
587 }
588
589 ssp_write_reg(ssp, SSCR0, sscr0);
590 ssp_write_reg(ssp, SSCR1, sscr1);
591 ssp_write_reg(ssp, SSPSP, sspsp);
592
593 dump_registers(ssp);
594
595 /* Since we are configuring the timings for the format by hand
596 * we have to defer some things until hw_params() where we
597 * know parameters like the sample size.
598 */
599 priv->dai_fmt = fmt;
600
601 return 0;
602}
603
604/*
605 * Set the SSP audio DMA parameters and sample size.
606 * Can be called multiple times by oss emulation.
607 */
608static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 609 struct snd_pcm_hw_params *params,
610 struct snd_soc_dai *dai)
1b340bd7
MB		 611{
612 struct snd_soc_pcm_runtime *rtd = substream->private_data;
613 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
614 struct ssp_priv *priv = cpu_dai->private_data;
615 struct ssp_device *ssp = priv->dev.ssp;
616 int dma = 0, chn = params_channels(params);
617 u32 sscr0;
618 u32 sspsp;
619 int width = snd_pcm_format_physical_width(params_format(params));
620
621 /* select correct DMA params */
622 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
623 dma = 1; /* capture DMA offset is 1,3 */
624 if (chn == 2)
625 dma += 2; /* stereo DMA offset is 2, mono is 0 */
626 cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma];
627
628 dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma);
629
630 /* we can only change the settings if the port is not in use */
631 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
632 return 0;
633
634 /* clear selected SSP bits */
635 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
636 ssp_write_reg(ssp, SSCR0, sscr0);
637
638 /* bit size */
639 sscr0 = ssp_read_reg(ssp, SSCR0);
640 switch (params_format(params)) {
641 case SNDRV_PCM_FORMAT_S16_LE:
642#ifdef CONFIG_PXA3xx
643 if (cpu_is_pxa3xx())
644 sscr0 |= SSCR0_FPCKE;
645#endif
646 sscr0 |= SSCR0_DataSize(16);
647 if (params_channels(params) > 1)
648 sscr0 |= SSCR0_EDSS;
649 break;
650 case SNDRV_PCM_FORMAT_S24_LE:
651 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
652 /* we must be in network mode (2 slots) for 24 bit stereo */
653 break;
654 case SNDRV_PCM_FORMAT_S32_LE:
655 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
656 /* we must be in network mode (2 slots) for 32 bit stereo */
657 break;
658 }
659 ssp_write_reg(ssp, SSCR0, sscr0);
660
661 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
662 case SND_SOC_DAIFMT_I2S:
663 /* Cleared when the DAI format is set */
664 sspsp = ssp_read_reg(ssp, SSPSP) | SSPSP_SFRMWDTH(width);
665 ssp_write_reg(ssp, SSPSP, sspsp);
666 break;
667 default:
668 break;
669 }
670
671 /* We always use a network mode so we always require TDM slots
672 * - complain loudly and fail if they've not been set up yet.
673 */
674 if (!(ssp_read_reg(ssp, SSTSA) & 0xf)) {
675 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
676 return -EINVAL;
677 }
678
679 dump_registers(ssp);
680
681 return 0;
682}
683
dee89c4d
MB		 684static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
685 struct snd_soc_dai *dai)
1b340bd7
MB		 686{
687 struct snd_soc_pcm_runtime *rtd = substream->private_data;
688 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
689 int ret = 0;
690 struct ssp_priv *priv = cpu_dai->private_data;
691 struct ssp_device *ssp = priv->dev.ssp;
692 int val;
693
694 switch (cmd) {
695 case SNDRV_PCM_TRIGGER_RESUME:
696 ssp_enable(&priv->dev);
697 break;
698 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
699 val = ssp_read_reg(ssp, SSCR1);
700 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
701 val |= SSCR1_TSRE;
702 else
703 val |= SSCR1_RSRE;
704 ssp_write_reg(ssp, SSCR1, val);
705 val = ssp_read_reg(ssp, SSSR);
706 ssp_write_reg(ssp, SSSR, val);
707 break;
708 case SNDRV_PCM_TRIGGER_START:
709 val = ssp_read_reg(ssp, SSCR1);
710 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
711 val |= SSCR1_TSRE;
712 else
713 val |= SSCR1_RSRE;
714 ssp_write_reg(ssp, SSCR1, val);
715 ssp_enable(&priv->dev);
716 break;
717 case SNDRV_PCM_TRIGGER_STOP:
718 val = ssp_read_reg(ssp, SSCR1);
719 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
720 val &= ~SSCR1_TSRE;
721 else
722 val &= ~SSCR1_RSRE;
723 ssp_write_reg(ssp, SSCR1, val);
724 break;
725 case SNDRV_PCM_TRIGGER_SUSPEND:
726 ssp_disable(&priv->dev);
727 break;
728 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
729 val = ssp_read_reg(ssp, SSCR1);
730 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
731 val &= ~SSCR1_TSRE;
732 else
733 val &= ~SSCR1_RSRE;
734 ssp_write_reg(ssp, SSCR1, val);
735 break;
736
737 default:
738 ret = -EINVAL;
739 }
740
741 dump_registers(ssp);
742
743 return ret;
744}
745
746static int pxa_ssp_probe(struct platform_device *pdev,
747 struct snd_soc_dai *dai)
748{
749 struct ssp_priv *priv;
750 int ret;
751
752 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
753 if (!priv)
754 return -ENOMEM;
755
0664678a 756 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
1b340bd7
MB		 757 if (priv->dev.ssp == NULL) {
758 ret = -ENODEV;
759 goto err_priv;
760 }
761
762 dai->private_data = priv;
763
764 return 0;
765
766err_priv:
767 kfree(priv);
768 return ret;
769}
770
771static void pxa_ssp_remove(struct platform_device *pdev,
772 struct snd_soc_dai *dai)
773{
774 struct ssp_priv *priv = dai->private_data;
775 ssp_free(priv->dev.ssp);
776}
777
778#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
779 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
780 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
781 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
782
783#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
784 SNDRV_PCM_FMTBIT_S24_LE | \
785 SNDRV_PCM_FMTBIT_S32_LE)
786
787struct snd_soc_dai pxa_ssp_dai[] = {
788 {
789 .name = "pxa2xx-ssp1",
790 .id = 0,
1b340bd7
MB		 791 .probe = pxa_ssp_probe,
792 .remove = pxa_ssp_remove,
793 .suspend = pxa_ssp_suspend,
794 .resume = pxa_ssp_resume,
795 .playback = {
796 .channels_min = 1,
797 .channels_max = 2,
798 .rates = PXA_SSP_RATES,
799 .formats = PXA_SSP_FORMATS,
800 },
801 .capture = {
802 .channels_min = 1,
803 .channels_max = 2,
804 .rates = PXA_SSP_RATES,
805 .formats = PXA_SSP_FORMATS,
806 },
807 .ops = {
808 .startup = pxa_ssp_startup,
809 .shutdown = pxa_ssp_shutdown,
810 .trigger = pxa_ssp_trigger,
811 .hw_params = pxa_ssp_hw_params,
1b340bd7
MB		 812 .set_sysclk = pxa_ssp_set_dai_sysclk,
813 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
814 .set_pll = pxa_ssp_set_dai_pll,
815 .set_fmt = pxa_ssp_set_dai_fmt,
816 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
817 .set_tristate = pxa_ssp_set_dai_tristate,
818 },
819 },
820 { .name = "pxa2xx-ssp2",
821 .id = 1,
1b340bd7
MB		 822 .probe = pxa_ssp_probe,
823 .remove = pxa_ssp_remove,
824 .suspend = pxa_ssp_suspend,
825 .resume = pxa_ssp_resume,
826 .playback = {
827 .channels_min = 1,
828 .channels_max = 2,
829 .rates = PXA_SSP_RATES,
830 .formats = PXA_SSP_FORMATS,
831 },
832 .capture = {
833 .channels_min = 1,
834 .channels_max = 2,
835 .rates = PXA_SSP_RATES,
836 .formats = PXA_SSP_FORMATS,
837 },
838 .ops = {
839 .startup = pxa_ssp_startup,
840 .shutdown = pxa_ssp_shutdown,
841 .trigger = pxa_ssp_trigger,
842 .hw_params = pxa_ssp_hw_params,
1b340bd7
MB		 843 .set_sysclk = pxa_ssp_set_dai_sysclk,
844 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
845 .set_pll = pxa_ssp_set_dai_pll,
846 .set_fmt = pxa_ssp_set_dai_fmt,
847 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
848 .set_tristate = pxa_ssp_set_dai_tristate,
849 },
850 },
851 {
852 .name = "pxa2xx-ssp3",
853 .id = 2,
1b340bd7
MB		 854 .probe = pxa_ssp_probe,
855 .remove = pxa_ssp_remove,
856 .suspend = pxa_ssp_suspend,
857 .resume = pxa_ssp_resume,
858 .playback = {
859 .channels_min = 1,
860 .channels_max = 2,
861 .rates = PXA_SSP_RATES,
862 .formats = PXA_SSP_FORMATS,
863 },
864 .capture = {
865 .channels_min = 1,
866 .channels_max = 2,
867 .rates = PXA_SSP_RATES,
868 .formats = PXA_SSP_FORMATS,
869 },
870 .ops = {
871 .startup = pxa_ssp_startup,
872 .shutdown = pxa_ssp_shutdown,
873 .trigger = pxa_ssp_trigger,
874 .hw_params = pxa_ssp_hw_params,
1b340bd7
MB		 875 .set_sysclk = pxa_ssp_set_dai_sysclk,
876 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
877 .set_pll = pxa_ssp_set_dai_pll,
878 .set_fmt = pxa_ssp_set_dai_fmt,
879 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
880 .set_tristate = pxa_ssp_set_dai_tristate,
881 },
882 },
883 {
884 .name = "pxa2xx-ssp4",
885 .id = 3,
1b340bd7
MB		 886 .probe = pxa_ssp_probe,
887 .remove = pxa_ssp_remove,
888 .suspend = pxa_ssp_suspend,
889 .resume = pxa_ssp_resume,
890 .playback = {
891 .channels_min = 1,
892 .channels_max = 2,
893 .rates = PXA_SSP_RATES,
894 .formats = PXA_SSP_FORMATS,
895 },
896 .capture = {
897 .channels_min = 1,
898 .channels_max = 2,
899 .rates = PXA_SSP_RATES,
900 .formats = PXA_SSP_FORMATS,
901 },
902 .ops = {
903 .startup = pxa_ssp_startup,
904 .shutdown = pxa_ssp_shutdown,
905 .trigger = pxa_ssp_trigger,
906 .hw_params = pxa_ssp_hw_params,
1b340bd7
MB		 907 .set_sysclk = pxa_ssp_set_dai_sysclk,
908 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
909 .set_pll = pxa_ssp_set_dai_pll,
910 .set_fmt = pxa_ssp_set_dai_fmt,
911 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
912 .set_tristate = pxa_ssp_set_dai_tristate,
913 },
914 },
915};
916EXPORT_SYMBOL_GPL(pxa_ssp_dai);
917
c9b3a40f 918static int __init pxa_ssp_init(void)
3f4b783c
MB		 919{
920 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
921}
922module_init(pxa_ssp_init);
923
924static void __exit pxa_ssp_exit(void)
925{
926 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
927}
928module_exit(pxa_ssp_exit);
929
1b340bd7
MB		 930/* Module information */
931MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
932MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
933MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)