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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
0664678a
PZ		 23#include <asm/irq.h>
24
1b340bd7
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/pxa2xx-lib.h>
31
32#include <mach/hardware.h>
7ebc8d56 33#include <mach/dma.h>
1b340bd7
MB		 34#include <mach/regs-ssp.h>
35#include <mach/audio.h>
36#include <mach/ssp.h>
37
38#include "pxa2xx-pcm.h"
39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
f9efc9df 45 struct ssp_device *ssp;
1b340bd7
MB		 46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
f9efc9df
EM		 49 uint32_t cr0;
50 uint32_t cr1;
51 uint32_t to;
52 uint32_t psp;
1b340bd7
MB		 53#endif
54};
55
1b340bd7
MB		 56static void dump_registers(struct ssp_device *ssp)
57{
58 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
59 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
60 ssp_read_reg(ssp, SSTO));
61
62 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
63 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
64 ssp_read_reg(ssp, SSACD));
65}
66
f9efc9df
EM		 67static void ssp_enable(struct ssp_device *ssp)
68{
69 uint32_t sscr0;
70
71 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
72 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
73}
74
75static void ssp_disable(struct ssp_device *ssp)
76{
77 uint32_t sscr0;
78
79 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
80 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
81}
82
2d7e71fa
EM		 83struct pxa2xx_pcm_dma_data {
84 struct pxa2xx_pcm_dma_params params;
85 char name[20];
1b340bd7
MB		 86};
87
2d7e71fa 88static struct pxa2xx_pcm_dma_params *
8eb9feab 89ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
2d7e71fa
EM		 90{
91 struct pxa2xx_pcm_dma_data *dma;
92
93 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
94 if (dma == NULL)
95 return NULL;
96
97 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
8eb9feab 98 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
2d7e71fa
EM		 99
100 dma->params.name = dma->name;
101 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
102 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
103 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
8eb9feab 104 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
2d7e71fa
EM		 105 dma->params.dev_addr = ssp->phys_base + SSDR;
106
107 return &dma->params;
108}
109
dee89c4d
MB		 110static int pxa_ssp_startup(struct snd_pcm_substream *substream,
111 struct snd_soc_dai *dai)
1b340bd7
MB		 112{
113 struct snd_soc_pcm_runtime *rtd = substream->private_data;
114 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
115 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 116 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 117 int ret = 0;
118
119 if (!cpu_dai->active) {
f9efc9df
EM		 120 clk_enable(ssp->clk);
121 ssp_disable(ssp);
1b340bd7 122 }
2d7e71fa
EM		 123
124 if (cpu_dai->dma_data) {
125 kfree(cpu_dai->dma_data);
126 cpu_dai->dma_data = NULL;
127 }
1b340bd7
MB		 128 return ret;
129}
130
dee89c4d
MB		 131static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
132 struct snd_soc_dai *dai)
1b340bd7
MB		 133{
134 struct snd_soc_pcm_runtime *rtd = substream->private_data;
135 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
136 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 137 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 138
139 if (!cpu_dai->active) {
f9efc9df
EM		 140 ssp_disable(ssp);
141 clk_disable(ssp->clk);
1b340bd7 142 }
2d7e71fa
EM		 143
144 if (cpu_dai->dma_data) {
145 kfree(cpu_dai->dma_data);
146 cpu_dai->dma_data = NULL;
147 }
1b340bd7
MB		 148}
149
150#ifdef CONFIG_PM
151
dc7d7b83 152static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 153{
154 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 155 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 156
157 if (!cpu_dai->active)
988addf8 158 clk_enable(ssp->clk);
1b340bd7 159
f9efc9df
EM		 160 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
161 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
162 priv->to = __raw_readl(ssp->mmio_base + SSTO);
163 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
164
165 ssp_disable(ssp);
166 clk_disable(ssp->clk);
1b340bd7
MB		 167 return 0;
168}
169
dc7d7b83 170static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 171{
172 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df
EM		 173 struct ssp_device *ssp = priv->ssp;
174 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
1b340bd7 175
f9efc9df
EM		 176 clk_enable(ssp->clk);
177
178 __raw_writel(sssr, ssp->mmio_base + SSSR);
f9efc9df
EM		 179 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
180 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
181 __raw_writel(priv->to, ssp->mmio_base + SSTO);
182 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
026384d6
DM		 183
184 if (cpu_dai->active)
988addf8 185 ssp_enable(ssp);
026384d6 186 else
988addf8 187 clk_disable(ssp->clk);
1b340bd7
MB		 188
189 return 0;
190}
191
192#else
193#define pxa_ssp_suspend NULL
194#define pxa_ssp_resume NULL
195#endif
196
197/**
198 * ssp_set_clkdiv - set SSP clock divider
199 * @div: serial clock rate divider
200 */
1a297286 201static void ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 202{
1a297286
PZ		 203 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
204
205 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
206 sscr0 &= ~0x0000ff00;
207 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
208 } else {
209 sscr0 &= ~0x000fff00;
210 sscr0 |= (div - 1) << 8; /* 1..4096 */
211 }
212 ssp_write_reg(ssp, SSCR0, sscr0);
213}
214
215/**
216 * ssp_get_clkdiv - get SSP clock divider
217 */
218static u32 ssp_get_scr(struct ssp_device *ssp)
219{
220 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
221 u32 div;
1b340bd7 222
1a297286
PZ		 223 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
224 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
225 else
226 div = ((sscr0 >> 8) & 0xfff) + 1;
227 return div;
1b340bd7
MB		 228}
229
230/*
231 * Set the SSP ports SYSCLK.
232 */
233static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
234 int clk_id, unsigned int freq, int dir)
235{
236 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 237 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 238 int val;
239
240 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 241 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 242
243 dev_dbg(&ssp->pdev->dev,
449bd54d 244 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 245 cpu_dai->id, clk_id, freq);
246
247 switch (clk_id) {
248 case PXA_SSP_CLK_NET_PLL:
249 sscr0 |= SSCR0_MOD;
250 break;
251 case PXA_SSP_CLK_PLL:
252 /* Internal PLL is fixed */
253 if (cpu_is_pxa25x())
254 priv->sysclk = 1843200;
255 else
256 priv->sysclk = 13000000;
257 break;
258 case PXA_SSP_CLK_EXT:
259 priv->sysclk = freq;
260 sscr0 |= SSCR0_ECS;
261 break;
262 case PXA_SSP_CLK_NET:
263 priv->sysclk = freq;
264 sscr0 |= SSCR0_NCS | SSCR0_MOD;
265 break;
266 case PXA_SSP_CLK_AUDIO:
267 priv->sysclk = 0;
1a297286 268 ssp_set_scr(ssp, 1);
20a41eac 269 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 270 break;
271 default:
272 return -ENODEV;
273 }
274
275 /* The SSP clock must be disabled when changing SSP clock mode
276 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
277 if (!cpu_is_pxa3xx())
f9efc9df 278 clk_disable(ssp->clk);
1b340bd7
MB		 279 val = ssp_read_reg(ssp, SSCR0) | sscr0;
280 ssp_write_reg(ssp, SSCR0, val);
281 if (!cpu_is_pxa3xx())
f9efc9df 282 clk_enable(ssp->clk);
1b340bd7
MB		 283
284 return 0;
285}
286
287/*
288 * Set the SSP clock dividers.
289 */
290static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
291 int div_id, int div)
292{
293 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 294 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 295 int val;
296
297 switch (div_id) {
298 case PXA_SSP_AUDIO_DIV_ACDS:
299 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
300 ssp_write_reg(ssp, SSACD, val);
301 break;
302 case PXA_SSP_AUDIO_DIV_SCDB:
303 val = ssp_read_reg(ssp, SSACD);
304 val &= ~SSACD_SCDB;
305#if defined(CONFIG_PXA3xx)
306 if (cpu_is_pxa3xx())
307 val &= ~SSACD_SCDX8;
308#endif
309 switch (div) {
310 case PXA_SSP_CLK_SCDB_1:
311 val |= SSACD_SCDB;
312 break;
313 case PXA_SSP_CLK_SCDB_4:
314 break;
315#if defined(CONFIG_PXA3xx)
316 case PXA_SSP_CLK_SCDB_8:
317 if (cpu_is_pxa3xx())
318 val |= SSACD_SCDX8;
319 else
320 return -EINVAL;
321 break;
322#endif
323 default:
324 return -EINVAL;
325 }
326 ssp_write_reg(ssp, SSACD, val);
327 break;
328 case PXA_SSP_DIV_SCR:
1a297286 329 ssp_set_scr(ssp, div);
1b340bd7
MB		 330 break;
331 default:
332 return -ENODEV;
333 }
334
335 return 0;
336}
337
338/*
339 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
340 */
85488037
MB		 341static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
342 int source, unsigned int freq_in, unsigned int freq_out)
1b340bd7
MB		 343{
344 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 345 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 346 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
347
348#if defined(CONFIG_PXA3xx)
349 if (cpu_is_pxa3xx())
350 ssp_write_reg(ssp, SSACDD, 0);
351#endif
352
353 switch (freq_out) {
354 case 5622000:
355 break;
356 case 11345000:
357 ssacd |= (0x1 << 4);
358 break;
359 case 12235000:
360 ssacd |= (0x2 << 4);
361 break;
362 case 14857000:
363 ssacd |= (0x3 << 4);
364 break;
365 case 32842000:
366 ssacd |= (0x4 << 4);
367 break;
368 case 48000000:
369 ssacd |= (0x5 << 4);
370 break;
371 case 0:
372 /* Disable */
373 break;
374
375 default:
376#ifdef CONFIG_PXA3xx
377 /* PXA3xx has a clock ditherer which can be used to generate
378 * a wider range of frequencies - calculate a value for it.
379 */
380 if (cpu_is_pxa3xx()) {
381 u32 val;
382 u64 tmp = 19968;
383 tmp *= 1000000;
384 do_div(tmp, freq_out);
385 val = tmp;
386
a419aef8 387 val = (val << 16) | 64;
1b340bd7
MB		 388 ssp_write_reg(ssp, SSACDD, val);
389
390 ssacd |= (0x6 << 4);
391
392 dev_dbg(&ssp->pdev->dev,
449bd54d 393 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 394 val, freq_out);
395 break;
396 }
397#endif
398
399 return -EINVAL;
400 }
401
402 ssp_write_reg(ssp, SSACD, ssacd);
403
404 return 0;
405}
406
407/*
408 * Set the active slots in TDM/Network mode
409 */
410static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
a5479e38 411 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1b340bd7
MB		 412{
413 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 414 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 415 u32 sscr0;
416
a5479e38
DR		 417 sscr0 = ssp_read_reg(ssp, SSCR0);
418 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
1b340bd7 419
a5479e38
DR		 420 /* set slot width */
421 if (slot_width > 16)
422 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
423 else
424 sscr0 |= SSCR0_DataSize(slot_width);
425
426 if (slots > 1) {
427 /* enable network mode */
428 sscr0 |= SSCR0_MOD;
429
430 /* set number of active slots */
431 sscr0 |= SSCR0_SlotsPerFrm(slots);
432
433 /* set active slot mask */
434 ssp_write_reg(ssp, SSTSA, tx_mask);
435 ssp_write_reg(ssp, SSRSA, rx_mask);
436 }
1b340bd7
MB		 437 ssp_write_reg(ssp, SSCR0, sscr0);
438
1b340bd7
MB		 439 return 0;
440}
441
442/*
443 * Tristate the SSP DAI lines
444 */
445static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
446 int tristate)
447{
448 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 449 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 450 u32 sscr1;
451
452 sscr1 = ssp_read_reg(ssp, SSCR1);
453 if (tristate)
454 sscr1 &= ~SSCR1_TTE;
455 else
456 sscr1 |= SSCR1_TTE;
457 ssp_write_reg(ssp, SSCR1, sscr1);
458
459 return 0;
460}
461
462/*
463 * Set up the SSP DAI format.
464 * The SSP Port must be inactive before calling this function as the
465 * physical interface format is changed.
466 */
467static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
468 unsigned int fmt)
469{
470 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 471 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 472 u32 sscr0;
473 u32 sscr1;
474 u32 sspsp;
475
cbf1146d
DM		 476 /* check if we need to change anything at all */
477 if (priv->dai_fmt == fmt)
478 return 0;
479
480 /* we can only change the settings if the port is not in use */
481 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
482 dev_err(&ssp->pdev->dev,
483 "can't change hardware dai format: stream is in use");
484 return -EINVAL;
485 }
486
1b340bd7
MB		 487 /* reset port settings */
488 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 489 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 490 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
491 sspsp = 0;
492
493 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
494 case SND_SOC_DAIFMT_CBM_CFM:
495 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
496 break;
497 case SND_SOC_DAIFMT_CBM_CFS:
498 sscr1 |= SSCR1_SCLKDIR;
499 break;
500 case SND_SOC_DAIFMT_CBS_CFS:
501 break;
502 default:
503 return -EINVAL;
504 }
505
fa44c077
DR		 506 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
507 case SND_SOC_DAIFMT_NB_NF:
508 sspsp |= SSPSP_SFRMP;
509 break;
510 case SND_SOC_DAIFMT_NB_IF:
511 break;
512 case SND_SOC_DAIFMT_IB_IF:
513 sspsp |= SSPSP_SCMODE(2);
514 break;
515 case SND_SOC_DAIFMT_IB_NF:
516 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
517 break;
518 default:
519 return -EINVAL;
520 }
1b340bd7
MB		 521
522 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
523 case SND_SOC_DAIFMT_I2S:
72d74664 524 sscr0 |= SSCR0_PSP;
1b340bd7 525 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0ce36c5f 526 /* See hw_params() */
1b340bd7
MB		 527 break;
528
529 case SND_SOC_DAIFMT_DSP_A:
530 sspsp |= SSPSP_FSRT;
531 case SND_SOC_DAIFMT_DSP_B:
532 sscr0 |= SSCR0_MOD | SSCR0_PSP;
533 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
1b340bd7
MB		 534 break;
535
536 default:
537 return -EINVAL;
538 }
539
540 ssp_write_reg(ssp, SSCR0, sscr0);
541 ssp_write_reg(ssp, SSCR1, sscr1);
542 ssp_write_reg(ssp, SSPSP, sspsp);
543
544 dump_registers(ssp);
545
546 /* Since we are configuring the timings for the format by hand
547 * we have to defer some things until hw_params() where we
548 * know parameters like the sample size.
549 */
550 priv->dai_fmt = fmt;
551
552 return 0;
553}
554
555/*
556 * Set the SSP audio DMA parameters and sample size.
557 * Can be called multiple times by oss emulation.
558 */
559static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 560 struct snd_pcm_hw_params *params,
561 struct snd_soc_dai *dai)
1b340bd7
MB		 562{
563 struct snd_soc_pcm_runtime *rtd = substream->private_data;
564 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
565 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 566 struct ssp_device *ssp = priv->ssp;
2d7e71fa 567 int chn = params_channels(params);
1b340bd7
MB		 568 u32 sscr0;
569 u32 sspsp;
570 int width = snd_pcm_format_physical_width(params_format(params));
92429069 571 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
1b340bd7 572
2d7e71fa
EM		 573 /* generate correct DMA params */
574 if (cpu_dai->dma_data)
575 kfree(cpu_dai->dma_data);
576
92429069
PZ		 577 /* Network mode with one active slot (ttsa == 1) can be used
578 * to force 16-bit frame width on the wire (for S16_LE), even
579 * with two channels. Use 16-bit DMA transfers for this case.
580 */
2d7e71fa
EM		 581 cpu_dai->dma_data = ssp_get_dma_params(ssp,
582 ((chn == 2) && (ttsa != 1)) || (width == 32),
583 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1b340bd7
MB		 584
585 /* we can only change the settings if the port is not in use */
586 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
587 return 0;
588
589 /* clear selected SSP bits */
590 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
591 ssp_write_reg(ssp, SSCR0, sscr0);
592
593 /* bit size */
594 sscr0 = ssp_read_reg(ssp, SSCR0);
595 switch (params_format(params)) {
596 case SNDRV_PCM_FORMAT_S16_LE:
597#ifdef CONFIG_PXA3xx
598 if (cpu_is_pxa3xx())
599 sscr0 |= SSCR0_FPCKE;
600#endif
601 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 602 break;
603 case SNDRV_PCM_FORMAT_S24_LE:
604 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 605 break;
606 case SNDRV_PCM_FORMAT_S32_LE:
607 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 608 break;
609 }
610 ssp_write_reg(ssp, SSCR0, sscr0);
611
612 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
613 case SND_SOC_DAIFMT_I2S:
72d74664
DM		 614 sspsp = ssp_read_reg(ssp, SSPSP);
615
1a297286 616 if ((ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 617 /* This is a special case where the bitclk is 64fs
618 * and we're not dealing with 2*32 bits of audio
619 * samples.
620 *
621 * The SSP values used for that are all found out by
622 * trying and failing a lot; some of the registers
623 * needed for that mode are only available on PXA3xx.
624 */
625
626#ifdef CONFIG_PXA3xx
627 if (!cpu_is_pxa3xx())
628 return -EINVAL;
629
630 sspsp |= SSPSP_SFRMWDTH(width * 2);
631 sspsp |= SSPSP_SFRMDLY(width * 4);
632 sspsp |= SSPSP_EDMYSTOP(3);
633 sspsp |= SSPSP_DMYSTOP(3);
634 sspsp |= SSPSP_DMYSTRT(1);
635#else
636 return -EINVAL;
637#endif
0ce36c5f
MB		 638 } else {
639 /* The frame width is the width the LRCLK is
640 * asserted for; the delay is expressed in
641 * half cycle units. We need the extra cycle
642 * because the data starts clocking out one BCLK
643 * after LRCLK changes polarity.
644 */
645 sspsp |= SSPSP_SFRMWDTH(width + 1);
646 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
647 sspsp |= SSPSP_DMYSTRT(1);
648 }
72d74664 649
1b340bd7
MB		 650 ssp_write_reg(ssp, SSPSP, sspsp);
651 break;
652 default:
653 break;
654 }
655
72d74664 656 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 657 * - complain loudly and fail if they've not been set up yet.
658 */
92429069 659 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 660 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
661 return -EINVAL;
662 }
663
664 dump_registers(ssp);
665
666 return 0;
667}
668
dee89c4d
MB		 669static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
670 struct snd_soc_dai *dai)
1b340bd7
MB		 671{
672 struct snd_soc_pcm_runtime *rtd = substream->private_data;
673 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
674 int ret = 0;
675 struct ssp_priv *priv = cpu_dai->private_data;
f9efc9df 676 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 677 int val;
678
679 switch (cmd) {
680 case SNDRV_PCM_TRIGGER_RESUME:
f9efc9df 681 ssp_enable(ssp);
1b340bd7
MB		 682 break;
683 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
684 val = ssp_read_reg(ssp, SSCR1);
685 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
686 val |= SSCR1_TSRE;
687 else
688 val |= SSCR1_RSRE;
689 ssp_write_reg(ssp, SSCR1, val);
690 val = ssp_read_reg(ssp, SSSR);
691 ssp_write_reg(ssp, SSSR, val);
692 break;
693 case SNDRV_PCM_TRIGGER_START:
694 val = ssp_read_reg(ssp, SSCR1);
695 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
696 val |= SSCR1_TSRE;
697 else
698 val |= SSCR1_RSRE;
699 ssp_write_reg(ssp, SSCR1, val);
f9efc9df 700 ssp_enable(ssp);
1b340bd7
MB		 701 break;
702 case SNDRV_PCM_TRIGGER_STOP:
703 val = ssp_read_reg(ssp, SSCR1);
704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
705 val &= ~SSCR1_TSRE;
706 else
707 val &= ~SSCR1_RSRE;
708 ssp_write_reg(ssp, SSCR1, val);
709 break;
710 case SNDRV_PCM_TRIGGER_SUSPEND:
f9efc9df 711 ssp_disable(ssp);
1b340bd7
MB		 712 break;
713 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
714 val = ssp_read_reg(ssp, SSCR1);
715 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
716 val &= ~SSCR1_TSRE;
717 else
718 val &= ~SSCR1_RSRE;
719 ssp_write_reg(ssp, SSCR1, val);
720 break;
721
722 default:
723 ret = -EINVAL;
724 }
725
726 dump_registers(ssp);
727
728 return ret;
729}
730
731static int pxa_ssp_probe(struct platform_device *pdev,
732 struct snd_soc_dai *dai)
733{
734 struct ssp_priv *priv;
735 int ret;
736
737 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
738 if (!priv)
739 return -ENOMEM;
740
f9efc9df
EM		 741 priv->ssp = ssp_request(dai->id + 1, "SoC audio");
742 if (priv->ssp == NULL) {
1b340bd7
MB		 743 ret = -ENODEV;
744 goto err_priv;
745 }
746
a5735b7e 747 priv->dai_fmt = (unsigned int) -1;
1b340bd7
MB		 748 dai->private_data = priv;
749
750 return 0;
751
752err_priv:
753 kfree(priv);
754 return ret;
755}
756
757static void pxa_ssp_remove(struct platform_device *pdev,
758 struct snd_soc_dai *dai)
759{
760 struct ssp_priv *priv = dai->private_data;
f9efc9df 761 ssp_free(priv->ssp);
1b340bd7
MB		 762}
763
764#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
765 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
766 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
767 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
768
769#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
770 SNDRV_PCM_FMTBIT_S24_LE | \
771 SNDRV_PCM_FMTBIT_S32_LE)
772
6335d055
EM		 773static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
774 .startup = pxa_ssp_startup,
775 .shutdown = pxa_ssp_shutdown,
776 .trigger = pxa_ssp_trigger,
777 .hw_params = pxa_ssp_hw_params,
778 .set_sysclk = pxa_ssp_set_dai_sysclk,
779 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
780 .set_pll = pxa_ssp_set_dai_pll,
781 .set_fmt = pxa_ssp_set_dai_fmt,
782 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
783 .set_tristate = pxa_ssp_set_dai_tristate,
784};
785
1b340bd7
MB		 786struct snd_soc_dai pxa_ssp_dai[] = {
787 {
788 .name = "pxa2xx-ssp1",
789 .id = 0,
1b340bd7
MB		 790 .probe = pxa_ssp_probe,
791 .remove = pxa_ssp_remove,
792 .suspend = pxa_ssp_suspend,
793 .resume = pxa_ssp_resume,
794 .playback = {
795 .channels_min = 1,
f34762b6 796 .channels_max = 8,
1b340bd7
MB		 797 .rates = PXA_SSP_RATES,
798 .formats = PXA_SSP_FORMATS,
799 },
800 .capture = {
801 .channels_min = 1,
f34762b6 802 .channels_max = 8,
1b340bd7
MB		 803 .rates = PXA_SSP_RATES,
804 .formats = PXA_SSP_FORMATS,
805 },
6335d055 806 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 807 },
808 { .name = "pxa2xx-ssp2",
809 .id = 1,
1b340bd7
MB		 810 .probe = pxa_ssp_probe,
811 .remove = pxa_ssp_remove,
812 .suspend = pxa_ssp_suspend,
813 .resume = pxa_ssp_resume,
814 .playback = {
815 .channels_min = 1,
f34762b6 816 .channels_max = 8,
1b340bd7
MB		 817 .rates = PXA_SSP_RATES,
818 .formats = PXA_SSP_FORMATS,
819 },
820 .capture = {
821 .channels_min = 1,
f34762b6 822 .channels_max = 8,
1b340bd7
MB		 823 .rates = PXA_SSP_RATES,
824 .formats = PXA_SSP_FORMATS,
825 },
6335d055 826 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 827 },
828 {
829 .name = "pxa2xx-ssp3",
830 .id = 2,
1b340bd7
MB		 831 .probe = pxa_ssp_probe,
832 .remove = pxa_ssp_remove,
833 .suspend = pxa_ssp_suspend,
834 .resume = pxa_ssp_resume,
835 .playback = {
836 .channels_min = 1,
f34762b6 837 .channels_max = 8,
1b340bd7
MB		 838 .rates = PXA_SSP_RATES,
839 .formats = PXA_SSP_FORMATS,
840 },
841 .capture = {
842 .channels_min = 1,
f34762b6 843 .channels_max = 8,
1b340bd7
MB		 844 .rates = PXA_SSP_RATES,
845 .formats = PXA_SSP_FORMATS,
846 },
6335d055 847 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 848 },
849 {
850 .name = "pxa2xx-ssp4",
851 .id = 3,
1b340bd7
MB		 852 .probe = pxa_ssp_probe,
853 .remove = pxa_ssp_remove,
854 .suspend = pxa_ssp_suspend,
855 .resume = pxa_ssp_resume,
856 .playback = {
857 .channels_min = 1,
f34762b6 858 .channels_max = 8,
1b340bd7
MB		 859 .rates = PXA_SSP_RATES,
860 .formats = PXA_SSP_FORMATS,
861 },
862 .capture = {
863 .channels_min = 1,
f34762b6 864 .channels_max = 8,
1b340bd7
MB		 865 .rates = PXA_SSP_RATES,
866 .formats = PXA_SSP_FORMATS,
867 },
6335d055 868 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 869 },
870};
871EXPORT_SYMBOL_GPL(pxa_ssp_dai);
872
c9b3a40f 873static int __init pxa_ssp_init(void)
3f4b783c
MB		 874{
875 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
876}
877module_init(pxa_ssp_init);
878
879static void __exit pxa_ssp_exit(void)
880{
881 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
882}
883module_exit(pxa_ssp_exit);
884
1b340bd7
MB		 885/* Module information */
886MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
887MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
888MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)