Commit | Line | Data |
---|---|---|
1b340bd7 MB |
1 | #define DEBUG |
2 | /* | |
3 | * pxa-ssp.c -- ALSA Soc Audio Layer | |
4 | * | |
5 | * Copyright 2005,2008 Wolfson Microelectronics PLC. | |
6 | * Author: Liam Girdwood | |
7 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * TODO: | |
15 | * o Test network mode for > 16bit sample size | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/io.h> | |
23 | ||
24 | #include <sound/core.h> | |
25 | #include <sound/pcm.h> | |
26 | #include <sound/initval.h> | |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/soc.h> | |
29 | #include <sound/pxa2xx-lib.h> | |
30 | ||
31 | #include <mach/hardware.h> | |
32 | #include <mach/pxa-regs.h> | |
33 | #include <mach/regs-ssp.h> | |
34 | #include <mach/audio.h> | |
35 | #include <mach/ssp.h> | |
36 | ||
37 | #include "pxa2xx-pcm.h" | |
38 | #include "pxa-ssp.h" | |
39 | ||
40 | /* | |
41 | * SSP audio private data | |
42 | */ | |
43 | struct ssp_priv { | |
44 | struct ssp_dev dev; | |
45 | unsigned int sysclk; | |
46 | int dai_fmt; | |
47 | #ifdef CONFIG_PM | |
48 | struct ssp_state state; | |
49 | #endif | |
50 | }; | |
51 | ||
52 | #define PXA2xx_SSP1_BASE 0x41000000 | |
53 | #define PXA27x_SSP2_BASE 0x41700000 | |
54 | #define PXA27x_SSP3_BASE 0x41900000 | |
55 | #define PXA3xx_SSP4_BASE 0x41a00000 | |
56 | ||
57 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = { | |
58 | .name = "SSP1 PCM Mono out", | |
59 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, | |
60 | .drcmr = &DRCMR(14), | |
61 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
62 | DCMD_BURST16 | DCMD_WIDTH2, | |
63 | }; | |
64 | ||
65 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = { | |
66 | .name = "SSP1 PCM Mono in", | |
67 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, | |
68 | .drcmr = &DRCMR(13), | |
69 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
70 | DCMD_BURST16 | DCMD_WIDTH2, | |
71 | }; | |
72 | ||
73 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = { | |
74 | .name = "SSP1 PCM Stereo out", | |
75 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, | |
76 | .drcmr = &DRCMR(14), | |
77 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
78 | DCMD_BURST16 | DCMD_WIDTH4, | |
79 | }; | |
80 | ||
81 | static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = { | |
82 | .name = "SSP1 PCM Stereo in", | |
83 | .dev_addr = PXA2xx_SSP1_BASE + SSDR, | |
84 | .drcmr = &DRCMR(13), | |
85 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
86 | DCMD_BURST16 | DCMD_WIDTH4, | |
87 | }; | |
88 | ||
89 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = { | |
90 | .name = "SSP2 PCM Mono out", | |
91 | .dev_addr = PXA27x_SSP2_BASE + SSDR, | |
92 | .drcmr = &DRCMR(16), | |
93 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
94 | DCMD_BURST16 | DCMD_WIDTH2, | |
95 | }; | |
96 | ||
97 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = { | |
98 | .name = "SSP2 PCM Mono in", | |
99 | .dev_addr = PXA27x_SSP2_BASE + SSDR, | |
100 | .drcmr = &DRCMR(15), | |
101 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
102 | DCMD_BURST16 | DCMD_WIDTH2, | |
103 | }; | |
104 | ||
105 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = { | |
106 | .name = "SSP2 PCM Stereo out", | |
107 | .dev_addr = PXA27x_SSP2_BASE + SSDR, | |
108 | .drcmr = &DRCMR(16), | |
109 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
110 | DCMD_BURST16 | DCMD_WIDTH4, | |
111 | }; | |
112 | ||
113 | static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = { | |
114 | .name = "SSP2 PCM Stereo in", | |
115 | .dev_addr = PXA27x_SSP2_BASE + SSDR, | |
116 | .drcmr = &DRCMR(15), | |
117 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
118 | DCMD_BURST16 | DCMD_WIDTH4, | |
119 | }; | |
120 | ||
121 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = { | |
122 | .name = "SSP3 PCM Mono out", | |
123 | .dev_addr = PXA27x_SSP3_BASE + SSDR, | |
124 | .drcmr = &DRCMR(67), | |
125 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
126 | DCMD_BURST16 | DCMD_WIDTH2, | |
127 | }; | |
128 | ||
129 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = { | |
130 | .name = "SSP3 PCM Mono in", | |
131 | .dev_addr = PXA27x_SSP3_BASE + SSDR, | |
132 | .drcmr = &DRCMR(66), | |
133 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
134 | DCMD_BURST16 | DCMD_WIDTH2, | |
135 | }; | |
136 | ||
137 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = { | |
138 | .name = "SSP3 PCM Stereo out", | |
139 | .dev_addr = PXA27x_SSP3_BASE + SSDR, | |
140 | .drcmr = &DRCMR(67), | |
141 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
142 | DCMD_BURST16 | DCMD_WIDTH4, | |
143 | }; | |
144 | ||
145 | static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = { | |
146 | .name = "SSP3 PCM Stereo in", | |
147 | .dev_addr = PXA27x_SSP3_BASE + SSDR, | |
148 | .drcmr = &DRCMR(66), | |
149 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
150 | DCMD_BURST16 | DCMD_WIDTH4, | |
151 | }; | |
152 | ||
153 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = { | |
154 | .name = "SSP4 PCM Mono out", | |
155 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, | |
156 | .drcmr = &DRCMR(67), | |
157 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
158 | DCMD_BURST16 | DCMD_WIDTH2, | |
159 | }; | |
160 | ||
161 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = { | |
162 | .name = "SSP4 PCM Mono in", | |
163 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, | |
164 | .drcmr = &DRCMR(66), | |
165 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
166 | DCMD_BURST16 | DCMD_WIDTH2, | |
167 | }; | |
168 | ||
169 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = { | |
170 | .name = "SSP4 PCM Stereo out", | |
171 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, | |
172 | .drcmr = &DRCMR(67), | |
173 | .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | | |
174 | DCMD_BURST16 | DCMD_WIDTH4, | |
175 | }; | |
176 | ||
177 | static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = { | |
178 | .name = "SSP4 PCM Stereo in", | |
179 | .dev_addr = PXA3xx_SSP4_BASE + SSDR, | |
180 | .drcmr = &DRCMR(66), | |
181 | .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | | |
182 | DCMD_BURST16 | DCMD_WIDTH4, | |
183 | }; | |
184 | ||
185 | static void dump_registers(struct ssp_device *ssp) | |
186 | { | |
187 | dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", | |
188 | ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1), | |
189 | ssp_read_reg(ssp, SSTO)); | |
190 | ||
191 | dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", | |
192 | ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR), | |
193 | ssp_read_reg(ssp, SSACD)); | |
194 | } | |
195 | ||
196 | static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = { | |
197 | { | |
198 | &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in, | |
199 | &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in, | |
200 | }, | |
201 | { | |
202 | &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in, | |
203 | &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in, | |
204 | }, | |
205 | { | |
206 | &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in, | |
207 | &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in, | |
208 | }, | |
209 | { | |
210 | &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in, | |
211 | &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in, | |
212 | }, | |
213 | }; | |
214 | ||
dee89c4d MB |
215 | static int pxa_ssp_startup(struct snd_pcm_substream *substream, |
216 | struct snd_soc_dai *dai) | |
1b340bd7 MB |
217 | { |
218 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
219 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
220 | struct ssp_priv *priv = cpu_dai->private_data; | |
221 | int ret = 0; | |
222 | ||
223 | if (!cpu_dai->active) { | |
224 | ret = ssp_init(&priv->dev, cpu_dai->id + 1, SSP_NO_IRQ); | |
225 | if (ret < 0) | |
226 | return ret; | |
227 | ssp_disable(&priv->dev); | |
228 | } | |
229 | return ret; | |
230 | } | |
231 | ||
dee89c4d MB |
232 | static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, |
233 | struct snd_soc_dai *dai) | |
1b340bd7 MB |
234 | { |
235 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
236 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
237 | struct ssp_priv *priv = cpu_dai->private_data; | |
238 | ||
239 | if (!cpu_dai->active) { | |
240 | ssp_disable(&priv->dev); | |
241 | ssp_exit(&priv->dev); | |
242 | } | |
243 | } | |
244 | ||
245 | #ifdef CONFIG_PM | |
246 | ||
dc7d7b83 | 247 | static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) |
1b340bd7 MB |
248 | { |
249 | struct ssp_priv *priv = cpu_dai->private_data; | |
250 | ||
251 | if (!cpu_dai->active) | |
252 | return 0; | |
253 | ||
254 | ssp_save_state(&priv->dev, &priv->state); | |
255 | clk_disable(priv->dev.ssp->clk); | |
256 | return 0; | |
257 | } | |
258 | ||
dc7d7b83 | 259 | static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) |
1b340bd7 MB |
260 | { |
261 | struct ssp_priv *priv = cpu_dai->private_data; | |
262 | ||
263 | if (!cpu_dai->active) | |
264 | return 0; | |
265 | ||
266 | clk_enable(priv->dev.ssp->clk); | |
267 | ssp_restore_state(&priv->dev, &priv->state); | |
268 | ssp_enable(&priv->dev); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | #else | |
274 | #define pxa_ssp_suspend NULL | |
275 | #define pxa_ssp_resume NULL | |
276 | #endif | |
277 | ||
278 | /** | |
279 | * ssp_set_clkdiv - set SSP clock divider | |
280 | * @div: serial clock rate divider | |
281 | */ | |
282 | static void ssp_set_scr(struct ssp_dev *dev, u32 div) | |
283 | { | |
284 | struct ssp_device *ssp = dev->ssp; | |
285 | u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR; | |
286 | ||
287 | ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div))); | |
288 | } | |
289 | ||
290 | /* | |
291 | * Set the SSP ports SYSCLK. | |
292 | */ | |
293 | static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
294 | int clk_id, unsigned int freq, int dir) | |
295 | { | |
296 | struct ssp_priv *priv = cpu_dai->private_data; | |
297 | struct ssp_device *ssp = priv->dev.ssp; | |
298 | int val; | |
299 | ||
300 | u32 sscr0 = ssp_read_reg(ssp, SSCR0) & | |
301 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC); | |
302 | ||
303 | dev_dbg(&ssp->pdev->dev, | |
304 | "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n", | |
305 | cpu_dai->id, clk_id, freq); | |
306 | ||
307 | switch (clk_id) { | |
308 | case PXA_SSP_CLK_NET_PLL: | |
309 | sscr0 |= SSCR0_MOD; | |
310 | break; | |
311 | case PXA_SSP_CLK_PLL: | |
312 | /* Internal PLL is fixed */ | |
313 | if (cpu_is_pxa25x()) | |
314 | priv->sysclk = 1843200; | |
315 | else | |
316 | priv->sysclk = 13000000; | |
317 | break; | |
318 | case PXA_SSP_CLK_EXT: | |
319 | priv->sysclk = freq; | |
320 | sscr0 |= SSCR0_ECS; | |
321 | break; | |
322 | case PXA_SSP_CLK_NET: | |
323 | priv->sysclk = freq; | |
324 | sscr0 |= SSCR0_NCS | SSCR0_MOD; | |
325 | break; | |
326 | case PXA_SSP_CLK_AUDIO: | |
327 | priv->sysclk = 0; | |
328 | ssp_set_scr(&priv->dev, 1); | |
329 | sscr0 |= SSCR0_ADC; | |
330 | break; | |
331 | default: | |
332 | return -ENODEV; | |
333 | } | |
334 | ||
335 | /* The SSP clock must be disabled when changing SSP clock mode | |
336 | * on PXA2xx. On PXA3xx it must be enabled when doing so. */ | |
337 | if (!cpu_is_pxa3xx()) | |
338 | clk_disable(priv->dev.ssp->clk); | |
339 | val = ssp_read_reg(ssp, SSCR0) | sscr0; | |
340 | ssp_write_reg(ssp, SSCR0, val); | |
341 | if (!cpu_is_pxa3xx()) | |
342 | clk_enable(priv->dev.ssp->clk); | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
347 | /* | |
348 | * Set the SSP clock dividers. | |
349 | */ | |
350 | static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |
351 | int div_id, int div) | |
352 | { | |
353 | struct ssp_priv *priv = cpu_dai->private_data; | |
354 | struct ssp_device *ssp = priv->dev.ssp; | |
355 | int val; | |
356 | ||
357 | switch (div_id) { | |
358 | case PXA_SSP_AUDIO_DIV_ACDS: | |
359 | val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); | |
360 | ssp_write_reg(ssp, SSACD, val); | |
361 | break; | |
362 | case PXA_SSP_AUDIO_DIV_SCDB: | |
363 | val = ssp_read_reg(ssp, SSACD); | |
364 | val &= ~SSACD_SCDB; | |
365 | #if defined(CONFIG_PXA3xx) | |
366 | if (cpu_is_pxa3xx()) | |
367 | val &= ~SSACD_SCDX8; | |
368 | #endif | |
369 | switch (div) { | |
370 | case PXA_SSP_CLK_SCDB_1: | |
371 | val |= SSACD_SCDB; | |
372 | break; | |
373 | case PXA_SSP_CLK_SCDB_4: | |
374 | break; | |
375 | #if defined(CONFIG_PXA3xx) | |
376 | case PXA_SSP_CLK_SCDB_8: | |
377 | if (cpu_is_pxa3xx()) | |
378 | val |= SSACD_SCDX8; | |
379 | else | |
380 | return -EINVAL; | |
381 | break; | |
382 | #endif | |
383 | default: | |
384 | return -EINVAL; | |
385 | } | |
386 | ssp_write_reg(ssp, SSACD, val); | |
387 | break; | |
388 | case PXA_SSP_DIV_SCR: | |
389 | ssp_set_scr(&priv->dev, div); | |
390 | break; | |
391 | default: | |
392 | return -ENODEV; | |
393 | } | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
398 | /* | |
399 | * Configure the PLL frequency pxa27x and (afaik - pxa320 only) | |
400 | */ | |
401 | static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, | |
402 | int pll_id, unsigned int freq_in, unsigned int freq_out) | |
403 | { | |
404 | struct ssp_priv *priv = cpu_dai->private_data; | |
405 | struct ssp_device *ssp = priv->dev.ssp; | |
406 | u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70; | |
407 | ||
408 | #if defined(CONFIG_PXA3xx) | |
409 | if (cpu_is_pxa3xx()) | |
410 | ssp_write_reg(ssp, SSACDD, 0); | |
411 | #endif | |
412 | ||
413 | switch (freq_out) { | |
414 | case 5622000: | |
415 | break; | |
416 | case 11345000: | |
417 | ssacd |= (0x1 << 4); | |
418 | break; | |
419 | case 12235000: | |
420 | ssacd |= (0x2 << 4); | |
421 | break; | |
422 | case 14857000: | |
423 | ssacd |= (0x3 << 4); | |
424 | break; | |
425 | case 32842000: | |
426 | ssacd |= (0x4 << 4); | |
427 | break; | |
428 | case 48000000: | |
429 | ssacd |= (0x5 << 4); | |
430 | break; | |
431 | case 0: | |
432 | /* Disable */ | |
433 | break; | |
434 | ||
435 | default: | |
436 | #ifdef CONFIG_PXA3xx | |
437 | /* PXA3xx has a clock ditherer which can be used to generate | |
438 | * a wider range of frequencies - calculate a value for it. | |
439 | */ | |
440 | if (cpu_is_pxa3xx()) { | |
441 | u32 val; | |
442 | u64 tmp = 19968; | |
443 | tmp *= 1000000; | |
444 | do_div(tmp, freq_out); | |
445 | val = tmp; | |
446 | ||
447 | val = (val << 16) | 64;; | |
448 | ssp_write_reg(ssp, SSACDD, val); | |
449 | ||
450 | ssacd |= (0x6 << 4); | |
451 | ||
452 | dev_dbg(&ssp->pdev->dev, | |
453 | "Using SSACDD %x to supply %dHz\n", | |
454 | val, freq_out); | |
455 | break; | |
456 | } | |
457 | #endif | |
458 | ||
459 | return -EINVAL; | |
460 | } | |
461 | ||
462 | ssp_write_reg(ssp, SSACD, ssacd); | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | /* | |
468 | * Set the active slots in TDM/Network mode | |
469 | */ | |
470 | static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, | |
471 | unsigned int mask, int slots) | |
472 | { | |
473 | struct ssp_priv *priv = cpu_dai->private_data; | |
474 | struct ssp_device *ssp = priv->dev.ssp; | |
475 | u32 sscr0; | |
476 | ||
477 | sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7); | |
478 | ||
479 | /* set number of active slots */ | |
480 | sscr0 |= SSCR0_SlotsPerFrm(slots); | |
481 | ssp_write_reg(ssp, SSCR0, sscr0); | |
482 | ||
483 | /* set active slot mask */ | |
484 | ssp_write_reg(ssp, SSTSA, mask); | |
485 | ssp_write_reg(ssp, SSRSA, mask); | |
486 | return 0; | |
487 | } | |
488 | ||
489 | /* | |
490 | * Tristate the SSP DAI lines | |
491 | */ | |
492 | static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, | |
493 | int tristate) | |
494 | { | |
495 | struct ssp_priv *priv = cpu_dai->private_data; | |
496 | struct ssp_device *ssp = priv->dev.ssp; | |
497 | u32 sscr1; | |
498 | ||
499 | sscr1 = ssp_read_reg(ssp, SSCR1); | |
500 | if (tristate) | |
501 | sscr1 &= ~SSCR1_TTE; | |
502 | else | |
503 | sscr1 |= SSCR1_TTE; | |
504 | ssp_write_reg(ssp, SSCR1, sscr1); | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
509 | /* | |
510 | * Set up the SSP DAI format. | |
511 | * The SSP Port must be inactive before calling this function as the | |
512 | * physical interface format is changed. | |
513 | */ | |
514 | static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
515 | unsigned int fmt) | |
516 | { | |
517 | struct ssp_priv *priv = cpu_dai->private_data; | |
518 | struct ssp_device *ssp = priv->dev.ssp; | |
519 | u32 sscr0; | |
520 | u32 sscr1; | |
521 | u32 sspsp; | |
522 | ||
523 | /* reset port settings */ | |
524 | sscr0 = ssp_read_reg(ssp, SSCR0) & | |
525 | (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC); | |
526 | sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); | |
527 | sspsp = 0; | |
528 | ||
529 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
530 | case SND_SOC_DAIFMT_CBM_CFM: | |
531 | sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR; | |
532 | break; | |
533 | case SND_SOC_DAIFMT_CBM_CFS: | |
534 | sscr1 |= SSCR1_SCLKDIR; | |
535 | break; | |
536 | case SND_SOC_DAIFMT_CBS_CFS: | |
537 | break; | |
538 | default: | |
539 | return -EINVAL; | |
540 | } | |
541 | ||
542 | ssp_write_reg(ssp, SSCR0, sscr0); | |
543 | ssp_write_reg(ssp, SSCR1, sscr1); | |
544 | ssp_write_reg(ssp, SSPSP, sspsp); | |
545 | ||
546 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
547 | case SND_SOC_DAIFMT_I2S: | |
548 | sscr0 |= SSCR0_MOD | SSCR0_PSP; | |
549 | sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; | |
550 | ||
551 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
552 | case SND_SOC_DAIFMT_NB_NF: | |
553 | sspsp |= SSPSP_FSRT; | |
554 | break; | |
555 | case SND_SOC_DAIFMT_NB_IF: | |
556 | sspsp |= SSPSP_SFRMP | SSPSP_FSRT; | |
557 | break; | |
558 | case SND_SOC_DAIFMT_IB_IF: | |
559 | sspsp |= SSPSP_SFRMP; | |
560 | break; | |
561 | default: | |
562 | return -EINVAL; | |
563 | } | |
564 | break; | |
565 | ||
566 | case SND_SOC_DAIFMT_DSP_A: | |
567 | sspsp |= SSPSP_FSRT; | |
568 | case SND_SOC_DAIFMT_DSP_B: | |
569 | sscr0 |= SSCR0_MOD | SSCR0_PSP; | |
570 | sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; | |
571 | ||
572 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
573 | case SND_SOC_DAIFMT_NB_NF: | |
574 | sspsp |= SSPSP_SFRMP; | |
575 | break; | |
576 | case SND_SOC_DAIFMT_IB_IF: | |
577 | break; | |
578 | default: | |
579 | return -EINVAL; | |
580 | } | |
581 | break; | |
582 | ||
583 | default: | |
584 | return -EINVAL; | |
585 | } | |
586 | ||
587 | ssp_write_reg(ssp, SSCR0, sscr0); | |
588 | ssp_write_reg(ssp, SSCR1, sscr1); | |
589 | ssp_write_reg(ssp, SSPSP, sspsp); | |
590 | ||
591 | dump_registers(ssp); | |
592 | ||
593 | /* Since we are configuring the timings for the format by hand | |
594 | * we have to defer some things until hw_params() where we | |
595 | * know parameters like the sample size. | |
596 | */ | |
597 | priv->dai_fmt = fmt; | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | /* | |
603 | * Set the SSP audio DMA parameters and sample size. | |
604 | * Can be called multiple times by oss emulation. | |
605 | */ | |
606 | static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
607 | struct snd_pcm_hw_params *params, |
608 | struct snd_soc_dai *dai) | |
1b340bd7 MB |
609 | { |
610 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
611 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
612 | struct ssp_priv *priv = cpu_dai->private_data; | |
613 | struct ssp_device *ssp = priv->dev.ssp; | |
614 | int dma = 0, chn = params_channels(params); | |
615 | u32 sscr0; | |
616 | u32 sspsp; | |
617 | int width = snd_pcm_format_physical_width(params_format(params)); | |
618 | ||
619 | /* select correct DMA params */ | |
620 | if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) | |
621 | dma = 1; /* capture DMA offset is 1,3 */ | |
622 | if (chn == 2) | |
623 | dma += 2; /* stereo DMA offset is 2, mono is 0 */ | |
624 | cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma]; | |
625 | ||
626 | dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma); | |
627 | ||
628 | /* we can only change the settings if the port is not in use */ | |
629 | if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) | |
630 | return 0; | |
631 | ||
632 | /* clear selected SSP bits */ | |
633 | sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); | |
634 | ssp_write_reg(ssp, SSCR0, sscr0); | |
635 | ||
636 | /* bit size */ | |
637 | sscr0 = ssp_read_reg(ssp, SSCR0); | |
638 | switch (params_format(params)) { | |
639 | case SNDRV_PCM_FORMAT_S16_LE: | |
640 | #ifdef CONFIG_PXA3xx | |
641 | if (cpu_is_pxa3xx()) | |
642 | sscr0 |= SSCR0_FPCKE; | |
643 | #endif | |
644 | sscr0 |= SSCR0_DataSize(16); | |
645 | if (params_channels(params) > 1) | |
646 | sscr0 |= SSCR0_EDSS; | |
647 | break; | |
648 | case SNDRV_PCM_FORMAT_S24_LE: | |
649 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); | |
650 | /* we must be in network mode (2 slots) for 24 bit stereo */ | |
651 | break; | |
652 | case SNDRV_PCM_FORMAT_S32_LE: | |
653 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); | |
654 | /* we must be in network mode (2 slots) for 32 bit stereo */ | |
655 | break; | |
656 | } | |
657 | ssp_write_reg(ssp, SSCR0, sscr0); | |
658 | ||
659 | switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
660 | case SND_SOC_DAIFMT_I2S: | |
661 | /* Cleared when the DAI format is set */ | |
662 | sspsp = ssp_read_reg(ssp, SSPSP) | SSPSP_SFRMWDTH(width); | |
663 | ssp_write_reg(ssp, SSPSP, sspsp); | |
664 | break; | |
665 | default: | |
666 | break; | |
667 | } | |
668 | ||
669 | /* We always use a network mode so we always require TDM slots | |
670 | * - complain loudly and fail if they've not been set up yet. | |
671 | */ | |
672 | if (!(ssp_read_reg(ssp, SSTSA) & 0xf)) { | |
673 | dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n"); | |
674 | return -EINVAL; | |
675 | } | |
676 | ||
677 | dump_registers(ssp); | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
dee89c4d MB |
682 | static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, |
683 | struct snd_soc_dai *dai) | |
1b340bd7 MB |
684 | { |
685 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
686 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
687 | int ret = 0; | |
688 | struct ssp_priv *priv = cpu_dai->private_data; | |
689 | struct ssp_device *ssp = priv->dev.ssp; | |
690 | int val; | |
691 | ||
692 | switch (cmd) { | |
693 | case SNDRV_PCM_TRIGGER_RESUME: | |
694 | ssp_enable(&priv->dev); | |
695 | break; | |
696 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
697 | val = ssp_read_reg(ssp, SSCR1); | |
698 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
699 | val |= SSCR1_TSRE; | |
700 | else | |
701 | val |= SSCR1_RSRE; | |
702 | ssp_write_reg(ssp, SSCR1, val); | |
703 | val = ssp_read_reg(ssp, SSSR); | |
704 | ssp_write_reg(ssp, SSSR, val); | |
705 | break; | |
706 | case SNDRV_PCM_TRIGGER_START: | |
707 | val = ssp_read_reg(ssp, SSCR1); | |
708 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
709 | val |= SSCR1_TSRE; | |
710 | else | |
711 | val |= SSCR1_RSRE; | |
712 | ssp_write_reg(ssp, SSCR1, val); | |
713 | ssp_enable(&priv->dev); | |
714 | break; | |
715 | case SNDRV_PCM_TRIGGER_STOP: | |
716 | val = ssp_read_reg(ssp, SSCR1); | |
717 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
718 | val &= ~SSCR1_TSRE; | |
719 | else | |
720 | val &= ~SSCR1_RSRE; | |
721 | ssp_write_reg(ssp, SSCR1, val); | |
722 | break; | |
723 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
724 | ssp_disable(&priv->dev); | |
725 | break; | |
726 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
727 | val = ssp_read_reg(ssp, SSCR1); | |
728 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
729 | val &= ~SSCR1_TSRE; | |
730 | else | |
731 | val &= ~SSCR1_RSRE; | |
732 | ssp_write_reg(ssp, SSCR1, val); | |
733 | break; | |
734 | ||
735 | default: | |
736 | ret = -EINVAL; | |
737 | } | |
738 | ||
739 | dump_registers(ssp); | |
740 | ||
741 | return ret; | |
742 | } | |
743 | ||
744 | static int pxa_ssp_probe(struct platform_device *pdev, | |
745 | struct snd_soc_dai *dai) | |
746 | { | |
747 | struct ssp_priv *priv; | |
748 | int ret; | |
749 | ||
750 | priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); | |
751 | if (!priv) | |
752 | return -ENOMEM; | |
753 | ||
754 | priv->dev.ssp = ssp_request(dai->id, "SoC audio"); | |
755 | if (priv->dev.ssp == NULL) { | |
756 | ret = -ENODEV; | |
757 | goto err_priv; | |
758 | } | |
759 | ||
760 | dai->private_data = priv; | |
761 | ||
762 | return 0; | |
763 | ||
764 | err_priv: | |
765 | kfree(priv); | |
766 | return ret; | |
767 | } | |
768 | ||
769 | static void pxa_ssp_remove(struct platform_device *pdev, | |
770 | struct snd_soc_dai *dai) | |
771 | { | |
772 | struct ssp_priv *priv = dai->private_data; | |
773 | ssp_free(priv->dev.ssp); | |
774 | } | |
775 | ||
776 | #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | |
777 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ | |
778 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ | |
779 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) | |
780 | ||
781 | #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
782 | SNDRV_PCM_FMTBIT_S24_LE | \ | |
783 | SNDRV_PCM_FMTBIT_S32_LE) | |
784 | ||
785 | struct snd_soc_dai pxa_ssp_dai[] = { | |
786 | { | |
787 | .name = "pxa2xx-ssp1", | |
788 | .id = 0, | |
1b340bd7 MB |
789 | .probe = pxa_ssp_probe, |
790 | .remove = pxa_ssp_remove, | |
791 | .suspend = pxa_ssp_suspend, | |
792 | .resume = pxa_ssp_resume, | |
793 | .playback = { | |
794 | .channels_min = 1, | |
795 | .channels_max = 2, | |
796 | .rates = PXA_SSP_RATES, | |
797 | .formats = PXA_SSP_FORMATS, | |
798 | }, | |
799 | .capture = { | |
800 | .channels_min = 1, | |
801 | .channels_max = 2, | |
802 | .rates = PXA_SSP_RATES, | |
803 | .formats = PXA_SSP_FORMATS, | |
804 | }, | |
805 | .ops = { | |
806 | .startup = pxa_ssp_startup, | |
807 | .shutdown = pxa_ssp_shutdown, | |
808 | .trigger = pxa_ssp_trigger, | |
809 | .hw_params = pxa_ssp_hw_params, | |
1b340bd7 MB |
810 | .set_sysclk = pxa_ssp_set_dai_sysclk, |
811 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, | |
812 | .set_pll = pxa_ssp_set_dai_pll, | |
813 | .set_fmt = pxa_ssp_set_dai_fmt, | |
814 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, | |
815 | .set_tristate = pxa_ssp_set_dai_tristate, | |
816 | }, | |
817 | }, | |
818 | { .name = "pxa2xx-ssp2", | |
819 | .id = 1, | |
1b340bd7 MB |
820 | .probe = pxa_ssp_probe, |
821 | .remove = pxa_ssp_remove, | |
822 | .suspend = pxa_ssp_suspend, | |
823 | .resume = pxa_ssp_resume, | |
824 | .playback = { | |
825 | .channels_min = 1, | |
826 | .channels_max = 2, | |
827 | .rates = PXA_SSP_RATES, | |
828 | .formats = PXA_SSP_FORMATS, | |
829 | }, | |
830 | .capture = { | |
831 | .channels_min = 1, | |
832 | .channels_max = 2, | |
833 | .rates = PXA_SSP_RATES, | |
834 | .formats = PXA_SSP_FORMATS, | |
835 | }, | |
836 | .ops = { | |
837 | .startup = pxa_ssp_startup, | |
838 | .shutdown = pxa_ssp_shutdown, | |
839 | .trigger = pxa_ssp_trigger, | |
840 | .hw_params = pxa_ssp_hw_params, | |
1b340bd7 MB |
841 | .set_sysclk = pxa_ssp_set_dai_sysclk, |
842 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, | |
843 | .set_pll = pxa_ssp_set_dai_pll, | |
844 | .set_fmt = pxa_ssp_set_dai_fmt, | |
845 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, | |
846 | .set_tristate = pxa_ssp_set_dai_tristate, | |
847 | }, | |
848 | }, | |
849 | { | |
850 | .name = "pxa2xx-ssp3", | |
851 | .id = 2, | |
1b340bd7 MB |
852 | .probe = pxa_ssp_probe, |
853 | .remove = pxa_ssp_remove, | |
854 | .suspend = pxa_ssp_suspend, | |
855 | .resume = pxa_ssp_resume, | |
856 | .playback = { | |
857 | .channels_min = 1, | |
858 | .channels_max = 2, | |
859 | .rates = PXA_SSP_RATES, | |
860 | .formats = PXA_SSP_FORMATS, | |
861 | }, | |
862 | .capture = { | |
863 | .channels_min = 1, | |
864 | .channels_max = 2, | |
865 | .rates = PXA_SSP_RATES, | |
866 | .formats = PXA_SSP_FORMATS, | |
867 | }, | |
868 | .ops = { | |
869 | .startup = pxa_ssp_startup, | |
870 | .shutdown = pxa_ssp_shutdown, | |
871 | .trigger = pxa_ssp_trigger, | |
872 | .hw_params = pxa_ssp_hw_params, | |
1b340bd7 MB |
873 | .set_sysclk = pxa_ssp_set_dai_sysclk, |
874 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, | |
875 | .set_pll = pxa_ssp_set_dai_pll, | |
876 | .set_fmt = pxa_ssp_set_dai_fmt, | |
877 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, | |
878 | .set_tristate = pxa_ssp_set_dai_tristate, | |
879 | }, | |
880 | }, | |
881 | { | |
882 | .name = "pxa2xx-ssp4", | |
883 | .id = 3, | |
1b340bd7 MB |
884 | .probe = pxa_ssp_probe, |
885 | .remove = pxa_ssp_remove, | |
886 | .suspend = pxa_ssp_suspend, | |
887 | .resume = pxa_ssp_resume, | |
888 | .playback = { | |
889 | .channels_min = 1, | |
890 | .channels_max = 2, | |
891 | .rates = PXA_SSP_RATES, | |
892 | .formats = PXA_SSP_FORMATS, | |
893 | }, | |
894 | .capture = { | |
895 | .channels_min = 1, | |
896 | .channels_max = 2, | |
897 | .rates = PXA_SSP_RATES, | |
898 | .formats = PXA_SSP_FORMATS, | |
899 | }, | |
900 | .ops = { | |
901 | .startup = pxa_ssp_startup, | |
902 | .shutdown = pxa_ssp_shutdown, | |
903 | .trigger = pxa_ssp_trigger, | |
904 | .hw_params = pxa_ssp_hw_params, | |
1b340bd7 MB |
905 | .set_sysclk = pxa_ssp_set_dai_sysclk, |
906 | .set_clkdiv = pxa_ssp_set_dai_clkdiv, | |
907 | .set_pll = pxa_ssp_set_dai_pll, | |
908 | .set_fmt = pxa_ssp_set_dai_fmt, | |
909 | .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, | |
910 | .set_tristate = pxa_ssp_set_dai_tristate, | |
911 | }, | |
912 | }, | |
913 | }; | |
914 | EXPORT_SYMBOL_GPL(pxa_ssp_dai); | |
915 | ||
916 | /* Module information */ | |
917 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
918 | MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); | |
919 | MODULE_LICENSE("GPL"); |