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ASoC: Allow 32 bit registers for DAPM
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
0664678a
PZ		 23#include <asm/irq.h>
24
1b340bd7
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/pxa2xx-lib.h>
31
32#include <mach/hardware.h>
7ebc8d56 33#include <mach/dma.h>
1b340bd7
MB		 34#include <mach/regs-ssp.h>
35#include <mach/audio.h>
36#include <mach/ssp.h>
37
38#include "pxa2xx-pcm.h"
39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
45 struct ssp_dev dev;
46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
49 struct ssp_state state;
50#endif
51};
52
1b340bd7
MB		 53static void dump_registers(struct ssp_device *ssp)
54{
55 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
56 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
57 ssp_read_reg(ssp, SSTO));
58
59 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
60 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
61 ssp_read_reg(ssp, SSACD));
62}
63
2d7e71fa
EM		 64struct pxa2xx_pcm_dma_data {
65 struct pxa2xx_pcm_dma_params params;
66 char name[20];
1b340bd7
MB		 67};
68
2d7e71fa 69static struct pxa2xx_pcm_dma_params *
8eb9feab 70ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
2d7e71fa
EM		 71{
72 struct pxa2xx_pcm_dma_data *dma;
73
74 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
75 if (dma == NULL)
76 return NULL;
77
78 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
8eb9feab 79 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
2d7e71fa
EM		 80
81 dma->params.name = dma->name;
82 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
83 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
84 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
8eb9feab 85 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
2d7e71fa
EM		 86 dma->params.dev_addr = ssp->phys_base + SSDR;
87
88 return &dma->params;
89}
90
dee89c4d
MB		 91static int pxa_ssp_startup(struct snd_pcm_substream *substream,
92 struct snd_soc_dai *dai)
1b340bd7
MB		 93{
94 struct snd_soc_pcm_runtime *rtd = substream->private_data;
95 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
96 struct ssp_priv *priv = cpu_dai->private_data;
97 int ret = 0;
98
99 if (!cpu_dai->active) {
0664678a
PZ		 100 priv->dev.port = cpu_dai->id + 1;
101 priv->dev.irq = NO_IRQ;
102 clk_enable(priv->dev.ssp->clk);
1b340bd7
MB		 103 ssp_disable(&priv->dev);
104 }
2d7e71fa
EM		 105
106 if (cpu_dai->dma_data) {
107 kfree(cpu_dai->dma_data);
108 cpu_dai->dma_data = NULL;
109 }
1b340bd7
MB		 110 return ret;
111}
112
dee89c4d
MB		 113static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
114 struct snd_soc_dai *dai)
1b340bd7
MB		 115{
116 struct snd_soc_pcm_runtime *rtd = substream->private_data;
117 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
118 struct ssp_priv *priv = cpu_dai->private_data;
119
120 if (!cpu_dai->active) {
121 ssp_disable(&priv->dev);
0664678a 122 clk_disable(priv->dev.ssp->clk);
1b340bd7 123 }
2d7e71fa
EM		 124
125 if (cpu_dai->dma_data) {
126 kfree(cpu_dai->dma_data);
127 cpu_dai->dma_data = NULL;
128 }
1b340bd7
MB		 129}
130
131#ifdef CONFIG_PM
132
dc7d7b83 133static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 134{
135 struct ssp_priv *priv = cpu_dai->private_data;
136
137 if (!cpu_dai->active)
138 return 0;
139
140 ssp_save_state(&priv->dev, &priv->state);
141 clk_disable(priv->dev.ssp->clk);
142 return 0;
143}
144
dc7d7b83 145static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 146{
147 struct ssp_priv *priv = cpu_dai->private_data;
148
149 if (!cpu_dai->active)
150 return 0;
151
152 clk_enable(priv->dev.ssp->clk);
153 ssp_restore_state(&priv->dev, &priv->state);
154 ssp_enable(&priv->dev);
155
156 return 0;
157}
158
159#else
160#define pxa_ssp_suspend NULL
161#define pxa_ssp_resume NULL
162#endif
163
164/**
165 * ssp_set_clkdiv - set SSP clock divider
166 * @div: serial clock rate divider
167 */
1a297286 168static void ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 169{
1a297286
PZ		 170 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
171
172 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
173 sscr0 &= ~0x0000ff00;
174 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
175 } else {
176 sscr0 &= ~0x000fff00;
177 sscr0 |= (div - 1) << 8; /* 1..4096 */
178 }
179 ssp_write_reg(ssp, SSCR0, sscr0);
180}
181
182/**
183 * ssp_get_clkdiv - get SSP clock divider
184 */
185static u32 ssp_get_scr(struct ssp_device *ssp)
186{
187 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
188 u32 div;
1b340bd7 189
1a297286
PZ		 190 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
191 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
192 else
193 div = ((sscr0 >> 8) & 0xfff) + 1;
194 return div;
1b340bd7
MB		 195}
196
197/*
198 * Set the SSP ports SYSCLK.
199 */
200static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
201 int clk_id, unsigned int freq, int dir)
202{
203 struct ssp_priv *priv = cpu_dai->private_data;
204 struct ssp_device *ssp = priv->dev.ssp;
205 int val;
206
207 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 208 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 209
210 dev_dbg(&ssp->pdev->dev,
449bd54d 211 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 212 cpu_dai->id, clk_id, freq);
213
214 switch (clk_id) {
215 case PXA_SSP_CLK_NET_PLL:
216 sscr0 |= SSCR0_MOD;
217 break;
218 case PXA_SSP_CLK_PLL:
219 /* Internal PLL is fixed */
220 if (cpu_is_pxa25x())
221 priv->sysclk = 1843200;
222 else
223 priv->sysclk = 13000000;
224 break;
225 case PXA_SSP_CLK_EXT:
226 priv->sysclk = freq;
227 sscr0 |= SSCR0_ECS;
228 break;
229 case PXA_SSP_CLK_NET:
230 priv->sysclk = freq;
231 sscr0 |= SSCR0_NCS | SSCR0_MOD;
232 break;
233 case PXA_SSP_CLK_AUDIO:
234 priv->sysclk = 0;
1a297286 235 ssp_set_scr(ssp, 1);
20a41eac 236 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 237 break;
238 default:
239 return -ENODEV;
240 }
241
242 /* The SSP clock must be disabled when changing SSP clock mode
243 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
244 if (!cpu_is_pxa3xx())
245 clk_disable(priv->dev.ssp->clk);
246 val = ssp_read_reg(ssp, SSCR0) | sscr0;
247 ssp_write_reg(ssp, SSCR0, val);
248 if (!cpu_is_pxa3xx())
249 clk_enable(priv->dev.ssp->clk);
250
251 return 0;
252}
253
254/*
255 * Set the SSP clock dividers.
256 */
257static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
258 int div_id, int div)
259{
260 struct ssp_priv *priv = cpu_dai->private_data;
261 struct ssp_device *ssp = priv->dev.ssp;
262 int val;
263
264 switch (div_id) {
265 case PXA_SSP_AUDIO_DIV_ACDS:
266 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
267 ssp_write_reg(ssp, SSACD, val);
268 break;
269 case PXA_SSP_AUDIO_DIV_SCDB:
270 val = ssp_read_reg(ssp, SSACD);
271 val &= ~SSACD_SCDB;
272#if defined(CONFIG_PXA3xx)
273 if (cpu_is_pxa3xx())
274 val &= ~SSACD_SCDX8;
275#endif
276 switch (div) {
277 case PXA_SSP_CLK_SCDB_1:
278 val |= SSACD_SCDB;
279 break;
280 case PXA_SSP_CLK_SCDB_4:
281 break;
282#if defined(CONFIG_PXA3xx)
283 case PXA_SSP_CLK_SCDB_8:
284 if (cpu_is_pxa3xx())
285 val |= SSACD_SCDX8;
286 else
287 return -EINVAL;
288 break;
289#endif
290 default:
291 return -EINVAL;
292 }
293 ssp_write_reg(ssp, SSACD, val);
294 break;
295 case PXA_SSP_DIV_SCR:
1a297286 296 ssp_set_scr(ssp, div);
1b340bd7
MB		 297 break;
298 default:
299 return -ENODEV;
300 }
301
302 return 0;
303}
304
305/*
306 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
307 */
308static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
309 int pll_id, unsigned int freq_in, unsigned int freq_out)
310{
311 struct ssp_priv *priv = cpu_dai->private_data;
312 struct ssp_device *ssp = priv->dev.ssp;
313 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
314
315#if defined(CONFIG_PXA3xx)
316 if (cpu_is_pxa3xx())
317 ssp_write_reg(ssp, SSACDD, 0);
318#endif
319
320 switch (freq_out) {
321 case 5622000:
322 break;
323 case 11345000:
324 ssacd |= (0x1 << 4);
325 break;
326 case 12235000:
327 ssacd |= (0x2 << 4);
328 break;
329 case 14857000:
330 ssacd |= (0x3 << 4);
331 break;
332 case 32842000:
333 ssacd |= (0x4 << 4);
334 break;
335 case 48000000:
336 ssacd |= (0x5 << 4);
337 break;
338 case 0:
339 /* Disable */
340 break;
341
342 default:
343#ifdef CONFIG_PXA3xx
344 /* PXA3xx has a clock ditherer which can be used to generate
345 * a wider range of frequencies - calculate a value for it.
346 */
347 if (cpu_is_pxa3xx()) {
348 u32 val;
349 u64 tmp = 19968;
350 tmp *= 1000000;
351 do_div(tmp, freq_out);
352 val = tmp;
353
354 val = (val << 16) | 64;;
355 ssp_write_reg(ssp, SSACDD, val);
356
357 ssacd |= (0x6 << 4);
358
359 dev_dbg(&ssp->pdev->dev,
449bd54d 360 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 361 val, freq_out);
362 break;
363 }
364#endif
365
366 return -EINVAL;
367 }
368
369 ssp_write_reg(ssp, SSACD, ssacd);
370
371 return 0;
372}
373
374/*
375 * Set the active slots in TDM/Network mode
376 */
377static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
378 unsigned int mask, int slots)
379{
380 struct ssp_priv *priv = cpu_dai->private_data;
381 struct ssp_device *ssp = priv->dev.ssp;
382 u32 sscr0;
383
384 sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
385
386 /* set number of active slots */
387 sscr0 |= SSCR0_SlotsPerFrm(slots);
388 ssp_write_reg(ssp, SSCR0, sscr0);
389
390 /* set active slot mask */
391 ssp_write_reg(ssp, SSTSA, mask);
392 ssp_write_reg(ssp, SSRSA, mask);
393 return 0;
394}
395
396/*
397 * Tristate the SSP DAI lines
398 */
399static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
400 int tristate)
401{
402 struct ssp_priv *priv = cpu_dai->private_data;
403 struct ssp_device *ssp = priv->dev.ssp;
404 u32 sscr1;
405
406 sscr1 = ssp_read_reg(ssp, SSCR1);
407 if (tristate)
408 sscr1 &= ~SSCR1_TTE;
409 else
410 sscr1 |= SSCR1_TTE;
411 ssp_write_reg(ssp, SSCR1, sscr1);
412
413 return 0;
414}
415
416/*
417 * Set up the SSP DAI format.
418 * The SSP Port must be inactive before calling this function as the
419 * physical interface format is changed.
420 */
421static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
422 unsigned int fmt)
423{
424 struct ssp_priv *priv = cpu_dai->private_data;
425 struct ssp_device *ssp = priv->dev.ssp;
426 u32 sscr0;
427 u32 sscr1;
428 u32 sspsp;
429
cbf1146d
DM		 430 /* check if we need to change anything at all */
431 if (priv->dai_fmt == fmt)
432 return 0;
433
434 /* we can only change the settings if the port is not in use */
435 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
436 dev_err(&ssp->pdev->dev,
437 "can't change hardware dai format: stream is in use");
438 return -EINVAL;
439 }
440
1b340bd7
MB		 441 /* reset port settings */
442 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 443 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 444 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
445 sspsp = 0;
446
447 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
448 case SND_SOC_DAIFMT_CBM_CFM:
449 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
450 break;
451 case SND_SOC_DAIFMT_CBM_CFS:
452 sscr1 |= SSCR1_SCLKDIR;
453 break;
454 case SND_SOC_DAIFMT_CBS_CFS:
455 break;
456 default:
457 return -EINVAL;
458 }
459
460 ssp_write_reg(ssp, SSCR0, sscr0);
461 ssp_write_reg(ssp, SSCR1, sscr1);
462 ssp_write_reg(ssp, SSPSP, sspsp);
463
464 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
465 case SND_SOC_DAIFMT_I2S:
72d74664 466 sscr0 |= SSCR0_PSP;
1b340bd7
MB		 467 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
468
0ce36c5f 469 /* See hw_params() */
1b340bd7
MB		 470 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
471 case SND_SOC_DAIFMT_NB_NF:
0ce36c5f 472 sspsp |= SSPSP_SFRMP;
1b340bd7
MB		 473 break;
474 case SND_SOC_DAIFMT_NB_IF:
1b340bd7
MB		 475 break;
476 case SND_SOC_DAIFMT_IB_IF:
a8205320
DR		 477 sspsp |= SSPSP_SCMODE(2);
478 break;
479 case SND_SOC_DAIFMT_IB_NF:
480 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
1b340bd7
MB		 481 break;
482 default:
483 return -EINVAL;
484 }
485 break;
486
487 case SND_SOC_DAIFMT_DSP_A:
488 sspsp |= SSPSP_FSRT;
489 case SND_SOC_DAIFMT_DSP_B:
490 sscr0 |= SSCR0_MOD | SSCR0_PSP;
491 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
492
493 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
494 case SND_SOC_DAIFMT_NB_NF:
495 sspsp |= SSPSP_SFRMP;
496 break;
a8205320
DR		 497 case SND_SOC_DAIFMT_NB_IF:
498 break;
1b340bd7 499 case SND_SOC_DAIFMT_IB_IF:
a8205320
DR		 500 sspsp |= SSPSP_SCMODE(2);
501 break;
502 case SND_SOC_DAIFMT_IB_NF:
503 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
1b340bd7
MB		 504 break;
505 default:
506 return -EINVAL;
507 }
508 break;
509
510 default:
511 return -EINVAL;
512 }
513
514 ssp_write_reg(ssp, SSCR0, sscr0);
515 ssp_write_reg(ssp, SSCR1, sscr1);
516 ssp_write_reg(ssp, SSPSP, sspsp);
517
518 dump_registers(ssp);
519
520 /* Since we are configuring the timings for the format by hand
521 * we have to defer some things until hw_params() where we
522 * know parameters like the sample size.
523 */
524 priv->dai_fmt = fmt;
525
526 return 0;
527}
528
529/*
530 * Set the SSP audio DMA parameters and sample size.
531 * Can be called multiple times by oss emulation.
532 */
533static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 534 struct snd_pcm_hw_params *params,
535 struct snd_soc_dai *dai)
1b340bd7
MB		 536{
537 struct snd_soc_pcm_runtime *rtd = substream->private_data;
538 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
539 struct ssp_priv *priv = cpu_dai->private_data;
540 struct ssp_device *ssp = priv->dev.ssp;
2d7e71fa 541 int chn = params_channels(params);
1b340bd7
MB		 542 u32 sscr0;
543 u32 sspsp;
544 int width = snd_pcm_format_physical_width(params_format(params));
92429069 545 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
1b340bd7 546
2d7e71fa
EM		 547 /* generate correct DMA params */
548 if (cpu_dai->dma_data)
549 kfree(cpu_dai->dma_data);
550
92429069
PZ		 551 /* Network mode with one active slot (ttsa == 1) can be used
552 * to force 16-bit frame width on the wire (for S16_LE), even
553 * with two channels. Use 16-bit DMA transfers for this case.
554 */
2d7e71fa
EM		 555 cpu_dai->dma_data = ssp_get_dma_params(ssp,
556 ((chn == 2) && (ttsa != 1)) || (width == 32),
557 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1b340bd7
MB		 558
559 /* we can only change the settings if the port is not in use */
560 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
561 return 0;
562
563 /* clear selected SSP bits */
564 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
565 ssp_write_reg(ssp, SSCR0, sscr0);
566
567 /* bit size */
568 sscr0 = ssp_read_reg(ssp, SSCR0);
569 switch (params_format(params)) {
570 case SNDRV_PCM_FORMAT_S16_LE:
571#ifdef CONFIG_PXA3xx
572 if (cpu_is_pxa3xx())
573 sscr0 |= SSCR0_FPCKE;
574#endif
575 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 576 break;
577 case SNDRV_PCM_FORMAT_S24_LE:
578 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 579 break;
580 case SNDRV_PCM_FORMAT_S32_LE:
581 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 582 break;
583 }
584 ssp_write_reg(ssp, SSCR0, sscr0);
585
586 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
587 case SND_SOC_DAIFMT_I2S:
72d74664
DM		 588 sspsp = ssp_read_reg(ssp, SSPSP);
589
1a297286 590 if ((ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 591 /* This is a special case where the bitclk is 64fs
592 * and we're not dealing with 2*32 bits of audio
593 * samples.
594 *
595 * The SSP values used for that are all found out by
596 * trying and failing a lot; some of the registers
597 * needed for that mode are only available on PXA3xx.
598 */
599
600#ifdef CONFIG_PXA3xx
601 if (!cpu_is_pxa3xx())
602 return -EINVAL;
603
604 sspsp |= SSPSP_SFRMWDTH(width * 2);
605 sspsp |= SSPSP_SFRMDLY(width * 4);
606 sspsp |= SSPSP_EDMYSTOP(3);
607 sspsp |= SSPSP_DMYSTOP(3);
608 sspsp |= SSPSP_DMYSTRT(1);
609#else
610 return -EINVAL;
611#endif
0ce36c5f
MB		 612 } else {
613 /* The frame width is the width the LRCLK is
614 * asserted for; the delay is expressed in
615 * half cycle units. We need the extra cycle
616 * because the data starts clocking out one BCLK
617 * after LRCLK changes polarity.
618 */
619 sspsp |= SSPSP_SFRMWDTH(width + 1);
620 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
621 sspsp |= SSPSP_DMYSTRT(1);
622 }
72d74664 623
1b340bd7
MB		 624 ssp_write_reg(ssp, SSPSP, sspsp);
625 break;
626 default:
627 break;
628 }
629
72d74664 630 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 631 * - complain loudly and fail if they've not been set up yet.
632 */
92429069 633 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 634 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
635 return -EINVAL;
636 }
637
638 dump_registers(ssp);
639
640 return 0;
641}
642
dee89c4d
MB		 643static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
644 struct snd_soc_dai *dai)
1b340bd7
MB		 645{
646 struct snd_soc_pcm_runtime *rtd = substream->private_data;
647 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
648 int ret = 0;
649 struct ssp_priv *priv = cpu_dai->private_data;
650 struct ssp_device *ssp = priv->dev.ssp;
651 int val;
652
653 switch (cmd) {
654 case SNDRV_PCM_TRIGGER_RESUME:
655 ssp_enable(&priv->dev);
656 break;
657 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
658 val = ssp_read_reg(ssp, SSCR1);
659 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
660 val |= SSCR1_TSRE;
661 else
662 val |= SSCR1_RSRE;
663 ssp_write_reg(ssp, SSCR1, val);
664 val = ssp_read_reg(ssp, SSSR);
665 ssp_write_reg(ssp, SSSR, val);
666 break;
667 case SNDRV_PCM_TRIGGER_START:
668 val = ssp_read_reg(ssp, SSCR1);
669 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
670 val |= SSCR1_TSRE;
671 else
672 val |= SSCR1_RSRE;
673 ssp_write_reg(ssp, SSCR1, val);
674 ssp_enable(&priv->dev);
675 break;
676 case SNDRV_PCM_TRIGGER_STOP:
677 val = ssp_read_reg(ssp, SSCR1);
678 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
679 val &= ~SSCR1_TSRE;
680 else
681 val &= ~SSCR1_RSRE;
682 ssp_write_reg(ssp, SSCR1, val);
683 break;
684 case SNDRV_PCM_TRIGGER_SUSPEND:
685 ssp_disable(&priv->dev);
686 break;
687 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
688 val = ssp_read_reg(ssp, SSCR1);
689 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
690 val &= ~SSCR1_TSRE;
691 else
692 val &= ~SSCR1_RSRE;
693 ssp_write_reg(ssp, SSCR1, val);
694 break;
695
696 default:
697 ret = -EINVAL;
698 }
699
700 dump_registers(ssp);
701
702 return ret;
703}
704
705static int pxa_ssp_probe(struct platform_device *pdev,
706 struct snd_soc_dai *dai)
707{
708 struct ssp_priv *priv;
709 int ret;
710
711 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
712 if (!priv)
713 return -ENOMEM;
714
0664678a 715 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
1b340bd7
MB		 716 if (priv->dev.ssp == NULL) {
717 ret = -ENODEV;
718 goto err_priv;
719 }
720
a5735b7e 721 priv->dai_fmt = (unsigned int) -1;
1b340bd7
MB		 722 dai->private_data = priv;
723
724 return 0;
725
726err_priv:
727 kfree(priv);
728 return ret;
729}
730
731static void pxa_ssp_remove(struct platform_device *pdev,
732 struct snd_soc_dai *dai)
733{
734 struct ssp_priv *priv = dai->private_data;
735 ssp_free(priv->dev.ssp);
736}
737
738#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
739 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
740 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
741 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
742
743#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
744 SNDRV_PCM_FMTBIT_S24_LE | \
745 SNDRV_PCM_FMTBIT_S32_LE)
746
6335d055
EM		 747static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
748 .startup = pxa_ssp_startup,
749 .shutdown = pxa_ssp_shutdown,
750 .trigger = pxa_ssp_trigger,
751 .hw_params = pxa_ssp_hw_params,
752 .set_sysclk = pxa_ssp_set_dai_sysclk,
753 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
754 .set_pll = pxa_ssp_set_dai_pll,
755 .set_fmt = pxa_ssp_set_dai_fmt,
756 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
757 .set_tristate = pxa_ssp_set_dai_tristate,
758};
759
1b340bd7
MB		 760struct snd_soc_dai pxa_ssp_dai[] = {
761 {
762 .name = "pxa2xx-ssp1",
763 .id = 0,
1b340bd7
MB		 764 .probe = pxa_ssp_probe,
765 .remove = pxa_ssp_remove,
766 .suspend = pxa_ssp_suspend,
767 .resume = pxa_ssp_resume,
768 .playback = {
769 .channels_min = 1,
770 .channels_max = 2,
771 .rates = PXA_SSP_RATES,
772 .formats = PXA_SSP_FORMATS,
773 },
774 .capture = {
775 .channels_min = 1,
776 .channels_max = 2,
777 .rates = PXA_SSP_RATES,
778 .formats = PXA_SSP_FORMATS,
779 },
6335d055 780 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 781 },
782 { .name = "pxa2xx-ssp2",
783 .id = 1,
1b340bd7
MB		 784 .probe = pxa_ssp_probe,
785 .remove = pxa_ssp_remove,
786 .suspend = pxa_ssp_suspend,
787 .resume = pxa_ssp_resume,
788 .playback = {
789 .channels_min = 1,
790 .channels_max = 2,
791 .rates = PXA_SSP_RATES,
792 .formats = PXA_SSP_FORMATS,
793 },
794 .capture = {
795 .channels_min = 1,
796 .channels_max = 2,
797 .rates = PXA_SSP_RATES,
798 .formats = PXA_SSP_FORMATS,
799 },
6335d055 800 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 801 },
802 {
803 .name = "pxa2xx-ssp3",
804 .id = 2,
1b340bd7
MB		 805 .probe = pxa_ssp_probe,
806 .remove = pxa_ssp_remove,
807 .suspend = pxa_ssp_suspend,
808 .resume = pxa_ssp_resume,
809 .playback = {
810 .channels_min = 1,
811 .channels_max = 2,
812 .rates = PXA_SSP_RATES,
813 .formats = PXA_SSP_FORMATS,
814 },
815 .capture = {
816 .channels_min = 1,
817 .channels_max = 2,
818 .rates = PXA_SSP_RATES,
819 .formats = PXA_SSP_FORMATS,
820 },
6335d055 821 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 822 },
823 {
824 .name = "pxa2xx-ssp4",
825 .id = 3,
1b340bd7
MB		 826 .probe = pxa_ssp_probe,
827 .remove = pxa_ssp_remove,
828 .suspend = pxa_ssp_suspend,
829 .resume = pxa_ssp_resume,
830 .playback = {
831 .channels_min = 1,
832 .channels_max = 2,
833 .rates = PXA_SSP_RATES,
834 .formats = PXA_SSP_FORMATS,
835 },
836 .capture = {
837 .channels_min = 1,
838 .channels_max = 2,
839 .rates = PXA_SSP_RATES,
840 .formats = PXA_SSP_FORMATS,
841 },
6335d055 842 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 843 },
844};
845EXPORT_SYMBOL_GPL(pxa_ssp_dai);
846
c9b3a40f 847static int __init pxa_ssp_init(void)
3f4b783c
MB		 848{
849 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
850}
851module_init(pxa_ssp_init);
852
853static void __exit pxa_ssp_exit(void)
854{
855 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
856}
857module_exit(pxa_ssp_exit);
858
1b340bd7
MB		 859/* Module information */
860MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
861MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
862MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)