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ASoC: TWL4030: Add VDL path support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22
0664678a
PZ		 23#include <asm/irq.h>
24
1b340bd7
MB		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/initval.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/pxa2xx-lib.h>
31
32#include <mach/hardware.h>
7ebc8d56 33#include <mach/dma.h>
1b340bd7
MB		 34#include <mach/regs-ssp.h>
35#include <mach/audio.h>
36#include <mach/ssp.h>
37
38#include "pxa2xx-pcm.h"
39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
45 struct ssp_dev dev;
46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
49 struct ssp_state state;
50#endif
51};
52
53#define PXA2xx_SSP1_BASE 0x41000000
54#define PXA27x_SSP2_BASE 0x41700000
55#define PXA27x_SSP3_BASE 0x41900000
56#define PXA3xx_SSP4_BASE 0x41a00000
57
58static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = {
59 .name = "SSP1 PCM Mono out",
60 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
61 .drcmr = &DRCMR(14),
62 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
63 DCMD_BURST16 | DCMD_WIDTH2,
64};
65
66static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = {
67 .name = "SSP1 PCM Mono in",
68 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
69 .drcmr = &DRCMR(13),
70 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
71 DCMD_BURST16 | DCMD_WIDTH2,
72};
73
74static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = {
75 .name = "SSP1 PCM Stereo out",
76 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
77 .drcmr = &DRCMR(14),
78 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
79 DCMD_BURST16 | DCMD_WIDTH4,
80};
81
82static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = {
83 .name = "SSP1 PCM Stereo in",
84 .dev_addr = PXA2xx_SSP1_BASE + SSDR,
85 .drcmr = &DRCMR(13),
86 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
87 DCMD_BURST16 | DCMD_WIDTH4,
88};
89
90static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = {
91 .name = "SSP2 PCM Mono out",
92 .dev_addr = PXA27x_SSP2_BASE + SSDR,
93 .drcmr = &DRCMR(16),
94 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
95 DCMD_BURST16 | DCMD_WIDTH2,
96};
97
98static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = {
99 .name = "SSP2 PCM Mono in",
100 .dev_addr = PXA27x_SSP2_BASE + SSDR,
101 .drcmr = &DRCMR(15),
102 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
103 DCMD_BURST16 | DCMD_WIDTH2,
104};
105
106static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = {
107 .name = "SSP2 PCM Stereo out",
108 .dev_addr = PXA27x_SSP2_BASE + SSDR,
109 .drcmr = &DRCMR(16),
110 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
111 DCMD_BURST16 | DCMD_WIDTH4,
112};
113
114static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = {
115 .name = "SSP2 PCM Stereo in",
116 .dev_addr = PXA27x_SSP2_BASE + SSDR,
117 .drcmr = &DRCMR(15),
118 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
119 DCMD_BURST16 | DCMD_WIDTH4,
120};
121
122static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = {
123 .name = "SSP3 PCM Mono out",
124 .dev_addr = PXA27x_SSP3_BASE + SSDR,
125 .drcmr = &DRCMR(67),
126 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
127 DCMD_BURST16 | DCMD_WIDTH2,
128};
129
130static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = {
131 .name = "SSP3 PCM Mono in",
132 .dev_addr = PXA27x_SSP3_BASE + SSDR,
133 .drcmr = &DRCMR(66),
134 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
135 DCMD_BURST16 | DCMD_WIDTH2,
136};
137
138static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = {
139 .name = "SSP3 PCM Stereo out",
140 .dev_addr = PXA27x_SSP3_BASE + SSDR,
141 .drcmr = &DRCMR(67),
142 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
143 DCMD_BURST16 | DCMD_WIDTH4,
144};
145
146static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = {
147 .name = "SSP3 PCM Stereo in",
148 .dev_addr = PXA27x_SSP3_BASE + SSDR,
149 .drcmr = &DRCMR(66),
150 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
151 DCMD_BURST16 | DCMD_WIDTH4,
152};
153
154static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = {
155 .name = "SSP4 PCM Mono out",
156 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
157 .drcmr = &DRCMR(67),
158 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
159 DCMD_BURST16 | DCMD_WIDTH2,
160};
161
162static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = {
163 .name = "SSP4 PCM Mono in",
164 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
165 .drcmr = &DRCMR(66),
166 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
167 DCMD_BURST16 | DCMD_WIDTH2,
168};
169
170static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = {
171 .name = "SSP4 PCM Stereo out",
172 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
173 .drcmr = &DRCMR(67),
174 .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
175 DCMD_BURST16 | DCMD_WIDTH4,
176};
177
178static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = {
179 .name = "SSP4 PCM Stereo in",
180 .dev_addr = PXA3xx_SSP4_BASE + SSDR,
181 .drcmr = &DRCMR(66),
182 .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
183 DCMD_BURST16 | DCMD_WIDTH4,
184};
185
186static void dump_registers(struct ssp_device *ssp)
187{
188 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
189 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
190 ssp_read_reg(ssp, SSTO));
191
192 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
193 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
194 ssp_read_reg(ssp, SSACD));
195}
196
197static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = {
198 {
199 &pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in,
200 &pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in,
201 },
202 {
203 &pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in,
204 &pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in,
205 },
206 {
207 &pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in,
208 &pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in,
209 },
210 {
211 &pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in,
212 &pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in,
213 },
214};
215
dee89c4d
MB		 216static int pxa_ssp_startup(struct snd_pcm_substream *substream,
217 struct snd_soc_dai *dai)
1b340bd7
MB		 218{
219 struct snd_soc_pcm_runtime *rtd = substream->private_data;
220 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
221 struct ssp_priv *priv = cpu_dai->private_data;
222 int ret = 0;
223
224 if (!cpu_dai->active) {
0664678a
PZ		 225 priv->dev.port = cpu_dai->id + 1;
226 priv->dev.irq = NO_IRQ;
227 clk_enable(priv->dev.ssp->clk);
1b340bd7
MB		 228 ssp_disable(&priv->dev);
229 }
230 return ret;
231}
232
dee89c4d
MB		 233static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
234 struct snd_soc_dai *dai)
1b340bd7
MB		 235{
236 struct snd_soc_pcm_runtime *rtd = substream->private_data;
237 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
238 struct ssp_priv *priv = cpu_dai->private_data;
239
240 if (!cpu_dai->active) {
241 ssp_disable(&priv->dev);
0664678a 242 clk_disable(priv->dev.ssp->clk);
1b340bd7
MB		 243 }
244}
245
246#ifdef CONFIG_PM
247
dc7d7b83 248static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 249{
250 struct ssp_priv *priv = cpu_dai->private_data;
251
252 if (!cpu_dai->active)
253 return 0;
254
255 ssp_save_state(&priv->dev, &priv->state);
256 clk_disable(priv->dev.ssp->clk);
257 return 0;
258}
259
dc7d7b83 260static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7
MB		 261{
262 struct ssp_priv *priv = cpu_dai->private_data;
263
264 if (!cpu_dai->active)
265 return 0;
266
267 clk_enable(priv->dev.ssp->clk);
268 ssp_restore_state(&priv->dev, &priv->state);
269 ssp_enable(&priv->dev);
270
271 return 0;
272}
273
274#else
275#define pxa_ssp_suspend NULL
276#define pxa_ssp_resume NULL
277#endif
278
279/**
280 * ssp_set_clkdiv - set SSP clock divider
281 * @div: serial clock rate divider
282 */
1a297286 283static void ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 284{
1a297286
PZ		 285 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
286
287 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
288 sscr0 &= ~0x0000ff00;
289 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
290 } else {
291 sscr0 &= ~0x000fff00;
292 sscr0 |= (div - 1) << 8; /* 1..4096 */
293 }
294 ssp_write_reg(ssp, SSCR0, sscr0);
295}
296
297/**
298 * ssp_get_clkdiv - get SSP clock divider
299 */
300static u32 ssp_get_scr(struct ssp_device *ssp)
301{
302 u32 sscr0 = ssp_read_reg(ssp, SSCR0);
303 u32 div;
1b340bd7 304
1a297286
PZ		 305 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
306 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
307 else
308 div = ((sscr0 >> 8) & 0xfff) + 1;
309 return div;
1b340bd7
MB		 310}
311
312/*
313 * Set the SSP ports SYSCLK.
314 */
315static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
316 int clk_id, unsigned int freq, int dir)
317{
318 struct ssp_priv *priv = cpu_dai->private_data;
319 struct ssp_device *ssp = priv->dev.ssp;
320 int val;
321
322 u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 323 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 324
325 dev_dbg(&ssp->pdev->dev,
326 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
327 cpu_dai->id, clk_id, freq);
328
329 switch (clk_id) {
330 case PXA_SSP_CLK_NET_PLL:
331 sscr0 |= SSCR0_MOD;
332 break;
333 case PXA_SSP_CLK_PLL:
334 /* Internal PLL is fixed */
335 if (cpu_is_pxa25x())
336 priv->sysclk = 1843200;
337 else
338 priv->sysclk = 13000000;
339 break;
340 case PXA_SSP_CLK_EXT:
341 priv->sysclk = freq;
342 sscr0 |= SSCR0_ECS;
343 break;
344 case PXA_SSP_CLK_NET:
345 priv->sysclk = freq;
346 sscr0 |= SSCR0_NCS | SSCR0_MOD;
347 break;
348 case PXA_SSP_CLK_AUDIO:
349 priv->sysclk = 0;
1a297286 350 ssp_set_scr(ssp, 1);
20a41eac 351 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 352 break;
353 default:
354 return -ENODEV;
355 }
356
357 /* The SSP clock must be disabled when changing SSP clock mode
358 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
359 if (!cpu_is_pxa3xx())
360 clk_disable(priv->dev.ssp->clk);
361 val = ssp_read_reg(ssp, SSCR0) | sscr0;
362 ssp_write_reg(ssp, SSCR0, val);
363 if (!cpu_is_pxa3xx())
364 clk_enable(priv->dev.ssp->clk);
365
366 return 0;
367}
368
369/*
370 * Set the SSP clock dividers.
371 */
372static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
373 int div_id, int div)
374{
375 struct ssp_priv *priv = cpu_dai->private_data;
376 struct ssp_device *ssp = priv->dev.ssp;
377 int val;
378
379 switch (div_id) {
380 case PXA_SSP_AUDIO_DIV_ACDS:
381 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
382 ssp_write_reg(ssp, SSACD, val);
383 break;
384 case PXA_SSP_AUDIO_DIV_SCDB:
385 val = ssp_read_reg(ssp, SSACD);
386 val &= ~SSACD_SCDB;
387#if defined(CONFIG_PXA3xx)
388 if (cpu_is_pxa3xx())
389 val &= ~SSACD_SCDX8;
390#endif
391 switch (div) {
392 case PXA_SSP_CLK_SCDB_1:
393 val |= SSACD_SCDB;
394 break;
395 case PXA_SSP_CLK_SCDB_4:
396 break;
397#if defined(CONFIG_PXA3xx)
398 case PXA_SSP_CLK_SCDB_8:
399 if (cpu_is_pxa3xx())
400 val |= SSACD_SCDX8;
401 else
402 return -EINVAL;
403 break;
404#endif
405 default:
406 return -EINVAL;
407 }
408 ssp_write_reg(ssp, SSACD, val);
409 break;
410 case PXA_SSP_DIV_SCR:
1a297286 411 ssp_set_scr(ssp, div);
1b340bd7
MB		 412 break;
413 default:
414 return -ENODEV;
415 }
416
417 return 0;
418}
419
420/*
421 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
422 */
423static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
424 int pll_id, unsigned int freq_in, unsigned int freq_out)
425{
426 struct ssp_priv *priv = cpu_dai->private_data;
427 struct ssp_device *ssp = priv->dev.ssp;
428 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
429
430#if defined(CONFIG_PXA3xx)
431 if (cpu_is_pxa3xx())
432 ssp_write_reg(ssp, SSACDD, 0);
433#endif
434
435 switch (freq_out) {
436 case 5622000:
437 break;
438 case 11345000:
439 ssacd |= (0x1 << 4);
440 break;
441 case 12235000:
442 ssacd |= (0x2 << 4);
443 break;
444 case 14857000:
445 ssacd |= (0x3 << 4);
446 break;
447 case 32842000:
448 ssacd |= (0x4 << 4);
449 break;
450 case 48000000:
451 ssacd |= (0x5 << 4);
452 break;
453 case 0:
454 /* Disable */
455 break;
456
457 default:
458#ifdef CONFIG_PXA3xx
459 /* PXA3xx has a clock ditherer which can be used to generate
460 * a wider range of frequencies - calculate a value for it.
461 */
462 if (cpu_is_pxa3xx()) {
463 u32 val;
464 u64 tmp = 19968;
465 tmp *= 1000000;
466 do_div(tmp, freq_out);
467 val = tmp;
468
469 val = (val << 16) | 64;;
470 ssp_write_reg(ssp, SSACDD, val);
471
472 ssacd |= (0x6 << 4);
473
474 dev_dbg(&ssp->pdev->dev,
475 "Using SSACDD %x to supply %dHz\n",
476 val, freq_out);
477 break;
478 }
479#endif
480
481 return -EINVAL;
482 }
483
484 ssp_write_reg(ssp, SSACD, ssacd);
485
486 return 0;
487}
488
489/*
490 * Set the active slots in TDM/Network mode
491 */
492static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
493 unsigned int mask, int slots)
494{
495 struct ssp_priv *priv = cpu_dai->private_data;
496 struct ssp_device *ssp = priv->dev.ssp;
497 u32 sscr0;
498
499 sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
500
501 /* set number of active slots */
502 sscr0 |= SSCR0_SlotsPerFrm(slots);
503 ssp_write_reg(ssp, SSCR0, sscr0);
504
505 /* set active slot mask */
506 ssp_write_reg(ssp, SSTSA, mask);
507 ssp_write_reg(ssp, SSRSA, mask);
508 return 0;
509}
510
511/*
512 * Tristate the SSP DAI lines
513 */
514static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
515 int tristate)
516{
517 struct ssp_priv *priv = cpu_dai->private_data;
518 struct ssp_device *ssp = priv->dev.ssp;
519 u32 sscr1;
520
521 sscr1 = ssp_read_reg(ssp, SSCR1);
522 if (tristate)
523 sscr1 &= ~SSCR1_TTE;
524 else
525 sscr1 |= SSCR1_TTE;
526 ssp_write_reg(ssp, SSCR1, sscr1);
527
528 return 0;
529}
530
531/*
532 * Set up the SSP DAI format.
533 * The SSP Port must be inactive before calling this function as the
534 * physical interface format is changed.
535 */
536static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
537 unsigned int fmt)
538{
539 struct ssp_priv *priv = cpu_dai->private_data;
540 struct ssp_device *ssp = priv->dev.ssp;
541 u32 sscr0;
542 u32 sscr1;
543 u32 sspsp;
544
cbf1146d
DM		 545 /* check if we need to change anything at all */
546 if (priv->dai_fmt == fmt)
547 return 0;
548
549 /* we can only change the settings if the port is not in use */
550 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
551 dev_err(&ssp->pdev->dev,
552 "can't change hardware dai format: stream is in use");
553 return -EINVAL;
554 }
555
1b340bd7
MB		 556 /* reset port settings */
557 sscr0 = ssp_read_reg(ssp, SSCR0) &
20a41eac 558 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 559 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
560 sspsp = 0;
561
562 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
563 case SND_SOC_DAIFMT_CBM_CFM:
564 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
565 break;
566 case SND_SOC_DAIFMT_CBM_CFS:
567 sscr1 |= SSCR1_SCLKDIR;
568 break;
569 case SND_SOC_DAIFMT_CBS_CFS:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 ssp_write_reg(ssp, SSCR0, sscr0);
576 ssp_write_reg(ssp, SSCR1, sscr1);
577 ssp_write_reg(ssp, SSPSP, sspsp);
578
579 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
580 case SND_SOC_DAIFMT_I2S:
72d74664 581 sscr0 |= SSCR0_PSP;
1b340bd7
MB		 582 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
583
0ce36c5f 584 /* See hw_params() */
1b340bd7
MB		 585 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
586 case SND_SOC_DAIFMT_NB_NF:
0ce36c5f 587 sspsp |= SSPSP_SFRMP;
1b340bd7
MB		 588 break;
589 case SND_SOC_DAIFMT_NB_IF:
1b340bd7
MB		 590 break;
591 case SND_SOC_DAIFMT_IB_IF:
a8205320
DR		 592 sspsp |= SSPSP_SCMODE(2);
593 break;
594 case SND_SOC_DAIFMT_IB_NF:
595 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
1b340bd7
MB		 596 break;
597 default:
598 return -EINVAL;
599 }
600 break;
601
602 case SND_SOC_DAIFMT_DSP_A:
603 sspsp |= SSPSP_FSRT;
604 case SND_SOC_DAIFMT_DSP_B:
605 sscr0 |= SSCR0_MOD | SSCR0_PSP;
606 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
607
608 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
609 case SND_SOC_DAIFMT_NB_NF:
610 sspsp |= SSPSP_SFRMP;
611 break;
a8205320
DR		 612 case SND_SOC_DAIFMT_NB_IF:
613 break;
1b340bd7 614 case SND_SOC_DAIFMT_IB_IF:
a8205320
DR		 615 sspsp |= SSPSP_SCMODE(2);
616 break;
617 case SND_SOC_DAIFMT_IB_NF:
618 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
1b340bd7
MB		 619 break;
620 default:
621 return -EINVAL;
622 }
623 break;
624
625 default:
626 return -EINVAL;
627 }
628
629 ssp_write_reg(ssp, SSCR0, sscr0);
630 ssp_write_reg(ssp, SSCR1, sscr1);
631 ssp_write_reg(ssp, SSPSP, sspsp);
632
633 dump_registers(ssp);
634
635 /* Since we are configuring the timings for the format by hand
636 * we have to defer some things until hw_params() where we
637 * know parameters like the sample size.
638 */
639 priv->dai_fmt = fmt;
640
641 return 0;
642}
643
644/*
645 * Set the SSP audio DMA parameters and sample size.
646 * Can be called multiple times by oss emulation.
647 */
648static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 649 struct snd_pcm_hw_params *params,
650 struct snd_soc_dai *dai)
1b340bd7
MB		 651{
652 struct snd_soc_pcm_runtime *rtd = substream->private_data;
653 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
654 struct ssp_priv *priv = cpu_dai->private_data;
655 struct ssp_device *ssp = priv->dev.ssp;
656 int dma = 0, chn = params_channels(params);
657 u32 sscr0;
658 u32 sspsp;
659 int width = snd_pcm_format_physical_width(params_format(params));
92429069 660 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf;
1b340bd7
MB		 661
662 /* select correct DMA params */
663 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
664 dma = 1; /* capture DMA offset is 1,3 */
92429069
PZ		 665 /* Network mode with one active slot (ttsa == 1) can be used
666 * to force 16-bit frame width on the wire (for S16_LE), even
667 * with two channels. Use 16-bit DMA transfers for this case.
668 */
669 if (((chn == 2) && (ttsa != 1)) || (width == 32))
670 dma += 2; /* 32-bit DMA offset is 2, 16-bit is 0 */
671
1b340bd7
MB		 672 cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma];
673
674 dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma);
675
676 /* we can only change the settings if the port is not in use */
677 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
678 return 0;
679
680 /* clear selected SSP bits */
681 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
682 ssp_write_reg(ssp, SSCR0, sscr0);
683
684 /* bit size */
685 sscr0 = ssp_read_reg(ssp, SSCR0);
686 switch (params_format(params)) {
687 case SNDRV_PCM_FORMAT_S16_LE:
688#ifdef CONFIG_PXA3xx
689 if (cpu_is_pxa3xx())
690 sscr0 |= SSCR0_FPCKE;
691#endif
692 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 693 break;
694 case SNDRV_PCM_FORMAT_S24_LE:
695 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 696 break;
697 case SNDRV_PCM_FORMAT_S32_LE:
698 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 699 break;
700 }
701 ssp_write_reg(ssp, SSCR0, sscr0);
702
703 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
704 case SND_SOC_DAIFMT_I2S:
72d74664
DM		 705 sspsp = ssp_read_reg(ssp, SSPSP);
706
1a297286 707 if ((ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 708 /* This is a special case where the bitclk is 64fs
709 * and we're not dealing with 2*32 bits of audio
710 * samples.
711 *
712 * The SSP values used for that are all found out by
713 * trying and failing a lot; some of the registers
714 * needed for that mode are only available on PXA3xx.
715 */
716
717#ifdef CONFIG_PXA3xx
718 if (!cpu_is_pxa3xx())
719 return -EINVAL;
720
721 sspsp |= SSPSP_SFRMWDTH(width * 2);
722 sspsp |= SSPSP_SFRMDLY(width * 4);
723 sspsp |= SSPSP_EDMYSTOP(3);
724 sspsp |= SSPSP_DMYSTOP(3);
725 sspsp |= SSPSP_DMYSTRT(1);
726#else
727 return -EINVAL;
728#endif
0ce36c5f
MB		 729 } else {
730 /* The frame width is the width the LRCLK is
731 * asserted for; the delay is expressed in
732 * half cycle units. We need the extra cycle
733 * because the data starts clocking out one BCLK
734 * after LRCLK changes polarity.
735 */
736 sspsp |= SSPSP_SFRMWDTH(width + 1);
737 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
738 sspsp |= SSPSP_DMYSTRT(1);
739 }
72d74664 740
1b340bd7
MB		 741 ssp_write_reg(ssp, SSPSP, sspsp);
742 break;
743 default:
744 break;
745 }
746
72d74664 747 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 748 * - complain loudly and fail if they've not been set up yet.
749 */
92429069 750 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 751 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
752 return -EINVAL;
753 }
754
755 dump_registers(ssp);
756
757 return 0;
758}
759
dee89c4d
MB		 760static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
761 struct snd_soc_dai *dai)
1b340bd7
MB		 762{
763 struct snd_soc_pcm_runtime *rtd = substream->private_data;
764 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
765 int ret = 0;
766 struct ssp_priv *priv = cpu_dai->private_data;
767 struct ssp_device *ssp = priv->dev.ssp;
768 int val;
769
770 switch (cmd) {
771 case SNDRV_PCM_TRIGGER_RESUME:
772 ssp_enable(&priv->dev);
773 break;
774 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
775 val = ssp_read_reg(ssp, SSCR1);
776 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
777 val |= SSCR1_TSRE;
778 else
779 val |= SSCR1_RSRE;
780 ssp_write_reg(ssp, SSCR1, val);
781 val = ssp_read_reg(ssp, SSSR);
782 ssp_write_reg(ssp, SSSR, val);
783 break;
784 case SNDRV_PCM_TRIGGER_START:
785 val = ssp_read_reg(ssp, SSCR1);
786 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
787 val |= SSCR1_TSRE;
788 else
789 val |= SSCR1_RSRE;
790 ssp_write_reg(ssp, SSCR1, val);
791 ssp_enable(&priv->dev);
792 break;
793 case SNDRV_PCM_TRIGGER_STOP:
794 val = ssp_read_reg(ssp, SSCR1);
795 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
796 val &= ~SSCR1_TSRE;
797 else
798 val &= ~SSCR1_RSRE;
799 ssp_write_reg(ssp, SSCR1, val);
800 break;
801 case SNDRV_PCM_TRIGGER_SUSPEND:
802 ssp_disable(&priv->dev);
803 break;
804 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
805 val = ssp_read_reg(ssp, SSCR1);
806 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
807 val &= ~SSCR1_TSRE;
808 else
809 val &= ~SSCR1_RSRE;
810 ssp_write_reg(ssp, SSCR1, val);
811 break;
812
813 default:
814 ret = -EINVAL;
815 }
816
817 dump_registers(ssp);
818
819 return ret;
820}
821
822static int pxa_ssp_probe(struct platform_device *pdev,
823 struct snd_soc_dai *dai)
824{
825 struct ssp_priv *priv;
826 int ret;
827
828 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
829 if (!priv)
830 return -ENOMEM;
831
0664678a 832 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio");
1b340bd7
MB		 833 if (priv->dev.ssp == NULL) {
834 ret = -ENODEV;
835 goto err_priv;
836 }
837
a5735b7e 838 priv->dai_fmt = (unsigned int) -1;
1b340bd7
MB		 839 dai->private_data = priv;
840
841 return 0;
842
843err_priv:
844 kfree(priv);
845 return ret;
846}
847
848static void pxa_ssp_remove(struct platform_device *pdev,
849 struct snd_soc_dai *dai)
850{
851 struct ssp_priv *priv = dai->private_data;
852 ssp_free(priv->dev.ssp);
853}
854
855#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
856 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
857 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
858 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
859
860#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
861 SNDRV_PCM_FMTBIT_S24_LE | \
862 SNDRV_PCM_FMTBIT_S32_LE)
863
6335d055
EM		 864static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
865 .startup = pxa_ssp_startup,
866 .shutdown = pxa_ssp_shutdown,
867 .trigger = pxa_ssp_trigger,
868 .hw_params = pxa_ssp_hw_params,
869 .set_sysclk = pxa_ssp_set_dai_sysclk,
870 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
871 .set_pll = pxa_ssp_set_dai_pll,
872 .set_fmt = pxa_ssp_set_dai_fmt,
873 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
874 .set_tristate = pxa_ssp_set_dai_tristate,
875};
876
1b340bd7
MB		 877struct snd_soc_dai pxa_ssp_dai[] = {
878 {
879 .name = "pxa2xx-ssp1",
880 .id = 0,
1b340bd7
MB		 881 .probe = pxa_ssp_probe,
882 .remove = pxa_ssp_remove,
883 .suspend = pxa_ssp_suspend,
884 .resume = pxa_ssp_resume,
885 .playback = {
886 .channels_min = 1,
887 .channels_max = 2,
888 .rates = PXA_SSP_RATES,
889 .formats = PXA_SSP_FORMATS,
890 },
891 .capture = {
892 .channels_min = 1,
893 .channels_max = 2,
894 .rates = PXA_SSP_RATES,
895 .formats = PXA_SSP_FORMATS,
896 },
6335d055 897 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 898 },
899 { .name = "pxa2xx-ssp2",
900 .id = 1,
1b340bd7
MB		 901 .probe = pxa_ssp_probe,
902 .remove = pxa_ssp_remove,
903 .suspend = pxa_ssp_suspend,
904 .resume = pxa_ssp_resume,
905 .playback = {
906 .channels_min = 1,
907 .channels_max = 2,
908 .rates = PXA_SSP_RATES,
909 .formats = PXA_SSP_FORMATS,
910 },
911 .capture = {
912 .channels_min = 1,
913 .channels_max = 2,
914 .rates = PXA_SSP_RATES,
915 .formats = PXA_SSP_FORMATS,
916 },
6335d055 917 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 918 },
919 {
920 .name = "pxa2xx-ssp3",
921 .id = 2,
1b340bd7
MB		 922 .probe = pxa_ssp_probe,
923 .remove = pxa_ssp_remove,
924 .suspend = pxa_ssp_suspend,
925 .resume = pxa_ssp_resume,
926 .playback = {
927 .channels_min = 1,
928 .channels_max = 2,
929 .rates = PXA_SSP_RATES,
930 .formats = PXA_SSP_FORMATS,
931 },
932 .capture = {
933 .channels_min = 1,
934 .channels_max = 2,
935 .rates = PXA_SSP_RATES,
936 .formats = PXA_SSP_FORMATS,
937 },
6335d055 938 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 939 },
940 {
941 .name = "pxa2xx-ssp4",
942 .id = 3,
1b340bd7
MB		 943 .probe = pxa_ssp_probe,
944 .remove = pxa_ssp_remove,
945 .suspend = pxa_ssp_suspend,
946 .resume = pxa_ssp_resume,
947 .playback = {
948 .channels_min = 1,
949 .channels_max = 2,
950 .rates = PXA_SSP_RATES,
951 .formats = PXA_SSP_FORMATS,
952 },
953 .capture = {
954 .channels_min = 1,
955 .channels_max = 2,
956 .rates = PXA_SSP_RATES,
957 .formats = PXA_SSP_FORMATS,
958 },
6335d055 959 .ops = &pxa_ssp_dai_ops,
1b340bd7
MB		 960 },
961};
962EXPORT_SYMBOL_GPL(pxa_ssp_dai);
963
c9b3a40f 964static int __init pxa_ssp_init(void)
3f4b783c
MB		 965{
966 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
967}
968module_init(pxa_ssp_init);
969
970static void __exit pxa_ssp_exit(void)
971{
972 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
973}
974module_exit(pxa_ssp_exit);
975
1b340bd7
MB		 976/* Module information */
977MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
978MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
979MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)