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ASoC: da7210: Minor improvements and a bugfix
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / pxa / pxa-ssp.c
CommitLineData
1b340bd7
MB		 1/*
2 * pxa-ssp.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * TODO:
14 * o Test network mode for > 16bit sample size
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
5a0e3ad6 19#include <linux/slab.h>
1b340bd7
MB		 20#include <linux/platform_device.h>
21#include <linux/clk.h>
22#include <linux/io.h>
8348c259 23#include <linux/pxa2xx_ssp.h>
1b340bd7 24
0664678a
PZ		 25#include <asm/irq.h>
26
1b340bd7
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/initval.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/pxa2xx-lib.h>
33
34#include <mach/hardware.h>
7ebc8d56 35#include <mach/dma.h>
1b340bd7 36#include <mach/audio.h>
1b340bd7 37
dd99a452 38#include "../../arm/pxa2xx-pcm.h"
1b340bd7
MB		 39#include "pxa-ssp.h"
40
41/*
42 * SSP audio private data
43 */
44struct ssp_priv {
f9efc9df 45 struct ssp_device *ssp;
1b340bd7
MB		 46 unsigned int sysclk;
47 int dai_fmt;
48#ifdef CONFIG_PM
f9efc9df
EM		 49 uint32_t cr0;
50 uint32_t cr1;
51 uint32_t to;
52 uint32_t psp;
1b340bd7
MB		 53#endif
54};
55
1b340bd7
MB		 56static void dump_registers(struct ssp_device *ssp)
57{
58 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
baffe169
HZ		 59 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
60 pxa_ssp_read_reg(ssp, SSTO));
1b340bd7
MB		 61
62 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
baffe169
HZ		 63 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
64 pxa_ssp_read_reg(ssp, SSACD));
1b340bd7
MB		 65}
66
baffe169 67static void pxa_ssp_enable(struct ssp_device *ssp)
f9efc9df
EM		 68{
69 uint32_t sscr0;
70
71 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
72 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
73}
74
baffe169 75static void pxa_ssp_disable(struct ssp_device *ssp)
f9efc9df
EM		 76{
77 uint32_t sscr0;
78
79 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
80 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
81}
82
2d7e71fa
EM		 83struct pxa2xx_pcm_dma_data {
84 struct pxa2xx_pcm_dma_params params;
85 char name[20];
1b340bd7
MB		 86};
87
2d7e71fa 88static struct pxa2xx_pcm_dma_params *
baffe169 89pxa_ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
2d7e71fa
EM		 90{
91 struct pxa2xx_pcm_dma_data *dma;
92
93 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
94 if (dma == NULL)
95 return NULL;
96
97 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
8eb9feab 98 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
2d7e71fa
EM		 99
100 dma->params.name = dma->name;
101 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
102 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
103 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
8eb9feab 104 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
2d7e71fa
EM		 105 dma->params.dev_addr = ssp->phys_base + SSDR;
106
107 return &dma->params;
108}
109
dee89c4d 110static int pxa_ssp_startup(struct snd_pcm_substream *substream,
f0fba2ad 111 struct snd_soc_dai *cpu_dai)
1b340bd7 112{
f0fba2ad 113 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 114 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 115 int ret = 0;
116
117 if (!cpu_dai->active) {
f9efc9df 118 clk_enable(ssp->clk);
baffe169 119 pxa_ssp_disable(ssp);
1b340bd7 120 }
2d7e71fa 121
5f712b2b
DM		 122 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
123 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
124
1b340bd7
MB		 125 return ret;
126}
127
dee89c4d 128static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
f0fba2ad 129 struct snd_soc_dai *cpu_dai)
1b340bd7 130{
f0fba2ad 131 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 132 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 133
134 if (!cpu_dai->active) {
baffe169 135 pxa_ssp_disable(ssp);
f9efc9df 136 clk_disable(ssp->clk);
1b340bd7 137 }
2d7e71fa 138
5f712b2b
DM		 139 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
140 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
1b340bd7
MB		 141}
142
143#ifdef CONFIG_PM
144
dc7d7b83 145static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
1b340bd7 146{
f0fba2ad 147 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 148 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 149
150 if (!cpu_dai->active)
988addf8 151 clk_enable(ssp->clk);
1b340bd7 152
f9efc9df
EM		 153 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
154 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
155 priv->to = __raw_readl(ssp->mmio_base + SSTO);
156 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
157
baffe169 158 pxa_ssp_disable(ssp);
f9efc9df 159 clk_disable(ssp->clk);
1b340bd7
MB		 160 return 0;
161}
162
dc7d7b83 163static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
1b340bd7 164{
f0fba2ad 165 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df
EM		 166 struct ssp_device *ssp = priv->ssp;
167 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
1b340bd7 168
f9efc9df
EM		 169 clk_enable(ssp->clk);
170
171 __raw_writel(sssr, ssp->mmio_base + SSSR);
f9efc9df
EM		 172 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
173 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
174 __raw_writel(priv->to, ssp->mmio_base + SSTO);
175 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
026384d6
DM		 176
177 if (cpu_dai->active)
baffe169 178 pxa_ssp_enable(ssp);
026384d6 179 else
988addf8 180 clk_disable(ssp->clk);
1b340bd7
MB		 181
182 return 0;
183}
184
185#else
186#define pxa_ssp_suspend NULL
187#define pxa_ssp_resume NULL
188#endif
189
190/**
191 * ssp_set_clkdiv - set SSP clock divider
192 * @div: serial clock rate divider
193 */
baffe169 194static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
1b340bd7 195{
baffe169 196 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
1a297286
PZ		 197
198 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
199 sscr0 &= ~0x0000ff00;
200 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
201 } else {
202 sscr0 &= ~0x000fff00;
203 sscr0 |= (div - 1) << 8; /* 1..4096 */
204 }
baffe169 205 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1a297286
PZ		 206}
207
208/**
baffe169 209 * pxa_ssp_get_clkdiv - get SSP clock divider
1a297286 210 */
baffe169 211static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
1a297286 212{
baffe169 213 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
1a297286 214 u32 div;
1b340bd7 215
1a297286
PZ		 216 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
217 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
218 else
219 div = ((sscr0 >> 8) & 0xfff) + 1;
220 return div;
1b340bd7
MB		 221}
222
223/*
224 * Set the SSP ports SYSCLK.
225 */
226static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
227 int clk_id, unsigned int freq, int dir)
228{
f0fba2ad 229 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 230 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 231 int val;
232
baffe169 233 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
20a41eac 234 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 235
236 dev_dbg(&ssp->pdev->dev,
449bd54d 237 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
1b340bd7
MB		 238 cpu_dai->id, clk_id, freq);
239
240 switch (clk_id) {
241 case PXA_SSP_CLK_NET_PLL:
242 sscr0 |= SSCR0_MOD;
243 break;
244 case PXA_SSP_CLK_PLL:
245 /* Internal PLL is fixed */
246 if (cpu_is_pxa25x())
247 priv->sysclk = 1843200;
248 else
249 priv->sysclk = 13000000;
250 break;
251 case PXA_SSP_CLK_EXT:
252 priv->sysclk = freq;
253 sscr0 |= SSCR0_ECS;
254 break;
255 case PXA_SSP_CLK_NET:
256 priv->sysclk = freq;
257 sscr0 |= SSCR0_NCS | SSCR0_MOD;
258 break;
259 case PXA_SSP_CLK_AUDIO:
260 priv->sysclk = 0;
baffe169 261 pxa_ssp_set_scr(ssp, 1);
20a41eac 262 sscr0 |= SSCR0_ACS;
1b340bd7
MB		 263 break;
264 default:
265 return -ENODEV;
266 }
267
268 /* The SSP clock must be disabled when changing SSP clock mode
269 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
270 if (!cpu_is_pxa3xx())
f9efc9df 271 clk_disable(ssp->clk);
baffe169
HZ		 272 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
273 pxa_ssp_write_reg(ssp, SSCR0, val);
1b340bd7 274 if (!cpu_is_pxa3xx())
f9efc9df 275 clk_enable(ssp->clk);
1b340bd7
MB		 276
277 return 0;
278}
279
280/*
281 * Set the SSP clock dividers.
282 */
283static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
284 int div_id, int div)
285{
f0fba2ad 286 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 287 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 288 int val;
289
290 switch (div_id) {
291 case PXA_SSP_AUDIO_DIV_ACDS:
baffe169
HZ		 292 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
293 pxa_ssp_write_reg(ssp, SSACD, val);
1b340bd7
MB		 294 break;
295 case PXA_SSP_AUDIO_DIV_SCDB:
baffe169 296 val = pxa_ssp_read_reg(ssp, SSACD);
1b340bd7
MB		 297 val &= ~SSACD_SCDB;
298#if defined(CONFIG_PXA3xx)
299 if (cpu_is_pxa3xx())
300 val &= ~SSACD_SCDX8;
301#endif
302 switch (div) {
303 case PXA_SSP_CLK_SCDB_1:
304 val |= SSACD_SCDB;
305 break;
306 case PXA_SSP_CLK_SCDB_4:
307 break;
308#if defined(CONFIG_PXA3xx)
309 case PXA_SSP_CLK_SCDB_8:
310 if (cpu_is_pxa3xx())
311 val |= SSACD_SCDX8;
312 else
313 return -EINVAL;
314 break;
315#endif
316 default:
317 return -EINVAL;
318 }
baffe169 319 pxa_ssp_write_reg(ssp, SSACD, val);
1b340bd7
MB		 320 break;
321 case PXA_SSP_DIV_SCR:
baffe169 322 pxa_ssp_set_scr(ssp, div);
1b340bd7
MB		 323 break;
324 default:
325 return -ENODEV;
326 }
327
328 return 0;
329}
330
331/*
332 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
333 */
85488037
MB		 334static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
335 int source, unsigned int freq_in, unsigned int freq_out)
1b340bd7 336{
f0fba2ad 337 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 338 struct ssp_device *ssp = priv->ssp;
baffe169 339 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
1b340bd7
MB		 340
341#if defined(CONFIG_PXA3xx)
342 if (cpu_is_pxa3xx())
baffe169 343 pxa_ssp_write_reg(ssp, SSACDD, 0);
1b340bd7
MB		 344#endif
345
346 switch (freq_out) {
347 case 5622000:
348 break;
349 case 11345000:
350 ssacd |= (0x1 << 4);
351 break;
352 case 12235000:
353 ssacd |= (0x2 << 4);
354 break;
355 case 14857000:
356 ssacd |= (0x3 << 4);
357 break;
358 case 32842000:
359 ssacd |= (0x4 << 4);
360 break;
361 case 48000000:
362 ssacd |= (0x5 << 4);
363 break;
364 case 0:
365 /* Disable */
366 break;
367
368 default:
369#ifdef CONFIG_PXA3xx
370 /* PXA3xx has a clock ditherer which can be used to generate
371 * a wider range of frequencies - calculate a value for it.
372 */
373 if (cpu_is_pxa3xx()) {
374 u32 val;
375 u64 tmp = 19968;
376 tmp *= 1000000;
377 do_div(tmp, freq_out);
378 val = tmp;
379
a419aef8 380 val = (val << 16) | 64;
baffe169 381 pxa_ssp_write_reg(ssp, SSACDD, val);
1b340bd7
MB		 382
383 ssacd |= (0x6 << 4);
384
385 dev_dbg(&ssp->pdev->dev,
449bd54d 386 "Using SSACDD %x to supply %uHz\n",
1b340bd7
MB		 387 val, freq_out);
388 break;
389 }
390#endif
391
392 return -EINVAL;
393 }
394
baffe169 395 pxa_ssp_write_reg(ssp, SSACD, ssacd);
1b340bd7
MB		 396
397 return 0;
398}
399
400/*
401 * Set the active slots in TDM/Network mode
402 */
403static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
a5479e38 404 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1b340bd7 405{
f0fba2ad 406 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 407 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 408 u32 sscr0;
409
baffe169 410 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
a5479e38 411 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
1b340bd7 412
a5479e38
DR		 413 /* set slot width */
414 if (slot_width > 16)
415 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
416 else
417 sscr0 |= SSCR0_DataSize(slot_width);
418
419 if (slots > 1) {
420 /* enable network mode */
421 sscr0 |= SSCR0_MOD;
422
423 /* set number of active slots */
424 sscr0 |= SSCR0_SlotsPerFrm(slots);
425
426 /* set active slot mask */
baffe169
HZ		 427 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
428 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
a5479e38 429 }
baffe169 430 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1b340bd7 431
1b340bd7
MB		 432 return 0;
433}
434
435/*
436 * Tristate the SSP DAI lines
437 */
438static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
439 int tristate)
440{
f0fba2ad 441 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 442 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 443 u32 sscr1;
444
baffe169 445 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
1b340bd7
MB		 446 if (tristate)
447 sscr1 &= ~SSCR1_TTE;
448 else
449 sscr1 |= SSCR1_TTE;
baffe169 450 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
1b340bd7
MB		 451
452 return 0;
453}
454
455/*
456 * Set up the SSP DAI format.
457 * The SSP Port must be inactive before calling this function as the
458 * physical interface format is changed.
459 */
460static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
461 unsigned int fmt)
462{
f0fba2ad 463 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 464 struct ssp_device *ssp = priv->ssp;
f5d1e5ed 465 u32 sscr0, sscr1, sspsp, scfr;
1b340bd7 466
cbf1146d
DM		 467 /* check if we need to change anything at all */
468 if (priv->dai_fmt == fmt)
469 return 0;
470
471 /* we can only change the settings if the port is not in use */
baffe169 472 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
cbf1146d
DM		 473 dev_err(&ssp->pdev->dev,
474 "can't change hardware dai format: stream is in use");
475 return -EINVAL;
476 }
477
1b340bd7 478 /* reset port settings */
baffe169 479 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
f5d1e5ed 480 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
1b340bd7
MB		 481 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
482 sspsp = 0;
483
484 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
485 case SND_SOC_DAIFMT_CBM_CFM:
f5d1e5ed 486 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
1b340bd7
MB		 487 break;
488 case SND_SOC_DAIFMT_CBM_CFS:
f5d1e5ed 489 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
1b340bd7
MB		 490 break;
491 case SND_SOC_DAIFMT_CBS_CFS:
492 break;
493 default:
494 return -EINVAL;
495 }
496
fa44c077
DR		 497 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
498 case SND_SOC_DAIFMT_NB_NF:
499 sspsp |= SSPSP_SFRMP;
500 break;
501 case SND_SOC_DAIFMT_NB_IF:
502 break;
503 case SND_SOC_DAIFMT_IB_IF:
504 sspsp |= SSPSP_SCMODE(2);
505 break;
506 case SND_SOC_DAIFMT_IB_NF:
507 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
508 break;
509 default:
510 return -EINVAL;
511 }
1b340bd7
MB		 512
513 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
514 case SND_SOC_DAIFMT_I2S:
72d74664 515 sscr0 |= SSCR0_PSP;
1b340bd7 516 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
0ce36c5f 517 /* See hw_params() */
1b340bd7
MB		 518 break;
519
520 case SND_SOC_DAIFMT_DSP_A:
521 sspsp |= SSPSP_FSRT;
522 case SND_SOC_DAIFMT_DSP_B:
523 sscr0 |= SSCR0_MOD | SSCR0_PSP;
524 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
1b340bd7
MB		 525 break;
526
527 default:
528 return -EINVAL;
529 }
530
baffe169
HZ		 531 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
532 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
533 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
1b340bd7 534
f5d1e5ed
HZ		 535 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
536 case SND_SOC_DAIFMT_CBM_CFM:
537 case SND_SOC_DAIFMT_CBM_CFS:
538 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
539 pxa_ssp_write_reg(ssp, SSCR1, scfr);
540
541 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
542 cpu_relax();
543 break;
544 }
545
1b340bd7
MB		 546 dump_registers(ssp);
547
548 /* Since we are configuring the timings for the format by hand
549 * we have to defer some things until hw_params() where we
550 * know parameters like the sample size.
551 */
552 priv->dai_fmt = fmt;
553
554 return 0;
555}
556
557/*
558 * Set the SSP audio DMA parameters and sample size.
559 * Can be called multiple times by oss emulation.
560 */
561static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
dee89c4d 562 struct snd_pcm_hw_params *params,
f0fba2ad 563 struct snd_soc_dai *cpu_dai)
1b340bd7 564{
f0fba2ad 565 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 566 struct ssp_device *ssp = priv->ssp;
2d7e71fa 567 int chn = params_channels(params);
1b340bd7
MB		 568 u32 sscr0;
569 u32 sspsp;
570 int width = snd_pcm_format_physical_width(params_format(params));
baffe169 571 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
5f712b2b
DM		 572 struct pxa2xx_pcm_dma_params *dma_data;
573
f0fba2ad 574 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
1b340bd7 575
2d7e71fa 576 /* generate correct DMA params */
5f712b2b 577 kfree(dma_data);
2d7e71fa 578
92429069
PZ		 579 /* Network mode with one active slot (ttsa == 1) can be used
580 * to force 16-bit frame width on the wire (for S16_LE), even
581 * with two channels. Use 16-bit DMA transfers for this case.
582 */
baffe169 583 dma_data = pxa_ssp_get_dma_params(ssp,
2d7e71fa
EM		 584 ((chn == 2) && (ttsa != 1)) || (width == 32),
585 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1b340bd7 586
f0fba2ad 587 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
5f712b2b 588
1b340bd7 589 /* we can only change the settings if the port is not in use */
baffe169 590 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
1b340bd7
MB		 591 return 0;
592
593 /* clear selected SSP bits */
baffe169 594 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
1b340bd7
MB		 595
596 /* bit size */
1b340bd7
MB		 597 switch (params_format(params)) {
598 case SNDRV_PCM_FORMAT_S16_LE:
599#ifdef CONFIG_PXA3xx
600 if (cpu_is_pxa3xx())
601 sscr0 |= SSCR0_FPCKE;
602#endif
603 sscr0 |= SSCR0_DataSize(16);
1b340bd7
MB		 604 break;
605 case SNDRV_PCM_FORMAT_S24_LE:
606 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
1b340bd7
MB		 607 break;
608 case SNDRV_PCM_FORMAT_S32_LE:
609 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
1b340bd7
MB		 610 break;
611 }
baffe169 612 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
1b340bd7
MB		 613
614 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
615 case SND_SOC_DAIFMT_I2S:
baffe169 616 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
72d74664 617
baffe169 618 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
72d74664
DM		 619 /* This is a special case where the bitclk is 64fs
620 * and we're not dealing with 2*32 bits of audio
621 * samples.
622 *
623 * The SSP values used for that are all found out by
624 * trying and failing a lot; some of the registers
625 * needed for that mode are only available on PXA3xx.
626 */
627
628#ifdef CONFIG_PXA3xx
629 if (!cpu_is_pxa3xx())
630 return -EINVAL;
631
632 sspsp |= SSPSP_SFRMWDTH(width * 2);
633 sspsp |= SSPSP_SFRMDLY(width * 4);
634 sspsp |= SSPSP_EDMYSTOP(3);
635 sspsp |= SSPSP_DMYSTOP(3);
636 sspsp |= SSPSP_DMYSTRT(1);
637#else
638 return -EINVAL;
639#endif
0ce36c5f
MB		 640 } else {
641 /* The frame width is the width the LRCLK is
642 * asserted for; the delay is expressed in
643 * half cycle units. We need the extra cycle
644 * because the data starts clocking out one BCLK
645 * after LRCLK changes polarity.
646 */
647 sspsp |= SSPSP_SFRMWDTH(width + 1);
648 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
649 sspsp |= SSPSP_DMYSTRT(1);
650 }
72d74664 651
baffe169 652 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
1b340bd7
MB		 653 break;
654 default:
655 break;
656 }
657
72d74664 658 /* When we use a network mode, we always require TDM slots
1b340bd7
MB		 659 * - complain loudly and fail if they've not been set up yet.
660 */
92429069 661 if ((sscr0 & SSCR0_MOD) && !ttsa) {
1b340bd7
MB		 662 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
663 return -EINVAL;
664 }
665
666 dump_registers(ssp);
667
668 return 0;
669}
670
273b72c8
DM		 671static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
672 struct ssp_device *ssp, int value)
673{
674 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
675 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
676 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
677 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
678
679 if (value && (sscr0 & SSCR0_SSE))
680 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
681
682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
683 if (value)
684 sscr1 |= SSCR1_TSRE;
685 else
686 sscr1 &= ~SSCR1_TSRE;
687 } else {
688 if (value)
689 sscr1 |= SSCR1_RSRE;
690 else
691 sscr1 &= ~SSCR1_RSRE;
692 }
693
694 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
695
696 if (value) {
697 pxa_ssp_write_reg(ssp, SSSR, sssr);
698 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
699 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
700 }
701}
702
dee89c4d 703static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
f0fba2ad 704 struct snd_soc_dai *cpu_dai)
1b340bd7 705{
1b340bd7 706 int ret = 0;
f0fba2ad 707 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
f9efc9df 708 struct ssp_device *ssp = priv->ssp;
1b340bd7
MB		 709 int val;
710
711 switch (cmd) {
712 case SNDRV_PCM_TRIGGER_RESUME:
baffe169 713 pxa_ssp_enable(ssp);
1b340bd7
MB		 714 break;
715 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
273b72c8 716 pxa_ssp_set_running_bit(substream, ssp, 1);
baffe169
HZ		 717 val = pxa_ssp_read_reg(ssp, SSSR);
718 pxa_ssp_write_reg(ssp, SSSR, val);
1b340bd7
MB		 719 break;
720 case SNDRV_PCM_TRIGGER_START:
273b72c8 721 pxa_ssp_set_running_bit(substream, ssp, 1);
1b340bd7
MB		 722 break;
723 case SNDRV_PCM_TRIGGER_STOP:
273b72c8 724 pxa_ssp_set_running_bit(substream, ssp, 0);
1b340bd7
MB		 725 break;
726 case SNDRV_PCM_TRIGGER_SUSPEND:
baffe169 727 pxa_ssp_disable(ssp);
1b340bd7
MB		 728 break;
729 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
273b72c8 730 pxa_ssp_set_running_bit(substream, ssp, 0);
1b340bd7
MB		 731 break;
732
733 default:
734 ret = -EINVAL;
735 }
736
737 dump_registers(ssp);
738
739 return ret;
740}
741
f0fba2ad 742static int pxa_ssp_probe(struct snd_soc_dai *dai)
1b340bd7
MB		 743{
744 struct ssp_priv *priv;
745 int ret;
746
747 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
748 if (!priv)
749 return -ENOMEM;
750
baffe169 751 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
f9efc9df 752 if (priv->ssp == NULL) {
1b340bd7
MB		 753 ret = -ENODEV;
754 goto err_priv;
755 }
756
a5735b7e 757 priv->dai_fmt = (unsigned int) -1;
f0fba2ad 758 snd_soc_dai_set_drvdata(dai, priv);
1b340bd7
MB		 759
760 return 0;
761
762err_priv:
763 kfree(priv);
764 return ret;
765}
766
f0fba2ad 767static int pxa_ssp_remove(struct snd_soc_dai *dai)
1b340bd7 768{
f0fba2ad
LG		 769 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
770
baffe169 771 pxa_ssp_free(priv->ssp);
014a2755 772 kfree(priv);
f0fba2ad 773 return 0;
1b340bd7
MB		 774}
775
776#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
777 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
8d8bf58b
QZ		 778 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
779 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
1b340bd7
MB		 780 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
781
782#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
783 SNDRV_PCM_FMTBIT_S24_LE | \
784 SNDRV_PCM_FMTBIT_S32_LE)
785
85e7652d 786static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
6335d055
EM		 787 .startup = pxa_ssp_startup,
788 .shutdown = pxa_ssp_shutdown,
789 .trigger = pxa_ssp_trigger,
790 .hw_params = pxa_ssp_hw_params,
791 .set_sysclk = pxa_ssp_set_dai_sysclk,
792 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
793 .set_pll = pxa_ssp_set_dai_pll,
794 .set_fmt = pxa_ssp_set_dai_fmt,
795 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
796 .set_tristate = pxa_ssp_set_dai_tristate,
797};
798
f0fba2ad 799static struct snd_soc_dai_driver pxa_ssp_dai = {
1b340bd7
MB		 800 .probe = pxa_ssp_probe,
801 .remove = pxa_ssp_remove,
802 .suspend = pxa_ssp_suspend,
803 .resume = pxa_ssp_resume,
804 .playback = {
805 .channels_min = 1,
f34762b6 806 .channels_max = 8,
1b340bd7
MB		 807 .rates = PXA_SSP_RATES,
808 .formats = PXA_SSP_FORMATS,
809 },
810 .capture = {
811 .channels_min = 1,
f34762b6 812 .channels_max = 8,
1b340bd7
MB		 813 .rates = PXA_SSP_RATES,
814 .formats = PXA_SSP_FORMATS,
815 },
6335d055 816 .ops = &pxa_ssp_dai_ops,
f0fba2ad
LG		 817};
818
819static __devinit int asoc_ssp_probe(struct platform_device *pdev)
820{
821 return snd_soc_register_dai(&pdev->dev, &pxa_ssp_dai);
822}
823
824static int __devexit asoc_ssp_remove(struct platform_device *pdev)
825{
826 snd_soc_unregister_dai(&pdev->dev);
827 return 0;
828}
829
830static struct platform_driver asoc_ssp_driver = {
831 .driver = {
832 .name = "pxa-ssp-dai",
833 .owner = THIS_MODULE,
1b340bd7 834 },
f0fba2ad
LG		 835
836 .probe = asoc_ssp_probe,
837 .remove = __devexit_p(asoc_ssp_remove),
1b340bd7 838};
1b340bd7 839
2f702a19 840module_platform_driver(asoc_ssp_driver);
3f4b783c 841
1b340bd7
MB		 842/* Module information */
843MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
844MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
845MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)