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iommu/amd: Implement function to send PPR completions
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / iommu / amd_iommu.c
CommitLineData
b6c02715 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
b6c02715
JR		 3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
72e1dcc4 20#include <linux/ratelimit.h>
b6c02715 21#include <linux/pci.h>
cb41ed85 22#include <linux/pci-ats.h>
a66022c4 23#include <linux/bitmap.h>
5a0e3ad6 24#include <linux/slab.h>
7f26508b 25#include <linux/debugfs.h>
b6c02715 26#include <linux/scatterlist.h>
51491367 27#include <linux/dma-mapping.h>
b6c02715 28#include <linux/iommu-helper.h>
c156e347 29#include <linux/iommu.h>
815b33fd 30#include <linux/delay.h>
403f81d8 31#include <linux/amd-iommu.h>
72e1dcc4
JR		 32#include <linux/notifier.h>
33#include <linux/export.h>
17f5b569 34#include <asm/msidef.h>
b6c02715 35#include <asm/proto.h>
46a7fa27 36#include <asm/iommu.h>
1d9b16d1 37#include <asm/gart.h>
27c2127a 38#include <asm/dma.h>
403f81d8
JR		 39
40#include "amd_iommu_proto.h"
41#include "amd_iommu_types.h"
b6c02715
JR		 42
43#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
44
815b33fd 45#define LOOP_TIMEOUT 100000
136f78a1 46
b6c02715
JR		 47static DEFINE_RWLOCK(amd_iommu_devtable_lock);
48
bd60b735
JR		 49/* A list of preallocated protection domains */
50static LIST_HEAD(iommu_pd_list);
51static DEFINE_SPINLOCK(iommu_pd_list_lock);
52
8fa5f802
JR		 53/* List of all available dev_data structures */
54static LIST_HEAD(dev_data_list);
55static DEFINE_SPINLOCK(dev_data_list_lock);
56
0feae533
JR		 57/*
58 * Domain for untranslated devices - only allocated
59 * if iommu=pt passed on kernel cmd line.
60 */
61static struct protection_domain *pt_domain;
62
26961efe 63static struct iommu_ops amd_iommu_ops;
26961efe 64
72e1dcc4 65static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
52815b75 66int amd_iommu_max_glx_val = -1;
72e1dcc4 67
431b2a20
JR		 68/*
69 * general struct to manage commands send to an IOMMU
70 */
d6449536 71struct iommu_cmd {
b6c02715
JR		 72 u32 data[4];
73};
74
04bfdd84 75static void update_domain(struct protection_domain *domain);
5abcdba4 76static int __init alloc_passthrough_domain(void);
c1eee67b 77
15898bbc
JR		 78/****************************************************************************
79 *
80 * Helper functions
81 *
82 ****************************************************************************/
83
f62dda66 84static struct iommu_dev_data *alloc_dev_data(u16 devid)
8fa5f802
JR		 85{
86 struct iommu_dev_data *dev_data;
87 unsigned long flags;
88
89 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
90 if (!dev_data)
91 return NULL;
92
f62dda66 93 dev_data->devid = devid;
8fa5f802
JR		 94 atomic_set(&dev_data->bind, 0);
95
96 spin_lock_irqsave(&dev_data_list_lock, flags);
97 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
98 spin_unlock_irqrestore(&dev_data_list_lock, flags);
99
100 return dev_data;
101}
102
103static void free_dev_data(struct iommu_dev_data *dev_data)
104{
105 unsigned long flags;
106
107 spin_lock_irqsave(&dev_data_list_lock, flags);
108 list_del(&dev_data->dev_data_list);
109 spin_unlock_irqrestore(&dev_data_list_lock, flags);
110
111 kfree(dev_data);
112}
113
3b03bb74
JR		 114static struct iommu_dev_data *search_dev_data(u16 devid)
115{
116 struct iommu_dev_data *dev_data;
117 unsigned long flags;
118
119 spin_lock_irqsave(&dev_data_list_lock, flags);
120 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
121 if (dev_data->devid == devid)
122 goto out_unlock;
123 }
124
125 dev_data = NULL;
126
127out_unlock:
128 spin_unlock_irqrestore(&dev_data_list_lock, flags);
129
130 return dev_data;
131}
132
133static struct iommu_dev_data *find_dev_data(u16 devid)
134{
135 struct iommu_dev_data *dev_data;
136
137 dev_data = search_dev_data(devid);
138
139 if (dev_data == NULL)
140 dev_data = alloc_dev_data(devid);
141
142 return dev_data;
143}
144
15898bbc
JR		 145static inline u16 get_device_id(struct device *dev)
146{
147 struct pci_dev *pdev = to_pci_dev(dev);
148
149 return calc_devid(pdev->bus->number, pdev->devfn);
150}
151
657cbb6b
JR		 152static struct iommu_dev_data *get_dev_data(struct device *dev)
153{
154 return dev->archdata.iommu;
155}
156
5abcdba4
JR		 157static bool pci_iommuv2_capable(struct pci_dev *pdev)
158{
159 static const int caps[] = {
160 PCI_EXT_CAP_ID_ATS,
161 PCI_PRI_CAP,
162 PCI_PASID_CAP,
163 };
164 int i, pos;
165
166 for (i = 0; i < 3; ++i) {
167 pos = pci_find_ext_capability(pdev, caps[i]);
168 if (pos == 0)
169 return false;
170 }
171
172 return true;
173}
174
71c70984
JR		 175/*
176 * In this function the list of preallocated protection domains is traversed to
177 * find the domain for a specific device
178 */
179static struct dma_ops_domain *find_protection_domain(u16 devid)
180{
181 struct dma_ops_domain *entry, *ret = NULL;
182 unsigned long flags;
183 u16 alias = amd_iommu_alias_table[devid];
184
185 if (list_empty(&iommu_pd_list))
186 return NULL;
187
188 spin_lock_irqsave(&iommu_pd_list_lock, flags);
189
190 list_for_each_entry(entry, &iommu_pd_list, list) {
191 if (entry->target_dev == devid ||
192 entry->target_dev == alias) {
193 ret = entry;
194 break;
195 }
196 }
197
198 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
199
200 return ret;
201}
202
98fc5a69
JR		 203/*
204 * This function checks if the driver got a valid device from the caller to
205 * avoid dereferencing invalid pointers.
206 */
207static bool check_device(struct device *dev)
208{
209 u16 devid;
210
211 if (!dev || !dev->dma_mask)
212 return false;
213
214 /* No device or no PCI device */
339d3261 215 if (dev->bus != &pci_bus_type)
98fc5a69
JR		 216 return false;
217
218 devid = get_device_id(dev);
219
220 /* Out of our scope? */
221 if (devid > amd_iommu_last_bdf)
222 return false;
223
224 if (amd_iommu_rlookup_table[devid] == NULL)
225 return false;
226
227 return true;
228}
229
657cbb6b
JR		 230static int iommu_init_device(struct device *dev)
231{
5abcdba4 232 struct pci_dev *pdev = to_pci_dev(dev);
657cbb6b 233 struct iommu_dev_data *dev_data;
8fa5f802 234 u16 alias;
657cbb6b
JR		 235
236 if (dev->archdata.iommu)
237 return 0;
238
3b03bb74 239 dev_data = find_dev_data(get_device_id(dev));
657cbb6b
JR		 240 if (!dev_data)
241 return -ENOMEM;
242
f62dda66 243 alias = amd_iommu_alias_table[dev_data->devid];
2b02b091 244 if (alias != dev_data->devid) {
71f77580 245 struct iommu_dev_data *alias_data;
b00d3bcf 246
71f77580
JR		 247 alias_data = find_dev_data(alias);
248 if (alias_data == NULL) {
249 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
250 dev_name(dev));
2b02b091
JR		 251 free_dev_data(dev_data);
252 return -ENOTSUPP;
253 }
71f77580 254 dev_data->alias_data = alias_data;
26018874 255 }
657cbb6b 256
5abcdba4
JR		 257 if (pci_iommuv2_capable(pdev)) {
258 struct amd_iommu *iommu;
259
260 iommu = amd_iommu_rlookup_table[dev_data->devid];
261 dev_data->iommu_v2 = iommu->is_iommu_v2;
262 }
263
657cbb6b
JR		 264 dev->archdata.iommu = dev_data;
265
657cbb6b
JR		 266 return 0;
267}
268
26018874
JR		 269static void iommu_ignore_device(struct device *dev)
270{
271 u16 devid, alias;
272
273 devid = get_device_id(dev);
274 alias = amd_iommu_alias_table[devid];
275
276 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
277 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
278
279 amd_iommu_rlookup_table[devid] = NULL;
280 amd_iommu_rlookup_table[alias] = NULL;
281}
282
657cbb6b
JR		 283static void iommu_uninit_device(struct device *dev)
284{
8fa5f802
JR		 285 /*
286 * Nothing to do here - we keep dev_data around for unplugged devices
287 * and reuse it when the device is re-plugged - not doing so would
288 * introduce a ton of races.
289 */
657cbb6b 290}
b7cc9554
JR		 291
292void __init amd_iommu_uninit_devices(void)
293{
8fa5f802 294 struct iommu_dev_data *dev_data, *n;
b7cc9554
JR		 295 struct pci_dev *pdev = NULL;
296
297 for_each_pci_dev(pdev) {
298
299 if (!check_device(&pdev->dev))
300 continue;
301
302 iommu_uninit_device(&pdev->dev);
303 }
8fa5f802
JR		 304
305 /* Free all of our dev_data structures */
306 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
307 free_dev_data(dev_data);
b7cc9554
JR		 308}
309
310int __init amd_iommu_init_devices(void)
311{
312 struct pci_dev *pdev = NULL;
313 int ret = 0;
314
315 for_each_pci_dev(pdev) {
316
317 if (!check_device(&pdev->dev))
318 continue;
319
320 ret = iommu_init_device(&pdev->dev);
26018874
JR		 321 if (ret == -ENOTSUPP)
322 iommu_ignore_device(&pdev->dev);
323 else if (ret)
b7cc9554
JR		 324 goto out_free;
325 }
326
327 return 0;
328
329out_free:
330
331 amd_iommu_uninit_devices();
332
333 return ret;
334}
7f26508b
JR		 335#ifdef CONFIG_AMD_IOMMU_STATS
336
337/*
338 * Initialization code for statistics collection
339 */
340
da49f6df 341DECLARE_STATS_COUNTER(compl_wait);
0f2a86f2 342DECLARE_STATS_COUNTER(cnt_map_single);
146a6917 343DECLARE_STATS_COUNTER(cnt_unmap_single);
d03f067a 344DECLARE_STATS_COUNTER(cnt_map_sg);
55877a6b 345DECLARE_STATS_COUNTER(cnt_unmap_sg);
c8f0fb36 346DECLARE_STATS_COUNTER(cnt_alloc_coherent);
5d31ee7e 347DECLARE_STATS_COUNTER(cnt_free_coherent);
c1858976 348DECLARE_STATS_COUNTER(cross_page);
f57d98ae 349DECLARE_STATS_COUNTER(domain_flush_single);
18811f55 350DECLARE_STATS_COUNTER(domain_flush_all);
5774f7c5 351DECLARE_STATS_COUNTER(alloced_io_mem);
8ecaf8f1 352DECLARE_STATS_COUNTER(total_map_requests);
da49f6df 353
7f26508b 354static struct dentry *stats_dir;
7f26508b
JR		 355static struct dentry *de_fflush;
356
357static void amd_iommu_stats_add(struct __iommu_counter *cnt)
358{
359 if (stats_dir == NULL)
360 return;
361
362 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
363 &cnt->value);
364}
365
366static void amd_iommu_stats_init(void)
367{
368 stats_dir = debugfs_create_dir("amd-iommu", NULL);
369 if (stats_dir == NULL)
370 return;
371
7f26508b
JR		 372 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
373 (u32 *)&amd_iommu_unmap_flush);
da49f6df
JR		 374
375 amd_iommu_stats_add(&compl_wait);
0f2a86f2 376 amd_iommu_stats_add(&cnt_map_single);
146a6917 377 amd_iommu_stats_add(&cnt_unmap_single);
d03f067a 378 amd_iommu_stats_add(&cnt_map_sg);
55877a6b 379 amd_iommu_stats_add(&cnt_unmap_sg);
c8f0fb36 380 amd_iommu_stats_add(&cnt_alloc_coherent);
5d31ee7e 381 amd_iommu_stats_add(&cnt_free_coherent);
c1858976 382 amd_iommu_stats_add(&cross_page);
f57d98ae 383 amd_iommu_stats_add(&domain_flush_single);
18811f55 384 amd_iommu_stats_add(&domain_flush_all);
5774f7c5 385 amd_iommu_stats_add(&alloced_io_mem);
8ecaf8f1 386 amd_iommu_stats_add(&total_map_requests);
7f26508b
JR		 387}
388
389#endif
390
a80dc3e0
JR		 391/****************************************************************************
392 *
393 * Interrupt handling functions
394 *
395 ****************************************************************************/
396
e3e59876
JR		 397static void dump_dte_entry(u16 devid)
398{
399 int i;
400
ee6c2868
JR		 401 for (i = 0; i < 4; ++i)
402 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
e3e59876
JR		 403 amd_iommu_dev_table[devid].data[i]);
404}
405
945b4ac4
JR		 406static void dump_command(unsigned long phys_addr)
407{
408 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
409 int i;
410
411 for (i = 0; i < 4; ++i)
412 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
413}
414
a345b23b 415static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
90008ee4
JR		 416{
417 u32 *event = __evt;
418 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
419 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
420 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
421 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
422 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
423
4c6f40d4 424 printk(KERN_ERR "AMD-Vi: Event logged [");
90008ee4
JR		 425
426 switch (type) {
427 case EVENT_TYPE_ILL_DEV:
428 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
429 "address=0x%016llx flags=0x%04x]\n",
430 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
431 address, flags);
e3e59876 432 dump_dte_entry(devid);
90008ee4
JR		 433 break;
434 case EVENT_TYPE_IO_FAULT:
435 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
436 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
437 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
438 domid, address, flags);
439 break;
440 case EVENT_TYPE_DEV_TAB_ERR:
441 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
442 "address=0x%016llx flags=0x%04x]\n",
443 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
444 address, flags);
445 break;
446 case EVENT_TYPE_PAGE_TAB_ERR:
447 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
448 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
449 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
450 domid, address, flags);
451 break;
452 case EVENT_TYPE_ILL_CMD:
453 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
945b4ac4 454 dump_command(address);
90008ee4
JR		 455 break;
456 case EVENT_TYPE_CMD_HARD_ERR:
457 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
458 "flags=0x%04x]\n", address, flags);
459 break;
460 case EVENT_TYPE_IOTLB_INV_TO:
461 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
462 "address=0x%016llx]\n",
463 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
464 address);
465 break;
466 case EVENT_TYPE_INV_DEV_REQ:
467 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
468 "address=0x%016llx flags=0x%04x]\n",
469 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
470 address, flags);
471 break;
472 default:
473 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
474 }
475}
476
477static void iommu_poll_events(struct amd_iommu *iommu)
478{
479 u32 head, tail;
480 unsigned long flags;
481
482 spin_lock_irqsave(&iommu->lock, flags);
483
484 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
485 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
486
487 while (head != tail) {
a345b23b 488 iommu_print_event(iommu, iommu->evt_buf + head);
90008ee4
JR		 489 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
490 }
491
492 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
493
494 spin_unlock_irqrestore(&iommu->lock, flags);
495}
496
72e1dcc4
JR		 497static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head)
498{
499 struct amd_iommu_fault fault;
500 volatile u64 *raw;
501 int i;
502
503 raw = (u64 *)(iommu->ppr_log + head);
504
505 /*
506 * Hardware bug: Interrupt may arrive before the entry is written to
507 * memory. If this happens we need to wait for the entry to arrive.
508 */
509 for (i = 0; i < LOOP_TIMEOUT; ++i) {
510 if (PPR_REQ_TYPE(raw[0]) != 0)
511 break;
512 udelay(1);
513 }
514
515 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
516 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
517 return;
518 }
519
520 fault.address = raw[1];
521 fault.pasid = PPR_PASID(raw[0]);
522 fault.device_id = PPR_DEVID(raw[0]);
523 fault.tag = PPR_TAG(raw[0]);
524 fault.flags = PPR_FLAGS(raw[0]);
525
526 /*
527 * To detect the hardware bug we need to clear the entry
528 * to back to zero.
529 */
530 raw[0] = raw[1] = 0;
531
532 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
533}
534
535static void iommu_poll_ppr_log(struct amd_iommu *iommu)
536{
537 unsigned long flags;
538 u32 head, tail;
539
540 if (iommu->ppr_log == NULL)
541 return;
542
543 spin_lock_irqsave(&iommu->lock, flags);
544
545 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
546 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
547
548 while (head != tail) {
549
550 /* Handle PPR entry */
551 iommu_handle_ppr_entry(iommu, head);
552
553 /* Update and refresh ring-buffer state*/
554 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
555 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
556 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
557 }
558
559 /* enable ppr interrupts again */
560 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
561
562 spin_unlock_irqrestore(&iommu->lock, flags);
563}
564
72fe00f0 565irqreturn_t amd_iommu_int_thread(int irq, void *data)
a80dc3e0 566{
90008ee4
JR		 567 struct amd_iommu *iommu;
568
72e1dcc4 569 for_each_iommu(iommu) {
90008ee4 570 iommu_poll_events(iommu);
72e1dcc4
JR		 571 iommu_poll_ppr_log(iommu);
572 }
90008ee4
JR		 573
574 return IRQ_HANDLED;
a80dc3e0
JR		 575}
576
72fe00f0
JR		 577irqreturn_t amd_iommu_int_handler(int irq, void *data)
578{
579 return IRQ_WAKE_THREAD;
580}
581
431b2a20
JR		 582/****************************************************************************
583 *
584 * IOMMU command queuing functions
585 *
586 ****************************************************************************/
587
ac0ea6e9
JR		 588static int wait_on_sem(volatile u64 *sem)
589{
590 int i = 0;
591
592 while (*sem == 0 && i < LOOP_TIMEOUT) {
593 udelay(1);
594 i += 1;
595 }
596
597 if (i == LOOP_TIMEOUT) {
598 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
599 return -EIO;
600 }
601
602 return 0;
603}
604
605static void copy_cmd_to_buffer(struct amd_iommu *iommu,
606 struct iommu_cmd *cmd,
607 u32 tail)
a19ae1ec 608{
a19ae1ec
JR		 609 u8 *target;
610
8a7c5ef3 611 target = iommu->cmd_buf + tail;
ac0ea6e9
JR		 612 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
613
614 /* Copy command to buffer */
615 memcpy(target, cmd, sizeof(*cmd));
616
617 /* Tell the IOMMU about it */
a19ae1ec 618 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
ac0ea6e9 619}
a19ae1ec 620
815b33fd 621static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
ded46737 622{
815b33fd
JR		 623 WARN_ON(address & 0x7ULL);
624
ded46737 625 memset(cmd, 0, sizeof(*cmd));
815b33fd
JR		 626 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
627 cmd->data[1] = upper_32_bits(__pa(address));
628 cmd->data[2] = 1;
ded46737
JR		 629 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
630}
631
94fe79e2
JR		 632static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
633{
634 memset(cmd, 0, sizeof(*cmd));
635 cmd->data[0] = devid;
636 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
637}
638
11b6402c
JR		 639static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
640 size_t size, u16 domid, int pde)
641{
642 u64 pages;
643 int s;
644
645 pages = iommu_num_pages(address, size, PAGE_SIZE);
646 s = 0;
647
648 if (pages > 1) {
649 /*
650 * If we have to flush more than one page, flush all
651 * TLB entries for this domain
652 */
653 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
654 s = 1;
655 }
656
657 address &= PAGE_MASK;
658
659 memset(cmd, 0, sizeof(*cmd));
660 cmd->data[1] |= domid;
661 cmd->data[2] = lower_32_bits(address);
662 cmd->data[3] = upper_32_bits(address);
663 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
664 if (s) /* size bit - we flush more than one 4kb page */
665 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
666 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
667 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
668}
669
cb41ed85
JR		 670static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
671 u64 address, size_t size)
672{
673 u64 pages;
674 int s;
675
676 pages = iommu_num_pages(address, size, PAGE_SIZE);
677 s = 0;
678
679 if (pages > 1) {
680 /*
681 * If we have to flush more than one page, flush all
682 * TLB entries for this domain
683 */
684 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
685 s = 1;
686 }
687
688 address &= PAGE_MASK;
689
690 memset(cmd, 0, sizeof(*cmd));
691 cmd->data[0] = devid;
692 cmd->data[0] |= (qdep & 0xff) << 24;
693 cmd->data[1] = devid;
694 cmd->data[2] = lower_32_bits(address);
695 cmd->data[3] = upper_32_bits(address);
696 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
697 if (s)
698 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
699}
700
22e266c7
JR		 701static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
702 u64 address, bool size)
703{
704 memset(cmd, 0, sizeof(*cmd));
705
706 address &= ~(0xfffULL);
707
708 cmd->data[0] = pasid & PASID_MASK;
709 cmd->data[1] = domid;
710 cmd->data[2] = lower_32_bits(address);
711 cmd->data[3] = upper_32_bits(address);
712 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
713 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
714 if (size)
715 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
716 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
717}
718
719static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
720 int qdep, u64 address, bool size)
721{
722 memset(cmd, 0, sizeof(*cmd));
723
724 address &= ~(0xfffULL);
725
726 cmd->data[0] = devid;
727 cmd->data[0] |= (pasid & 0xff) << 16;
728 cmd->data[0] |= (qdep & 0xff) << 24;
729 cmd->data[1] = devid;
730 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
731 cmd->data[2] = lower_32_bits(address);
732 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
733 cmd->data[3] = upper_32_bits(address);
734 if (size)
735 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
736 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
737}
738
c99afa25
JR		 739static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
740 int status, int tag, bool gn)
741{
742 memset(cmd, 0, sizeof(*cmd));
743
744 cmd->data[0] = devid;
745 if (gn) {
746 cmd->data[1] = pasid & PASID_MASK;
747 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
748 }
749 cmd->data[3] = tag & 0x1ff;
750 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
751
752 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
753}
754
58fc7f14
JR		 755static void build_inv_all(struct iommu_cmd *cmd)
756{
757 memset(cmd, 0, sizeof(*cmd));
758 CMD_SET_TYPE(cmd, CMD_INV_ALL);
a19ae1ec
JR		 759}
760
431b2a20 761/*
431b2a20 762 * Writes the command to the IOMMUs command buffer and informs the
ac0ea6e9 763 * hardware about the new command.
431b2a20 764 */
f1ca1512
JR		 765static int iommu_queue_command_sync(struct amd_iommu *iommu,
766 struct iommu_cmd *cmd,
767 bool sync)
a19ae1ec 768{
ac0ea6e9 769 u32 left, tail, head, next_tail;
a19ae1ec 770 unsigned long flags;
a19ae1ec 771
549c90dc 772 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
ac0ea6e9
JR		 773
774again:
a19ae1ec 775 spin_lock_irqsave(&iommu->lock, flags);
a19ae1ec 776
ac0ea6e9
JR		 777 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
778 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
779 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
780 left = (head - next_tail) % iommu->cmd_buf_size;
a19ae1ec 781
ac0ea6e9
JR		 782 if (left <= 2) {
783 struct iommu_cmd sync_cmd;
784 volatile u64 sem = 0;
785 int ret;
8d201968 786
ac0ea6e9
JR		 787 build_completion_wait(&sync_cmd, (u64)&sem);
788 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
da49f6df 789
ac0ea6e9
JR		 790 spin_unlock_irqrestore(&iommu->lock, flags);
791
792 if ((ret = wait_on_sem(&sem)) != 0)
793 return ret;
794
795 goto again;
8d201968
JR		 796 }
797
ac0ea6e9
JR		 798 copy_cmd_to_buffer(iommu, cmd, tail);
799
800 /* We need to sync now to make sure all commands are processed */
f1ca1512 801 iommu->need_sync = sync;
ac0ea6e9 802
a19ae1ec 803 spin_unlock_irqrestore(&iommu->lock, flags);
8d201968 804
815b33fd 805 return 0;
8d201968
JR		 806}
807
f1ca1512
JR		 808static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
809{
810 return iommu_queue_command_sync(iommu, cmd, true);
811}
812
8d201968
JR		 813/*
814 * This function queues a completion wait command into the command
815 * buffer of an IOMMU
816 */
a19ae1ec 817static int iommu_completion_wait(struct amd_iommu *iommu)
8d201968
JR		 818{
819 struct iommu_cmd cmd;
815b33fd 820 volatile u64 sem = 0;
ac0ea6e9 821 int ret;
8d201968 822
09ee17eb 823 if (!iommu->need_sync)
815b33fd 824 return 0;
09ee17eb 825
815b33fd 826 build_completion_wait(&cmd, (u64)&sem);
a19ae1ec 827
f1ca1512 828 ret = iommu_queue_command_sync(iommu, &cmd, false);
a19ae1ec 829 if (ret)
815b33fd 830 return ret;
8d201968 831
ac0ea6e9 832 return wait_on_sem(&sem);
8d201968
JR		 833}
834
d8c13085 835static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
a19ae1ec 836{
d8c13085 837 struct iommu_cmd cmd;
a19ae1ec 838
d8c13085 839 build_inv_dte(&cmd, devid);
7e4f88da 840
d8c13085
JR		 841 return iommu_queue_command(iommu, &cmd);
842}
09ee17eb 843
7d0c5cc5
JR		 844static void iommu_flush_dte_all(struct amd_iommu *iommu)
845{
846 u32 devid;
09ee17eb 847
7d0c5cc5
JR		 848 for (devid = 0; devid <= 0xffff; ++devid)
849 iommu_flush_dte(iommu, devid);
a19ae1ec 850
7d0c5cc5
JR		 851 iommu_completion_wait(iommu);
852}
84df8175 853
7d0c5cc5
JR		 854/*
855 * This function uses heavy locking and may disable irqs for some time. But
856 * this is no issue because it is only called during resume.
857 */
858static void iommu_flush_tlb_all(struct amd_iommu *iommu)
859{
860 u32 dom_id;
a19ae1ec 861
7d0c5cc5
JR		 862 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
863 struct iommu_cmd cmd;
864 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
865 dom_id, 1);
866 iommu_queue_command(iommu, &cmd);
867 }
8eed9833 868
7d0c5cc5 869 iommu_completion_wait(iommu);
a19ae1ec
JR		 870}
871
58fc7f14 872static void iommu_flush_all(struct amd_iommu *iommu)
0518a3a4 873{
58fc7f14 874 struct iommu_cmd cmd;
0518a3a4 875
58fc7f14 876 build_inv_all(&cmd);
0518a3a4 877
58fc7f14
JR		 878 iommu_queue_command(iommu, &cmd);
879 iommu_completion_wait(iommu);
880}
881
7d0c5cc5
JR		 882void iommu_flush_all_caches(struct amd_iommu *iommu)
883{
58fc7f14
JR		 884 if (iommu_feature(iommu, FEATURE_IA)) {
885 iommu_flush_all(iommu);
886 } else {
887 iommu_flush_dte_all(iommu);
888 iommu_flush_tlb_all(iommu);
0518a3a4
JR		 889 }
890}
891
431b2a20 892/*
cb41ed85 893 * Command send function for flushing on-device TLB
431b2a20 894 */
6c542047
JR		 895static int device_flush_iotlb(struct iommu_dev_data *dev_data,
896 u64 address, size_t size)
3fa43655
JR		 897{
898 struct amd_iommu *iommu;
b00d3bcf 899 struct iommu_cmd cmd;
cb41ed85 900 int qdep;
3fa43655 901
ea61cddb
JR		 902 qdep = dev_data->ats.qdep;
903 iommu = amd_iommu_rlookup_table[dev_data->devid];
3fa43655 904
ea61cddb 905 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
b00d3bcf
JR		 906
907 return iommu_queue_command(iommu, &cmd);
3fa43655
JR		 908}
909
431b2a20 910/*
431b2a20 911 * Command send function for invalidating a device table entry
431b2a20 912 */
6c542047 913static int device_flush_dte(struct iommu_dev_data *dev_data)
a19ae1ec 914{
3fa43655 915 struct amd_iommu *iommu;
ee2fa743 916 int ret;
a19ae1ec 917
6c542047 918 iommu = amd_iommu_rlookup_table[dev_data->devid];
a19ae1ec 919
f62dda66 920 ret = iommu_flush_dte(iommu, dev_data->devid);
cb41ed85
JR		 921 if (ret)
922 return ret;
923
ea61cddb 924 if (dev_data->ats.enabled)
6c542047 925 ret = device_flush_iotlb(dev_data, 0, ~0UL);
ee2fa743 926
ee2fa743 927 return ret;
a19ae1ec
JR		 928}
929
431b2a20
JR		 930/*
931 * TLB invalidation function which is called from the mapping functions.
932 * It invalidates a single PTE if the range to flush is within a single
933 * page. Otherwise it flushes the whole TLB of the IOMMU.
934 */
17b124bf
JR		 935static void __domain_flush_pages(struct protection_domain *domain,
936 u64 address, size_t size, int pde)
a19ae1ec 937{
cb41ed85 938 struct iommu_dev_data *dev_data;
11b6402c
JR		 939 struct iommu_cmd cmd;
940 int ret = 0, i;
a19ae1ec 941
11b6402c 942 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
999ba417 943
6de8ad9b
JR		 944 for (i = 0; i < amd_iommus_present; ++i) {
945 if (!domain->dev_iommu[i])
946 continue;
947
948 /*
949 * Devices of this domain are behind this IOMMU
950 * We need a TLB flush
951 */
11b6402c 952 ret |= iommu_queue_command(amd_iommus[i], &cmd);
6de8ad9b
JR		 953 }
954
cb41ed85 955 list_for_each_entry(dev_data, &domain->dev_list, list) {
cb41ed85 956
ea61cddb 957 if (!dev_data->ats.enabled)
cb41ed85
JR		 958 continue;
959
6c542047 960 ret |= device_flush_iotlb(dev_data, address, size);
cb41ed85
JR		 961 }
962
11b6402c 963 WARN_ON(ret);
6de8ad9b
JR		 964}
965
17b124bf
JR		 966static void domain_flush_pages(struct protection_domain *domain,
967 u64 address, size_t size)
6de8ad9b 968{
17b124bf 969 __domain_flush_pages(domain, address, size, 0);
a19ae1ec 970}
b6c02715 971
1c655773 972/* Flush the whole IO/TLB for a given protection domain */
17b124bf 973static void domain_flush_tlb(struct protection_domain *domain)
1c655773 974{
17b124bf 975 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1c655773
JR		 976}
977
42a49f96 978/* Flush the whole IO/TLB for a given protection domain - including PDE */
17b124bf 979static void domain_flush_tlb_pde(struct protection_domain *domain)
42a49f96 980{
17b124bf 981 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
42a49f96
CW		 982}
983
17b124bf 984static void domain_flush_complete(struct protection_domain *domain)
b00d3bcf 985{
17b124bf 986 int i;
18811f55 987
17b124bf
JR		 988 for (i = 0; i < amd_iommus_present; ++i) {
989 if (!domain->dev_iommu[i])
990 continue;
bfd1be18 991
17b124bf
JR		 992 /*
993 * Devices of this domain are behind this IOMMU
994 * We need to wait for completion of all commands.
995 */
996 iommu_completion_wait(amd_iommus[i]);
bfd1be18 997 }
e394d72a
JR		 998}
999
b00d3bcf 1000
09b42804 1001/*
b00d3bcf 1002 * This function flushes the DTEs for all devices in domain
09b42804 1003 */
17b124bf 1004static void domain_flush_devices(struct protection_domain *domain)
e394d72a 1005{
b00d3bcf 1006 struct iommu_dev_data *dev_data;
b26e81b8 1007
b00d3bcf 1008 list_for_each_entry(dev_data, &domain->dev_list, list)
6c542047 1009 device_flush_dte(dev_data);
a345b23b
JR		 1010}
1011
431b2a20
JR		 1012/****************************************************************************
1013 *
1014 * The functions below are used the create the page table mappings for
1015 * unity mapped regions.
1016 *
1017 ****************************************************************************/
1018
308973d3
JR		 1019/*
1020 * This function is used to add another level to an IO page table. Adding
1021 * another level increases the size of the address space by 9 bits to a size up
1022 * to 64 bits.
1023 */
1024static bool increase_address_space(struct protection_domain *domain,
1025 gfp_t gfp)
1026{
1027 u64 *pte;
1028
1029 if (domain->mode == PAGE_MODE_6_LEVEL)
1030 /* address space already 64 bit large */
1031 return false;
1032
1033 pte = (void *)get_zeroed_page(gfp);
1034 if (!pte)
1035 return false;
1036
1037 *pte = PM_LEVEL_PDE(domain->mode,
1038 virt_to_phys(domain->pt_root));
1039 domain->pt_root = pte;
1040 domain->mode += 1;
1041 domain->updated = true;
1042
1043 return true;
1044}
1045
1046static u64 *alloc_pte(struct protection_domain *domain,
1047 unsigned long address,
cbb9d729 1048 unsigned long page_size,
308973d3
JR		 1049 u64 **pte_page,
1050 gfp_t gfp)
1051{
cbb9d729 1052 int level, end_lvl;
308973d3 1053 u64 *pte, *page;
cbb9d729
JR		 1054
1055 BUG_ON(!is_power_of_2(page_size));
308973d3
JR		 1056
1057 while (address > PM_LEVEL_SIZE(domain->mode))
1058 increase_address_space(domain, gfp);
1059
cbb9d729
JR		 1060 level = domain->mode - 1;
1061 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1062 address = PAGE_SIZE_ALIGN(address, page_size);
1063 end_lvl = PAGE_SIZE_LEVEL(page_size);
308973d3
JR		 1064
1065 while (level > end_lvl) {
1066 if (!IOMMU_PTE_PRESENT(*pte)) {
1067 page = (u64 *)get_zeroed_page(gfp);
1068 if (!page)
1069 return NULL;
1070 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1071 }
1072
cbb9d729
JR		 1073 /* No level skipping support yet */
1074 if (PM_PTE_LEVEL(*pte) != level)
1075 return NULL;
1076
308973d3
JR		 1077 level -= 1;
1078
1079 pte = IOMMU_PTE_PAGE(*pte);
1080
1081 if (pte_page && level == end_lvl)
1082 *pte_page = pte;
1083
1084 pte = &pte[PM_LEVEL_INDEX(level, address)];
1085 }
1086
1087 return pte;
1088}
1089
1090/*
1091 * This function checks if there is a PTE for a given dma address. If
1092 * there is one, it returns the pointer to it.
1093 */
24cd7723 1094static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
308973d3
JR		 1095{
1096 int level;
1097 u64 *pte;
1098
24cd7723
JR		 1099 if (address > PM_LEVEL_SIZE(domain->mode))
1100 return NULL;
1101
1102 level = domain->mode - 1;
1103 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
308973d3 1104
24cd7723
JR		 1105 while (level > 0) {
1106
1107 /* Not Present */
308973d3
JR		 1108 if (!IOMMU_PTE_PRESENT(*pte))
1109 return NULL;
1110
24cd7723
JR		 1111 /* Large PTE */
1112 if (PM_PTE_LEVEL(*pte) == 0x07) {
1113 unsigned long pte_mask, __pte;
1114
1115 /*
1116 * If we have a series of large PTEs, make
1117 * sure to return a pointer to the first one.
1118 */
1119 pte_mask = PTE_PAGE_SIZE(*pte);
1120 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1121 __pte = ((unsigned long)pte) & pte_mask;
1122
1123 return (u64 *)__pte;
1124 }
1125
1126 /* No level skipping support yet */
1127 if (PM_PTE_LEVEL(*pte) != level)
1128 return NULL;
1129
308973d3
JR		 1130 level -= 1;
1131
24cd7723 1132 /* Walk to the next level */
308973d3
JR		 1133 pte = IOMMU_PTE_PAGE(*pte);
1134 pte = &pte[PM_LEVEL_INDEX(level, address)];
308973d3
JR		 1135 }
1136
1137 return pte;
1138}
1139
431b2a20
JR		 1140/*
1141 * Generic mapping functions. It maps a physical address into a DMA
1142 * address space. It allocates the page table pages if necessary.
1143 * In the future it can be extended to a generic mapping function
1144 * supporting all features of AMD IOMMU page tables like level skipping
1145 * and full 64 bit address spaces.
1146 */
38e817fe
JR		 1147static int iommu_map_page(struct protection_domain *dom,
1148 unsigned long bus_addr,
1149 unsigned long phys_addr,
abdc5eb3 1150 int prot,
cbb9d729 1151 unsigned long page_size)
bd0e5211 1152{
8bda3092 1153 u64 __pte, *pte;
cbb9d729 1154 int i, count;
abdc5eb3 1155
bad1cac2 1156 if (!(prot & IOMMU_PROT_MASK))
bd0e5211
JR		 1157 return -EINVAL;
1158
cbb9d729
JR		 1159 bus_addr = PAGE_ALIGN(bus_addr);
1160 phys_addr = PAGE_ALIGN(phys_addr);
1161 count = PAGE_SIZE_PTE_COUNT(page_size);
1162 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1163
1164 for (i = 0; i < count; ++i)
1165 if (IOMMU_PTE_PRESENT(pte[i]))
1166 return -EBUSY;
bd0e5211 1167
cbb9d729
JR		 1168 if (page_size > PAGE_SIZE) {
1169 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1170 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1171 } else
1172 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
bd0e5211 1173
bd0e5211
JR		 1174 if (prot & IOMMU_PROT_IR)
1175 __pte |= IOMMU_PTE_IR;
1176 if (prot & IOMMU_PROT_IW)
1177 __pte |= IOMMU_PTE_IW;
1178
cbb9d729
JR		 1179 for (i = 0; i < count; ++i)
1180 pte[i] = __pte;
bd0e5211 1181
04bfdd84
JR		 1182 update_domain(dom);
1183
bd0e5211
JR		 1184 return 0;
1185}
1186
24cd7723
JR		 1187static unsigned long iommu_unmap_page(struct protection_domain *dom,
1188 unsigned long bus_addr,
1189 unsigned long page_size)
eb74ff6c 1190{
24cd7723
JR		 1191 unsigned long long unmap_size, unmapped;
1192 u64 *pte;
1193
1194 BUG_ON(!is_power_of_2(page_size));
1195
1196 unmapped = 0;
eb74ff6c 1197
24cd7723
JR		 1198 while (unmapped < page_size) {
1199
1200 pte = fetch_pte(dom, bus_addr);
1201
1202 if (!pte) {
1203 /*
1204 * No PTE for this address
1205 * move forward in 4kb steps
1206 */
1207 unmap_size = PAGE_SIZE;
1208 } else if (PM_PTE_LEVEL(*pte) == 0) {
1209 /* 4kb PTE found for this address */
1210 unmap_size = PAGE_SIZE;
1211 *pte = 0ULL;
1212 } else {
1213 int count, i;
1214
1215 /* Large PTE found which maps this address */
1216 unmap_size = PTE_PAGE_SIZE(*pte);
1217 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1218 for (i = 0; i < count; i++)
1219 pte[i] = 0ULL;
1220 }
1221
1222 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1223 unmapped += unmap_size;
1224 }
1225
1226 BUG_ON(!is_power_of_2(unmapped));
eb74ff6c 1227
24cd7723 1228 return unmapped;
eb74ff6c 1229}
eb74ff6c 1230
431b2a20
JR		 1231/*
1232 * This function checks if a specific unity mapping entry is needed for
1233 * this specific IOMMU.
1234 */
bd0e5211
JR		 1235static int iommu_for_unity_map(struct amd_iommu *iommu,
1236 struct unity_map_entry *entry)
1237{
1238 u16 bdf, i;
1239
1240 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1241 bdf = amd_iommu_alias_table[i];
1242 if (amd_iommu_rlookup_table[bdf] == iommu)
1243 return 1;
1244 }
1245
1246 return 0;
1247}
1248
431b2a20
JR		 1249/*
1250 * This function actually applies the mapping to the page table of the
1251 * dma_ops domain.
1252 */
bd0e5211
JR		 1253static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1254 struct unity_map_entry *e)
1255{
1256 u64 addr;
1257 int ret;
1258
1259 for (addr = e->address_start; addr < e->address_end;
1260 addr += PAGE_SIZE) {
abdc5eb3 1261 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
cbb9d729 1262 PAGE_SIZE);
bd0e5211
JR		 1263 if (ret)
1264 return ret;
1265 /*
1266 * if unity mapping is in aperture range mark the page
1267 * as allocated in the aperture
1268 */
1269 if (addr < dma_dom->aperture_size)
c3239567 1270 __set_bit(addr >> PAGE_SHIFT,
384de729 1271 dma_dom->aperture[0]->bitmap);
bd0e5211
JR		 1272 }
1273
1274 return 0;
1275}
1276
171e7b37
JR		 1277/*
1278 * Init the unity mappings for a specific IOMMU in the system
1279 *
1280 * Basically iterates over all unity mapping entries and applies them to
1281 * the default domain DMA of that IOMMU if necessary.
1282 */
1283static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1284{
1285 struct unity_map_entry *entry;
1286 int ret;
1287
1288 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1289 if (!iommu_for_unity_map(iommu, entry))
1290 continue;
1291 ret = dma_ops_unity_map(iommu->default_dom, entry);
1292 if (ret)
1293 return ret;
1294 }
1295
1296 return 0;
1297}
1298
431b2a20
JR		 1299/*
1300 * Inits the unity mappings required for a specific device
1301 */
bd0e5211
JR		 1302static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1303 u16 devid)
1304{
1305 struct unity_map_entry *e;
1306 int ret;
1307
1308 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1309 if (!(devid >= e->devid_start && devid <= e->devid_end))
1310 continue;
1311 ret = dma_ops_unity_map(dma_dom, e);
1312 if (ret)
1313 return ret;
1314 }
1315
1316 return 0;
1317}
1318
431b2a20
JR		 1319/****************************************************************************
1320 *
1321 * The next functions belong to the address allocator for the dma_ops
1322 * interface functions. They work like the allocators in the other IOMMU
1323 * drivers. Its basically a bitmap which marks the allocated pages in
1324 * the aperture. Maybe it could be enhanced in the future to a more
1325 * efficient allocator.
1326 *
1327 ****************************************************************************/
d3086444 1328
431b2a20 1329/*
384de729 1330 * The address allocator core functions.
431b2a20
JR		 1331 *
1332 * called with domain->lock held
1333 */
384de729 1334
171e7b37
JR		 1335/*
1336 * Used to reserve address ranges in the aperture (e.g. for exclusion
1337 * ranges.
1338 */
1339static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1340 unsigned long start_page,
1341 unsigned int pages)
1342{
1343 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1344
1345 if (start_page + pages > last_page)
1346 pages = last_page - start_page;
1347
1348 for (i = start_page; i < start_page + pages; ++i) {
1349 int index = i / APERTURE_RANGE_PAGES;
1350 int page = i % APERTURE_RANGE_PAGES;
1351 __set_bit(page, dom->aperture[index]->bitmap);
1352 }
1353}
1354
9cabe89b
JR		 1355/*
1356 * This function is used to add a new aperture range to an existing
1357 * aperture in case of dma_ops domain allocation or address allocation
1358 * failure.
1359 */
576175c2 1360static int alloc_new_range(struct dma_ops_domain *dma_dom,
9cabe89b
JR		 1361 bool populate, gfp_t gfp)
1362{
1363 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
576175c2 1364 struct amd_iommu *iommu;
17f5b569 1365 unsigned long i, old_size;
9cabe89b 1366
f5e9705c
JR		 1367#ifdef CONFIG_IOMMU_STRESS
1368 populate = false;
1369#endif
1370
9cabe89b
JR		 1371 if (index >= APERTURE_MAX_RANGES)
1372 return -ENOMEM;
1373
1374 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1375 if (!dma_dom->aperture[index])
1376 return -ENOMEM;
1377
1378 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1379 if (!dma_dom->aperture[index]->bitmap)
1380 goto out_free;
1381
1382 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1383
1384 if (populate) {
1385 unsigned long address = dma_dom->aperture_size;
1386 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1387 u64 *pte, *pte_page;
1388
1389 for (i = 0; i < num_ptes; ++i) {
cbb9d729 1390 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
9cabe89b
JR		 1391 &pte_page, gfp);
1392 if (!pte)
1393 goto out_free;
1394
1395 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1396
1397 address += APERTURE_RANGE_SIZE / 64;
1398 }
1399 }
1400
17f5b569 1401 old_size = dma_dom->aperture_size;
9cabe89b
JR		 1402 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1403
17f5b569
JR		 1404 /* Reserve address range used for MSI messages */
1405 if (old_size < MSI_ADDR_BASE_LO &&
1406 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1407 unsigned long spage;
1408 int pages;
1409
1410 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1411 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1412
1413 dma_ops_reserve_addresses(dma_dom, spage, pages);
1414 }
1415
b595076a 1416 /* Initialize the exclusion range if necessary */
576175c2
JR		 1417 for_each_iommu(iommu) {
1418 if (iommu->exclusion_start &&
1419 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1420 && iommu->exclusion_start < dma_dom->aperture_size) {
1421 unsigned long startpage;
1422 int pages = iommu_num_pages(iommu->exclusion_start,
1423 iommu->exclusion_length,
1424 PAGE_SIZE);
1425 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1426 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1427 }
00cd122a
JR		 1428 }
1429
1430 /*
1431 * Check for areas already mapped as present in the new aperture
1432 * range and mark those pages as reserved in the allocator. Such
1433 * mappings may already exist as a result of requested unity
1434 * mappings for devices.
1435 */
1436 for (i = dma_dom->aperture[index]->offset;
1437 i < dma_dom->aperture_size;
1438 i += PAGE_SIZE) {
24cd7723 1439 u64 *pte = fetch_pte(&dma_dom->domain, i);
00cd122a
JR		 1440 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1441 continue;
1442
fcd0861d 1443 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
00cd122a
JR		 1444 }
1445
04bfdd84
JR		 1446 update_domain(&dma_dom->domain);
1447
9cabe89b
JR		 1448 return 0;
1449
1450out_free:
04bfdd84
JR		 1451 update_domain(&dma_dom->domain);
1452
9cabe89b
JR		 1453 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1454
1455 kfree(dma_dom->aperture[index]);
1456 dma_dom->aperture[index] = NULL;
1457
1458 return -ENOMEM;
1459}
1460
384de729
JR		 1461static unsigned long dma_ops_area_alloc(struct device *dev,
1462 struct dma_ops_domain *dom,
1463 unsigned int pages,
1464 unsigned long align_mask,
1465 u64 dma_mask,
1466 unsigned long start)
1467{
803b8cb4 1468 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
384de729
JR		 1469 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1470 int i = start >> APERTURE_RANGE_SHIFT;
1471 unsigned long boundary_size;
1472 unsigned long address = -1;
1473 unsigned long limit;
1474
803b8cb4
JR		 1475 next_bit >>= PAGE_SHIFT;
1476
384de729
JR		 1477 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1478 PAGE_SIZE) >> PAGE_SHIFT;
1479
1480 for (;i < max_index; ++i) {
1481 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1482
1483 if (dom->aperture[i]->offset >= dma_mask)
1484 break;
1485
1486 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1487 dma_mask >> PAGE_SHIFT);
1488
1489 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1490 limit, next_bit, pages, 0,
1491 boundary_size, align_mask);
1492 if (address != -1) {
1493 address = dom->aperture[i]->offset +
1494 (address << PAGE_SHIFT);
803b8cb4 1495 dom->next_address = address + (pages << PAGE_SHIFT);
384de729
JR		 1496 break;
1497 }
1498
1499 next_bit = 0;
1500 }
1501
1502 return address;
1503}
1504
d3086444
JR		 1505static unsigned long dma_ops_alloc_addresses(struct device *dev,
1506 struct dma_ops_domain *dom,
6d4f343f 1507 unsigned int pages,
832a90c3
JR		 1508 unsigned long align_mask,
1509 u64 dma_mask)
d3086444 1510{
d3086444 1511 unsigned long address;
d3086444 1512
fe16f088
JR		 1513#ifdef CONFIG_IOMMU_STRESS
1514 dom->next_address = 0;
1515 dom->need_flush = true;
1516#endif
d3086444 1517
384de729 1518 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
803b8cb4 1519 dma_mask, dom->next_address);
d3086444 1520
1c655773 1521 if (address == -1) {
803b8cb4 1522 dom->next_address = 0;
384de729
JR		 1523 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1524 dma_mask, 0);
1c655773
JR		 1525 dom->need_flush = true;
1526 }
d3086444 1527
384de729 1528 if (unlikely(address == -1))
8fd524b3 1529 address = DMA_ERROR_CODE;
d3086444
JR		 1530
1531 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1532
1533 return address;
1534}
1535
431b2a20
JR		 1536/*
1537 * The address free function.
1538 *
1539 * called with domain->lock held
1540 */
d3086444
JR		 1541static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1542 unsigned long address,
1543 unsigned int pages)
1544{
384de729
JR		 1545 unsigned i = address >> APERTURE_RANGE_SHIFT;
1546 struct aperture_range *range = dom->aperture[i];
80be308d 1547
384de729
JR		 1548 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1549
47bccd6b
JR		 1550#ifdef CONFIG_IOMMU_STRESS
1551 if (i < 4)
1552 return;
1553#endif
80be308d 1554
803b8cb4 1555 if (address >= dom->next_address)
80be308d 1556 dom->need_flush = true;
384de729
JR		 1557
1558 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
803b8cb4 1559
a66022c4 1560 bitmap_clear(range->bitmap, address, pages);
384de729 1561
d3086444
JR		 1562}
1563
431b2a20
JR		 1564/****************************************************************************
1565 *
1566 * The next functions belong to the domain allocation. A domain is
1567 * allocated for every IOMMU as the default domain. If device isolation
1568 * is enabled, every device get its own domain. The most important thing
1569 * about domains is the page table mapping the DMA address space they
1570 * contain.
1571 *
1572 ****************************************************************************/
1573
aeb26f55
JR		 1574/*
1575 * This function adds a protection domain to the global protection domain list
1576 */
1577static void add_domain_to_list(struct protection_domain *domain)
1578{
1579 unsigned long flags;
1580
1581 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1582 list_add(&domain->list, &amd_iommu_pd_list);
1583 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1584}
1585
1586/*
1587 * This function removes a protection domain to the global
1588 * protection domain list
1589 */
1590static void del_domain_from_list(struct protection_domain *domain)
1591{
1592 unsigned long flags;
1593
1594 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1595 list_del(&domain->list);
1596 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1597}
1598
ec487d1a
JR		 1599static u16 domain_id_alloc(void)
1600{
1601 unsigned long flags;
1602 int id;
1603
1604 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1605 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1606 BUG_ON(id == 0);
1607 if (id > 0 && id < MAX_DOMAIN_ID)
1608 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1609 else
1610 id = 0;
1611 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1612
1613 return id;
1614}
1615
a2acfb75
JR		 1616static void domain_id_free(int id)
1617{
1618 unsigned long flags;
1619
1620 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1621 if (id > 0 && id < MAX_DOMAIN_ID)
1622 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1623 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1624}
a2acfb75 1625
86db2e5d 1626static void free_pagetable(struct protection_domain *domain)
ec487d1a
JR		 1627{
1628 int i, j;
1629 u64 *p1, *p2, *p3;
1630
86db2e5d 1631 p1 = domain->pt_root;
ec487d1a
JR		 1632
1633 if (!p1)
1634 return;
1635
1636 for (i = 0; i < 512; ++i) {
1637 if (!IOMMU_PTE_PRESENT(p1[i]))
1638 continue;
1639
1640 p2 = IOMMU_PTE_PAGE(p1[i]);
3cc3d84b 1641 for (j = 0; j < 512; ++j) {
ec487d1a
JR		 1642 if (!IOMMU_PTE_PRESENT(p2[j]))
1643 continue;
1644 p3 = IOMMU_PTE_PAGE(p2[j]);
1645 free_page((unsigned long)p3);
1646 }
1647
1648 free_page((unsigned long)p2);
1649 }
1650
1651 free_page((unsigned long)p1);
86db2e5d
JR		 1652
1653 domain->pt_root = NULL;
ec487d1a
JR		 1654}
1655
b16137b1
JR		 1656static void free_gcr3_tbl_level1(u64 *tbl)
1657{
1658 u64 *ptr;
1659 int i;
1660
1661 for (i = 0; i < 512; ++i) {
1662 if (!(tbl[i] & GCR3_VALID))
1663 continue;
1664
1665 ptr = __va(tbl[i] & PAGE_MASK);
1666
1667 free_page((unsigned long)ptr);
1668 }
1669}
1670
1671static void free_gcr3_tbl_level2(u64 *tbl)
1672{
1673 u64 *ptr;
1674 int i;
1675
1676 for (i = 0; i < 512; ++i) {
1677 if (!(tbl[i] & GCR3_VALID))
1678 continue;
1679
1680 ptr = __va(tbl[i] & PAGE_MASK);
1681
1682 free_gcr3_tbl_level1(ptr);
1683 }
1684}
1685
52815b75
JR		 1686static void free_gcr3_table(struct protection_domain *domain)
1687{
b16137b1
JR		 1688 if (domain->glx == 2)
1689 free_gcr3_tbl_level2(domain->gcr3_tbl);
1690 else if (domain->glx == 1)
1691 free_gcr3_tbl_level1(domain->gcr3_tbl);
1692 else if (domain->glx != 0)
1693 BUG();
1694
52815b75
JR		 1695 free_page((unsigned long)domain->gcr3_tbl);
1696}
1697
431b2a20
JR		 1698/*
1699 * Free a domain, only used if something went wrong in the
1700 * allocation path and we need to free an already allocated page table
1701 */
ec487d1a
JR		 1702static void dma_ops_domain_free(struct dma_ops_domain *dom)
1703{
384de729
JR		 1704 int i;
1705
ec487d1a
JR		 1706 if (!dom)
1707 return;
1708
aeb26f55
JR		 1709 del_domain_from_list(&dom->domain);
1710
86db2e5d 1711 free_pagetable(&dom->domain);
ec487d1a 1712
384de729
JR		 1713 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1714 if (!dom->aperture[i])
1715 continue;
1716 free_page((unsigned long)dom->aperture[i]->bitmap);
1717 kfree(dom->aperture[i]);
1718 }
ec487d1a
JR		 1719
1720 kfree(dom);
1721}
1722
431b2a20
JR		 1723/*
1724 * Allocates a new protection domain usable for the dma_ops functions.
b595076a 1725 * It also initializes the page table and the address allocator data
431b2a20
JR		 1726 * structures required for the dma_ops interface
1727 */
87a64d52 1728static struct dma_ops_domain *dma_ops_domain_alloc(void)
ec487d1a
JR		 1729{
1730 struct dma_ops_domain *dma_dom;
ec487d1a
JR		 1731
1732 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1733 if (!dma_dom)
1734 return NULL;
1735
1736 spin_lock_init(&dma_dom->domain.lock);
1737
1738 dma_dom->domain.id = domain_id_alloc();
1739 if (dma_dom->domain.id == 0)
1740 goto free_dma_dom;
7c392cbe 1741 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
8f7a017c 1742 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
ec487d1a 1743 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
9fdb19d6 1744 dma_dom->domain.flags = PD_DMA_OPS_MASK;
ec487d1a
JR		 1745 dma_dom->domain.priv = dma_dom;
1746 if (!dma_dom->domain.pt_root)
1747 goto free_dma_dom;
ec487d1a 1748
1c655773 1749 dma_dom->need_flush = false;
bd60b735 1750 dma_dom->target_dev = 0xffff;
1c655773 1751
aeb26f55
JR		 1752 add_domain_to_list(&dma_dom->domain);
1753
576175c2 1754 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
ec487d1a 1755 goto free_dma_dom;
ec487d1a 1756
431b2a20 1757 /*
ec487d1a
JR		 1758 * mark the first page as allocated so we never return 0 as
1759 * a valid dma-address. So we can use 0 as error value
431b2a20 1760 */
384de729 1761 dma_dom->aperture[0]->bitmap[0] = 1;
803b8cb4 1762 dma_dom->next_address = 0;
ec487d1a 1763
ec487d1a
JR		 1764
1765 return dma_dom;
1766
1767free_dma_dom:
1768 dma_ops_domain_free(dma_dom);
1769
1770 return NULL;
1771}
1772
5b28df6f
JR		 1773/*
1774 * little helper function to check whether a given protection domain is a
1775 * dma_ops domain
1776 */
1777static bool dma_ops_domain(struct protection_domain *domain)
1778{
1779 return domain->flags & PD_DMA_OPS_MASK;
1780}
1781
fd7b5535 1782static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
b20ac0d4 1783{
132bd68f 1784 u64 pte_root = 0;
ee6c2868 1785 u64 flags = 0;
863c74eb 1786
132bd68f
JR		 1787 if (domain->mode != PAGE_MODE_NONE)
1788 pte_root = virt_to_phys(domain->pt_root);
1789
38ddf41b
JR		 1790 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1791 << DEV_ENTRY_MODE_SHIFT;
1792 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
b20ac0d4 1793
ee6c2868
JR		 1794 flags = amd_iommu_dev_table[devid].data[1];
1795
fd7b5535
JR		 1796 if (ats)
1797 flags |= DTE_FLAG_IOTLB;
1798
52815b75
JR		 1799 if (domain->flags & PD_IOMMUV2_MASK) {
1800 u64 gcr3 = __pa(domain->gcr3_tbl);
1801 u64 glx = domain->glx;
1802 u64 tmp;
1803
1804 pte_root |= DTE_FLAG_GV;
1805 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1806
1807 /* First mask out possible old values for GCR3 table */
1808 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1809 flags &= ~tmp;
1810
1811 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1812 flags &= ~tmp;
1813
1814 /* Encode GCR3 table into DTE */
1815 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1816 pte_root |= tmp;
1817
1818 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1819 flags |= tmp;
1820
1821 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1822 flags |= tmp;
1823 }
1824
ee6c2868
JR		 1825 flags &= ~(0xffffUL);
1826 flags |= domain->id;
1827
1828 amd_iommu_dev_table[devid].data[1] = flags;
1829 amd_iommu_dev_table[devid].data[0] = pte_root;
15898bbc
JR		 1830}
1831
1832static void clear_dte_entry(u16 devid)
1833{
15898bbc
JR		 1834 /* remove entry from the device table seen by the hardware */
1835 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1836 amd_iommu_dev_table[devid].data[1] = 0;
15898bbc
JR		 1837
1838 amd_iommu_apply_erratum_63(devid);
7f760ddd
JR		 1839}
1840
ec9e79ef
JR		 1841static void do_attach(struct iommu_dev_data *dev_data,
1842 struct protection_domain *domain)
7f760ddd 1843{
7f760ddd 1844 struct amd_iommu *iommu;
ec9e79ef 1845 bool ats;
fd7b5535 1846
ec9e79ef
JR		 1847 iommu = amd_iommu_rlookup_table[dev_data->devid];
1848 ats = dev_data->ats.enabled;
7f760ddd
JR		 1849
1850 /* Update data structures */
1851 dev_data->domain = domain;
1852 list_add(&dev_data->list, &domain->dev_list);
f62dda66 1853 set_dte_entry(dev_data->devid, domain, ats);
7f760ddd
JR		 1854
1855 /* Do reference counting */
1856 domain->dev_iommu[iommu->index] += 1;
1857 domain->dev_cnt += 1;
1858
1859 /* Flush the DTE entry */
6c542047 1860 device_flush_dte(dev_data);
7f760ddd
JR		 1861}
1862
ec9e79ef 1863static void do_detach(struct iommu_dev_data *dev_data)
7f760ddd 1864{
7f760ddd 1865 struct amd_iommu *iommu;
7f760ddd 1866
ec9e79ef 1867 iommu = amd_iommu_rlookup_table[dev_data->devid];
15898bbc
JR		 1868
1869 /* decrease reference counters */
7f760ddd
JR		 1870 dev_data->domain->dev_iommu[iommu->index] -= 1;
1871 dev_data->domain->dev_cnt -= 1;
1872
1873 /* Update data structures */
1874 dev_data->domain = NULL;
1875 list_del(&dev_data->list);
f62dda66 1876 clear_dte_entry(dev_data->devid);
15898bbc 1877
7f760ddd 1878 /* Flush the DTE entry */
6c542047 1879 device_flush_dte(dev_data);
2b681faf
JR		 1880}
1881
1882/*
1883 * If a device is not yet associated with a domain, this function does
1884 * assigns it visible for the hardware
1885 */
ec9e79ef 1886static int __attach_device(struct iommu_dev_data *dev_data,
15898bbc 1887 struct protection_domain *domain)
2b681faf 1888{
84fe6c19 1889 int ret;
657cbb6b 1890
2b681faf
JR		 1891 /* lock domain */
1892 spin_lock(&domain->lock);
1893
71f77580
JR		 1894 if (dev_data->alias_data != NULL) {
1895 struct iommu_dev_data *alias_data = dev_data->alias_data;
15898bbc 1896
2b02b091
JR		 1897 /* Some sanity checks */
1898 ret = -EBUSY;
1899 if (alias_data->domain != NULL &&
1900 alias_data->domain != domain)
1901 goto out_unlock;
eba6ac60 1902
2b02b091
JR		 1903 if (dev_data->domain != NULL &&
1904 dev_data->domain != domain)
1905 goto out_unlock;
15898bbc 1906
2b02b091 1907 /* Do real assignment */
7f760ddd 1908 if (alias_data->domain == NULL)
ec9e79ef 1909 do_attach(alias_data, domain);
24100055
JR		 1910
1911 atomic_inc(&alias_data->bind);
657cbb6b 1912 }
15898bbc 1913
7f760ddd 1914 if (dev_data->domain == NULL)
ec9e79ef 1915 do_attach(dev_data, domain);
eba6ac60 1916
24100055
JR		 1917 atomic_inc(&dev_data->bind);
1918
84fe6c19
JL		 1919 ret = 0;
1920
1921out_unlock:
1922
eba6ac60
JR		 1923 /* ready */
1924 spin_unlock(&domain->lock);
15898bbc 1925
84fe6c19 1926 return ret;
0feae533 1927}
b20ac0d4 1928
52815b75
JR		 1929
1930static void pdev_iommuv2_disable(struct pci_dev *pdev)
1931{
1932 pci_disable_ats(pdev);
1933 pci_disable_pri(pdev);
1934 pci_disable_pasid(pdev);
1935}
1936
1937static int pdev_iommuv2_enable(struct pci_dev *pdev)
1938{
1939 int ret;
1940
1941 /* Only allow access to user-accessible pages */
1942 ret = pci_enable_pasid(pdev, 0);
1943 if (ret)
1944 goto out_err;
1945
1946 /* First reset the PRI state of the device */
1947 ret = pci_reset_pri(pdev);
1948 if (ret)
1949 goto out_err;
1950
1951 /* FIXME: Hardcode number of outstanding requests for now */
1952 ret = pci_enable_pri(pdev, 32);
1953 if (ret)
1954 goto out_err;
1955
1956 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1957 if (ret)
1958 goto out_err;
1959
1960 return 0;
1961
1962out_err:
1963 pci_disable_pri(pdev);
1964 pci_disable_pasid(pdev);
1965
1966 return ret;
1967}
1968
c99afa25
JR		 1969/* FIXME: Move this to PCI code */
1970#define PCI_PRI_TLP_OFF (1 << 2)
1971
1972bool pci_pri_tlp_required(struct pci_dev *pdev)
1973{
1974 u16 control;
1975 int pos;
1976
1977 pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
1978 if (!pos)
1979 return false;
1980
1981 pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
1982
1983 return (control & PCI_PRI_TLP_OFF) ? true : false;
1984}
1985
407d733e
JR		 1986/*
1987 * If a device is not yet associated with a domain, this function does
1988 * assigns it visible for the hardware
1989 */
15898bbc
JR		 1990static int attach_device(struct device *dev,
1991 struct protection_domain *domain)
0feae533 1992{
fd7b5535 1993 struct pci_dev *pdev = to_pci_dev(dev);
ea61cddb 1994 struct iommu_dev_data *dev_data;
eba6ac60 1995 unsigned long flags;
15898bbc 1996 int ret;
eba6ac60 1997
ea61cddb
JR		 1998 dev_data = get_dev_data(dev);
1999
52815b75
JR		 2000 if (domain->flags & PD_IOMMUV2_MASK) {
2001 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2002 return -EINVAL;
2003
2004 if (pdev_iommuv2_enable(pdev) != 0)
2005 return -EINVAL;
2006
2007 dev_data->ats.enabled = true;
2008 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
c99afa25 2009 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
52815b75
JR		 2010 } else if (amd_iommu_iotlb_sup &&
2011 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
ea61cddb
JR		 2012 dev_data->ats.enabled = true;
2013 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2014 }
fd7b5535 2015
eba6ac60 2016 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2017 ret = __attach_device(dev_data, domain);
b20ac0d4
JR		 2018 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2019
0feae533
JR		 2020 /*
2021 * We might boot into a crash-kernel here. The crashed kernel
2022 * left the caches in the IOMMU dirty. So we have to flush
2023 * here to evict all dirty stuff.
2024 */
17b124bf 2025 domain_flush_tlb_pde(domain);
15898bbc
JR		 2026
2027 return ret;
b20ac0d4
JR		 2028}
2029
355bf553
JR		 2030/*
2031 * Removes a device from a protection domain (unlocked)
2032 */
ec9e79ef 2033static void __detach_device(struct iommu_dev_data *dev_data)
355bf553 2034{
2ca76279 2035 struct protection_domain *domain;
7c392cbe 2036 unsigned long flags;
c4596114 2037
7f760ddd 2038 BUG_ON(!dev_data->domain);
355bf553 2039
2ca76279
JR		 2040 domain = dev_data->domain;
2041
2042 spin_lock_irqsave(&domain->lock, flags);
24100055 2043
71f77580
JR		 2044 if (dev_data->alias_data != NULL) {
2045 struct iommu_dev_data *alias_data = dev_data->alias_data;
2046
7f760ddd 2047 if (atomic_dec_and_test(&alias_data->bind))
ec9e79ef 2048 do_detach(alias_data);
24100055
JR		 2049 }
2050
7f760ddd 2051 if (atomic_dec_and_test(&dev_data->bind))
ec9e79ef 2052 do_detach(dev_data);
7f760ddd 2053
2ca76279 2054 spin_unlock_irqrestore(&domain->lock, flags);
21129f78
JR		 2055
2056 /*
2057 * If we run in passthrough mode the device must be assigned to the
d3ad9373
JR		 2058 * passthrough domain if it is detached from any other domain.
2059 * Make sure we can deassign from the pt_domain itself.
21129f78 2060 */
5abcdba4 2061 if (dev_data->passthrough &&
d3ad9373 2062 (dev_data->domain == NULL && domain != pt_domain))
ec9e79ef 2063 __attach_device(dev_data, pt_domain);
355bf553
JR		 2064}
2065
2066/*
2067 * Removes a device from a protection domain (with devtable_lock held)
2068 */
15898bbc 2069static void detach_device(struct device *dev)
355bf553 2070{
52815b75 2071 struct protection_domain *domain;
ea61cddb 2072 struct iommu_dev_data *dev_data;
355bf553
JR		 2073 unsigned long flags;
2074
ec9e79ef 2075 dev_data = get_dev_data(dev);
52815b75 2076 domain = dev_data->domain;
ec9e79ef 2077
355bf553
JR		 2078 /* lock device table */
2079 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2080 __detach_device(dev_data);
355bf553 2081 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
fd7b5535 2082
52815b75
JR		 2083 if (domain->flags & PD_IOMMUV2_MASK)
2084 pdev_iommuv2_disable(to_pci_dev(dev));
2085 else if (dev_data->ats.enabled)
ea61cddb 2086 pci_disable_ats(to_pci_dev(dev));
52815b75
JR		 2087
2088 dev_data->ats.enabled = false;
355bf553 2089}
e275a2a0 2090
15898bbc
JR		 2091/*
2092 * Find out the protection domain structure for a given PCI device. This
2093 * will give us the pointer to the page table root for example.
2094 */
2095static struct protection_domain *domain_for_device(struct device *dev)
2096{
71f77580 2097 struct iommu_dev_data *dev_data;
2b02b091 2098 struct protection_domain *dom = NULL;
15898bbc 2099 unsigned long flags;
15898bbc 2100
657cbb6b 2101 dev_data = get_dev_data(dev);
15898bbc 2102
2b02b091
JR		 2103 if (dev_data->domain)
2104 return dev_data->domain;
15898bbc 2105
71f77580
JR		 2106 if (dev_data->alias_data != NULL) {
2107 struct iommu_dev_data *alias_data = dev_data->alias_data;
2b02b091
JR		 2108
2109 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2110 if (alias_data->domain != NULL) {
2111 __attach_device(dev_data, alias_data->domain);
2112 dom = alias_data->domain;
2113 }
2114 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2115 }
15898bbc
JR		 2116
2117 return dom;
2118}
2119
e275a2a0
JR		 2120static int device_change_notifier(struct notifier_block *nb,
2121 unsigned long action, void *data)
2122{
e275a2a0 2123 struct dma_ops_domain *dma_domain;
5abcdba4
JR		 2124 struct protection_domain *domain;
2125 struct iommu_dev_data *dev_data;
2126 struct device *dev = data;
e275a2a0 2127 struct amd_iommu *iommu;
1ac4cbbc 2128 unsigned long flags;
5abcdba4 2129 u16 devid;
e275a2a0 2130
98fc5a69
JR		 2131 if (!check_device(dev))
2132 return 0;
e275a2a0 2133
5abcdba4
JR		 2134 devid = get_device_id(dev);
2135 iommu = amd_iommu_rlookup_table[devid];
2136 dev_data = get_dev_data(dev);
e275a2a0
JR		 2137
2138 switch (action) {
c1eee67b 2139 case BUS_NOTIFY_UNBOUND_DRIVER:
657cbb6b
JR		 2140
2141 domain = domain_for_device(dev);
2142
e275a2a0
JR		 2143 if (!domain)
2144 goto out;
5abcdba4 2145 if (dev_data->passthrough)
a1ca331c 2146 break;
15898bbc 2147 detach_device(dev);
1ac4cbbc
JR		 2148 break;
2149 case BUS_NOTIFY_ADD_DEVICE:
657cbb6b
JR		 2150
2151 iommu_init_device(dev);
2152
2153 domain = domain_for_device(dev);
2154
1ac4cbbc
JR		 2155 /* allocate a protection domain if a device is added */
2156 dma_domain = find_protection_domain(devid);
2157 if (dma_domain)
2158 goto out;
87a64d52 2159 dma_domain = dma_ops_domain_alloc();
1ac4cbbc
JR		 2160 if (!dma_domain)
2161 goto out;
2162 dma_domain->target_dev = devid;
2163
2164 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2165 list_add_tail(&dma_domain->list, &iommu_pd_list);
2166 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2167
e275a2a0 2168 break;
657cbb6b
JR		 2169 case BUS_NOTIFY_DEL_DEVICE:
2170
2171 iommu_uninit_device(dev);
2172
e275a2a0
JR		 2173 default:
2174 goto out;
2175 }
2176
e275a2a0
JR		 2177 iommu_completion_wait(iommu);
2178
2179out:
2180 return 0;
2181}
2182
b25ae679 2183static struct notifier_block device_nb = {
e275a2a0
JR		 2184 .notifier_call = device_change_notifier,
2185};
355bf553 2186
8638c491
JR		 2187void amd_iommu_init_notifier(void)
2188{
2189 bus_register_notifier(&pci_bus_type, &device_nb);
2190}
2191
431b2a20
JR		 2192/*****************************************************************************
2193 *
2194 * The next functions belong to the dma_ops mapping/unmapping code.
2195 *
2196 *****************************************************************************/
2197
2198/*
2199 * In the dma_ops path we only have the struct device. This function
2200 * finds the corresponding IOMMU, the protection domain and the
2201 * requestor id for a given device.
2202 * If the device is not yet associated with a domain this is also done
2203 * in this function.
2204 */
94f6d190 2205static struct protection_domain *get_domain(struct device *dev)
b20ac0d4 2206{
94f6d190 2207 struct protection_domain *domain;
b20ac0d4 2208 struct dma_ops_domain *dma_dom;
94f6d190 2209 u16 devid = get_device_id(dev);
b20ac0d4 2210
f99c0f1c 2211 if (!check_device(dev))
94f6d190 2212 return ERR_PTR(-EINVAL);
b20ac0d4 2213
94f6d190
JR		 2214 domain = domain_for_device(dev);
2215 if (domain != NULL && !dma_ops_domain(domain))
2216 return ERR_PTR(-EBUSY);
f99c0f1c 2217
94f6d190
JR		 2218 if (domain != NULL)
2219 return domain;
b20ac0d4 2220
15898bbc 2221 /* Device not bount yet - bind it */
94f6d190 2222 dma_dom = find_protection_domain(devid);
15898bbc 2223 if (!dma_dom)
94f6d190
JR		 2224 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2225 attach_device(dev, &dma_dom->domain);
15898bbc 2226 DUMP_printk("Using protection domain %d for device %s\n",
94f6d190 2227 dma_dom->domain.id, dev_name(dev));
f91ba190 2228
94f6d190 2229 return &dma_dom->domain;
b20ac0d4
JR		 2230}
2231
04bfdd84
JR		 2232static void update_device_table(struct protection_domain *domain)
2233{
492667da 2234 struct iommu_dev_data *dev_data;
04bfdd84 2235
ea61cddb
JR		 2236 list_for_each_entry(dev_data, &domain->dev_list, list)
2237 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
04bfdd84
JR		 2238}
2239
2240static void update_domain(struct protection_domain *domain)
2241{
2242 if (!domain->updated)
2243 return;
2244
2245 update_device_table(domain);
17b124bf
JR		 2246
2247 domain_flush_devices(domain);
2248 domain_flush_tlb_pde(domain);
04bfdd84
JR		 2249
2250 domain->updated = false;
2251}
2252
8bda3092
JR		 2253/*
2254 * This function fetches the PTE for a given address in the aperture
2255 */
2256static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2257 unsigned long address)
2258{
384de729 2259 struct aperture_range *aperture;
8bda3092
JR		 2260 u64 *pte, *pte_page;
2261
384de729
JR		 2262 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2263 if (!aperture)
2264 return NULL;
2265
2266 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
8bda3092 2267 if (!pte) {
cbb9d729 2268 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
abdc5eb3 2269 GFP_ATOMIC);
384de729
JR		 2270 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2271 } else
8c8c143c 2272 pte += PM_LEVEL_INDEX(0, address);
8bda3092 2273
04bfdd84 2274 update_domain(&dom->domain);
8bda3092
JR		 2275
2276 return pte;
2277}
2278
431b2a20
JR		 2279/*
2280 * This is the generic map function. It maps one 4kb page at paddr to
2281 * the given address in the DMA address space for the domain.
2282 */
680525e0 2283static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
cb76c322
JR		 2284 unsigned long address,
2285 phys_addr_t paddr,
2286 int direction)
2287{
2288 u64 *pte, __pte;
2289
2290 WARN_ON(address > dom->aperture_size);
2291
2292 paddr &= PAGE_MASK;
2293
8bda3092 2294 pte = dma_ops_get_pte(dom, address);
53812c11 2295 if (!pte)
8fd524b3 2296 return DMA_ERROR_CODE;
cb76c322
JR		 2297
2298 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2299
2300 if (direction == DMA_TO_DEVICE)
2301 __pte |= IOMMU_PTE_IR;
2302 else if (direction == DMA_FROM_DEVICE)
2303 __pte |= IOMMU_PTE_IW;
2304 else if (direction == DMA_BIDIRECTIONAL)
2305 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2306
2307 WARN_ON(*pte);
2308
2309 *pte = __pte;
2310
2311 return (dma_addr_t)address;
2312}
2313
431b2a20
JR		 2314/*
2315 * The generic unmapping function for on page in the DMA address space.
2316 */
680525e0 2317static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
cb76c322
JR		 2318 unsigned long address)
2319{
384de729 2320 struct aperture_range *aperture;
cb76c322
JR		 2321 u64 *pte;
2322
2323 if (address >= dom->aperture_size)
2324 return;
2325
384de729
JR		 2326 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2327 if (!aperture)
2328 return;
2329
2330 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2331 if (!pte)
2332 return;
cb76c322 2333
8c8c143c 2334 pte += PM_LEVEL_INDEX(0, address);
cb76c322
JR		 2335
2336 WARN_ON(!*pte);
2337
2338 *pte = 0ULL;
2339}
2340
431b2a20
JR		 2341/*
2342 * This function contains common code for mapping of a physically
24f81160
JR		 2343 * contiguous memory region into DMA address space. It is used by all
2344 * mapping functions provided with this IOMMU driver.
431b2a20
JR		 2345 * Must be called with the domain lock held.
2346 */
cb76c322 2347static dma_addr_t __map_single(struct device *dev,
cb76c322
JR		 2348 struct dma_ops_domain *dma_dom,
2349 phys_addr_t paddr,
2350 size_t size,
6d4f343f 2351 int dir,
832a90c3
JR		 2352 bool align,
2353 u64 dma_mask)
cb76c322
JR		 2354{
2355 dma_addr_t offset = paddr & ~PAGE_MASK;
53812c11 2356 dma_addr_t address, start, ret;
cb76c322 2357 unsigned int pages;
6d4f343f 2358 unsigned long align_mask = 0;
cb76c322
JR		 2359 int i;
2360
e3c449f5 2361 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
cb76c322
JR		 2362 paddr &= PAGE_MASK;
2363
8ecaf8f1
JR		 2364 INC_STATS_COUNTER(total_map_requests);
2365
c1858976
JR		 2366 if (pages > 1)
2367 INC_STATS_COUNTER(cross_page);
2368
6d4f343f
JR		 2369 if (align)
2370 align_mask = (1UL << get_order(size)) - 1;
2371
11b83888 2372retry:
832a90c3
JR		 2373 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2374 dma_mask);
8fd524b3 2375 if (unlikely(address == DMA_ERROR_CODE)) {
11b83888
JR		 2376 /*
2377 * setting next_address here will let the address
2378 * allocator only scan the new allocated range in the
2379 * first run. This is a small optimization.
2380 */
2381 dma_dom->next_address = dma_dom->aperture_size;
2382
576175c2 2383 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
11b83888
JR		 2384 goto out;
2385
2386 /*
af901ca1 2387 * aperture was successfully enlarged by 128 MB, try
11b83888
JR		 2388 * allocation again
2389 */
2390 goto retry;
2391 }
cb76c322
JR		 2392
2393 start = address;
2394 for (i = 0; i < pages; ++i) {
680525e0 2395 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
8fd524b3 2396 if (ret == DMA_ERROR_CODE)
53812c11
JR		 2397 goto out_unmap;
2398
cb76c322
JR		 2399 paddr += PAGE_SIZE;
2400 start += PAGE_SIZE;
2401 }
2402 address += offset;
2403
5774f7c5
JR		 2404 ADD_STATS_COUNTER(alloced_io_mem, size);
2405
afa9fdc2 2406 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
17b124bf 2407 domain_flush_tlb(&dma_dom->domain);
1c655773 2408 dma_dom->need_flush = false;
318afd41 2409 } else if (unlikely(amd_iommu_np_cache))
17b124bf 2410 domain_flush_pages(&dma_dom->domain, address, size);
270cab24 2411
cb76c322
JR		 2412out:
2413 return address;
53812c11
JR		 2414
2415out_unmap:
2416
2417 for (--i; i >= 0; --i) {
2418 start -= PAGE_SIZE;
680525e0 2419 dma_ops_domain_unmap(dma_dom, start);
53812c11
JR		 2420 }
2421
2422 dma_ops_free_addresses(dma_dom, address, pages);
2423
8fd524b3 2424 return DMA_ERROR_CODE;
cb76c322
JR		 2425}
2426
431b2a20
JR		 2427/*
2428 * Does the reverse of the __map_single function. Must be called with
2429 * the domain lock held too
2430 */
cd8c82e8 2431static void __unmap_single(struct dma_ops_domain *dma_dom,
cb76c322
JR		 2432 dma_addr_t dma_addr,
2433 size_t size,
2434 int dir)
2435{
04e0463e 2436 dma_addr_t flush_addr;
cb76c322
JR		 2437 dma_addr_t i, start;
2438 unsigned int pages;
2439
8fd524b3 2440 if ((dma_addr == DMA_ERROR_CODE) ||
b8d9905d 2441 (dma_addr + size > dma_dom->aperture_size))
cb76c322
JR		 2442 return;
2443
04e0463e 2444 flush_addr = dma_addr;
e3c449f5 2445 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
cb76c322
JR		 2446 dma_addr &= PAGE_MASK;
2447 start = dma_addr;
2448
2449 for (i = 0; i < pages; ++i) {
680525e0 2450 dma_ops_domain_unmap(dma_dom, start);
cb76c322
JR		 2451 start += PAGE_SIZE;
2452 }
2453
5774f7c5
JR		 2454 SUB_STATS_COUNTER(alloced_io_mem, size);
2455
cb76c322 2456 dma_ops_free_addresses(dma_dom, dma_addr, pages);
270cab24 2457
80be308d 2458 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
17b124bf 2459 domain_flush_pages(&dma_dom->domain, flush_addr, size);
80be308d
JR		 2460 dma_dom->need_flush = false;
2461 }
cb76c322
JR		 2462}
2463
431b2a20
JR		 2464/*
2465 * The exported map_single function for dma_ops.
2466 */
51491367
FT		 2467static dma_addr_t map_page(struct device *dev, struct page *page,
2468 unsigned long offset, size_t size,
2469 enum dma_data_direction dir,
2470 struct dma_attrs *attrs)
4da70b9e
JR		 2471{
2472 unsigned long flags;
4da70b9e 2473 struct protection_domain *domain;
4da70b9e 2474 dma_addr_t addr;
832a90c3 2475 u64 dma_mask;
51491367 2476 phys_addr_t paddr = page_to_phys(page) + offset;
4da70b9e 2477
0f2a86f2
JR		 2478 INC_STATS_COUNTER(cnt_map_single);
2479
94f6d190
JR		 2480 domain = get_domain(dev);
2481 if (PTR_ERR(domain) == -EINVAL)
4da70b9e 2482 return (dma_addr_t)paddr;
94f6d190
JR		 2483 else if (IS_ERR(domain))
2484 return DMA_ERROR_CODE;
4da70b9e 2485
f99c0f1c
JR		 2486 dma_mask = *dev->dma_mask;
2487
4da70b9e 2488 spin_lock_irqsave(&domain->lock, flags);
94f6d190 2489
cd8c82e8 2490 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
832a90c3 2491 dma_mask);
8fd524b3 2492 if (addr == DMA_ERROR_CODE)
4da70b9e
JR		 2493 goto out;
2494
17b124bf 2495 domain_flush_complete(domain);
4da70b9e
JR		 2496
2497out:
2498 spin_unlock_irqrestore(&domain->lock, flags);
2499
2500 return addr;
2501}
2502
431b2a20
JR		 2503/*
2504 * The exported unmap_single function for dma_ops.
2505 */
51491367
FT		 2506static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2507 enum dma_data_direction dir, struct dma_attrs *attrs)
4da70b9e
JR		 2508{
2509 unsigned long flags;
4da70b9e 2510 struct protection_domain *domain;
4da70b9e 2511
146a6917
JR		 2512 INC_STATS_COUNTER(cnt_unmap_single);
2513
94f6d190
JR		 2514 domain = get_domain(dev);
2515 if (IS_ERR(domain))
5b28df6f
JR		 2516 return;
2517
4da70b9e
JR		 2518 spin_lock_irqsave(&domain->lock, flags);
2519
cd8c82e8 2520 __unmap_single(domain->priv, dma_addr, size, dir);
4da70b9e 2521
17b124bf 2522 domain_flush_complete(domain);
4da70b9e
JR		 2523
2524 spin_unlock_irqrestore(&domain->lock, flags);
2525}
2526
431b2a20
JR		 2527/*
2528 * This is a special map_sg function which is used if we should map a
2529 * device which is not handled by an AMD IOMMU in the system.
2530 */
65b050ad
JR		 2531static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2532 int nelems, int dir)
2533{
2534 struct scatterlist *s;
2535 int i;
2536
2537 for_each_sg(sglist, s, nelems, i) {
2538 s->dma_address = (dma_addr_t)sg_phys(s);
2539 s->dma_length = s->length;
2540 }
2541
2542 return nelems;
2543}
2544
431b2a20
JR		 2545/*
2546 * The exported map_sg function for dma_ops (handles scatter-gather
2547 * lists).
2548 */
65b050ad 2549static int map_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2550 int nelems, enum dma_data_direction dir,
2551 struct dma_attrs *attrs)
65b050ad
JR		 2552{
2553 unsigned long flags;
65b050ad 2554 struct protection_domain *domain;
65b050ad
JR		 2555 int i;
2556 struct scatterlist *s;
2557 phys_addr_t paddr;
2558 int mapped_elems = 0;
832a90c3 2559 u64 dma_mask;
65b050ad 2560
d03f067a
JR		 2561 INC_STATS_COUNTER(cnt_map_sg);
2562
94f6d190
JR		 2563 domain = get_domain(dev);
2564 if (PTR_ERR(domain) == -EINVAL)
f99c0f1c 2565 return map_sg_no_iommu(dev, sglist, nelems, dir);
94f6d190
JR		 2566 else if (IS_ERR(domain))
2567 return 0;
dbcc112e 2568
832a90c3 2569 dma_mask = *dev->dma_mask;
65b050ad 2570
65b050ad
JR		 2571 spin_lock_irqsave(&domain->lock, flags);
2572
2573 for_each_sg(sglist, s, nelems, i) {
2574 paddr = sg_phys(s);
2575
cd8c82e8 2576 s->dma_address = __map_single(dev, domain->priv,
832a90c3
JR		 2577 paddr, s->length, dir, false,
2578 dma_mask);
65b050ad
JR		 2579
2580 if (s->dma_address) {
2581 s->dma_length = s->length;
2582 mapped_elems++;
2583 } else
2584 goto unmap;
65b050ad
JR		 2585 }
2586
17b124bf 2587 domain_flush_complete(domain);
65b050ad
JR		 2588
2589out:
2590 spin_unlock_irqrestore(&domain->lock, flags);
2591
2592 return mapped_elems;
2593unmap:
2594 for_each_sg(sglist, s, mapped_elems, i) {
2595 if (s->dma_address)
cd8c82e8 2596 __unmap_single(domain->priv, s->dma_address,
65b050ad
JR		 2597 s->dma_length, dir);
2598 s->dma_address = s->dma_length = 0;
2599 }
2600
2601 mapped_elems = 0;
2602
2603 goto out;
2604}
2605
431b2a20
JR		 2606/*
2607 * The exported map_sg function for dma_ops (handles scatter-gather
2608 * lists).
2609 */
65b050ad 2610static void unmap_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2611 int nelems, enum dma_data_direction dir,
2612 struct dma_attrs *attrs)
65b050ad
JR		 2613{
2614 unsigned long flags;
65b050ad
JR		 2615 struct protection_domain *domain;
2616 struct scatterlist *s;
65b050ad
JR		 2617 int i;
2618
55877a6b
JR		 2619 INC_STATS_COUNTER(cnt_unmap_sg);
2620
94f6d190
JR		 2621 domain = get_domain(dev);
2622 if (IS_ERR(domain))
5b28df6f
JR		 2623 return;
2624
65b050ad
JR		 2625 spin_lock_irqsave(&domain->lock, flags);
2626
2627 for_each_sg(sglist, s, nelems, i) {
cd8c82e8 2628 __unmap_single(domain->priv, s->dma_address,
65b050ad 2629 s->dma_length, dir);
65b050ad
JR		 2630 s->dma_address = s->dma_length = 0;
2631 }
2632
17b124bf 2633 domain_flush_complete(domain);
65b050ad
JR		 2634
2635 spin_unlock_irqrestore(&domain->lock, flags);
2636}
2637
431b2a20
JR		 2638/*
2639 * The exported alloc_coherent function for dma_ops.
2640 */
5d8b53cf
JR		 2641static void *alloc_coherent(struct device *dev, size_t size,
2642 dma_addr_t *dma_addr, gfp_t flag)
2643{
2644 unsigned long flags;
2645 void *virt_addr;
5d8b53cf 2646 struct protection_domain *domain;
5d8b53cf 2647 phys_addr_t paddr;
832a90c3 2648 u64 dma_mask = dev->coherent_dma_mask;
5d8b53cf 2649
c8f0fb36
JR		 2650 INC_STATS_COUNTER(cnt_alloc_coherent);
2651
94f6d190
JR		 2652 domain = get_domain(dev);
2653 if (PTR_ERR(domain) == -EINVAL) {
f99c0f1c
JR		 2654 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2655 *dma_addr = __pa(virt_addr);
2656 return virt_addr;
94f6d190
JR		 2657 } else if (IS_ERR(domain))
2658 return NULL;
5d8b53cf 2659
f99c0f1c
JR		 2660 dma_mask = dev->coherent_dma_mask;
2661 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2662 flag |= __GFP_ZERO;
5d8b53cf
JR		 2663
2664 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2665 if (!virt_addr)
b25ae679 2666 return NULL;
5d8b53cf 2667
5d8b53cf
JR		 2668 paddr = virt_to_phys(virt_addr);
2669
832a90c3
JR		 2670 if (!dma_mask)
2671 dma_mask = *dev->dma_mask;
2672
5d8b53cf
JR		 2673 spin_lock_irqsave(&domain->lock, flags);
2674
cd8c82e8 2675 *dma_addr = __map_single(dev, domain->priv, paddr,
832a90c3 2676 size, DMA_BIDIRECTIONAL, true, dma_mask);
5d8b53cf 2677
8fd524b3 2678 if (*dma_addr == DMA_ERROR_CODE) {
367d04c4 2679 spin_unlock_irqrestore(&domain->lock, flags);
5b28df6f 2680 goto out_free;
367d04c4 2681 }
5d8b53cf 2682
17b124bf 2683 domain_flush_complete(domain);
5d8b53cf 2684
5d8b53cf
JR		 2685 spin_unlock_irqrestore(&domain->lock, flags);
2686
2687 return virt_addr;
5b28df6f
JR		 2688
2689out_free:
2690
2691 free_pages((unsigned long)virt_addr, get_order(size));
2692
2693 return NULL;
5d8b53cf
JR		 2694}
2695
431b2a20
JR		 2696/*
2697 * The exported free_coherent function for dma_ops.
431b2a20 2698 */
5d8b53cf
JR		 2699static void free_coherent(struct device *dev, size_t size,
2700 void *virt_addr, dma_addr_t dma_addr)
2701{
2702 unsigned long flags;
5d8b53cf 2703 struct protection_domain *domain;
5d8b53cf 2704
5d31ee7e
JR		 2705 INC_STATS_COUNTER(cnt_free_coherent);
2706
94f6d190
JR		 2707 domain = get_domain(dev);
2708 if (IS_ERR(domain))
5b28df6f
JR		 2709 goto free_mem;
2710
5d8b53cf
JR		 2711 spin_lock_irqsave(&domain->lock, flags);
2712
cd8c82e8 2713 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
5d8b53cf 2714
17b124bf 2715 domain_flush_complete(domain);
5d8b53cf
JR		 2716
2717 spin_unlock_irqrestore(&domain->lock, flags);
2718
2719free_mem:
2720 free_pages((unsigned long)virt_addr, get_order(size));
2721}
2722
b39ba6ad
JR		 2723/*
2724 * This function is called by the DMA layer to find out if we can handle a
2725 * particular device. It is part of the dma_ops.
2726 */
2727static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2728{
420aef8a 2729 return check_device(dev);
b39ba6ad
JR		 2730}
2731
c432f3df 2732/*
431b2a20
JR		 2733 * The function for pre-allocating protection domains.
2734 *
c432f3df
JR		 2735 * If the driver core informs the DMA layer if a driver grabs a device
2736 * we don't need to preallocate the protection domains anymore.
2737 * For now we have to.
2738 */
0e93dd88 2739static void prealloc_protection_domains(void)
c432f3df 2740{
5abcdba4 2741 struct iommu_dev_data *dev_data;
c432f3df 2742 struct dma_ops_domain *dma_dom;
5abcdba4 2743 struct pci_dev *dev = NULL;
98fc5a69 2744 u16 devid;
c432f3df 2745
d18c69d3 2746 for_each_pci_dev(dev) {
98fc5a69
JR		 2747
2748 /* Do we handle this device? */
2749 if (!check_device(&dev->dev))
c432f3df 2750 continue;
98fc5a69 2751
5abcdba4
JR		 2752 dev_data = get_dev_data(&dev->dev);
2753 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
2754 /* Make sure passthrough domain is allocated */
2755 alloc_passthrough_domain();
2756 dev_data->passthrough = true;
2757 attach_device(&dev->dev, pt_domain);
2758 pr_info("AMD-Vi: Using passthough domain for device %s\n",
2759 dev_name(&dev->dev));
2760 }
2761
98fc5a69 2762 /* Is there already any domain for it? */
15898bbc 2763 if (domain_for_device(&dev->dev))
c432f3df 2764 continue;
98fc5a69
JR		 2765
2766 devid = get_device_id(&dev->dev);
2767
87a64d52 2768 dma_dom = dma_ops_domain_alloc();
c432f3df
JR		 2769 if (!dma_dom)
2770 continue;
2771 init_unity_mappings_for_device(dma_dom, devid);
bd60b735
JR		 2772 dma_dom->target_dev = devid;
2773
15898bbc 2774 attach_device(&dev->dev, &dma_dom->domain);
be831297 2775
bd60b735 2776 list_add_tail(&dma_dom->list, &iommu_pd_list);
c432f3df
JR		 2777 }
2778}
2779
160c1d8e 2780static struct dma_map_ops amd_iommu_dma_ops = {
6631ee9d
JR		 2781 .alloc_coherent = alloc_coherent,
2782 .free_coherent = free_coherent,
51491367
FT		 2783 .map_page = map_page,
2784 .unmap_page = unmap_page,
6631ee9d
JR		 2785 .map_sg = map_sg,
2786 .unmap_sg = unmap_sg,
b39ba6ad 2787 .dma_supported = amd_iommu_dma_supported,
6631ee9d
JR		 2788};
2789
27c2127a
JR		 2790static unsigned device_dma_ops_init(void)
2791{
5abcdba4 2792 struct iommu_dev_data *dev_data;
27c2127a
JR		 2793 struct pci_dev *pdev = NULL;
2794 unsigned unhandled = 0;
2795
2796 for_each_pci_dev(pdev) {
2797 if (!check_device(&pdev->dev)) {
2798 unhandled += 1;
2799 continue;
2800 }
2801
5abcdba4
JR		 2802 dev_data = get_dev_data(&pdev->dev);
2803
2804 if (!dev_data->passthrough)
2805 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2806 else
2807 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
27c2127a
JR		 2808 }
2809
2810 return unhandled;
2811}
2812
431b2a20
JR		 2813/*
2814 * The function which clues the AMD IOMMU driver into dma_ops.
2815 */
f5325094
JR		 2816
2817void __init amd_iommu_init_api(void)
2818{
2cc21c42 2819 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
f5325094
JR		 2820}
2821
6631ee9d
JR		 2822int __init amd_iommu_init_dma_ops(void)
2823{
2824 struct amd_iommu *iommu;
27c2127a 2825 int ret, unhandled;
6631ee9d 2826
431b2a20
JR		 2827 /*
2828 * first allocate a default protection domain for every IOMMU we
2829 * found in the system. Devices not assigned to any other
2830 * protection domain will be assigned to the default one.
2831 */
3bd22172 2832 for_each_iommu(iommu) {
87a64d52 2833 iommu->default_dom = dma_ops_domain_alloc();
6631ee9d
JR		 2834 if (iommu->default_dom == NULL)
2835 return -ENOMEM;
e2dc14a2 2836 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
6631ee9d
JR		 2837 ret = iommu_init_unity_mappings(iommu);
2838 if (ret)
2839 goto free_domains;
2840 }
2841
431b2a20 2842 /*
8793abeb 2843 * Pre-allocate the protection domains for each device.
431b2a20 2844 */
8793abeb 2845 prealloc_protection_domains();
6631ee9d
JR		 2846
2847 iommu_detected = 1;
75f1cdf1 2848 swiotlb = 0;
6631ee9d 2849
431b2a20 2850 /* Make the driver finally visible to the drivers */
27c2127a
JR		 2851 unhandled = device_dma_ops_init();
2852 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2853 /* There are unhandled devices - initialize swiotlb for them */
2854 swiotlb = 1;
2855 }
6631ee9d 2856
7f26508b
JR		 2857 amd_iommu_stats_init();
2858
6631ee9d
JR		 2859 return 0;
2860
2861free_domains:
2862
3bd22172 2863 for_each_iommu(iommu) {
6631ee9d
JR		 2864 if (iommu->default_dom)
2865 dma_ops_domain_free(iommu->default_dom);
2866 }
2867
2868 return ret;
2869}
6d98cd80
JR		 2870
2871/*****************************************************************************
2872 *
2873 * The following functions belong to the exported interface of AMD IOMMU
2874 *
2875 * This interface allows access to lower level functions of the IOMMU
2876 * like protection domain handling and assignement of devices to domains
2877 * which is not possible with the dma_ops interface.
2878 *
2879 *****************************************************************************/
2880
6d98cd80
JR		 2881static void cleanup_domain(struct protection_domain *domain)
2882{
492667da 2883 struct iommu_dev_data *dev_data, *next;
6d98cd80 2884 unsigned long flags;
6d98cd80
JR		 2885
2886 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2887
492667da 2888 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
ec9e79ef 2889 __detach_device(dev_data);
492667da
JR		 2890 atomic_set(&dev_data->bind, 0);
2891 }
6d98cd80
JR		 2892
2893 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2894}
2895
2650815f
JR		 2896static void protection_domain_free(struct protection_domain *domain)
2897{
2898 if (!domain)
2899 return;
2900
aeb26f55
JR		 2901 del_domain_from_list(domain);
2902
2650815f
JR		 2903 if (domain->id)
2904 domain_id_free(domain->id);
2905
2906 kfree(domain);
2907}
2908
2909static struct protection_domain *protection_domain_alloc(void)
c156e347
JR		 2910{
2911 struct protection_domain *domain;
2912
2913 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2914 if (!domain)
2650815f 2915 return NULL;
c156e347
JR		 2916
2917 spin_lock_init(&domain->lock);
5d214fe6 2918 mutex_init(&domain->api_lock);
c156e347
JR		 2919 domain->id = domain_id_alloc();
2920 if (!domain->id)
2650815f 2921 goto out_err;
7c392cbe 2922 INIT_LIST_HEAD(&domain->dev_list);
2650815f 2923
aeb26f55
JR		 2924 add_domain_to_list(domain);
2925
2650815f
JR		 2926 return domain;
2927
2928out_err:
2929 kfree(domain);
2930
2931 return NULL;
2932}
2933
5abcdba4
JR		 2934static int __init alloc_passthrough_domain(void)
2935{
2936 if (pt_domain != NULL)
2937 return 0;
2938
2939 /* allocate passthrough domain */
2940 pt_domain = protection_domain_alloc();
2941 if (!pt_domain)
2942 return -ENOMEM;
2943
2944 pt_domain->mode = PAGE_MODE_NONE;
2945
2946 return 0;
2947}
2650815f
JR		 2948static int amd_iommu_domain_init(struct iommu_domain *dom)
2949{
2950 struct protection_domain *domain;
2951
2952 domain = protection_domain_alloc();
2953 if (!domain)
c156e347 2954 goto out_free;
2650815f
JR		 2955
2956 domain->mode = PAGE_MODE_3_LEVEL;
c156e347
JR		 2957 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2958 if (!domain->pt_root)
2959 goto out_free;
2960
2961 dom->priv = domain;
2962
2963 return 0;
2964
2965out_free:
2650815f 2966 protection_domain_free(domain);
c156e347
JR		 2967
2968 return -ENOMEM;
2969}
2970
98383fc3
JR		 2971static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2972{
2973 struct protection_domain *domain = dom->priv;
2974
2975 if (!domain)
2976 return;
2977
2978 if (domain->dev_cnt > 0)
2979 cleanup_domain(domain);
2980
2981 BUG_ON(domain->dev_cnt != 0);
2982
132bd68f
JR		 2983 if (domain->mode != PAGE_MODE_NONE)
2984 free_pagetable(domain);
98383fc3 2985
52815b75
JR		 2986 if (domain->flags & PD_IOMMUV2_MASK)
2987 free_gcr3_table(domain);
2988
8b408fe4 2989 protection_domain_free(domain);
98383fc3
JR		 2990
2991 dom->priv = NULL;
2992}
2993
684f2888
JR		 2994static void amd_iommu_detach_device(struct iommu_domain *dom,
2995 struct device *dev)
2996{
657cbb6b 2997 struct iommu_dev_data *dev_data = dev->archdata.iommu;
684f2888 2998 struct amd_iommu *iommu;
684f2888
JR		 2999 u16 devid;
3000
98fc5a69 3001 if (!check_device(dev))
684f2888
JR		 3002 return;
3003
98fc5a69 3004 devid = get_device_id(dev);
684f2888 3005
657cbb6b 3006 if (dev_data->domain != NULL)
15898bbc 3007 detach_device(dev);
684f2888
JR		 3008
3009 iommu = amd_iommu_rlookup_table[devid];
3010 if (!iommu)
3011 return;
3012
684f2888
JR		 3013 iommu_completion_wait(iommu);
3014}
3015
01106066
JR		 3016static int amd_iommu_attach_device(struct iommu_domain *dom,
3017 struct device *dev)
3018{
3019 struct protection_domain *domain = dom->priv;
657cbb6b 3020 struct iommu_dev_data *dev_data;
01106066 3021 struct amd_iommu *iommu;
15898bbc 3022 int ret;
01106066 3023
98fc5a69 3024 if (!check_device(dev))
01106066
JR		 3025 return -EINVAL;
3026
657cbb6b
JR		 3027 dev_data = dev->archdata.iommu;
3028
f62dda66 3029 iommu = amd_iommu_rlookup_table[dev_data->devid];
01106066
JR		 3030 if (!iommu)
3031 return -EINVAL;
3032
657cbb6b 3033 if (dev_data->domain)
15898bbc 3034 detach_device(dev);
01106066 3035
15898bbc 3036 ret = attach_device(dev, domain);
01106066
JR		 3037
3038 iommu_completion_wait(iommu);
3039
15898bbc 3040 return ret;
01106066
JR		 3041}
3042
468e2366
JR		 3043static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3044 phys_addr_t paddr, int gfp_order, int iommu_prot)
c6229ca6 3045{
468e2366 3046 unsigned long page_size = 0x1000UL << gfp_order;
c6229ca6 3047 struct protection_domain *domain = dom->priv;
c6229ca6
JR		 3048 int prot = 0;
3049 int ret;
3050
132bd68f
JR		 3051 if (domain->mode == PAGE_MODE_NONE)
3052 return -EINVAL;
3053
c6229ca6
JR		 3054 if (iommu_prot & IOMMU_READ)
3055 prot |= IOMMU_PROT_IR;
3056 if (iommu_prot & IOMMU_WRITE)
3057 prot |= IOMMU_PROT_IW;
3058
5d214fe6 3059 mutex_lock(&domain->api_lock);
795e74f7 3060 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
5d214fe6
JR		 3061 mutex_unlock(&domain->api_lock);
3062
795e74f7 3063 return ret;
c6229ca6
JR		 3064}
3065
468e2366
JR		 3066static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3067 int gfp_order)
eb74ff6c 3068{
eb74ff6c 3069 struct protection_domain *domain = dom->priv;
468e2366 3070 unsigned long page_size, unmap_size;
eb74ff6c 3071
132bd68f
JR		 3072 if (domain->mode == PAGE_MODE_NONE)
3073 return -EINVAL;
3074
468e2366 3075 page_size = 0x1000UL << gfp_order;
eb74ff6c 3076
5d214fe6 3077 mutex_lock(&domain->api_lock);
468e2366 3078 unmap_size = iommu_unmap_page(domain, iova, page_size);
795e74f7 3079 mutex_unlock(&domain->api_lock);
eb74ff6c 3080
17b124bf 3081 domain_flush_tlb_pde(domain);
5d214fe6 3082
468e2366 3083 return get_order(unmap_size);
eb74ff6c
JR		 3084}
3085
645c4c8d
JR		 3086static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3087 unsigned long iova)
3088{
3089 struct protection_domain *domain = dom->priv;
f03152bb 3090 unsigned long offset_mask;
645c4c8d 3091 phys_addr_t paddr;
f03152bb 3092 u64 *pte, __pte;
645c4c8d 3093
132bd68f
JR		 3094 if (domain->mode == PAGE_MODE_NONE)
3095 return iova;
3096
24cd7723 3097 pte = fetch_pte(domain, iova);
645c4c8d 3098
a6d41a40 3099 if (!pte || !IOMMU_PTE_PRESENT(*pte))
645c4c8d
JR		 3100 return 0;
3101
f03152bb
JR		 3102 if (PM_PTE_LEVEL(*pte) == 0)
3103 offset_mask = PAGE_SIZE - 1;
3104 else
3105 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3106
3107 __pte = *pte & PM_ADDR_MASK;
3108 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
645c4c8d
JR		 3109
3110 return paddr;
3111}
3112
dbb9fd86
SY		 3113static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3114 unsigned long cap)
3115{
80a506b8
JR		 3116 switch (cap) {
3117 case IOMMU_CAP_CACHE_COHERENCY:
3118 return 1;
3119 }
3120
dbb9fd86
SY		 3121 return 0;
3122}
3123
26961efe
JR		 3124static struct iommu_ops amd_iommu_ops = {
3125 .domain_init = amd_iommu_domain_init,
3126 .domain_destroy = amd_iommu_domain_destroy,
3127 .attach_dev = amd_iommu_attach_device,
3128 .detach_dev = amd_iommu_detach_device,
468e2366
JR		 3129 .map = amd_iommu_map,
3130 .unmap = amd_iommu_unmap,
26961efe 3131 .iova_to_phys = amd_iommu_iova_to_phys,
dbb9fd86 3132 .domain_has_cap = amd_iommu_domain_has_cap,
26961efe
JR		 3133};
3134
0feae533
JR		 3135/*****************************************************************************
3136 *
3137 * The next functions do a basic initialization of IOMMU for pass through
3138 * mode
3139 *
3140 * In passthrough mode the IOMMU is initialized and enabled but not used for
3141 * DMA-API translation.
3142 *
3143 *****************************************************************************/
3144
3145int __init amd_iommu_init_passthrough(void)
3146{
5abcdba4 3147 struct iommu_dev_data *dev_data;
0feae533 3148 struct pci_dev *dev = NULL;
5abcdba4 3149 struct amd_iommu *iommu;
15898bbc 3150 u16 devid;
5abcdba4 3151 int ret;
0feae533 3152
5abcdba4
JR		 3153 ret = alloc_passthrough_domain();
3154 if (ret)
3155 return ret;
0feae533 3156
6c54aabd 3157 for_each_pci_dev(dev) {
98fc5a69 3158 if (!check_device(&dev->dev))
0feae533
JR		 3159 continue;
3160
5abcdba4
JR		 3161 dev_data = get_dev_data(&dev->dev);
3162 dev_data->passthrough = true;
3163
98fc5a69
JR		 3164 devid = get_device_id(&dev->dev);
3165
15898bbc 3166 iommu = amd_iommu_rlookup_table[devid];
0feae533
JR		 3167 if (!iommu)
3168 continue;
3169
15898bbc 3170 attach_device(&dev->dev, pt_domain);
0feae533
JR		 3171 }
3172
3173 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3174
3175 return 0;
3176}
72e1dcc4
JR		 3177
3178/* IOMMUv2 specific functions */
3179int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3180{
3181 return atomic_notifier_chain_register(&ppr_notifier, nb);
3182}
3183EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3184
3185int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3186{
3187 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3188}
3189EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
132bd68f
JR		 3190
3191void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3192{
3193 struct protection_domain *domain = dom->priv;
3194 unsigned long flags;
3195
3196 spin_lock_irqsave(&domain->lock, flags);
3197
3198 /* Update data structure */
3199 domain->mode = PAGE_MODE_NONE;
3200 domain->updated = true;
3201
3202 /* Make changes visible to IOMMUs */
3203 update_domain(domain);
3204
3205 /* Page-table is not visible to IOMMU anymore, so free it */
3206 free_pagetable(domain);
3207
3208 spin_unlock_irqrestore(&domain->lock, flags);
3209}
3210EXPORT_SYMBOL(amd_iommu_domain_direct_map);
52815b75
JR		 3211
3212int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3213{
3214 struct protection_domain *domain = dom->priv;
3215 unsigned long flags;
3216 int levels, ret;
3217
3218 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3219 return -EINVAL;
3220
3221 /* Number of GCR3 table levels required */
3222 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3223 levels += 1;
3224
3225 if (levels > amd_iommu_max_glx_val)
3226 return -EINVAL;
3227
3228 spin_lock_irqsave(&domain->lock, flags);
3229
3230 /*
3231 * Save us all sanity checks whether devices already in the
3232 * domain support IOMMUv2. Just force that the domain has no
3233 * devices attached when it is switched into IOMMUv2 mode.
3234 */
3235 ret = -EBUSY;
3236 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3237 goto out;
3238
3239 ret = -ENOMEM;
3240 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3241 if (domain->gcr3_tbl == NULL)
3242 goto out;
3243
3244 domain->glx = levels;
3245 domain->flags |= PD_IOMMUV2_MASK;
3246 domain->updated = true;
3247
3248 update_domain(domain);
3249
3250 ret = 0;
3251
3252out:
3253 spin_unlock_irqrestore(&domain->lock, flags);
3254
3255 return ret;
3256}
3257EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
22e266c7
JR		 3258
3259static int __flush_pasid(struct protection_domain *domain, int pasid,
3260 u64 address, bool size)
3261{
3262 struct iommu_dev_data *dev_data;
3263 struct iommu_cmd cmd;
3264 int i, ret;
3265
3266 if (!(domain->flags & PD_IOMMUV2_MASK))
3267 return -EINVAL;
3268
3269 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3270
3271 /*
3272 * IOMMU TLB needs to be flushed before Device TLB to
3273 * prevent device TLB refill from IOMMU TLB
3274 */
3275 for (i = 0; i < amd_iommus_present; ++i) {
3276 if (domain->dev_iommu[i] == 0)
3277 continue;
3278
3279 ret = iommu_queue_command(amd_iommus[i], &cmd);
3280 if (ret != 0)
3281 goto out;
3282 }
3283
3284 /* Wait until IOMMU TLB flushes are complete */
3285 domain_flush_complete(domain);
3286
3287 /* Now flush device TLBs */
3288 list_for_each_entry(dev_data, &domain->dev_list, list) {
3289 struct amd_iommu *iommu;
3290 int qdep;
3291
3292 BUG_ON(!dev_data->ats.enabled);
3293
3294 qdep = dev_data->ats.qdep;
3295 iommu = amd_iommu_rlookup_table[dev_data->devid];
3296
3297 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3298 qdep, address, size);
3299
3300 ret = iommu_queue_command(iommu, &cmd);
3301 if (ret != 0)
3302 goto out;
3303 }
3304
3305 /* Wait until all device TLBs are flushed */
3306 domain_flush_complete(domain);
3307
3308 ret = 0;
3309
3310out:
3311
3312 return ret;
3313}
3314
3315static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3316 u64 address)
3317{
3318 return __flush_pasid(domain, pasid, address, false);
3319}
3320
3321int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3322 u64 address)
3323{
3324 struct protection_domain *domain = dom->priv;
3325 unsigned long flags;
3326 int ret;
3327
3328 spin_lock_irqsave(&domain->lock, flags);
3329 ret = __amd_iommu_flush_page(domain, pasid, address);
3330 spin_unlock_irqrestore(&domain->lock, flags);
3331
3332 return ret;
3333}
3334EXPORT_SYMBOL(amd_iommu_flush_page);
3335
3336static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3337{
3338 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3339 true);
3340}
3341
3342int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3343{
3344 struct protection_domain *domain = dom->priv;
3345 unsigned long flags;
3346 int ret;
3347
3348 spin_lock_irqsave(&domain->lock, flags);
3349 ret = __amd_iommu_flush_tlb(domain, pasid);
3350 spin_unlock_irqrestore(&domain->lock, flags);
3351
3352 return ret;
3353}
3354EXPORT_SYMBOL(amd_iommu_flush_tlb);
3355
b16137b1
JR		 3356static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3357{
3358 int index;
3359 u64 *pte;
3360
3361 while (true) {
3362
3363 index = (pasid >> (9 * level)) & 0x1ff;
3364 pte = &root[index];
3365
3366 if (level == 0)
3367 break;
3368
3369 if (!(*pte & GCR3_VALID)) {
3370 if (!alloc)
3371 return NULL;
3372
3373 root = (void *)get_zeroed_page(GFP_ATOMIC);
3374 if (root == NULL)
3375 return NULL;
3376
3377 *pte = __pa(root) | GCR3_VALID;
3378 }
3379
3380 root = __va(*pte & PAGE_MASK);
3381
3382 level -= 1;
3383 }
3384
3385 return pte;
3386}
3387
3388static int __set_gcr3(struct protection_domain *domain, int pasid,
3389 unsigned long cr3)
3390{
3391 u64 *pte;
3392
3393 if (domain->mode != PAGE_MODE_NONE)
3394 return -EINVAL;
3395
3396 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3397 if (pte == NULL)
3398 return -ENOMEM;
3399
3400 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3401
3402 return __amd_iommu_flush_tlb(domain, pasid);
3403}
3404
3405static int __clear_gcr3(struct protection_domain *domain, int pasid)
3406{
3407 u64 *pte;
3408
3409 if (domain->mode != PAGE_MODE_NONE)
3410 return -EINVAL;
3411
3412 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3413 if (pte == NULL)
3414 return 0;
3415
3416 *pte = 0;
3417
3418 return __amd_iommu_flush_tlb(domain, pasid);
3419}
3420
3421int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3422 unsigned long cr3)
3423{
3424 struct protection_domain *domain = dom->priv;
3425 unsigned long flags;
3426 int ret;
3427
3428 spin_lock_irqsave(&domain->lock, flags);
3429 ret = __set_gcr3(domain, pasid, cr3);
3430 spin_unlock_irqrestore(&domain->lock, flags);
3431
3432 return ret;
3433}
3434EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3435
3436int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3437{
3438 struct protection_domain *domain = dom->priv;
3439 unsigned long flags;
3440 int ret;
3441
3442 spin_lock_irqsave(&domain->lock, flags);
3443 ret = __clear_gcr3(domain, pasid);
3444 spin_unlock_irqrestore(&domain->lock, flags);
3445
3446 return ret;
3447}
3448EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
c99afa25
JR		 3449
3450int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3451 int status, int tag)
3452{
3453 struct iommu_dev_data *dev_data;
3454 struct amd_iommu *iommu;
3455 struct iommu_cmd cmd;
3456
3457 dev_data = get_dev_data(&pdev->dev);
3458 iommu = amd_iommu_rlookup_table[dev_data->devid];
3459
3460 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3461 tag, dev_data->pri_tlp);
3462
3463 return iommu_queue_command(iommu, &cmd);
3464}
3465EXPORT_SYMBOL(amd_iommu_complete_ppr);
kernel source for telekom puls (alcatel/mediatek)