Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
58 | static u64* alloc_pte(struct protection_domain *dom, |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
00cd122a JR |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
bd0e5211 | 64 | |
7f26508b JR |
65 | #ifdef CONFIG_AMD_IOMMU_STATS |
66 | ||
67 | /* | |
68 | * Initialization code for statistics collection | |
69 | */ | |
70 | ||
da49f6df | 71 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 72 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 73 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 74 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 75 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 76 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 77 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 78 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 79 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 80 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 81 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 82 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 83 | |
7f26508b JR |
84 | static struct dentry *stats_dir; |
85 | static struct dentry *de_isolate; | |
86 | static struct dentry *de_fflush; | |
87 | ||
88 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
89 | { | |
90 | if (stats_dir == NULL) | |
91 | return; | |
92 | ||
93 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
94 | &cnt->value); | |
95 | } | |
96 | ||
97 | static void amd_iommu_stats_init(void) | |
98 | { | |
99 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
100 | if (stats_dir == NULL) | |
101 | return; | |
102 | ||
103 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
104 | (u32 *)&amd_iommu_isolate); | |
105 | ||
106 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
107 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
108 | |
109 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 110 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 111 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 112 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 113 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 114 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 115 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 116 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 117 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 118 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 119 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 120 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
121 | } |
122 | ||
123 | #endif | |
124 | ||
431b2a20 | 125 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
126 | static int iommu_has_npcache(struct amd_iommu *iommu) |
127 | { | |
ae9b9403 | 128 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
129 | } |
130 | ||
a80dc3e0 JR |
131 | /**************************************************************************** |
132 | * | |
133 | * Interrupt handling functions | |
134 | * | |
135 | ****************************************************************************/ | |
136 | ||
90008ee4 JR |
137 | static void iommu_print_event(void *__evt) |
138 | { | |
139 | u32 *event = __evt; | |
140 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
141 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
142 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
143 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
144 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
145 | ||
146 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
147 | ||
148 | switch (type) { | |
149 | case EVENT_TYPE_ILL_DEV: | |
150 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
151 | "address=0x%016llx flags=0x%04x]\n", | |
152 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
153 | address, flags); | |
154 | break; | |
155 | case EVENT_TYPE_IO_FAULT: | |
156 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
157 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
158 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
159 | domid, address, flags); | |
160 | break; | |
161 | case EVENT_TYPE_DEV_TAB_ERR: | |
162 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
163 | "address=0x%016llx flags=0x%04x]\n", | |
164 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
165 | address, flags); | |
166 | break; | |
167 | case EVENT_TYPE_PAGE_TAB_ERR: | |
168 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
169 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
170 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
171 | domid, address, flags); | |
172 | break; | |
173 | case EVENT_TYPE_ILL_CMD: | |
174 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
175 | break; | |
176 | case EVENT_TYPE_CMD_HARD_ERR: | |
177 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
178 | "flags=0x%04x]\n", address, flags); | |
179 | break; | |
180 | case EVENT_TYPE_IOTLB_INV_TO: | |
181 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
182 | "address=0x%016llx]\n", | |
183 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
184 | address); | |
185 | break; | |
186 | case EVENT_TYPE_INV_DEV_REQ: | |
187 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
188 | "address=0x%016llx flags=0x%04x]\n", | |
189 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
190 | address, flags); | |
191 | break; | |
192 | default: | |
193 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
194 | } | |
195 | } | |
196 | ||
197 | static void iommu_poll_events(struct amd_iommu *iommu) | |
198 | { | |
199 | u32 head, tail; | |
200 | unsigned long flags; | |
201 | ||
202 | spin_lock_irqsave(&iommu->lock, flags); | |
203 | ||
204 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
205 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
206 | ||
207 | while (head != tail) { | |
208 | iommu_print_event(iommu->evt_buf + head); | |
209 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
210 | } | |
211 | ||
212 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
213 | ||
214 | spin_unlock_irqrestore(&iommu->lock, flags); | |
215 | } | |
216 | ||
a80dc3e0 JR |
217 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
218 | { | |
90008ee4 JR |
219 | struct amd_iommu *iommu; |
220 | ||
221 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
222 | iommu_poll_events(iommu); | |
223 | ||
224 | return IRQ_HANDLED; | |
a80dc3e0 JR |
225 | } |
226 | ||
431b2a20 JR |
227 | /**************************************************************************** |
228 | * | |
229 | * IOMMU command queuing functions | |
230 | * | |
231 | ****************************************************************************/ | |
232 | ||
233 | /* | |
234 | * Writes the command to the IOMMUs command buffer and informs the | |
235 | * hardware about the new command. Must be called with iommu->lock held. | |
236 | */ | |
d6449536 | 237 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
238 | { |
239 | u32 tail, head; | |
240 | u8 *target; | |
241 | ||
242 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 243 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
244 | memcpy_toio(target, cmd, sizeof(*cmd)); |
245 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
246 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
247 | if (tail == head) | |
248 | return -ENOMEM; | |
249 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
431b2a20 JR |
254 | /* |
255 | * General queuing function for commands. Takes iommu->lock and calls | |
256 | * __iommu_queue_command(). | |
257 | */ | |
d6449536 | 258 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
259 | { |
260 | unsigned long flags; | |
261 | int ret; | |
262 | ||
263 | spin_lock_irqsave(&iommu->lock, flags); | |
264 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 265 | if (!ret) |
0cfd7aa9 | 266 | iommu->need_sync = true; |
a19ae1ec JR |
267 | spin_unlock_irqrestore(&iommu->lock, flags); |
268 | ||
269 | return ret; | |
270 | } | |
271 | ||
8d201968 JR |
272 | /* |
273 | * This function waits until an IOMMU has completed a completion | |
274 | * wait command | |
275 | */ | |
276 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
277 | { | |
278 | int ready = 0; | |
279 | unsigned status = 0; | |
280 | unsigned long i = 0; | |
281 | ||
da49f6df JR |
282 | INC_STATS_COUNTER(compl_wait); |
283 | ||
8d201968 JR |
284 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
285 | ++i; | |
286 | /* wait for the bit to become one */ | |
287 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
288 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
289 | } | |
290 | ||
291 | /* set bit back to zero */ | |
292 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
293 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
294 | ||
295 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
296 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
297 | } | |
298 | ||
299 | /* | |
300 | * This function queues a completion wait command into the command | |
301 | * buffer of an IOMMU | |
302 | */ | |
303 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
304 | { | |
305 | struct iommu_cmd cmd; | |
306 | ||
307 | memset(&cmd, 0, sizeof(cmd)); | |
308 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
309 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
310 | ||
311 | return __iommu_queue_command(iommu, &cmd); | |
312 | } | |
313 | ||
431b2a20 JR |
314 | /* |
315 | * This function is called whenever we need to ensure that the IOMMU has | |
316 | * completed execution of all commands we sent. It sends a | |
317 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
318 | * us about that by writing a value to a physical address we pass with | |
319 | * the command. | |
320 | */ | |
a19ae1ec JR |
321 | static int iommu_completion_wait(struct amd_iommu *iommu) |
322 | { | |
8d201968 JR |
323 | int ret = 0; |
324 | unsigned long flags; | |
a19ae1ec | 325 | |
7e4f88da JR |
326 | spin_lock_irqsave(&iommu->lock, flags); |
327 | ||
09ee17eb JR |
328 | if (!iommu->need_sync) |
329 | goto out; | |
330 | ||
8d201968 | 331 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 332 | |
0cfd7aa9 | 333 | iommu->need_sync = false; |
a19ae1ec JR |
334 | |
335 | if (ret) | |
7e4f88da | 336 | goto out; |
a19ae1ec | 337 | |
8d201968 | 338 | __iommu_wait_for_completion(iommu); |
84df8175 | 339 | |
7e4f88da JR |
340 | out: |
341 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
342 | |
343 | return 0; | |
344 | } | |
345 | ||
431b2a20 JR |
346 | /* |
347 | * Command send function for invalidating a device table entry | |
348 | */ | |
a19ae1ec JR |
349 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
350 | { | |
d6449536 | 351 | struct iommu_cmd cmd; |
ee2fa743 | 352 | int ret; |
a19ae1ec JR |
353 | |
354 | BUG_ON(iommu == NULL); | |
355 | ||
356 | memset(&cmd, 0, sizeof(cmd)); | |
357 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
358 | cmd.data[0] = devid; | |
359 | ||
ee2fa743 JR |
360 | ret = iommu_queue_command(iommu, &cmd); |
361 | ||
ee2fa743 | 362 | return ret; |
a19ae1ec JR |
363 | } |
364 | ||
237b6f33 JR |
365 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
366 | u16 domid, int pde, int s) | |
367 | { | |
368 | memset(cmd, 0, sizeof(*cmd)); | |
369 | address &= PAGE_MASK; | |
370 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
371 | cmd->data[1] |= domid; | |
372 | cmd->data[2] = lower_32_bits(address); | |
373 | cmd->data[3] = upper_32_bits(address); | |
374 | if (s) /* size bit - we flush more than one 4kb page */ | |
375 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
376 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
377 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
378 | } | |
379 | ||
431b2a20 JR |
380 | /* |
381 | * Generic command send function for invalidaing TLB entries | |
382 | */ | |
a19ae1ec JR |
383 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
384 | u64 address, u16 domid, int pde, int s) | |
385 | { | |
d6449536 | 386 | struct iommu_cmd cmd; |
ee2fa743 | 387 | int ret; |
a19ae1ec | 388 | |
237b6f33 | 389 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 390 | |
ee2fa743 JR |
391 | ret = iommu_queue_command(iommu, &cmd); |
392 | ||
ee2fa743 | 393 | return ret; |
a19ae1ec JR |
394 | } |
395 | ||
431b2a20 JR |
396 | /* |
397 | * TLB invalidation function which is called from the mapping functions. | |
398 | * It invalidates a single PTE if the range to flush is within a single | |
399 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
400 | */ | |
a19ae1ec JR |
401 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
402 | u64 address, size_t size) | |
403 | { | |
999ba417 | 404 | int s = 0; |
e3c449f5 | 405 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
406 | |
407 | address &= PAGE_MASK; | |
408 | ||
999ba417 JR |
409 | if (pages > 1) { |
410 | /* | |
411 | * If we have to flush more than one page, flush all | |
412 | * TLB entries for this domain | |
413 | */ | |
414 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
415 | s = 1; | |
a19ae1ec JR |
416 | } |
417 | ||
999ba417 JR |
418 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
419 | ||
a19ae1ec JR |
420 | return 0; |
421 | } | |
b6c02715 | 422 | |
1c655773 JR |
423 | /* Flush the whole IO/TLB for a given protection domain */ |
424 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
425 | { | |
426 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
427 | ||
f57d98ae JR |
428 | INC_STATS_COUNTER(domain_flush_single); |
429 | ||
1c655773 JR |
430 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
431 | } | |
432 | ||
43f49609 JR |
433 | /* |
434 | * This function is used to flush the IO/TLB for a given protection domain | |
435 | * on every IOMMU in the system | |
436 | */ | |
437 | static void iommu_flush_domain(u16 domid) | |
438 | { | |
439 | unsigned long flags; | |
440 | struct amd_iommu *iommu; | |
441 | struct iommu_cmd cmd; | |
442 | ||
18811f55 JR |
443 | INC_STATS_COUNTER(domain_flush_all); |
444 | ||
43f49609 JR |
445 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
446 | domid, 1, 1); | |
447 | ||
448 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
449 | spin_lock_irqsave(&iommu->lock, flags); | |
450 | __iommu_queue_command(iommu, &cmd); | |
451 | __iommu_completion_wait(iommu); | |
452 | __iommu_wait_for_completion(iommu); | |
453 | spin_unlock_irqrestore(&iommu->lock, flags); | |
454 | } | |
455 | } | |
43f49609 | 456 | |
431b2a20 JR |
457 | /**************************************************************************** |
458 | * | |
459 | * The functions below are used the create the page table mappings for | |
460 | * unity mapped regions. | |
461 | * | |
462 | ****************************************************************************/ | |
463 | ||
464 | /* | |
465 | * Generic mapping functions. It maps a physical address into a DMA | |
466 | * address space. It allocates the page table pages if necessary. | |
467 | * In the future it can be extended to a generic mapping function | |
468 | * supporting all features of AMD IOMMU page tables like level skipping | |
469 | * and full 64 bit address spaces. | |
470 | */ | |
38e817fe JR |
471 | static int iommu_map_page(struct protection_domain *dom, |
472 | unsigned long bus_addr, | |
473 | unsigned long phys_addr, | |
474 | int prot) | |
bd0e5211 | 475 | { |
8bda3092 | 476 | u64 __pte, *pte; |
bd0e5211 JR |
477 | |
478 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 479 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
480 | |
481 | /* only support 512GB address spaces for now */ | |
482 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
483 | return -EINVAL; | |
484 | ||
8bda3092 | 485 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
486 | |
487 | if (IOMMU_PTE_PRESENT(*pte)) | |
488 | return -EBUSY; | |
489 | ||
490 | __pte = phys_addr | IOMMU_PTE_P; | |
491 | if (prot & IOMMU_PROT_IR) | |
492 | __pte |= IOMMU_PTE_IR; | |
493 | if (prot & IOMMU_PROT_IW) | |
494 | __pte |= IOMMU_PTE_IW; | |
495 | ||
496 | *pte = __pte; | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
eb74ff6c JR |
501 | static void iommu_unmap_page(struct protection_domain *dom, |
502 | unsigned long bus_addr) | |
503 | { | |
504 | u64 *pte; | |
505 | ||
506 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
507 | ||
508 | if (!IOMMU_PTE_PRESENT(*pte)) | |
509 | return; | |
510 | ||
511 | pte = IOMMU_PTE_PAGE(*pte); | |
512 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
513 | ||
514 | if (!IOMMU_PTE_PRESENT(*pte)) | |
515 | return; | |
516 | ||
517 | pte = IOMMU_PTE_PAGE(*pte); | |
518 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
519 | ||
520 | *pte = 0; | |
521 | } | |
eb74ff6c | 522 | |
431b2a20 JR |
523 | /* |
524 | * This function checks if a specific unity mapping entry is needed for | |
525 | * this specific IOMMU. | |
526 | */ | |
bd0e5211 JR |
527 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
528 | struct unity_map_entry *entry) | |
529 | { | |
530 | u16 bdf, i; | |
531 | ||
532 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
533 | bdf = amd_iommu_alias_table[i]; | |
534 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
535 | return 1; | |
536 | } | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
431b2a20 JR |
541 | /* |
542 | * Init the unity mappings for a specific IOMMU in the system | |
543 | * | |
544 | * Basically iterates over all unity mapping entries and applies them to | |
545 | * the default domain DMA of that IOMMU if necessary. | |
546 | */ | |
bd0e5211 JR |
547 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
548 | { | |
549 | struct unity_map_entry *entry; | |
550 | int ret; | |
551 | ||
552 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
553 | if (!iommu_for_unity_map(iommu, entry)) | |
554 | continue; | |
555 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
556 | if (ret) | |
557 | return ret; | |
558 | } | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
431b2a20 JR |
563 | /* |
564 | * This function actually applies the mapping to the page table of the | |
565 | * dma_ops domain. | |
566 | */ | |
bd0e5211 JR |
567 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
568 | struct unity_map_entry *e) | |
569 | { | |
570 | u64 addr; | |
571 | int ret; | |
572 | ||
573 | for (addr = e->address_start; addr < e->address_end; | |
574 | addr += PAGE_SIZE) { | |
38e817fe | 575 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
576 | if (ret) |
577 | return ret; | |
578 | /* | |
579 | * if unity mapping is in aperture range mark the page | |
580 | * as allocated in the aperture | |
581 | */ | |
582 | if (addr < dma_dom->aperture_size) | |
c3239567 | 583 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 584 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
585 | } |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
431b2a20 JR |
590 | /* |
591 | * Inits the unity mappings required for a specific device | |
592 | */ | |
bd0e5211 JR |
593 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
594 | u16 devid) | |
595 | { | |
596 | struct unity_map_entry *e; | |
597 | int ret; | |
598 | ||
599 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
600 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
601 | continue; | |
602 | ret = dma_ops_unity_map(dma_dom, e); | |
603 | if (ret) | |
604 | return ret; | |
605 | } | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
431b2a20 JR |
610 | /**************************************************************************** |
611 | * | |
612 | * The next functions belong to the address allocator for the dma_ops | |
613 | * interface functions. They work like the allocators in the other IOMMU | |
614 | * drivers. Its basically a bitmap which marks the allocated pages in | |
615 | * the aperture. Maybe it could be enhanced in the future to a more | |
616 | * efficient allocator. | |
617 | * | |
618 | ****************************************************************************/ | |
d3086444 | 619 | |
431b2a20 | 620 | /* |
384de729 | 621 | * The address allocator core functions. |
431b2a20 JR |
622 | * |
623 | * called with domain->lock held | |
624 | */ | |
384de729 | 625 | |
00cd122a JR |
626 | /* |
627 | * This function checks if there is a PTE for a given dma address. If | |
628 | * there is one, it returns the pointer to it. | |
629 | */ | |
630 | static u64* fetch_pte(struct protection_domain *domain, | |
631 | unsigned long address) | |
632 | { | |
633 | u64 *pte; | |
634 | ||
635 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
636 | ||
637 | if (!IOMMU_PTE_PRESENT(*pte)) | |
638 | return NULL; | |
639 | ||
640 | pte = IOMMU_PTE_PAGE(*pte); | |
641 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
642 | ||
643 | if (!IOMMU_PTE_PRESENT(*pte)) | |
644 | return NULL; | |
645 | ||
646 | pte = IOMMU_PTE_PAGE(*pte); | |
647 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
648 | ||
649 | return pte; | |
650 | } | |
651 | ||
9cabe89b JR |
652 | /* |
653 | * This function is used to add a new aperture range to an existing | |
654 | * aperture in case of dma_ops domain allocation or address allocation | |
655 | * failure. | |
656 | */ | |
00cd122a JR |
657 | static int alloc_new_range(struct amd_iommu *iommu, |
658 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
659 | bool populate, gfp_t gfp) |
660 | { | |
661 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 662 | int i; |
9cabe89b JR |
663 | |
664 | if (index >= APERTURE_MAX_RANGES) | |
665 | return -ENOMEM; | |
666 | ||
667 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
668 | if (!dma_dom->aperture[index]) | |
669 | return -ENOMEM; | |
670 | ||
671 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
672 | if (!dma_dom->aperture[index]->bitmap) | |
673 | goto out_free; | |
674 | ||
675 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
676 | ||
677 | if (populate) { | |
678 | unsigned long address = dma_dom->aperture_size; | |
679 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
680 | u64 *pte, *pte_page; | |
681 | ||
682 | for (i = 0; i < num_ptes; ++i) { | |
683 | pte = alloc_pte(&dma_dom->domain, address, | |
684 | &pte_page, gfp); | |
685 | if (!pte) | |
686 | goto out_free; | |
687 | ||
688 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
689 | ||
690 | address += APERTURE_RANGE_SIZE / 64; | |
691 | } | |
692 | } | |
693 | ||
694 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
695 | ||
00cd122a JR |
696 | /* Intialize the exclusion range if necessary */ |
697 | if (iommu->exclusion_start && | |
698 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
699 | iommu->exclusion_start < dma_dom->aperture_size) { | |
700 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
701 | int pages = iommu_num_pages(iommu->exclusion_start, | |
702 | iommu->exclusion_length, | |
703 | PAGE_SIZE); | |
704 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
705 | } | |
706 | ||
707 | /* | |
708 | * Check for areas already mapped as present in the new aperture | |
709 | * range and mark those pages as reserved in the allocator. Such | |
710 | * mappings may already exist as a result of requested unity | |
711 | * mappings for devices. | |
712 | */ | |
713 | for (i = dma_dom->aperture[index]->offset; | |
714 | i < dma_dom->aperture_size; | |
715 | i += PAGE_SIZE) { | |
716 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
717 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
718 | continue; | |
719 | ||
720 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
721 | } | |
722 | ||
9cabe89b JR |
723 | return 0; |
724 | ||
725 | out_free: | |
726 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
727 | ||
728 | kfree(dma_dom->aperture[index]); | |
729 | dma_dom->aperture[index] = NULL; | |
730 | ||
731 | return -ENOMEM; | |
732 | } | |
733 | ||
384de729 JR |
734 | static unsigned long dma_ops_area_alloc(struct device *dev, |
735 | struct dma_ops_domain *dom, | |
736 | unsigned int pages, | |
737 | unsigned long align_mask, | |
738 | u64 dma_mask, | |
739 | unsigned long start) | |
740 | { | |
803b8cb4 | 741 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
742 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
743 | int i = start >> APERTURE_RANGE_SHIFT; | |
744 | unsigned long boundary_size; | |
745 | unsigned long address = -1; | |
746 | unsigned long limit; | |
747 | ||
803b8cb4 JR |
748 | next_bit >>= PAGE_SHIFT; |
749 | ||
384de729 JR |
750 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
751 | PAGE_SIZE) >> PAGE_SHIFT; | |
752 | ||
753 | for (;i < max_index; ++i) { | |
754 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
755 | ||
756 | if (dom->aperture[i]->offset >= dma_mask) | |
757 | break; | |
758 | ||
759 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
760 | dma_mask >> PAGE_SHIFT); | |
761 | ||
762 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
763 | limit, next_bit, pages, 0, | |
764 | boundary_size, align_mask); | |
765 | if (address != -1) { | |
766 | address = dom->aperture[i]->offset + | |
767 | (address << PAGE_SHIFT); | |
803b8cb4 | 768 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
769 | break; |
770 | } | |
771 | ||
772 | next_bit = 0; | |
773 | } | |
774 | ||
775 | return address; | |
776 | } | |
777 | ||
d3086444 JR |
778 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
779 | struct dma_ops_domain *dom, | |
6d4f343f | 780 | unsigned int pages, |
832a90c3 JR |
781 | unsigned long align_mask, |
782 | u64 dma_mask) | |
d3086444 | 783 | { |
d3086444 | 784 | unsigned long address; |
d3086444 | 785 | |
fe16f088 JR |
786 | #ifdef CONFIG_IOMMU_STRESS |
787 | dom->next_address = 0; | |
788 | dom->need_flush = true; | |
789 | #endif | |
790 | ||
384de729 | 791 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 792 | dma_mask, dom->next_address); |
d3086444 | 793 | |
1c655773 | 794 | if (address == -1) { |
803b8cb4 | 795 | dom->next_address = 0; |
384de729 JR |
796 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
797 | dma_mask, 0); | |
1c655773 JR |
798 | dom->need_flush = true; |
799 | } | |
d3086444 | 800 | |
384de729 | 801 | if (unlikely(address == -1)) |
d3086444 JR |
802 | address = bad_dma_address; |
803 | ||
804 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
805 | ||
806 | return address; | |
807 | } | |
808 | ||
431b2a20 JR |
809 | /* |
810 | * The address free function. | |
811 | * | |
812 | * called with domain->lock held | |
813 | */ | |
d3086444 JR |
814 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
815 | unsigned long address, | |
816 | unsigned int pages) | |
817 | { | |
384de729 JR |
818 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
819 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 820 | |
384de729 JR |
821 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
822 | ||
803b8cb4 | 823 | if (address >= dom->next_address) |
80be308d | 824 | dom->need_flush = true; |
384de729 JR |
825 | |
826 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 827 | |
384de729 JR |
828 | iommu_area_free(range->bitmap, address, pages); |
829 | ||
d3086444 JR |
830 | } |
831 | ||
431b2a20 JR |
832 | /**************************************************************************** |
833 | * | |
834 | * The next functions belong to the domain allocation. A domain is | |
835 | * allocated for every IOMMU as the default domain. If device isolation | |
836 | * is enabled, every device get its own domain. The most important thing | |
837 | * about domains is the page table mapping the DMA address space they | |
838 | * contain. | |
839 | * | |
840 | ****************************************************************************/ | |
841 | ||
ec487d1a JR |
842 | static u16 domain_id_alloc(void) |
843 | { | |
844 | unsigned long flags; | |
845 | int id; | |
846 | ||
847 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
848 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
849 | BUG_ON(id == 0); | |
850 | if (id > 0 && id < MAX_DOMAIN_ID) | |
851 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
852 | else | |
853 | id = 0; | |
854 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
855 | ||
856 | return id; | |
857 | } | |
858 | ||
a2acfb75 JR |
859 | static void domain_id_free(int id) |
860 | { | |
861 | unsigned long flags; | |
862 | ||
863 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
864 | if (id > 0 && id < MAX_DOMAIN_ID) | |
865 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
866 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
867 | } | |
a2acfb75 | 868 | |
431b2a20 JR |
869 | /* |
870 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
871 | * ranges. | |
872 | */ | |
ec487d1a JR |
873 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
874 | unsigned long start_page, | |
875 | unsigned int pages) | |
876 | { | |
384de729 | 877 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
878 | |
879 | if (start_page + pages > last_page) | |
880 | pages = last_page - start_page; | |
881 | ||
384de729 JR |
882 | for (i = start_page; i < start_page + pages; ++i) { |
883 | int index = i / APERTURE_RANGE_PAGES; | |
884 | int page = i % APERTURE_RANGE_PAGES; | |
885 | __set_bit(page, dom->aperture[index]->bitmap); | |
886 | } | |
ec487d1a JR |
887 | } |
888 | ||
86db2e5d | 889 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
890 | { |
891 | int i, j; | |
892 | u64 *p1, *p2, *p3; | |
893 | ||
86db2e5d | 894 | p1 = domain->pt_root; |
ec487d1a JR |
895 | |
896 | if (!p1) | |
897 | return; | |
898 | ||
899 | for (i = 0; i < 512; ++i) { | |
900 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
901 | continue; | |
902 | ||
903 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 904 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
905 | if (!IOMMU_PTE_PRESENT(p2[j])) |
906 | continue; | |
907 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
908 | free_page((unsigned long)p3); | |
909 | } | |
910 | ||
911 | free_page((unsigned long)p2); | |
912 | } | |
913 | ||
914 | free_page((unsigned long)p1); | |
86db2e5d JR |
915 | |
916 | domain->pt_root = NULL; | |
ec487d1a JR |
917 | } |
918 | ||
431b2a20 JR |
919 | /* |
920 | * Free a domain, only used if something went wrong in the | |
921 | * allocation path and we need to free an already allocated page table | |
922 | */ | |
ec487d1a JR |
923 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
924 | { | |
384de729 JR |
925 | int i; |
926 | ||
ec487d1a JR |
927 | if (!dom) |
928 | return; | |
929 | ||
86db2e5d | 930 | free_pagetable(&dom->domain); |
ec487d1a | 931 | |
384de729 JR |
932 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
933 | if (!dom->aperture[i]) | |
934 | continue; | |
935 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
936 | kfree(dom->aperture[i]); | |
937 | } | |
ec487d1a JR |
938 | |
939 | kfree(dom); | |
940 | } | |
941 | ||
431b2a20 JR |
942 | /* |
943 | * Allocates a new protection domain usable for the dma_ops functions. | |
944 | * It also intializes the page table and the address allocator data | |
945 | * structures required for the dma_ops interface | |
946 | */ | |
d9cfed92 | 947 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
948 | { |
949 | struct dma_ops_domain *dma_dom; | |
ec487d1a | 950 | |
ec487d1a JR |
951 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); |
952 | if (!dma_dom) | |
953 | return NULL; | |
954 | ||
955 | spin_lock_init(&dma_dom->domain.lock); | |
956 | ||
957 | dma_dom->domain.id = domain_id_alloc(); | |
958 | if (dma_dom->domain.id == 0) | |
959 | goto free_dma_dom; | |
960 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
961 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 962 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
963 | dma_dom->domain.priv = dma_dom; |
964 | if (!dma_dom->domain.pt_root) | |
965 | goto free_dma_dom; | |
9cabe89b JR |
966 | |
967 | dma_dom->need_flush = false; | |
968 | dma_dom->target_dev = 0xffff; | |
969 | ||
00cd122a | 970 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 971 | goto free_dma_dom; |
9cabe89b | 972 | |
ec487d1a JR |
973 | /* |
974 | * mark the first page as allocated so we never return 0 as | |
975 | * a valid dma-address. So we can use 0 as error value | |
976 | */ | |
384de729 | 977 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 978 | dma_dom->next_address = 0; |
ec487d1a | 979 | |
ec487d1a | 980 | |
ec487d1a JR |
981 | return dma_dom; |
982 | ||
983 | free_dma_dom: | |
984 | dma_ops_domain_free(dma_dom); | |
985 | ||
986 | return NULL; | |
987 | } | |
988 | ||
5b28df6f JR |
989 | /* |
990 | * little helper function to check whether a given protection domain is a | |
991 | * dma_ops domain | |
992 | */ | |
993 | static bool dma_ops_domain(struct protection_domain *domain) | |
994 | { | |
995 | return domain->flags & PD_DMA_OPS_MASK; | |
996 | } | |
997 | ||
431b2a20 JR |
998 | /* |
999 | * Find out the protection domain structure for a given PCI device. This | |
1000 | * will give us the pointer to the page table root for example. | |
1001 | */ | |
b20ac0d4 JR |
1002 | static struct protection_domain *domain_for_device(u16 devid) |
1003 | { | |
1004 | struct protection_domain *dom; | |
1005 | unsigned long flags; | |
1006 | ||
1007 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1008 | dom = amd_iommu_pd_table[devid]; | |
1009 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1010 | ||
1011 | return dom; | |
1012 | } | |
1013 | ||
431b2a20 JR |
1014 | /* |
1015 | * If a device is not yet associated with a domain, this function does | |
1016 | * assigns it visible for the hardware | |
1017 | */ | |
f1179dc0 JR |
1018 | static void attach_device(struct amd_iommu *iommu, |
1019 | struct protection_domain *domain, | |
1020 | u16 devid) | |
b20ac0d4 JR |
1021 | { |
1022 | unsigned long flags; | |
b20ac0d4 JR |
1023 | u64 pte_root = virt_to_phys(domain->pt_root); |
1024 | ||
863c74eb JR |
1025 | domain->dev_cnt += 1; |
1026 | ||
38ddf41b JR |
1027 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1028 | << DEV_ENTRY_MODE_SHIFT; | |
1029 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1030 | |
1031 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
1032 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
1033 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
1034 | amd_iommu_dev_table[devid].data[2] = domain->id; |
1035 | ||
1036 | amd_iommu_pd_table[devid] = domain; | |
1037 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1038 | ||
1039 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
1040 | } |
1041 | ||
355bf553 JR |
1042 | /* |
1043 | * Removes a device from a protection domain (unlocked) | |
1044 | */ | |
1045 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1046 | { | |
1047 | ||
1048 | /* lock domain */ | |
1049 | spin_lock(&domain->lock); | |
1050 | ||
1051 | /* remove domain from the lookup table */ | |
1052 | amd_iommu_pd_table[devid] = NULL; | |
1053 | ||
1054 | /* remove entry from the device table seen by the hardware */ | |
1055 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1056 | amd_iommu_dev_table[devid].data[1] = 0; | |
1057 | amd_iommu_dev_table[devid].data[2] = 0; | |
1058 | ||
1059 | /* decrease reference counter */ | |
1060 | domain->dev_cnt -= 1; | |
1061 | ||
1062 | /* ready */ | |
1063 | spin_unlock(&domain->lock); | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * Removes a device from a protection domain (with devtable_lock held) | |
1068 | */ | |
1069 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1070 | { | |
1071 | unsigned long flags; | |
1072 | ||
1073 | /* lock device table */ | |
1074 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1075 | __detach_device(domain, devid); | |
1076 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1077 | } | |
e275a2a0 JR |
1078 | |
1079 | static int device_change_notifier(struct notifier_block *nb, | |
1080 | unsigned long action, void *data) | |
1081 | { | |
1082 | struct device *dev = data; | |
1083 | struct pci_dev *pdev = to_pci_dev(dev); | |
1084 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1085 | struct protection_domain *domain; | |
1086 | struct dma_ops_domain *dma_domain; | |
1087 | struct amd_iommu *iommu; | |
1ac4cbbc | 1088 | unsigned long flags; |
e275a2a0 JR |
1089 | |
1090 | if (devid > amd_iommu_last_bdf) | |
1091 | goto out; | |
1092 | ||
1093 | devid = amd_iommu_alias_table[devid]; | |
1094 | ||
1095 | iommu = amd_iommu_rlookup_table[devid]; | |
1096 | if (iommu == NULL) | |
1097 | goto out; | |
1098 | ||
1099 | domain = domain_for_device(devid); | |
1100 | ||
1101 | if (domain && !dma_ops_domain(domain)) | |
1102 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1103 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1104 | ||
1105 | switch (action) { | |
1106 | case BUS_NOTIFY_BOUND_DRIVER: | |
1107 | if (domain) | |
1108 | goto out; | |
1109 | dma_domain = find_protection_domain(devid); | |
1110 | if (!dma_domain) | |
1111 | dma_domain = iommu->default_dom; | |
1112 | attach_device(iommu, &dma_domain->domain, devid); | |
1113 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
1114 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
1115 | break; | |
1116 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1117 | if (!domain) | |
1118 | goto out; | |
1119 | detach_device(domain, devid); | |
1ac4cbbc JR |
1120 | break; |
1121 | case BUS_NOTIFY_ADD_DEVICE: | |
1122 | /* allocate a protection domain if a device is added */ | |
1123 | dma_domain = find_protection_domain(devid); | |
1124 | if (dma_domain) | |
1125 | goto out; | |
d9cfed92 | 1126 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1127 | if (!dma_domain) |
1128 | goto out; | |
1129 | dma_domain->target_dev = devid; | |
1130 | ||
1131 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1132 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1133 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1134 | ||
e275a2a0 JR |
1135 | break; |
1136 | default: | |
1137 | goto out; | |
1138 | } | |
1139 | ||
1140 | iommu_queue_inv_dev_entry(iommu, devid); | |
1141 | iommu_completion_wait(iommu); | |
1142 | ||
1143 | out: | |
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | struct notifier_block device_nb = { | |
1148 | .notifier_call = device_change_notifier, | |
1149 | }; | |
355bf553 | 1150 | |
431b2a20 JR |
1151 | /***************************************************************************** |
1152 | * | |
1153 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1154 | * | |
1155 | *****************************************************************************/ | |
1156 | ||
dbcc112e JR |
1157 | /* |
1158 | * This function checks if the driver got a valid device from the caller to | |
1159 | * avoid dereferencing invalid pointers. | |
1160 | */ | |
1161 | static bool check_device(struct device *dev) | |
1162 | { | |
1163 | if (!dev || !dev->dma_mask) | |
1164 | return false; | |
1165 | ||
1166 | return true; | |
1167 | } | |
1168 | ||
bd60b735 JR |
1169 | /* |
1170 | * In this function the list of preallocated protection domains is traversed to | |
1171 | * find the domain for a specific device | |
1172 | */ | |
1173 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1174 | { | |
1175 | struct dma_ops_domain *entry, *ret = NULL; | |
1176 | unsigned long flags; | |
1177 | ||
1178 | if (list_empty(&iommu_pd_list)) | |
1179 | return NULL; | |
1180 | ||
1181 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1182 | ||
1183 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1184 | if (entry->target_dev == devid) { | |
1185 | ret = entry; | |
bd60b735 JR |
1186 | break; |
1187 | } | |
1188 | } | |
1189 | ||
1190 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1191 | ||
1192 | return ret; | |
1193 | } | |
1194 | ||
431b2a20 JR |
1195 | /* |
1196 | * In the dma_ops path we only have the struct device. This function | |
1197 | * finds the corresponding IOMMU, the protection domain and the | |
1198 | * requestor id for a given device. | |
1199 | * If the device is not yet associated with a domain this is also done | |
1200 | * in this function. | |
1201 | */ | |
b20ac0d4 JR |
1202 | static int get_device_resources(struct device *dev, |
1203 | struct amd_iommu **iommu, | |
1204 | struct protection_domain **domain, | |
1205 | u16 *bdf) | |
1206 | { | |
1207 | struct dma_ops_domain *dma_dom; | |
1208 | struct pci_dev *pcidev; | |
1209 | u16 _bdf; | |
1210 | ||
dbcc112e JR |
1211 | *iommu = NULL; |
1212 | *domain = NULL; | |
1213 | *bdf = 0xffff; | |
1214 | ||
1215 | if (dev->bus != &pci_bus_type) | |
1216 | return 0; | |
b20ac0d4 JR |
1217 | |
1218 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1219 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1220 | |
431b2a20 | 1221 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1222 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1223 | return 0; |
b20ac0d4 JR |
1224 | |
1225 | *bdf = amd_iommu_alias_table[_bdf]; | |
1226 | ||
1227 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1228 | if (*iommu == NULL) | |
1229 | return 0; | |
b20ac0d4 JR |
1230 | *domain = domain_for_device(*bdf); |
1231 | if (*domain == NULL) { | |
bd60b735 JR |
1232 | dma_dom = find_protection_domain(*bdf); |
1233 | if (!dma_dom) | |
1234 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1235 | *domain = &dma_dom->domain; |
f1179dc0 | 1236 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1237 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1238 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1239 | } |
1240 | ||
f91ba190 | 1241 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1242 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1243 | |
b20ac0d4 JR |
1244 | return 1; |
1245 | } | |
1246 | ||
8bda3092 JR |
1247 | /* |
1248 | * If the pte_page is not yet allocated this function is called | |
1249 | */ | |
1250 | static u64* alloc_pte(struct protection_domain *dom, | |
1251 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1252 | { | |
1253 | u64 *pte, *page; | |
1254 | ||
1255 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1256 | ||
1257 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1258 | page = (u64 *)get_zeroed_page(gfp); | |
1259 | if (!page) | |
1260 | return NULL; | |
1261 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1262 | } | |
1263 | ||
1264 | pte = IOMMU_PTE_PAGE(*pte); | |
1265 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1266 | ||
1267 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1268 | page = (u64 *)get_zeroed_page(gfp); | |
1269 | if (!page) | |
1270 | return NULL; | |
1271 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1272 | } | |
1273 | ||
1274 | pte = IOMMU_PTE_PAGE(*pte); | |
1275 | ||
1276 | if (pte_page) | |
1277 | *pte_page = pte; | |
1278 | ||
1279 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1280 | ||
1281 | return pte; | |
1282 | } | |
1283 | ||
1284 | /* | |
1285 | * This function fetches the PTE for a given address in the aperture | |
1286 | */ | |
1287 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1288 | unsigned long address) | |
1289 | { | |
384de729 | 1290 | struct aperture_range *aperture; |
8bda3092 JR |
1291 | u64 *pte, *pte_page; |
1292 | ||
384de729 JR |
1293 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1294 | if (!aperture) | |
1295 | return NULL; | |
1296 | ||
1297 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1298 | if (!pte) { |
1299 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1300 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1301 | } else | |
1302 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1303 | |
1304 | return pte; | |
1305 | } | |
1306 | ||
431b2a20 JR |
1307 | /* |
1308 | * This is the generic map function. It maps one 4kb page at paddr to | |
1309 | * the given address in the DMA address space for the domain. | |
1310 | */ | |
cb76c322 JR |
1311 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1312 | struct dma_ops_domain *dom, | |
1313 | unsigned long address, | |
1314 | phys_addr_t paddr, | |
1315 | int direction) | |
1316 | { | |
1317 | u64 *pte, __pte; | |
1318 | ||
1319 | WARN_ON(address > dom->aperture_size); | |
1320 | ||
1321 | paddr &= PAGE_MASK; | |
1322 | ||
8bda3092 | 1323 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1324 | if (!pte) |
1325 | return bad_dma_address; | |
cb76c322 JR |
1326 | |
1327 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1328 | ||
1329 | if (direction == DMA_TO_DEVICE) | |
1330 | __pte |= IOMMU_PTE_IR; | |
1331 | else if (direction == DMA_FROM_DEVICE) | |
1332 | __pte |= IOMMU_PTE_IW; | |
1333 | else if (direction == DMA_BIDIRECTIONAL) | |
1334 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1335 | ||
1336 | WARN_ON(*pte); | |
1337 | ||
1338 | *pte = __pte; | |
1339 | ||
1340 | return (dma_addr_t)address; | |
1341 | } | |
1342 | ||
431b2a20 JR |
1343 | /* |
1344 | * The generic unmapping function for on page in the DMA address space. | |
1345 | */ | |
cb76c322 JR |
1346 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1347 | struct dma_ops_domain *dom, | |
1348 | unsigned long address) | |
1349 | { | |
384de729 | 1350 | struct aperture_range *aperture; |
cb76c322 JR |
1351 | u64 *pte; |
1352 | ||
1353 | if (address >= dom->aperture_size) | |
1354 | return; | |
1355 | ||
384de729 JR |
1356 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1357 | if (!aperture) | |
1358 | return; | |
1359 | ||
1360 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1361 | if (!pte) | |
1362 | return; | |
cb76c322 | 1363 | |
cb76c322 JR |
1364 | pte += IOMMU_PTE_L0_INDEX(address); |
1365 | ||
1366 | WARN_ON(!*pte); | |
1367 | ||
1368 | *pte = 0ULL; | |
1369 | } | |
1370 | ||
431b2a20 JR |
1371 | /* |
1372 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1373 | * contiguous memory region into DMA address space. It is used by all |
1374 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1375 | * Must be called with the domain lock held. |
1376 | */ | |
cb76c322 JR |
1377 | static dma_addr_t __map_single(struct device *dev, |
1378 | struct amd_iommu *iommu, | |
1379 | struct dma_ops_domain *dma_dom, | |
1380 | phys_addr_t paddr, | |
1381 | size_t size, | |
6d4f343f | 1382 | int dir, |
832a90c3 JR |
1383 | bool align, |
1384 | u64 dma_mask) | |
cb76c322 JR |
1385 | { |
1386 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1387 | dma_addr_t address, start, ret; |
cb76c322 | 1388 | unsigned int pages; |
6d4f343f | 1389 | unsigned long align_mask = 0; |
cb76c322 JR |
1390 | int i; |
1391 | ||
e3c449f5 | 1392 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1393 | paddr &= PAGE_MASK; |
1394 | ||
8ecaf8f1 JR |
1395 | INC_STATS_COUNTER(total_map_requests); |
1396 | ||
c1858976 JR |
1397 | if (pages > 1) |
1398 | INC_STATS_COUNTER(cross_page); | |
1399 | ||
6d4f343f JR |
1400 | if (align) |
1401 | align_mask = (1UL << get_order(size)) - 1; | |
1402 | ||
11b83888 | 1403 | retry: |
832a90c3 JR |
1404 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1405 | dma_mask); | |
11b83888 JR |
1406 | if (unlikely(address == bad_dma_address)) { |
1407 | /* | |
1408 | * setting next_address here will let the address | |
1409 | * allocator only scan the new allocated range in the | |
1410 | * first run. This is a small optimization. | |
1411 | */ | |
1412 | dma_dom->next_address = dma_dom->aperture_size; | |
1413 | ||
1414 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1415 | goto out; | |
1416 | ||
1417 | /* | |
1418 | * aperture was sucessfully enlarged by 128 MB, try | |
1419 | * allocation again | |
1420 | */ | |
1421 | goto retry; | |
1422 | } | |
cb76c322 JR |
1423 | |
1424 | start = address; | |
1425 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1426 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1427 | if (ret == bad_dma_address) | |
1428 | goto out_unmap; | |
1429 | ||
cb76c322 JR |
1430 | paddr += PAGE_SIZE; |
1431 | start += PAGE_SIZE; | |
1432 | } | |
1433 | address += offset; | |
1434 | ||
5774f7c5 JR |
1435 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1436 | ||
afa9fdc2 | 1437 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1438 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1439 | dma_dom->need_flush = false; | |
1440 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1441 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1442 | ||
cb76c322 JR |
1443 | out: |
1444 | return address; | |
53812c11 JR |
1445 | |
1446 | out_unmap: | |
1447 | ||
1448 | for (--i; i >= 0; --i) { | |
1449 | start -= PAGE_SIZE; | |
1450 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1451 | } | |
1452 | ||
1453 | dma_ops_free_addresses(dma_dom, address, pages); | |
1454 | ||
1455 | return bad_dma_address; | |
cb76c322 JR |
1456 | } |
1457 | ||
431b2a20 JR |
1458 | /* |
1459 | * Does the reverse of the __map_single function. Must be called with | |
1460 | * the domain lock held too | |
1461 | */ | |
cb76c322 JR |
1462 | static void __unmap_single(struct amd_iommu *iommu, |
1463 | struct dma_ops_domain *dma_dom, | |
1464 | dma_addr_t dma_addr, | |
1465 | size_t size, | |
1466 | int dir) | |
1467 | { | |
1468 | dma_addr_t i, start; | |
1469 | unsigned int pages; | |
1470 | ||
b8d9905d JR |
1471 | if ((dma_addr == bad_dma_address) || |
1472 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1473 | return; |
1474 | ||
e3c449f5 | 1475 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1476 | dma_addr &= PAGE_MASK; |
1477 | start = dma_addr; | |
1478 | ||
1479 | for (i = 0; i < pages; ++i) { | |
1480 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1481 | start += PAGE_SIZE; | |
1482 | } | |
1483 | ||
5774f7c5 JR |
1484 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1485 | ||
cb76c322 | 1486 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1487 | |
80be308d | 1488 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1489 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1490 | dma_dom->need_flush = false; |
1491 | } | |
cb76c322 JR |
1492 | } |
1493 | ||
431b2a20 JR |
1494 | /* |
1495 | * The exported map_single function for dma_ops. | |
1496 | */ | |
51491367 FT |
1497 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1498 | unsigned long offset, size_t size, | |
1499 | enum dma_data_direction dir, | |
1500 | struct dma_attrs *attrs) | |
4da70b9e JR |
1501 | { |
1502 | unsigned long flags; | |
1503 | struct amd_iommu *iommu; | |
1504 | struct protection_domain *domain; | |
1505 | u16 devid; | |
1506 | dma_addr_t addr; | |
832a90c3 | 1507 | u64 dma_mask; |
51491367 | 1508 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1509 | |
0f2a86f2 JR |
1510 | INC_STATS_COUNTER(cnt_map_single); |
1511 | ||
dbcc112e JR |
1512 | if (!check_device(dev)) |
1513 | return bad_dma_address; | |
1514 | ||
832a90c3 | 1515 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1516 | |
1517 | get_device_resources(dev, &iommu, &domain, &devid); | |
1518 | ||
1519 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1520 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1521 | return (dma_addr_t)paddr; |
1522 | ||
5b28df6f JR |
1523 | if (!dma_ops_domain(domain)) |
1524 | return bad_dma_address; | |
1525 | ||
4da70b9e | 1526 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1527 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1528 | dma_mask); | |
4da70b9e JR |
1529 | if (addr == bad_dma_address) |
1530 | goto out; | |
1531 | ||
09ee17eb | 1532 | iommu_completion_wait(iommu); |
4da70b9e JR |
1533 | |
1534 | out: | |
1535 | spin_unlock_irqrestore(&domain->lock, flags); | |
1536 | ||
1537 | return addr; | |
1538 | } | |
1539 | ||
431b2a20 JR |
1540 | /* |
1541 | * The exported unmap_single function for dma_ops. | |
1542 | */ | |
51491367 FT |
1543 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1544 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1545 | { |
1546 | unsigned long flags; | |
1547 | struct amd_iommu *iommu; | |
1548 | struct protection_domain *domain; | |
1549 | u16 devid; | |
1550 | ||
146a6917 JR |
1551 | INC_STATS_COUNTER(cnt_unmap_single); |
1552 | ||
dbcc112e JR |
1553 | if (!check_device(dev) || |
1554 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1555 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1556 | return; |
1557 | ||
5b28df6f JR |
1558 | if (!dma_ops_domain(domain)) |
1559 | return; | |
1560 | ||
4da70b9e JR |
1561 | spin_lock_irqsave(&domain->lock, flags); |
1562 | ||
1563 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1564 | ||
09ee17eb | 1565 | iommu_completion_wait(iommu); |
4da70b9e JR |
1566 | |
1567 | spin_unlock_irqrestore(&domain->lock, flags); | |
1568 | } | |
1569 | ||
431b2a20 JR |
1570 | /* |
1571 | * This is a special map_sg function which is used if we should map a | |
1572 | * device which is not handled by an AMD IOMMU in the system. | |
1573 | */ | |
65b050ad JR |
1574 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1575 | int nelems, int dir) | |
1576 | { | |
1577 | struct scatterlist *s; | |
1578 | int i; | |
1579 | ||
1580 | for_each_sg(sglist, s, nelems, i) { | |
1581 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1582 | s->dma_length = s->length; | |
1583 | } | |
1584 | ||
1585 | return nelems; | |
1586 | } | |
1587 | ||
431b2a20 JR |
1588 | /* |
1589 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1590 | * lists). | |
1591 | */ | |
65b050ad | 1592 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1593 | int nelems, enum dma_data_direction dir, |
1594 | struct dma_attrs *attrs) | |
65b050ad JR |
1595 | { |
1596 | unsigned long flags; | |
1597 | struct amd_iommu *iommu; | |
1598 | struct protection_domain *domain; | |
1599 | u16 devid; | |
1600 | int i; | |
1601 | struct scatterlist *s; | |
1602 | phys_addr_t paddr; | |
1603 | int mapped_elems = 0; | |
832a90c3 | 1604 | u64 dma_mask; |
65b050ad | 1605 | |
d03f067a JR |
1606 | INC_STATS_COUNTER(cnt_map_sg); |
1607 | ||
dbcc112e JR |
1608 | if (!check_device(dev)) |
1609 | return 0; | |
1610 | ||
832a90c3 | 1611 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1612 | |
1613 | get_device_resources(dev, &iommu, &domain, &devid); | |
1614 | ||
1615 | if (!iommu || !domain) | |
1616 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1617 | ||
5b28df6f JR |
1618 | if (!dma_ops_domain(domain)) |
1619 | return 0; | |
1620 | ||
65b050ad JR |
1621 | spin_lock_irqsave(&domain->lock, flags); |
1622 | ||
1623 | for_each_sg(sglist, s, nelems, i) { | |
1624 | paddr = sg_phys(s); | |
1625 | ||
1626 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1627 | paddr, s->length, dir, false, |
1628 | dma_mask); | |
65b050ad JR |
1629 | |
1630 | if (s->dma_address) { | |
1631 | s->dma_length = s->length; | |
1632 | mapped_elems++; | |
1633 | } else | |
1634 | goto unmap; | |
65b050ad JR |
1635 | } |
1636 | ||
09ee17eb | 1637 | iommu_completion_wait(iommu); |
65b050ad JR |
1638 | |
1639 | out: | |
1640 | spin_unlock_irqrestore(&domain->lock, flags); | |
1641 | ||
1642 | return mapped_elems; | |
1643 | unmap: | |
1644 | for_each_sg(sglist, s, mapped_elems, i) { | |
1645 | if (s->dma_address) | |
1646 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1647 | s->dma_length, dir); | |
1648 | s->dma_address = s->dma_length = 0; | |
1649 | } | |
1650 | ||
1651 | mapped_elems = 0; | |
1652 | ||
1653 | goto out; | |
1654 | } | |
1655 | ||
431b2a20 JR |
1656 | /* |
1657 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1658 | * lists). | |
1659 | */ | |
65b050ad | 1660 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1661 | int nelems, enum dma_data_direction dir, |
1662 | struct dma_attrs *attrs) | |
65b050ad JR |
1663 | { |
1664 | unsigned long flags; | |
1665 | struct amd_iommu *iommu; | |
1666 | struct protection_domain *domain; | |
1667 | struct scatterlist *s; | |
1668 | u16 devid; | |
1669 | int i; | |
1670 | ||
55877a6b JR |
1671 | INC_STATS_COUNTER(cnt_unmap_sg); |
1672 | ||
dbcc112e JR |
1673 | if (!check_device(dev) || |
1674 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1675 | return; |
1676 | ||
5b28df6f JR |
1677 | if (!dma_ops_domain(domain)) |
1678 | return; | |
1679 | ||
65b050ad JR |
1680 | spin_lock_irqsave(&domain->lock, flags); |
1681 | ||
1682 | for_each_sg(sglist, s, nelems, i) { | |
1683 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1684 | s->dma_length, dir); | |
65b050ad JR |
1685 | s->dma_address = s->dma_length = 0; |
1686 | } | |
1687 | ||
09ee17eb | 1688 | iommu_completion_wait(iommu); |
65b050ad JR |
1689 | |
1690 | spin_unlock_irqrestore(&domain->lock, flags); | |
1691 | } | |
1692 | ||
431b2a20 JR |
1693 | /* |
1694 | * The exported alloc_coherent function for dma_ops. | |
1695 | */ | |
5d8b53cf JR |
1696 | static void *alloc_coherent(struct device *dev, size_t size, |
1697 | dma_addr_t *dma_addr, gfp_t flag) | |
1698 | { | |
1699 | unsigned long flags; | |
1700 | void *virt_addr; | |
1701 | struct amd_iommu *iommu; | |
1702 | struct protection_domain *domain; | |
1703 | u16 devid; | |
1704 | phys_addr_t paddr; | |
832a90c3 | 1705 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1706 | |
c8f0fb36 JR |
1707 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1708 | ||
dbcc112e JR |
1709 | if (!check_device(dev)) |
1710 | return NULL; | |
5d8b53cf | 1711 | |
13d9fead FT |
1712 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1713 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1714 | |
c97ac535 | 1715 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1716 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1717 | if (!virt_addr) | |
1718 | return 0; | |
1719 | ||
5d8b53cf JR |
1720 | paddr = virt_to_phys(virt_addr); |
1721 | ||
5d8b53cf JR |
1722 | if (!iommu || !domain) { |
1723 | *dma_addr = (dma_addr_t)paddr; | |
1724 | return virt_addr; | |
1725 | } | |
1726 | ||
5b28df6f JR |
1727 | if (!dma_ops_domain(domain)) |
1728 | goto out_free; | |
1729 | ||
832a90c3 JR |
1730 | if (!dma_mask) |
1731 | dma_mask = *dev->dma_mask; | |
1732 | ||
5d8b53cf JR |
1733 | spin_lock_irqsave(&domain->lock, flags); |
1734 | ||
1735 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1736 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1737 | |
5b28df6f JR |
1738 | if (*dma_addr == bad_dma_address) |
1739 | goto out_free; | |
5d8b53cf | 1740 | |
09ee17eb | 1741 | iommu_completion_wait(iommu); |
5d8b53cf | 1742 | |
5d8b53cf JR |
1743 | spin_unlock_irqrestore(&domain->lock, flags); |
1744 | ||
1745 | return virt_addr; | |
5b28df6f JR |
1746 | |
1747 | out_free: | |
1748 | ||
1749 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1750 | ||
1751 | return NULL; | |
5d8b53cf JR |
1752 | } |
1753 | ||
431b2a20 JR |
1754 | /* |
1755 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1756 | */ |
5d8b53cf JR |
1757 | static void free_coherent(struct device *dev, size_t size, |
1758 | void *virt_addr, dma_addr_t dma_addr) | |
1759 | { | |
1760 | unsigned long flags; | |
1761 | struct amd_iommu *iommu; | |
1762 | struct protection_domain *domain; | |
1763 | u16 devid; | |
1764 | ||
5d31ee7e JR |
1765 | INC_STATS_COUNTER(cnt_free_coherent); |
1766 | ||
dbcc112e JR |
1767 | if (!check_device(dev)) |
1768 | return; | |
1769 | ||
5d8b53cf JR |
1770 | get_device_resources(dev, &iommu, &domain, &devid); |
1771 | ||
1772 | if (!iommu || !domain) | |
1773 | goto free_mem; | |
1774 | ||
5b28df6f JR |
1775 | if (!dma_ops_domain(domain)) |
1776 | goto free_mem; | |
1777 | ||
5d8b53cf JR |
1778 | spin_lock_irqsave(&domain->lock, flags); |
1779 | ||
1780 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1781 | |
09ee17eb | 1782 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1783 | |
1784 | spin_unlock_irqrestore(&domain->lock, flags); | |
1785 | ||
1786 | free_mem: | |
1787 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1788 | } | |
1789 | ||
b39ba6ad JR |
1790 | /* |
1791 | * This function is called by the DMA layer to find out if we can handle a | |
1792 | * particular device. It is part of the dma_ops. | |
1793 | */ | |
1794 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1795 | { | |
1796 | u16 bdf; | |
1797 | struct pci_dev *pcidev; | |
1798 | ||
1799 | /* No device or no PCI device */ | |
1800 | if (!dev || dev->bus != &pci_bus_type) | |
1801 | return 0; | |
1802 | ||
1803 | pcidev = to_pci_dev(dev); | |
1804 | ||
1805 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1806 | ||
1807 | /* Out of our scope? */ | |
1808 | if (bdf > amd_iommu_last_bdf) | |
1809 | return 0; | |
1810 | ||
1811 | return 1; | |
1812 | } | |
1813 | ||
c432f3df | 1814 | /* |
431b2a20 JR |
1815 | * The function for pre-allocating protection domains. |
1816 | * | |
c432f3df JR |
1817 | * If the driver core informs the DMA layer if a driver grabs a device |
1818 | * we don't need to preallocate the protection domains anymore. | |
1819 | * For now we have to. | |
1820 | */ | |
0e93dd88 | 1821 | static void prealloc_protection_domains(void) |
c432f3df JR |
1822 | { |
1823 | struct pci_dev *dev = NULL; | |
1824 | struct dma_ops_domain *dma_dom; | |
1825 | struct amd_iommu *iommu; | |
c432f3df JR |
1826 | u16 devid; |
1827 | ||
1828 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1829 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1830 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1831 | continue; |
1832 | devid = amd_iommu_alias_table[devid]; | |
1833 | if (domain_for_device(devid)) | |
1834 | continue; | |
1835 | iommu = amd_iommu_rlookup_table[devid]; | |
1836 | if (!iommu) | |
1837 | continue; | |
d9cfed92 | 1838 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1839 | if (!dma_dom) |
1840 | continue; | |
1841 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1842 | dma_dom->target_dev = devid; |
1843 | ||
1844 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1845 | } |
1846 | } | |
1847 | ||
160c1d8e | 1848 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1849 | .alloc_coherent = alloc_coherent, |
1850 | .free_coherent = free_coherent, | |
51491367 FT |
1851 | .map_page = map_page, |
1852 | .unmap_page = unmap_page, | |
6631ee9d JR |
1853 | .map_sg = map_sg, |
1854 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1855 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1856 | }; |
1857 | ||
431b2a20 JR |
1858 | /* |
1859 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1860 | */ | |
6631ee9d JR |
1861 | int __init amd_iommu_init_dma_ops(void) |
1862 | { | |
1863 | struct amd_iommu *iommu; | |
6631ee9d JR |
1864 | int ret; |
1865 | ||
431b2a20 JR |
1866 | /* |
1867 | * first allocate a default protection domain for every IOMMU we | |
1868 | * found in the system. Devices not assigned to any other | |
1869 | * protection domain will be assigned to the default one. | |
1870 | */ | |
6631ee9d | 1871 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
d9cfed92 | 1872 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1873 | if (iommu->default_dom == NULL) |
1874 | return -ENOMEM; | |
e2dc14a2 | 1875 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1876 | ret = iommu_init_unity_mappings(iommu); |
1877 | if (ret) | |
1878 | goto free_domains; | |
1879 | } | |
1880 | ||
431b2a20 JR |
1881 | /* |
1882 | * If device isolation is enabled, pre-allocate the protection | |
1883 | * domains for each device. | |
1884 | */ | |
6631ee9d JR |
1885 | if (amd_iommu_isolate) |
1886 | prealloc_protection_domains(); | |
1887 | ||
1888 | iommu_detected = 1; | |
1889 | force_iommu = 1; | |
1890 | bad_dma_address = 0; | |
92af4e29 | 1891 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1892 | gart_iommu_aperture_disabled = 1; |
1893 | gart_iommu_aperture = 0; | |
92af4e29 | 1894 | #endif |
6631ee9d | 1895 | |
431b2a20 | 1896 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1897 | dma_ops = &amd_iommu_dma_ops; |
1898 | ||
26961efe | 1899 | register_iommu(&amd_iommu_ops); |
26961efe | 1900 | |
e275a2a0 JR |
1901 | bus_register_notifier(&pci_bus_type, &device_nb); |
1902 | ||
7f26508b JR |
1903 | amd_iommu_stats_init(); |
1904 | ||
6631ee9d JR |
1905 | return 0; |
1906 | ||
1907 | free_domains: | |
1908 | ||
1909 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1910 | if (iommu->default_dom) | |
1911 | dma_ops_domain_free(iommu->default_dom); | |
1912 | } | |
1913 | ||
1914 | return ret; | |
1915 | } | |
6d98cd80 JR |
1916 | |
1917 | /***************************************************************************** | |
1918 | * | |
1919 | * The following functions belong to the exported interface of AMD IOMMU | |
1920 | * | |
1921 | * This interface allows access to lower level functions of the IOMMU | |
1922 | * like protection domain handling and assignement of devices to domains | |
1923 | * which is not possible with the dma_ops interface. | |
1924 | * | |
1925 | *****************************************************************************/ | |
1926 | ||
6d98cd80 JR |
1927 | static void cleanup_domain(struct protection_domain *domain) |
1928 | { | |
1929 | unsigned long flags; | |
1930 | u16 devid; | |
1931 | ||
1932 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1933 | ||
1934 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1935 | if (amd_iommu_pd_table[devid] == domain) | |
1936 | __detach_device(domain, devid); | |
1937 | ||
1938 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1939 | } | |
1940 | ||
c156e347 JR |
1941 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1942 | { | |
1943 | struct protection_domain *domain; | |
1944 | ||
1945 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1946 | if (!domain) | |
1947 | return -ENOMEM; | |
1948 | ||
1949 | spin_lock_init(&domain->lock); | |
1950 | domain->mode = PAGE_MODE_3_LEVEL; | |
1951 | domain->id = domain_id_alloc(); | |
1952 | if (!domain->id) | |
1953 | goto out_free; | |
1954 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1955 | if (!domain->pt_root) | |
1956 | goto out_free; | |
1957 | ||
1958 | dom->priv = domain; | |
1959 | ||
1960 | return 0; | |
1961 | ||
1962 | out_free: | |
1963 | kfree(domain); | |
1964 | ||
1965 | return -ENOMEM; | |
1966 | } | |
1967 | ||
98383fc3 JR |
1968 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1969 | { | |
1970 | struct protection_domain *domain = dom->priv; | |
1971 | ||
1972 | if (!domain) | |
1973 | return; | |
1974 | ||
1975 | if (domain->dev_cnt > 0) | |
1976 | cleanup_domain(domain); | |
1977 | ||
1978 | BUG_ON(domain->dev_cnt != 0); | |
1979 | ||
1980 | free_pagetable(domain); | |
1981 | ||
1982 | domain_id_free(domain->id); | |
1983 | ||
1984 | kfree(domain); | |
1985 | ||
1986 | dom->priv = NULL; | |
1987 | } | |
1988 | ||
684f2888 JR |
1989 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1990 | struct device *dev) | |
1991 | { | |
1992 | struct protection_domain *domain = dom->priv; | |
1993 | struct amd_iommu *iommu; | |
1994 | struct pci_dev *pdev; | |
1995 | u16 devid; | |
1996 | ||
1997 | if (dev->bus != &pci_bus_type) | |
1998 | return; | |
1999 | ||
2000 | pdev = to_pci_dev(dev); | |
2001 | ||
2002 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2003 | ||
2004 | if (devid > 0) | |
2005 | detach_device(domain, devid); | |
2006 | ||
2007 | iommu = amd_iommu_rlookup_table[devid]; | |
2008 | if (!iommu) | |
2009 | return; | |
2010 | ||
2011 | iommu_queue_inv_dev_entry(iommu, devid); | |
2012 | iommu_completion_wait(iommu); | |
2013 | } | |
2014 | ||
01106066 JR |
2015 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2016 | struct device *dev) | |
2017 | { | |
2018 | struct protection_domain *domain = dom->priv; | |
2019 | struct protection_domain *old_domain; | |
2020 | struct amd_iommu *iommu; | |
2021 | struct pci_dev *pdev; | |
2022 | u16 devid; | |
2023 | ||
2024 | if (dev->bus != &pci_bus_type) | |
2025 | return -EINVAL; | |
2026 | ||
2027 | pdev = to_pci_dev(dev); | |
2028 | ||
2029 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2030 | ||
2031 | if (devid >= amd_iommu_last_bdf || | |
2032 | devid != amd_iommu_alias_table[devid]) | |
2033 | return -EINVAL; | |
2034 | ||
2035 | iommu = amd_iommu_rlookup_table[devid]; | |
2036 | if (!iommu) | |
2037 | return -EINVAL; | |
2038 | ||
2039 | old_domain = domain_for_device(devid); | |
2040 | if (old_domain) | |
2041 | return -EBUSY; | |
2042 | ||
2043 | attach_device(iommu, domain, devid); | |
2044 | ||
2045 | iommu_completion_wait(iommu); | |
2046 | ||
2047 | return 0; | |
2048 | } | |
2049 | ||
c6229ca6 JR |
2050 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2051 | unsigned long iova, phys_addr_t paddr, | |
2052 | size_t size, int iommu_prot) | |
2053 | { | |
2054 | struct protection_domain *domain = dom->priv; | |
2055 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2056 | int prot = 0; | |
2057 | int ret; | |
2058 | ||
2059 | if (iommu_prot & IOMMU_READ) | |
2060 | prot |= IOMMU_PROT_IR; | |
2061 | if (iommu_prot & IOMMU_WRITE) | |
2062 | prot |= IOMMU_PROT_IW; | |
2063 | ||
2064 | iova &= PAGE_MASK; | |
2065 | paddr &= PAGE_MASK; | |
2066 | ||
2067 | for (i = 0; i < npages; ++i) { | |
2068 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2069 | if (ret) | |
2070 | return ret; | |
2071 | ||
2072 | iova += PAGE_SIZE; | |
2073 | paddr += PAGE_SIZE; | |
2074 | } | |
2075 | ||
2076 | return 0; | |
2077 | } | |
2078 | ||
eb74ff6c JR |
2079 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2080 | unsigned long iova, size_t size) | |
2081 | { | |
2082 | ||
2083 | struct protection_domain *domain = dom->priv; | |
2084 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2085 | ||
2086 | iova &= PAGE_MASK; | |
2087 | ||
2088 | for (i = 0; i < npages; ++i) { | |
2089 | iommu_unmap_page(domain, iova); | |
2090 | iova += PAGE_SIZE; | |
2091 | } | |
2092 | ||
2093 | iommu_flush_domain(domain->id); | |
2094 | } | |
2095 | ||
645c4c8d JR |
2096 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2097 | unsigned long iova) | |
2098 | { | |
2099 | struct protection_domain *domain = dom->priv; | |
2100 | unsigned long offset = iova & ~PAGE_MASK; | |
2101 | phys_addr_t paddr; | |
2102 | u64 *pte; | |
2103 | ||
2104 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2105 | ||
2106 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2107 | return 0; | |
2108 | ||
2109 | pte = IOMMU_PTE_PAGE(*pte); | |
2110 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2111 | ||
2112 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2113 | return 0; | |
2114 | ||
2115 | pte = IOMMU_PTE_PAGE(*pte); | |
2116 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2117 | ||
2118 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2119 | return 0; | |
2120 | ||
2121 | paddr = *pte & IOMMU_PAGE_MASK; | |
2122 | paddr |= offset; | |
2123 | ||
2124 | return paddr; | |
2125 | } | |
2126 | ||
dbb9fd86 SY |
2127 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2128 | unsigned long cap) | |
2129 | { | |
2130 | return 0; | |
2131 | } | |
2132 | ||
26961efe JR |
2133 | static struct iommu_ops amd_iommu_ops = { |
2134 | .domain_init = amd_iommu_domain_init, | |
2135 | .domain_destroy = amd_iommu_domain_destroy, | |
2136 | .attach_dev = amd_iommu_attach_device, | |
2137 | .detach_dev = amd_iommu_detach_device, | |
2138 | .map = amd_iommu_map_range, | |
2139 | .unmap = amd_iommu_unmap_range, | |
2140 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2141 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2142 | }; |
2143 |