Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
17f5b569 | 34 | #include <asm/msidef.h> |
b6c02715 | 35 | #include <asm/proto.h> |
46a7fa27 | 36 | #include <asm/iommu.h> |
1d9b16d1 | 37 | #include <asm/gart.h> |
27c2127a | 38 | #include <asm/dma.h> |
403f81d8 JR |
39 | |
40 | #include "amd_iommu_proto.h" | |
41 | #include "amd_iommu_types.h" | |
b6c02715 JR |
42 | |
43 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
44 | ||
815b33fd | 45 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 46 | |
b6c02715 JR |
47 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
48 | ||
bd60b735 JR |
49 | /* A list of preallocated protection domains */ |
50 | static LIST_HEAD(iommu_pd_list); | |
51 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
52 | ||
8fa5f802 JR |
53 | /* List of all available dev_data structures */ |
54 | static LIST_HEAD(dev_data_list); | |
55 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
56 | ||
0feae533 JR |
57 | /* |
58 | * Domain for untranslated devices - only allocated | |
59 | * if iommu=pt passed on kernel cmd line. | |
60 | */ | |
61 | static struct protection_domain *pt_domain; | |
62 | ||
26961efe | 63 | static struct iommu_ops amd_iommu_ops; |
26961efe | 64 | |
72e1dcc4 JR |
65 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
66 | ||
431b2a20 JR |
67 | /* |
68 | * general struct to manage commands send to an IOMMU | |
69 | */ | |
d6449536 | 70 | struct iommu_cmd { |
b6c02715 JR |
71 | u32 data[4]; |
72 | }; | |
73 | ||
04bfdd84 | 74 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 75 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 76 | |
15898bbc JR |
77 | /**************************************************************************** |
78 | * | |
79 | * Helper functions | |
80 | * | |
81 | ****************************************************************************/ | |
82 | ||
f62dda66 | 83 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
84 | { |
85 | struct iommu_dev_data *dev_data; | |
86 | unsigned long flags; | |
87 | ||
88 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
89 | if (!dev_data) | |
90 | return NULL; | |
91 | ||
f62dda66 | 92 | dev_data->devid = devid; |
8fa5f802 JR |
93 | atomic_set(&dev_data->bind, 0); |
94 | ||
95 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
96 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
97 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
98 | ||
99 | return dev_data; | |
100 | } | |
101 | ||
102 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
103 | { | |
104 | unsigned long flags; | |
105 | ||
106 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
107 | list_del(&dev_data->dev_data_list); | |
108 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
109 | ||
110 | kfree(dev_data); | |
111 | } | |
112 | ||
3b03bb74 JR |
113 | static struct iommu_dev_data *search_dev_data(u16 devid) |
114 | { | |
115 | struct iommu_dev_data *dev_data; | |
116 | unsigned long flags; | |
117 | ||
118 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
119 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
120 | if (dev_data->devid == devid) | |
121 | goto out_unlock; | |
122 | } | |
123 | ||
124 | dev_data = NULL; | |
125 | ||
126 | out_unlock: | |
127 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
128 | ||
129 | return dev_data; | |
130 | } | |
131 | ||
132 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
133 | { | |
134 | struct iommu_dev_data *dev_data; | |
135 | ||
136 | dev_data = search_dev_data(devid); | |
137 | ||
138 | if (dev_data == NULL) | |
139 | dev_data = alloc_dev_data(devid); | |
140 | ||
141 | return dev_data; | |
142 | } | |
143 | ||
15898bbc JR |
144 | static inline u16 get_device_id(struct device *dev) |
145 | { | |
146 | struct pci_dev *pdev = to_pci_dev(dev); | |
147 | ||
148 | return calc_devid(pdev->bus->number, pdev->devfn); | |
149 | } | |
150 | ||
657cbb6b JR |
151 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
152 | { | |
153 | return dev->archdata.iommu; | |
154 | } | |
155 | ||
5abcdba4 JR |
156 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
157 | { | |
158 | static const int caps[] = { | |
159 | PCI_EXT_CAP_ID_ATS, | |
160 | PCI_PRI_CAP, | |
161 | PCI_PASID_CAP, | |
162 | }; | |
163 | int i, pos; | |
164 | ||
165 | for (i = 0; i < 3; ++i) { | |
166 | pos = pci_find_ext_capability(pdev, caps[i]); | |
167 | if (pos == 0) | |
168 | return false; | |
169 | } | |
170 | ||
171 | return true; | |
172 | } | |
173 | ||
71c70984 JR |
174 | /* |
175 | * In this function the list of preallocated protection domains is traversed to | |
176 | * find the domain for a specific device | |
177 | */ | |
178 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
179 | { | |
180 | struct dma_ops_domain *entry, *ret = NULL; | |
181 | unsigned long flags; | |
182 | u16 alias = amd_iommu_alias_table[devid]; | |
183 | ||
184 | if (list_empty(&iommu_pd_list)) | |
185 | return NULL; | |
186 | ||
187 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
188 | ||
189 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
190 | if (entry->target_dev == devid || | |
191 | entry->target_dev == alias) { | |
192 | ret = entry; | |
193 | break; | |
194 | } | |
195 | } | |
196 | ||
197 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
98fc5a69 JR |
202 | /* |
203 | * This function checks if the driver got a valid device from the caller to | |
204 | * avoid dereferencing invalid pointers. | |
205 | */ | |
206 | static bool check_device(struct device *dev) | |
207 | { | |
208 | u16 devid; | |
209 | ||
210 | if (!dev || !dev->dma_mask) | |
211 | return false; | |
212 | ||
213 | /* No device or no PCI device */ | |
339d3261 | 214 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
215 | return false; |
216 | ||
217 | devid = get_device_id(dev); | |
218 | ||
219 | /* Out of our scope? */ | |
220 | if (devid > amd_iommu_last_bdf) | |
221 | return false; | |
222 | ||
223 | if (amd_iommu_rlookup_table[devid] == NULL) | |
224 | return false; | |
225 | ||
226 | return true; | |
227 | } | |
228 | ||
657cbb6b JR |
229 | static int iommu_init_device(struct device *dev) |
230 | { | |
5abcdba4 | 231 | struct pci_dev *pdev = to_pci_dev(dev); |
657cbb6b | 232 | struct iommu_dev_data *dev_data; |
8fa5f802 | 233 | u16 alias; |
657cbb6b JR |
234 | |
235 | if (dev->archdata.iommu) | |
236 | return 0; | |
237 | ||
3b03bb74 | 238 | dev_data = find_dev_data(get_device_id(dev)); |
657cbb6b JR |
239 | if (!dev_data) |
240 | return -ENOMEM; | |
241 | ||
f62dda66 | 242 | alias = amd_iommu_alias_table[dev_data->devid]; |
2b02b091 | 243 | if (alias != dev_data->devid) { |
71f77580 | 244 | struct iommu_dev_data *alias_data; |
b00d3bcf | 245 | |
71f77580 JR |
246 | alias_data = find_dev_data(alias); |
247 | if (alias_data == NULL) { | |
248 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
249 | dev_name(dev)); | |
2b02b091 JR |
250 | free_dev_data(dev_data); |
251 | return -ENOTSUPP; | |
252 | } | |
71f77580 | 253 | dev_data->alias_data = alias_data; |
26018874 | 254 | } |
657cbb6b | 255 | |
5abcdba4 JR |
256 | if (pci_iommuv2_capable(pdev)) { |
257 | struct amd_iommu *iommu; | |
258 | ||
259 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
260 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
261 | } | |
262 | ||
657cbb6b JR |
263 | dev->archdata.iommu = dev_data; |
264 | ||
657cbb6b JR |
265 | return 0; |
266 | } | |
267 | ||
26018874 JR |
268 | static void iommu_ignore_device(struct device *dev) |
269 | { | |
270 | u16 devid, alias; | |
271 | ||
272 | devid = get_device_id(dev); | |
273 | alias = amd_iommu_alias_table[devid]; | |
274 | ||
275 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
276 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
277 | ||
278 | amd_iommu_rlookup_table[devid] = NULL; | |
279 | amd_iommu_rlookup_table[alias] = NULL; | |
280 | } | |
281 | ||
657cbb6b JR |
282 | static void iommu_uninit_device(struct device *dev) |
283 | { | |
8fa5f802 JR |
284 | /* |
285 | * Nothing to do here - we keep dev_data around for unplugged devices | |
286 | * and reuse it when the device is re-plugged - not doing so would | |
287 | * introduce a ton of races. | |
288 | */ | |
657cbb6b | 289 | } |
b7cc9554 JR |
290 | |
291 | void __init amd_iommu_uninit_devices(void) | |
292 | { | |
8fa5f802 | 293 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
294 | struct pci_dev *pdev = NULL; |
295 | ||
296 | for_each_pci_dev(pdev) { | |
297 | ||
298 | if (!check_device(&pdev->dev)) | |
299 | continue; | |
300 | ||
301 | iommu_uninit_device(&pdev->dev); | |
302 | } | |
8fa5f802 JR |
303 | |
304 | /* Free all of our dev_data structures */ | |
305 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
306 | free_dev_data(dev_data); | |
b7cc9554 JR |
307 | } |
308 | ||
309 | int __init amd_iommu_init_devices(void) | |
310 | { | |
311 | struct pci_dev *pdev = NULL; | |
312 | int ret = 0; | |
313 | ||
314 | for_each_pci_dev(pdev) { | |
315 | ||
316 | if (!check_device(&pdev->dev)) | |
317 | continue; | |
318 | ||
319 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
320 | if (ret == -ENOTSUPP) |
321 | iommu_ignore_device(&pdev->dev); | |
322 | else if (ret) | |
b7cc9554 JR |
323 | goto out_free; |
324 | } | |
325 | ||
326 | return 0; | |
327 | ||
328 | out_free: | |
329 | ||
330 | amd_iommu_uninit_devices(); | |
331 | ||
332 | return ret; | |
333 | } | |
7f26508b JR |
334 | #ifdef CONFIG_AMD_IOMMU_STATS |
335 | ||
336 | /* | |
337 | * Initialization code for statistics collection | |
338 | */ | |
339 | ||
da49f6df | 340 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 341 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 342 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 343 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 344 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 345 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 346 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 347 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 348 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 349 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 350 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 351 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 352 | |
7f26508b | 353 | static struct dentry *stats_dir; |
7f26508b JR |
354 | static struct dentry *de_fflush; |
355 | ||
356 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
357 | { | |
358 | if (stats_dir == NULL) | |
359 | return; | |
360 | ||
361 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
362 | &cnt->value); | |
363 | } | |
364 | ||
365 | static void amd_iommu_stats_init(void) | |
366 | { | |
367 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
368 | if (stats_dir == NULL) | |
369 | return; | |
370 | ||
7f26508b JR |
371 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
372 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
373 | |
374 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 375 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 376 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 377 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 378 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 379 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 380 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 381 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 382 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 383 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 384 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 385 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
386 | } |
387 | ||
388 | #endif | |
389 | ||
a80dc3e0 JR |
390 | /**************************************************************************** |
391 | * | |
392 | * Interrupt handling functions | |
393 | * | |
394 | ****************************************************************************/ | |
395 | ||
e3e59876 JR |
396 | static void dump_dte_entry(u16 devid) |
397 | { | |
398 | int i; | |
399 | ||
ee6c2868 JR |
400 | for (i = 0; i < 4; ++i) |
401 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
402 | amd_iommu_dev_table[devid].data[i]); |
403 | } | |
404 | ||
945b4ac4 JR |
405 | static void dump_command(unsigned long phys_addr) |
406 | { | |
407 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
408 | int i; | |
409 | ||
410 | for (i = 0; i < 4; ++i) | |
411 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
412 | } | |
413 | ||
a345b23b | 414 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
415 | { |
416 | u32 *event = __evt; | |
417 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
418 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
419 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
420 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
421 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
422 | ||
4c6f40d4 | 423 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
424 | |
425 | switch (type) { | |
426 | case EVENT_TYPE_ILL_DEV: | |
427 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
428 | "address=0x%016llx flags=0x%04x]\n", | |
429 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
430 | address, flags); | |
e3e59876 | 431 | dump_dte_entry(devid); |
90008ee4 JR |
432 | break; |
433 | case EVENT_TYPE_IO_FAULT: | |
434 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
435 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
436 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
437 | domid, address, flags); | |
438 | break; | |
439 | case EVENT_TYPE_DEV_TAB_ERR: | |
440 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
441 | "address=0x%016llx flags=0x%04x]\n", | |
442 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
443 | address, flags); | |
444 | break; | |
445 | case EVENT_TYPE_PAGE_TAB_ERR: | |
446 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
447 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
448 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
449 | domid, address, flags); | |
450 | break; | |
451 | case EVENT_TYPE_ILL_CMD: | |
452 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 453 | dump_command(address); |
90008ee4 JR |
454 | break; |
455 | case EVENT_TYPE_CMD_HARD_ERR: | |
456 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
457 | "flags=0x%04x]\n", address, flags); | |
458 | break; | |
459 | case EVENT_TYPE_IOTLB_INV_TO: | |
460 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
461 | "address=0x%016llx]\n", | |
462 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
463 | address); | |
464 | break; | |
465 | case EVENT_TYPE_INV_DEV_REQ: | |
466 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
467 | "address=0x%016llx flags=0x%04x]\n", | |
468 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
469 | address, flags); | |
470 | break; | |
471 | default: | |
472 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
473 | } | |
474 | } | |
475 | ||
476 | static void iommu_poll_events(struct amd_iommu *iommu) | |
477 | { | |
478 | u32 head, tail; | |
479 | unsigned long flags; | |
480 | ||
481 | spin_lock_irqsave(&iommu->lock, flags); | |
482 | ||
483 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
484 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
485 | ||
486 | while (head != tail) { | |
a345b23b | 487 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
488 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
489 | } | |
490 | ||
491 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
492 | ||
493 | spin_unlock_irqrestore(&iommu->lock, flags); | |
494 | } | |
495 | ||
72e1dcc4 JR |
496 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head) |
497 | { | |
498 | struct amd_iommu_fault fault; | |
499 | volatile u64 *raw; | |
500 | int i; | |
501 | ||
502 | raw = (u64 *)(iommu->ppr_log + head); | |
503 | ||
504 | /* | |
505 | * Hardware bug: Interrupt may arrive before the entry is written to | |
506 | * memory. If this happens we need to wait for the entry to arrive. | |
507 | */ | |
508 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
509 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
510 | break; | |
511 | udelay(1); | |
512 | } | |
513 | ||
514 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { | |
515 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
516 | return; | |
517 | } | |
518 | ||
519 | fault.address = raw[1]; | |
520 | fault.pasid = PPR_PASID(raw[0]); | |
521 | fault.device_id = PPR_DEVID(raw[0]); | |
522 | fault.tag = PPR_TAG(raw[0]); | |
523 | fault.flags = PPR_FLAGS(raw[0]); | |
524 | ||
525 | /* | |
526 | * To detect the hardware bug we need to clear the entry | |
527 | * to back to zero. | |
528 | */ | |
529 | raw[0] = raw[1] = 0; | |
530 | ||
531 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); | |
532 | } | |
533 | ||
534 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
535 | { | |
536 | unsigned long flags; | |
537 | u32 head, tail; | |
538 | ||
539 | if (iommu->ppr_log == NULL) | |
540 | return; | |
541 | ||
542 | spin_lock_irqsave(&iommu->lock, flags); | |
543 | ||
544 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
545 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
546 | ||
547 | while (head != tail) { | |
548 | ||
549 | /* Handle PPR entry */ | |
550 | iommu_handle_ppr_entry(iommu, head); | |
551 | ||
552 | /* Update and refresh ring-buffer state*/ | |
553 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; | |
554 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
555 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
556 | } | |
557 | ||
558 | /* enable ppr interrupts again */ | |
559 | writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
560 | ||
561 | spin_unlock_irqrestore(&iommu->lock, flags); | |
562 | } | |
563 | ||
72fe00f0 | 564 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 565 | { |
90008ee4 JR |
566 | struct amd_iommu *iommu; |
567 | ||
72e1dcc4 | 568 | for_each_iommu(iommu) { |
90008ee4 | 569 | iommu_poll_events(iommu); |
72e1dcc4 JR |
570 | iommu_poll_ppr_log(iommu); |
571 | } | |
90008ee4 JR |
572 | |
573 | return IRQ_HANDLED; | |
a80dc3e0 JR |
574 | } |
575 | ||
72fe00f0 JR |
576 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
577 | { | |
578 | return IRQ_WAKE_THREAD; | |
579 | } | |
580 | ||
431b2a20 JR |
581 | /**************************************************************************** |
582 | * | |
583 | * IOMMU command queuing functions | |
584 | * | |
585 | ****************************************************************************/ | |
586 | ||
ac0ea6e9 JR |
587 | static int wait_on_sem(volatile u64 *sem) |
588 | { | |
589 | int i = 0; | |
590 | ||
591 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
592 | udelay(1); | |
593 | i += 1; | |
594 | } | |
595 | ||
596 | if (i == LOOP_TIMEOUT) { | |
597 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
598 | return -EIO; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
605 | struct iommu_cmd *cmd, | |
606 | u32 tail) | |
a19ae1ec | 607 | { |
a19ae1ec JR |
608 | u8 *target; |
609 | ||
8a7c5ef3 | 610 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
611 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
612 | ||
613 | /* Copy command to buffer */ | |
614 | memcpy(target, cmd, sizeof(*cmd)); | |
615 | ||
616 | /* Tell the IOMMU about it */ | |
a19ae1ec | 617 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 618 | } |
a19ae1ec | 619 | |
815b33fd | 620 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 621 | { |
815b33fd JR |
622 | WARN_ON(address & 0x7ULL); |
623 | ||
ded46737 | 624 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
625 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
626 | cmd->data[1] = upper_32_bits(__pa(address)); | |
627 | cmd->data[2] = 1; | |
ded46737 JR |
628 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
629 | } | |
630 | ||
94fe79e2 JR |
631 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
632 | { | |
633 | memset(cmd, 0, sizeof(*cmd)); | |
634 | cmd->data[0] = devid; | |
635 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
636 | } | |
637 | ||
11b6402c JR |
638 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
639 | size_t size, u16 domid, int pde) | |
640 | { | |
641 | u64 pages; | |
642 | int s; | |
643 | ||
644 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
645 | s = 0; | |
646 | ||
647 | if (pages > 1) { | |
648 | /* | |
649 | * If we have to flush more than one page, flush all | |
650 | * TLB entries for this domain | |
651 | */ | |
652 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
653 | s = 1; | |
654 | } | |
655 | ||
656 | address &= PAGE_MASK; | |
657 | ||
658 | memset(cmd, 0, sizeof(*cmd)); | |
659 | cmd->data[1] |= domid; | |
660 | cmd->data[2] = lower_32_bits(address); | |
661 | cmd->data[3] = upper_32_bits(address); | |
662 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
663 | if (s) /* size bit - we flush more than one 4kb page */ | |
664 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
665 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
666 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
667 | } | |
668 | ||
cb41ed85 JR |
669 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
670 | u64 address, size_t size) | |
671 | { | |
672 | u64 pages; | |
673 | int s; | |
674 | ||
675 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
676 | s = 0; | |
677 | ||
678 | if (pages > 1) { | |
679 | /* | |
680 | * If we have to flush more than one page, flush all | |
681 | * TLB entries for this domain | |
682 | */ | |
683 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
684 | s = 1; | |
685 | } | |
686 | ||
687 | address &= PAGE_MASK; | |
688 | ||
689 | memset(cmd, 0, sizeof(*cmd)); | |
690 | cmd->data[0] = devid; | |
691 | cmd->data[0] |= (qdep & 0xff) << 24; | |
692 | cmd->data[1] = devid; | |
693 | cmd->data[2] = lower_32_bits(address); | |
694 | cmd->data[3] = upper_32_bits(address); | |
695 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
696 | if (s) | |
697 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
698 | } | |
699 | ||
58fc7f14 JR |
700 | static void build_inv_all(struct iommu_cmd *cmd) |
701 | { | |
702 | memset(cmd, 0, sizeof(*cmd)); | |
703 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
704 | } |
705 | ||
431b2a20 | 706 | /* |
431b2a20 | 707 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 708 | * hardware about the new command. |
431b2a20 | 709 | */ |
f1ca1512 JR |
710 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
711 | struct iommu_cmd *cmd, | |
712 | bool sync) | |
a19ae1ec | 713 | { |
ac0ea6e9 | 714 | u32 left, tail, head, next_tail; |
a19ae1ec | 715 | unsigned long flags; |
a19ae1ec | 716 | |
549c90dc | 717 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
718 | |
719 | again: | |
a19ae1ec | 720 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 721 | |
ac0ea6e9 JR |
722 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
723 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
724 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
725 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 726 | |
ac0ea6e9 JR |
727 | if (left <= 2) { |
728 | struct iommu_cmd sync_cmd; | |
729 | volatile u64 sem = 0; | |
730 | int ret; | |
8d201968 | 731 | |
ac0ea6e9 JR |
732 | build_completion_wait(&sync_cmd, (u64)&sem); |
733 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 734 | |
ac0ea6e9 JR |
735 | spin_unlock_irqrestore(&iommu->lock, flags); |
736 | ||
737 | if ((ret = wait_on_sem(&sem)) != 0) | |
738 | return ret; | |
739 | ||
740 | goto again; | |
8d201968 JR |
741 | } |
742 | ||
ac0ea6e9 JR |
743 | copy_cmd_to_buffer(iommu, cmd, tail); |
744 | ||
745 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 746 | iommu->need_sync = sync; |
ac0ea6e9 | 747 | |
a19ae1ec | 748 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 749 | |
815b33fd | 750 | return 0; |
8d201968 JR |
751 | } |
752 | ||
f1ca1512 JR |
753 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
754 | { | |
755 | return iommu_queue_command_sync(iommu, cmd, true); | |
756 | } | |
757 | ||
8d201968 JR |
758 | /* |
759 | * This function queues a completion wait command into the command | |
760 | * buffer of an IOMMU | |
761 | */ | |
a19ae1ec | 762 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
763 | { |
764 | struct iommu_cmd cmd; | |
815b33fd | 765 | volatile u64 sem = 0; |
ac0ea6e9 | 766 | int ret; |
8d201968 | 767 | |
09ee17eb | 768 | if (!iommu->need_sync) |
815b33fd | 769 | return 0; |
09ee17eb | 770 | |
815b33fd | 771 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 772 | |
f1ca1512 | 773 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 774 | if (ret) |
815b33fd | 775 | return ret; |
8d201968 | 776 | |
ac0ea6e9 | 777 | return wait_on_sem(&sem); |
8d201968 JR |
778 | } |
779 | ||
d8c13085 | 780 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 781 | { |
d8c13085 | 782 | struct iommu_cmd cmd; |
a19ae1ec | 783 | |
d8c13085 | 784 | build_inv_dte(&cmd, devid); |
7e4f88da | 785 | |
d8c13085 JR |
786 | return iommu_queue_command(iommu, &cmd); |
787 | } | |
09ee17eb | 788 | |
7d0c5cc5 JR |
789 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
790 | { | |
791 | u32 devid; | |
09ee17eb | 792 | |
7d0c5cc5 JR |
793 | for (devid = 0; devid <= 0xffff; ++devid) |
794 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 795 | |
7d0c5cc5 JR |
796 | iommu_completion_wait(iommu); |
797 | } | |
84df8175 | 798 | |
7d0c5cc5 JR |
799 | /* |
800 | * This function uses heavy locking and may disable irqs for some time. But | |
801 | * this is no issue because it is only called during resume. | |
802 | */ | |
803 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
804 | { | |
805 | u32 dom_id; | |
a19ae1ec | 806 | |
7d0c5cc5 JR |
807 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
808 | struct iommu_cmd cmd; | |
809 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
810 | dom_id, 1); | |
811 | iommu_queue_command(iommu, &cmd); | |
812 | } | |
8eed9833 | 813 | |
7d0c5cc5 | 814 | iommu_completion_wait(iommu); |
a19ae1ec JR |
815 | } |
816 | ||
58fc7f14 | 817 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 818 | { |
58fc7f14 | 819 | struct iommu_cmd cmd; |
0518a3a4 | 820 | |
58fc7f14 | 821 | build_inv_all(&cmd); |
0518a3a4 | 822 | |
58fc7f14 JR |
823 | iommu_queue_command(iommu, &cmd); |
824 | iommu_completion_wait(iommu); | |
825 | } | |
826 | ||
7d0c5cc5 JR |
827 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
828 | { | |
58fc7f14 JR |
829 | if (iommu_feature(iommu, FEATURE_IA)) { |
830 | iommu_flush_all(iommu); | |
831 | } else { | |
832 | iommu_flush_dte_all(iommu); | |
833 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
834 | } |
835 | } | |
836 | ||
431b2a20 | 837 | /* |
cb41ed85 | 838 | * Command send function for flushing on-device TLB |
431b2a20 | 839 | */ |
6c542047 JR |
840 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
841 | u64 address, size_t size) | |
3fa43655 JR |
842 | { |
843 | struct amd_iommu *iommu; | |
b00d3bcf | 844 | struct iommu_cmd cmd; |
cb41ed85 | 845 | int qdep; |
3fa43655 | 846 | |
ea61cddb JR |
847 | qdep = dev_data->ats.qdep; |
848 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 849 | |
ea61cddb | 850 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
851 | |
852 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
853 | } |
854 | ||
431b2a20 | 855 | /* |
431b2a20 | 856 | * Command send function for invalidating a device table entry |
431b2a20 | 857 | */ |
6c542047 | 858 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 859 | { |
3fa43655 | 860 | struct amd_iommu *iommu; |
ee2fa743 | 861 | int ret; |
a19ae1ec | 862 | |
6c542047 | 863 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 864 | |
f62dda66 | 865 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
866 | if (ret) |
867 | return ret; | |
868 | ||
ea61cddb | 869 | if (dev_data->ats.enabled) |
6c542047 | 870 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 871 | |
ee2fa743 | 872 | return ret; |
a19ae1ec JR |
873 | } |
874 | ||
431b2a20 JR |
875 | /* |
876 | * TLB invalidation function which is called from the mapping functions. | |
877 | * It invalidates a single PTE if the range to flush is within a single | |
878 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
879 | */ | |
17b124bf JR |
880 | static void __domain_flush_pages(struct protection_domain *domain, |
881 | u64 address, size_t size, int pde) | |
a19ae1ec | 882 | { |
cb41ed85 | 883 | struct iommu_dev_data *dev_data; |
11b6402c JR |
884 | struct iommu_cmd cmd; |
885 | int ret = 0, i; | |
a19ae1ec | 886 | |
11b6402c | 887 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 888 | |
6de8ad9b JR |
889 | for (i = 0; i < amd_iommus_present; ++i) { |
890 | if (!domain->dev_iommu[i]) | |
891 | continue; | |
892 | ||
893 | /* | |
894 | * Devices of this domain are behind this IOMMU | |
895 | * We need a TLB flush | |
896 | */ | |
11b6402c | 897 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
898 | } |
899 | ||
cb41ed85 | 900 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 901 | |
ea61cddb | 902 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
903 | continue; |
904 | ||
6c542047 | 905 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
906 | } |
907 | ||
11b6402c | 908 | WARN_ON(ret); |
6de8ad9b JR |
909 | } |
910 | ||
17b124bf JR |
911 | static void domain_flush_pages(struct protection_domain *domain, |
912 | u64 address, size_t size) | |
6de8ad9b | 913 | { |
17b124bf | 914 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 915 | } |
b6c02715 | 916 | |
1c655773 | 917 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 918 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 919 | { |
17b124bf | 920 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
921 | } |
922 | ||
42a49f96 | 923 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 924 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 925 | { |
17b124bf | 926 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
927 | } |
928 | ||
17b124bf | 929 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 930 | { |
17b124bf | 931 | int i; |
18811f55 | 932 | |
17b124bf JR |
933 | for (i = 0; i < amd_iommus_present; ++i) { |
934 | if (!domain->dev_iommu[i]) | |
935 | continue; | |
bfd1be18 | 936 | |
17b124bf JR |
937 | /* |
938 | * Devices of this domain are behind this IOMMU | |
939 | * We need to wait for completion of all commands. | |
940 | */ | |
941 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 942 | } |
e394d72a JR |
943 | } |
944 | ||
b00d3bcf | 945 | |
09b42804 | 946 | /* |
b00d3bcf | 947 | * This function flushes the DTEs for all devices in domain |
09b42804 | 948 | */ |
17b124bf | 949 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 950 | { |
b00d3bcf | 951 | struct iommu_dev_data *dev_data; |
b26e81b8 | 952 | |
b00d3bcf | 953 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 954 | device_flush_dte(dev_data); |
a345b23b JR |
955 | } |
956 | ||
431b2a20 JR |
957 | /**************************************************************************** |
958 | * | |
959 | * The functions below are used the create the page table mappings for | |
960 | * unity mapped regions. | |
961 | * | |
962 | ****************************************************************************/ | |
963 | ||
308973d3 JR |
964 | /* |
965 | * This function is used to add another level to an IO page table. Adding | |
966 | * another level increases the size of the address space by 9 bits to a size up | |
967 | * to 64 bits. | |
968 | */ | |
969 | static bool increase_address_space(struct protection_domain *domain, | |
970 | gfp_t gfp) | |
971 | { | |
972 | u64 *pte; | |
973 | ||
974 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
975 | /* address space already 64 bit large */ | |
976 | return false; | |
977 | ||
978 | pte = (void *)get_zeroed_page(gfp); | |
979 | if (!pte) | |
980 | return false; | |
981 | ||
982 | *pte = PM_LEVEL_PDE(domain->mode, | |
983 | virt_to_phys(domain->pt_root)); | |
984 | domain->pt_root = pte; | |
985 | domain->mode += 1; | |
986 | domain->updated = true; | |
987 | ||
988 | return true; | |
989 | } | |
990 | ||
991 | static u64 *alloc_pte(struct protection_domain *domain, | |
992 | unsigned long address, | |
cbb9d729 | 993 | unsigned long page_size, |
308973d3 JR |
994 | u64 **pte_page, |
995 | gfp_t gfp) | |
996 | { | |
cbb9d729 | 997 | int level, end_lvl; |
308973d3 | 998 | u64 *pte, *page; |
cbb9d729 JR |
999 | |
1000 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1001 | |
1002 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1003 | increase_address_space(domain, gfp); | |
1004 | ||
cbb9d729 JR |
1005 | level = domain->mode - 1; |
1006 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1007 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1008 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1009 | |
1010 | while (level > end_lvl) { | |
1011 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1012 | page = (u64 *)get_zeroed_page(gfp); | |
1013 | if (!page) | |
1014 | return NULL; | |
1015 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1016 | } | |
1017 | ||
cbb9d729 JR |
1018 | /* No level skipping support yet */ |
1019 | if (PM_PTE_LEVEL(*pte) != level) | |
1020 | return NULL; | |
1021 | ||
308973d3 JR |
1022 | level -= 1; |
1023 | ||
1024 | pte = IOMMU_PTE_PAGE(*pte); | |
1025 | ||
1026 | if (pte_page && level == end_lvl) | |
1027 | *pte_page = pte; | |
1028 | ||
1029 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1030 | } | |
1031 | ||
1032 | return pte; | |
1033 | } | |
1034 | ||
1035 | /* | |
1036 | * This function checks if there is a PTE for a given dma address. If | |
1037 | * there is one, it returns the pointer to it. | |
1038 | */ | |
24cd7723 | 1039 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1040 | { |
1041 | int level; | |
1042 | u64 *pte; | |
1043 | ||
24cd7723 JR |
1044 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1045 | return NULL; | |
1046 | ||
1047 | level = domain->mode - 1; | |
1048 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1049 | |
24cd7723 JR |
1050 | while (level > 0) { |
1051 | ||
1052 | /* Not Present */ | |
308973d3 JR |
1053 | if (!IOMMU_PTE_PRESENT(*pte)) |
1054 | return NULL; | |
1055 | ||
24cd7723 JR |
1056 | /* Large PTE */ |
1057 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1058 | unsigned long pte_mask, __pte; | |
1059 | ||
1060 | /* | |
1061 | * If we have a series of large PTEs, make | |
1062 | * sure to return a pointer to the first one. | |
1063 | */ | |
1064 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1065 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1066 | __pte = ((unsigned long)pte) & pte_mask; | |
1067 | ||
1068 | return (u64 *)__pte; | |
1069 | } | |
1070 | ||
1071 | /* No level skipping support yet */ | |
1072 | if (PM_PTE_LEVEL(*pte) != level) | |
1073 | return NULL; | |
1074 | ||
308973d3 JR |
1075 | level -= 1; |
1076 | ||
24cd7723 | 1077 | /* Walk to the next level */ |
308973d3 JR |
1078 | pte = IOMMU_PTE_PAGE(*pte); |
1079 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1080 | } |
1081 | ||
1082 | return pte; | |
1083 | } | |
1084 | ||
431b2a20 JR |
1085 | /* |
1086 | * Generic mapping functions. It maps a physical address into a DMA | |
1087 | * address space. It allocates the page table pages if necessary. | |
1088 | * In the future it can be extended to a generic mapping function | |
1089 | * supporting all features of AMD IOMMU page tables like level skipping | |
1090 | * and full 64 bit address spaces. | |
1091 | */ | |
38e817fe JR |
1092 | static int iommu_map_page(struct protection_domain *dom, |
1093 | unsigned long bus_addr, | |
1094 | unsigned long phys_addr, | |
abdc5eb3 | 1095 | int prot, |
cbb9d729 | 1096 | unsigned long page_size) |
bd0e5211 | 1097 | { |
8bda3092 | 1098 | u64 __pte, *pte; |
cbb9d729 | 1099 | int i, count; |
abdc5eb3 | 1100 | |
bad1cac2 | 1101 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1102 | return -EINVAL; |
1103 | ||
cbb9d729 JR |
1104 | bus_addr = PAGE_ALIGN(bus_addr); |
1105 | phys_addr = PAGE_ALIGN(phys_addr); | |
1106 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1107 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1108 | ||
1109 | for (i = 0; i < count; ++i) | |
1110 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1111 | return -EBUSY; | |
bd0e5211 | 1112 | |
cbb9d729 JR |
1113 | if (page_size > PAGE_SIZE) { |
1114 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1115 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1116 | } else | |
1117 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1118 | |
bd0e5211 JR |
1119 | if (prot & IOMMU_PROT_IR) |
1120 | __pte |= IOMMU_PTE_IR; | |
1121 | if (prot & IOMMU_PROT_IW) | |
1122 | __pte |= IOMMU_PTE_IW; | |
1123 | ||
cbb9d729 JR |
1124 | for (i = 0; i < count; ++i) |
1125 | pte[i] = __pte; | |
bd0e5211 | 1126 | |
04bfdd84 JR |
1127 | update_domain(dom); |
1128 | ||
bd0e5211 JR |
1129 | return 0; |
1130 | } | |
1131 | ||
24cd7723 JR |
1132 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1133 | unsigned long bus_addr, | |
1134 | unsigned long page_size) | |
eb74ff6c | 1135 | { |
24cd7723 JR |
1136 | unsigned long long unmap_size, unmapped; |
1137 | u64 *pte; | |
1138 | ||
1139 | BUG_ON(!is_power_of_2(page_size)); | |
1140 | ||
1141 | unmapped = 0; | |
eb74ff6c | 1142 | |
24cd7723 JR |
1143 | while (unmapped < page_size) { |
1144 | ||
1145 | pte = fetch_pte(dom, bus_addr); | |
1146 | ||
1147 | if (!pte) { | |
1148 | /* | |
1149 | * No PTE for this address | |
1150 | * move forward in 4kb steps | |
1151 | */ | |
1152 | unmap_size = PAGE_SIZE; | |
1153 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1154 | /* 4kb PTE found for this address */ | |
1155 | unmap_size = PAGE_SIZE; | |
1156 | *pte = 0ULL; | |
1157 | } else { | |
1158 | int count, i; | |
1159 | ||
1160 | /* Large PTE found which maps this address */ | |
1161 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1162 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1163 | for (i = 0; i < count; i++) | |
1164 | pte[i] = 0ULL; | |
1165 | } | |
1166 | ||
1167 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1168 | unmapped += unmap_size; | |
1169 | } | |
1170 | ||
1171 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1172 | |
24cd7723 | 1173 | return unmapped; |
eb74ff6c | 1174 | } |
eb74ff6c | 1175 | |
431b2a20 JR |
1176 | /* |
1177 | * This function checks if a specific unity mapping entry is needed for | |
1178 | * this specific IOMMU. | |
1179 | */ | |
bd0e5211 JR |
1180 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1181 | struct unity_map_entry *entry) | |
1182 | { | |
1183 | u16 bdf, i; | |
1184 | ||
1185 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1186 | bdf = amd_iommu_alias_table[i]; | |
1187 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1188 | return 1; | |
1189 | } | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
431b2a20 JR |
1194 | /* |
1195 | * This function actually applies the mapping to the page table of the | |
1196 | * dma_ops domain. | |
1197 | */ | |
bd0e5211 JR |
1198 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1199 | struct unity_map_entry *e) | |
1200 | { | |
1201 | u64 addr; | |
1202 | int ret; | |
1203 | ||
1204 | for (addr = e->address_start; addr < e->address_end; | |
1205 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1206 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1207 | PAGE_SIZE); |
bd0e5211 JR |
1208 | if (ret) |
1209 | return ret; | |
1210 | /* | |
1211 | * if unity mapping is in aperture range mark the page | |
1212 | * as allocated in the aperture | |
1213 | */ | |
1214 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1215 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1216 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1217 | } |
1218 | ||
1219 | return 0; | |
1220 | } | |
1221 | ||
171e7b37 JR |
1222 | /* |
1223 | * Init the unity mappings for a specific IOMMU in the system | |
1224 | * | |
1225 | * Basically iterates over all unity mapping entries and applies them to | |
1226 | * the default domain DMA of that IOMMU if necessary. | |
1227 | */ | |
1228 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1229 | { | |
1230 | struct unity_map_entry *entry; | |
1231 | int ret; | |
1232 | ||
1233 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1234 | if (!iommu_for_unity_map(iommu, entry)) | |
1235 | continue; | |
1236 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1237 | if (ret) | |
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | return 0; | |
1242 | } | |
1243 | ||
431b2a20 JR |
1244 | /* |
1245 | * Inits the unity mappings required for a specific device | |
1246 | */ | |
bd0e5211 JR |
1247 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1248 | u16 devid) | |
1249 | { | |
1250 | struct unity_map_entry *e; | |
1251 | int ret; | |
1252 | ||
1253 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1254 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1255 | continue; | |
1256 | ret = dma_ops_unity_map(dma_dom, e); | |
1257 | if (ret) | |
1258 | return ret; | |
1259 | } | |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
431b2a20 JR |
1264 | /**************************************************************************** |
1265 | * | |
1266 | * The next functions belong to the address allocator for the dma_ops | |
1267 | * interface functions. They work like the allocators in the other IOMMU | |
1268 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1269 | * the aperture. Maybe it could be enhanced in the future to a more | |
1270 | * efficient allocator. | |
1271 | * | |
1272 | ****************************************************************************/ | |
d3086444 | 1273 | |
431b2a20 | 1274 | /* |
384de729 | 1275 | * The address allocator core functions. |
431b2a20 JR |
1276 | * |
1277 | * called with domain->lock held | |
1278 | */ | |
384de729 | 1279 | |
171e7b37 JR |
1280 | /* |
1281 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1282 | * ranges. | |
1283 | */ | |
1284 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1285 | unsigned long start_page, | |
1286 | unsigned int pages) | |
1287 | { | |
1288 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1289 | ||
1290 | if (start_page + pages > last_page) | |
1291 | pages = last_page - start_page; | |
1292 | ||
1293 | for (i = start_page; i < start_page + pages; ++i) { | |
1294 | int index = i / APERTURE_RANGE_PAGES; | |
1295 | int page = i % APERTURE_RANGE_PAGES; | |
1296 | __set_bit(page, dom->aperture[index]->bitmap); | |
1297 | } | |
1298 | } | |
1299 | ||
9cabe89b JR |
1300 | /* |
1301 | * This function is used to add a new aperture range to an existing | |
1302 | * aperture in case of dma_ops domain allocation or address allocation | |
1303 | * failure. | |
1304 | */ | |
576175c2 | 1305 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1306 | bool populate, gfp_t gfp) |
1307 | { | |
1308 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1309 | struct amd_iommu *iommu; |
17f5b569 | 1310 | unsigned long i, old_size; |
9cabe89b | 1311 | |
f5e9705c JR |
1312 | #ifdef CONFIG_IOMMU_STRESS |
1313 | populate = false; | |
1314 | #endif | |
1315 | ||
9cabe89b JR |
1316 | if (index >= APERTURE_MAX_RANGES) |
1317 | return -ENOMEM; | |
1318 | ||
1319 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1320 | if (!dma_dom->aperture[index]) | |
1321 | return -ENOMEM; | |
1322 | ||
1323 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1324 | if (!dma_dom->aperture[index]->bitmap) | |
1325 | goto out_free; | |
1326 | ||
1327 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1328 | ||
1329 | if (populate) { | |
1330 | unsigned long address = dma_dom->aperture_size; | |
1331 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1332 | u64 *pte, *pte_page; | |
1333 | ||
1334 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1335 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1336 | &pte_page, gfp); |
1337 | if (!pte) | |
1338 | goto out_free; | |
1339 | ||
1340 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1341 | ||
1342 | address += APERTURE_RANGE_SIZE / 64; | |
1343 | } | |
1344 | } | |
1345 | ||
17f5b569 | 1346 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1347 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1348 | ||
17f5b569 JR |
1349 | /* Reserve address range used for MSI messages */ |
1350 | if (old_size < MSI_ADDR_BASE_LO && | |
1351 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1352 | unsigned long spage; | |
1353 | int pages; | |
1354 | ||
1355 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1356 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1357 | ||
1358 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1359 | } | |
1360 | ||
b595076a | 1361 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1362 | for_each_iommu(iommu) { |
1363 | if (iommu->exclusion_start && | |
1364 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1365 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1366 | unsigned long startpage; | |
1367 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1368 | iommu->exclusion_length, | |
1369 | PAGE_SIZE); | |
1370 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1371 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1372 | } | |
00cd122a JR |
1373 | } |
1374 | ||
1375 | /* | |
1376 | * Check for areas already mapped as present in the new aperture | |
1377 | * range and mark those pages as reserved in the allocator. Such | |
1378 | * mappings may already exist as a result of requested unity | |
1379 | * mappings for devices. | |
1380 | */ | |
1381 | for (i = dma_dom->aperture[index]->offset; | |
1382 | i < dma_dom->aperture_size; | |
1383 | i += PAGE_SIZE) { | |
24cd7723 | 1384 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1385 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1386 | continue; | |
1387 | ||
fcd0861d | 1388 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1389 | } |
1390 | ||
04bfdd84 JR |
1391 | update_domain(&dma_dom->domain); |
1392 | ||
9cabe89b JR |
1393 | return 0; |
1394 | ||
1395 | out_free: | |
04bfdd84 JR |
1396 | update_domain(&dma_dom->domain); |
1397 | ||
9cabe89b JR |
1398 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1399 | ||
1400 | kfree(dma_dom->aperture[index]); | |
1401 | dma_dom->aperture[index] = NULL; | |
1402 | ||
1403 | return -ENOMEM; | |
1404 | } | |
1405 | ||
384de729 JR |
1406 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1407 | struct dma_ops_domain *dom, | |
1408 | unsigned int pages, | |
1409 | unsigned long align_mask, | |
1410 | u64 dma_mask, | |
1411 | unsigned long start) | |
1412 | { | |
803b8cb4 | 1413 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1414 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1415 | int i = start >> APERTURE_RANGE_SHIFT; | |
1416 | unsigned long boundary_size; | |
1417 | unsigned long address = -1; | |
1418 | unsigned long limit; | |
1419 | ||
803b8cb4 JR |
1420 | next_bit >>= PAGE_SHIFT; |
1421 | ||
384de729 JR |
1422 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1423 | PAGE_SIZE) >> PAGE_SHIFT; | |
1424 | ||
1425 | for (;i < max_index; ++i) { | |
1426 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1427 | ||
1428 | if (dom->aperture[i]->offset >= dma_mask) | |
1429 | break; | |
1430 | ||
1431 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1432 | dma_mask >> PAGE_SHIFT); | |
1433 | ||
1434 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1435 | limit, next_bit, pages, 0, | |
1436 | boundary_size, align_mask); | |
1437 | if (address != -1) { | |
1438 | address = dom->aperture[i]->offset + | |
1439 | (address << PAGE_SHIFT); | |
803b8cb4 | 1440 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1441 | break; |
1442 | } | |
1443 | ||
1444 | next_bit = 0; | |
1445 | } | |
1446 | ||
1447 | return address; | |
1448 | } | |
1449 | ||
d3086444 JR |
1450 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1451 | struct dma_ops_domain *dom, | |
6d4f343f | 1452 | unsigned int pages, |
832a90c3 JR |
1453 | unsigned long align_mask, |
1454 | u64 dma_mask) | |
d3086444 | 1455 | { |
d3086444 | 1456 | unsigned long address; |
d3086444 | 1457 | |
fe16f088 JR |
1458 | #ifdef CONFIG_IOMMU_STRESS |
1459 | dom->next_address = 0; | |
1460 | dom->need_flush = true; | |
1461 | #endif | |
d3086444 | 1462 | |
384de729 | 1463 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1464 | dma_mask, dom->next_address); |
d3086444 | 1465 | |
1c655773 | 1466 | if (address == -1) { |
803b8cb4 | 1467 | dom->next_address = 0; |
384de729 JR |
1468 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1469 | dma_mask, 0); | |
1c655773 JR |
1470 | dom->need_flush = true; |
1471 | } | |
d3086444 | 1472 | |
384de729 | 1473 | if (unlikely(address == -1)) |
8fd524b3 | 1474 | address = DMA_ERROR_CODE; |
d3086444 JR |
1475 | |
1476 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1477 | ||
1478 | return address; | |
1479 | } | |
1480 | ||
431b2a20 JR |
1481 | /* |
1482 | * The address free function. | |
1483 | * | |
1484 | * called with domain->lock held | |
1485 | */ | |
d3086444 JR |
1486 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1487 | unsigned long address, | |
1488 | unsigned int pages) | |
1489 | { | |
384de729 JR |
1490 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1491 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1492 | |
384de729 JR |
1493 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1494 | ||
47bccd6b JR |
1495 | #ifdef CONFIG_IOMMU_STRESS |
1496 | if (i < 4) | |
1497 | return; | |
1498 | #endif | |
80be308d | 1499 | |
803b8cb4 | 1500 | if (address >= dom->next_address) |
80be308d | 1501 | dom->need_flush = true; |
384de729 JR |
1502 | |
1503 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1504 | |
a66022c4 | 1505 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1506 | |
d3086444 JR |
1507 | } |
1508 | ||
431b2a20 JR |
1509 | /**************************************************************************** |
1510 | * | |
1511 | * The next functions belong to the domain allocation. A domain is | |
1512 | * allocated for every IOMMU as the default domain. If device isolation | |
1513 | * is enabled, every device get its own domain. The most important thing | |
1514 | * about domains is the page table mapping the DMA address space they | |
1515 | * contain. | |
1516 | * | |
1517 | ****************************************************************************/ | |
1518 | ||
aeb26f55 JR |
1519 | /* |
1520 | * This function adds a protection domain to the global protection domain list | |
1521 | */ | |
1522 | static void add_domain_to_list(struct protection_domain *domain) | |
1523 | { | |
1524 | unsigned long flags; | |
1525 | ||
1526 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1527 | list_add(&domain->list, &amd_iommu_pd_list); | |
1528 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1529 | } | |
1530 | ||
1531 | /* | |
1532 | * This function removes a protection domain to the global | |
1533 | * protection domain list | |
1534 | */ | |
1535 | static void del_domain_from_list(struct protection_domain *domain) | |
1536 | { | |
1537 | unsigned long flags; | |
1538 | ||
1539 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1540 | list_del(&domain->list); | |
1541 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1542 | } | |
1543 | ||
ec487d1a JR |
1544 | static u16 domain_id_alloc(void) |
1545 | { | |
1546 | unsigned long flags; | |
1547 | int id; | |
1548 | ||
1549 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1550 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1551 | BUG_ON(id == 0); | |
1552 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1553 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1554 | else | |
1555 | id = 0; | |
1556 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1557 | ||
1558 | return id; | |
1559 | } | |
1560 | ||
a2acfb75 JR |
1561 | static void domain_id_free(int id) |
1562 | { | |
1563 | unsigned long flags; | |
1564 | ||
1565 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1566 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1567 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1568 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1569 | } | |
a2acfb75 | 1570 | |
86db2e5d | 1571 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1572 | { |
1573 | int i, j; | |
1574 | u64 *p1, *p2, *p3; | |
1575 | ||
86db2e5d | 1576 | p1 = domain->pt_root; |
ec487d1a JR |
1577 | |
1578 | if (!p1) | |
1579 | return; | |
1580 | ||
1581 | for (i = 0; i < 512; ++i) { | |
1582 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1583 | continue; | |
1584 | ||
1585 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1586 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1587 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1588 | continue; | |
1589 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1590 | free_page((unsigned long)p3); | |
1591 | } | |
1592 | ||
1593 | free_page((unsigned long)p2); | |
1594 | } | |
1595 | ||
1596 | free_page((unsigned long)p1); | |
86db2e5d JR |
1597 | |
1598 | domain->pt_root = NULL; | |
ec487d1a JR |
1599 | } |
1600 | ||
431b2a20 JR |
1601 | /* |
1602 | * Free a domain, only used if something went wrong in the | |
1603 | * allocation path and we need to free an already allocated page table | |
1604 | */ | |
ec487d1a JR |
1605 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1606 | { | |
384de729 JR |
1607 | int i; |
1608 | ||
ec487d1a JR |
1609 | if (!dom) |
1610 | return; | |
1611 | ||
aeb26f55 JR |
1612 | del_domain_from_list(&dom->domain); |
1613 | ||
86db2e5d | 1614 | free_pagetable(&dom->domain); |
ec487d1a | 1615 | |
384de729 JR |
1616 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1617 | if (!dom->aperture[i]) | |
1618 | continue; | |
1619 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1620 | kfree(dom->aperture[i]); | |
1621 | } | |
ec487d1a JR |
1622 | |
1623 | kfree(dom); | |
1624 | } | |
1625 | ||
431b2a20 JR |
1626 | /* |
1627 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1628 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1629 | * structures required for the dma_ops interface |
1630 | */ | |
87a64d52 | 1631 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1632 | { |
1633 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1634 | |
1635 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1636 | if (!dma_dom) | |
1637 | return NULL; | |
1638 | ||
1639 | spin_lock_init(&dma_dom->domain.lock); | |
1640 | ||
1641 | dma_dom->domain.id = domain_id_alloc(); | |
1642 | if (dma_dom->domain.id == 0) | |
1643 | goto free_dma_dom; | |
7c392cbe | 1644 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1645 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1646 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1647 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1648 | dma_dom->domain.priv = dma_dom; |
1649 | if (!dma_dom->domain.pt_root) | |
1650 | goto free_dma_dom; | |
ec487d1a | 1651 | |
1c655773 | 1652 | dma_dom->need_flush = false; |
bd60b735 | 1653 | dma_dom->target_dev = 0xffff; |
1c655773 | 1654 | |
aeb26f55 JR |
1655 | add_domain_to_list(&dma_dom->domain); |
1656 | ||
576175c2 | 1657 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1658 | goto free_dma_dom; |
ec487d1a | 1659 | |
431b2a20 | 1660 | /* |
ec487d1a JR |
1661 | * mark the first page as allocated so we never return 0 as |
1662 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1663 | */ |
384de729 | 1664 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1665 | dma_dom->next_address = 0; |
ec487d1a | 1666 | |
ec487d1a JR |
1667 | |
1668 | return dma_dom; | |
1669 | ||
1670 | free_dma_dom: | |
1671 | dma_ops_domain_free(dma_dom); | |
1672 | ||
1673 | return NULL; | |
1674 | } | |
1675 | ||
5b28df6f JR |
1676 | /* |
1677 | * little helper function to check whether a given protection domain is a | |
1678 | * dma_ops domain | |
1679 | */ | |
1680 | static bool dma_ops_domain(struct protection_domain *domain) | |
1681 | { | |
1682 | return domain->flags & PD_DMA_OPS_MASK; | |
1683 | } | |
1684 | ||
fd7b5535 | 1685 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1686 | { |
b20ac0d4 | 1687 | u64 pte_root = virt_to_phys(domain->pt_root); |
ee6c2868 | 1688 | u64 flags = 0; |
863c74eb | 1689 | |
38ddf41b JR |
1690 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1691 | << DEV_ENTRY_MODE_SHIFT; | |
1692 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1693 | |
ee6c2868 JR |
1694 | flags = amd_iommu_dev_table[devid].data[1]; |
1695 | ||
fd7b5535 JR |
1696 | if (ats) |
1697 | flags |= DTE_FLAG_IOTLB; | |
1698 | ||
ee6c2868 JR |
1699 | flags &= ~(0xffffUL); |
1700 | flags |= domain->id; | |
1701 | ||
1702 | amd_iommu_dev_table[devid].data[1] = flags; | |
1703 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1704 | } |
1705 | ||
1706 | static void clear_dte_entry(u16 devid) | |
1707 | { | |
15898bbc JR |
1708 | /* remove entry from the device table seen by the hardware */ |
1709 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1710 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
1711 | |
1712 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1713 | } |
1714 | ||
ec9e79ef JR |
1715 | static void do_attach(struct iommu_dev_data *dev_data, |
1716 | struct protection_domain *domain) | |
7f760ddd | 1717 | { |
7f760ddd | 1718 | struct amd_iommu *iommu; |
ec9e79ef | 1719 | bool ats; |
fd7b5535 | 1720 | |
ec9e79ef JR |
1721 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1722 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1723 | |
1724 | /* Update data structures */ | |
1725 | dev_data->domain = domain; | |
1726 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1727 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1728 | |
1729 | /* Do reference counting */ | |
1730 | domain->dev_iommu[iommu->index] += 1; | |
1731 | domain->dev_cnt += 1; | |
1732 | ||
1733 | /* Flush the DTE entry */ | |
6c542047 | 1734 | device_flush_dte(dev_data); |
7f760ddd JR |
1735 | } |
1736 | ||
ec9e79ef | 1737 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1738 | { |
7f760ddd | 1739 | struct amd_iommu *iommu; |
7f760ddd | 1740 | |
ec9e79ef | 1741 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1742 | |
1743 | /* decrease reference counters */ | |
7f760ddd JR |
1744 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1745 | dev_data->domain->dev_cnt -= 1; | |
1746 | ||
1747 | /* Update data structures */ | |
1748 | dev_data->domain = NULL; | |
1749 | list_del(&dev_data->list); | |
f62dda66 | 1750 | clear_dte_entry(dev_data->devid); |
15898bbc | 1751 | |
7f760ddd | 1752 | /* Flush the DTE entry */ |
6c542047 | 1753 | device_flush_dte(dev_data); |
2b681faf JR |
1754 | } |
1755 | ||
1756 | /* | |
1757 | * If a device is not yet associated with a domain, this function does | |
1758 | * assigns it visible for the hardware | |
1759 | */ | |
ec9e79ef | 1760 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1761 | struct protection_domain *domain) |
2b681faf | 1762 | { |
84fe6c19 | 1763 | int ret; |
657cbb6b | 1764 | |
2b681faf JR |
1765 | /* lock domain */ |
1766 | spin_lock(&domain->lock); | |
1767 | ||
71f77580 JR |
1768 | if (dev_data->alias_data != NULL) { |
1769 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 1770 | |
2b02b091 JR |
1771 | /* Some sanity checks */ |
1772 | ret = -EBUSY; | |
1773 | if (alias_data->domain != NULL && | |
1774 | alias_data->domain != domain) | |
1775 | goto out_unlock; | |
eba6ac60 | 1776 | |
2b02b091 JR |
1777 | if (dev_data->domain != NULL && |
1778 | dev_data->domain != domain) | |
1779 | goto out_unlock; | |
15898bbc | 1780 | |
2b02b091 | 1781 | /* Do real assignment */ |
7f760ddd | 1782 | if (alias_data->domain == NULL) |
ec9e79ef | 1783 | do_attach(alias_data, domain); |
24100055 JR |
1784 | |
1785 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1786 | } |
15898bbc | 1787 | |
7f760ddd | 1788 | if (dev_data->domain == NULL) |
ec9e79ef | 1789 | do_attach(dev_data, domain); |
eba6ac60 | 1790 | |
24100055 JR |
1791 | atomic_inc(&dev_data->bind); |
1792 | ||
84fe6c19 JL |
1793 | ret = 0; |
1794 | ||
1795 | out_unlock: | |
1796 | ||
eba6ac60 JR |
1797 | /* ready */ |
1798 | spin_unlock(&domain->lock); | |
15898bbc | 1799 | |
84fe6c19 | 1800 | return ret; |
0feae533 | 1801 | } |
b20ac0d4 | 1802 | |
407d733e JR |
1803 | /* |
1804 | * If a device is not yet associated with a domain, this function does | |
1805 | * assigns it visible for the hardware | |
1806 | */ | |
15898bbc JR |
1807 | static int attach_device(struct device *dev, |
1808 | struct protection_domain *domain) | |
0feae533 | 1809 | { |
fd7b5535 | 1810 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 1811 | struct iommu_dev_data *dev_data; |
eba6ac60 | 1812 | unsigned long flags; |
15898bbc | 1813 | int ret; |
eba6ac60 | 1814 | |
ea61cddb JR |
1815 | dev_data = get_dev_data(dev); |
1816 | ||
1817 | if (amd_iommu_iotlb_sup && pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
1818 | dev_data->ats.enabled = true; | |
1819 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1820 | } | |
fd7b5535 | 1821 | |
eba6ac60 | 1822 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 1823 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
1824 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1825 | ||
0feae533 JR |
1826 | /* |
1827 | * We might boot into a crash-kernel here. The crashed kernel | |
1828 | * left the caches in the IOMMU dirty. So we have to flush | |
1829 | * here to evict all dirty stuff. | |
1830 | */ | |
17b124bf | 1831 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1832 | |
1833 | return ret; | |
b20ac0d4 JR |
1834 | } |
1835 | ||
355bf553 JR |
1836 | /* |
1837 | * Removes a device from a protection domain (unlocked) | |
1838 | */ | |
ec9e79ef | 1839 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 1840 | { |
2ca76279 | 1841 | struct protection_domain *domain; |
7c392cbe | 1842 | unsigned long flags; |
c4596114 | 1843 | |
7f760ddd | 1844 | BUG_ON(!dev_data->domain); |
355bf553 | 1845 | |
2ca76279 JR |
1846 | domain = dev_data->domain; |
1847 | ||
1848 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1849 | |
71f77580 JR |
1850 | if (dev_data->alias_data != NULL) { |
1851 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
1852 | ||
7f760ddd | 1853 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 1854 | do_detach(alias_data); |
24100055 JR |
1855 | } |
1856 | ||
7f760ddd | 1857 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 1858 | do_detach(dev_data); |
7f760ddd | 1859 | |
2ca76279 | 1860 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1861 | |
1862 | /* | |
1863 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1864 | * passthrough domain if it is detached from any other domain. |
1865 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1866 | */ |
5abcdba4 | 1867 | if (dev_data->passthrough && |
d3ad9373 | 1868 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 1869 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
1870 | } |
1871 | ||
1872 | /* | |
1873 | * Removes a device from a protection domain (with devtable_lock held) | |
1874 | */ | |
15898bbc | 1875 | static void detach_device(struct device *dev) |
355bf553 | 1876 | { |
ea61cddb | 1877 | struct iommu_dev_data *dev_data; |
355bf553 JR |
1878 | unsigned long flags; |
1879 | ||
ec9e79ef JR |
1880 | dev_data = get_dev_data(dev); |
1881 | ||
355bf553 JR |
1882 | /* lock device table */ |
1883 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 1884 | __detach_device(dev_data); |
355bf553 | 1885 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 1886 | |
ea61cddb JR |
1887 | if (dev_data->ats.enabled) { |
1888 | pci_disable_ats(to_pci_dev(dev)); | |
1889 | dev_data->ats.enabled = false; | |
1890 | } | |
355bf553 | 1891 | } |
e275a2a0 | 1892 | |
15898bbc JR |
1893 | /* |
1894 | * Find out the protection domain structure for a given PCI device. This | |
1895 | * will give us the pointer to the page table root for example. | |
1896 | */ | |
1897 | static struct protection_domain *domain_for_device(struct device *dev) | |
1898 | { | |
71f77580 | 1899 | struct iommu_dev_data *dev_data; |
2b02b091 | 1900 | struct protection_domain *dom = NULL; |
15898bbc | 1901 | unsigned long flags; |
15898bbc | 1902 | |
657cbb6b | 1903 | dev_data = get_dev_data(dev); |
15898bbc | 1904 | |
2b02b091 JR |
1905 | if (dev_data->domain) |
1906 | return dev_data->domain; | |
15898bbc | 1907 | |
71f77580 JR |
1908 | if (dev_data->alias_data != NULL) { |
1909 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
1910 | |
1911 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1912 | if (alias_data->domain != NULL) { | |
1913 | __attach_device(dev_data, alias_data->domain); | |
1914 | dom = alias_data->domain; | |
1915 | } | |
1916 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1917 | } | |
15898bbc JR |
1918 | |
1919 | return dom; | |
1920 | } | |
1921 | ||
e275a2a0 JR |
1922 | static int device_change_notifier(struct notifier_block *nb, |
1923 | unsigned long action, void *data) | |
1924 | { | |
e275a2a0 | 1925 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
1926 | struct protection_domain *domain; |
1927 | struct iommu_dev_data *dev_data; | |
1928 | struct device *dev = data; | |
e275a2a0 | 1929 | struct amd_iommu *iommu; |
1ac4cbbc | 1930 | unsigned long flags; |
5abcdba4 | 1931 | u16 devid; |
e275a2a0 | 1932 | |
98fc5a69 JR |
1933 | if (!check_device(dev)) |
1934 | return 0; | |
e275a2a0 | 1935 | |
5abcdba4 JR |
1936 | devid = get_device_id(dev); |
1937 | iommu = amd_iommu_rlookup_table[devid]; | |
1938 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
1939 | |
1940 | switch (action) { | |
c1eee67b | 1941 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1942 | |
1943 | domain = domain_for_device(dev); | |
1944 | ||
e275a2a0 JR |
1945 | if (!domain) |
1946 | goto out; | |
5abcdba4 | 1947 | if (dev_data->passthrough) |
a1ca331c | 1948 | break; |
15898bbc | 1949 | detach_device(dev); |
1ac4cbbc JR |
1950 | break; |
1951 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1952 | |
1953 | iommu_init_device(dev); | |
1954 | ||
1955 | domain = domain_for_device(dev); | |
1956 | ||
1ac4cbbc JR |
1957 | /* allocate a protection domain if a device is added */ |
1958 | dma_domain = find_protection_domain(devid); | |
1959 | if (dma_domain) | |
1960 | goto out; | |
87a64d52 | 1961 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1962 | if (!dma_domain) |
1963 | goto out; | |
1964 | dma_domain->target_dev = devid; | |
1965 | ||
1966 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1967 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1968 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1969 | ||
e275a2a0 | 1970 | break; |
657cbb6b JR |
1971 | case BUS_NOTIFY_DEL_DEVICE: |
1972 | ||
1973 | iommu_uninit_device(dev); | |
1974 | ||
e275a2a0 JR |
1975 | default: |
1976 | goto out; | |
1977 | } | |
1978 | ||
e275a2a0 JR |
1979 | iommu_completion_wait(iommu); |
1980 | ||
1981 | out: | |
1982 | return 0; | |
1983 | } | |
1984 | ||
b25ae679 | 1985 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1986 | .notifier_call = device_change_notifier, |
1987 | }; | |
355bf553 | 1988 | |
8638c491 JR |
1989 | void amd_iommu_init_notifier(void) |
1990 | { | |
1991 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1992 | } | |
1993 | ||
431b2a20 JR |
1994 | /***************************************************************************** |
1995 | * | |
1996 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1997 | * | |
1998 | *****************************************************************************/ | |
1999 | ||
2000 | /* | |
2001 | * In the dma_ops path we only have the struct device. This function | |
2002 | * finds the corresponding IOMMU, the protection domain and the | |
2003 | * requestor id for a given device. | |
2004 | * If the device is not yet associated with a domain this is also done | |
2005 | * in this function. | |
2006 | */ | |
94f6d190 | 2007 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2008 | { |
94f6d190 | 2009 | struct protection_domain *domain; |
b20ac0d4 | 2010 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2011 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2012 | |
f99c0f1c | 2013 | if (!check_device(dev)) |
94f6d190 | 2014 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2015 | |
94f6d190 JR |
2016 | domain = domain_for_device(dev); |
2017 | if (domain != NULL && !dma_ops_domain(domain)) | |
2018 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2019 | |
94f6d190 JR |
2020 | if (domain != NULL) |
2021 | return domain; | |
b20ac0d4 | 2022 | |
15898bbc | 2023 | /* Device not bount yet - bind it */ |
94f6d190 | 2024 | dma_dom = find_protection_domain(devid); |
15898bbc | 2025 | if (!dma_dom) |
94f6d190 JR |
2026 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2027 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2028 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2029 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2030 | |
94f6d190 | 2031 | return &dma_dom->domain; |
b20ac0d4 JR |
2032 | } |
2033 | ||
04bfdd84 JR |
2034 | static void update_device_table(struct protection_domain *domain) |
2035 | { | |
492667da | 2036 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2037 | |
ea61cddb JR |
2038 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2039 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2040 | } |
2041 | ||
2042 | static void update_domain(struct protection_domain *domain) | |
2043 | { | |
2044 | if (!domain->updated) | |
2045 | return; | |
2046 | ||
2047 | update_device_table(domain); | |
17b124bf JR |
2048 | |
2049 | domain_flush_devices(domain); | |
2050 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2051 | |
2052 | domain->updated = false; | |
2053 | } | |
2054 | ||
8bda3092 JR |
2055 | /* |
2056 | * This function fetches the PTE for a given address in the aperture | |
2057 | */ | |
2058 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2059 | unsigned long address) | |
2060 | { | |
384de729 | 2061 | struct aperture_range *aperture; |
8bda3092 JR |
2062 | u64 *pte, *pte_page; |
2063 | ||
384de729 JR |
2064 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2065 | if (!aperture) | |
2066 | return NULL; | |
2067 | ||
2068 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2069 | if (!pte) { |
cbb9d729 | 2070 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2071 | GFP_ATOMIC); |
384de729 JR |
2072 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2073 | } else | |
8c8c143c | 2074 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2075 | |
04bfdd84 | 2076 | update_domain(&dom->domain); |
8bda3092 JR |
2077 | |
2078 | return pte; | |
2079 | } | |
2080 | ||
431b2a20 JR |
2081 | /* |
2082 | * This is the generic map function. It maps one 4kb page at paddr to | |
2083 | * the given address in the DMA address space for the domain. | |
2084 | */ | |
680525e0 | 2085 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2086 | unsigned long address, |
2087 | phys_addr_t paddr, | |
2088 | int direction) | |
2089 | { | |
2090 | u64 *pte, __pte; | |
2091 | ||
2092 | WARN_ON(address > dom->aperture_size); | |
2093 | ||
2094 | paddr &= PAGE_MASK; | |
2095 | ||
8bda3092 | 2096 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2097 | if (!pte) |
8fd524b3 | 2098 | return DMA_ERROR_CODE; |
cb76c322 JR |
2099 | |
2100 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2101 | ||
2102 | if (direction == DMA_TO_DEVICE) | |
2103 | __pte |= IOMMU_PTE_IR; | |
2104 | else if (direction == DMA_FROM_DEVICE) | |
2105 | __pte |= IOMMU_PTE_IW; | |
2106 | else if (direction == DMA_BIDIRECTIONAL) | |
2107 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2108 | ||
2109 | WARN_ON(*pte); | |
2110 | ||
2111 | *pte = __pte; | |
2112 | ||
2113 | return (dma_addr_t)address; | |
2114 | } | |
2115 | ||
431b2a20 JR |
2116 | /* |
2117 | * The generic unmapping function for on page in the DMA address space. | |
2118 | */ | |
680525e0 | 2119 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2120 | unsigned long address) |
2121 | { | |
384de729 | 2122 | struct aperture_range *aperture; |
cb76c322 JR |
2123 | u64 *pte; |
2124 | ||
2125 | if (address >= dom->aperture_size) | |
2126 | return; | |
2127 | ||
384de729 JR |
2128 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2129 | if (!aperture) | |
2130 | return; | |
2131 | ||
2132 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2133 | if (!pte) | |
2134 | return; | |
cb76c322 | 2135 | |
8c8c143c | 2136 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2137 | |
2138 | WARN_ON(!*pte); | |
2139 | ||
2140 | *pte = 0ULL; | |
2141 | } | |
2142 | ||
431b2a20 JR |
2143 | /* |
2144 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2145 | * contiguous memory region into DMA address space. It is used by all |
2146 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2147 | * Must be called with the domain lock held. |
2148 | */ | |
cb76c322 | 2149 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2150 | struct dma_ops_domain *dma_dom, |
2151 | phys_addr_t paddr, | |
2152 | size_t size, | |
6d4f343f | 2153 | int dir, |
832a90c3 JR |
2154 | bool align, |
2155 | u64 dma_mask) | |
cb76c322 JR |
2156 | { |
2157 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2158 | dma_addr_t address, start, ret; |
cb76c322 | 2159 | unsigned int pages; |
6d4f343f | 2160 | unsigned long align_mask = 0; |
cb76c322 JR |
2161 | int i; |
2162 | ||
e3c449f5 | 2163 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2164 | paddr &= PAGE_MASK; |
2165 | ||
8ecaf8f1 JR |
2166 | INC_STATS_COUNTER(total_map_requests); |
2167 | ||
c1858976 JR |
2168 | if (pages > 1) |
2169 | INC_STATS_COUNTER(cross_page); | |
2170 | ||
6d4f343f JR |
2171 | if (align) |
2172 | align_mask = (1UL << get_order(size)) - 1; | |
2173 | ||
11b83888 | 2174 | retry: |
832a90c3 JR |
2175 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2176 | dma_mask); | |
8fd524b3 | 2177 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2178 | /* |
2179 | * setting next_address here will let the address | |
2180 | * allocator only scan the new allocated range in the | |
2181 | * first run. This is a small optimization. | |
2182 | */ | |
2183 | dma_dom->next_address = dma_dom->aperture_size; | |
2184 | ||
576175c2 | 2185 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2186 | goto out; |
2187 | ||
2188 | /* | |
af901ca1 | 2189 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2190 | * allocation again |
2191 | */ | |
2192 | goto retry; | |
2193 | } | |
cb76c322 JR |
2194 | |
2195 | start = address; | |
2196 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2197 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2198 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2199 | goto out_unmap; |
2200 | ||
cb76c322 JR |
2201 | paddr += PAGE_SIZE; |
2202 | start += PAGE_SIZE; | |
2203 | } | |
2204 | address += offset; | |
2205 | ||
5774f7c5 JR |
2206 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2207 | ||
afa9fdc2 | 2208 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2209 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2210 | dma_dom->need_flush = false; |
318afd41 | 2211 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2212 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2213 | |
cb76c322 JR |
2214 | out: |
2215 | return address; | |
53812c11 JR |
2216 | |
2217 | out_unmap: | |
2218 | ||
2219 | for (--i; i >= 0; --i) { | |
2220 | start -= PAGE_SIZE; | |
680525e0 | 2221 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2222 | } |
2223 | ||
2224 | dma_ops_free_addresses(dma_dom, address, pages); | |
2225 | ||
8fd524b3 | 2226 | return DMA_ERROR_CODE; |
cb76c322 JR |
2227 | } |
2228 | ||
431b2a20 JR |
2229 | /* |
2230 | * Does the reverse of the __map_single function. Must be called with | |
2231 | * the domain lock held too | |
2232 | */ | |
cd8c82e8 | 2233 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2234 | dma_addr_t dma_addr, |
2235 | size_t size, | |
2236 | int dir) | |
2237 | { | |
04e0463e | 2238 | dma_addr_t flush_addr; |
cb76c322 JR |
2239 | dma_addr_t i, start; |
2240 | unsigned int pages; | |
2241 | ||
8fd524b3 | 2242 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2243 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2244 | return; |
2245 | ||
04e0463e | 2246 | flush_addr = dma_addr; |
e3c449f5 | 2247 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2248 | dma_addr &= PAGE_MASK; |
2249 | start = dma_addr; | |
2250 | ||
2251 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2252 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2253 | start += PAGE_SIZE; |
2254 | } | |
2255 | ||
5774f7c5 JR |
2256 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2257 | ||
cb76c322 | 2258 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2259 | |
80be308d | 2260 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2261 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2262 | dma_dom->need_flush = false; |
2263 | } | |
cb76c322 JR |
2264 | } |
2265 | ||
431b2a20 JR |
2266 | /* |
2267 | * The exported map_single function for dma_ops. | |
2268 | */ | |
51491367 FT |
2269 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2270 | unsigned long offset, size_t size, | |
2271 | enum dma_data_direction dir, | |
2272 | struct dma_attrs *attrs) | |
4da70b9e JR |
2273 | { |
2274 | unsigned long flags; | |
4da70b9e | 2275 | struct protection_domain *domain; |
4da70b9e | 2276 | dma_addr_t addr; |
832a90c3 | 2277 | u64 dma_mask; |
51491367 | 2278 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2279 | |
0f2a86f2 JR |
2280 | INC_STATS_COUNTER(cnt_map_single); |
2281 | ||
94f6d190 JR |
2282 | domain = get_domain(dev); |
2283 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2284 | return (dma_addr_t)paddr; |
94f6d190 JR |
2285 | else if (IS_ERR(domain)) |
2286 | return DMA_ERROR_CODE; | |
4da70b9e | 2287 | |
f99c0f1c JR |
2288 | dma_mask = *dev->dma_mask; |
2289 | ||
4da70b9e | 2290 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2291 | |
cd8c82e8 | 2292 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2293 | dma_mask); |
8fd524b3 | 2294 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2295 | goto out; |
2296 | ||
17b124bf | 2297 | domain_flush_complete(domain); |
4da70b9e JR |
2298 | |
2299 | out: | |
2300 | spin_unlock_irqrestore(&domain->lock, flags); | |
2301 | ||
2302 | return addr; | |
2303 | } | |
2304 | ||
431b2a20 JR |
2305 | /* |
2306 | * The exported unmap_single function for dma_ops. | |
2307 | */ | |
51491367 FT |
2308 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2309 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2310 | { |
2311 | unsigned long flags; | |
4da70b9e | 2312 | struct protection_domain *domain; |
4da70b9e | 2313 | |
146a6917 JR |
2314 | INC_STATS_COUNTER(cnt_unmap_single); |
2315 | ||
94f6d190 JR |
2316 | domain = get_domain(dev); |
2317 | if (IS_ERR(domain)) | |
5b28df6f JR |
2318 | return; |
2319 | ||
4da70b9e JR |
2320 | spin_lock_irqsave(&domain->lock, flags); |
2321 | ||
cd8c82e8 | 2322 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2323 | |
17b124bf | 2324 | domain_flush_complete(domain); |
4da70b9e JR |
2325 | |
2326 | spin_unlock_irqrestore(&domain->lock, flags); | |
2327 | } | |
2328 | ||
431b2a20 JR |
2329 | /* |
2330 | * This is a special map_sg function which is used if we should map a | |
2331 | * device which is not handled by an AMD IOMMU in the system. | |
2332 | */ | |
65b050ad JR |
2333 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2334 | int nelems, int dir) | |
2335 | { | |
2336 | struct scatterlist *s; | |
2337 | int i; | |
2338 | ||
2339 | for_each_sg(sglist, s, nelems, i) { | |
2340 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2341 | s->dma_length = s->length; | |
2342 | } | |
2343 | ||
2344 | return nelems; | |
2345 | } | |
2346 | ||
431b2a20 JR |
2347 | /* |
2348 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2349 | * lists). | |
2350 | */ | |
65b050ad | 2351 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2352 | int nelems, enum dma_data_direction dir, |
2353 | struct dma_attrs *attrs) | |
65b050ad JR |
2354 | { |
2355 | unsigned long flags; | |
65b050ad | 2356 | struct protection_domain *domain; |
65b050ad JR |
2357 | int i; |
2358 | struct scatterlist *s; | |
2359 | phys_addr_t paddr; | |
2360 | int mapped_elems = 0; | |
832a90c3 | 2361 | u64 dma_mask; |
65b050ad | 2362 | |
d03f067a JR |
2363 | INC_STATS_COUNTER(cnt_map_sg); |
2364 | ||
94f6d190 JR |
2365 | domain = get_domain(dev); |
2366 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2367 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2368 | else if (IS_ERR(domain)) |
2369 | return 0; | |
dbcc112e | 2370 | |
832a90c3 | 2371 | dma_mask = *dev->dma_mask; |
65b050ad | 2372 | |
65b050ad JR |
2373 | spin_lock_irqsave(&domain->lock, flags); |
2374 | ||
2375 | for_each_sg(sglist, s, nelems, i) { | |
2376 | paddr = sg_phys(s); | |
2377 | ||
cd8c82e8 | 2378 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2379 | paddr, s->length, dir, false, |
2380 | dma_mask); | |
65b050ad JR |
2381 | |
2382 | if (s->dma_address) { | |
2383 | s->dma_length = s->length; | |
2384 | mapped_elems++; | |
2385 | } else | |
2386 | goto unmap; | |
65b050ad JR |
2387 | } |
2388 | ||
17b124bf | 2389 | domain_flush_complete(domain); |
65b050ad JR |
2390 | |
2391 | out: | |
2392 | spin_unlock_irqrestore(&domain->lock, flags); | |
2393 | ||
2394 | return mapped_elems; | |
2395 | unmap: | |
2396 | for_each_sg(sglist, s, mapped_elems, i) { | |
2397 | if (s->dma_address) | |
cd8c82e8 | 2398 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2399 | s->dma_length, dir); |
2400 | s->dma_address = s->dma_length = 0; | |
2401 | } | |
2402 | ||
2403 | mapped_elems = 0; | |
2404 | ||
2405 | goto out; | |
2406 | } | |
2407 | ||
431b2a20 JR |
2408 | /* |
2409 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2410 | * lists). | |
2411 | */ | |
65b050ad | 2412 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2413 | int nelems, enum dma_data_direction dir, |
2414 | struct dma_attrs *attrs) | |
65b050ad JR |
2415 | { |
2416 | unsigned long flags; | |
65b050ad JR |
2417 | struct protection_domain *domain; |
2418 | struct scatterlist *s; | |
65b050ad JR |
2419 | int i; |
2420 | ||
55877a6b JR |
2421 | INC_STATS_COUNTER(cnt_unmap_sg); |
2422 | ||
94f6d190 JR |
2423 | domain = get_domain(dev); |
2424 | if (IS_ERR(domain)) | |
5b28df6f JR |
2425 | return; |
2426 | ||
65b050ad JR |
2427 | spin_lock_irqsave(&domain->lock, flags); |
2428 | ||
2429 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2430 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2431 | s->dma_length, dir); |
65b050ad JR |
2432 | s->dma_address = s->dma_length = 0; |
2433 | } | |
2434 | ||
17b124bf | 2435 | domain_flush_complete(domain); |
65b050ad JR |
2436 | |
2437 | spin_unlock_irqrestore(&domain->lock, flags); | |
2438 | } | |
2439 | ||
431b2a20 JR |
2440 | /* |
2441 | * The exported alloc_coherent function for dma_ops. | |
2442 | */ | |
5d8b53cf JR |
2443 | static void *alloc_coherent(struct device *dev, size_t size, |
2444 | dma_addr_t *dma_addr, gfp_t flag) | |
2445 | { | |
2446 | unsigned long flags; | |
2447 | void *virt_addr; | |
5d8b53cf | 2448 | struct protection_domain *domain; |
5d8b53cf | 2449 | phys_addr_t paddr; |
832a90c3 | 2450 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2451 | |
c8f0fb36 JR |
2452 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2453 | ||
94f6d190 JR |
2454 | domain = get_domain(dev); |
2455 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2456 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2457 | *dma_addr = __pa(virt_addr); | |
2458 | return virt_addr; | |
94f6d190 JR |
2459 | } else if (IS_ERR(domain)) |
2460 | return NULL; | |
5d8b53cf | 2461 | |
f99c0f1c JR |
2462 | dma_mask = dev->coherent_dma_mask; |
2463 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2464 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2465 | |
2466 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2467 | if (!virt_addr) | |
b25ae679 | 2468 | return NULL; |
5d8b53cf | 2469 | |
5d8b53cf JR |
2470 | paddr = virt_to_phys(virt_addr); |
2471 | ||
832a90c3 JR |
2472 | if (!dma_mask) |
2473 | dma_mask = *dev->dma_mask; | |
2474 | ||
5d8b53cf JR |
2475 | spin_lock_irqsave(&domain->lock, flags); |
2476 | ||
cd8c82e8 | 2477 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2478 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2479 | |
8fd524b3 | 2480 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2481 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2482 | goto out_free; |
367d04c4 | 2483 | } |
5d8b53cf | 2484 | |
17b124bf | 2485 | domain_flush_complete(domain); |
5d8b53cf | 2486 | |
5d8b53cf JR |
2487 | spin_unlock_irqrestore(&domain->lock, flags); |
2488 | ||
2489 | return virt_addr; | |
5b28df6f JR |
2490 | |
2491 | out_free: | |
2492 | ||
2493 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2494 | ||
2495 | return NULL; | |
5d8b53cf JR |
2496 | } |
2497 | ||
431b2a20 JR |
2498 | /* |
2499 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2500 | */ |
5d8b53cf JR |
2501 | static void free_coherent(struct device *dev, size_t size, |
2502 | void *virt_addr, dma_addr_t dma_addr) | |
2503 | { | |
2504 | unsigned long flags; | |
5d8b53cf | 2505 | struct protection_domain *domain; |
5d8b53cf | 2506 | |
5d31ee7e JR |
2507 | INC_STATS_COUNTER(cnt_free_coherent); |
2508 | ||
94f6d190 JR |
2509 | domain = get_domain(dev); |
2510 | if (IS_ERR(domain)) | |
5b28df6f JR |
2511 | goto free_mem; |
2512 | ||
5d8b53cf JR |
2513 | spin_lock_irqsave(&domain->lock, flags); |
2514 | ||
cd8c82e8 | 2515 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2516 | |
17b124bf | 2517 | domain_flush_complete(domain); |
5d8b53cf JR |
2518 | |
2519 | spin_unlock_irqrestore(&domain->lock, flags); | |
2520 | ||
2521 | free_mem: | |
2522 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2523 | } | |
2524 | ||
b39ba6ad JR |
2525 | /* |
2526 | * This function is called by the DMA layer to find out if we can handle a | |
2527 | * particular device. It is part of the dma_ops. | |
2528 | */ | |
2529 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2530 | { | |
420aef8a | 2531 | return check_device(dev); |
b39ba6ad JR |
2532 | } |
2533 | ||
c432f3df | 2534 | /* |
431b2a20 JR |
2535 | * The function for pre-allocating protection domains. |
2536 | * | |
c432f3df JR |
2537 | * If the driver core informs the DMA layer if a driver grabs a device |
2538 | * we don't need to preallocate the protection domains anymore. | |
2539 | * For now we have to. | |
2540 | */ | |
0e93dd88 | 2541 | static void prealloc_protection_domains(void) |
c432f3df | 2542 | { |
5abcdba4 | 2543 | struct iommu_dev_data *dev_data; |
c432f3df | 2544 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 2545 | struct pci_dev *dev = NULL; |
98fc5a69 | 2546 | u16 devid; |
c432f3df | 2547 | |
d18c69d3 | 2548 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2549 | |
2550 | /* Do we handle this device? */ | |
2551 | if (!check_device(&dev->dev)) | |
c432f3df | 2552 | continue; |
98fc5a69 | 2553 | |
5abcdba4 JR |
2554 | dev_data = get_dev_data(&dev->dev); |
2555 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
2556 | /* Make sure passthrough domain is allocated */ | |
2557 | alloc_passthrough_domain(); | |
2558 | dev_data->passthrough = true; | |
2559 | attach_device(&dev->dev, pt_domain); | |
2560 | pr_info("AMD-Vi: Using passthough domain for device %s\n", | |
2561 | dev_name(&dev->dev)); | |
2562 | } | |
2563 | ||
98fc5a69 | 2564 | /* Is there already any domain for it? */ |
15898bbc | 2565 | if (domain_for_device(&dev->dev)) |
c432f3df | 2566 | continue; |
98fc5a69 JR |
2567 | |
2568 | devid = get_device_id(&dev->dev); | |
2569 | ||
87a64d52 | 2570 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2571 | if (!dma_dom) |
2572 | continue; | |
2573 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2574 | dma_dom->target_dev = devid; |
2575 | ||
15898bbc | 2576 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2577 | |
bd60b735 | 2578 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2579 | } |
2580 | } | |
2581 | ||
160c1d8e | 2582 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2583 | .alloc_coherent = alloc_coherent, |
2584 | .free_coherent = free_coherent, | |
51491367 FT |
2585 | .map_page = map_page, |
2586 | .unmap_page = unmap_page, | |
6631ee9d JR |
2587 | .map_sg = map_sg, |
2588 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2589 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2590 | }; |
2591 | ||
27c2127a JR |
2592 | static unsigned device_dma_ops_init(void) |
2593 | { | |
5abcdba4 | 2594 | struct iommu_dev_data *dev_data; |
27c2127a JR |
2595 | struct pci_dev *pdev = NULL; |
2596 | unsigned unhandled = 0; | |
2597 | ||
2598 | for_each_pci_dev(pdev) { | |
2599 | if (!check_device(&pdev->dev)) { | |
2600 | unhandled += 1; | |
2601 | continue; | |
2602 | } | |
2603 | ||
5abcdba4 JR |
2604 | dev_data = get_dev_data(&pdev->dev); |
2605 | ||
2606 | if (!dev_data->passthrough) | |
2607 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2608 | else | |
2609 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
2610 | } |
2611 | ||
2612 | return unhandled; | |
2613 | } | |
2614 | ||
431b2a20 JR |
2615 | /* |
2616 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2617 | */ | |
f5325094 JR |
2618 | |
2619 | void __init amd_iommu_init_api(void) | |
2620 | { | |
2cc21c42 | 2621 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2622 | } |
2623 | ||
6631ee9d JR |
2624 | int __init amd_iommu_init_dma_ops(void) |
2625 | { | |
2626 | struct amd_iommu *iommu; | |
27c2127a | 2627 | int ret, unhandled; |
6631ee9d | 2628 | |
431b2a20 JR |
2629 | /* |
2630 | * first allocate a default protection domain for every IOMMU we | |
2631 | * found in the system. Devices not assigned to any other | |
2632 | * protection domain will be assigned to the default one. | |
2633 | */ | |
3bd22172 | 2634 | for_each_iommu(iommu) { |
87a64d52 | 2635 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2636 | if (iommu->default_dom == NULL) |
2637 | return -ENOMEM; | |
e2dc14a2 | 2638 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2639 | ret = iommu_init_unity_mappings(iommu); |
2640 | if (ret) | |
2641 | goto free_domains; | |
2642 | } | |
2643 | ||
431b2a20 | 2644 | /* |
8793abeb | 2645 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2646 | */ |
8793abeb | 2647 | prealloc_protection_domains(); |
6631ee9d JR |
2648 | |
2649 | iommu_detected = 1; | |
75f1cdf1 | 2650 | swiotlb = 0; |
6631ee9d | 2651 | |
431b2a20 | 2652 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2653 | unhandled = device_dma_ops_init(); |
2654 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2655 | /* There are unhandled devices - initialize swiotlb for them */ | |
2656 | swiotlb = 1; | |
2657 | } | |
6631ee9d | 2658 | |
7f26508b JR |
2659 | amd_iommu_stats_init(); |
2660 | ||
6631ee9d JR |
2661 | return 0; |
2662 | ||
2663 | free_domains: | |
2664 | ||
3bd22172 | 2665 | for_each_iommu(iommu) { |
6631ee9d JR |
2666 | if (iommu->default_dom) |
2667 | dma_ops_domain_free(iommu->default_dom); | |
2668 | } | |
2669 | ||
2670 | return ret; | |
2671 | } | |
6d98cd80 JR |
2672 | |
2673 | /***************************************************************************** | |
2674 | * | |
2675 | * The following functions belong to the exported interface of AMD IOMMU | |
2676 | * | |
2677 | * This interface allows access to lower level functions of the IOMMU | |
2678 | * like protection domain handling and assignement of devices to domains | |
2679 | * which is not possible with the dma_ops interface. | |
2680 | * | |
2681 | *****************************************************************************/ | |
2682 | ||
6d98cd80 JR |
2683 | static void cleanup_domain(struct protection_domain *domain) |
2684 | { | |
492667da | 2685 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2686 | unsigned long flags; |
6d98cd80 JR |
2687 | |
2688 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2689 | ||
492667da | 2690 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 2691 | __detach_device(dev_data); |
492667da JR |
2692 | atomic_set(&dev_data->bind, 0); |
2693 | } | |
6d98cd80 JR |
2694 | |
2695 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2696 | } | |
2697 | ||
2650815f JR |
2698 | static void protection_domain_free(struct protection_domain *domain) |
2699 | { | |
2700 | if (!domain) | |
2701 | return; | |
2702 | ||
aeb26f55 JR |
2703 | del_domain_from_list(domain); |
2704 | ||
2650815f JR |
2705 | if (domain->id) |
2706 | domain_id_free(domain->id); | |
2707 | ||
2708 | kfree(domain); | |
2709 | } | |
2710 | ||
2711 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2712 | { |
2713 | struct protection_domain *domain; | |
2714 | ||
2715 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2716 | if (!domain) | |
2650815f | 2717 | return NULL; |
c156e347 JR |
2718 | |
2719 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2720 | mutex_init(&domain->api_lock); |
c156e347 JR |
2721 | domain->id = domain_id_alloc(); |
2722 | if (!domain->id) | |
2650815f | 2723 | goto out_err; |
7c392cbe | 2724 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2725 | |
aeb26f55 JR |
2726 | add_domain_to_list(domain); |
2727 | ||
2650815f JR |
2728 | return domain; |
2729 | ||
2730 | out_err: | |
2731 | kfree(domain); | |
2732 | ||
2733 | return NULL; | |
2734 | } | |
2735 | ||
5abcdba4 JR |
2736 | static int __init alloc_passthrough_domain(void) |
2737 | { | |
2738 | if (pt_domain != NULL) | |
2739 | return 0; | |
2740 | ||
2741 | /* allocate passthrough domain */ | |
2742 | pt_domain = protection_domain_alloc(); | |
2743 | if (!pt_domain) | |
2744 | return -ENOMEM; | |
2745 | ||
2746 | pt_domain->mode = PAGE_MODE_NONE; | |
2747 | ||
2748 | return 0; | |
2749 | } | |
2650815f JR |
2750 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
2751 | { | |
2752 | struct protection_domain *domain; | |
2753 | ||
2754 | domain = protection_domain_alloc(); | |
2755 | if (!domain) | |
c156e347 | 2756 | goto out_free; |
2650815f JR |
2757 | |
2758 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2759 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2760 | if (!domain->pt_root) | |
2761 | goto out_free; | |
2762 | ||
2763 | dom->priv = domain; | |
2764 | ||
2765 | return 0; | |
2766 | ||
2767 | out_free: | |
2650815f | 2768 | protection_domain_free(domain); |
c156e347 JR |
2769 | |
2770 | return -ENOMEM; | |
2771 | } | |
2772 | ||
98383fc3 JR |
2773 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2774 | { | |
2775 | struct protection_domain *domain = dom->priv; | |
2776 | ||
2777 | if (!domain) | |
2778 | return; | |
2779 | ||
2780 | if (domain->dev_cnt > 0) | |
2781 | cleanup_domain(domain); | |
2782 | ||
2783 | BUG_ON(domain->dev_cnt != 0); | |
2784 | ||
2785 | free_pagetable(domain); | |
2786 | ||
8b408fe4 | 2787 | protection_domain_free(domain); |
98383fc3 JR |
2788 | |
2789 | dom->priv = NULL; | |
2790 | } | |
2791 | ||
684f2888 JR |
2792 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2793 | struct device *dev) | |
2794 | { | |
657cbb6b | 2795 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2796 | struct amd_iommu *iommu; |
684f2888 JR |
2797 | u16 devid; |
2798 | ||
98fc5a69 | 2799 | if (!check_device(dev)) |
684f2888 JR |
2800 | return; |
2801 | ||
98fc5a69 | 2802 | devid = get_device_id(dev); |
684f2888 | 2803 | |
657cbb6b | 2804 | if (dev_data->domain != NULL) |
15898bbc | 2805 | detach_device(dev); |
684f2888 JR |
2806 | |
2807 | iommu = amd_iommu_rlookup_table[devid]; | |
2808 | if (!iommu) | |
2809 | return; | |
2810 | ||
684f2888 JR |
2811 | iommu_completion_wait(iommu); |
2812 | } | |
2813 | ||
01106066 JR |
2814 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2815 | struct device *dev) | |
2816 | { | |
2817 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2818 | struct iommu_dev_data *dev_data; |
01106066 | 2819 | struct amd_iommu *iommu; |
15898bbc | 2820 | int ret; |
01106066 | 2821 | |
98fc5a69 | 2822 | if (!check_device(dev)) |
01106066 JR |
2823 | return -EINVAL; |
2824 | ||
657cbb6b JR |
2825 | dev_data = dev->archdata.iommu; |
2826 | ||
f62dda66 | 2827 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
2828 | if (!iommu) |
2829 | return -EINVAL; | |
2830 | ||
657cbb6b | 2831 | if (dev_data->domain) |
15898bbc | 2832 | detach_device(dev); |
01106066 | 2833 | |
15898bbc | 2834 | ret = attach_device(dev, domain); |
01106066 JR |
2835 | |
2836 | iommu_completion_wait(iommu); | |
2837 | ||
15898bbc | 2838 | return ret; |
01106066 JR |
2839 | } |
2840 | ||
468e2366 JR |
2841 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2842 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2843 | { |
468e2366 | 2844 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2845 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2846 | int prot = 0; |
2847 | int ret; | |
2848 | ||
2849 | if (iommu_prot & IOMMU_READ) | |
2850 | prot |= IOMMU_PROT_IR; | |
2851 | if (iommu_prot & IOMMU_WRITE) | |
2852 | prot |= IOMMU_PROT_IW; | |
2853 | ||
5d214fe6 | 2854 | mutex_lock(&domain->api_lock); |
795e74f7 | 2855 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2856 | mutex_unlock(&domain->api_lock); |
2857 | ||
795e74f7 | 2858 | return ret; |
c6229ca6 JR |
2859 | } |
2860 | ||
468e2366 JR |
2861 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2862 | int gfp_order) | |
eb74ff6c | 2863 | { |
eb74ff6c | 2864 | struct protection_domain *domain = dom->priv; |
468e2366 | 2865 | unsigned long page_size, unmap_size; |
eb74ff6c | 2866 | |
468e2366 | 2867 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2868 | |
5d214fe6 | 2869 | mutex_lock(&domain->api_lock); |
468e2366 | 2870 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2871 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2872 | |
17b124bf | 2873 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2874 | |
468e2366 | 2875 | return get_order(unmap_size); |
eb74ff6c JR |
2876 | } |
2877 | ||
645c4c8d JR |
2878 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2879 | unsigned long iova) | |
2880 | { | |
2881 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2882 | unsigned long offset_mask; |
645c4c8d | 2883 | phys_addr_t paddr; |
f03152bb | 2884 | u64 *pte, __pte; |
645c4c8d | 2885 | |
24cd7723 | 2886 | pte = fetch_pte(domain, iova); |
645c4c8d | 2887 | |
a6d41a40 | 2888 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2889 | return 0; |
2890 | ||
f03152bb JR |
2891 | if (PM_PTE_LEVEL(*pte) == 0) |
2892 | offset_mask = PAGE_SIZE - 1; | |
2893 | else | |
2894 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2895 | ||
2896 | __pte = *pte & PM_ADDR_MASK; | |
2897 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2898 | |
2899 | return paddr; | |
2900 | } | |
2901 | ||
dbb9fd86 SY |
2902 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2903 | unsigned long cap) | |
2904 | { | |
80a506b8 JR |
2905 | switch (cap) { |
2906 | case IOMMU_CAP_CACHE_COHERENCY: | |
2907 | return 1; | |
2908 | } | |
2909 | ||
dbb9fd86 SY |
2910 | return 0; |
2911 | } | |
2912 | ||
26961efe JR |
2913 | static struct iommu_ops amd_iommu_ops = { |
2914 | .domain_init = amd_iommu_domain_init, | |
2915 | .domain_destroy = amd_iommu_domain_destroy, | |
2916 | .attach_dev = amd_iommu_attach_device, | |
2917 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2918 | .map = amd_iommu_map, |
2919 | .unmap = amd_iommu_unmap, | |
26961efe | 2920 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2921 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2922 | }; |
2923 | ||
0feae533 JR |
2924 | /***************************************************************************** |
2925 | * | |
2926 | * The next functions do a basic initialization of IOMMU for pass through | |
2927 | * mode | |
2928 | * | |
2929 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2930 | * DMA-API translation. | |
2931 | * | |
2932 | *****************************************************************************/ | |
2933 | ||
2934 | int __init amd_iommu_init_passthrough(void) | |
2935 | { | |
5abcdba4 | 2936 | struct iommu_dev_data *dev_data; |
0feae533 | 2937 | struct pci_dev *dev = NULL; |
5abcdba4 | 2938 | struct amd_iommu *iommu; |
15898bbc | 2939 | u16 devid; |
5abcdba4 | 2940 | int ret; |
0feae533 | 2941 | |
5abcdba4 JR |
2942 | ret = alloc_passthrough_domain(); |
2943 | if (ret) | |
2944 | return ret; | |
0feae533 | 2945 | |
6c54aabd | 2946 | for_each_pci_dev(dev) { |
98fc5a69 | 2947 | if (!check_device(&dev->dev)) |
0feae533 JR |
2948 | continue; |
2949 | ||
5abcdba4 JR |
2950 | dev_data = get_dev_data(&dev->dev); |
2951 | dev_data->passthrough = true; | |
2952 | ||
98fc5a69 JR |
2953 | devid = get_device_id(&dev->dev); |
2954 | ||
15898bbc | 2955 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2956 | if (!iommu) |
2957 | continue; | |
2958 | ||
15898bbc | 2959 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2960 | } |
2961 | ||
2962 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2963 | ||
2964 | return 0; | |
2965 | } | |
72e1dcc4 JR |
2966 | |
2967 | /* IOMMUv2 specific functions */ | |
2968 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
2969 | { | |
2970 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
2971 | } | |
2972 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
2973 | ||
2974 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
2975 | { | |
2976 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
2977 | } | |
2978 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); |