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bnx2x: Support reading I2C EEPROM SFF8472
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
c96bdc0c
DK		 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
ec6ba945
VZ		 68};
69
70#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72static const struct {
73 long offset;
74 int size;
75 u32 flags;
76#define STATS_FLAGS_PORT 1
77#define STATS_FLAGS_FUNC 2
78#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80} bnx2x_stats_arr[] = {
81/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
c96bdc0c
DK		 182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
e9939c80
YM		 184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
07ba6af4 189
1ac9e428
YR		 190static int bnx2x_get_port_type(struct bnx2x *bp)
191{
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217}
ec6ba945 218
de0c62db
DK		 219static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
220{
221 struct bnx2x *bp = netdev_priv(dev);
a22f0788 222 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 223
a22f0788
YR		 224 /* Dual Media boards present all available port types */
225 cmd->supported = bp->port.supported[cfg_idx] |
226 (bp->port.supported[cfg_idx ^ 1] &
227 (SUPPORTED_TP | SUPPORTED_FIBRE));
228 cmd->advertising = bp->port.advertising[cfg_idx];
dbef807e
YM		 229 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
230 ETH_PHY_SFP_1G_FIBER) {
231 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
232 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
233 }
de0c62db 234
59694f00
YM		 235 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
236 !(bp->flags & MF_FUNC_DIS)) {
2de67439 237 cmd->duplex = bp->link_vars.duplex;
38298461
YM		 238
239 if (IS_MF(bp) && !BP_NOMCP(bp))
240 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
59694f00
YM		 241 else
242 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 243 } else {
38298461
YM		 244 cmd->duplex = DUPLEX_UNKNOWN;
245 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 246 }
f2e0899f 247
1ac9e428 248 cmd->port = bnx2x_get_port_type(bp);
a22f0788 249
de0c62db
DK		 250 cmd->phy_address = bp->mdio.prtad;
251 cmd->transceiver = XCVR_INTERNAL;
252
a22f0788 253 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 254 cmd->autoneg = AUTONEG_ENABLE;
255 else
256 cmd->autoneg = AUTONEG_DISABLE;
257
9e7e8399
MY		 258 /* Publish LP advertised speeds and FC */
259 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
260 u32 status = bp->link_vars.link_status;
261
262 cmd->lp_advertising |= ADVERTISED_Autoneg;
263 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
264 cmd->lp_advertising |= ADVERTISED_Pause;
265 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
266 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
267
268 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
269 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
270 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
271 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
272 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
273 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
274 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
275 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
276 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
277 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
278 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
279 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
280 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
281 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
282 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
283 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
be94bea7
YR		 284 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
285 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
9e7e8399
MY		 286 }
287
de0c62db
DK		 288 cmd->maxtxpkt = 0;
289 cmd->maxrxpkt = 0;
290
51c1a580 291 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 292 " supported 0x%x advertising 0x%x speed %u\n"
293 " duplex %d port %d phy_address %d transceiver %d\n"
294 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 295 cmd->cmd, cmd->supported, cmd->advertising,
296 ethtool_cmd_speed(cmd),
de0c62db
DK		 297 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
298 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
299
300 return 0;
301}
302
303static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
304{
305 struct bnx2x *bp = netdev_priv(dev);
a22f0788 306 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 307 u32 speed, phy_idx;
de0c62db 308
0793f83f 309 if (IS_MF_SD(bp))
de0c62db
DK		 310 return 0;
311
51c1a580 312 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 313 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 314 " duplex %d port %d phy_address %d transceiver %d\n"
315 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 316 cmd->cmd, cmd->supported, cmd->advertising,
317 ethtool_cmd_speed(cmd),
de0c62db
DK		 318 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
319 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
320
b3337e4c 321 speed = ethtool_cmd_speed(cmd);
0793f83f 322
38298461
YM		 323 /* If recieved a request for an unknown duplex, assume full*/
324 if (cmd->duplex == DUPLEX_UNKNOWN)
325 cmd->duplex = DUPLEX_FULL;
326
0793f83f 327 if (IS_MF_SI(bp)) {
e3835b99 328 u32 part;
0793f83f
DK		 329 u32 line_speed = bp->link_vars.line_speed;
330
331 /* use 10G if no link detected */
332 if (!line_speed)
333 line_speed = 10000;
334
335 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 336 DP(BNX2X_MSG_ETHTOOL,
337 "To set speed BC %X or higher is required, please upgrade BC\n",
338 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 339 return -EINVAL;
340 }
e3835b99 341
faa6fcbb 342 part = (speed * 100) / line_speed;
e3835b99 343
faa6fcbb 344 if (line_speed < speed || !part) {
51c1a580
MS		 345 DP(BNX2X_MSG_ETHTOOL,
346 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 347 return -EINVAL;
348 }
0793f83f 349
e3835b99
DK		 350 if (bp->state != BNX2X_STATE_OPEN)
351 /* store value for following "load" */
352 bp->pending_max = part;
353 else
354 bnx2x_update_max_mf_config(bp, part);
0793f83f 355
0793f83f
DK		 356 return 0;
357 }
358
a22f0788
YR		 359 cfg_idx = bnx2x_get_link_cfg_idx(bp);
360 old_multi_phy_config = bp->link_params.multi_phy_config;
361 switch (cmd->port) {
362 case PORT_TP:
363 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
364 break; /* no port change */
365
366 if (!(bp->port.supported[0] & SUPPORTED_TP ||
367 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 368 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 369 return -EINVAL;
370 }
371 bp->link_params.multi_phy_config &=
372 ~PORT_HW_CFG_PHY_SELECTION_MASK;
373 if (bp->link_params.multi_phy_config &
374 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
375 bp->link_params.multi_phy_config |=
376 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
377 else
378 bp->link_params.multi_phy_config |=
379 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
380 break;
381 case PORT_FIBRE:
bfdb5823 382 case PORT_DA:
a22f0788
YR		 383 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
384 break; /* no port change */
385
386 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
387 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 388 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 389 return -EINVAL;
390 }
391 bp->link_params.multi_phy_config &=
392 ~PORT_HW_CFG_PHY_SELECTION_MASK;
393 if (bp->link_params.multi_phy_config &
394 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
395 bp->link_params.multi_phy_config |=
396 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
397 else
398 bp->link_params.multi_phy_config |=
399 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
400 break;
401 default:
51c1a580 402 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 403 return -EINVAL;
404 }
2de67439 405 /* Save new config in case command complete successfully */
a22f0788
YR		 406 new_multi_phy_config = bp->link_params.multi_phy_config;
407 /* Get the new cfg_idx */
408 cfg_idx = bnx2x_get_link_cfg_idx(bp);
409 /* Restore old config in case command failed */
410 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 411 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 412
de0c62db 413 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 414 u32 an_supported_speed = bp->port.supported[cfg_idx];
415 if (bp->link_params.phy[EXT_PHY1].type ==
416 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
417 an_supported_speed |= (SUPPORTED_100baseT_Half |
418 SUPPORTED_100baseT_Full);
a22f0788 419 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 420 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 421 return -EINVAL;
422 }
423
424 /* advertise the requested speed and duplex if supported */
75318327 425 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 426 DP(BNX2X_MSG_ETHTOOL,
427 "Advertisement parameters are not supported\n");
8d661637
YR		 428 return -EINVAL;
429 }
de0c62db 430
a22f0788 431 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 432 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
433 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 434 cmd->advertising);
8d661637
YR		 435 if (cmd->advertising) {
436
437 bp->link_params.speed_cap_mask[cfg_idx] = 0;
438 if (cmd->advertising & ADVERTISED_10baseT_Half) {
439 bp->link_params.speed_cap_mask[cfg_idx] |=
440 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
441 }
442 if (cmd->advertising & ADVERTISED_10baseT_Full)
443 bp->link_params.speed_cap_mask[cfg_idx] |=
444 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 445
8d661637
YR		 446 if (cmd->advertising & ADVERTISED_100baseT_Full)
447 bp->link_params.speed_cap_mask[cfg_idx] |=
448 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
449
450 if (cmd->advertising & ADVERTISED_100baseT_Half) {
451 bp->link_params.speed_cap_mask[cfg_idx] |=
452 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
453 }
454 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
455 bp->link_params.speed_cap_mask[cfg_idx] |=
456 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
457 }
458 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
459 ADVERTISED_1000baseKX_Full))
460 bp->link_params.speed_cap_mask[cfg_idx] |=
461 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
462
463 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
464 ADVERTISED_10000baseKX4_Full |
465 ADVERTISED_10000baseKR_Full))
466 bp->link_params.speed_cap_mask[cfg_idx] |=
467 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
be94bea7
YR		 468
469 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
470 bp->link_params.speed_cap_mask[cfg_idx] |=
471 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
8d661637 472 }
de0c62db
DK		 473 } else { /* forced speed */
474 /* advertise the requested speed and duplex if supported */
a22f0788 475 switch (speed) {
de0c62db
DK		 476 case SPEED_10:
477 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 478 if (!(bp->port.supported[cfg_idx] &
de0c62db 479 SUPPORTED_10baseT_Full)) {
51c1a580 480 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 481 "10M full not supported\n");
482 return -EINVAL;
483 }
484
485 advertising = (ADVERTISED_10baseT_Full |
486 ADVERTISED_TP);
487 } else {
a22f0788 488 if (!(bp->port.supported[cfg_idx] &
de0c62db 489 SUPPORTED_10baseT_Half)) {
51c1a580 490 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 491 "10M half not supported\n");
492 return -EINVAL;
493 }
494
495 advertising = (ADVERTISED_10baseT_Half |
496 ADVERTISED_TP);
497 }
498 break;
499
500 case SPEED_100:
501 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 502 if (!(bp->port.supported[cfg_idx] &
de0c62db 503 SUPPORTED_100baseT_Full)) {
51c1a580 504 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 505 "100M full not supported\n");
506 return -EINVAL;
507 }
508
509 advertising = (ADVERTISED_100baseT_Full |
510 ADVERTISED_TP);
511 } else {
a22f0788 512 if (!(bp->port.supported[cfg_idx] &
de0c62db 513 SUPPORTED_100baseT_Half)) {
51c1a580 514 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 515 "100M half not supported\n");
516 return -EINVAL;
517 }
518
519 advertising = (ADVERTISED_100baseT_Half |
520 ADVERTISED_TP);
521 }
522 break;
523
524 case SPEED_1000:
525 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 526 DP(BNX2X_MSG_ETHTOOL,
527 "1G half not supported\n");
de0c62db
DK		 528 return -EINVAL;
529 }
530
a22f0788
YR		 531 if (!(bp->port.supported[cfg_idx] &
532 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 533 DP(BNX2X_MSG_ETHTOOL,
534 "1G full not supported\n");
de0c62db
DK		 535 return -EINVAL;
536 }
537
538 advertising = (ADVERTISED_1000baseT_Full |
539 ADVERTISED_TP);
540 break;
541
542 case SPEED_2500:
543 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 544 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 545 "2.5G half not supported\n");
546 return -EINVAL;
547 }
548
a22f0788
YR		 549 if (!(bp->port.supported[cfg_idx]
550 & SUPPORTED_2500baseX_Full)) {
51c1a580 551 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 552 "2.5G full not supported\n");
553 return -EINVAL;
554 }
555
556 advertising = (ADVERTISED_2500baseX_Full |
557 ADVERTISED_TP);
558 break;
559
560 case SPEED_10000:
561 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 562 DP(BNX2X_MSG_ETHTOOL,
563 "10G half not supported\n");
de0c62db
DK		 564 return -EINVAL;
565 }
dbef807e 566 phy_idx = bnx2x_get_cur_phy_idx(bp);
a22f0788 567 if (!(bp->port.supported[cfg_idx]
dbef807e
YM		 568 & SUPPORTED_10000baseT_Full) ||
569 (bp->link_params.phy[phy_idx].media_type ==
570 ETH_PHY_SFP_1G_FIBER)) {
51c1a580
MS		 571 DP(BNX2X_MSG_ETHTOOL,
572 "10G full not supported\n");
de0c62db
DK		 573 return -EINVAL;
574 }
575
576 advertising = (ADVERTISED_10000baseT_Full |
577 ADVERTISED_FIBRE);
578 break;
579
580 default:
51c1a580 581 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 582 return -EINVAL;
583 }
584
a22f0788
YR		 585 bp->link_params.req_line_speed[cfg_idx] = speed;
586 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
587 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 588 }
589
51c1a580 590 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 591 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 592 bp->link_params.req_line_speed[cfg_idx],
593 bp->link_params.req_duplex[cfg_idx],
594 bp->port.advertising[cfg_idx]);
de0c62db 595
a22f0788
YR		 596 /* Set new config */
597 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 598 if (netif_running(dev)) {
599 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
600 bnx2x_link_set(bp);
601 }
602
603 return 0;
604}
605
07ba6af4
MS		 606#define DUMP_ALL_PRESETS 0x1FFF
607#define DUMP_MAX_PRESETS 13
0fea29c1 608
07ba6af4 609static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
0fea29c1
VZ		 610{
611 if (CHIP_IS_E1(bp))
07ba6af4 612 return dump_num_registers[0][preset-1];
0fea29c1 613 else if (CHIP_IS_E1H(bp))
07ba6af4 614 return dump_num_registers[1][preset-1];
0fea29c1 615 else if (CHIP_IS_E2(bp))
07ba6af4 616 return dump_num_registers[2][preset-1];
0fea29c1 617 else if (CHIP_IS_E3A0(bp))
07ba6af4 618 return dump_num_registers[3][preset-1];
0fea29c1 619 else if (CHIP_IS_E3B0(bp))
07ba6af4 620 return dump_num_registers[4][preset-1];
0fea29c1 621 else
07ba6af4
MS		 622 return 0;
623}
624
625static int __bnx2x_get_regs_len(struct bnx2x *bp)
626{
627 u32 preset_idx;
628 int regdump_len = 0;
629
630 /* Calculate the total preset regs length */
631 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
632 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
633
634 return regdump_len;
635}
636
637static int bnx2x_get_regs_len(struct net_device *dev)
638{
639 struct bnx2x *bp = netdev_priv(dev);
640 int regdump_len = 0;
641
642 regdump_len = __bnx2x_get_regs_len(bp);
643 regdump_len *= 4;
644 regdump_len += sizeof(struct dump_header);
645
646 return regdump_len;
0fea29c1
VZ		 647}
648
07ba6af4
MS		 649#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
650#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
651#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
652#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
653#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
654
655#define IS_REG_IN_PRESET(presets, idx) \
656 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
657
0fea29c1 658/******* Paged registers info selectors ********/
1191cb83 659static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 660{
661 if (CHIP_IS_E2(bp))
662 return page_vals_e2;
663 else if (CHIP_IS_E3(bp))
664 return page_vals_e3;
665 else
666 return NULL;
667}
668
1191cb83 669static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 670{
671 if (CHIP_IS_E2(bp))
672 return PAGE_MODE_VALUES_E2;
673 else if (CHIP_IS_E3(bp))
674 return PAGE_MODE_VALUES_E3;
675 else
676 return 0;
677}
678
1191cb83 679static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 680{
681 if (CHIP_IS_E2(bp))
682 return page_write_regs_e2;
683 else if (CHIP_IS_E3(bp))
684 return page_write_regs_e3;
685 else
686 return NULL;
687}
688
1191cb83 689static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 690{
691 if (CHIP_IS_E2(bp))
692 return PAGE_WRITE_REGS_E2;
693 else if (CHIP_IS_E3(bp))
694 return PAGE_WRITE_REGS_E3;
695 else
696 return 0;
697}
698
1191cb83 699static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 700{
701 if (CHIP_IS_E2(bp))
702 return page_read_regs_e2;
703 else if (CHIP_IS_E3(bp))
704 return page_read_regs_e3;
705 else
706 return NULL;
707}
708
1191cb83 709static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 710{
711 if (CHIP_IS_E2(bp))
712 return PAGE_READ_REGS_E2;
713 else if (CHIP_IS_E3(bp))
714 return PAGE_READ_REGS_E3;
715 else
716 return 0;
717}
718
07ba6af4
MS		 719static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
720 const struct reg_addr *reg_info)
0fea29c1 721{
07ba6af4
MS		 722 if (CHIP_IS_E1(bp))
723 return IS_E1_REG(reg_info->chips);
724 else if (CHIP_IS_E1H(bp))
725 return IS_E1H_REG(reg_info->chips);
726 else if (CHIP_IS_E2(bp))
727 return IS_E2_REG(reg_info->chips);
728 else if (CHIP_IS_E3A0(bp))
729 return IS_E3A0_REG(reg_info->chips);
730 else if (CHIP_IS_E3B0(bp))
731 return IS_E3B0_REG(reg_info->chips);
732 else
733 return false;
0fea29c1 734}
de0c62db 735
de0c62db 736
07ba6af4
MS		 737static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
738 const struct wreg_addr *wreg_info)
739{
740 if (CHIP_IS_E1(bp))
741 return IS_E1_REG(wreg_info->chips);
742 else if (CHIP_IS_E1H(bp))
743 return IS_E1H_REG(wreg_info->chips);
744 else if (CHIP_IS_E2(bp))
745 return IS_E2_REG(wreg_info->chips);
746 else if (CHIP_IS_E3A0(bp))
747 return IS_E3A0_REG(wreg_info->chips);
748 else if (CHIP_IS_E3B0(bp))
749 return IS_E3B0_REG(wreg_info->chips);
750 else
751 return false;
de0c62db
DK		 752}
753
0fea29c1
VZ		 754/**
755 * bnx2x_read_pages_regs - read "paged" registers
756 *
757 * @bp device handle
758 * @p output buffer
759 *
2de67439
YM		 760 * Reads "paged" memories: memories that may only be read by first writing to a
761 * specific address ("write address") and then reading from a specific address
762 * ("read address"). There may be more than one write address per "page" and
763 * more than one read address per write address.
0fea29c1 764 */
07ba6af4 765static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
f2e0899f
DK		 766{
767 u32 i, j, k, n;
07ba6af4 768
0fea29c1
VZ		 769 /* addresses of the paged registers */
770 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
771 /* number of paged registers */
772 int num_pages = __bnx2x_get_page_reg_num(bp);
773 /* write addresses */
774 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
775 /* number of write addresses */
776 int write_num = __bnx2x_get_page_write_num(bp);
777 /* read addresses info */
778 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
779 /* number of read addresses */
780 int read_num = __bnx2x_get_page_read_num(bp);
07ba6af4 781 u32 addr, size;
0fea29c1
VZ		 782
783 for (i = 0; i < num_pages; i++) {
784 for (j = 0; j < write_num; j++) {
785 REG_WR(bp, write_addr[j], page_addr[i]);
07ba6af4
MS		 786
787 for (k = 0; k < read_num; k++) {
788 if (IS_REG_IN_PRESET(read_addr[k].presets,
789 preset)) {
790 size = read_addr[k].size;
791 for (n = 0; n < size; n++) {
792 addr = read_addr[k].addr + n*4;
793 *p++ = REG_RD(bp, addr);
794 }
795 }
796 }
f2e0899f
DK		 797 }
798 }
799}
800
07ba6af4 801static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
0fea29c1 802{
07ba6af4
MS		 803 u32 i, j, addr;
804 const struct wreg_addr *wreg_addr_p = NULL;
805
806 if (CHIP_IS_E1(bp))
807 wreg_addr_p = &wreg_addr_e1;
808 else if (CHIP_IS_E1H(bp))
809 wreg_addr_p = &wreg_addr_e1h;
810 else if (CHIP_IS_E2(bp))
811 wreg_addr_p = &wreg_addr_e2;
812 else if (CHIP_IS_E3A0(bp))
813 wreg_addr_p = &wreg_addr_e3;
814 else if (CHIP_IS_E3B0(bp))
815 wreg_addr_p = &wreg_addr_e3b0;
816
817 /* Read the idle_chk registers */
818 for (i = 0; i < IDLE_REGS_COUNT; i++) {
819 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
820 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
821 for (j = 0; j < idle_reg_addrs[i].size; j++)
822 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
823 }
824 }
0fea29c1
VZ		 825
826 /* Read the regular registers */
07ba6af4
MS		 827 for (i = 0; i < REGS_COUNT; i++) {
828 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
829 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
0fea29c1
VZ		 830 for (j = 0; j < reg_addrs[i].size; j++)
831 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
07ba6af4
MS		 832 }
833 }
834
835 /* Read the CAM registers */
836 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
837 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
838 for (i = 0; i < wreg_addr_p->size; i++) {
839 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
840
841 /* In case of wreg_addr register, read additional
842 registers from read_regs array
843 */
844 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
845 addr = *(wreg_addr_p->read_regs);
846 *p++ = REG_RD(bp, addr + j*4);
847 }
848 }
849 }
850
851 /* Paged registers are supported in E2 & E3 only */
852 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
853 /* Read "paged" registes */
854 bnx2x_read_pages_regs(bp, p, preset);
855 }
856
857 return 0;
858}
859
860static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
861{
862 u32 preset_idx;
0fea29c1 863
07ba6af4
MS		 864 /* Read all registers, by reading all preset registers */
865 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
866 /* Skip presets with IOR */
867 if ((preset_idx == 2) ||
868 (preset_idx == 5) ||
869 (preset_idx == 8) ||
870 (preset_idx == 11))
871 continue;
872 __bnx2x_get_preset_regs(bp, p, preset_idx);
873 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
874 }
0fea29c1
VZ		 875}
876
de0c62db
DK		 877static void bnx2x_get_regs(struct net_device *dev,
878 struct ethtool_regs *regs, void *_p)
879{
0fea29c1 880 u32 *p = _p;
de0c62db 881 struct bnx2x *bp = netdev_priv(dev);
07ba6af4 882 struct dump_header dump_hdr = {0};
de0c62db 883
07ba6af4 884 regs->version = 2;
de0c62db
DK		 885 memset(p, 0, regs->len);
886
887 if (!netif_running(bp->dev))
888 return;
889
4a33bc03
VZ		 890 /* Disable parity attentions as long as following dump may
891 * cause false alarms by reading never written registers. We
892 * will re-enable parity attentions right after the dump.
893 */
07ba6af4
MS		 894
895 /* Disable parity on path 0 */
896 bnx2x_pretend_func(bp, 0);
4a33bc03
VZ		 897 bnx2x_disable_blocks_parity(bp);
898
07ba6af4
MS		 899 /* Disable parity on path 1 */
900 bnx2x_pretend_func(bp, 1);
901 bnx2x_disable_blocks_parity(bp);
f2e0899f 902
07ba6af4
MS		 903 /* Return to current function */
904 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
de0c62db 905
07ba6af4
MS		 906 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
907 dump_hdr.preset = DUMP_ALL_PRESETS;
908 dump_hdr.version = BNX2X_DUMP_VERSION;
909
910 /* dump_meta_data presents OR of CHIP and PATH. */
911 if (CHIP_IS_E1(bp)) {
912 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
913 } else if (CHIP_IS_E1H(bp)) {
914 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
915 } else if (CHIP_IS_E2(bp)) {
916 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
917 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
918 } else if (CHIP_IS_E3A0(bp)) {
919 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
920 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
921 } else if (CHIP_IS_E3B0(bp)) {
922 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
923 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
924 }
925
926 memcpy(p, &dump_hdr, sizeof(struct dump_header));
927 p += dump_hdr.header_size + 1;
de0c62db 928
0fea29c1
VZ		 929 /* Actually read the registers */
930 __bnx2x_get_regs(bp, p);
931
07ba6af4
MS		 932 /* Re-enable parity attentions on path 0 */
933 bnx2x_pretend_func(bp, 0);
934 bnx2x_clear_blocks_parity(bp);
935 bnx2x_enable_blocks_parity(bp);
936
937 /* Re-enable parity attentions on path 1 */
938 bnx2x_pretend_func(bp, 1);
4a33bc03 939 bnx2x_clear_blocks_parity(bp);
c9ee9206 940 bnx2x_enable_blocks_parity(bp);
07ba6af4
MS		 941
942 /* Return to current function */
943 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
944}
945
946static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
947{
948 struct bnx2x *bp = netdev_priv(dev);
949 int regdump_len = 0;
950
951 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
952 regdump_len *= 4;
953 regdump_len += sizeof(struct dump_header);
954
955 return regdump_len;
956}
957
958static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
959{
960 struct bnx2x *bp = netdev_priv(dev);
961
962 /* Use the ethtool_dump "flag" field as the dump preset index */
963 bp->dump_preset_idx = val->flag;
964 return 0;
965}
966
967static int bnx2x_get_dump_flag(struct net_device *dev,
968 struct ethtool_dump *dump)
969{
970 struct bnx2x *bp = netdev_priv(dev);
971
972 /* Calculate the requested preset idx length */
973 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
974 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
975 bp->dump_preset_idx, dump->len);
976
977 dump->flag = ETHTOOL_GET_DUMP_DATA;
978 return 0;
979}
980
981static int bnx2x_get_dump_data(struct net_device *dev,
982 struct ethtool_dump *dump,
983 void *buffer)
984{
985 u32 *p = buffer;
986 struct bnx2x *bp = netdev_priv(dev);
987 struct dump_header dump_hdr = {0};
988
989 memset(p, 0, dump->len);
990
991 /* Disable parity attentions as long as following dump may
992 * cause false alarms by reading never written registers. We
993 * will re-enable parity attentions right after the dump.
994 */
995
996 /* Disable parity on path 0 */
997 bnx2x_pretend_func(bp, 0);
998 bnx2x_disable_blocks_parity(bp);
999
1000 /* Disable parity on path 1 */
1001 bnx2x_pretend_func(bp, 1);
1002 bnx2x_disable_blocks_parity(bp);
1003
1004 /* Return to current function */
1005 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1006
1007 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1008 dump_hdr.preset = bp->dump_preset_idx;
1009 dump_hdr.version = BNX2X_DUMP_VERSION;
1010
1011 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1012
1013 /* dump_meta_data presents OR of CHIP and PATH. */
1014 if (CHIP_IS_E1(bp)) {
1015 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1016 } else if (CHIP_IS_E1H(bp)) {
1017 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1018 } else if (CHIP_IS_E2(bp)) {
1019 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1020 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1021 } else if (CHIP_IS_E3A0(bp)) {
1022 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1023 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1024 } else if (CHIP_IS_E3B0(bp)) {
1025 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1026 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1027 }
1028
1029 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1030 p += dump_hdr.header_size + 1;
1031
1032 /* Actually read the registers */
1033 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1034
1035 /* Re-enable parity attentions on path 0 */
1036 bnx2x_pretend_func(bp, 0);
1037 bnx2x_clear_blocks_parity(bp);
1038 bnx2x_enable_blocks_parity(bp);
1039
1040 /* Re-enable parity attentions on path 1 */
1041 bnx2x_pretend_func(bp, 1);
1042 bnx2x_clear_blocks_parity(bp);
1043 bnx2x_enable_blocks_parity(bp);
1044
1045 /* Return to current function */
1046 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1047
1048 return 0;
de0c62db
DK		 1049}
1050
de0c62db
DK		 1051static void bnx2x_get_drvinfo(struct net_device *dev,
1052 struct ethtool_drvinfo *info)
1053{
1054 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1055
68aad78c
RJ		 1056 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1057 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db 1058
8ca5e17e
AE		 1059 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1060
68aad78c 1061 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 1062 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 1063 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 1064 info->eedump_len = bp->common.flash_size;
1065 info->regdump_len = bnx2x_get_regs_len(dev);
1066}
1067
1068static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1069{
1070 struct bnx2x *bp = netdev_priv(dev);
1071
1072 if (bp->flags & NO_WOL_FLAG) {
1073 wol->supported = 0;
1074 wol->wolopts = 0;
1075 } else {
1076 wol->supported = WAKE_MAGIC;
1077 if (bp->wol)
1078 wol->wolopts = WAKE_MAGIC;
1079 else
1080 wol->wolopts = 0;
1081 }
1082 memset(&wol->sopass, 0, sizeof(wol->sopass));
1083}
1084
1085static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1086{
1087 struct bnx2x *bp = netdev_priv(dev);
1088
51c1a580 1089 if (wol->wolopts & ~WAKE_MAGIC) {
2de67439 1090 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1091 return -EINVAL;
51c1a580 1092 }
de0c62db
DK		 1093
1094 if (wol->wolopts & WAKE_MAGIC) {
51c1a580 1095 if (bp->flags & NO_WOL_FLAG) {
2de67439 1096 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1097 return -EINVAL;
51c1a580 1098 }
de0c62db
DK		 1099 bp->wol = 1;
1100 } else
1101 bp->wol = 0;
1102
1103 return 0;
1104}
1105
1106static u32 bnx2x_get_msglevel(struct net_device *dev)
1107{
1108 struct bnx2x *bp = netdev_priv(dev);
1109
1110 return bp->msg_enable;
1111}
1112
1113static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1114{
1115 struct bnx2x *bp = netdev_priv(dev);
1116
7a25cc73
DK		 1117 if (capable(CAP_NET_ADMIN)) {
1118 /* dump MCP trace */
ad5afc89 1119 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
7a25cc73 1120 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 1121 bp->msg_enable = level;
7a25cc73 1122 }
de0c62db
DK		 1123}
1124
1125static int bnx2x_nway_reset(struct net_device *dev)
1126{
1127 struct bnx2x *bp = netdev_priv(dev);
1128
1129 if (!bp->port.pmf)
1130 return 0;
1131
1132 if (netif_running(dev)) {
1133 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1134 bnx2x_force_link_reset(bp);
de0c62db
DK		 1135 bnx2x_link_set(bp);
1136 }
1137
1138 return 0;
1139}
1140
1141static u32 bnx2x_get_link(struct net_device *dev)
1142{
1143 struct bnx2x *bp = netdev_priv(dev);
1144
f2e0899f 1145 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 1146 return 0;
1147
1148 return bp->link_vars.link_up;
1149}
1150
1151static int bnx2x_get_eeprom_len(struct net_device *dev)
1152{
1153 struct bnx2x *bp = netdev_priv(dev);
1154
1155 return bp->common.flash_size;
1156}
1157
f16da43b
AE		 1158/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
1159 * we done things the other way around, if two pfs from the same port would
1160 * attempt to access nvram at the same time, we could run into a scenario such
1161 * as:
1162 * pf A takes the port lock.
1163 * pf B succeeds in taking the same lock since they are from the same port.
1164 * pf A takes the per pf misc lock. Performs eeprom access.
1165 * pf A finishes. Unlocks the per pf misc lock.
1166 * Pf B takes the lock and proceeds to perform it's own access.
1167 * pf A unlocks the per port lock, while pf B is still working (!).
1168 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
2de67439 1169 * access corrupted by pf B)
f16da43b 1170 */
de0c62db
DK		 1171static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1172{
1173 int port = BP_PORT(bp);
1174 int count, i;
f16da43b
AE		 1175 u32 val;
1176
1177 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1178 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1179
1180 /* adjust timeout for emulation/FPGA */
754a2f52 1181 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1182 if (CHIP_REV_IS_SLOW(bp))
1183 count *= 100;
1184
1185 /* request access to nvram interface */
1186 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1187 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1188
1189 for (i = 0; i < count*10; i++) {
1190 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1191 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1192 break;
1193
1194 udelay(5);
1195 }
1196
1197 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 1198 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1199 "cannot get access to nvram interface\n");
de0c62db
DK		 1200 return -EBUSY;
1201 }
1202
1203 return 0;
1204}
1205
1206static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1207{
1208 int port = BP_PORT(bp);
1209 int count, i;
f16da43b 1210 u32 val;
de0c62db
DK		 1211
1212 /* adjust timeout for emulation/FPGA */
754a2f52 1213 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1214 if (CHIP_REV_IS_SLOW(bp))
1215 count *= 100;
1216
1217 /* relinquish nvram interface */
1218 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1219 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1220
1221 for (i = 0; i < count*10; i++) {
1222 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1223 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1224 break;
1225
1226 udelay(5);
1227 }
1228
1229 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 1230 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1231 "cannot free access to nvram interface\n");
de0c62db
DK		 1232 return -EBUSY;
1233 }
1234
f16da43b
AE		 1235 /* release HW lock: protect against other PFs in PF Direct Assignment */
1236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1237 return 0;
1238}
1239
1240static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1241{
1242 u32 val;
1243
1244 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1245
1246 /* enable both bits, even on read */
1247 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1248 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1249 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1250}
1251
1252static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1253{
1254 u32 val;
1255
1256 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1257
1258 /* disable both bits, even after read */
1259 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1260 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1261 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1262}
1263
1264static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1265 u32 cmd_flags)
1266{
1267 int count, i, rc;
1268 u32 val;
1269
1270 /* build the command word */
1271 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1272
1273 /* need to clear DONE bit separately */
1274 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1275
1276 /* address of the NVRAM to read from */
1277 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1278 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1279
1280 /* issue a read command */
1281 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1282
1283 /* adjust timeout for emulation/FPGA */
754a2f52 1284 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1285 if (CHIP_REV_IS_SLOW(bp))
1286 count *= 100;
1287
1288 /* wait for completion */
1289 *ret_val = 0;
1290 rc = -EBUSY;
1291 for (i = 0; i < count; i++) {
1292 udelay(5);
1293 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1294
1295 if (val & MCPR_NVM_COMMAND_DONE) {
1296 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1297 /* we read nvram data in cpu order
1298 * but ethtool sees it as an array of bytes
07ba6af4
MS		 1299 * converting to big-endian will do the work
1300 */
de0c62db
DK		 1301 *ret_val = cpu_to_be32(val);
1302 rc = 0;
1303 break;
1304 }
1305 }
51c1a580
MS		 1306 if (rc == -EBUSY)
1307 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1308 "nvram read timeout expired\n");
de0c62db
DK		 1309 return rc;
1310}
1311
1312static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1313 int buf_size)
1314{
1315 int rc;
1316 u32 cmd_flags;
1317 __be32 val;
1318
1319 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1321 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1322 offset, buf_size);
1323 return -EINVAL;
1324 }
1325
1326 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1327 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1328 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1329 offset, buf_size, bp->common.flash_size);
1330 return -EINVAL;
1331 }
1332
1333 /* request access to nvram interface */
1334 rc = bnx2x_acquire_nvram_lock(bp);
1335 if (rc)
1336 return rc;
1337
1338 /* enable access to nvram interface */
1339 bnx2x_enable_nvram_access(bp);
1340
1341 /* read the first word(s) */
1342 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1343 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1344 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1345 memcpy(ret_buf, &val, 4);
1346
1347 /* advance to the next dword */
1348 offset += sizeof(u32);
1349 ret_buf += sizeof(u32);
1350 buf_size -= sizeof(u32);
1351 cmd_flags = 0;
1352 }
1353
1354 if (rc == 0) {
1355 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1356 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1357 memcpy(ret_buf, &val, 4);
1358 }
1359
1360 /* disable access to nvram interface */
1361 bnx2x_disable_nvram_access(bp);
1362 bnx2x_release_nvram_lock(bp);
1363
1364 return rc;
1365}
1366
1367static int bnx2x_get_eeprom(struct net_device *dev,
1368 struct ethtool_eeprom *eeprom, u8 *eebuf)
1369{
1370 struct bnx2x *bp = netdev_priv(dev);
1371 int rc;
1372
51c1a580
MS		 1373 if (!netif_running(dev)) {
1374 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1375 "cannot access eeprom when the interface is down\n");
de0c62db 1376 return -EAGAIN;
51c1a580 1377 }
de0c62db 1378
51c1a580 1379 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1380 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1381 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1382 eeprom->len, eeprom->len);
1383
1384 /* parameters already validated in ethtool_get_eeprom */
1385
1386 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1387
1388 return rc;
1389}
1390
24ea818e
YM		 1391static int bnx2x_get_module_eeprom(struct net_device *dev,
1392 struct ethtool_eeprom *ee,
1393 u8 *data)
1394{
1395 struct bnx2x *bp = netdev_priv(dev);
669d6996 1396 int rc = -EINVAL, phy_idx;
24ea818e 1397 u8 *user_data = data;
669d6996 1398 unsigned int start_addr = ee->offset, xfer_size = 0;
24ea818e
YM		 1399
1400 if (!netif_running(dev)) {
1401 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1402 "cannot access eeprom when the interface is down\n");
1403 return -EAGAIN;
1404 }
1405
1406 phy_idx = bnx2x_get_cur_phy_idx(bp);
669d6996
YR		 1407
1408 /* Read A0 section */
1409 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1410 /* Limit transfer size to the A0 section boundary */
1411 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1412 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1413 else
1414 xfer_size = ee->len;
1415 bnx2x_acquire_phy_lock(bp);
24ea818e
YM		 1416 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1417 &bp->link_params,
669d6996
YR		 1418 I2C_DEV_ADDR_A0,
1419 start_addr,
24ea818e
YM		 1420 xfer_size,
1421 user_data);
669d6996
YR		 1422 bnx2x_release_phy_lock(bp);
1423 if (rc) {
1424 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1425
1426 return -EINVAL;
1427 }
24ea818e 1428 user_data += xfer_size;
669d6996 1429 start_addr += xfer_size;
24ea818e
YM		 1430 }
1431
669d6996
YR		 1432 /* Read A2 section */
1433 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1434 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1435 xfer_size = ee->len - xfer_size;
1436 /* Limit transfer size to the A2 section boundary */
1437 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1438 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1439 start_addr -= ETH_MODULE_SFF_8079_LEN;
1440 bnx2x_acquire_phy_lock(bp);
1441 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1442 &bp->link_params,
1443 I2C_DEV_ADDR_A2,
1444 start_addr,
1445 xfer_size,
1446 user_data);
1447 bnx2x_release_phy_lock(bp);
1448 if (rc) {
1449 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1450 return -EINVAL;
1451 }
1452 }
24ea818e
YM		 1453 return rc;
1454}
1455
1456static int bnx2x_get_module_info(struct net_device *dev,
1457 struct ethtool_modinfo *modinfo)
1458{
1459 struct bnx2x *bp = netdev_priv(dev);
669d6996
YR		 1460 int phy_idx, rc;
1461 u8 sff8472_comp, diag_type;
1462
24ea818e 1463 if (!netif_running(dev)) {
669d6996 1464 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
24ea818e
YM		 1465 "cannot access eeprom when the interface is down\n");
1466 return -EAGAIN;
1467 }
24ea818e 1468 phy_idx = bnx2x_get_cur_phy_idx(bp);
669d6996
YR		 1469 bnx2x_acquire_phy_lock(bp);
1470 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1471 &bp->link_params,
1472 I2C_DEV_ADDR_A0,
1473 SFP_EEPROM_SFF_8472_COMP_ADDR,
1474 SFP_EEPROM_SFF_8472_COMP_SIZE,
1475 &sff8472_comp);
1476 bnx2x_release_phy_lock(bp);
1477 if (rc) {
1478 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1479 return -EINVAL;
1480 }
1481
1482 bnx2x_acquire_phy_lock(bp);
1483 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1484 &bp->link_params,
1485 I2C_DEV_ADDR_A0,
1486 SFP_EEPROM_DIAG_TYPE_ADDR,
1487 SFP_EEPROM_DIAG_TYPE_SIZE,
1488 &diag_type);
1489 bnx2x_release_phy_lock(bp);
1490 if (rc) {
1491 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1492 return -EINVAL;
1493 }
1494
1495 if (!sff8472_comp ||
1496 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
24ea818e
YM		 1497 modinfo->type = ETH_MODULE_SFF_8079;
1498 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
669d6996
YR		 1499 } else {
1500 modinfo->type = ETH_MODULE_SFF_8472;
1501 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
24ea818e 1502 }
669d6996 1503 return 0;
24ea818e
YM		 1504}
1505
de0c62db
DK		 1506static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1507 u32 cmd_flags)
1508{
1509 int count, i, rc;
1510
1511 /* build the command word */
1512 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1513
1514 /* need to clear DONE bit separately */
1515 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1516
1517 /* write the data */
1518 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1519
1520 /* address of the NVRAM to write to */
1521 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1522 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1523
1524 /* issue the write command */
1525 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1526
1527 /* adjust timeout for emulation/FPGA */
754a2f52 1528 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1529 if (CHIP_REV_IS_SLOW(bp))
1530 count *= 100;
1531
1532 /* wait for completion */
1533 rc = -EBUSY;
1534 for (i = 0; i < count; i++) {
1535 udelay(5);
1536 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1537 if (val & MCPR_NVM_COMMAND_DONE) {
1538 rc = 0;
1539 break;
1540 }
1541 }
1542
51c1a580
MS		 1543 if (rc == -EBUSY)
1544 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1545 "nvram write timeout expired\n");
de0c62db
DK		 1546 return rc;
1547}
1548
1549#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1550
1551static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1552 int buf_size)
1553{
1554 int rc;
1555 u32 cmd_flags;
1556 u32 align_offset;
1557 __be32 val;
1558
1559 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1560 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1561 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1562 offset, buf_size, bp->common.flash_size);
1563 return -EINVAL;
1564 }
1565
1566 /* request access to nvram interface */
1567 rc = bnx2x_acquire_nvram_lock(bp);
1568 if (rc)
1569 return rc;
1570
1571 /* enable access to nvram interface */
1572 bnx2x_enable_nvram_access(bp);
1573
1574 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1575 align_offset = (offset & ~0x03);
1576 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1577
1578 if (rc == 0) {
1579 val &= ~(0xff << BYTE_OFFSET(offset));
1580 val |= (*data_buf << BYTE_OFFSET(offset));
1581
1582 /* nvram data is returned as an array of bytes
07ba6af4
MS		 1583 * convert it back to cpu order
1584 */
de0c62db
DK		 1585 val = be32_to_cpu(val);
1586
1587 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1588 cmd_flags);
1589 }
1590
1591 /* disable access to nvram interface */
1592 bnx2x_disable_nvram_access(bp);
1593 bnx2x_release_nvram_lock(bp);
1594
1595 return rc;
1596}
1597
1598static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1599 int buf_size)
1600{
1601 int rc;
1602 u32 cmd_flags;
1603 u32 val;
1604 u32 written_so_far;
1605
1606 if (buf_size == 1) /* ethtool */
1607 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1608
1609 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1610 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1611 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1612 offset, buf_size);
1613 return -EINVAL;
1614 }
1615
1616 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1617 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1618 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1619 offset, buf_size, bp->common.flash_size);
1620 return -EINVAL;
1621 }
1622
1623 /* request access to nvram interface */
1624 rc = bnx2x_acquire_nvram_lock(bp);
1625 if (rc)
1626 return rc;
1627
1628 /* enable access to nvram interface */
1629 bnx2x_enable_nvram_access(bp);
1630
1631 written_so_far = 0;
1632 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1633 while ((written_so_far < buf_size) && (rc == 0)) {
1634 if (written_so_far == (buf_size - sizeof(u32)))
1635 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1636 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1637 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1638 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1639 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1640
1641 memcpy(&val, data_buf, 4);
1642
1643 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1644
1645 /* advance to the next dword */
1646 offset += sizeof(u32);
1647 data_buf += sizeof(u32);
1648 written_so_far += sizeof(u32);
1649 cmd_flags = 0;
1650 }
1651
1652 /* disable access to nvram interface */
1653 bnx2x_disable_nvram_access(bp);
1654 bnx2x_release_nvram_lock(bp);
1655
1656 return rc;
1657}
1658
1659static int bnx2x_set_eeprom(struct net_device *dev,
1660 struct ethtool_eeprom *eeprom, u8 *eebuf)
1661{
1662 struct bnx2x *bp = netdev_priv(dev);
1663 int port = BP_PORT(bp);
1664 int rc = 0;
e10bc84d 1665 u32 ext_phy_config;
51c1a580
MS		 1666 if (!netif_running(dev)) {
1667 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1668 "cannot access eeprom when the interface is down\n");
de0c62db 1669 return -EAGAIN;
51c1a580 1670 }
de0c62db 1671
51c1a580 1672 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1673 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1674 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1675 eeprom->len, eeprom->len);
1676
1677 /* parameters already validated in ethtool_set_eeprom */
1678
1679 /* PHY eeprom can be accessed only by the PMF */
1680 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1681 !bp->port.pmf) {
1682 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1683 "wrong magic or interface is not pmf\n");
de0c62db 1684 return -EINVAL;
51c1a580 1685 }
de0c62db 1686
e10bc84d
YR		 1687 ext_phy_config =
1688 SHMEM_RD(bp,
1689 dev_info.port_hw_config[port].external_phy_config);
1690
de0c62db
DK		 1691 if (eeprom->magic == 0x50485950) {
1692 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1693 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1694
1695 bnx2x_acquire_phy_lock(bp);
1696 rc |= bnx2x_link_reset(&bp->link_params,
1697 &bp->link_vars, 0);
e10bc84d 1698 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1699 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1700 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1701 MISC_REGISTERS_GPIO_HIGH, port);
1702 bnx2x_release_phy_lock(bp);
1703 bnx2x_link_report(bp);
1704
1705 } else if (eeprom->magic == 0x50485952) {
1706 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1707 if (bp->state == BNX2X_STATE_OPEN) {
1708 bnx2x_acquire_phy_lock(bp);
1709 rc |= bnx2x_link_reset(&bp->link_params,
1710 &bp->link_vars, 1);
1711
1712 rc |= bnx2x_phy_init(&bp->link_params,
1713 &bp->link_vars);
1714 bnx2x_release_phy_lock(bp);
1715 bnx2x_calc_fc_adv(bp);
1716 }
1717 } else if (eeprom->magic == 0x53985943) {
1718 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1719 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1720 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1721
1722 /* DSP Remove Download Mode */
1723 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1724 MISC_REGISTERS_GPIO_LOW, port);
1725
1726 bnx2x_acquire_phy_lock(bp);
1727
e10bc84d
YR		 1728 bnx2x_sfx7101_sp_sw_reset(bp,
1729 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1730
1731 /* wait 0.5 sec to allow it to run */
1732 msleep(500);
1733 bnx2x_ext_phy_hw_reset(bp, port);
1734 msleep(500);
1735 bnx2x_release_phy_lock(bp);
1736 }
1737 } else
1738 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1739
1740 return rc;
1741}
f85582f8 1742
de0c62db
DK		 1743static int bnx2x_get_coalesce(struct net_device *dev,
1744 struct ethtool_coalesce *coal)
1745{
1746 struct bnx2x *bp = netdev_priv(dev);
1747
1748 memset(coal, 0, sizeof(struct ethtool_coalesce));
1749
1750 coal->rx_coalesce_usecs = bp->rx_ticks;
1751 coal->tx_coalesce_usecs = bp->tx_ticks;
1752
1753 return 0;
1754}
1755
1756static int bnx2x_set_coalesce(struct net_device *dev,
1757 struct ethtool_coalesce *coal)
1758{
1759 struct bnx2x *bp = netdev_priv(dev);
1760
1761 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1762 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1763 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1764
1765 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1766 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1767 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1768
1769 if (netif_running(dev))
1770 bnx2x_update_coalesce(bp);
1771
1772 return 0;
1773}
1774
1775static void bnx2x_get_ringparam(struct net_device *dev,
1776 struct ethtool_ringparam *ering)
1777{
1778 struct bnx2x *bp = netdev_priv(dev);
1779
1780 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1781
25141580
DK		 1782 if (bp->rx_ring_size)
1783 ering->rx_pending = bp->rx_ring_size;
1784 else
c2188952 1785 ering->rx_pending = MAX_RX_AVAIL;
25141580 1786
a3348722 1787 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1788 ering->tx_pending = bp->tx_ring_size;
1789}
1790
1791static int bnx2x_set_ringparam(struct net_device *dev,
1792 struct ethtool_ringparam *ering)
1793{
1794 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1795
04c46736
YM		 1796 DP(BNX2X_MSG_ETHTOOL,
1797 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1798 ering->rx_pending, ering->tx_pending);
1799
de0c62db 1800 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1801 DP(BNX2X_MSG_ETHTOOL,
1802 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1803 return -EAGAIN;
1804 }
1805
1806 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1807 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1808 MIN_RX_SIZE_TPA)) ||
a3348722 1809 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1810 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1811 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1812 return -EINVAL;
51c1a580 1813 }
de0c62db
DK		 1814
1815 bp->rx_ring_size = ering->rx_pending;
1816 bp->tx_ring_size = ering->tx_pending;
1817
a9fccec7 1818 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1819}
1820
1821static void bnx2x_get_pauseparam(struct net_device *dev,
1822 struct ethtool_pauseparam *epause)
1823{
1824 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1825 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1826 int cfg_reg;
1827
a22f0788
YR		 1828 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1829 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1830
9e7e8399 1831 if (!epause->autoneg)
241fb5d2 1832 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1833 else
1834 cfg_reg = bp->link_params.req_fc_auto_adv;
1835
1836 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1837 BNX2X_FLOW_CTRL_RX);
9e7e8399 1838 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1839 BNX2X_FLOW_CTRL_TX);
1840
51c1a580 1841 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1842 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1843 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1844}
1845
1846static int bnx2x_set_pauseparam(struct net_device *dev,
1847 struct ethtool_pauseparam *epause)
1848{
1849 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1850 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1851 if (IS_MF(bp))
de0c62db
DK		 1852 return 0;
1853
51c1a580 1854 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1855 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1856 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1857
a22f0788 1858 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1859
1860 if (epause->rx_pause)
a22f0788 1861 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1862
1863 if (epause->tx_pause)
a22f0788 1864 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1865
a22f0788
YR		 1866 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1867 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1868
1869 if (epause->autoneg) {
a22f0788 1870 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1871 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1872 return -EINVAL;
1873 }
1874
a22f0788
YR		 1875 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1876 bp->link_params.req_flow_ctrl[cfg_idx] =
1877 BNX2X_FLOW_CTRL_AUTO;
1878 }
5cd75f0c
YR		 1879 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1880 if (epause->rx_pause)
1881 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1882
1883 if (epause->tx_pause)
1884 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
de0c62db
DK		 1885 }
1886
51c1a580 1887 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1888 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1889
1890 if (netif_running(dev)) {
1891 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1892 bnx2x_link_set(bp);
1893 }
1894
1895 return 0;
1896}
1897
5889335c 1898static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
cf2c1df6
MS		 1899 "register_test (offline) ",
1900 "memory_test (offline) ",
1901 "int_loopback_test (offline)",
1902 "ext_loopback_test (offline)",
1903 "nvram_test (online) ",
1904 "interrupt_test (online) ",
1905 "link_test (online) "
de0c62db
DK		 1906};
1907
e9939c80
YM		 1908static u32 bnx2x_eee_to_adv(u32 eee_adv)
1909{
1910 u32 modes = 0;
1911
1912 if (eee_adv & SHMEM_EEE_100M_ADV)
1913 modes |= ADVERTISED_100baseT_Full;
1914 if (eee_adv & SHMEM_EEE_1G_ADV)
1915 modes |= ADVERTISED_1000baseT_Full;
1916 if (eee_adv & SHMEM_EEE_10G_ADV)
1917 modes |= ADVERTISED_10000baseT_Full;
1918
1919 return modes;
1920}
1921
1922static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1923{
1924 u32 eee_adv = 0;
1925 if (modes & ADVERTISED_100baseT_Full)
1926 eee_adv |= SHMEM_EEE_100M_ADV;
1927 if (modes & ADVERTISED_1000baseT_Full)
1928 eee_adv |= SHMEM_EEE_1G_ADV;
1929 if (modes & ADVERTISED_10000baseT_Full)
1930 eee_adv |= SHMEM_EEE_10G_ADV;
1931
1932 return eee_adv << shift;
1933}
1934
1935static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1936{
1937 struct bnx2x *bp = netdev_priv(dev);
1938 u32 eee_cfg;
1939
1940 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1941 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1942 return -EOPNOTSUPP;
1943 }
1944
08e9acc2 1945 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1946
1947 edata->supported =
1948 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1949 SHMEM_EEE_SUPPORTED_SHIFT);
1950
1951 edata->advertised =
1952 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1953 SHMEM_EEE_ADV_STATUS_SHIFT);
1954 edata->lp_advertised =
1955 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1956 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1957
1958 /* SHMEM value is in 16u units --> Convert to 1u units. */
1959 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1960
1961 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1962 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1963 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1964
1965 return 0;
1966}
1967
1968static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1969{
1970 struct bnx2x *bp = netdev_priv(dev);
1971 u32 eee_cfg;
1972 u32 advertised;
1973
1974 if (IS_MF(bp))
1975 return 0;
1976
1977 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1978 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1979 return -EOPNOTSUPP;
1980 }
1981
08e9acc2 1982 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1983
1984 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1985 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1986 return -EOPNOTSUPP;
1987 }
1988
1989 advertised = bnx2x_adv_to_eee(edata->advertised,
1990 SHMEM_EEE_ADV_STATUS_SHIFT);
1991 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1992 DP(BNX2X_MSG_ETHTOOL,
efc7ce03 1993 "Direct manipulation of EEE advertisement is not supported\n");
e9939c80
YM		 1994 return -EINVAL;
1995 }
1996
1997 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1998 DP(BNX2X_MSG_ETHTOOL,
1999 "Maximal Tx Lpi timer supported is %x(u)\n",
2000 EEE_MODE_TIMER_MASK);
2001 return -EINVAL;
2002 }
2003 if (edata->tx_lpi_enabled &&
2004 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2005 DP(BNX2X_MSG_ETHTOOL,
2006 "Minimal Tx Lpi timer supported is %d(u)\n",
2007 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2008 return -EINVAL;
2009 }
2010
2011 /* All is well; Apply changes*/
2012 if (edata->eee_enabled)
2013 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2014 else
2015 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2016
2017 if (edata->tx_lpi_enabled)
2018 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2019 else
2020 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2021
2022 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2023 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2024 EEE_MODE_TIMER_MASK) |
2025 EEE_MODE_OVERRIDE_NVRAM |
2026 EEE_MODE_OUTPUT_TIME;
2027
2028 /* Restart link to propogate changes */
2029 if (netif_running(dev)) {
2030 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 2031 bnx2x_force_link_reset(bp);
e9939c80
YM		 2032 bnx2x_link_set(bp);
2033 }
2034
2035 return 0;
2036}
2037
619c5cb6
VZ		 2038enum {
2039 BNX2X_CHIP_E1_OFST = 0,
2040 BNX2X_CHIP_E1H_OFST,
2041 BNX2X_CHIP_E2_OFST,
2042 BNX2X_CHIP_E3_OFST,
2043 BNX2X_CHIP_E3B0_OFST,
2044 BNX2X_CHIP_MAX_OFST
2045};
2046
2047#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2048#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2049#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2050#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2051#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2052
2053#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2054#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2055
de0c62db
DK		 2056static int bnx2x_test_registers(struct bnx2x *bp)
2057{
2058 int idx, i, rc = -ENODEV;
619c5cb6 2059 u32 wr_val = 0, hw;
de0c62db
DK		 2060 int port = BP_PORT(bp);
2061 static const struct {
619c5cb6 2062 u32 hw;
de0c62db
DK		 2063 u32 offset0;
2064 u32 offset1;
2065 u32 mask;
2066 } reg_tbl[] = {
619c5cb6
VZ		 2067/* 0 */ { BNX2X_CHIP_MASK_ALL,
2068 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2069 { BNX2X_CHIP_MASK_ALL,
2070 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2071 { BNX2X_CHIP_MASK_E1X,
2072 HC_REG_AGG_INT_0, 4, 0x000003ff },
2073 { BNX2X_CHIP_MASK_ALL,
2074 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2075 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2076 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2077 { BNX2X_CHIP_MASK_E3B0,
2078 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2079 { BNX2X_CHIP_MASK_ALL,
2080 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2081 { BNX2X_CHIP_MASK_ALL,
2082 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2083 { BNX2X_CHIP_MASK_ALL,
2084 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2085 { BNX2X_CHIP_MASK_ALL,
2086 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2087/* 10 */ { BNX2X_CHIP_MASK_ALL,
2088 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2089 { BNX2X_CHIP_MASK_ALL,
2090 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2091 { BNX2X_CHIP_MASK_ALL,
2092 QM_REG_CONNNUM_0, 4, 0x000fffff },
2093 { BNX2X_CHIP_MASK_ALL,
2094 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2095 { BNX2X_CHIP_MASK_ALL,
2096 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2097 { BNX2X_CHIP_MASK_ALL,
2098 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2099 { BNX2X_CHIP_MASK_ALL,
2100 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2101 { BNX2X_CHIP_MASK_ALL,
2102 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2103 { BNX2X_CHIP_MASK_ALL,
2104 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2105 { BNX2X_CHIP_MASK_ALL,
2106 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2107/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2108 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2109 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2110 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2111 { BNX2X_CHIP_MASK_ALL,
2112 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2113 { BNX2X_CHIP_MASK_ALL,
2114 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2115 { BNX2X_CHIP_MASK_ALL,
2116 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2117 { BNX2X_CHIP_MASK_ALL,
2118 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2119 { BNX2X_CHIP_MASK_ALL,
2120 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2121 { BNX2X_CHIP_MASK_ALL,
2122 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2123 { BNX2X_CHIP_MASK_ALL,
2124 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2125 { BNX2X_CHIP_MASK_ALL,
2126 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2127/* 30 */ { BNX2X_CHIP_MASK_ALL,
2128 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2129 { BNX2X_CHIP_MASK_ALL,
2130 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2131 { BNX2X_CHIP_MASK_ALL,
2132 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2133 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2134 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2135 { BNX2X_CHIP_MASK_ALL,
2136 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2137 { BNX2X_CHIP_MASK_ALL,
2138 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2139 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2140 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2141 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2142 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2143
2144 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 2145 };
2146
51c1a580
MS		 2147 if (!netif_running(bp->dev)) {
2148 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2149 "cannot access eeprom when the interface is down\n");
de0c62db 2150 return rc;
51c1a580 2151 }
de0c62db 2152
619c5cb6
VZ		 2153 if (CHIP_IS_E1(bp))
2154 hw = BNX2X_CHIP_MASK_E1;
2155 else if (CHIP_IS_E1H(bp))
2156 hw = BNX2X_CHIP_MASK_E1H;
2157 else if (CHIP_IS_E2(bp))
2158 hw = BNX2X_CHIP_MASK_E2;
2159 else if (CHIP_IS_E3B0(bp))
2160 hw = BNX2X_CHIP_MASK_E3B0;
2161 else /* e3 A0 */
2162 hw = BNX2X_CHIP_MASK_E3;
2163
de0c62db 2164 /* Repeat the test twice:
07ba6af4
MS		 2165 * First by writing 0x00000000, second by writing 0xffffffff
2166 */
de0c62db
DK		 2167 for (idx = 0; idx < 2; idx++) {
2168
2169 switch (idx) {
2170 case 0:
2171 wr_val = 0;
2172 break;
2173 case 1:
2174 wr_val = 0xffffffff;
2175 break;
2176 }
2177
2178 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2179 u32 offset, mask, save_val, val;
619c5cb6 2180 if (!(hw & reg_tbl[i].hw))
f2e0899f 2181 continue;
de0c62db
DK		 2182
2183 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2184 mask = reg_tbl[i].mask;
2185
2186 save_val = REG_RD(bp, offset);
2187
ec6ba945 2188 REG_WR(bp, offset, wr_val & mask);
f85582f8 2189
de0c62db
DK		 2190 val = REG_RD(bp, offset);
2191
2192 /* Restore the original register's value */
2193 REG_WR(bp, offset, save_val);
2194
2195 /* verify value is as expected */
2196 if ((val & mask) != (wr_val & mask)) {
51c1a580 2197 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2198 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2199 offset, val, wr_val, mask);
2200 goto test_reg_exit;
2201 }
2202 }
2203 }
2204
2205 rc = 0;
2206
2207test_reg_exit:
2208 return rc;
2209}
2210
2211static int bnx2x_test_memory(struct bnx2x *bp)
2212{
2213 int i, j, rc = -ENODEV;
619c5cb6 2214 u32 val, index;
de0c62db
DK		 2215 static const struct {
2216 u32 offset;
2217 int size;
2218 } mem_tbl[] = {
2219 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2220 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2221 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2222 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2223 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2224 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2225 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2226
2227 { 0xffffffff, 0 }
2228 };
619c5cb6 2229
de0c62db
DK		 2230 static const struct {
2231 char *name;
2232 u32 offset;
619c5cb6 2233 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 2234 } prty_tbl[] = {
619c5cb6
VZ		 2235 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2236 {0x3ffc0, 0, 0, 0} },
2237 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2238 {0x2, 0x2, 0, 0} },
2239 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2240 {0, 0, 0, 0} },
2241 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2242 {0x3ffc0, 0, 0, 0} },
2243 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2244 {0x3ffc0, 0, 0, 0} },
2245 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2246 {0x3ffc1, 0, 0, 0} },
2247
2248 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 2249 };
2250
51c1a580
MS		 2251 if (!netif_running(bp->dev)) {
2252 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2253 "cannot access eeprom when the interface is down\n");
de0c62db 2254 return rc;
51c1a580 2255 }
de0c62db 2256
619c5cb6
VZ		 2257 if (CHIP_IS_E1(bp))
2258 index = BNX2X_CHIP_E1_OFST;
2259 else if (CHIP_IS_E1H(bp))
2260 index = BNX2X_CHIP_E1H_OFST;
2261 else if (CHIP_IS_E2(bp))
2262 index = BNX2X_CHIP_E2_OFST;
2263 else /* e3 */
2264 index = BNX2X_CHIP_E3_OFST;
2265
f2e0899f
DK		 2266 /* pre-Check the parity status */
2267 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2268 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2269 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2270 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 2271 "%s is 0x%x\n", prty_tbl[i].name, val);
2272 goto test_mem_exit;
2273 }
2274 }
2275
de0c62db
DK		 2276 /* Go through all the memories */
2277 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2278 for (j = 0; j < mem_tbl[i].size; j++)
2279 REG_RD(bp, mem_tbl[i].offset + j*4);
2280
2281 /* Check the parity status */
2282 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2283 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2284 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2285 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2286 "%s is 0x%x\n", prty_tbl[i].name, val);
2287 goto test_mem_exit;
2288 }
2289 }
2290
2291 rc = 0;
2292
2293test_mem_exit:
2294 return rc;
2295}
2296
a22f0788 2297static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 2298{
f2e0899f 2299 int cnt = 1400;
de0c62db 2300
619c5cb6 2301 if (link_up) {
a22f0788 2302 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 2303 msleep(20);
2304
2305 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 2306 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 2307
2308 cnt = 1400;
2309 while (!bp->link_vars.link_up && cnt--)
2310 msleep(20);
2311
2312 if (cnt <= 0 && !bp->link_vars.link_up)
2313 DP(BNX2X_MSG_ETHTOOL,
2314 "Timeout waiting for link init\n");
619c5cb6 2315 }
de0c62db
DK		 2316}
2317
619c5cb6 2318static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 2319{
2320 unsigned int pkt_size, num_pkts, i;
2321 struct sk_buff *skb;
2322 unsigned char *packet;
2323 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2324 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 2325 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 2326 u16 tx_start_idx, tx_idx;
2327 u16 rx_start_idx, rx_idx;
b0700b1e 2328 u16 pkt_prod, bd_prod;
de0c62db
DK		 2329 struct sw_tx_bd *tx_buf;
2330 struct eth_tx_start_bd *tx_start_bd;
de0c62db
DK		 2331 dma_addr_t mapping;
2332 union eth_rx_cqe *cqe;
619c5cb6 2333 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 2334 struct sw_rx_bd *rx_buf;
2335 u16 len;
2336 int rc = -ENODEV;
e52fcb24 2337 u8 *data;
8970b2e4
MS		 2338 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2339 txdata->txq_index);
de0c62db
DK		 2340
2341 /* check the loopback mode */
2342 switch (loopback_mode) {
2343 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 2344 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2345 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 2346 return -EINVAL;
8970b2e4 2347 }
de0c62db
DK		 2348 break;
2349 case BNX2X_MAC_LOOPBACK:
32911333
YR		 2350 if (CHIP_IS_E3(bp)) {
2351 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2352 if (bp->port.supported[cfg_idx] &
2353 (SUPPORTED_10000baseT_Full |
2354 SUPPORTED_20000baseMLD2_Full |
2355 SUPPORTED_20000baseKR2_Full))
2356 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2357 else
2358 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2359 } else
2360 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2361
de0c62db
DK		 2362 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2363 break;
8970b2e4
MS		 2364 case BNX2X_EXT_LOOPBACK:
2365 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2366 DP(BNX2X_MSG_ETHTOOL,
2367 "Can't configure external loopback\n");
2368 return -EINVAL;
2369 }
2370 break;
de0c62db 2371 default:
51c1a580 2372 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2373 return -EINVAL;
2374 }
2375
2376 /* prepare the loopback packet */
2377 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2378 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2379 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2380 if (!skb) {
51c1a580 2381 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2382 rc = -ENOMEM;
2383 goto test_loopback_exit;
2384 }
2385 packet = skb_put(skb, pkt_size);
2386 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2387 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2388 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2389 for (i = ETH_HLEN; i < pkt_size; i++)
2390 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2391 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2392 skb_headlen(skb), DMA_TO_DEVICE);
2393 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2394 rc = -ENOMEM;
2395 dev_kfree_skb(skb);
51c1a580 2396 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2397 goto test_loopback_exit;
2398 }
de0c62db
DK		 2399
2400 /* send the loopback packet */
2401 num_pkts = 0;
6383c0b3 2402 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2403 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2404
73dbb5e1
DK		 2405 netdev_tx_sent_queue(txq, skb->len);
2406
6383c0b3
AE		 2407 pkt_prod = txdata->tx_pkt_prod++;
2408 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2409 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2410 tx_buf->skb = skb;
2411 tx_buf->flags = 0;
2412
6383c0b3
AE		 2413 bd_prod = TX_BD(txdata->tx_bd_prod);
2414 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2415 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2416 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2417 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2418 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2419 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2420 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2421 SET_FLAG(tx_start_bd->general_data,
2422 ETH_TX_START_BD_HDR_NBDS,
2423 1);
96bed4b9
YM		 2424 SET_FLAG(tx_start_bd->general_data,
2425 ETH_TX_START_BD_PARSE_NBDS,
2426 0);
de0c62db
DK		 2427
2428 /* turn on parsing and get a BD */
2429 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2430
96bed4b9
YM		 2431 if (CHIP_IS_E1x(bp)) {
2432 u16 global_data = 0;
2433 struct eth_tx_parse_bd_e1x *pbd_e1x =
2434 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2435 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2436 SET_FLAG(global_data,
2437 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2438 pbd_e1x->global_data = cpu_to_le16(global_data);
2439 } else {
2440 u32 parsing_data = 0;
2441 struct eth_tx_parse_bd_e2 *pbd_e2 =
2442 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2443 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2444 SET_FLAG(parsing_data,
2445 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2446 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2447 }
de0c62db
DK		 2448 wmb();
2449
6383c0b3 2450 txdata->tx_db.data.prod += 2;
de0c62db 2451 barrier();
6383c0b3 2452 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2453
2454 mmiowb();
619c5cb6 2455 barrier();
de0c62db
DK		 2456
2457 num_pkts++;
6383c0b3 2458 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2459
2460 udelay(100);
2461
6383c0b3 2462 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2463 if (tx_idx != tx_start_idx + num_pkts)
2464 goto test_loopback_exit;
2465
f2e0899f
DK		 2466 /* Unlike HC IGU won't generate an interrupt for status block
2467 * updates that have been performed while interrupts were
2468 * disabled.
2469 */
e1210d12
ED		 2470 if (bp->common.int_block == INT_BLOCK_IGU) {
2471 /* Disable local BHes to prevent a dead-lock situation between
2472 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2473 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2474 */
2475 local_bh_disable();
6383c0b3 2476 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2477 local_bh_enable();
2478 }
f2e0899f 2479
de0c62db
DK		 2480 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2481 if (rx_idx != rx_start_idx + num_pkts)
2482 goto test_loopback_exit;
2483
b0700b1e 2484 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2485 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2486 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2487 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2488 goto test_loopback_rx_exit;
2489
621b4d66 2490 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2491 if (len != pkt_size)
2492 goto test_loopback_rx_exit;
2493
2494 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2495 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2496 dma_unmap_addr(rx_buf, mapping),
2497 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2498 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2499 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2500 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2501 goto test_loopback_rx_exit;
2502
2503 rc = 0;
2504
2505test_loopback_rx_exit:
2506
2507 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2508 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2509 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2510 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2511
2512 /* Update producers */
2513 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2514 fp_rx->rx_sge_prod);
2515
2516test_loopback_exit:
2517 bp->link_params.loopback_mode = LOOPBACK_NONE;
2518
2519 return rc;
2520}
2521
619c5cb6 2522static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2523{
2524 int rc = 0, res;
2525
2526 if (BP_NOMCP(bp))
2527 return rc;
2528
2529 if (!netif_running(bp->dev))
2530 return BNX2X_LOOPBACK_FAILED;
2531
2532 bnx2x_netif_stop(bp, 1);
2533 bnx2x_acquire_phy_lock(bp);
2534
619c5cb6 2535 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2536 if (res) {
51c1a580 2537 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2538 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2539 }
2540
619c5cb6 2541 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2542 if (res) {
51c1a580 2543 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2544 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2545 }
2546
2547 bnx2x_release_phy_lock(bp);
2548 bnx2x_netif_start(bp);
2549
2550 return rc;
2551}
2552
8970b2e4
MS		 2553static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2554{
2555 int rc;
2556 u8 is_serdes =
2557 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2558
2559 if (BP_NOMCP(bp))
2560 return -ENODEV;
2561
2562 if (!netif_running(bp->dev))
2563 return BNX2X_EXT_LOOPBACK_FAILED;
2564
5d07d868 2565 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
8970b2e4
MS		 2566 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2567 if (rc) {
2568 DP(BNX2X_MSG_ETHTOOL,
2569 "Can't perform self-test, nic_load (for external lb) failed\n");
2570 return -ENODEV;
2571 }
2572 bnx2x_wait_for_link(bp, 1, is_serdes);
2573
2574 bnx2x_netif_stop(bp, 1);
2575
2576 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2577 if (rc)
2578 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2579
2580 bnx2x_netif_start(bp);
2581
2582 return rc;
2583}
2584
de0c62db
DK		 2585#define CRC32_RESIDUAL 0xdebb20e3
2586
2587static int bnx2x_test_nvram(struct bnx2x *bp)
2588{
2589 static const struct {
2590 int offset;
2591 int size;
2592 } nvram_tbl[] = {
2593 { 0, 0x14 }, /* bootstrap */
2594 { 0x14, 0xec }, /* dir */
2595 { 0x100, 0x350 }, /* manuf_info */
2596 { 0x450, 0xf0 }, /* feature_info */
2597 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2598 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2599 { 0, 0 }
2600 };
afa13b4b
MY		 2601 __be32 *buf;
2602 u8 *data;
de0c62db
DK		 2603 int i, rc;
2604 u32 magic, crc;
2605
2606 if (BP_NOMCP(bp))
2607 return 0;
2608
afa13b4b
MY		 2609 buf = kmalloc(0x350, GFP_KERNEL);
2610 if (!buf) {
51c1a580 2611 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2612 rc = -ENOMEM;
2613 goto test_nvram_exit;
2614 }
2615 data = (u8 *)buf;
2616
de0c62db
DK		 2617 rc = bnx2x_nvram_read(bp, 0, data, 4);
2618 if (rc) {
51c1a580
MS		 2619 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2620 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2621 goto test_nvram_exit;
2622 }
2623
2624 magic = be32_to_cpu(buf[0]);
2625 if (magic != 0x669955aa) {
51c1a580
MS		 2626 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2627 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2628 rc = -ENODEV;
2629 goto test_nvram_exit;
2630 }
2631
2632 for (i = 0; nvram_tbl[i].size; i++) {
2633
2634 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2635 nvram_tbl[i].size);
2636 if (rc) {
51c1a580 2637 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2638 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2639 goto test_nvram_exit;
2640 }
2641
2642 crc = ether_crc_le(nvram_tbl[i].size, data);
2643 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2644 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2645 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2646 rc = -ENODEV;
2647 goto test_nvram_exit;
2648 }
2649 }
2650
2651test_nvram_exit:
afa13b4b 2652 kfree(buf);
de0c62db
DK		 2653 return rc;
2654}
2655
619c5cb6 2656/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2657static int bnx2x_test_intr(struct bnx2x *bp)
2658{
3b603066 2659 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2660
51c1a580
MS		 2661 if (!netif_running(bp->dev)) {
2662 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2663 "cannot access eeprom when the interface is down\n");
de0c62db 2664 return -ENODEV;
51c1a580 2665 }
de0c62db 2666
15192a8c 2667 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2668 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2669
619c5cb6
VZ		 2670 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2671
2672 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2673}
2674
2675static void bnx2x_self_test(struct net_device *dev,
2676 struct ethtool_test *etest, u64 *buf)
2677{
2678 struct bnx2x *bp = netdev_priv(dev);
a336ca7c
YR		 2679 u8 is_serdes, link_up;
2680 int rc, cnt = 0;
cf2c1df6 2681
de0c62db 2682 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2683 netdev_err(bp->dev,
2684 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2685 etest->flags |= ETH_TEST_FL_FAILED;
2686 return;
2687 }
2de67439 2688
8970b2e4
MS		 2689 DP(BNX2X_MSG_ETHTOOL,
2690 "Self-test command parameters: offline = %d, external_lb = %d\n",
2691 (etest->flags & ETH_TEST_FL_OFFLINE),
2692 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2693
cf2c1df6 2694 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2695
cf2c1df6
MS		 2696 if (!netif_running(dev)) {
2697 DP(BNX2X_MSG_ETHTOOL,
2698 "Can't perform self-test when interface is down\n");
de0c62db 2699 return;
cf2c1df6 2700 }
de0c62db 2701
a22f0788 2702 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
a336ca7c 2703 link_up = bp->link_vars.link_up;
cf2c1df6
MS		 2704 /* offline tests are not supported in MF mode */
2705 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2706 int port = BP_PORT(bp);
2707 u32 val;
de0c62db
DK		 2708
2709 /* save current value of input enable for TX port IF */
2710 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2711 /* disable input for TX port IF */
2712 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2713
5d07d868 2714 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
cf2c1df6
MS		 2715 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2716 if (rc) {
2717 etest->flags |= ETH_TEST_FL_FAILED;
2718 DP(BNX2X_MSG_ETHTOOL,
2719 "Can't perform self-test, nic_load (for offline) failed\n");
2720 return;
2721 }
2722
de0c62db 2723 /* wait until link state is restored */
619c5cb6 2724 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2725
2726 if (bnx2x_test_registers(bp) != 0) {
2727 buf[0] = 1;
2728 etest->flags |= ETH_TEST_FL_FAILED;
2729 }
2730 if (bnx2x_test_memory(bp) != 0) {
2731 buf[1] = 1;
2732 etest->flags |= ETH_TEST_FL_FAILED;
2733 }
f85582f8 2734
8970b2e4 2735 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2736 if (buf[2] != 0)
2737 etest->flags |= ETH_TEST_FL_FAILED;
2738
8970b2e4
MS		 2739 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2740 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2741 if (buf[3] != 0)
2742 etest->flags |= ETH_TEST_FL_FAILED;
2743 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2744 }
2745
5d07d868 2746 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
de0c62db
DK		 2747
2748 /* restore input for TX port IF */
2749 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2750 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2751 if (rc) {
2752 etest->flags |= ETH_TEST_FL_FAILED;
2753 DP(BNX2X_MSG_ETHTOOL,
2754 "Can't perform self-test, nic_load (for online) failed\n");
2755 return;
2756 }
de0c62db 2757 /* wait until link state is restored */
a22f0788 2758 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2759 }
2760 if (bnx2x_test_nvram(bp) != 0) {
cf2c1df6
MS		 2761 if (!IS_MF(bp))
2762 buf[4] = 1;
2763 else
2764 buf[0] = 1;
de0c62db
DK		 2765 etest->flags |= ETH_TEST_FL_FAILED;
2766 }
2767 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 2768 if (!IS_MF(bp))
2769 buf[5] = 1;
2770 else
2771 buf[1] = 1;
de0c62db
DK		 2772 etest->flags |= ETH_TEST_FL_FAILED;
2773 }
633ac363 2774
a336ca7c
YR		 2775 if (link_up) {
2776 cnt = 100;
2777 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2778 msleep(20);
2779 }
2780
2781 if (!cnt) {
cf2c1df6
MS		 2782 if (!IS_MF(bp))
2783 buf[6] = 1;
2784 else
2785 buf[2] = 1;
633ac363
DK		 2786 etest->flags |= ETH_TEST_FL_FAILED;
2787 }
de0c62db
DK		 2788}
2789
de0c62db
DK		 2790#define IS_PORT_STAT(i) \
2791 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2792#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2793#define IS_MF_MODE_STAT(bp) \
2794 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2795
619c5cb6
VZ		 2796/* ethtool statistics are displayed for all regular ethernet queues and the
2797 * fcoe L2 queue if not disabled
2798 */
1191cb83 2799static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2800{
2801 return BNX2X_NUM_ETH_QUEUES(bp);
2802}
2803
de0c62db
DK		 2804static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2805{
2806 struct bnx2x *bp = netdev_priv(dev);
2807 int i, num_stats;
2808
2809 switch (stringset) {
2810 case ETH_SS_STATS:
2811 if (is_multi(bp)) {
619c5cb6 2812 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2813 BNX2X_NUM_Q_STATS;
2814 } else
2815 num_stats = 0;
2816 if (IS_MF_MODE_STAT(bp)) {
2817 for (i = 0; i < BNX2X_NUM_STATS; i++)
2818 if (IS_FUNC_STAT(i))
2819 num_stats++;
2820 } else
2821 num_stats += BNX2X_NUM_STATS;
2822
de0c62db
DK		 2823 return num_stats;
2824
2825 case ETH_SS_TEST:
cf2c1df6 2826 return BNX2X_NUM_TESTS(bp);
de0c62db
DK		 2827
2828 default:
2829 return -EINVAL;
2830 }
2831}
2832
2833static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2834{
2835 struct bnx2x *bp = netdev_priv(dev);
5889335c 2836 int i, j, k, start;
ec6ba945 2837 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2838
2839 switch (stringset) {
2840 case ETH_SS_STATS:
d5e83632 2841 k = 0;
de0c62db 2842 if (is_multi(bp)) {
619c5cb6 2843 for_each_eth_queue(bp, i) {
ec6ba945 2844 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2845 sprintf(queue_name, "%d", i);
de0c62db 2846 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2847 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2848 ETH_GSTRING_LEN,
2849 bnx2x_q_stats_arr[j].string,
2850 queue_name);
de0c62db
DK		 2851 k += BNX2X_NUM_Q_STATS;
2852 }
de0c62db 2853 }
d5e83632
YM		 2854
2855
2856 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2857 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2858 continue;
2859 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2860 bnx2x_stats_arr[i].string);
2861 j++;
2862 }
2863
de0c62db
DK		 2864 break;
2865
2866 case ETH_SS_TEST:
cf2c1df6
MS		 2867 /* First 4 tests cannot be done in MF mode */
2868 if (!IS_MF(bp))
2869 start = 0;
2870 else
2871 start = 4;
5889335c
MS		 2872 memcpy(buf, bnx2x_tests_str_arr + start,
2873 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
de0c62db
DK		 2874 }
2875}
2876
2877static void bnx2x_get_ethtool_stats(struct net_device *dev,
2878 struct ethtool_stats *stats, u64 *buf)
2879{
2880 struct bnx2x *bp = netdev_priv(dev);
2881 u32 *hw_stats, *offset;
d5e83632 2882 int i, j, k = 0;
de0c62db
DK		 2883
2884 if (is_multi(bp)) {
619c5cb6 2885 for_each_eth_queue(bp, i) {
15192a8c 2886 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 2887 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2888 if (bnx2x_q_stats_arr[j].size == 0) {
2889 /* skip this counter */
2890 buf[k + j] = 0;
2891 continue;
2892 }
2893 offset = (hw_stats +
2894 bnx2x_q_stats_arr[j].offset);
2895 if (bnx2x_q_stats_arr[j].size == 4) {
2896 /* 4-byte counter */
2897 buf[k + j] = (u64) *offset;
2898 continue;
2899 }
2900 /* 8-byte counter */
2901 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2902 }
2903 k += BNX2X_NUM_Q_STATS;
2904 }
d5e83632
YM		 2905 }
2906
2907 hw_stats = (u32 *)&bp->eth_stats;
2908 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2909 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2910 continue;
2911 if (bnx2x_stats_arr[i].size == 0) {
2912 /* skip this counter */
2913 buf[k + j] = 0;
2914 j++;
2915 continue;
de0c62db 2916 }
d5e83632
YM		 2917 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2918 if (bnx2x_stats_arr[i].size == 4) {
2919 /* 4-byte counter */
2920 buf[k + j] = (u64) *offset;
de0c62db 2921 j++;
d5e83632 2922 continue;
de0c62db 2923 }
d5e83632
YM		 2924 /* 8-byte counter */
2925 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2926 j++;
de0c62db
DK		 2927 }
2928}
2929
32d36134 2930static int bnx2x_set_phys_id(struct net_device *dev,
2931 enum ethtool_phys_id_state state)
de0c62db
DK		 2932{
2933 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2934
51c1a580
MS		 2935 if (!netif_running(dev)) {
2936 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2937 "cannot access eeprom when the interface is down\n");
32d36134 2938 return -EAGAIN;
51c1a580 2939 }
de0c62db 2940
51c1a580
MS		 2941 if (!bp->port.pmf) {
2942 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2943 return -EOPNOTSUPP;
51c1a580 2944 }
de0c62db 2945
32d36134 2946 switch (state) {
2947 case ETHTOOL_ID_ACTIVE:
fce55922 2948 return 1; /* cycle on/off once per second */
de0c62db 2949
32d36134 2950 case ETHTOOL_ID_ON:
8203c4b6 2951 bnx2x_acquire_phy_lock(bp);
32d36134 2952 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2953 LED_MODE_ON, SPEED_1000);
8203c4b6 2954 bnx2x_release_phy_lock(bp);
32d36134 2955 break;
de0c62db 2956
32d36134 2957 case ETHTOOL_ID_OFF:
8203c4b6 2958 bnx2x_acquire_phy_lock(bp);
32d36134 2959 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2960 LED_MODE_FRONT_PANEL_OFF, 0);
8203c4b6 2961 bnx2x_release_phy_lock(bp);
32d36134 2962 break;
2963
2964 case ETHTOOL_ID_INACTIVE:
8203c4b6 2965 bnx2x_acquire_phy_lock(bp);
e1943424
DM		 2966 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2967 LED_MODE_OPER,
2968 bp->link_vars.line_speed);
8203c4b6 2969 bnx2x_release_phy_lock(bp);
32d36134 2970 }
de0c62db
DK		 2971
2972 return 0;
2973}
2974
5d317c6a
MS		 2975static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2976{
2977
2978 switch (info->flow_type) {
2979 case TCP_V4_FLOW:
2980 case TCP_V6_FLOW:
2981 info->data = RXH_IP_SRC | RXH_IP_DST |
2982 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2983 break;
2984 case UDP_V4_FLOW:
2985 if (bp->rss_conf_obj.udp_rss_v4)
2986 info->data = RXH_IP_SRC | RXH_IP_DST |
2987 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2988 else
2989 info->data = RXH_IP_SRC | RXH_IP_DST;
2990 break;
2991 case UDP_V6_FLOW:
2992 if (bp->rss_conf_obj.udp_rss_v6)
2993 info->data = RXH_IP_SRC | RXH_IP_DST |
2994 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2995 else
2996 info->data = RXH_IP_SRC | RXH_IP_DST;
2997 break;
2998 case IPV4_FLOW:
2999 case IPV6_FLOW:
3000 info->data = RXH_IP_SRC | RXH_IP_DST;
3001 break;
3002 default:
3003 info->data = 0;
3004 break;
3005 }
3006
3007 return 0;
3008}
3009
ab532cf3 3010static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 3011 u32 *rules __always_unused)
ab532cf3
TH		 3012{
3013 struct bnx2x *bp = netdev_priv(dev);
3014
3015 switch (info->cmd) {
3016 case ETHTOOL_GRXRINGS:
3017 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3018 return 0;
5d317c6a
MS		 3019 case ETHTOOL_GRXFH:
3020 return bnx2x_get_rss_flags(bp, info);
3021 default:
3022 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3023 return -EOPNOTSUPP;
3024 }
3025}
3026
3027static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3028{
3029 int udp_rss_requested;
3030
3031 DP(BNX2X_MSG_ETHTOOL,
3032 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3033 info->flow_type, info->data);
3034
3035 switch (info->flow_type) {
3036 case TCP_V4_FLOW:
3037 case TCP_V6_FLOW:
3038 /* For TCP only 4-tupple hash is supported */
3039 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3040 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3041 DP(BNX2X_MSG_ETHTOOL,
3042 "Command parameters not supported\n");
3043 return -EINVAL;
5d317c6a 3044 }
2de67439 3045 return 0;
5d317c6a
MS		 3046
3047 case UDP_V4_FLOW:
3048 case UDP_V6_FLOW:
3049 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3050 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2de67439 3051 RXH_L4_B_0_1 | RXH_L4_B_2_3))
5d317c6a
MS		 3052 udp_rss_requested = 1;
3053 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3054 udp_rss_requested = 0;
3055 else
3056 return -EINVAL;
3057 if ((info->flow_type == UDP_V4_FLOW) &&
3058 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3059 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3060 DP(BNX2X_MSG_ETHTOOL,
3061 "rss re-configured, UDP 4-tupple %s\n",
3062 udp_rss_requested ? "enabled" : "disabled");
3063 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3064 } else if ((info->flow_type == UDP_V6_FLOW) &&
3065 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3066 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
5d317c6a
MS		 3067 DP(BNX2X_MSG_ETHTOOL,
3068 "rss re-configured, UDP 4-tupple %s\n",
3069 udp_rss_requested ? "enabled" : "disabled");
337da3e3 3070 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
5d317c6a 3071 }
924d75ab
YM		 3072 return 0;
3073
5d317c6a
MS		 3074 case IPV4_FLOW:
3075 case IPV6_FLOW:
3076 /* For IP only 2-tupple hash is supported */
3077 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3078 DP(BNX2X_MSG_ETHTOOL,
3079 "Command parameters not supported\n");
3080 return -EINVAL;
5d317c6a 3081 }
924d75ab
YM		 3082 return 0;
3083
5d317c6a
MS		 3084 case SCTP_V4_FLOW:
3085 case AH_ESP_V4_FLOW:
3086 case AH_V4_FLOW:
3087 case ESP_V4_FLOW:
3088 case SCTP_V6_FLOW:
3089 case AH_ESP_V6_FLOW:
3090 case AH_V6_FLOW:
3091 case ESP_V6_FLOW:
3092 case IP_USER_FLOW:
3093 case ETHER_FLOW:
3094 /* RSS is not supported for these protocols */
3095 if (info->data) {
3096 DP(BNX2X_MSG_ETHTOOL,
3097 "Command parameters not supported\n");
3098 return -EINVAL;
5d317c6a 3099 }
924d75ab
YM		 3100 return 0;
3101
5d317c6a
MS		 3102 default:
3103 return -EINVAL;
3104 }
3105}
3106
3107static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3108{
3109 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 3110
5d317c6a
MS		 3111 switch (info->cmd) {
3112 case ETHTOOL_SRXFH:
3113 return bnx2x_set_rss_flags(bp, info);
ab532cf3 3114 default:
51c1a580 3115 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 3116 return -EOPNOTSUPP;
3117 }
3118}
3119
7850f63f
BH		 3120static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3121{
96305234 3122 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 3123}
3124
3125static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 3126{
3127 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 3128 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3129 size_t i;
ab532cf3 3130
619c5cb6
VZ		 3131 /* Get the current configuration of the RSS indirection table */
3132 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3133
3134 /*
3135 * We can't use a memcpy() as an internal storage of an
3136 * indirection table is a u8 array while indir->ring_index
3137 * points to an array of u32.
3138 *
3139 * Indirection table contains the FW Client IDs, so we need to
3140 * align the returned table to the Client ID of the leading RSS
3141 * queue.
3142 */
7850f63f
BH		 3143 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3144 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 3145
ab532cf3
TH		 3146 return 0;
3147}
3148
7850f63f 3149static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 3150{
3151 struct bnx2x *bp = netdev_priv(dev);
3152 size_t i;
619c5cb6
VZ		 3153
3154 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 3155 /*
3156 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3157 * as an internal storage of an indirection table is a u8 array
3158 * while indir->ring_index points to an array of u32.
3159 *
3160 * Indirection table contains the FW Client IDs, so we need to
3161 * align the received table to the Client ID of the leading RSS
3162 * queue
3163 */
5d317c6a 3164 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 3165 }
ab532cf3 3166
5d317c6a 3167 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 3168}
3169
0e8d2ec5
MS		 3170/**
3171 * bnx2x_get_channels - gets the number of RSS queues.
3172 *
3173 * @dev: net device
3174 * @channels: returns the number of max / current queues
3175 */
3176static void bnx2x_get_channels(struct net_device *dev,
3177 struct ethtool_channels *channels)
3178{
3179 struct bnx2x *bp = netdev_priv(dev);
3180
3181 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3182 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3183}
3184
3185/**
3186 * bnx2x_change_num_queues - change the number of RSS queues.
3187 *
3188 * @bp: bnx2x private structure
3189 *
3190 * Re-configure interrupt mode to get the new number of MSI-X
3191 * vectors and re-add NAPI objects.
3192 */
3193static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3194{
0e8d2ec5 3195 bnx2x_disable_msi(bp);
55c11941
MS		 3196 bp->num_ethernet_queues = num_rss;
3197 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3198 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
0e8d2ec5 3199 bnx2x_set_int_mode(bp);
0e8d2ec5
MS		 3200}
3201
3202/**
3203 * bnx2x_set_channels - sets the number of RSS queues.
3204 *
3205 * @dev: net device
3206 * @channels: includes the number of queues requested
3207 */
3208static int bnx2x_set_channels(struct net_device *dev,
3209 struct ethtool_channels *channels)
3210{
3211 struct bnx2x *bp = netdev_priv(dev);
3212
3213
3214 DP(BNX2X_MSG_ETHTOOL,
3215 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3216 channels->rx_count, channels->tx_count, channels->other_count,
3217 channels->combined_count);
3218
3219 /* We don't support separate rx / tx channels.
3220 * We don't allow setting 'other' channels.
3221 */
3222 if (channels->rx_count || channels->tx_count || channels->other_count
3223 || (channels->combined_count == 0) ||
3224 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3225 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3226 return -EINVAL;
3227 }
3228
3229 /* Check if there was a change in the active parameters */
3230 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3231 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3232 return 0;
3233 }
3234
3235 /* Set the requested number of queues in bp context.
3236 * Note that the actual number of queues created during load may be
3237 * less than requested if memory is low.
3238 */
3239 if (unlikely(!netif_running(dev))) {
3240 bnx2x_change_num_queues(bp, channels->combined_count);
3241 return 0;
3242 }
5d07d868 3243 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
0e8d2ec5
MS		 3244 bnx2x_change_num_queues(bp, channels->combined_count);
3245 return bnx2x_nic_load(bp, LOAD_NORMAL);
3246}
3247
de0c62db
DK		 3248static const struct ethtool_ops bnx2x_ethtool_ops = {
3249 .get_settings = bnx2x_get_settings,
3250 .set_settings = bnx2x_set_settings,
3251 .get_drvinfo = bnx2x_get_drvinfo,
3252 .get_regs_len = bnx2x_get_regs_len,
3253 .get_regs = bnx2x_get_regs,
07ba6af4
MS		 3254 .get_dump_flag = bnx2x_get_dump_flag,
3255 .get_dump_data = bnx2x_get_dump_data,
3256 .set_dump = bnx2x_set_dump,
de0c62db
DK		 3257 .get_wol = bnx2x_get_wol,
3258 .set_wol = bnx2x_set_wol,
3259 .get_msglevel = bnx2x_get_msglevel,
3260 .set_msglevel = bnx2x_set_msglevel,
3261 .nway_reset = bnx2x_nway_reset,
3262 .get_link = bnx2x_get_link,
3263 .get_eeprom_len = bnx2x_get_eeprom_len,
3264 .get_eeprom = bnx2x_get_eeprom,
3265 .set_eeprom = bnx2x_set_eeprom,
3266 .get_coalesce = bnx2x_get_coalesce,
3267 .set_coalesce = bnx2x_set_coalesce,
3268 .get_ringparam = bnx2x_get_ringparam,
3269 .set_ringparam = bnx2x_set_ringparam,
3270 .get_pauseparam = bnx2x_get_pauseparam,
3271 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 3272 .self_test = bnx2x_self_test,
3273 .get_sset_count = bnx2x_get_sset_count,
3274 .get_strings = bnx2x_get_strings,
32d36134 3275 .set_phys_id = bnx2x_set_phys_id,
de0c62db 3276 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 3277 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 3278 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 3279 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 3280 .get_rxfh_indir = bnx2x_get_rxfh_indir,
3281 .set_rxfh_indir = bnx2x_set_rxfh_indir,
0e8d2ec5
MS		 3282 .get_channels = bnx2x_get_channels,
3283 .set_channels = bnx2x_set_channels,
24ea818e
YM		 3284 .get_module_info = bnx2x_get_module_info,
3285 .get_module_eeprom = bnx2x_get_module_eeprom,
e9939c80
YM		 3286 .get_eee = bnx2x_get_eee,
3287 .set_eee = bnx2x_set_eee,
be53ce1e 3288 .get_ts_info = ethtool_op_get_ts_info,
de0c62db
DK		 3289};
3290
005a07ba
AE		 3291static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3292 .get_settings = bnx2x_get_settings,
3293 .set_settings = bnx2x_set_settings,
3294 .get_drvinfo = bnx2x_get_drvinfo,
3295 .get_msglevel = bnx2x_get_msglevel,
3296 .set_msglevel = bnx2x_set_msglevel,
3297 .get_link = bnx2x_get_link,
3298 .get_coalesce = bnx2x_get_coalesce,
3299 .get_ringparam = bnx2x_get_ringparam,
3300 .set_ringparam = bnx2x_set_ringparam,
3301 .get_sset_count = bnx2x_get_sset_count,
3302 .get_strings = bnx2x_get_strings,
3303 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3304 .get_rxnfc = bnx2x_get_rxnfc,
3305 .set_rxnfc = bnx2x_set_rxnfc,
3306 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3307 .get_rxfh_indir = bnx2x_get_rxfh_indir,
3308 .set_rxfh_indir = bnx2x_set_rxfh_indir,
3309 .get_channels = bnx2x_get_channels,
3310 .set_channels = bnx2x_set_channels,
3311};
3312
3313void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
de0c62db 3314{
005a07ba
AE		 3315 if (IS_PF(bp))
3316 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3317 else /* vf */
3318 SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops);
de0c62db 3319}
kernel source for telekom puls (alcatel/mediatek)