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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x / bnx2x_ethtool.c
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de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/crc32.h>
22
23
24#include "bnx2x.h"
25#include "bnx2x_cmn.h"
26#include "bnx2x_dump.h"
4a33bc03 27#include "bnx2x_init.h"
de0c62db 28
ec6ba945
VZ		 29/* Note: in the format strings below %s is replaced by the queue-name which is
30 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
31 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
32 */
33#define MAX_QUEUE_NAME_LEN 4
34static const struct {
35 long offset;
36 int size;
37 char string[ETH_GSTRING_LEN];
38} bnx2x_q_stats_arr[] = {
39/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
40 { Q_STATS_OFFSET32(error_bytes_received_hi),
41 8, "[%s]: rx_error_bytes" },
42 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
43 8, "[%s]: rx_ucast_packets" },
44 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
45 8, "[%s]: rx_mcast_packets" },
46 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
47 8, "[%s]: rx_bcast_packets" },
48 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
49 { Q_STATS_OFFSET32(rx_err_discard_pkt),
50 4, "[%s]: rx_phy_ip_err_discards"},
51 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
52 4, "[%s]: rx_skb_alloc_discard" },
53 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
54
55/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
56 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
57 8, "[%s]: tx_ucast_packets" },
58 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
59 8, "[%s]: tx_mcast_packets" },
60 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
61 8, "[%s]: tx_bcast_packets" }
62};
63
64#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
65
66static const struct {
67 long offset;
68 int size;
69 u32 flags;
70#define STATS_FLAGS_PORT 1
71#define STATS_FLAGS_FUNC 2
72#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
73 char string[ETH_GSTRING_LEN];
74} bnx2x_stats_arr[] = {
75/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
76 8, STATS_FLAGS_BOTH, "rx_bytes" },
77 { STATS_OFFSET32(error_bytes_received_hi),
78 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
79 { STATS_OFFSET32(total_unicast_packets_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
81 { STATS_OFFSET32(total_multicast_packets_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
83 { STATS_OFFSET32(total_broadcast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
85 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
86 8, STATS_FLAGS_PORT, "rx_crc_errors" },
87 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
88 8, STATS_FLAGS_PORT, "rx_align_errors" },
89 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
90 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
91 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
92 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
93/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
94 8, STATS_FLAGS_PORT, "rx_fragments" },
95 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
96 8, STATS_FLAGS_PORT, "rx_jabbers" },
97 { STATS_OFFSET32(no_buff_discard_hi),
98 8, STATS_FLAGS_BOTH, "rx_discards" },
99 { STATS_OFFSET32(mac_filter_discard),
100 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
101 { STATS_OFFSET32(xxoverflow_discard),
102 4, STATS_FLAGS_PORT, "rx_fw_discards" },
103 { STATS_OFFSET32(brb_drop_hi),
104 8, STATS_FLAGS_PORT, "rx_brb_discard" },
105 { STATS_OFFSET32(brb_truncate_hi),
106 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
107 { STATS_OFFSET32(pause_frames_received_hi),
108 8, STATS_FLAGS_PORT, "rx_pause_frames" },
109 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
110 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
111 { STATS_OFFSET32(nig_timer_max),
112 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
113/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
114 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
115 { STATS_OFFSET32(rx_skb_alloc_failed),
116 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
117 { STATS_OFFSET32(hw_csum_err),
118 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
119
120 { STATS_OFFSET32(total_bytes_transmitted_hi),
121 8, STATS_FLAGS_BOTH, "tx_bytes" },
122 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
123 8, STATS_FLAGS_PORT, "tx_error_bytes" },
124 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
126 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
127 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
128 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
130 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
131 8, STATS_FLAGS_PORT, "tx_mac_errors" },
132 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
133 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
134/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
135 8, STATS_FLAGS_PORT, "tx_single_collisions" },
136 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
137 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
138 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
139 8, STATS_FLAGS_PORT, "tx_deferred" },
140 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
141 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
143 8, STATS_FLAGS_PORT, "tx_late_collisions" },
144 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_total_collisions" },
146 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
147 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
148 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
149 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
151 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
153 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
154/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
155 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
156 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
157 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
158 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
159 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
160 { STATS_OFFSET32(pause_frames_sent_hi),
161 8, STATS_FLAGS_PORT, "tx_pause_frames" }
162};
163
164#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
165
de0c62db
DK		 166static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
167{
168 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 169 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
170 /* Dual Media boards present all available port types */
171 cmd->supported = bp->port.supported[cfg_idx] |
172 (bp->port.supported[cfg_idx ^ 1] &
173 (SUPPORTED_TP | SUPPORTED_FIBRE));
174 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db
DK		 175
176 if ((bp->state == BNX2X_STATE_OPEN) &&
177 !(bp->flags & MF_FUNC_DIS) &&
178 (bp->link_vars.link_up)) {
179 cmd->speed = bp->link_vars.line_speed;
180 cmd->duplex = bp->link_vars.duplex;
de0c62db 181 } else {
f2e0899f 182
a22f0788
YR		 183 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
184 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
de0c62db 185 }
f2e0899f 186
0793f83f
DK		 187 if (IS_MF(bp))
188 cmd->speed = bnx2x_get_mf_speed(bp);
de0c62db 189
a22f0788
YR		 190 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
191 cmd->port = PORT_TP;
192 else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
193 cmd->port = PORT_FIBRE;
194 else
195 BNX2X_ERR("XGXS PHY Failure detected\n");
196
de0c62db
DK		 197 cmd->phy_address = bp->mdio.prtad;
198 cmd->transceiver = XCVR_INTERNAL;
199
a22f0788 200 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 201 cmd->autoneg = AUTONEG_ENABLE;
202 else
203 cmd->autoneg = AUTONEG_DISABLE;
204
205 cmd->maxtxpkt = 0;
206 cmd->maxrxpkt = 0;
207
208 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
209 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
210 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
211 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
212 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
213 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
214 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
215
216 return 0;
217}
218
219static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
220{
221 struct bnx2x *bp = netdev_priv(dev);
a22f0788 222 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 223 u32 speed;
de0c62db 224
0793f83f 225 if (IS_MF_SD(bp))
de0c62db
DK		 226 return 0;
227
228 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
0793f83f
DK		 229 " supported 0x%x advertising 0x%x speed %d speed_hi %d\n"
230 " duplex %d port %d phy_address %d transceiver %d\n"
231 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
de0c62db 232 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
0793f83f 233 cmd->speed_hi,
de0c62db
DK		 234 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
235 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
236
0793f83f
DK		 237 speed = cmd->speed;
238 speed |= (cmd->speed_hi << 16);
239
240 if (IS_MF_SI(bp)) {
e3835b99 241 u32 part;
0793f83f
DK		 242 u32 line_speed = bp->link_vars.line_speed;
243
244 /* use 10G if no link detected */
245 if (!line_speed)
246 line_speed = 10000;
247
248 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
249 BNX2X_DEV_INFO("To set speed BC %X or higher "
250 "is required, please upgrade BC\n",
251 REQ_BC_VER_4_SET_MF_BW);
252 return -EINVAL;
253 }
e3835b99 254
faa6fcbb 255 part = (speed * 100) / line_speed;
e3835b99 256
faa6fcbb
DK		 257 if (line_speed < speed || !part) {
258 BNX2X_DEV_INFO("Speed setting should be in a range "
259 "from 1%% to 100%% "
260 "of actual line speed\n");
0793f83f
DK		 261 return -EINVAL;
262 }
0793f83f 263
e3835b99
DK		 264 if (bp->state != BNX2X_STATE_OPEN)
265 /* store value for following "load" */
266 bp->pending_max = part;
267 else
268 bnx2x_update_max_mf_config(bp, part);
0793f83f 269
0793f83f
DK		 270 return 0;
271 }
272
a22f0788
YR		 273 cfg_idx = bnx2x_get_link_cfg_idx(bp);
274 old_multi_phy_config = bp->link_params.multi_phy_config;
275 switch (cmd->port) {
276 case PORT_TP:
277 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
278 break; /* no port change */
279
280 if (!(bp->port.supported[0] & SUPPORTED_TP ||
281 bp->port.supported[1] & SUPPORTED_TP)) {
282 DP(NETIF_MSG_LINK, "Unsupported port type\n");
283 return -EINVAL;
284 }
285 bp->link_params.multi_phy_config &=
286 ~PORT_HW_CFG_PHY_SELECTION_MASK;
287 if (bp->link_params.multi_phy_config &
288 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
289 bp->link_params.multi_phy_config |=
290 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
291 else
292 bp->link_params.multi_phy_config |=
293 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
294 break;
295 case PORT_FIBRE:
296 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
297 break; /* no port change */
298
299 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
300 bp->port.supported[1] & SUPPORTED_FIBRE)) {
301 DP(NETIF_MSG_LINK, "Unsupported port type\n");
302 return -EINVAL;
303 }
304 bp->link_params.multi_phy_config &=
305 ~PORT_HW_CFG_PHY_SELECTION_MASK;
306 if (bp->link_params.multi_phy_config &
307 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
308 bp->link_params.multi_phy_config |=
309 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
310 else
311 bp->link_params.multi_phy_config |=
312 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
313 break;
314 default:
315 DP(NETIF_MSG_LINK, "Unsupported port type\n");
316 return -EINVAL;
317 }
318 /* Save new config in case command complete successuly */
319 new_multi_phy_config = bp->link_params.multi_phy_config;
320 /* Get the new cfg_idx */
321 cfg_idx = bnx2x_get_link_cfg_idx(bp);
322 /* Restore old config in case command failed */
323 bp->link_params.multi_phy_config = old_multi_phy_config;
324 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
325
de0c62db 326 if (cmd->autoneg == AUTONEG_ENABLE) {
a22f0788 327 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 328 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
329 return -EINVAL;
330 }
331
332 /* advertise the requested speed and duplex if supported */
a22f0788 333 cmd->advertising &= bp->port.supported[cfg_idx];
de0c62db 334
a22f0788
YR		 335 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
336 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
337 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
de0c62db
DK		 338 cmd->advertising);
339
340 } else { /* forced speed */
341 /* advertise the requested speed and duplex if supported */
a22f0788 342 switch (speed) {
de0c62db
DK		 343 case SPEED_10:
344 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 345 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 346 SUPPORTED_10baseT_Full)) {
347 DP(NETIF_MSG_LINK,
348 "10M full not supported\n");
349 return -EINVAL;
350 }
351
352 advertising = (ADVERTISED_10baseT_Full |
353 ADVERTISED_TP);
354 } else {
a22f0788 355 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 356 SUPPORTED_10baseT_Half)) {
357 DP(NETIF_MSG_LINK,
358 "10M half not supported\n");
359 return -EINVAL;
360 }
361
362 advertising = (ADVERTISED_10baseT_Half |
363 ADVERTISED_TP);
364 }
365 break;
366
367 case SPEED_100:
368 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 369 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 370 SUPPORTED_100baseT_Full)) {
371 DP(NETIF_MSG_LINK,
372 "100M full not supported\n");
373 return -EINVAL;
374 }
375
376 advertising = (ADVERTISED_100baseT_Full |
377 ADVERTISED_TP);
378 } else {
a22f0788 379 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 380 SUPPORTED_100baseT_Half)) {
381 DP(NETIF_MSG_LINK,
382 "100M half not supported\n");
383 return -EINVAL;
384 }
385
386 advertising = (ADVERTISED_100baseT_Half |
387 ADVERTISED_TP);
388 }
389 break;
390
391 case SPEED_1000:
392 if (cmd->duplex != DUPLEX_FULL) {
393 DP(NETIF_MSG_LINK, "1G half not supported\n");
394 return -EINVAL;
395 }
396
a22f0788
YR		 397 if (!(bp->port.supported[cfg_idx] &
398 SUPPORTED_1000baseT_Full)) {
de0c62db
DK		 399 DP(NETIF_MSG_LINK, "1G full not supported\n");
400 return -EINVAL;
401 }
402
403 advertising = (ADVERTISED_1000baseT_Full |
404 ADVERTISED_TP);
405 break;
406
407 case SPEED_2500:
408 if (cmd->duplex != DUPLEX_FULL) {
409 DP(NETIF_MSG_LINK,
410 "2.5G half not supported\n");
411 return -EINVAL;
412 }
413
a22f0788
YR		 414 if (!(bp->port.supported[cfg_idx]
415 & SUPPORTED_2500baseX_Full)) {
de0c62db
DK		 416 DP(NETIF_MSG_LINK,
417 "2.5G full not supported\n");
418 return -EINVAL;
419 }
420
421 advertising = (ADVERTISED_2500baseX_Full |
422 ADVERTISED_TP);
423 break;
424
425 case SPEED_10000:
426 if (cmd->duplex != DUPLEX_FULL) {
427 DP(NETIF_MSG_LINK, "10G half not supported\n");
428 return -EINVAL;
429 }
430
a22f0788
YR		 431 if (!(bp->port.supported[cfg_idx]
432 & SUPPORTED_10000baseT_Full)) {
de0c62db
DK		 433 DP(NETIF_MSG_LINK, "10G full not supported\n");
434 return -EINVAL;
435 }
436
437 advertising = (ADVERTISED_10000baseT_Full |
438 ADVERTISED_FIBRE);
439 break;
440
441 default:
a22f0788 442 DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed);
de0c62db
DK		 443 return -EINVAL;
444 }
445
a22f0788
YR		 446 bp->link_params.req_line_speed[cfg_idx] = speed;
447 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
448 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 449 }
450
451 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
452 DP_LEVEL " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 453 bp->link_params.req_line_speed[cfg_idx],
454 bp->link_params.req_duplex[cfg_idx],
455 bp->port.advertising[cfg_idx]);
de0c62db 456
a22f0788
YR		 457 /* Set new config */
458 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 459 if (netif_running(dev)) {
460 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
461 bnx2x_link_set(bp);
462 }
463
464 return 0;
465}
466
467#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
468#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 469#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
de0c62db
DK		 470
471static int bnx2x_get_regs_len(struct net_device *dev)
472{
473 struct bnx2x *bp = netdev_priv(dev);
474 int regdump_len = 0;
4a33bc03 475 int i, j, k;
de0c62db
DK		 476
477 if (CHIP_IS_E1(bp)) {
478 for (i = 0; i < REGS_COUNT; i++)
479 if (IS_E1_ONLINE(reg_addrs[i].info))
480 regdump_len += reg_addrs[i].size;
481
482 for (i = 0; i < WREGS_COUNT_E1; i++)
483 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
484 regdump_len += wreg_addrs_e1[i].size *
485 (1 + wreg_addrs_e1[i].read_regs_count);
486
f2e0899f 487 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 488 for (i = 0; i < REGS_COUNT; i++)
489 if (IS_E1H_ONLINE(reg_addrs[i].info))
490 regdump_len += reg_addrs[i].size;
491
492 for (i = 0; i < WREGS_COUNT_E1H; i++)
493 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
494 regdump_len += wreg_addrs_e1h[i].size *
495 (1 + wreg_addrs_e1h[i].read_regs_count);
f2e0899f
DK		 496 } else if (CHIP_IS_E2(bp)) {
497 for (i = 0; i < REGS_COUNT; i++)
498 if (IS_E2_ONLINE(reg_addrs[i].info))
499 regdump_len += reg_addrs[i].size;
500
501 for (i = 0; i < WREGS_COUNT_E2; i++)
502 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
503 regdump_len += wreg_addrs_e2[i].size *
504 (1 + wreg_addrs_e2[i].read_regs_count);
4a33bc03
VZ		 505
506 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
507 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
508 for (k = 0; k < PAGE_READ_REGS_E2; k++)
509 if (IS_E2_ONLINE(page_read_regs_e2[k].
510 info))
511 regdump_len +=
512 page_read_regs_e2[k].size;
513 }
de0c62db
DK		 514 }
515 regdump_len *= 4;
516 regdump_len += sizeof(struct dump_hdr);
517
518 return regdump_len;
519}
520
f2e0899f
DK		 521static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
522{
523 u32 i, j, k, n;
524
525 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
526 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
527 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
528 for (k = 0; k < PAGE_READ_REGS_E2; k++)
529 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
530 for (n = 0; n <
531 page_read_regs_e2[k].size; n++)
532 *p++ = REG_RD(bp,
533 page_read_regs_e2[k].addr + n*4);
534 }
535 }
536}
537
de0c62db
DK		 538static void bnx2x_get_regs(struct net_device *dev,
539 struct ethtool_regs *regs, void *_p)
540{
541 u32 *p = _p, i, j;
542 struct bnx2x *bp = netdev_priv(dev);
543 struct dump_hdr dump_hdr = {0};
544
545 regs->version = 0;
546 memset(p, 0, regs->len);
547
548 if (!netif_running(bp->dev))
549 return;
550
4a33bc03
VZ		 551 /* Disable parity attentions as long as following dump may
552 * cause false alarms by reading never written registers. We
553 * will re-enable parity attentions right after the dump.
554 */
555 bnx2x_disable_blocks_parity(bp);
556
de0c62db
DK		 557 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
558 dump_hdr.dump_sign = dump_sign_all;
559 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
560 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
561 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
562 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 563
564 if (CHIP_IS_E1(bp))
565 dump_hdr.info = RI_E1_ONLINE;
566 else if (CHIP_IS_E1H(bp))
567 dump_hdr.info = RI_E1H_ONLINE;
568 else if (CHIP_IS_E2(bp))
569 dump_hdr.info = RI_E2_ONLINE |
570 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 571
572 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
573 p += dump_hdr.hdr_size + 1;
574
575 if (CHIP_IS_E1(bp)) {
576 for (i = 0; i < REGS_COUNT; i++)
577 if (IS_E1_ONLINE(reg_addrs[i].info))
578 for (j = 0; j < reg_addrs[i].size; j++)
579 *p++ = REG_RD(bp,
580 reg_addrs[i].addr + j*4);
581
f2e0899f 582 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 583 for (i = 0; i < REGS_COUNT; i++)
584 if (IS_E1H_ONLINE(reg_addrs[i].info))
585 for (j = 0; j < reg_addrs[i].size; j++)
586 *p++ = REG_RD(bp,
587 reg_addrs[i].addr + j*4);
f2e0899f
DK		 588
589 } else if (CHIP_IS_E2(bp)) {
590 for (i = 0; i < REGS_COUNT; i++)
591 if (IS_E2_ONLINE(reg_addrs[i].info))
592 for (j = 0; j < reg_addrs[i].size; j++)
593 *p++ = REG_RD(bp,
594 reg_addrs[i].addr + j*4);
595
596 bnx2x_read_pages_regs_e2(bp, p);
de0c62db 597 }
4a33bc03
VZ		 598 /* Re-enable parity attentions */
599 bnx2x_clear_blocks_parity(bp);
600 if (CHIP_PARITY_ENABLED(bp))
601 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 602}
603
f2e0899f 604#define PHY_FW_VER_LEN 20
de0c62db
DK		 605
606static void bnx2x_get_drvinfo(struct net_device *dev,
607 struct ethtool_drvinfo *info)
608{
609 struct bnx2x *bp = netdev_priv(dev);
610 u8 phy_fw_ver[PHY_FW_VER_LEN];
611
612 strcpy(info->driver, DRV_MODULE_NAME);
613 strcpy(info->version, DRV_MODULE_VERSION);
614
615 phy_fw_ver[0] = '\0';
616 if (bp->port.pmf) {
617 bnx2x_acquire_phy_lock(bp);
618 bnx2x_get_ext_phy_fw_version(&bp->link_params,
619 (bp->state != BNX2X_STATE_CLOSED),
620 phy_fw_ver, PHY_FW_VER_LEN);
621 bnx2x_release_phy_lock(bp);
622 }
623
624 strncpy(info->fw_version, bp->fw_ver, 32);
625 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
626 "bc %d.%d.%d%s%s",
627 (bp->common.bc_ver & 0xff0000) >> 16,
628 (bp->common.bc_ver & 0xff00) >> 8,
629 (bp->common.bc_ver & 0xff),
630 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
631 strcpy(info->bus_info, pci_name(bp->pdev));
632 info->n_stats = BNX2X_NUM_STATS;
633 info->testinfo_len = BNX2X_NUM_TESTS;
634 info->eedump_len = bp->common.flash_size;
635 info->regdump_len = bnx2x_get_regs_len(dev);
636}
637
638static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
639{
640 struct bnx2x *bp = netdev_priv(dev);
641
642 if (bp->flags & NO_WOL_FLAG) {
643 wol->supported = 0;
644 wol->wolopts = 0;
645 } else {
646 wol->supported = WAKE_MAGIC;
647 if (bp->wol)
648 wol->wolopts = WAKE_MAGIC;
649 else
650 wol->wolopts = 0;
651 }
652 memset(&wol->sopass, 0, sizeof(wol->sopass));
653}
654
655static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
656{
657 struct bnx2x *bp = netdev_priv(dev);
658
659 if (wol->wolopts & ~WAKE_MAGIC)
660 return -EINVAL;
661
662 if (wol->wolopts & WAKE_MAGIC) {
663 if (bp->flags & NO_WOL_FLAG)
664 return -EINVAL;
665
666 bp->wol = 1;
667 } else
668 bp->wol = 0;
669
670 return 0;
671}
672
673static u32 bnx2x_get_msglevel(struct net_device *dev)
674{
675 struct bnx2x *bp = netdev_priv(dev);
676
677 return bp->msg_enable;
678}
679
680static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
681{
682 struct bnx2x *bp = netdev_priv(dev);
683
684 if (capable(CAP_NET_ADMIN))
685 bp->msg_enable = level;
686}
687
688static int bnx2x_nway_reset(struct net_device *dev)
689{
690 struct bnx2x *bp = netdev_priv(dev);
691
692 if (!bp->port.pmf)
693 return 0;
694
695 if (netif_running(dev)) {
696 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
697 bnx2x_link_set(bp);
698 }
699
700 return 0;
701}
702
703static u32 bnx2x_get_link(struct net_device *dev)
704{
705 struct bnx2x *bp = netdev_priv(dev);
706
f2e0899f 707 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 708 return 0;
709
710 return bp->link_vars.link_up;
711}
712
713static int bnx2x_get_eeprom_len(struct net_device *dev)
714{
715 struct bnx2x *bp = netdev_priv(dev);
716
717 return bp->common.flash_size;
718}
719
720static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
721{
722 int port = BP_PORT(bp);
723 int count, i;
724 u32 val = 0;
725
726 /* adjust timeout for emulation/FPGA */
727 count = NVRAM_TIMEOUT_COUNT;
728 if (CHIP_REV_IS_SLOW(bp))
729 count *= 100;
730
731 /* request access to nvram interface */
732 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
733 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
734
735 for (i = 0; i < count*10; i++) {
736 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
737 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
738 break;
739
740 udelay(5);
741 }
742
743 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
744 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
745 return -EBUSY;
746 }
747
748 return 0;
749}
750
751static int bnx2x_release_nvram_lock(struct bnx2x *bp)
752{
753 int port = BP_PORT(bp);
754 int count, i;
755 u32 val = 0;
756
757 /* adjust timeout for emulation/FPGA */
758 count = NVRAM_TIMEOUT_COUNT;
759 if (CHIP_REV_IS_SLOW(bp))
760 count *= 100;
761
762 /* relinquish nvram interface */
763 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
764 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
765
766 for (i = 0; i < count*10; i++) {
767 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
768 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
769 break;
770
771 udelay(5);
772 }
773
774 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
775 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
776 return -EBUSY;
777 }
778
779 return 0;
780}
781
782static void bnx2x_enable_nvram_access(struct bnx2x *bp)
783{
784 u32 val;
785
786 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
787
788 /* enable both bits, even on read */
789 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
790 (val | MCPR_NVM_ACCESS_ENABLE_EN |
791 MCPR_NVM_ACCESS_ENABLE_WR_EN));
792}
793
794static void bnx2x_disable_nvram_access(struct bnx2x *bp)
795{
796 u32 val;
797
798 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
799
800 /* disable both bits, even after read */
801 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
802 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
803 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
804}
805
806static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
807 u32 cmd_flags)
808{
809 int count, i, rc;
810 u32 val;
811
812 /* build the command word */
813 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
814
815 /* need to clear DONE bit separately */
816 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
817
818 /* address of the NVRAM to read from */
819 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
820 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
821
822 /* issue a read command */
823 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
824
825 /* adjust timeout for emulation/FPGA */
826 count = NVRAM_TIMEOUT_COUNT;
827 if (CHIP_REV_IS_SLOW(bp))
828 count *= 100;
829
830 /* wait for completion */
831 *ret_val = 0;
832 rc = -EBUSY;
833 for (i = 0; i < count; i++) {
834 udelay(5);
835 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
836
837 if (val & MCPR_NVM_COMMAND_DONE) {
838 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
839 /* we read nvram data in cpu order
840 * but ethtool sees it as an array of bytes
841 * converting to big-endian will do the work */
842 *ret_val = cpu_to_be32(val);
843 rc = 0;
844 break;
845 }
846 }
847
848 return rc;
849}
850
851static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
852 int buf_size)
853{
854 int rc;
855 u32 cmd_flags;
856 __be32 val;
857
858 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
859 DP(BNX2X_MSG_NVM,
860 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
861 offset, buf_size);
862 return -EINVAL;
863 }
864
865 if (offset + buf_size > bp->common.flash_size) {
866 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
867 " buf_size (0x%x) > flash_size (0x%x)\n",
868 offset, buf_size, bp->common.flash_size);
869 return -EINVAL;
870 }
871
872 /* request access to nvram interface */
873 rc = bnx2x_acquire_nvram_lock(bp);
874 if (rc)
875 return rc;
876
877 /* enable access to nvram interface */
878 bnx2x_enable_nvram_access(bp);
879
880 /* read the first word(s) */
881 cmd_flags = MCPR_NVM_COMMAND_FIRST;
882 while ((buf_size > sizeof(u32)) && (rc == 0)) {
883 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
884 memcpy(ret_buf, &val, 4);
885
886 /* advance to the next dword */
887 offset += sizeof(u32);
888 ret_buf += sizeof(u32);
889 buf_size -= sizeof(u32);
890 cmd_flags = 0;
891 }
892
893 if (rc == 0) {
894 cmd_flags |= MCPR_NVM_COMMAND_LAST;
895 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
896 memcpy(ret_buf, &val, 4);
897 }
898
899 /* disable access to nvram interface */
900 bnx2x_disable_nvram_access(bp);
901 bnx2x_release_nvram_lock(bp);
902
903 return rc;
904}
905
906static int bnx2x_get_eeprom(struct net_device *dev,
907 struct ethtool_eeprom *eeprom, u8 *eebuf)
908{
909 struct bnx2x *bp = netdev_priv(dev);
910 int rc;
911
912 if (!netif_running(dev))
913 return -EAGAIN;
914
915 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
916 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
917 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
918 eeprom->len, eeprom->len);
919
920 /* parameters already validated in ethtool_get_eeprom */
921
922 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
923
924 return rc;
925}
926
927static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
928 u32 cmd_flags)
929{
930 int count, i, rc;
931
932 /* build the command word */
933 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
934
935 /* need to clear DONE bit separately */
936 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
937
938 /* write the data */
939 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
940
941 /* address of the NVRAM to write to */
942 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
943 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
944
945 /* issue the write command */
946 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
947
948 /* adjust timeout for emulation/FPGA */
949 count = NVRAM_TIMEOUT_COUNT;
950 if (CHIP_REV_IS_SLOW(bp))
951 count *= 100;
952
953 /* wait for completion */
954 rc = -EBUSY;
955 for (i = 0; i < count; i++) {
956 udelay(5);
957 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
958 if (val & MCPR_NVM_COMMAND_DONE) {
959 rc = 0;
960 break;
961 }
962 }
963
964 return rc;
965}
966
967#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
968
969static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
970 int buf_size)
971{
972 int rc;
973 u32 cmd_flags;
974 u32 align_offset;
975 __be32 val;
976
977 if (offset + buf_size > bp->common.flash_size) {
978 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
979 " buf_size (0x%x) > flash_size (0x%x)\n",
980 offset, buf_size, bp->common.flash_size);
981 return -EINVAL;
982 }
983
984 /* request access to nvram interface */
985 rc = bnx2x_acquire_nvram_lock(bp);
986 if (rc)
987 return rc;
988
989 /* enable access to nvram interface */
990 bnx2x_enable_nvram_access(bp);
991
992 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
993 align_offset = (offset & ~0x03);
994 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
995
996 if (rc == 0) {
997 val &= ~(0xff << BYTE_OFFSET(offset));
998 val |= (*data_buf << BYTE_OFFSET(offset));
999
1000 /* nvram data is returned as an array of bytes
1001 * convert it back to cpu order */
1002 val = be32_to_cpu(val);
1003
1004 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1005 cmd_flags);
1006 }
1007
1008 /* disable access to nvram interface */
1009 bnx2x_disable_nvram_access(bp);
1010 bnx2x_release_nvram_lock(bp);
1011
1012 return rc;
1013}
1014
1015static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1016 int buf_size)
1017{
1018 int rc;
1019 u32 cmd_flags;
1020 u32 val;
1021 u32 written_so_far;
1022
1023 if (buf_size == 1) /* ethtool */
1024 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1025
1026 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1027 DP(BNX2X_MSG_NVM,
1028 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1029 offset, buf_size);
1030 return -EINVAL;
1031 }
1032
1033 if (offset + buf_size > bp->common.flash_size) {
1034 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1035 " buf_size (0x%x) > flash_size (0x%x)\n",
1036 offset, buf_size, bp->common.flash_size);
1037 return -EINVAL;
1038 }
1039
1040 /* request access to nvram interface */
1041 rc = bnx2x_acquire_nvram_lock(bp);
1042 if (rc)
1043 return rc;
1044
1045 /* enable access to nvram interface */
1046 bnx2x_enable_nvram_access(bp);
1047
1048 written_so_far = 0;
1049 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1050 while ((written_so_far < buf_size) && (rc == 0)) {
1051 if (written_so_far == (buf_size - sizeof(u32)))
1052 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1053 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1054 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1055 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1056 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1057
1058 memcpy(&val, data_buf, 4);
1059
1060 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1061
1062 /* advance to the next dword */
1063 offset += sizeof(u32);
1064 data_buf += sizeof(u32);
1065 written_so_far += sizeof(u32);
1066 cmd_flags = 0;
1067 }
1068
1069 /* disable access to nvram interface */
1070 bnx2x_disable_nvram_access(bp);
1071 bnx2x_release_nvram_lock(bp);
1072
1073 return rc;
1074}
1075
1076static int bnx2x_set_eeprom(struct net_device *dev,
1077 struct ethtool_eeprom *eeprom, u8 *eebuf)
1078{
1079 struct bnx2x *bp = netdev_priv(dev);
1080 int port = BP_PORT(bp);
1081 int rc = 0;
e10bc84d 1082 u32 ext_phy_config;
de0c62db
DK		 1083 if (!netif_running(dev))
1084 return -EAGAIN;
1085
1086 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1087 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1088 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1089 eeprom->len, eeprom->len);
1090
1091 /* parameters already validated in ethtool_set_eeprom */
1092
1093 /* PHY eeprom can be accessed only by the PMF */
1094 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1095 !bp->port.pmf)
1096 return -EINVAL;
1097
e10bc84d
YR		 1098 ext_phy_config =
1099 SHMEM_RD(bp,
1100 dev_info.port_hw_config[port].external_phy_config);
1101
de0c62db
DK		 1102 if (eeprom->magic == 0x50485950) {
1103 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1104 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1105
1106 bnx2x_acquire_phy_lock(bp);
1107 rc |= bnx2x_link_reset(&bp->link_params,
1108 &bp->link_vars, 0);
e10bc84d 1109 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1110 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1111 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1112 MISC_REGISTERS_GPIO_HIGH, port);
1113 bnx2x_release_phy_lock(bp);
1114 bnx2x_link_report(bp);
1115
1116 } else if (eeprom->magic == 0x50485952) {
1117 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1118 if (bp->state == BNX2X_STATE_OPEN) {
1119 bnx2x_acquire_phy_lock(bp);
1120 rc |= bnx2x_link_reset(&bp->link_params,
1121 &bp->link_vars, 1);
1122
1123 rc |= bnx2x_phy_init(&bp->link_params,
1124 &bp->link_vars);
1125 bnx2x_release_phy_lock(bp);
1126 bnx2x_calc_fc_adv(bp);
1127 }
1128 } else if (eeprom->magic == 0x53985943) {
1129 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1130 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1131 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1132
1133 /* DSP Remove Download Mode */
1134 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1135 MISC_REGISTERS_GPIO_LOW, port);
1136
1137 bnx2x_acquire_phy_lock(bp);
1138
e10bc84d
YR		 1139 bnx2x_sfx7101_sp_sw_reset(bp,
1140 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1141
1142 /* wait 0.5 sec to allow it to run */
1143 msleep(500);
1144 bnx2x_ext_phy_hw_reset(bp, port);
1145 msleep(500);
1146 bnx2x_release_phy_lock(bp);
1147 }
1148 } else
1149 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1150
1151 return rc;
1152}
f85582f8 1153
de0c62db
DK		 1154static int bnx2x_get_coalesce(struct net_device *dev,
1155 struct ethtool_coalesce *coal)
1156{
1157 struct bnx2x *bp = netdev_priv(dev);
1158
1159 memset(coal, 0, sizeof(struct ethtool_coalesce));
1160
1161 coal->rx_coalesce_usecs = bp->rx_ticks;
1162 coal->tx_coalesce_usecs = bp->tx_ticks;
1163
1164 return 0;
1165}
1166
1167static int bnx2x_set_coalesce(struct net_device *dev,
1168 struct ethtool_coalesce *coal)
1169{
1170 struct bnx2x *bp = netdev_priv(dev);
1171
1172 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1173 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1174 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1175
1176 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1177 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1178 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1179
1180 if (netif_running(dev))
1181 bnx2x_update_coalesce(bp);
1182
1183 return 0;
1184}
1185
1186static void bnx2x_get_ringparam(struct net_device *dev,
1187 struct ethtool_ringparam *ering)
1188{
1189 struct bnx2x *bp = netdev_priv(dev);
1190
1191 ering->rx_max_pending = MAX_RX_AVAIL;
1192 ering->rx_mini_max_pending = 0;
1193 ering->rx_jumbo_max_pending = 0;
1194
25141580
DK		 1195 if (bp->rx_ring_size)
1196 ering->rx_pending = bp->rx_ring_size;
1197 else
1198 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1199 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1200 else
1201 ering->rx_pending = MAX_RX_AVAIL;
1202
de0c62db
DK		 1203 ering->rx_mini_pending = 0;
1204 ering->rx_jumbo_pending = 0;
1205
1206 ering->tx_max_pending = MAX_TX_AVAIL;
1207 ering->tx_pending = bp->tx_ring_size;
1208}
1209
1210static int bnx2x_set_ringparam(struct net_device *dev,
1211 struct ethtool_ringparam *ering)
1212{
1213 struct bnx2x *bp = netdev_priv(dev);
1214 int rc = 0;
1215
1216 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1217 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1218 return -EAGAIN;
1219 }
1220
1221 if ((ering->rx_pending > MAX_RX_AVAIL) ||
25141580 1222 (ering->rx_pending < MIN_RX_AVAIL) ||
de0c62db
DK		 1223 (ering->tx_pending > MAX_TX_AVAIL) ||
1224 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1225 return -EINVAL;
1226
1227 bp->rx_ring_size = ering->rx_pending;
1228 bp->tx_ring_size = ering->tx_pending;
1229
1230 if (netif_running(dev)) {
1231 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1232 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1233 }
1234
1235 return rc;
1236}
1237
1238static void bnx2x_get_pauseparam(struct net_device *dev,
1239 struct ethtool_pauseparam *epause)
1240{
1241 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 1242 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1243 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1244 BNX2X_FLOW_CTRL_AUTO);
de0c62db
DK		 1245
1246 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1247 BNX2X_FLOW_CTRL_RX);
1248 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1249 BNX2X_FLOW_CTRL_TX);
1250
1251 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1252 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1253 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1254}
1255
1256static int bnx2x_set_pauseparam(struct net_device *dev,
1257 struct ethtool_pauseparam *epause)
1258{
1259 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1260 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1261 if (IS_MF(bp))
de0c62db
DK		 1262 return 0;
1263
1264 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1265 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1266 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1267
a22f0788 1268 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1269
1270 if (epause->rx_pause)
a22f0788 1271 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1272
1273 if (epause->tx_pause)
a22f0788 1274 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1275
a22f0788
YR		 1276 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1277 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1278
1279 if (epause->autoneg) {
a22f0788 1280 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 1281 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1282 return -EINVAL;
1283 }
1284
a22f0788
YR		 1285 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1286 bp->link_params.req_flow_ctrl[cfg_idx] =
1287 BNX2X_FLOW_CTRL_AUTO;
1288 }
de0c62db
DK		 1289 }
1290
1291 DP(NETIF_MSG_LINK,
a22f0788 1292 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1293
1294 if (netif_running(dev)) {
1295 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1296 bnx2x_link_set(bp);
1297 }
1298
1299 return 0;
1300}
1301
de0c62db
DK		 1302static const struct {
1303 char string[ETH_GSTRING_LEN];
1304} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1305 { "register_test (offline)" },
1306 { "memory_test (offline)" },
1307 { "loopback_test (offline)" },
1308 { "nvram_test (online)" },
1309 { "interrupt_test (online)" },
1310 { "link_test (online)" },
1311 { "idle check (online)" }
1312};
1313
1314static int bnx2x_test_registers(struct bnx2x *bp)
1315{
1316 int idx, i, rc = -ENODEV;
1317 u32 wr_val = 0;
1318 int port = BP_PORT(bp);
1319 static const struct {
1320 u32 offset0;
1321 u32 offset1;
1322 u32 mask;
1323 } reg_tbl[] = {
1324/* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1325 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1326 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1327 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1328 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1329 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1330 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1331 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1332 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1333 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1334/* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1335 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1336 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1337 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1338 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1339 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1340 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1341 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1342 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1343 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1344/* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1345 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1346 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1347 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1348 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1349 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1350 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1351 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1352 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1353 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1354/* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1355 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1356 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1357 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1358 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1359 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1360 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1361
1362 { 0xffffffff, 0, 0x00000000 }
1363 };
1364
1365 if (!netif_running(bp->dev))
1366 return rc;
1367
1368 /* Repeat the test twice:
1369 First by writing 0x00000000, second by writing 0xffffffff */
1370 for (idx = 0; idx < 2; idx++) {
1371
1372 switch (idx) {
1373 case 0:
1374 wr_val = 0;
1375 break;
1376 case 1:
1377 wr_val = 0xffffffff;
1378 break;
1379 }
1380
1381 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1382 u32 offset, mask, save_val, val;
f2e0899f
DK		 1383 if (CHIP_IS_E2(bp) &&
1384 reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1385 continue;
de0c62db
DK		 1386
1387 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1388 mask = reg_tbl[i].mask;
1389
1390 save_val = REG_RD(bp, offset);
1391
ec6ba945 1392 REG_WR(bp, offset, wr_val & mask);
f85582f8 1393
de0c62db
DK		 1394 val = REG_RD(bp, offset);
1395
1396 /* Restore the original register's value */
1397 REG_WR(bp, offset, save_val);
1398
1399 /* verify value is as expected */
1400 if ((val & mask) != (wr_val & mask)) {
1401 DP(NETIF_MSG_PROBE,
1402 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1403 offset, val, wr_val, mask);
1404 goto test_reg_exit;
1405 }
1406 }
1407 }
1408
1409 rc = 0;
1410
1411test_reg_exit:
1412 return rc;
1413}
1414
1415static int bnx2x_test_memory(struct bnx2x *bp)
1416{
1417 int i, j, rc = -ENODEV;
1418 u32 val;
1419 static const struct {
1420 u32 offset;
1421 int size;
1422 } mem_tbl[] = {
1423 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1424 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1425 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1426 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1427 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1428 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1429 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1430
1431 { 0xffffffff, 0 }
1432 };
1433 static const struct {
1434 char *name;
1435 u32 offset;
1436 u32 e1_mask;
1437 u32 e1h_mask;
f2e0899f 1438 u32 e2_mask;
de0c62db 1439 } prty_tbl[] = {
f2e0899f
DK		 1440 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 },
1441 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 },
1442 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 },
1443 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 },
1444 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 },
1445 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 },
1446
1447 { NULL, 0xffffffff, 0, 0, 0 }
de0c62db
DK		 1448 };
1449
1450 if (!netif_running(bp->dev))
1451 return rc;
1452
f2e0899f
DK		 1453 /* pre-Check the parity status */
1454 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1455 val = REG_RD(bp, prty_tbl[i].offset);
1456 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1457 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1458 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1459 DP(NETIF_MSG_HW,
1460 "%s is 0x%x\n", prty_tbl[i].name, val);
1461 goto test_mem_exit;
1462 }
1463 }
1464
de0c62db
DK		 1465 /* Go through all the memories */
1466 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1467 for (j = 0; j < mem_tbl[i].size; j++)
1468 REG_RD(bp, mem_tbl[i].offset + j*4);
1469
1470 /* Check the parity status */
1471 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1472 val = REG_RD(bp, prty_tbl[i].offset);
1473 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
f2e0899f
DK		 1474 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1475 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
de0c62db
DK		 1476 DP(NETIF_MSG_HW,
1477 "%s is 0x%x\n", prty_tbl[i].name, val);
1478 goto test_mem_exit;
1479 }
1480 }
1481
1482 rc = 0;
1483
1484test_mem_exit:
1485 return rc;
1486}
1487
a22f0788 1488static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1489{
f2e0899f 1490 int cnt = 1400;
de0c62db
DK		 1491
1492 if (link_up)
a22f0788 1493 while (bnx2x_link_test(bp, is_serdes) && cnt--)
de0c62db
DK		 1494 msleep(10);
1495}
1496
1497static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1498{
1499 unsigned int pkt_size, num_pkts, i;
1500 struct sk_buff *skb;
1501 unsigned char *packet;
1502 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1503 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1504 u16 tx_start_idx, tx_idx;
1505 u16 rx_start_idx, rx_idx;
1506 u16 pkt_prod, bd_prod;
1507 struct sw_tx_bd *tx_buf;
1508 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1509 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1510 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1511 dma_addr_t mapping;
1512 union eth_rx_cqe *cqe;
1513 u8 cqe_fp_flags;
1514 struct sw_rx_bd *rx_buf;
1515 u16 len;
1516 int rc = -ENODEV;
1517
1518 /* check the loopback mode */
1519 switch (loopback_mode) {
1520 case BNX2X_PHY_LOOPBACK:
de6eae1f 1521 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1522 return -EINVAL;
1523 break;
1524 case BNX2X_MAC_LOOPBACK:
1525 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1526 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1527 break;
1528 default:
1529 return -EINVAL;
1530 }
1531
1532 /* prepare the loopback packet */
1533 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1534 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 1535 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db
DK		 1536 if (!skb) {
1537 rc = -ENOMEM;
1538 goto test_loopback_exit;
1539 }
1540 packet = skb_put(skb, pkt_size);
1541 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1542 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1543 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1544 for (i = ETH_HLEN; i < pkt_size; i++)
1545 packet[i] = (unsigned char) (i & 0xff);
1546
1547 /* send the loopback packet */
1548 num_pkts = 0;
1549 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1550 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1551
1552 pkt_prod = fp_tx->tx_pkt_prod++;
1553 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1554 tx_buf->first_bd = fp_tx->tx_bd_prod;
1555 tx_buf->skb = skb;
1556 tx_buf->flags = 0;
1557
1558 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1559 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1560 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1561 skb_headlen(skb), DMA_TO_DEVICE);
1562 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1563 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1564 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1565 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1566 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1567 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1568 SET_FLAG(tx_start_bd->general_data,
1569 ETH_TX_START_BD_ETH_ADDR_TYPE,
1570 UNICAST_ADDRESS);
1571 SET_FLAG(tx_start_bd->general_data,
1572 ETH_TX_START_BD_HDR_NBDS,
1573 1);
de0c62db
DK		 1574
1575 /* turn on parsing and get a BD */
1576 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 1577
523224a3 1578 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
f2e0899f 1579 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1580
f2e0899f 1581 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1582 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1583
1584 wmb();
1585
1586 fp_tx->tx_db.data.prod += 2;
1587 barrier();
1588 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1589
1590 mmiowb();
1591
1592 num_pkts++;
1593 fp_tx->tx_bd_prod += 2; /* start + pbd */
1594
1595 udelay(100);
1596
1597 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1598 if (tx_idx != tx_start_idx + num_pkts)
1599 goto test_loopback_exit;
1600
f2e0899f
DK		 1601 /* Unlike HC IGU won't generate an interrupt for status block
1602 * updates that have been performed while interrupts were
1603 * disabled.
1604 */
e1210d12
ED		 1605 if (bp->common.int_block == INT_BLOCK_IGU) {
1606 /* Disable local BHes to prevent a dead-lock situation between
1607 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1608 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1609 */
1610 local_bh_disable();
f2e0899f 1611 bnx2x_tx_int(fp_tx);
e1210d12
ED		 1612 local_bh_enable();
1613 }
f2e0899f 1614
de0c62db
DK		 1615 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1616 if (rx_idx != rx_start_idx + num_pkts)
1617 goto test_loopback_exit;
1618
1619 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1620 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1621 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1622 goto test_loopback_rx_exit;
1623
1624 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1625 if (len != pkt_size)
1626 goto test_loopback_rx_exit;
1627
1628 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1629 skb = rx_buf->skb;
1630 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1631 for (i = ETH_HLEN; i < pkt_size; i++)
1632 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1633 goto test_loopback_rx_exit;
1634
1635 rc = 0;
1636
1637test_loopback_rx_exit:
1638
1639 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1640 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1641 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1642 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1643
1644 /* Update producers */
1645 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1646 fp_rx->rx_sge_prod);
1647
1648test_loopback_exit:
1649 bp->link_params.loopback_mode = LOOPBACK_NONE;
1650
1651 return rc;
1652}
1653
1654static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1655{
1656 int rc = 0, res;
1657
1658 if (BP_NOMCP(bp))
1659 return rc;
1660
1661 if (!netif_running(bp->dev))
1662 return BNX2X_LOOPBACK_FAILED;
1663
1664 bnx2x_netif_stop(bp, 1);
1665 bnx2x_acquire_phy_lock(bp);
1666
1667 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1668 if (res) {
1669 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1670 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1671 }
1672
1673 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1674 if (res) {
1675 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1676 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1677 }
1678
1679 bnx2x_release_phy_lock(bp);
1680 bnx2x_netif_start(bp);
1681
1682 return rc;
1683}
1684
1685#define CRC32_RESIDUAL 0xdebb20e3
1686
1687static int bnx2x_test_nvram(struct bnx2x *bp)
1688{
1689 static const struct {
1690 int offset;
1691 int size;
1692 } nvram_tbl[] = {
1693 { 0, 0x14 }, /* bootstrap */
1694 { 0x14, 0xec }, /* dir */
1695 { 0x100, 0x350 }, /* manuf_info */
1696 { 0x450, 0xf0 }, /* feature_info */
1697 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 1698 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 1699 { 0, 0 }
1700 };
1701 __be32 buf[0x350 / 4];
1702 u8 *data = (u8 *)buf;
1703 int i, rc;
1704 u32 magic, crc;
1705
1706 if (BP_NOMCP(bp))
1707 return 0;
1708
1709 rc = bnx2x_nvram_read(bp, 0, data, 4);
1710 if (rc) {
1711 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1712 goto test_nvram_exit;
1713 }
1714
1715 magic = be32_to_cpu(buf[0]);
1716 if (magic != 0x669955aa) {
1717 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1718 rc = -ENODEV;
1719 goto test_nvram_exit;
1720 }
1721
1722 for (i = 0; nvram_tbl[i].size; i++) {
1723
1724 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1725 nvram_tbl[i].size);
1726 if (rc) {
1727 DP(NETIF_MSG_PROBE,
1728 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1729 goto test_nvram_exit;
1730 }
1731
1732 crc = ether_crc_le(nvram_tbl[i].size, data);
1733 if (crc != CRC32_RESIDUAL) {
1734 DP(NETIF_MSG_PROBE,
1735 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1736 rc = -ENODEV;
1737 goto test_nvram_exit;
1738 }
1739 }
1740
1741test_nvram_exit:
1742 return rc;
1743}
1744
1745static int bnx2x_test_intr(struct bnx2x *bp)
1746{
1747 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1748 int i, rc;
1749
1750 if (!netif_running(bp->dev))
1751 return -ENODEV;
1752
1753 config->hdr.length = 0;
1754 if (CHIP_IS_E1(bp))
f2e0899f 1755 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
de0c62db
DK		 1756 else
1757 config->hdr.offset = BP_FUNC(bp);
1758 config->hdr.client_id = bp->fp->cl_id;
1759 config->hdr.reserved1 = 0;
1760
ec6ba945 1761 bp->set_mac_pending = 1;
de0c62db 1762 smp_wmb();
523224a3 1763 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
de0c62db 1764 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3 1765 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
de0c62db
DK		 1766 if (rc == 0) {
1767 for (i = 0; i < 10; i++) {
1768 if (!bp->set_mac_pending)
1769 break;
1770 smp_rmb();
1771 msleep_interruptible(10);
1772 }
1773 if (i == 10)
1774 rc = -ENODEV;
1775 }
1776
1777 return rc;
1778}
1779
1780static void bnx2x_self_test(struct net_device *dev,
1781 struct ethtool_test *etest, u64 *buf)
1782{
1783 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1784 u8 is_serdes;
de0c62db
DK		 1785 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1786 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1787 etest->flags |= ETH_TEST_FL_FAILED;
1788 return;
1789 }
1790
1791 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1792
1793 if (!netif_running(dev))
1794 return;
1795
1796 /* offline tests are not supported in MF mode */
fb3bff17 1797 if (IS_MF(bp))
de0c62db 1798 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 1799 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 1800
1801 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1802 int port = BP_PORT(bp);
1803 u32 val;
1804 u8 link_up;
1805
1806 /* save current value of input enable for TX port IF */
1807 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1808 /* disable input for TX port IF */
1809 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1810
a22f0788
YR		 1811 link_up = bp->link_vars.link_up;
1812
de0c62db
DK		 1813 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1814 bnx2x_nic_load(bp, LOAD_DIAG);
1815 /* wait until link state is restored */
a22f0788 1816 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1817
1818 if (bnx2x_test_registers(bp) != 0) {
1819 buf[0] = 1;
1820 etest->flags |= ETH_TEST_FL_FAILED;
1821 }
1822 if (bnx2x_test_memory(bp) != 0) {
1823 buf[1] = 1;
1824 etest->flags |= ETH_TEST_FL_FAILED;
1825 }
f85582f8 1826
de0c62db
DK		 1827 buf[2] = bnx2x_test_loopback(bp, link_up);
1828 if (buf[2] != 0)
1829 etest->flags |= ETH_TEST_FL_FAILED;
1830
1831 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1832
1833 /* restore input for TX port IF */
1834 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1835
1836 bnx2x_nic_load(bp, LOAD_NORMAL);
1837 /* wait until link state is restored */
a22f0788 1838 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1839 }
1840 if (bnx2x_test_nvram(bp) != 0) {
1841 buf[3] = 1;
1842 etest->flags |= ETH_TEST_FL_FAILED;
1843 }
1844 if (bnx2x_test_intr(bp) != 0) {
1845 buf[4] = 1;
1846 etest->flags |= ETH_TEST_FL_FAILED;
1847 }
633ac363
DK		 1848
1849 if (bnx2x_link_test(bp, is_serdes) != 0) {
1850 buf[5] = 1;
1851 etest->flags |= ETH_TEST_FL_FAILED;
1852 }
de0c62db
DK		 1853
1854#ifdef BNX2X_EXTRA_DEBUG
1855 bnx2x_panic_dump(bp);
1856#endif
1857}
1858
de0c62db
DK		 1859#define IS_PORT_STAT(i) \
1860 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1861#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 1862#define IS_MF_MODE_STAT(bp) \
1863 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db
DK		 1864
1865static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1866{
1867 struct bnx2x *bp = netdev_priv(dev);
1868 int i, num_stats;
1869
1870 switch (stringset) {
1871 case ETH_SS_STATS:
1872 if (is_multi(bp)) {
ec6ba945
VZ		 1873 num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1874 BNX2X_NUM_Q_STATS;
fb3bff17 1875 if (!IS_MF_MODE_STAT(bp))
de0c62db
DK		 1876 num_stats += BNX2X_NUM_STATS;
1877 } else {
fb3bff17 1878 if (IS_MF_MODE_STAT(bp)) {
de0c62db
DK		 1879 num_stats = 0;
1880 for (i = 0; i < BNX2X_NUM_STATS; i++)
1881 if (IS_FUNC_STAT(i))
1882 num_stats++;
1883 } else
1884 num_stats = BNX2X_NUM_STATS;
1885 }
1886 return num_stats;
1887
1888 case ETH_SS_TEST:
1889 return BNX2X_NUM_TESTS;
1890
1891 default:
1892 return -EINVAL;
1893 }
1894}
1895
1896static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1897{
1898 struct bnx2x *bp = netdev_priv(dev);
1899 int i, j, k;
ec6ba945 1900 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 1901
1902 switch (stringset) {
1903 case ETH_SS_STATS:
1904 if (is_multi(bp)) {
1905 k = 0;
ec6ba945
VZ		 1906 for_each_napi_queue(bp, i) {
1907 memset(queue_name, 0, sizeof(queue_name));
1908
1909 if (IS_FCOE_IDX(i))
1910 sprintf(queue_name, "fcoe");
1911 else
1912 sprintf(queue_name, "%d", i);
1913
de0c62db 1914 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 1915 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
1916 ETH_GSTRING_LEN,
1917 bnx2x_q_stats_arr[j].string,
1918 queue_name);
de0c62db
DK		 1919 k += BNX2X_NUM_Q_STATS;
1920 }
fb3bff17 1921 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 1922 break;
1923 for (j = 0; j < BNX2X_NUM_STATS; j++)
1924 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1925 bnx2x_stats_arr[j].string);
1926 } else {
1927 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 1928 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 1929 continue;
1930 strcpy(buf + j*ETH_GSTRING_LEN,
1931 bnx2x_stats_arr[i].string);
1932 j++;
1933 }
1934 }
1935 break;
1936
1937 case ETH_SS_TEST:
1938 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1939 break;
1940 }
1941}
1942
1943static void bnx2x_get_ethtool_stats(struct net_device *dev,
1944 struct ethtool_stats *stats, u64 *buf)
1945{
1946 struct bnx2x *bp = netdev_priv(dev);
1947 u32 *hw_stats, *offset;
1948 int i, j, k;
1949
1950 if (is_multi(bp)) {
1951 k = 0;
ec6ba945 1952 for_each_napi_queue(bp, i) {
de0c62db
DK		 1953 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1954 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1955 if (bnx2x_q_stats_arr[j].size == 0) {
1956 /* skip this counter */
1957 buf[k + j] = 0;
1958 continue;
1959 }
1960 offset = (hw_stats +
1961 bnx2x_q_stats_arr[j].offset);
1962 if (bnx2x_q_stats_arr[j].size == 4) {
1963 /* 4-byte counter */
1964 buf[k + j] = (u64) *offset;
1965 continue;
1966 }
1967 /* 8-byte counter */
1968 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1969 }
1970 k += BNX2X_NUM_Q_STATS;
1971 }
fb3bff17 1972 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 1973 return;
1974 hw_stats = (u32 *)&bp->eth_stats;
1975 for (j = 0; j < BNX2X_NUM_STATS; j++) {
1976 if (bnx2x_stats_arr[j].size == 0) {
1977 /* skip this counter */
1978 buf[k + j] = 0;
1979 continue;
1980 }
1981 offset = (hw_stats + bnx2x_stats_arr[j].offset);
1982 if (bnx2x_stats_arr[j].size == 4) {
1983 /* 4-byte counter */
1984 buf[k + j] = (u64) *offset;
1985 continue;
1986 }
1987 /* 8-byte counter */
1988 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1989 }
1990 } else {
1991 hw_stats = (u32 *)&bp->eth_stats;
1992 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 1993 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 1994 continue;
1995 if (bnx2x_stats_arr[i].size == 0) {
1996 /* skip this counter */
1997 buf[j] = 0;
1998 j++;
1999 continue;
2000 }
2001 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2002 if (bnx2x_stats_arr[i].size == 4) {
2003 /* 4-byte counter */
2004 buf[j] = (u64) *offset;
2005 j++;
2006 continue;
2007 }
2008 /* 8-byte counter */
2009 buf[j] = HILO_U64(*offset, *(offset + 1));
2010 j++;
2011 }
2012 }
2013}
2014
32d36134 2015static int bnx2x_set_phys_id(struct net_device *dev,
2016 enum ethtool_phys_id_state state)
de0c62db
DK		 2017{
2018 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 2019
2020 if (!netif_running(dev))
32d36134 2021 return -EAGAIN;
de0c62db
DK		 2022
2023 if (!bp->port.pmf)
32d36134 2024 return -EOPNOTSUPP;
de0c62db 2025
32d36134 2026 switch (state) {
2027 case ETHTOOL_ID_ACTIVE:
fce55922 2028 return 1; /* cycle on/off once per second */
de0c62db 2029
32d36134 2030 case ETHTOOL_ID_ON:
2031 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2032 LED_MODE_OPER, SPEED_1000);
2033 break;
de0c62db 2034
32d36134 2035 case ETHTOOL_ID_OFF:
2036 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2037 LED_MODE_OFF, 0);
de0c62db 2038
32d36134 2039 break;
2040
2041 case ETHTOOL_ID_INACTIVE:
2042 if (bp->link_vars.link_up)
2043 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2044 LED_MODE_OPER,
2045 bp->link_vars.line_speed);
2046 }
de0c62db
DK		 2047
2048 return 0;
2049}
2050
ab532cf3
TH		 2051static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2052 void *rules __always_unused)
2053{
2054 struct bnx2x *bp = netdev_priv(dev);
2055
2056 switch (info->cmd) {
2057 case ETHTOOL_GRXRINGS:
2058 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2059 return 0;
2060
2061 default:
2062 return -EOPNOTSUPP;
2063 }
2064}
2065
2066static int bnx2x_get_rxfh_indir(struct net_device *dev,
2067 struct ethtool_rxfh_indir *indir)
2068{
2069 struct bnx2x *bp = netdev_priv(dev);
2070 size_t copy_size =
2071 min_t(size_t, indir->size, TSTORM_INDIRECTION_TABLE_SIZE);
2072
2073 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2074 return -EOPNOTSUPP;
2075
2076 indir->size = TSTORM_INDIRECTION_TABLE_SIZE;
2077 memcpy(indir->ring_index, bp->rx_indir_table,
2078 copy_size * sizeof(bp->rx_indir_table[0]));
2079 return 0;
2080}
2081
2082static int bnx2x_set_rxfh_indir(struct net_device *dev,
2083 const struct ethtool_rxfh_indir *indir)
2084{
2085 struct bnx2x *bp = netdev_priv(dev);
2086 size_t i;
2087
2088 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2089 return -EOPNOTSUPP;
2090
2091 /* Validate size and indices */
2092 if (indir->size != TSTORM_INDIRECTION_TABLE_SIZE)
2093 return -EINVAL;
2094 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
2095 if (indir->ring_index[i] >= BNX2X_NUM_ETH_QUEUES(bp))
2096 return -EINVAL;
2097
2098 memcpy(bp->rx_indir_table, indir->ring_index,
2099 indir->size * sizeof(bp->rx_indir_table[0]));
2100 bnx2x_push_indir_table(bp);
2101 return 0;
2102}
2103
de0c62db
DK		 2104static const struct ethtool_ops bnx2x_ethtool_ops = {
2105 .get_settings = bnx2x_get_settings,
2106 .set_settings = bnx2x_set_settings,
2107 .get_drvinfo = bnx2x_get_drvinfo,
2108 .get_regs_len = bnx2x_get_regs_len,
2109 .get_regs = bnx2x_get_regs,
2110 .get_wol = bnx2x_get_wol,
2111 .set_wol = bnx2x_set_wol,
2112 .get_msglevel = bnx2x_get_msglevel,
2113 .set_msglevel = bnx2x_set_msglevel,
2114 .nway_reset = bnx2x_nway_reset,
2115 .get_link = bnx2x_get_link,
2116 .get_eeprom_len = bnx2x_get_eeprom_len,
2117 .get_eeprom = bnx2x_get_eeprom,
2118 .set_eeprom = bnx2x_set_eeprom,
2119 .get_coalesce = bnx2x_get_coalesce,
2120 .set_coalesce = bnx2x_set_coalesce,
2121 .get_ringparam = bnx2x_get_ringparam,
2122 .set_ringparam = bnx2x_set_ringparam,
2123 .get_pauseparam = bnx2x_get_pauseparam,
2124 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2125 .self_test = bnx2x_self_test,
2126 .get_sset_count = bnx2x_get_sset_count,
2127 .get_strings = bnx2x_get_strings,
32d36134 2128 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2129 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3
TH		 2130 .get_rxnfc = bnx2x_get_rxnfc,
2131 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2132 .set_rxfh_indir = bnx2x_set_rxfh_indir,
de0c62db
DK		 2133};
2134
2135void bnx2x_set_ethtool_ops(struct net_device *netdev)
2136{
2137 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2138}
kernel source for telekom puls (alcatel/mediatek)