projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: fix nla_policy_len to actually _iterate_ over the policy
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/crc32.h>
22
23
24#include "bnx2x.h"
25#include "bnx2x_cmn.h"
26#include "bnx2x_dump.h"
4a33bc03 27#include "bnx2x_init.h"
de0c62db 28
ec6ba945
VZ		 29/* Note: in the format strings below %s is replaced by the queue-name which is
30 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
31 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
32 */
33#define MAX_QUEUE_NAME_LEN 4
34static const struct {
35 long offset;
36 int size;
37 char string[ETH_GSTRING_LEN];
38} bnx2x_q_stats_arr[] = {
39/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
40 { Q_STATS_OFFSET32(error_bytes_received_hi),
41 8, "[%s]: rx_error_bytes" },
42 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
43 8, "[%s]: rx_ucast_packets" },
44 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
45 8, "[%s]: rx_mcast_packets" },
46 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
47 8, "[%s]: rx_bcast_packets" },
48 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
49 { Q_STATS_OFFSET32(rx_err_discard_pkt),
50 4, "[%s]: rx_phy_ip_err_discards"},
51 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
52 4, "[%s]: rx_skb_alloc_discard" },
53 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
54
55/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
56 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
57 8, "[%s]: tx_ucast_packets" },
58 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
59 8, "[%s]: tx_mcast_packets" },
60 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
61 8, "[%s]: tx_bcast_packets" }
62};
63
64#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
65
66static const struct {
67 long offset;
68 int size;
69 u32 flags;
70#define STATS_FLAGS_PORT 1
71#define STATS_FLAGS_FUNC 2
72#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
73 char string[ETH_GSTRING_LEN];
74} bnx2x_stats_arr[] = {
75/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
76 8, STATS_FLAGS_BOTH, "rx_bytes" },
77 { STATS_OFFSET32(error_bytes_received_hi),
78 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
79 { STATS_OFFSET32(total_unicast_packets_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
81 { STATS_OFFSET32(total_multicast_packets_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
83 { STATS_OFFSET32(total_broadcast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
85 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
86 8, STATS_FLAGS_PORT, "rx_crc_errors" },
87 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
88 8, STATS_FLAGS_PORT, "rx_align_errors" },
89 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
90 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
91 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
92 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
93/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
94 8, STATS_FLAGS_PORT, "rx_fragments" },
95 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
96 8, STATS_FLAGS_PORT, "rx_jabbers" },
97 { STATS_OFFSET32(no_buff_discard_hi),
98 8, STATS_FLAGS_BOTH, "rx_discards" },
99 { STATS_OFFSET32(mac_filter_discard),
100 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
101 { STATS_OFFSET32(xxoverflow_discard),
102 4, STATS_FLAGS_PORT, "rx_fw_discards" },
103 { STATS_OFFSET32(brb_drop_hi),
104 8, STATS_FLAGS_PORT, "rx_brb_discard" },
105 { STATS_OFFSET32(brb_truncate_hi),
106 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
107 { STATS_OFFSET32(pause_frames_received_hi),
108 8, STATS_FLAGS_PORT, "rx_pause_frames" },
109 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
110 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
111 { STATS_OFFSET32(nig_timer_max),
112 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
113/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
114 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
115 { STATS_OFFSET32(rx_skb_alloc_failed),
116 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
117 { STATS_OFFSET32(hw_csum_err),
118 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
119
120 { STATS_OFFSET32(total_bytes_transmitted_hi),
121 8, STATS_FLAGS_BOTH, "tx_bytes" },
122 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
123 8, STATS_FLAGS_PORT, "tx_error_bytes" },
124 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
126 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
127 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
128 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
130 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
131 8, STATS_FLAGS_PORT, "tx_mac_errors" },
132 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
133 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
134/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
135 8, STATS_FLAGS_PORT, "tx_single_collisions" },
136 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
137 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
138 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
139 8, STATS_FLAGS_PORT, "tx_deferred" },
140 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
141 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
143 8, STATS_FLAGS_PORT, "tx_late_collisions" },
144 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_total_collisions" },
146 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
147 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
148 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
149 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
151 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
153 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
154/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
155 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
156 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
157 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
158 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
159 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
160 { STATS_OFFSET32(pause_frames_sent_hi),
161 8, STATS_FLAGS_PORT, "tx_pause_frames" }
162};
163
164#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
165
de0c62db
DK		 166static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
167{
168 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 169 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
170 /* Dual Media boards present all available port types */
171 cmd->supported = bp->port.supported[cfg_idx] |
172 (bp->port.supported[cfg_idx ^ 1] &
173 (SUPPORTED_TP | SUPPORTED_FIBRE));
174 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db
DK		 175
176 if ((bp->state == BNX2X_STATE_OPEN) &&
177 !(bp->flags & MF_FUNC_DIS) &&
178 (bp->link_vars.link_up)) {
179 cmd->speed = bp->link_vars.line_speed;
180 cmd->duplex = bp->link_vars.duplex;
de0c62db 181 } else {
f2e0899f 182
a22f0788
YR		 183 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
184 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
de0c62db 185 }
f2e0899f 186
0793f83f
DK		 187 if (IS_MF(bp))
188 cmd->speed = bnx2x_get_mf_speed(bp);
de0c62db 189
a22f0788
YR		 190 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
191 cmd->port = PORT_TP;
192 else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
193 cmd->port = PORT_FIBRE;
194 else
195 BNX2X_ERR("XGXS PHY Failure detected\n");
196
de0c62db
DK		 197 cmd->phy_address = bp->mdio.prtad;
198 cmd->transceiver = XCVR_INTERNAL;
199
a22f0788 200 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 201 cmd->autoneg = AUTONEG_ENABLE;
202 else
203 cmd->autoneg = AUTONEG_DISABLE;
204
205 cmd->maxtxpkt = 0;
206 cmd->maxrxpkt = 0;
207
208 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
209 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
210 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
211 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
212 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
213 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
214 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
215
216 return 0;
217}
218
219static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
220{
221 struct bnx2x *bp = netdev_priv(dev);
a22f0788 222 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 223 u32 speed;
de0c62db 224
0793f83f 225 if (IS_MF_SD(bp))
de0c62db
DK		 226 return 0;
227
228 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
0793f83f
DK		 229 " supported 0x%x advertising 0x%x speed %d speed_hi %d\n"
230 " duplex %d port %d phy_address %d transceiver %d\n"
231 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
de0c62db 232 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
0793f83f 233 cmd->speed_hi,
de0c62db
DK		 234 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
235 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
236
0793f83f
DK		 237 speed = cmd->speed;
238 speed |= (cmd->speed_hi << 16);
239
240 if (IS_MF_SI(bp)) {
241 u32 param = 0;
242 u32 line_speed = bp->link_vars.line_speed;
243
244 /* use 10G if no link detected */
245 if (!line_speed)
246 line_speed = 10000;
247
248 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
249 BNX2X_DEV_INFO("To set speed BC %X or higher "
250 "is required, please upgrade BC\n",
251 REQ_BC_VER_4_SET_MF_BW);
252 return -EINVAL;
253 }
254 if (line_speed < speed) {
255 BNX2X_DEV_INFO("New speed should be less or equal "
256 "to actual line speed\n");
257 return -EINVAL;
258 }
259 /* load old values */
260 param = bp->mf_config[BP_VN(bp)];
261
262 /* leave only MIN value */
263 param &= FUNC_MF_CFG_MIN_BW_MASK;
264
265 /* set new MAX value */
266 param |= (((speed * 100) / line_speed)
267 << FUNC_MF_CFG_MAX_BW_SHIFT)
268 & FUNC_MF_CFG_MAX_BW_MASK;
269
270 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, param);
271 return 0;
272 }
273
a22f0788
YR		 274 cfg_idx = bnx2x_get_link_cfg_idx(bp);
275 old_multi_phy_config = bp->link_params.multi_phy_config;
276 switch (cmd->port) {
277 case PORT_TP:
278 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
279 break; /* no port change */
280
281 if (!(bp->port.supported[0] & SUPPORTED_TP ||
282 bp->port.supported[1] & SUPPORTED_TP)) {
283 DP(NETIF_MSG_LINK, "Unsupported port type\n");
284 return -EINVAL;
285 }
286 bp->link_params.multi_phy_config &=
287 ~PORT_HW_CFG_PHY_SELECTION_MASK;
288 if (bp->link_params.multi_phy_config &
289 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
290 bp->link_params.multi_phy_config |=
291 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
292 else
293 bp->link_params.multi_phy_config |=
294 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
295 break;
296 case PORT_FIBRE:
297 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
298 break; /* no port change */
299
300 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
301 bp->port.supported[1] & SUPPORTED_FIBRE)) {
302 DP(NETIF_MSG_LINK, "Unsupported port type\n");
303 return -EINVAL;
304 }
305 bp->link_params.multi_phy_config &=
306 ~PORT_HW_CFG_PHY_SELECTION_MASK;
307 if (bp->link_params.multi_phy_config &
308 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
309 bp->link_params.multi_phy_config |=
310 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
311 else
312 bp->link_params.multi_phy_config |=
313 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
314 break;
315 default:
316 DP(NETIF_MSG_LINK, "Unsupported port type\n");
317 return -EINVAL;
318 }
319 /* Save new config in case command complete successuly */
320 new_multi_phy_config = bp->link_params.multi_phy_config;
321 /* Get the new cfg_idx */
322 cfg_idx = bnx2x_get_link_cfg_idx(bp);
323 /* Restore old config in case command failed */
324 bp->link_params.multi_phy_config = old_multi_phy_config;
325 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
326
de0c62db 327 if (cmd->autoneg == AUTONEG_ENABLE) {
a22f0788 328 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 329 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
330 return -EINVAL;
331 }
332
333 /* advertise the requested speed and duplex if supported */
a22f0788 334 cmd->advertising &= bp->port.supported[cfg_idx];
de0c62db 335
a22f0788
YR		 336 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
337 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
338 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
de0c62db
DK		 339 cmd->advertising);
340
341 } else { /* forced speed */
342 /* advertise the requested speed and duplex if supported */
a22f0788 343 switch (speed) {
de0c62db
DK		 344 case SPEED_10:
345 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 346 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 347 SUPPORTED_10baseT_Full)) {
348 DP(NETIF_MSG_LINK,
349 "10M full not supported\n");
350 return -EINVAL;
351 }
352
353 advertising = (ADVERTISED_10baseT_Full |
354 ADVERTISED_TP);
355 } else {
a22f0788 356 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 357 SUPPORTED_10baseT_Half)) {
358 DP(NETIF_MSG_LINK,
359 "10M half not supported\n");
360 return -EINVAL;
361 }
362
363 advertising = (ADVERTISED_10baseT_Half |
364 ADVERTISED_TP);
365 }
366 break;
367
368 case SPEED_100:
369 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 370 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 371 SUPPORTED_100baseT_Full)) {
372 DP(NETIF_MSG_LINK,
373 "100M full not supported\n");
374 return -EINVAL;
375 }
376
377 advertising = (ADVERTISED_100baseT_Full |
378 ADVERTISED_TP);
379 } else {
a22f0788 380 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 381 SUPPORTED_100baseT_Half)) {
382 DP(NETIF_MSG_LINK,
383 "100M half not supported\n");
384 return -EINVAL;
385 }
386
387 advertising = (ADVERTISED_100baseT_Half |
388 ADVERTISED_TP);
389 }
390 break;
391
392 case SPEED_1000:
393 if (cmd->duplex != DUPLEX_FULL) {
394 DP(NETIF_MSG_LINK, "1G half not supported\n");
395 return -EINVAL;
396 }
397
a22f0788
YR		 398 if (!(bp->port.supported[cfg_idx] &
399 SUPPORTED_1000baseT_Full)) {
de0c62db
DK		 400 DP(NETIF_MSG_LINK, "1G full not supported\n");
401 return -EINVAL;
402 }
403
404 advertising = (ADVERTISED_1000baseT_Full |
405 ADVERTISED_TP);
406 break;
407
408 case SPEED_2500:
409 if (cmd->duplex != DUPLEX_FULL) {
410 DP(NETIF_MSG_LINK,
411 "2.5G half not supported\n");
412 return -EINVAL;
413 }
414
a22f0788
YR		 415 if (!(bp->port.supported[cfg_idx]
416 & SUPPORTED_2500baseX_Full)) {
de0c62db
DK		 417 DP(NETIF_MSG_LINK,
418 "2.5G full not supported\n");
419 return -EINVAL;
420 }
421
422 advertising = (ADVERTISED_2500baseX_Full |
423 ADVERTISED_TP);
424 break;
425
426 case SPEED_10000:
427 if (cmd->duplex != DUPLEX_FULL) {
428 DP(NETIF_MSG_LINK, "10G half not supported\n");
429 return -EINVAL;
430 }
431
a22f0788
YR		 432 if (!(bp->port.supported[cfg_idx]
433 & SUPPORTED_10000baseT_Full)) {
de0c62db
DK		 434 DP(NETIF_MSG_LINK, "10G full not supported\n");
435 return -EINVAL;
436 }
437
438 advertising = (ADVERTISED_10000baseT_Full |
439 ADVERTISED_FIBRE);
440 break;
441
442 default:
a22f0788 443 DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed);
de0c62db
DK		 444 return -EINVAL;
445 }
446
a22f0788
YR		 447 bp->link_params.req_line_speed[cfg_idx] = speed;
448 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
449 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 450 }
451
452 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
453 DP_LEVEL " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 454 bp->link_params.req_line_speed[cfg_idx],
455 bp->link_params.req_duplex[cfg_idx],
456 bp->port.advertising[cfg_idx]);
de0c62db 457
a22f0788
YR		 458 /* Set new config */
459 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 460 if (netif_running(dev)) {
461 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
462 bnx2x_link_set(bp);
463 }
464
465 return 0;
466}
467
468#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
469#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 470#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
de0c62db
DK		 471
472static int bnx2x_get_regs_len(struct net_device *dev)
473{
474 struct bnx2x *bp = netdev_priv(dev);
475 int regdump_len = 0;
4a33bc03 476 int i, j, k;
de0c62db
DK		 477
478 if (CHIP_IS_E1(bp)) {
479 for (i = 0; i < REGS_COUNT; i++)
480 if (IS_E1_ONLINE(reg_addrs[i].info))
481 regdump_len += reg_addrs[i].size;
482
483 for (i = 0; i < WREGS_COUNT_E1; i++)
484 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
485 regdump_len += wreg_addrs_e1[i].size *
486 (1 + wreg_addrs_e1[i].read_regs_count);
487
f2e0899f 488 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 489 for (i = 0; i < REGS_COUNT; i++)
490 if (IS_E1H_ONLINE(reg_addrs[i].info))
491 regdump_len += reg_addrs[i].size;
492
493 for (i = 0; i < WREGS_COUNT_E1H; i++)
494 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
495 regdump_len += wreg_addrs_e1h[i].size *
496 (1 + wreg_addrs_e1h[i].read_regs_count);
f2e0899f
DK		 497 } else if (CHIP_IS_E2(bp)) {
498 for (i = 0; i < REGS_COUNT; i++)
499 if (IS_E2_ONLINE(reg_addrs[i].info))
500 regdump_len += reg_addrs[i].size;
501
502 for (i = 0; i < WREGS_COUNT_E2; i++)
503 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
504 regdump_len += wreg_addrs_e2[i].size *
505 (1 + wreg_addrs_e2[i].read_regs_count);
4a33bc03
VZ		 506
507 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
508 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
509 for (k = 0; k < PAGE_READ_REGS_E2; k++)
510 if (IS_E2_ONLINE(page_read_regs_e2[k].
511 info))
512 regdump_len +=
513 page_read_regs_e2[k].size;
514 }
de0c62db
DK		 515 }
516 regdump_len *= 4;
517 regdump_len += sizeof(struct dump_hdr);
518
519 return regdump_len;
520}
521
f2e0899f
DK		 522static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
523{
524 u32 i, j, k, n;
525
526 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
527 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
528 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
529 for (k = 0; k < PAGE_READ_REGS_E2; k++)
530 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
531 for (n = 0; n <
532 page_read_regs_e2[k].size; n++)
533 *p++ = REG_RD(bp,
534 page_read_regs_e2[k].addr + n*4);
535 }
536 }
537}
538
de0c62db
DK		 539static void bnx2x_get_regs(struct net_device *dev,
540 struct ethtool_regs *regs, void *_p)
541{
542 u32 *p = _p, i, j;
543 struct bnx2x *bp = netdev_priv(dev);
544 struct dump_hdr dump_hdr = {0};
545
546 regs->version = 0;
547 memset(p, 0, regs->len);
548
549 if (!netif_running(bp->dev))
550 return;
551
4a33bc03
VZ		 552 /* Disable parity attentions as long as following dump may
553 * cause false alarms by reading never written registers. We
554 * will re-enable parity attentions right after the dump.
555 */
556 bnx2x_disable_blocks_parity(bp);
557
de0c62db
DK		 558 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
559 dump_hdr.dump_sign = dump_sign_all;
560 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
561 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
562 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
563 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 564
565 if (CHIP_IS_E1(bp))
566 dump_hdr.info = RI_E1_ONLINE;
567 else if (CHIP_IS_E1H(bp))
568 dump_hdr.info = RI_E1H_ONLINE;
569 else if (CHIP_IS_E2(bp))
570 dump_hdr.info = RI_E2_ONLINE |
571 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 572
573 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
574 p += dump_hdr.hdr_size + 1;
575
576 if (CHIP_IS_E1(bp)) {
577 for (i = 0; i < REGS_COUNT; i++)
578 if (IS_E1_ONLINE(reg_addrs[i].info))
579 for (j = 0; j < reg_addrs[i].size; j++)
580 *p++ = REG_RD(bp,
581 reg_addrs[i].addr + j*4);
582
f2e0899f 583 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 584 for (i = 0; i < REGS_COUNT; i++)
585 if (IS_E1H_ONLINE(reg_addrs[i].info))
586 for (j = 0; j < reg_addrs[i].size; j++)
587 *p++ = REG_RD(bp,
588 reg_addrs[i].addr + j*4);
f2e0899f
DK		 589
590 } else if (CHIP_IS_E2(bp)) {
591 for (i = 0; i < REGS_COUNT; i++)
592 if (IS_E2_ONLINE(reg_addrs[i].info))
593 for (j = 0; j < reg_addrs[i].size; j++)
594 *p++ = REG_RD(bp,
595 reg_addrs[i].addr + j*4);
596
597 bnx2x_read_pages_regs_e2(bp, p);
de0c62db 598 }
4a33bc03
VZ		 599 /* Re-enable parity attentions */
600 bnx2x_clear_blocks_parity(bp);
601 if (CHIP_PARITY_ENABLED(bp))
602 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 603}
604
f2e0899f 605#define PHY_FW_VER_LEN 20
de0c62db
DK		 606
607static void bnx2x_get_drvinfo(struct net_device *dev,
608 struct ethtool_drvinfo *info)
609{
610 struct bnx2x *bp = netdev_priv(dev);
611 u8 phy_fw_ver[PHY_FW_VER_LEN];
612
613 strcpy(info->driver, DRV_MODULE_NAME);
614 strcpy(info->version, DRV_MODULE_VERSION);
615
616 phy_fw_ver[0] = '\0';
617 if (bp->port.pmf) {
618 bnx2x_acquire_phy_lock(bp);
619 bnx2x_get_ext_phy_fw_version(&bp->link_params,
620 (bp->state != BNX2X_STATE_CLOSED),
621 phy_fw_ver, PHY_FW_VER_LEN);
622 bnx2x_release_phy_lock(bp);
623 }
624
625 strncpy(info->fw_version, bp->fw_ver, 32);
626 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
627 "bc %d.%d.%d%s%s",
628 (bp->common.bc_ver & 0xff0000) >> 16,
629 (bp->common.bc_ver & 0xff00) >> 8,
630 (bp->common.bc_ver & 0xff),
631 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
632 strcpy(info->bus_info, pci_name(bp->pdev));
633 info->n_stats = BNX2X_NUM_STATS;
634 info->testinfo_len = BNX2X_NUM_TESTS;
635 info->eedump_len = bp->common.flash_size;
636 info->regdump_len = bnx2x_get_regs_len(dev);
637}
638
639static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
640{
641 struct bnx2x *bp = netdev_priv(dev);
642
643 if (bp->flags & NO_WOL_FLAG) {
644 wol->supported = 0;
645 wol->wolopts = 0;
646 } else {
647 wol->supported = WAKE_MAGIC;
648 if (bp->wol)
649 wol->wolopts = WAKE_MAGIC;
650 else
651 wol->wolopts = 0;
652 }
653 memset(&wol->sopass, 0, sizeof(wol->sopass));
654}
655
656static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
657{
658 struct bnx2x *bp = netdev_priv(dev);
659
660 if (wol->wolopts & ~WAKE_MAGIC)
661 return -EINVAL;
662
663 if (wol->wolopts & WAKE_MAGIC) {
664 if (bp->flags & NO_WOL_FLAG)
665 return -EINVAL;
666
667 bp->wol = 1;
668 } else
669 bp->wol = 0;
670
671 return 0;
672}
673
674static u32 bnx2x_get_msglevel(struct net_device *dev)
675{
676 struct bnx2x *bp = netdev_priv(dev);
677
678 return bp->msg_enable;
679}
680
681static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
682{
683 struct bnx2x *bp = netdev_priv(dev);
684
685 if (capable(CAP_NET_ADMIN))
686 bp->msg_enable = level;
687}
688
689static int bnx2x_nway_reset(struct net_device *dev)
690{
691 struct bnx2x *bp = netdev_priv(dev);
692
693 if (!bp->port.pmf)
694 return 0;
695
696 if (netif_running(dev)) {
697 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
698 bnx2x_link_set(bp);
699 }
700
701 return 0;
702}
703
704static u32 bnx2x_get_link(struct net_device *dev)
705{
706 struct bnx2x *bp = netdev_priv(dev);
707
f2e0899f 708 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 709 return 0;
710
711 return bp->link_vars.link_up;
712}
713
714static int bnx2x_get_eeprom_len(struct net_device *dev)
715{
716 struct bnx2x *bp = netdev_priv(dev);
717
718 return bp->common.flash_size;
719}
720
721static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
722{
723 int port = BP_PORT(bp);
724 int count, i;
725 u32 val = 0;
726
727 /* adjust timeout for emulation/FPGA */
728 count = NVRAM_TIMEOUT_COUNT;
729 if (CHIP_REV_IS_SLOW(bp))
730 count *= 100;
731
732 /* request access to nvram interface */
733 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
734 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
735
736 for (i = 0; i < count*10; i++) {
737 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
738 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
739 break;
740
741 udelay(5);
742 }
743
744 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
745 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
746 return -EBUSY;
747 }
748
749 return 0;
750}
751
752static int bnx2x_release_nvram_lock(struct bnx2x *bp)
753{
754 int port = BP_PORT(bp);
755 int count, i;
756 u32 val = 0;
757
758 /* adjust timeout for emulation/FPGA */
759 count = NVRAM_TIMEOUT_COUNT;
760 if (CHIP_REV_IS_SLOW(bp))
761 count *= 100;
762
763 /* relinquish nvram interface */
764 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
765 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
766
767 for (i = 0; i < count*10; i++) {
768 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
769 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
770 break;
771
772 udelay(5);
773 }
774
775 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
776 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
777 return -EBUSY;
778 }
779
780 return 0;
781}
782
783static void bnx2x_enable_nvram_access(struct bnx2x *bp)
784{
785 u32 val;
786
787 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
788
789 /* enable both bits, even on read */
790 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
791 (val | MCPR_NVM_ACCESS_ENABLE_EN |
792 MCPR_NVM_ACCESS_ENABLE_WR_EN));
793}
794
795static void bnx2x_disable_nvram_access(struct bnx2x *bp)
796{
797 u32 val;
798
799 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
800
801 /* disable both bits, even after read */
802 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
803 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
804 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
805}
806
807static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
808 u32 cmd_flags)
809{
810 int count, i, rc;
811 u32 val;
812
813 /* build the command word */
814 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
815
816 /* need to clear DONE bit separately */
817 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
818
819 /* address of the NVRAM to read from */
820 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
821 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
822
823 /* issue a read command */
824 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
825
826 /* adjust timeout for emulation/FPGA */
827 count = NVRAM_TIMEOUT_COUNT;
828 if (CHIP_REV_IS_SLOW(bp))
829 count *= 100;
830
831 /* wait for completion */
832 *ret_val = 0;
833 rc = -EBUSY;
834 for (i = 0; i < count; i++) {
835 udelay(5);
836 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
837
838 if (val & MCPR_NVM_COMMAND_DONE) {
839 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
840 /* we read nvram data in cpu order
841 * but ethtool sees it as an array of bytes
842 * converting to big-endian will do the work */
843 *ret_val = cpu_to_be32(val);
844 rc = 0;
845 break;
846 }
847 }
848
849 return rc;
850}
851
852static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
853 int buf_size)
854{
855 int rc;
856 u32 cmd_flags;
857 __be32 val;
858
859 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
860 DP(BNX2X_MSG_NVM,
861 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
862 offset, buf_size);
863 return -EINVAL;
864 }
865
866 if (offset + buf_size > bp->common.flash_size) {
867 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
868 " buf_size (0x%x) > flash_size (0x%x)\n",
869 offset, buf_size, bp->common.flash_size);
870 return -EINVAL;
871 }
872
873 /* request access to nvram interface */
874 rc = bnx2x_acquire_nvram_lock(bp);
875 if (rc)
876 return rc;
877
878 /* enable access to nvram interface */
879 bnx2x_enable_nvram_access(bp);
880
881 /* read the first word(s) */
882 cmd_flags = MCPR_NVM_COMMAND_FIRST;
883 while ((buf_size > sizeof(u32)) && (rc == 0)) {
884 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
885 memcpy(ret_buf, &val, 4);
886
887 /* advance to the next dword */
888 offset += sizeof(u32);
889 ret_buf += sizeof(u32);
890 buf_size -= sizeof(u32);
891 cmd_flags = 0;
892 }
893
894 if (rc == 0) {
895 cmd_flags |= MCPR_NVM_COMMAND_LAST;
896 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
897 memcpy(ret_buf, &val, 4);
898 }
899
900 /* disable access to nvram interface */
901 bnx2x_disable_nvram_access(bp);
902 bnx2x_release_nvram_lock(bp);
903
904 return rc;
905}
906
907static int bnx2x_get_eeprom(struct net_device *dev,
908 struct ethtool_eeprom *eeprom, u8 *eebuf)
909{
910 struct bnx2x *bp = netdev_priv(dev);
911 int rc;
912
913 if (!netif_running(dev))
914 return -EAGAIN;
915
916 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
917 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
918 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
919 eeprom->len, eeprom->len);
920
921 /* parameters already validated in ethtool_get_eeprom */
922
923 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
924
925 return rc;
926}
927
928static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
929 u32 cmd_flags)
930{
931 int count, i, rc;
932
933 /* build the command word */
934 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
935
936 /* need to clear DONE bit separately */
937 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
938
939 /* write the data */
940 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
941
942 /* address of the NVRAM to write to */
943 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
944 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
945
946 /* issue the write command */
947 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
948
949 /* adjust timeout for emulation/FPGA */
950 count = NVRAM_TIMEOUT_COUNT;
951 if (CHIP_REV_IS_SLOW(bp))
952 count *= 100;
953
954 /* wait for completion */
955 rc = -EBUSY;
956 for (i = 0; i < count; i++) {
957 udelay(5);
958 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
959 if (val & MCPR_NVM_COMMAND_DONE) {
960 rc = 0;
961 break;
962 }
963 }
964
965 return rc;
966}
967
968#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
969
970static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
971 int buf_size)
972{
973 int rc;
974 u32 cmd_flags;
975 u32 align_offset;
976 __be32 val;
977
978 if (offset + buf_size > bp->common.flash_size) {
979 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
980 " buf_size (0x%x) > flash_size (0x%x)\n",
981 offset, buf_size, bp->common.flash_size);
982 return -EINVAL;
983 }
984
985 /* request access to nvram interface */
986 rc = bnx2x_acquire_nvram_lock(bp);
987 if (rc)
988 return rc;
989
990 /* enable access to nvram interface */
991 bnx2x_enable_nvram_access(bp);
992
993 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
994 align_offset = (offset & ~0x03);
995 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
996
997 if (rc == 0) {
998 val &= ~(0xff << BYTE_OFFSET(offset));
999 val |= (*data_buf << BYTE_OFFSET(offset));
1000
1001 /* nvram data is returned as an array of bytes
1002 * convert it back to cpu order */
1003 val = be32_to_cpu(val);
1004
1005 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1006 cmd_flags);
1007 }
1008
1009 /* disable access to nvram interface */
1010 bnx2x_disable_nvram_access(bp);
1011 bnx2x_release_nvram_lock(bp);
1012
1013 return rc;
1014}
1015
1016static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1017 int buf_size)
1018{
1019 int rc;
1020 u32 cmd_flags;
1021 u32 val;
1022 u32 written_so_far;
1023
1024 if (buf_size == 1) /* ethtool */
1025 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1026
1027 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1028 DP(BNX2X_MSG_NVM,
1029 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1030 offset, buf_size);
1031 return -EINVAL;
1032 }
1033
1034 if (offset + buf_size > bp->common.flash_size) {
1035 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1036 " buf_size (0x%x) > flash_size (0x%x)\n",
1037 offset, buf_size, bp->common.flash_size);
1038 return -EINVAL;
1039 }
1040
1041 /* request access to nvram interface */
1042 rc = bnx2x_acquire_nvram_lock(bp);
1043 if (rc)
1044 return rc;
1045
1046 /* enable access to nvram interface */
1047 bnx2x_enable_nvram_access(bp);
1048
1049 written_so_far = 0;
1050 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1051 while ((written_so_far < buf_size) && (rc == 0)) {
1052 if (written_so_far == (buf_size - sizeof(u32)))
1053 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1054 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1055 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1056 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1057 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1058
1059 memcpy(&val, data_buf, 4);
1060
1061 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1062
1063 /* advance to the next dword */
1064 offset += sizeof(u32);
1065 data_buf += sizeof(u32);
1066 written_so_far += sizeof(u32);
1067 cmd_flags = 0;
1068 }
1069
1070 /* disable access to nvram interface */
1071 bnx2x_disable_nvram_access(bp);
1072 bnx2x_release_nvram_lock(bp);
1073
1074 return rc;
1075}
1076
1077static int bnx2x_set_eeprom(struct net_device *dev,
1078 struct ethtool_eeprom *eeprom, u8 *eebuf)
1079{
1080 struct bnx2x *bp = netdev_priv(dev);
1081 int port = BP_PORT(bp);
1082 int rc = 0;
e10bc84d 1083 u32 ext_phy_config;
de0c62db
DK		 1084 if (!netif_running(dev))
1085 return -EAGAIN;
1086
1087 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1088 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1089 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1090 eeprom->len, eeprom->len);
1091
1092 /* parameters already validated in ethtool_set_eeprom */
1093
1094 /* PHY eeprom can be accessed only by the PMF */
1095 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1096 !bp->port.pmf)
1097 return -EINVAL;
1098
e10bc84d
YR		 1099 ext_phy_config =
1100 SHMEM_RD(bp,
1101 dev_info.port_hw_config[port].external_phy_config);
1102
de0c62db
DK		 1103 if (eeprom->magic == 0x50485950) {
1104 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1105 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1106
1107 bnx2x_acquire_phy_lock(bp);
1108 rc |= bnx2x_link_reset(&bp->link_params,
1109 &bp->link_vars, 0);
e10bc84d 1110 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1111 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1112 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1113 MISC_REGISTERS_GPIO_HIGH, port);
1114 bnx2x_release_phy_lock(bp);
1115 bnx2x_link_report(bp);
1116
1117 } else if (eeprom->magic == 0x50485952) {
1118 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1119 if (bp->state == BNX2X_STATE_OPEN) {
1120 bnx2x_acquire_phy_lock(bp);
1121 rc |= bnx2x_link_reset(&bp->link_params,
1122 &bp->link_vars, 1);
1123
1124 rc |= bnx2x_phy_init(&bp->link_params,
1125 &bp->link_vars);
1126 bnx2x_release_phy_lock(bp);
1127 bnx2x_calc_fc_adv(bp);
1128 }
1129 } else if (eeprom->magic == 0x53985943) {
1130 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1131 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1132 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1133
1134 /* DSP Remove Download Mode */
1135 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1136 MISC_REGISTERS_GPIO_LOW, port);
1137
1138 bnx2x_acquire_phy_lock(bp);
1139
e10bc84d
YR		 1140 bnx2x_sfx7101_sp_sw_reset(bp,
1141 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1142
1143 /* wait 0.5 sec to allow it to run */
1144 msleep(500);
1145 bnx2x_ext_phy_hw_reset(bp, port);
1146 msleep(500);
1147 bnx2x_release_phy_lock(bp);
1148 }
1149 } else
1150 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1151
1152 return rc;
1153}
f85582f8 1154
de0c62db
DK		 1155static int bnx2x_get_coalesce(struct net_device *dev,
1156 struct ethtool_coalesce *coal)
1157{
1158 struct bnx2x *bp = netdev_priv(dev);
1159
1160 memset(coal, 0, sizeof(struct ethtool_coalesce));
1161
1162 coal->rx_coalesce_usecs = bp->rx_ticks;
1163 coal->tx_coalesce_usecs = bp->tx_ticks;
1164
1165 return 0;
1166}
1167
1168static int bnx2x_set_coalesce(struct net_device *dev,
1169 struct ethtool_coalesce *coal)
1170{
1171 struct bnx2x *bp = netdev_priv(dev);
1172
1173 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1174 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1175 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1176
1177 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1178 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1179 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1180
1181 if (netif_running(dev))
1182 bnx2x_update_coalesce(bp);
1183
1184 return 0;
1185}
1186
1187static void bnx2x_get_ringparam(struct net_device *dev,
1188 struct ethtool_ringparam *ering)
1189{
1190 struct bnx2x *bp = netdev_priv(dev);
1191
1192 ering->rx_max_pending = MAX_RX_AVAIL;
1193 ering->rx_mini_max_pending = 0;
1194 ering->rx_jumbo_max_pending = 0;
1195
25141580
DK		 1196 if (bp->rx_ring_size)
1197 ering->rx_pending = bp->rx_ring_size;
1198 else
1199 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1200 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1201 else
1202 ering->rx_pending = MAX_RX_AVAIL;
1203
de0c62db
DK		 1204 ering->rx_mini_pending = 0;
1205 ering->rx_jumbo_pending = 0;
1206
1207 ering->tx_max_pending = MAX_TX_AVAIL;
1208 ering->tx_pending = bp->tx_ring_size;
1209}
1210
1211static int bnx2x_set_ringparam(struct net_device *dev,
1212 struct ethtool_ringparam *ering)
1213{
1214 struct bnx2x *bp = netdev_priv(dev);
1215 int rc = 0;
1216
1217 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1218 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1219 return -EAGAIN;
1220 }
1221
1222 if ((ering->rx_pending > MAX_RX_AVAIL) ||
25141580 1223 (ering->rx_pending < MIN_RX_AVAIL) ||
de0c62db
DK		 1224 (ering->tx_pending > MAX_TX_AVAIL) ||
1225 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1226 return -EINVAL;
1227
1228 bp->rx_ring_size = ering->rx_pending;
1229 bp->tx_ring_size = ering->tx_pending;
1230
1231 if (netif_running(dev)) {
1232 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1233 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1234 }
1235
1236 return rc;
1237}
1238
1239static void bnx2x_get_pauseparam(struct net_device *dev,
1240 struct ethtool_pauseparam *epause)
1241{
1242 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 1243 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1244 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1245 BNX2X_FLOW_CTRL_AUTO);
de0c62db
DK		 1246
1247 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1248 BNX2X_FLOW_CTRL_RX);
1249 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1250 BNX2X_FLOW_CTRL_TX);
1251
1252 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1253 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1254 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1255}
1256
1257static int bnx2x_set_pauseparam(struct net_device *dev,
1258 struct ethtool_pauseparam *epause)
1259{
1260 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1261 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1262 if (IS_MF(bp))
de0c62db
DK		 1263 return 0;
1264
1265 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1266 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1267 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1268
a22f0788 1269 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1270
1271 if (epause->rx_pause)
a22f0788 1272 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1273
1274 if (epause->tx_pause)
a22f0788 1275 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1276
a22f0788
YR		 1277 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1278 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1279
1280 if (epause->autoneg) {
a22f0788 1281 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 1282 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1283 return -EINVAL;
1284 }
1285
a22f0788
YR		 1286 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1287 bp->link_params.req_flow_ctrl[cfg_idx] =
1288 BNX2X_FLOW_CTRL_AUTO;
1289 }
de0c62db
DK		 1290 }
1291
1292 DP(NETIF_MSG_LINK,
a22f0788 1293 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1294
1295 if (netif_running(dev)) {
1296 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1297 bnx2x_link_set(bp);
1298 }
1299
1300 return 0;
1301}
1302
1303static int bnx2x_set_flags(struct net_device *dev, u32 data)
1304{
1305 struct bnx2x *bp = netdev_priv(dev);
1306 int changed = 0;
1307 int rc = 0;
1308
de0c62db
DK		 1309 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1310 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1311 return -EAGAIN;
1312 }
1313
9bcc0893 1314 if (!(data & ETH_FLAG_RXVLAN))
ec37a48d 1315 return -EINVAL;
9bcc0893
HZ		 1316
1317 if ((data & ETH_FLAG_LRO) && bp->rx_csum && bp->disable_tpa)
1318 return -EINVAL;
1319
1320 rc = ethtool_op_set_flags(dev, data, ETH_FLAG_LRO | ETH_FLAG_RXVLAN |
1321 ETH_FLAG_TXVLAN | ETH_FLAG_RXHASH);
1322 if (rc)
1323 return rc;
1324
de0c62db
DK		 1325 /* TPA requires Rx CSUM offloading */
1326 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
9bcc0893
HZ		 1327 if (!(bp->flags & TPA_ENABLE_FLAG)) {
1328 bp->flags |= TPA_ENABLE_FLAG;
1329 changed = 1;
1330 }
1331 } else if (bp->flags & TPA_ENABLE_FLAG) {
de0c62db
DK		 1332 dev->features &= ~NETIF_F_LRO;
1333 bp->flags &= ~TPA_ENABLE_FLAG;
1334 changed = 1;
1335 }
1336
de0c62db
DK		 1337 if (changed && netif_running(dev)) {
1338 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1339 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1340 }
1341
1342 return rc;
1343}
1344
1345static u32 bnx2x_get_rx_csum(struct net_device *dev)
1346{
1347 struct bnx2x *bp = netdev_priv(dev);
1348
1349 return bp->rx_csum;
1350}
1351
1352static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
1353{
1354 struct bnx2x *bp = netdev_priv(dev);
1355 int rc = 0;
1356
1357 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1358 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1359 return -EAGAIN;
1360 }
1361
1362 bp->rx_csum = data;
1363
1364 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
1365 TPA'ed packets will be discarded due to wrong TCP CSUM */
1366 if (!data) {
1367 u32 flags = ethtool_op_get_flags(dev);
1368
1369 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
1370 }
1371
1372 return rc;
1373}
1374
1375static int bnx2x_set_tso(struct net_device *dev, u32 data)
1376{
1377 if (data) {
1378 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
1379 dev->features |= NETIF_F_TSO6;
1380 } else {
1381 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
1382 dev->features &= ~NETIF_F_TSO6;
1383 }
1384
1385 return 0;
1386}
1387
1388static const struct {
1389 char string[ETH_GSTRING_LEN];
1390} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1391 { "register_test (offline)" },
1392 { "memory_test (offline)" },
1393 { "loopback_test (offline)" },
1394 { "nvram_test (online)" },
1395 { "interrupt_test (online)" },
1396 { "link_test (online)" },
1397 { "idle check (online)" }
1398};
1399
1400static int bnx2x_test_registers(struct bnx2x *bp)
1401{
1402 int idx, i, rc = -ENODEV;
1403 u32 wr_val = 0;
1404 int port = BP_PORT(bp);
1405 static const struct {
1406 u32 offset0;
1407 u32 offset1;
1408 u32 mask;
1409 } reg_tbl[] = {
1410/* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1411 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1412 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1413 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1414 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1415 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1416 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1417 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1418 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1419 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1420/* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1421 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1422 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1423 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1424 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1425 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1426 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1427 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1428 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1429 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1430/* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1431 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1432 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1433 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1434 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1435 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1436 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1437 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1438 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1439 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1440/* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1441 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1442 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1443 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1444 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1445 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1446 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1447
1448 { 0xffffffff, 0, 0x00000000 }
1449 };
1450
1451 if (!netif_running(bp->dev))
1452 return rc;
1453
1454 /* Repeat the test twice:
1455 First by writing 0x00000000, second by writing 0xffffffff */
1456 for (idx = 0; idx < 2; idx++) {
1457
1458 switch (idx) {
1459 case 0:
1460 wr_val = 0;
1461 break;
1462 case 1:
1463 wr_val = 0xffffffff;
1464 break;
1465 }
1466
1467 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1468 u32 offset, mask, save_val, val;
f2e0899f
DK		 1469 if (CHIP_IS_E2(bp) &&
1470 reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1471 continue;
de0c62db
DK		 1472
1473 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1474 mask = reg_tbl[i].mask;
1475
1476 save_val = REG_RD(bp, offset);
1477
ec6ba945 1478 REG_WR(bp, offset, wr_val & mask);
f85582f8 1479
de0c62db
DK		 1480 val = REG_RD(bp, offset);
1481
1482 /* Restore the original register's value */
1483 REG_WR(bp, offset, save_val);
1484
1485 /* verify value is as expected */
1486 if ((val & mask) != (wr_val & mask)) {
1487 DP(NETIF_MSG_PROBE,
1488 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1489 offset, val, wr_val, mask);
1490 goto test_reg_exit;
1491 }
1492 }
1493 }
1494
1495 rc = 0;
1496
1497test_reg_exit:
1498 return rc;
1499}
1500
1501static int bnx2x_test_memory(struct bnx2x *bp)
1502{
1503 int i, j, rc = -ENODEV;
1504 u32 val;
1505 static const struct {
1506 u32 offset;
1507 int size;
1508 } mem_tbl[] = {
1509 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1510 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1511 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1512 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1513 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1514 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1515 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1516
1517 { 0xffffffff, 0 }
1518 };
1519 static const struct {
1520 char *name;
1521 u32 offset;
1522 u32 e1_mask;
1523 u32 e1h_mask;
f2e0899f 1524 u32 e2_mask;
de0c62db 1525 } prty_tbl[] = {
f2e0899f
DK		 1526 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 },
1527 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 },
1528 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 },
1529 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 },
1530 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 },
1531 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 },
1532
1533 { NULL, 0xffffffff, 0, 0, 0 }
de0c62db
DK		 1534 };
1535
1536 if (!netif_running(bp->dev))
1537 return rc;
1538
f2e0899f
DK		 1539 /* pre-Check the parity status */
1540 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1541 val = REG_RD(bp, prty_tbl[i].offset);
1542 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1543 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1544 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1545 DP(NETIF_MSG_HW,
1546 "%s is 0x%x\n", prty_tbl[i].name, val);
1547 goto test_mem_exit;
1548 }
1549 }
1550
de0c62db
DK		 1551 /* Go through all the memories */
1552 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1553 for (j = 0; j < mem_tbl[i].size; j++)
1554 REG_RD(bp, mem_tbl[i].offset + j*4);
1555
1556 /* Check the parity status */
1557 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1558 val = REG_RD(bp, prty_tbl[i].offset);
1559 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
f2e0899f
DK		 1560 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1561 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
de0c62db
DK		 1562 DP(NETIF_MSG_HW,
1563 "%s is 0x%x\n", prty_tbl[i].name, val);
1564 goto test_mem_exit;
1565 }
1566 }
1567
1568 rc = 0;
1569
1570test_mem_exit:
1571 return rc;
1572}
1573
a22f0788 1574static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1575{
f2e0899f 1576 int cnt = 1400;
de0c62db
DK		 1577
1578 if (link_up)
a22f0788 1579 while (bnx2x_link_test(bp, is_serdes) && cnt--)
de0c62db
DK		 1580 msleep(10);
1581}
1582
1583static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1584{
1585 unsigned int pkt_size, num_pkts, i;
1586 struct sk_buff *skb;
1587 unsigned char *packet;
1588 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1589 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1590 u16 tx_start_idx, tx_idx;
1591 u16 rx_start_idx, rx_idx;
1592 u16 pkt_prod, bd_prod;
1593 struct sw_tx_bd *tx_buf;
1594 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1595 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1596 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1597 dma_addr_t mapping;
1598 union eth_rx_cqe *cqe;
1599 u8 cqe_fp_flags;
1600 struct sw_rx_bd *rx_buf;
1601 u16 len;
1602 int rc = -ENODEV;
1603
1604 /* check the loopback mode */
1605 switch (loopback_mode) {
1606 case BNX2X_PHY_LOOPBACK:
de6eae1f 1607 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1608 return -EINVAL;
1609 break;
1610 case BNX2X_MAC_LOOPBACK:
1611 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1612 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1613 break;
1614 default:
1615 return -EINVAL;
1616 }
1617
1618 /* prepare the loopback packet */
1619 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1620 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1621 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1622 if (!skb) {
1623 rc = -ENOMEM;
1624 goto test_loopback_exit;
1625 }
1626 packet = skb_put(skb, pkt_size);
1627 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1628 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1629 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1630 for (i = ETH_HLEN; i < pkt_size; i++)
1631 packet[i] = (unsigned char) (i & 0xff);
1632
1633 /* send the loopback packet */
1634 num_pkts = 0;
1635 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1636 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1637
1638 pkt_prod = fp_tx->tx_pkt_prod++;
1639 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1640 tx_buf->first_bd = fp_tx->tx_bd_prod;
1641 tx_buf->skb = skb;
1642 tx_buf->flags = 0;
1643
1644 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1645 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1646 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1647 skb_headlen(skb), DMA_TO_DEVICE);
1648 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1649 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1650 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1651 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1652 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1653 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1654 SET_FLAG(tx_start_bd->general_data,
1655 ETH_TX_START_BD_ETH_ADDR_TYPE,
1656 UNICAST_ADDRESS);
1657 SET_FLAG(tx_start_bd->general_data,
1658 ETH_TX_START_BD_HDR_NBDS,
1659 1);
de0c62db
DK		 1660
1661 /* turn on parsing and get a BD */
1662 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 1663
523224a3 1664 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
f2e0899f 1665 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1666
f2e0899f 1667 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1668 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1669
1670 wmb();
1671
1672 fp_tx->tx_db.data.prod += 2;
1673 barrier();
1674 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1675
1676 mmiowb();
1677
1678 num_pkts++;
1679 fp_tx->tx_bd_prod += 2; /* start + pbd */
1680
1681 udelay(100);
1682
1683 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1684 if (tx_idx != tx_start_idx + num_pkts)
1685 goto test_loopback_exit;
1686
f2e0899f
DK		 1687 /* Unlike HC IGU won't generate an interrupt for status block
1688 * updates that have been performed while interrupts were
1689 * disabled.
1690 */
e1210d12
ED		 1691 if (bp->common.int_block == INT_BLOCK_IGU) {
1692 /* Disable local BHes to prevent a dead-lock situation between
1693 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1694 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1695 */
1696 local_bh_disable();
f2e0899f 1697 bnx2x_tx_int(fp_tx);
e1210d12
ED		 1698 local_bh_enable();
1699 }
f2e0899f 1700
de0c62db
DK		 1701 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1702 if (rx_idx != rx_start_idx + num_pkts)
1703 goto test_loopback_exit;
1704
1705 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1706 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1707 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1708 goto test_loopback_rx_exit;
1709
1710 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1711 if (len != pkt_size)
1712 goto test_loopback_rx_exit;
1713
1714 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1715 skb = rx_buf->skb;
1716 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1717 for (i = ETH_HLEN; i < pkt_size; i++)
1718 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1719 goto test_loopback_rx_exit;
1720
1721 rc = 0;
1722
1723test_loopback_rx_exit:
1724
1725 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1726 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1727 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1728 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1729
1730 /* Update producers */
1731 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1732 fp_rx->rx_sge_prod);
1733
1734test_loopback_exit:
1735 bp->link_params.loopback_mode = LOOPBACK_NONE;
1736
1737 return rc;
1738}
1739
1740static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1741{
1742 int rc = 0, res;
1743
1744 if (BP_NOMCP(bp))
1745 return rc;
1746
1747 if (!netif_running(bp->dev))
1748 return BNX2X_LOOPBACK_FAILED;
1749
1750 bnx2x_netif_stop(bp, 1);
1751 bnx2x_acquire_phy_lock(bp);
1752
1753 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1754 if (res) {
1755 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1756 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1757 }
1758
1759 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1760 if (res) {
1761 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1762 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1763 }
1764
1765 bnx2x_release_phy_lock(bp);
1766 bnx2x_netif_start(bp);
1767
1768 return rc;
1769}
1770
1771#define CRC32_RESIDUAL 0xdebb20e3
1772
1773static int bnx2x_test_nvram(struct bnx2x *bp)
1774{
1775 static const struct {
1776 int offset;
1777 int size;
1778 } nvram_tbl[] = {
1779 { 0, 0x14 }, /* bootstrap */
1780 { 0x14, 0xec }, /* dir */
1781 { 0x100, 0x350 }, /* manuf_info */
1782 { 0x450, 0xf0 }, /* feature_info */
1783 { 0x640, 0x64 }, /* upgrade_key_info */
1784 { 0x6a4, 0x64 },
1785 { 0x708, 0x70 }, /* manuf_key_info */
1786 { 0x778, 0x70 },
1787 { 0, 0 }
1788 };
1789 __be32 buf[0x350 / 4];
1790 u8 *data = (u8 *)buf;
1791 int i, rc;
1792 u32 magic, crc;
1793
1794 if (BP_NOMCP(bp))
1795 return 0;
1796
1797 rc = bnx2x_nvram_read(bp, 0, data, 4);
1798 if (rc) {
1799 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1800 goto test_nvram_exit;
1801 }
1802
1803 magic = be32_to_cpu(buf[0]);
1804 if (magic != 0x669955aa) {
1805 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1806 rc = -ENODEV;
1807 goto test_nvram_exit;
1808 }
1809
1810 for (i = 0; nvram_tbl[i].size; i++) {
1811
1812 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1813 nvram_tbl[i].size);
1814 if (rc) {
1815 DP(NETIF_MSG_PROBE,
1816 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1817 goto test_nvram_exit;
1818 }
1819
1820 crc = ether_crc_le(nvram_tbl[i].size, data);
1821 if (crc != CRC32_RESIDUAL) {
1822 DP(NETIF_MSG_PROBE,
1823 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1824 rc = -ENODEV;
1825 goto test_nvram_exit;
1826 }
1827 }
1828
1829test_nvram_exit:
1830 return rc;
1831}
1832
1833static int bnx2x_test_intr(struct bnx2x *bp)
1834{
1835 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1836 int i, rc;
1837
1838 if (!netif_running(bp->dev))
1839 return -ENODEV;
1840
1841 config->hdr.length = 0;
1842 if (CHIP_IS_E1(bp))
f2e0899f 1843 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
de0c62db
DK		 1844 else
1845 config->hdr.offset = BP_FUNC(bp);
1846 config->hdr.client_id = bp->fp->cl_id;
1847 config->hdr.reserved1 = 0;
1848
ec6ba945 1849 bp->set_mac_pending = 1;
de0c62db 1850 smp_wmb();
523224a3 1851 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
de0c62db 1852 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3 1853 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
de0c62db
DK		 1854 if (rc == 0) {
1855 for (i = 0; i < 10; i++) {
1856 if (!bp->set_mac_pending)
1857 break;
1858 smp_rmb();
1859 msleep_interruptible(10);
1860 }
1861 if (i == 10)
1862 rc = -ENODEV;
1863 }
1864
1865 return rc;
1866}
1867
1868static void bnx2x_self_test(struct net_device *dev,
1869 struct ethtool_test *etest, u64 *buf)
1870{
1871 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1872 u8 is_serdes;
de0c62db
DK		 1873 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1874 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1875 etest->flags |= ETH_TEST_FL_FAILED;
1876 return;
1877 }
1878
1879 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1880
1881 if (!netif_running(dev))
1882 return;
1883
1884 /* offline tests are not supported in MF mode */
fb3bff17 1885 if (IS_MF(bp))
de0c62db 1886 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 1887 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 1888
1889 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1890 int port = BP_PORT(bp);
1891 u32 val;
1892 u8 link_up;
1893
1894 /* save current value of input enable for TX port IF */
1895 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1896 /* disable input for TX port IF */
1897 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1898
a22f0788
YR		 1899 link_up = bp->link_vars.link_up;
1900
de0c62db
DK		 1901 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1902 bnx2x_nic_load(bp, LOAD_DIAG);
1903 /* wait until link state is restored */
a22f0788 1904 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1905
1906 if (bnx2x_test_registers(bp) != 0) {
1907 buf[0] = 1;
1908 etest->flags |= ETH_TEST_FL_FAILED;
1909 }
1910 if (bnx2x_test_memory(bp) != 0) {
1911 buf[1] = 1;
1912 etest->flags |= ETH_TEST_FL_FAILED;
1913 }
f85582f8 1914
de0c62db
DK		 1915 buf[2] = bnx2x_test_loopback(bp, link_up);
1916 if (buf[2] != 0)
1917 etest->flags |= ETH_TEST_FL_FAILED;
1918
1919 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1920
1921 /* restore input for TX port IF */
1922 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1923
1924 bnx2x_nic_load(bp, LOAD_NORMAL);
1925 /* wait until link state is restored */
a22f0788 1926 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1927 }
1928 if (bnx2x_test_nvram(bp) != 0) {
1929 buf[3] = 1;
1930 etest->flags |= ETH_TEST_FL_FAILED;
1931 }
1932 if (bnx2x_test_intr(bp) != 0) {
1933 buf[4] = 1;
1934 etest->flags |= ETH_TEST_FL_FAILED;
1935 }
1936 if (bp->port.pmf)
a22f0788 1937 if (bnx2x_link_test(bp, is_serdes) != 0) {
de0c62db
DK		 1938 buf[5] = 1;
1939 etest->flags |= ETH_TEST_FL_FAILED;
1940 }
1941
1942#ifdef BNX2X_EXTRA_DEBUG
1943 bnx2x_panic_dump(bp);
1944#endif
1945}
1946
de0c62db
DK		 1947#define IS_PORT_STAT(i) \
1948 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1949#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 1950#define IS_MF_MODE_STAT(bp) \
1951 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db
DK		 1952
1953static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1954{
1955 struct bnx2x *bp = netdev_priv(dev);
1956 int i, num_stats;
1957
1958 switch (stringset) {
1959 case ETH_SS_STATS:
1960 if (is_multi(bp)) {
ec6ba945
VZ		 1961 num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1962 BNX2X_NUM_Q_STATS;
fb3bff17 1963 if (!IS_MF_MODE_STAT(bp))
de0c62db
DK		 1964 num_stats += BNX2X_NUM_STATS;
1965 } else {
fb3bff17 1966 if (IS_MF_MODE_STAT(bp)) {
de0c62db
DK		 1967 num_stats = 0;
1968 for (i = 0; i < BNX2X_NUM_STATS; i++)
1969 if (IS_FUNC_STAT(i))
1970 num_stats++;
1971 } else
1972 num_stats = BNX2X_NUM_STATS;
1973 }
1974 return num_stats;
1975
1976 case ETH_SS_TEST:
1977 return BNX2X_NUM_TESTS;
1978
1979 default:
1980 return -EINVAL;
1981 }
1982}
1983
1984static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1985{
1986 struct bnx2x *bp = netdev_priv(dev);
1987 int i, j, k;
ec6ba945 1988 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 1989
1990 switch (stringset) {
1991 case ETH_SS_STATS:
1992 if (is_multi(bp)) {
1993 k = 0;
ec6ba945
VZ		 1994 for_each_napi_queue(bp, i) {
1995 memset(queue_name, 0, sizeof(queue_name));
1996
1997 if (IS_FCOE_IDX(i))
1998 sprintf(queue_name, "fcoe");
1999 else
2000 sprintf(queue_name, "%d", i);
2001
de0c62db 2002 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2003 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2004 ETH_GSTRING_LEN,
2005 bnx2x_q_stats_arr[j].string,
2006 queue_name);
de0c62db
DK		 2007 k += BNX2X_NUM_Q_STATS;
2008 }
fb3bff17 2009 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 2010 break;
2011 for (j = 0; j < BNX2X_NUM_STATS; j++)
2012 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2013 bnx2x_stats_arr[j].string);
2014 } else {
2015 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2016 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2017 continue;
2018 strcpy(buf + j*ETH_GSTRING_LEN,
2019 bnx2x_stats_arr[i].string);
2020 j++;
2021 }
2022 }
2023 break;
2024
2025 case ETH_SS_TEST:
2026 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2027 break;
2028 }
2029}
2030
2031static void bnx2x_get_ethtool_stats(struct net_device *dev,
2032 struct ethtool_stats *stats, u64 *buf)
2033{
2034 struct bnx2x *bp = netdev_priv(dev);
2035 u32 *hw_stats, *offset;
2036 int i, j, k;
2037
2038 if (is_multi(bp)) {
2039 k = 0;
ec6ba945 2040 for_each_napi_queue(bp, i) {
de0c62db
DK		 2041 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2042 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2043 if (bnx2x_q_stats_arr[j].size == 0) {
2044 /* skip this counter */
2045 buf[k + j] = 0;
2046 continue;
2047 }
2048 offset = (hw_stats +
2049 bnx2x_q_stats_arr[j].offset);
2050 if (bnx2x_q_stats_arr[j].size == 4) {
2051 /* 4-byte counter */
2052 buf[k + j] = (u64) *offset;
2053 continue;
2054 }
2055 /* 8-byte counter */
2056 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2057 }
2058 k += BNX2X_NUM_Q_STATS;
2059 }
fb3bff17 2060 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 2061 return;
2062 hw_stats = (u32 *)&bp->eth_stats;
2063 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2064 if (bnx2x_stats_arr[j].size == 0) {
2065 /* skip this counter */
2066 buf[k + j] = 0;
2067 continue;
2068 }
2069 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2070 if (bnx2x_stats_arr[j].size == 4) {
2071 /* 4-byte counter */
2072 buf[k + j] = (u64) *offset;
2073 continue;
2074 }
2075 /* 8-byte counter */
2076 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2077 }
2078 } else {
2079 hw_stats = (u32 *)&bp->eth_stats;
2080 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2081 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2082 continue;
2083 if (bnx2x_stats_arr[i].size == 0) {
2084 /* skip this counter */
2085 buf[j] = 0;
2086 j++;
2087 continue;
2088 }
2089 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2090 if (bnx2x_stats_arr[i].size == 4) {
2091 /* 4-byte counter */
2092 buf[j] = (u64) *offset;
2093 j++;
2094 continue;
2095 }
2096 /* 8-byte counter */
2097 buf[j] = HILO_U64(*offset, *(offset + 1));
2098 j++;
2099 }
2100 }
2101}
2102
2103static int bnx2x_phys_id(struct net_device *dev, u32 data)
2104{
2105 struct bnx2x *bp = netdev_priv(dev);
2106 int i;
2107
2108 if (!netif_running(dev))
2109 return 0;
2110
2111 if (!bp->port.pmf)
2112 return 0;
2113
2114 if (data == 0)
2115 data = 2;
2116
2117 for (i = 0; i < (data * 2); i++) {
2118 if ((i % 2) == 0)
7f02c4ad
YR		 2119 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2120 LED_MODE_OPER, SPEED_1000);
de0c62db 2121 else
7f02c4ad
YR		 2122 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2123 LED_MODE_OFF, 0);
de0c62db
DK		 2124
2125 msleep_interruptible(500);
2126 if (signal_pending(current))
2127 break;
2128 }
2129
2130 if (bp->link_vars.link_up)
7f02c4ad 2131 bnx2x_set_led(&bp->link_params, &bp->link_vars, LED_MODE_OPER,
de0c62db
DK		 2132 bp->link_vars.line_speed);
2133
2134 return 0;
2135}
2136
2137static const struct ethtool_ops bnx2x_ethtool_ops = {
2138 .get_settings = bnx2x_get_settings,
2139 .set_settings = bnx2x_set_settings,
2140 .get_drvinfo = bnx2x_get_drvinfo,
2141 .get_regs_len = bnx2x_get_regs_len,
2142 .get_regs = bnx2x_get_regs,
2143 .get_wol = bnx2x_get_wol,
2144 .set_wol = bnx2x_set_wol,
2145 .get_msglevel = bnx2x_get_msglevel,
2146 .set_msglevel = bnx2x_set_msglevel,
2147 .nway_reset = bnx2x_nway_reset,
2148 .get_link = bnx2x_get_link,
2149 .get_eeprom_len = bnx2x_get_eeprom_len,
2150 .get_eeprom = bnx2x_get_eeprom,
2151 .set_eeprom = bnx2x_set_eeprom,
2152 .get_coalesce = bnx2x_get_coalesce,
2153 .set_coalesce = bnx2x_set_coalesce,
2154 .get_ringparam = bnx2x_get_ringparam,
2155 .set_ringparam = bnx2x_set_ringparam,
2156 .get_pauseparam = bnx2x_get_pauseparam,
2157 .set_pauseparam = bnx2x_set_pauseparam,
2158 .get_rx_csum = bnx2x_get_rx_csum,
2159 .set_rx_csum = bnx2x_set_rx_csum,
2160 .get_tx_csum = ethtool_op_get_tx_csum,
2161 .set_tx_csum = ethtool_op_set_tx_hw_csum,
2162 .set_flags = bnx2x_set_flags,
2163 .get_flags = ethtool_op_get_flags,
2164 .get_sg = ethtool_op_get_sg,
2165 .set_sg = ethtool_op_set_sg,
2166 .get_tso = ethtool_op_get_tso,
2167 .set_tso = bnx2x_set_tso,
2168 .self_test = bnx2x_self_test,
2169 .get_sset_count = bnx2x_get_sset_count,
2170 .get_strings = bnx2x_get_strings,
2171 .phys_id = bnx2x_phys_id,
2172 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2173};
2174
2175void bnx2x_set_ethtool_ops(struct net_device *netdev)
2176{
2177 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2178}
kernel source for telekom puls (alcatel/mediatek)