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ipv6: remove some useless RCU read lock
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 66};
67
68#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70static const struct {
71 long offset;
72 int size;
73 u32 flags;
74#define STATS_FLAGS_PORT 1
75#define STATS_FLAGS_FUNC 2
76#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78} bnx2x_stats_arr[] = {
79/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 107 { STATS_OFFSET32(pfc_frames_received_hi),
108 8, STATS_FLAGS_PORT, "pfc_frames_received" },
109 { STATS_OFFSET32(pfc_frames_sent_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 111 { STATS_OFFSET32(brb_drop_hi),
112 8, STATS_FLAGS_PORT, "rx_brb_discard" },
113 { STATS_OFFSET32(brb_truncate_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
115 { STATS_OFFSET32(pause_frames_received_hi),
116 8, STATS_FLAGS_PORT, "rx_pause_frames" },
117 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
118 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
119 { STATS_OFFSET32(nig_timer_max),
120 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
121/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
122 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
123 { STATS_OFFSET32(rx_skb_alloc_failed),
124 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
125 { STATS_OFFSET32(hw_csum_err),
126 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
127
128 { STATS_OFFSET32(total_bytes_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bytes" },
130 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
131 8, STATS_FLAGS_PORT, "tx_error_bytes" },
132 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
134 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
136 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
138 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
139 8, STATS_FLAGS_PORT, "tx_mac_errors" },
140 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
141 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
142/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
143 8, STATS_FLAGS_PORT, "tx_single_collisions" },
144 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
147 8, STATS_FLAGS_PORT, "tx_deferred" },
148 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
150 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_late_collisions" },
152 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_total_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
155 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
157 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
159 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
161 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
162/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
163 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
164 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
165 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
166 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
168 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 169 8, STATS_FLAGS_PORT, "tx_pause_frames" },
170 { STATS_OFFSET32(total_tpa_aggregations_hi),
171 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
172 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
174 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 175 8, STATS_FLAGS_FUNC, "tpa_bytes"},
176 { STATS_OFFSET32(recoverable_error),
177 4, STATS_FLAGS_FUNC, "recoverable_errors" },
178 { STATS_OFFSET32(unrecoverable_error),
179 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
e9939c80
YM		 180 { STATS_OFFSET32(eee_tx_lpi),
181 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 182};
183
184#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 185static int bnx2x_get_port_type(struct bnx2x *bp)
186{
187 int port_type;
188 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
189 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 190 case ETH_PHY_SFPP_10G_FIBER:
191 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 192 case ETH_PHY_XFP_FIBER:
193 case ETH_PHY_KR:
194 case ETH_PHY_CX4:
195 port_type = PORT_FIBRE;
196 break;
197 case ETH_PHY_DA_TWINAX:
198 port_type = PORT_DA;
199 break;
200 case ETH_PHY_BASE_T:
201 port_type = PORT_TP;
202 break;
203 case ETH_PHY_NOT_PRESENT:
204 port_type = PORT_NONE;
205 break;
206 case ETH_PHY_UNSPECIFIED:
207 default:
208 port_type = PORT_OTHER;
209 break;
210 }
211 return port_type;
212}
ec6ba945 213
de0c62db
DK		 214static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
215{
216 struct bnx2x *bp = netdev_priv(dev);
a22f0788 217 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 218
a22f0788
YR		 219 /* Dual Media boards present all available port types */
220 cmd->supported = bp->port.supported[cfg_idx] |
221 (bp->port.supported[cfg_idx ^ 1] &
222 (SUPPORTED_TP | SUPPORTED_FIBRE));
223 cmd->advertising = bp->port.advertising[cfg_idx];
dbef807e
YM		 224 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
225 ETH_PHY_SFP_1G_FIBER) {
226 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
227 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
228 }
de0c62db 229
38298461
YM		 230 if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
231 if (!(bp->flags & MF_FUNC_DIS)) {
232 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
233 cmd->duplex = bp->link_vars.duplex;
234 } else {
235 ethtool_cmd_speed_set(
236 cmd, bp->link_params.req_line_speed[cfg_idx]);
237 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
238 }
239
240 if (IS_MF(bp) && !BP_NOMCP(bp))
241 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 242 } else {
38298461
YM		 243 cmd->duplex = DUPLEX_UNKNOWN;
244 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 245 }
f2e0899f 246
1ac9e428 247 cmd->port = bnx2x_get_port_type(bp);
a22f0788 248
de0c62db
DK		 249 cmd->phy_address = bp->mdio.prtad;
250 cmd->transceiver = XCVR_INTERNAL;
251
a22f0788 252 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 253 cmd->autoneg = AUTONEG_ENABLE;
254 else
255 cmd->autoneg = AUTONEG_DISABLE;
256
9e7e8399
MY		 257 /* Publish LP advertised speeds and FC */
258 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
259 u32 status = bp->link_vars.link_status;
260
261 cmd->lp_advertising |= ADVERTISED_Autoneg;
262 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
263 cmd->lp_advertising |= ADVERTISED_Pause;
264 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
265 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
266
267 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
268 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
269 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
270 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
271 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
272 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
273 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
274 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
275 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
276 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
277 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
278 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
279 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
280 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
281 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
282 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
283 }
284
de0c62db
DK		 285 cmd->maxtxpkt = 0;
286 cmd->maxrxpkt = 0;
287
51c1a580 288 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 289 " supported 0x%x advertising 0x%x speed %u\n"
290 " duplex %d port %d phy_address %d transceiver %d\n"
291 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 292 cmd->cmd, cmd->supported, cmd->advertising,
293 ethtool_cmd_speed(cmd),
de0c62db
DK		 294 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
295 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
296
297 return 0;
298}
299
300static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
301{
302 struct bnx2x *bp = netdev_priv(dev);
a22f0788 303 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 304 u32 speed, phy_idx;
de0c62db 305
0793f83f 306 if (IS_MF_SD(bp))
de0c62db
DK		 307 return 0;
308
51c1a580 309 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 310 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 311 " duplex %d port %d phy_address %d transceiver %d\n"
312 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 313 cmd->cmd, cmd->supported, cmd->advertising,
314 ethtool_cmd_speed(cmd),
de0c62db
DK		 315 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
316 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
317
b3337e4c 318 speed = ethtool_cmd_speed(cmd);
0793f83f 319
38298461
YM		 320 /* If recieved a request for an unknown duplex, assume full*/
321 if (cmd->duplex == DUPLEX_UNKNOWN)
322 cmd->duplex = DUPLEX_FULL;
323
0793f83f 324 if (IS_MF_SI(bp)) {
e3835b99 325 u32 part;
0793f83f
DK		 326 u32 line_speed = bp->link_vars.line_speed;
327
328 /* use 10G if no link detected */
329 if (!line_speed)
330 line_speed = 10000;
331
332 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 333 DP(BNX2X_MSG_ETHTOOL,
334 "To set speed BC %X or higher is required, please upgrade BC\n",
335 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 336 return -EINVAL;
337 }
e3835b99 338
faa6fcbb 339 part = (speed * 100) / line_speed;
e3835b99 340
faa6fcbb 341 if (line_speed < speed || !part) {
51c1a580
MS		 342 DP(BNX2X_MSG_ETHTOOL,
343 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 344 return -EINVAL;
345 }
0793f83f 346
e3835b99
DK		 347 if (bp->state != BNX2X_STATE_OPEN)
348 /* store value for following "load" */
349 bp->pending_max = part;
350 else
351 bnx2x_update_max_mf_config(bp, part);
0793f83f 352
0793f83f
DK		 353 return 0;
354 }
355
a22f0788
YR		 356 cfg_idx = bnx2x_get_link_cfg_idx(bp);
357 old_multi_phy_config = bp->link_params.multi_phy_config;
358 switch (cmd->port) {
359 case PORT_TP:
360 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
361 break; /* no port change */
362
363 if (!(bp->port.supported[0] & SUPPORTED_TP ||
364 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 365 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 366 return -EINVAL;
367 }
368 bp->link_params.multi_phy_config &=
369 ~PORT_HW_CFG_PHY_SELECTION_MASK;
370 if (bp->link_params.multi_phy_config &
371 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
372 bp->link_params.multi_phy_config |=
373 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
374 else
375 bp->link_params.multi_phy_config |=
376 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
377 break;
378 case PORT_FIBRE:
bfdb5823 379 case PORT_DA:
a22f0788
YR		 380 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
381 break; /* no port change */
382
383 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
384 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 385 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 386 return -EINVAL;
387 }
388 bp->link_params.multi_phy_config &=
389 ~PORT_HW_CFG_PHY_SELECTION_MASK;
390 if (bp->link_params.multi_phy_config &
391 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
392 bp->link_params.multi_phy_config |=
393 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
394 else
395 bp->link_params.multi_phy_config |=
396 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
397 break;
398 default:
51c1a580 399 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 400 return -EINVAL;
401 }
2f751a80 402 /* Save new config in case command complete successully */
a22f0788
YR		 403 new_multi_phy_config = bp->link_params.multi_phy_config;
404 /* Get the new cfg_idx */
405 cfg_idx = bnx2x_get_link_cfg_idx(bp);
406 /* Restore old config in case command failed */
407 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 408 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 409
de0c62db 410 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 411 u32 an_supported_speed = bp->port.supported[cfg_idx];
412 if (bp->link_params.phy[EXT_PHY1].type ==
413 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
414 an_supported_speed |= (SUPPORTED_100baseT_Half |
415 SUPPORTED_100baseT_Full);
a22f0788 416 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 417 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 418 return -EINVAL;
419 }
420
421 /* advertise the requested speed and duplex if supported */
75318327 422 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 423 DP(BNX2X_MSG_ETHTOOL,
424 "Advertisement parameters are not supported\n");
8d661637
YR		 425 return -EINVAL;
426 }
de0c62db 427
a22f0788 428 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 429 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
430 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 431 cmd->advertising);
8d661637
YR		 432 if (cmd->advertising) {
433
434 bp->link_params.speed_cap_mask[cfg_idx] = 0;
435 if (cmd->advertising & ADVERTISED_10baseT_Half) {
436 bp->link_params.speed_cap_mask[cfg_idx] |=
437 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
438 }
439 if (cmd->advertising & ADVERTISED_10baseT_Full)
440 bp->link_params.speed_cap_mask[cfg_idx] |=
441 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 442
8d661637
YR		 443 if (cmd->advertising & ADVERTISED_100baseT_Full)
444 bp->link_params.speed_cap_mask[cfg_idx] |=
445 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
446
447 if (cmd->advertising & ADVERTISED_100baseT_Half) {
448 bp->link_params.speed_cap_mask[cfg_idx] |=
449 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
450 }
451 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
452 bp->link_params.speed_cap_mask[cfg_idx] |=
453 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
454 }
455 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
456 ADVERTISED_1000baseKX_Full))
457 bp->link_params.speed_cap_mask[cfg_idx] |=
458 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
459
460 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
461 ADVERTISED_10000baseKX4_Full |
462 ADVERTISED_10000baseKR_Full))
463 bp->link_params.speed_cap_mask[cfg_idx] |=
464 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
465 }
de0c62db
DK		 466 } else { /* forced speed */
467 /* advertise the requested speed and duplex if supported */
a22f0788 468 switch (speed) {
de0c62db
DK		 469 case SPEED_10:
470 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 471 if (!(bp->port.supported[cfg_idx] &
de0c62db 472 SUPPORTED_10baseT_Full)) {
51c1a580 473 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 474 "10M full not supported\n");
475 return -EINVAL;
476 }
477
478 advertising = (ADVERTISED_10baseT_Full |
479 ADVERTISED_TP);
480 } else {
a22f0788 481 if (!(bp->port.supported[cfg_idx] &
de0c62db 482 SUPPORTED_10baseT_Half)) {
51c1a580 483 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 484 "10M half not supported\n");
485 return -EINVAL;
486 }
487
488 advertising = (ADVERTISED_10baseT_Half |
489 ADVERTISED_TP);
490 }
491 break;
492
493 case SPEED_100:
494 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 495 if (!(bp->port.supported[cfg_idx] &
de0c62db 496 SUPPORTED_100baseT_Full)) {
51c1a580 497 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 498 "100M full not supported\n");
499 return -EINVAL;
500 }
501
502 advertising = (ADVERTISED_100baseT_Full |
503 ADVERTISED_TP);
504 } else {
a22f0788 505 if (!(bp->port.supported[cfg_idx] &
de0c62db 506 SUPPORTED_100baseT_Half)) {
51c1a580 507 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 508 "100M half not supported\n");
509 return -EINVAL;
510 }
511
512 advertising = (ADVERTISED_100baseT_Half |
513 ADVERTISED_TP);
514 }
515 break;
516
517 case SPEED_1000:
518 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 519 DP(BNX2X_MSG_ETHTOOL,
520 "1G half not supported\n");
de0c62db
DK		 521 return -EINVAL;
522 }
523
a22f0788
YR		 524 if (!(bp->port.supported[cfg_idx] &
525 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 526 DP(BNX2X_MSG_ETHTOOL,
527 "1G full not supported\n");
de0c62db
DK		 528 return -EINVAL;
529 }
530
531 advertising = (ADVERTISED_1000baseT_Full |
532 ADVERTISED_TP);
533 break;
534
535 case SPEED_2500:
536 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 537 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 538 "2.5G half not supported\n");
539 return -EINVAL;
540 }
541
a22f0788
YR		 542 if (!(bp->port.supported[cfg_idx]
543 & SUPPORTED_2500baseX_Full)) {
51c1a580 544 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 545 "2.5G full not supported\n");
546 return -EINVAL;
547 }
548
549 advertising = (ADVERTISED_2500baseX_Full |
550 ADVERTISED_TP);
551 break;
552
553 case SPEED_10000:
554 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 555 DP(BNX2X_MSG_ETHTOOL,
556 "10G half not supported\n");
de0c62db
DK		 557 return -EINVAL;
558 }
dbef807e 559 phy_idx = bnx2x_get_cur_phy_idx(bp);
a22f0788 560 if (!(bp->port.supported[cfg_idx]
dbef807e
YM		 561 & SUPPORTED_10000baseT_Full) ||
562 (bp->link_params.phy[phy_idx].media_type ==
563 ETH_PHY_SFP_1G_FIBER)) {
51c1a580
MS		 564 DP(BNX2X_MSG_ETHTOOL,
565 "10G full not supported\n");
de0c62db
DK		 566 return -EINVAL;
567 }
568
569 advertising = (ADVERTISED_10000baseT_Full |
570 ADVERTISED_FIBRE);
571 break;
572
573 default:
51c1a580 574 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 575 return -EINVAL;
576 }
577
a22f0788
YR		 578 bp->link_params.req_line_speed[cfg_idx] = speed;
579 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
580 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 581 }
582
51c1a580 583 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 584 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 585 bp->link_params.req_line_speed[cfg_idx],
586 bp->link_params.req_duplex[cfg_idx],
587 bp->port.advertising[cfg_idx]);
de0c62db 588
a22f0788
YR		 589 /* Set new config */
590 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 591 if (netif_running(dev)) {
592 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
593 bnx2x_link_set(bp);
594 }
595
596 return 0;
597}
598
599#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
600#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 601#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 602#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
603#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
604
1191cb83
ED		 605static bool bnx2x_is_reg_online(struct bnx2x *bp,
606 const struct reg_addr *reg_info)
0fea29c1
VZ		 607{
608 if (CHIP_IS_E1(bp))
609 return IS_E1_ONLINE(reg_info->info);
610 else if (CHIP_IS_E1H(bp))
611 return IS_E1H_ONLINE(reg_info->info);
612 else if (CHIP_IS_E2(bp))
613 return IS_E2_ONLINE(reg_info->info);
614 else if (CHIP_IS_E3A0(bp))
615 return IS_E3_ONLINE(reg_info->info);
616 else if (CHIP_IS_E3B0(bp))
617 return IS_E3B0_ONLINE(reg_info->info);
618 else
619 return false;
620}
621
622/******* Paged registers info selectors ********/
1191cb83 623static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 624{
625 if (CHIP_IS_E2(bp))
626 return page_vals_e2;
627 else if (CHIP_IS_E3(bp))
628 return page_vals_e3;
629 else
630 return NULL;
631}
632
1191cb83 633static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 634{
635 if (CHIP_IS_E2(bp))
636 return PAGE_MODE_VALUES_E2;
637 else if (CHIP_IS_E3(bp))
638 return PAGE_MODE_VALUES_E3;
639 else
640 return 0;
641}
642
1191cb83 643static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 644{
645 if (CHIP_IS_E2(bp))
646 return page_write_regs_e2;
647 else if (CHIP_IS_E3(bp))
648 return page_write_regs_e3;
649 else
650 return NULL;
651}
652
1191cb83 653static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 654{
655 if (CHIP_IS_E2(bp))
656 return PAGE_WRITE_REGS_E2;
657 else if (CHIP_IS_E3(bp))
658 return PAGE_WRITE_REGS_E3;
659 else
660 return 0;
661}
662
1191cb83 663static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 664{
665 if (CHIP_IS_E2(bp))
666 return page_read_regs_e2;
667 else if (CHIP_IS_E3(bp))
668 return page_read_regs_e3;
669 else
670 return NULL;
671}
672
1191cb83 673static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 674{
675 if (CHIP_IS_E2(bp))
676 return PAGE_READ_REGS_E2;
677 else if (CHIP_IS_E3(bp))
678 return PAGE_READ_REGS_E3;
679 else
680 return 0;
681}
682
1191cb83 683static int __bnx2x_get_regs_len(struct bnx2x *bp)
0fea29c1
VZ		 684{
685 int num_pages = __bnx2x_get_page_reg_num(bp);
686 int page_write_num = __bnx2x_get_page_write_num(bp);
687 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
688 int page_read_num = __bnx2x_get_page_read_num(bp);
689 int regdump_len = 0;
690 int i, j, k;
691
692 for (i = 0; i < REGS_COUNT; i++)
693 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
694 regdump_len += reg_addrs[i].size;
695
696 for (i = 0; i < num_pages; i++)
697 for (j = 0; j < page_write_num; j++)
698 for (k = 0; k < page_read_num; k++)
699 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
700 regdump_len += page_read_addr[k].size;
701
702 return regdump_len;
703}
de0c62db
DK		 704
705static int bnx2x_get_regs_len(struct net_device *dev)
706{
707 struct bnx2x *bp = netdev_priv(dev);
708 int regdump_len = 0;
de0c62db 709
0fea29c1 710 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 711 regdump_len *= 4;
712 regdump_len += sizeof(struct dump_hdr);
713
714 return regdump_len;
715}
716
0fea29c1
VZ		 717/**
718 * bnx2x_read_pages_regs - read "paged" registers
719 *
720 * @bp device handle
721 * @p output buffer
722 *
723 * Reads "paged" memories: memories that may only be read by first writing to a
724 * specific address ("write address") and then reading from a specific address
725 * ("read address"). There may be more than one write address per "page" and
726 * more than one read address per write address.
727 */
1191cb83 728static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 729{
730 u32 i, j, k, n;
0fea29c1
VZ		 731 /* addresses of the paged registers */
732 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
733 /* number of paged registers */
734 int num_pages = __bnx2x_get_page_reg_num(bp);
735 /* write addresses */
736 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
737 /* number of write addresses */
738 int write_num = __bnx2x_get_page_write_num(bp);
739 /* read addresses info */
740 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
741 /* number of read addresses */
742 int read_num = __bnx2x_get_page_read_num(bp);
743
744 for (i = 0; i < num_pages; i++) {
745 for (j = 0; j < write_num; j++) {
746 REG_WR(bp, write_addr[j], page_addr[i]);
747 for (k = 0; k < read_num; k++)
748 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 749 for (n = 0; n <
0fea29c1 750 read_addr[k].size; n++)
f2e0899f 751 *p++ = REG_RD(bp,
0fea29c1 752 read_addr[k].addr + n*4);
f2e0899f
DK		 753 }
754 }
755}
756
1191cb83 757static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
0fea29c1
VZ		 758{
759 u32 i, j;
760
761 /* Read the regular registers */
762 for (i = 0; i < REGS_COUNT; i++)
763 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
764 for (j = 0; j < reg_addrs[i].size; j++)
765 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
766
767 /* Read "paged" registes */
768 bnx2x_read_pages_regs(bp, p);
769}
770
de0c62db
DK		 771static void bnx2x_get_regs(struct net_device *dev,
772 struct ethtool_regs *regs, void *_p)
773{
0fea29c1 774 u32 *p = _p;
de0c62db
DK		 775 struct bnx2x *bp = netdev_priv(dev);
776 struct dump_hdr dump_hdr = {0};
777
778 regs->version = 0;
779 memset(p, 0, regs->len);
780
781 if (!netif_running(bp->dev))
782 return;
783
4a33bc03
VZ		 784 /* Disable parity attentions as long as following dump may
785 * cause false alarms by reading never written registers. We
786 * will re-enable parity attentions right after the dump.
787 */
788 bnx2x_disable_blocks_parity(bp);
789
de0c62db
DK		 790 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
791 dump_hdr.dump_sign = dump_sign_all;
792 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
793 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
794 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
795 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 796
797 if (CHIP_IS_E1(bp))
798 dump_hdr.info = RI_E1_ONLINE;
799 else if (CHIP_IS_E1H(bp))
800 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 801 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 802 dump_hdr.info = RI_E2_ONLINE |
803 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 804
805 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
806 p += dump_hdr.hdr_size + 1;
807
0fea29c1
VZ		 808 /* Actually read the registers */
809 __bnx2x_get_regs(bp, p);
810
4a33bc03
VZ		 811 /* Re-enable parity attentions */
812 bnx2x_clear_blocks_parity(bp);
c9ee9206 813 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 814}
815
de0c62db
DK		 816static void bnx2x_get_drvinfo(struct net_device *dev,
817 struct ethtool_drvinfo *info)
818{
819 struct bnx2x *bp = netdev_priv(dev);
820 u8 phy_fw_ver[PHY_FW_VER_LEN];
821
68aad78c
RJ		 822 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
823 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db
DK		 824
825 phy_fw_ver[0] = '\0';
a1e785e0
MY		 826 bnx2x_get_ext_phy_fw_version(&bp->link_params,
827 phy_fw_ver, PHY_FW_VER_LEN);
68aad78c 828 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
de0c62db
DK		 829 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
830 "bc %d.%d.%d%s%s",
831 (bp->common.bc_ver & 0xff0000) >> 16,
832 (bp->common.bc_ver & 0xff00) >> 8,
833 (bp->common.bc_ver & 0xff),
834 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
68aad78c 835 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 836 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 837 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 838 info->eedump_len = bp->common.flash_size;
839 info->regdump_len = bnx2x_get_regs_len(dev);
840}
841
842static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
843{
844 struct bnx2x *bp = netdev_priv(dev);
845
846 if (bp->flags & NO_WOL_FLAG) {
847 wol->supported = 0;
848 wol->wolopts = 0;
849 } else {
850 wol->supported = WAKE_MAGIC;
851 if (bp->wol)
852 wol->wolopts = WAKE_MAGIC;
853 else
854 wol->wolopts = 0;
855 }
856 memset(&wol->sopass, 0, sizeof(wol->sopass));
857}
858
859static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
860{
861 struct bnx2x *bp = netdev_priv(dev);
862
51c1a580
MS		 863 if (wol->wolopts & ~WAKE_MAGIC) {
864 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 865 return -EINVAL;
51c1a580 866 }
de0c62db
DK		 867
868 if (wol->wolopts & WAKE_MAGIC) {
51c1a580
MS		 869 if (bp->flags & NO_WOL_FLAG) {
870 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 871 return -EINVAL;
51c1a580 872 }
de0c62db
DK		 873 bp->wol = 1;
874 } else
875 bp->wol = 0;
876
877 return 0;
878}
879
880static u32 bnx2x_get_msglevel(struct net_device *dev)
881{
882 struct bnx2x *bp = netdev_priv(dev);
883
884 return bp->msg_enable;
885}
886
887static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
888{
889 struct bnx2x *bp = netdev_priv(dev);
890
7a25cc73
DK		 891 if (capable(CAP_NET_ADMIN)) {
892 /* dump MCP trace */
893 if (level & BNX2X_MSG_MCP)
894 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 895 bp->msg_enable = level;
7a25cc73 896 }
de0c62db
DK		 897}
898
899static int bnx2x_nway_reset(struct net_device *dev)
900{
901 struct bnx2x *bp = netdev_priv(dev);
902
903 if (!bp->port.pmf)
904 return 0;
905
906 if (netif_running(dev)) {
907 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
908 bnx2x_link_set(bp);
909 }
910
911 return 0;
912}
913
914static u32 bnx2x_get_link(struct net_device *dev)
915{
916 struct bnx2x *bp = netdev_priv(dev);
917
f2e0899f 918 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 919 return 0;
920
921 return bp->link_vars.link_up;
922}
923
924static int bnx2x_get_eeprom_len(struct net_device *dev)
925{
926 struct bnx2x *bp = netdev_priv(dev);
927
928 return bp->common.flash_size;
929}
930
f16da43b
AE		 931/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
932 * we done things the other way around, if two pfs from the same port would
933 * attempt to access nvram at the same time, we could run into a scenario such
934 * as:
935 * pf A takes the port lock.
936 * pf B succeeds in taking the same lock since they are from the same port.
937 * pf A takes the per pf misc lock. Performs eeprom access.
938 * pf A finishes. Unlocks the per pf misc lock.
939 * Pf B takes the lock and proceeds to perform it's own access.
940 * pf A unlocks the per port lock, while pf B is still working (!).
941 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
942 * acess corrupted by pf B).*
943 */
de0c62db
DK		 944static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
945{
946 int port = BP_PORT(bp);
947 int count, i;
f16da43b
AE		 948 u32 val;
949
950 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
951 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 952
953 /* adjust timeout for emulation/FPGA */
754a2f52 954 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 955 if (CHIP_REV_IS_SLOW(bp))
956 count *= 100;
957
958 /* request access to nvram interface */
959 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
960 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
961
962 for (i = 0; i < count*10; i++) {
963 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
964 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
965 break;
966
967 udelay(5);
968 }
969
970 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 971 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
972 "cannot get access to nvram interface\n");
de0c62db
DK		 973 return -EBUSY;
974 }
975
976 return 0;
977}
978
979static int bnx2x_release_nvram_lock(struct bnx2x *bp)
980{
981 int port = BP_PORT(bp);
982 int count, i;
f16da43b 983 u32 val;
de0c62db
DK		 984
985 /* adjust timeout for emulation/FPGA */
754a2f52 986 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 987 if (CHIP_REV_IS_SLOW(bp))
988 count *= 100;
989
990 /* relinquish nvram interface */
991 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
992 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
993
994 for (i = 0; i < count*10; i++) {
995 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
996 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
997 break;
998
999 udelay(5);
1000 }
1001
1002 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 1003 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1004 "cannot free access to nvram interface\n");
de0c62db
DK		 1005 return -EBUSY;
1006 }
1007
f16da43b
AE		 1008 /* release HW lock: protect against other PFs in PF Direct Assignment */
1009 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1010 return 0;
1011}
1012
1013static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1014{
1015 u32 val;
1016
1017 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1018
1019 /* enable both bits, even on read */
1020 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1021 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1022 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1023}
1024
1025static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1026{
1027 u32 val;
1028
1029 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1030
1031 /* disable both bits, even after read */
1032 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1033 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1034 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1035}
1036
1037static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1038 u32 cmd_flags)
1039{
1040 int count, i, rc;
1041 u32 val;
1042
1043 /* build the command word */
1044 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1045
1046 /* need to clear DONE bit separately */
1047 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1048
1049 /* address of the NVRAM to read from */
1050 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1051 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1052
1053 /* issue a read command */
1054 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1055
1056 /* adjust timeout for emulation/FPGA */
754a2f52 1057 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1058 if (CHIP_REV_IS_SLOW(bp))
1059 count *= 100;
1060
1061 /* wait for completion */
1062 *ret_val = 0;
1063 rc = -EBUSY;
1064 for (i = 0; i < count; i++) {
1065 udelay(5);
1066 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1067
1068 if (val & MCPR_NVM_COMMAND_DONE) {
1069 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1070 /* we read nvram data in cpu order
1071 * but ethtool sees it as an array of bytes
1072 * converting to big-endian will do the work */
1073 *ret_val = cpu_to_be32(val);
1074 rc = 0;
1075 break;
1076 }
1077 }
51c1a580
MS		 1078 if (rc == -EBUSY)
1079 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1080 "nvram read timeout expired\n");
de0c62db
DK		 1081 return rc;
1082}
1083
1084static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1085 int buf_size)
1086{
1087 int rc;
1088 u32 cmd_flags;
1089 __be32 val;
1090
1091 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1092 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1093 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1094 offset, buf_size);
1095 return -EINVAL;
1096 }
1097
1098 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1099 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1100 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1101 offset, buf_size, bp->common.flash_size);
1102 return -EINVAL;
1103 }
1104
1105 /* request access to nvram interface */
1106 rc = bnx2x_acquire_nvram_lock(bp);
1107 if (rc)
1108 return rc;
1109
1110 /* enable access to nvram interface */
1111 bnx2x_enable_nvram_access(bp);
1112
1113 /* read the first word(s) */
1114 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1115 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1116 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1117 memcpy(ret_buf, &val, 4);
1118
1119 /* advance to the next dword */
1120 offset += sizeof(u32);
1121 ret_buf += sizeof(u32);
1122 buf_size -= sizeof(u32);
1123 cmd_flags = 0;
1124 }
1125
1126 if (rc == 0) {
1127 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1128 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1129 memcpy(ret_buf, &val, 4);
1130 }
1131
1132 /* disable access to nvram interface */
1133 bnx2x_disable_nvram_access(bp);
1134 bnx2x_release_nvram_lock(bp);
1135
1136 return rc;
1137}
1138
1139static int bnx2x_get_eeprom(struct net_device *dev,
1140 struct ethtool_eeprom *eeprom, u8 *eebuf)
1141{
1142 struct bnx2x *bp = netdev_priv(dev);
1143 int rc;
1144
51c1a580
MS		 1145 if (!netif_running(dev)) {
1146 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1147 "cannot access eeprom when the interface is down\n");
de0c62db 1148 return -EAGAIN;
51c1a580 1149 }
de0c62db 1150
51c1a580 1151 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1152 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1153 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1154 eeprom->len, eeprom->len);
1155
1156 /* parameters already validated in ethtool_get_eeprom */
1157
1158 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1159
1160 return rc;
1161}
1162
24ea818e
YM		 1163static int bnx2x_get_module_eeprom(struct net_device *dev,
1164 struct ethtool_eeprom *ee,
1165 u8 *data)
1166{
1167 struct bnx2x *bp = netdev_priv(dev);
1168 int rc = 0, phy_idx;
1169 u8 *user_data = data;
1170 int remaining_len = ee->len, xfer_size;
1171 unsigned int page_off = ee->offset;
1172
1173 if (!netif_running(dev)) {
1174 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1175 "cannot access eeprom when the interface is down\n");
1176 return -EAGAIN;
1177 }
1178
1179 phy_idx = bnx2x_get_cur_phy_idx(bp);
1180 bnx2x_acquire_phy_lock(bp);
1181 while (!rc && remaining_len > 0) {
1182 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1183 SFP_EEPROM_PAGE_SIZE : remaining_len;
1184 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1185 &bp->link_params,
1186 page_off,
1187 xfer_size,
1188 user_data);
1189 remaining_len -= xfer_size;
1190 user_data += xfer_size;
1191 page_off += xfer_size;
1192 }
1193
1194 bnx2x_release_phy_lock(bp);
1195 return rc;
1196}
1197
1198static int bnx2x_get_module_info(struct net_device *dev,
1199 struct ethtool_modinfo *modinfo)
1200{
1201 struct bnx2x *bp = netdev_priv(dev);
1202 int phy_idx;
1203 if (!netif_running(dev)) {
1204 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1205 "cannot access eeprom when the interface is down\n");
1206 return -EAGAIN;
1207 }
1208
1209 phy_idx = bnx2x_get_cur_phy_idx(bp);
1210 switch (bp->link_params.phy[phy_idx].media_type) {
1211 case ETH_PHY_SFPP_10G_FIBER:
1212 case ETH_PHY_SFP_1G_FIBER:
1213 case ETH_PHY_DA_TWINAX:
1214 modinfo->type = ETH_MODULE_SFF_8079;
1215 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1216 return 0;
1217 default:
1218 return -EOPNOTSUPP;
1219 }
1220}
1221
de0c62db
DK		 1222static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1223 u32 cmd_flags)
1224{
1225 int count, i, rc;
1226
1227 /* build the command word */
1228 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1229
1230 /* need to clear DONE bit separately */
1231 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1232
1233 /* write the data */
1234 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1235
1236 /* address of the NVRAM to write to */
1237 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1238 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1239
1240 /* issue the write command */
1241 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1242
1243 /* adjust timeout for emulation/FPGA */
754a2f52 1244 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1245 if (CHIP_REV_IS_SLOW(bp))
1246 count *= 100;
1247
1248 /* wait for completion */
1249 rc = -EBUSY;
1250 for (i = 0; i < count; i++) {
1251 udelay(5);
1252 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1253 if (val & MCPR_NVM_COMMAND_DONE) {
1254 rc = 0;
1255 break;
1256 }
1257 }
1258
51c1a580
MS		 1259 if (rc == -EBUSY)
1260 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1261 "nvram write timeout expired\n");
de0c62db
DK		 1262 return rc;
1263}
1264
1265#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1266
1267static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1268 int buf_size)
1269{
1270 int rc;
1271 u32 cmd_flags;
1272 u32 align_offset;
1273 __be32 val;
1274
1275 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1276 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1277 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1278 offset, buf_size, bp->common.flash_size);
1279 return -EINVAL;
1280 }
1281
1282 /* request access to nvram interface */
1283 rc = bnx2x_acquire_nvram_lock(bp);
1284 if (rc)
1285 return rc;
1286
1287 /* enable access to nvram interface */
1288 bnx2x_enable_nvram_access(bp);
1289
1290 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1291 align_offset = (offset & ~0x03);
1292 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1293
1294 if (rc == 0) {
1295 val &= ~(0xff << BYTE_OFFSET(offset));
1296 val |= (*data_buf << BYTE_OFFSET(offset));
1297
1298 /* nvram data is returned as an array of bytes
1299 * convert it back to cpu order */
1300 val = be32_to_cpu(val);
1301
1302 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1303 cmd_flags);
1304 }
1305
1306 /* disable access to nvram interface */
1307 bnx2x_disable_nvram_access(bp);
1308 bnx2x_release_nvram_lock(bp);
1309
1310 return rc;
1311}
1312
1313static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1314 int buf_size)
1315{
1316 int rc;
1317 u32 cmd_flags;
1318 u32 val;
1319 u32 written_so_far;
1320
1321 if (buf_size == 1) /* ethtool */
1322 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1323
1324 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1325 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1326 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1327 offset, buf_size);
1328 return -EINVAL;
1329 }
1330
1331 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1332 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1333 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1334 offset, buf_size, bp->common.flash_size);
1335 return -EINVAL;
1336 }
1337
1338 /* request access to nvram interface */
1339 rc = bnx2x_acquire_nvram_lock(bp);
1340 if (rc)
1341 return rc;
1342
1343 /* enable access to nvram interface */
1344 bnx2x_enable_nvram_access(bp);
1345
1346 written_so_far = 0;
1347 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1348 while ((written_so_far < buf_size) && (rc == 0)) {
1349 if (written_so_far == (buf_size - sizeof(u32)))
1350 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1351 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1352 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1353 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1354 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1355
1356 memcpy(&val, data_buf, 4);
1357
1358 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1359
1360 /* advance to the next dword */
1361 offset += sizeof(u32);
1362 data_buf += sizeof(u32);
1363 written_so_far += sizeof(u32);
1364 cmd_flags = 0;
1365 }
1366
1367 /* disable access to nvram interface */
1368 bnx2x_disable_nvram_access(bp);
1369 bnx2x_release_nvram_lock(bp);
1370
1371 return rc;
1372}
1373
1374static int bnx2x_set_eeprom(struct net_device *dev,
1375 struct ethtool_eeprom *eeprom, u8 *eebuf)
1376{
1377 struct bnx2x *bp = netdev_priv(dev);
1378 int port = BP_PORT(bp);
1379 int rc = 0;
e10bc84d 1380 u32 ext_phy_config;
51c1a580
MS		 1381 if (!netif_running(dev)) {
1382 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1383 "cannot access eeprom when the interface is down\n");
de0c62db 1384 return -EAGAIN;
51c1a580 1385 }
de0c62db 1386
51c1a580 1387 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1388 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1389 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1390 eeprom->len, eeprom->len);
1391
1392 /* parameters already validated in ethtool_set_eeprom */
1393
1394 /* PHY eeprom can be accessed only by the PMF */
1395 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1396 !bp->port.pmf) {
1397 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1398 "wrong magic or interface is not pmf\n");
de0c62db 1399 return -EINVAL;
51c1a580 1400 }
de0c62db 1401
e10bc84d
YR		 1402 ext_phy_config =
1403 SHMEM_RD(bp,
1404 dev_info.port_hw_config[port].external_phy_config);
1405
de0c62db
DK		 1406 if (eeprom->magic == 0x50485950) {
1407 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1408 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1409
1410 bnx2x_acquire_phy_lock(bp);
1411 rc |= bnx2x_link_reset(&bp->link_params,
1412 &bp->link_vars, 0);
e10bc84d 1413 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1414 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1415 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1416 MISC_REGISTERS_GPIO_HIGH, port);
1417 bnx2x_release_phy_lock(bp);
1418 bnx2x_link_report(bp);
1419
1420 } else if (eeprom->magic == 0x50485952) {
1421 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1422 if (bp->state == BNX2X_STATE_OPEN) {
1423 bnx2x_acquire_phy_lock(bp);
1424 rc |= bnx2x_link_reset(&bp->link_params,
1425 &bp->link_vars, 1);
1426
1427 rc |= bnx2x_phy_init(&bp->link_params,
1428 &bp->link_vars);
1429 bnx2x_release_phy_lock(bp);
1430 bnx2x_calc_fc_adv(bp);
1431 }
1432 } else if (eeprom->magic == 0x53985943) {
1433 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1434 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1435 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1436
1437 /* DSP Remove Download Mode */
1438 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1439 MISC_REGISTERS_GPIO_LOW, port);
1440
1441 bnx2x_acquire_phy_lock(bp);
1442
e10bc84d
YR		 1443 bnx2x_sfx7101_sp_sw_reset(bp,
1444 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1445
1446 /* wait 0.5 sec to allow it to run */
1447 msleep(500);
1448 bnx2x_ext_phy_hw_reset(bp, port);
1449 msleep(500);
1450 bnx2x_release_phy_lock(bp);
1451 }
1452 } else
1453 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1454
1455 return rc;
1456}
f85582f8 1457
de0c62db
DK		 1458static int bnx2x_get_coalesce(struct net_device *dev,
1459 struct ethtool_coalesce *coal)
1460{
1461 struct bnx2x *bp = netdev_priv(dev);
1462
1463 memset(coal, 0, sizeof(struct ethtool_coalesce));
1464
1465 coal->rx_coalesce_usecs = bp->rx_ticks;
1466 coal->tx_coalesce_usecs = bp->tx_ticks;
1467
1468 return 0;
1469}
1470
1471static int bnx2x_set_coalesce(struct net_device *dev,
1472 struct ethtool_coalesce *coal)
1473{
1474 struct bnx2x *bp = netdev_priv(dev);
1475
1476 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1477 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1478 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1479
1480 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1481 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1482 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1483
1484 if (netif_running(dev))
1485 bnx2x_update_coalesce(bp);
1486
1487 return 0;
1488}
1489
1490static void bnx2x_get_ringparam(struct net_device *dev,
1491 struct ethtool_ringparam *ering)
1492{
1493 struct bnx2x *bp = netdev_priv(dev);
1494
1495 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1496
25141580
DK		 1497 if (bp->rx_ring_size)
1498 ering->rx_pending = bp->rx_ring_size;
1499 else
c2188952 1500 ering->rx_pending = MAX_RX_AVAIL;
25141580 1501
a3348722 1502 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1503 ering->tx_pending = bp->tx_ring_size;
1504}
1505
1506static int bnx2x_set_ringparam(struct net_device *dev,
1507 struct ethtool_ringparam *ering)
1508{
1509 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1510
1511 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1512 DP(BNX2X_MSG_ETHTOOL,
1513 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1514 return -EAGAIN;
1515 }
1516
1517 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1518 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1519 MIN_RX_SIZE_TPA)) ||
a3348722 1520 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1521 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1522 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1523 return -EINVAL;
51c1a580 1524 }
de0c62db
DK		 1525
1526 bp->rx_ring_size = ering->rx_pending;
1527 bp->tx_ring_size = ering->tx_pending;
1528
a9fccec7 1529 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1530}
1531
1532static void bnx2x_get_pauseparam(struct net_device *dev,
1533 struct ethtool_pauseparam *epause)
1534{
1535 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1536 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1537 int cfg_reg;
1538
a22f0788
YR		 1539 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1540 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1541
9e7e8399 1542 if (!epause->autoneg)
241fb5d2 1543 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1544 else
1545 cfg_reg = bp->link_params.req_fc_auto_adv;
1546
1547 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1548 BNX2X_FLOW_CTRL_RX);
9e7e8399 1549 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1550 BNX2X_FLOW_CTRL_TX);
1551
51c1a580 1552 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1553 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1554 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1555}
1556
1557static int bnx2x_set_pauseparam(struct net_device *dev,
1558 struct ethtool_pauseparam *epause)
1559{
1560 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1561 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1562 if (IS_MF(bp))
de0c62db
DK		 1563 return 0;
1564
51c1a580 1565 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1566 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1567 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1568
a22f0788 1569 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1570
1571 if (epause->rx_pause)
a22f0788 1572 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1573
1574 if (epause->tx_pause)
a22f0788 1575 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1576
a22f0788
YR		 1577 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1578 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1579
1580 if (epause->autoneg) {
a22f0788 1581 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1582 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1583 return -EINVAL;
1584 }
1585
a22f0788
YR		 1586 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1587 bp->link_params.req_flow_ctrl[cfg_idx] =
1588 BNX2X_FLOW_CTRL_AUTO;
1589 }
de0c62db
DK		 1590 }
1591
51c1a580 1592 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1593 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1594
1595 if (netif_running(dev)) {
1596 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1597 bnx2x_link_set(bp);
1598 }
1599
1600 return 0;
1601}
1602
ebe6e21d 1603static char *bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF] = {
cf2c1df6
MS		 1604 "register_test (offline) ",
1605 "memory_test (offline) ",
1606 "int_loopback_test (offline)",
1607 "ext_loopback_test (offline)",
1608 "nvram_test (online) ",
1609 "interrupt_test (online) ",
1610 "link_test (online) "
de0c62db
DK		 1611};
1612
e9939c80
YM		 1613static u32 bnx2x_eee_to_adv(u32 eee_adv)
1614{
1615 u32 modes = 0;
1616
1617 if (eee_adv & SHMEM_EEE_100M_ADV)
1618 modes |= ADVERTISED_100baseT_Full;
1619 if (eee_adv & SHMEM_EEE_1G_ADV)
1620 modes |= ADVERTISED_1000baseT_Full;
1621 if (eee_adv & SHMEM_EEE_10G_ADV)
1622 modes |= ADVERTISED_10000baseT_Full;
1623
1624 return modes;
1625}
1626
1627static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1628{
1629 u32 eee_adv = 0;
1630 if (modes & ADVERTISED_100baseT_Full)
1631 eee_adv |= SHMEM_EEE_100M_ADV;
1632 if (modes & ADVERTISED_1000baseT_Full)
1633 eee_adv |= SHMEM_EEE_1G_ADV;
1634 if (modes & ADVERTISED_10000baseT_Full)
1635 eee_adv |= SHMEM_EEE_10G_ADV;
1636
1637 return eee_adv << shift;
1638}
1639
1640static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1641{
1642 struct bnx2x *bp = netdev_priv(dev);
1643 u32 eee_cfg;
1644
1645 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1646 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1647 return -EOPNOTSUPP;
1648 }
1649
1650 eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1651
1652 edata->supported =
1653 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1654 SHMEM_EEE_SUPPORTED_SHIFT);
1655
1656 edata->advertised =
1657 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1658 SHMEM_EEE_ADV_STATUS_SHIFT);
1659 edata->lp_advertised =
1660 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1661 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1662
1663 /* SHMEM value is in 16u units --> Convert to 1u units. */
1664 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1665
1666 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1667 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1668 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1669
1670 return 0;
1671}
1672
1673static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1674{
1675 struct bnx2x *bp = netdev_priv(dev);
1676 u32 eee_cfg;
1677 u32 advertised;
1678
1679 if (IS_MF(bp))
1680 return 0;
1681
1682 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1683 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1684 return -EOPNOTSUPP;
1685 }
1686
1687 eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1688
1689 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1690 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1691 return -EOPNOTSUPP;
1692 }
1693
1694 advertised = bnx2x_adv_to_eee(edata->advertised,
1695 SHMEM_EEE_ADV_STATUS_SHIFT);
1696 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1697 DP(BNX2X_MSG_ETHTOOL,
1698 "Direct manipulation of EEE advertisment is not supported\n");
1699 return -EINVAL;
1700 }
1701
1702 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1703 DP(BNX2X_MSG_ETHTOOL,
1704 "Maximal Tx Lpi timer supported is %x(u)\n",
1705 EEE_MODE_TIMER_MASK);
1706 return -EINVAL;
1707 }
1708 if (edata->tx_lpi_enabled &&
1709 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1710 DP(BNX2X_MSG_ETHTOOL,
1711 "Minimal Tx Lpi timer supported is %d(u)\n",
1712 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1713 return -EINVAL;
1714 }
1715
1716 /* All is well; Apply changes*/
1717 if (edata->eee_enabled)
1718 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1719 else
1720 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1721
1722 if (edata->tx_lpi_enabled)
1723 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1724 else
1725 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1726
1727 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1728 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1729 EEE_MODE_TIMER_MASK) |
1730 EEE_MODE_OVERRIDE_NVRAM |
1731 EEE_MODE_OUTPUT_TIME;
1732
1733 /* Restart link to propogate changes */
1734 if (netif_running(dev)) {
1735 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1736 bnx2x_link_set(bp);
1737 }
1738
1739 return 0;
1740}
1741
1742
619c5cb6
VZ		 1743enum {
1744 BNX2X_CHIP_E1_OFST = 0,
1745 BNX2X_CHIP_E1H_OFST,
1746 BNX2X_CHIP_E2_OFST,
1747 BNX2X_CHIP_E3_OFST,
1748 BNX2X_CHIP_E3B0_OFST,
1749 BNX2X_CHIP_MAX_OFST
1750};
1751
1752#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1753#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1754#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1755#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1756#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1757
1758#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1759#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1760
de0c62db
DK		 1761static int bnx2x_test_registers(struct bnx2x *bp)
1762{
1763 int idx, i, rc = -ENODEV;
619c5cb6 1764 u32 wr_val = 0, hw;
de0c62db
DK		 1765 int port = BP_PORT(bp);
1766 static const struct {
619c5cb6 1767 u32 hw;
de0c62db
DK		 1768 u32 offset0;
1769 u32 offset1;
1770 u32 mask;
1771 } reg_tbl[] = {
619c5cb6
VZ		 1772/* 0 */ { BNX2X_CHIP_MASK_ALL,
1773 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1774 { BNX2X_CHIP_MASK_ALL,
1775 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1776 { BNX2X_CHIP_MASK_E1X,
1777 HC_REG_AGG_INT_0, 4, 0x000003ff },
1778 { BNX2X_CHIP_MASK_ALL,
1779 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1780 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1781 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1782 { BNX2X_CHIP_MASK_E3B0,
1783 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1784 { BNX2X_CHIP_MASK_ALL,
1785 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1786 { BNX2X_CHIP_MASK_ALL,
1787 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1788 { BNX2X_CHIP_MASK_ALL,
1789 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1790 { BNX2X_CHIP_MASK_ALL,
1791 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1792/* 10 */ { BNX2X_CHIP_MASK_ALL,
1793 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1794 { BNX2X_CHIP_MASK_ALL,
1795 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1796 { BNX2X_CHIP_MASK_ALL,
1797 QM_REG_CONNNUM_0, 4, 0x000fffff },
1798 { BNX2X_CHIP_MASK_ALL,
1799 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1800 { BNX2X_CHIP_MASK_ALL,
1801 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1802 { BNX2X_CHIP_MASK_ALL,
1803 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1804 { BNX2X_CHIP_MASK_ALL,
1805 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1806 { BNX2X_CHIP_MASK_ALL,
1807 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1808 { BNX2X_CHIP_MASK_ALL,
1809 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1810 { BNX2X_CHIP_MASK_ALL,
1811 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1812/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1813 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1814 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1815 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1816 { BNX2X_CHIP_MASK_ALL,
1817 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1818 { BNX2X_CHIP_MASK_ALL,
1819 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1820 { BNX2X_CHIP_MASK_ALL,
1821 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1822 { BNX2X_CHIP_MASK_ALL,
1823 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1824 { BNX2X_CHIP_MASK_ALL,
1825 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1826 { BNX2X_CHIP_MASK_ALL,
1827 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1828 { BNX2X_CHIP_MASK_ALL,
1829 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1830 { BNX2X_CHIP_MASK_ALL,
1831 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1832/* 30 */ { BNX2X_CHIP_MASK_ALL,
1833 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1834 { BNX2X_CHIP_MASK_ALL,
1835 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1836 { BNX2X_CHIP_MASK_ALL,
1837 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1838 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1839 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1840 { BNX2X_CHIP_MASK_ALL,
1841 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1842 { BNX2X_CHIP_MASK_ALL,
1843 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1844 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1845 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1846 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1847 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1848
1849 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1850 };
1851
51c1a580
MS		 1852 if (!netif_running(bp->dev)) {
1853 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1854 "cannot access eeprom when the interface is down\n");
de0c62db 1855 return rc;
51c1a580 1856 }
de0c62db 1857
619c5cb6
VZ		 1858 if (CHIP_IS_E1(bp))
1859 hw = BNX2X_CHIP_MASK_E1;
1860 else if (CHIP_IS_E1H(bp))
1861 hw = BNX2X_CHIP_MASK_E1H;
1862 else if (CHIP_IS_E2(bp))
1863 hw = BNX2X_CHIP_MASK_E2;
1864 else if (CHIP_IS_E3B0(bp))
1865 hw = BNX2X_CHIP_MASK_E3B0;
1866 else /* e3 A0 */
1867 hw = BNX2X_CHIP_MASK_E3;
1868
de0c62db
DK		 1869 /* Repeat the test twice:
1870 First by writing 0x00000000, second by writing 0xffffffff */
1871 for (idx = 0; idx < 2; idx++) {
1872
1873 switch (idx) {
1874 case 0:
1875 wr_val = 0;
1876 break;
1877 case 1:
1878 wr_val = 0xffffffff;
1879 break;
1880 }
1881
1882 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1883 u32 offset, mask, save_val, val;
619c5cb6 1884 if (!(hw & reg_tbl[i].hw))
f2e0899f 1885 continue;
de0c62db
DK		 1886
1887 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1888 mask = reg_tbl[i].mask;
1889
1890 save_val = REG_RD(bp, offset);
1891
ec6ba945 1892 REG_WR(bp, offset, wr_val & mask);
f85582f8 1893
de0c62db
DK		 1894 val = REG_RD(bp, offset);
1895
1896 /* Restore the original register's value */
1897 REG_WR(bp, offset, save_val);
1898
1899 /* verify value is as expected */
1900 if ((val & mask) != (wr_val & mask)) {
51c1a580 1901 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1902 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1903 offset, val, wr_val, mask);
1904 goto test_reg_exit;
1905 }
1906 }
1907 }
1908
1909 rc = 0;
1910
1911test_reg_exit:
1912 return rc;
1913}
1914
1915static int bnx2x_test_memory(struct bnx2x *bp)
1916{
1917 int i, j, rc = -ENODEV;
619c5cb6 1918 u32 val, index;
de0c62db
DK		 1919 static const struct {
1920 u32 offset;
1921 int size;
1922 } mem_tbl[] = {
1923 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1924 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1925 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1926 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1927 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1928 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1929 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1930
1931 { 0xffffffff, 0 }
1932 };
619c5cb6 1933
de0c62db
DK		 1934 static const struct {
1935 char *name;
1936 u32 offset;
619c5cb6 1937 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1938 } prty_tbl[] = {
619c5cb6
VZ		 1939 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1940 {0x3ffc0, 0, 0, 0} },
1941 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1942 {0x2, 0x2, 0, 0} },
1943 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1944 {0, 0, 0, 0} },
1945 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1946 {0x3ffc0, 0, 0, 0} },
1947 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1948 {0x3ffc0, 0, 0, 0} },
1949 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1950 {0x3ffc1, 0, 0, 0} },
1951
1952 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1953 };
1954
51c1a580
MS		 1955 if (!netif_running(bp->dev)) {
1956 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1957 "cannot access eeprom when the interface is down\n");
de0c62db 1958 return rc;
51c1a580 1959 }
de0c62db 1960
619c5cb6
VZ		 1961 if (CHIP_IS_E1(bp))
1962 index = BNX2X_CHIP_E1_OFST;
1963 else if (CHIP_IS_E1H(bp))
1964 index = BNX2X_CHIP_E1H_OFST;
1965 else if (CHIP_IS_E2(bp))
1966 index = BNX2X_CHIP_E2_OFST;
1967 else /* e3 */
1968 index = BNX2X_CHIP_E3_OFST;
1969
f2e0899f
DK		 1970 /* pre-Check the parity status */
1971 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1972 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1973 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1974 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 1975 "%s is 0x%x\n", prty_tbl[i].name, val);
1976 goto test_mem_exit;
1977 }
1978 }
1979
de0c62db
DK		 1980 /* Go through all the memories */
1981 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1982 for (j = 0; j < mem_tbl[i].size; j++)
1983 REG_RD(bp, mem_tbl[i].offset + j*4);
1984
1985 /* Check the parity status */
1986 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1987 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1988 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1989 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1990 "%s is 0x%x\n", prty_tbl[i].name, val);
1991 goto test_mem_exit;
1992 }
1993 }
1994
1995 rc = 0;
1996
1997test_mem_exit:
1998 return rc;
1999}
2000
a22f0788 2001static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 2002{
f2e0899f 2003 int cnt = 1400;
de0c62db 2004
619c5cb6 2005 if (link_up) {
a22f0788 2006 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 2007 msleep(20);
2008
2009 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 2010 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 2011
2012 cnt = 1400;
2013 while (!bp->link_vars.link_up && cnt--)
2014 msleep(20);
2015
2016 if (cnt <= 0 && !bp->link_vars.link_up)
2017 DP(BNX2X_MSG_ETHTOOL,
2018 "Timeout waiting for link init\n");
619c5cb6 2019 }
de0c62db
DK		 2020}
2021
619c5cb6 2022static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 2023{
2024 unsigned int pkt_size, num_pkts, i;
2025 struct sk_buff *skb;
2026 unsigned char *packet;
2027 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2028 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 2029 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 2030 u16 tx_start_idx, tx_idx;
2031 u16 rx_start_idx, rx_idx;
b0700b1e 2032 u16 pkt_prod, bd_prod;
de0c62db
DK		 2033 struct sw_tx_bd *tx_buf;
2034 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 2035 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
2036 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 2037 dma_addr_t mapping;
2038 union eth_rx_cqe *cqe;
619c5cb6 2039 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 2040 struct sw_rx_bd *rx_buf;
2041 u16 len;
2042 int rc = -ENODEV;
e52fcb24 2043 u8 *data;
8970b2e4
MS		 2044 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2045 txdata->txq_index);
de0c62db
DK		 2046
2047 /* check the loopback mode */
2048 switch (loopback_mode) {
2049 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 2050 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2051 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 2052 return -EINVAL;
8970b2e4 2053 }
de0c62db
DK		 2054 break;
2055 case BNX2X_MAC_LOOPBACK:
32911333
YR		 2056 if (CHIP_IS_E3(bp)) {
2057 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2058 if (bp->port.supported[cfg_idx] &
2059 (SUPPORTED_10000baseT_Full |
2060 SUPPORTED_20000baseMLD2_Full |
2061 SUPPORTED_20000baseKR2_Full))
2062 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2063 else
2064 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2065 } else
2066 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2067
de0c62db
DK		 2068 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2069 break;
8970b2e4
MS		 2070 case BNX2X_EXT_LOOPBACK:
2071 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2072 DP(BNX2X_MSG_ETHTOOL,
2073 "Can't configure external loopback\n");
2074 return -EINVAL;
2075 }
2076 break;
de0c62db 2077 default:
51c1a580 2078 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2079 return -EINVAL;
2080 }
2081
2082 /* prepare the loopback packet */
2083 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2084 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2085 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2086 if (!skb) {
51c1a580 2087 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2088 rc = -ENOMEM;
2089 goto test_loopback_exit;
2090 }
2091 packet = skb_put(skb, pkt_size);
2092 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2093 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2094 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2095 for (i = ETH_HLEN; i < pkt_size; i++)
2096 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2097 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2098 skb_headlen(skb), DMA_TO_DEVICE);
2099 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2100 rc = -ENOMEM;
2101 dev_kfree_skb(skb);
51c1a580 2102 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2103 goto test_loopback_exit;
2104 }
de0c62db
DK		 2105
2106 /* send the loopback packet */
2107 num_pkts = 0;
6383c0b3 2108 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2109 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2110
73dbb5e1
DK		 2111 netdev_tx_sent_queue(txq, skb->len);
2112
6383c0b3
AE		 2113 pkt_prod = txdata->tx_pkt_prod++;
2114 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2115 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2116 tx_buf->skb = skb;
2117 tx_buf->flags = 0;
2118
6383c0b3
AE		 2119 bd_prod = TX_BD(txdata->tx_bd_prod);
2120 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2121 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2122 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2123 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2124 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2125 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2126 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2127 SET_FLAG(tx_start_bd->general_data,
2128 ETH_TX_START_BD_ETH_ADDR_TYPE,
2129 UNICAST_ADDRESS);
2130 SET_FLAG(tx_start_bd->general_data,
2131 ETH_TX_START_BD_HDR_NBDS,
2132 1);
de0c62db
DK		 2133
2134 /* turn on parsing and get a BD */
2135 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2136
6383c0b3
AE		 2137 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2138 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 2139
f2e0899f 2140 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 2141 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 2142
2143 wmb();
2144
6383c0b3 2145 txdata->tx_db.data.prod += 2;
de0c62db 2146 barrier();
6383c0b3 2147 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2148
2149 mmiowb();
619c5cb6 2150 barrier();
de0c62db
DK		 2151
2152 num_pkts++;
6383c0b3 2153 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2154
2155 udelay(100);
2156
6383c0b3 2157 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2158 if (tx_idx != tx_start_idx + num_pkts)
2159 goto test_loopback_exit;
2160
f2e0899f
DK		 2161 /* Unlike HC IGU won't generate an interrupt for status block
2162 * updates that have been performed while interrupts were
2163 * disabled.
2164 */
e1210d12
ED		 2165 if (bp->common.int_block == INT_BLOCK_IGU) {
2166 /* Disable local BHes to prevent a dead-lock situation between
2167 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2168 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2169 */
2170 local_bh_disable();
6383c0b3 2171 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2172 local_bh_enable();
2173 }
f2e0899f 2174
de0c62db
DK		 2175 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2176 if (rx_idx != rx_start_idx + num_pkts)
2177 goto test_loopback_exit;
2178
b0700b1e 2179 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2180 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2181 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2182 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2183 goto test_loopback_rx_exit;
2184
621b4d66 2185 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2186 if (len != pkt_size)
2187 goto test_loopback_rx_exit;
2188
2189 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2190 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2191 dma_unmap_addr(rx_buf, mapping),
2192 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2193 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2194 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2195 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2196 goto test_loopback_rx_exit;
2197
2198 rc = 0;
2199
2200test_loopback_rx_exit:
2201
2202 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2203 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2204 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2205 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2206
2207 /* Update producers */
2208 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2209 fp_rx->rx_sge_prod);
2210
2211test_loopback_exit:
2212 bp->link_params.loopback_mode = LOOPBACK_NONE;
2213
2214 return rc;
2215}
2216
619c5cb6 2217static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2218{
2219 int rc = 0, res;
2220
2221 if (BP_NOMCP(bp))
2222 return rc;
2223
2224 if (!netif_running(bp->dev))
2225 return BNX2X_LOOPBACK_FAILED;
2226
2227 bnx2x_netif_stop(bp, 1);
2228 bnx2x_acquire_phy_lock(bp);
2229
619c5cb6 2230 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2231 if (res) {
51c1a580 2232 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2233 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2234 }
2235
619c5cb6 2236 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2237 if (res) {
51c1a580 2238 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2239 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2240 }
2241
2242 bnx2x_release_phy_lock(bp);
2243 bnx2x_netif_start(bp);
2244
2245 return rc;
2246}
2247
8970b2e4
MS		 2248static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2249{
2250 int rc;
2251 u8 is_serdes =
2252 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2253
2254 if (BP_NOMCP(bp))
2255 return -ENODEV;
2256
2257 if (!netif_running(bp->dev))
2258 return BNX2X_EXT_LOOPBACK_FAILED;
2259
2260 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2261 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2262 if (rc) {
2263 DP(BNX2X_MSG_ETHTOOL,
2264 "Can't perform self-test, nic_load (for external lb) failed\n");
2265 return -ENODEV;
2266 }
2267 bnx2x_wait_for_link(bp, 1, is_serdes);
2268
2269 bnx2x_netif_stop(bp, 1);
2270
2271 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2272 if (rc)
2273 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2274
2275 bnx2x_netif_start(bp);
2276
2277 return rc;
2278}
2279
de0c62db
DK		 2280#define CRC32_RESIDUAL 0xdebb20e3
2281
2282static int bnx2x_test_nvram(struct bnx2x *bp)
2283{
2284 static const struct {
2285 int offset;
2286 int size;
2287 } nvram_tbl[] = {
2288 { 0, 0x14 }, /* bootstrap */
2289 { 0x14, 0xec }, /* dir */
2290 { 0x100, 0x350 }, /* manuf_info */
2291 { 0x450, 0xf0 }, /* feature_info */
2292 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2293 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2294 { 0, 0 }
2295 };
afa13b4b
MY		 2296 __be32 *buf;
2297 u8 *data;
de0c62db
DK		 2298 int i, rc;
2299 u32 magic, crc;
2300
2301 if (BP_NOMCP(bp))
2302 return 0;
2303
afa13b4b
MY		 2304 buf = kmalloc(0x350, GFP_KERNEL);
2305 if (!buf) {
51c1a580 2306 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2307 rc = -ENOMEM;
2308 goto test_nvram_exit;
2309 }
2310 data = (u8 *)buf;
2311
de0c62db
DK		 2312 rc = bnx2x_nvram_read(bp, 0, data, 4);
2313 if (rc) {
51c1a580
MS		 2314 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2315 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2316 goto test_nvram_exit;
2317 }
2318
2319 magic = be32_to_cpu(buf[0]);
2320 if (magic != 0x669955aa) {
51c1a580
MS		 2321 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2322 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2323 rc = -ENODEV;
2324 goto test_nvram_exit;
2325 }
2326
2327 for (i = 0; nvram_tbl[i].size; i++) {
2328
2329 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2330 nvram_tbl[i].size);
2331 if (rc) {
51c1a580 2332 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2333 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2334 goto test_nvram_exit;
2335 }
2336
2337 crc = ether_crc_le(nvram_tbl[i].size, data);
2338 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2339 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2340 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2341 rc = -ENODEV;
2342 goto test_nvram_exit;
2343 }
2344 }
2345
2346test_nvram_exit:
afa13b4b 2347 kfree(buf);
de0c62db
DK		 2348 return rc;
2349}
2350
619c5cb6 2351/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2352static int bnx2x_test_intr(struct bnx2x *bp)
2353{
3b603066 2354 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2355
51c1a580
MS		 2356 if (!netif_running(bp->dev)) {
2357 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2358 "cannot access eeprom when the interface is down\n");
de0c62db 2359 return -ENODEV;
51c1a580 2360 }
de0c62db 2361
15192a8c 2362 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2363 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2364
619c5cb6
VZ		 2365 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2366
2367 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2368}
2369
2370static void bnx2x_self_test(struct net_device *dev,
2371 struct ethtool_test *etest, u64 *buf)
2372{
2373 struct bnx2x *bp = netdev_priv(dev);
a22f0788 2374 u8 is_serdes;
cf2c1df6
MS		 2375 int rc;
2376
de0c62db 2377 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2378 netdev_err(bp->dev,
2379 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2380 etest->flags |= ETH_TEST_FL_FAILED;
2381 return;
2382 }
8970b2e4
MS		 2383 DP(BNX2X_MSG_ETHTOOL,
2384 "Self-test command parameters: offline = %d, external_lb = %d\n",
2385 (etest->flags & ETH_TEST_FL_OFFLINE),
2386 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2387
cf2c1df6 2388 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2389
cf2c1df6
MS		 2390 if (!netif_running(dev)) {
2391 DP(BNX2X_MSG_ETHTOOL,
2392 "Can't perform self-test when interface is down\n");
de0c62db 2393 return;
cf2c1df6 2394 }
de0c62db 2395
a22f0788 2396 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db 2397
cf2c1df6
MS		 2398 /* offline tests are not supported in MF mode */
2399 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2400 int port = BP_PORT(bp);
2401 u32 val;
2402 u8 link_up;
2403
2404 /* save current value of input enable for TX port IF */
2405 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2406 /* disable input for TX port IF */
2407 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2408
a22f0788
YR		 2409 link_up = bp->link_vars.link_up;
2410
de0c62db 2411 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
cf2c1df6
MS		 2412 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2413 if (rc) {
2414 etest->flags |= ETH_TEST_FL_FAILED;
2415 DP(BNX2X_MSG_ETHTOOL,
2416 "Can't perform self-test, nic_load (for offline) failed\n");
2417 return;
2418 }
2419
de0c62db 2420 /* wait until link state is restored */
619c5cb6 2421 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2422
2423 if (bnx2x_test_registers(bp) != 0) {
2424 buf[0] = 1;
2425 etest->flags |= ETH_TEST_FL_FAILED;
2426 }
2427 if (bnx2x_test_memory(bp) != 0) {
2428 buf[1] = 1;
2429 etest->flags |= ETH_TEST_FL_FAILED;
2430 }
f85582f8 2431
8970b2e4 2432 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2433 if (buf[2] != 0)
2434 etest->flags |= ETH_TEST_FL_FAILED;
2435
8970b2e4
MS		 2436 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2437 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2438 if (buf[3] != 0)
2439 etest->flags |= ETH_TEST_FL_FAILED;
2440 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2441 }
2442
de0c62db
DK		 2443 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2444
2445 /* restore input for TX port IF */
2446 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2447 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2448 if (rc) {
2449 etest->flags |= ETH_TEST_FL_FAILED;
2450 DP(BNX2X_MSG_ETHTOOL,
2451 "Can't perform self-test, nic_load (for online) failed\n");
2452 return;
2453 }
de0c62db 2454 /* wait until link state is restored */
a22f0788 2455 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2456 }
2457 if (bnx2x_test_nvram(bp) != 0) {
cf2c1df6
MS		 2458 if (!IS_MF(bp))
2459 buf[4] = 1;
2460 else
2461 buf[0] = 1;
de0c62db
DK		 2462 etest->flags |= ETH_TEST_FL_FAILED;
2463 }
2464 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 2465 if (!IS_MF(bp))
2466 buf[5] = 1;
2467 else
2468 buf[1] = 1;
de0c62db
DK		 2469 etest->flags |= ETH_TEST_FL_FAILED;
2470 }
633ac363
DK		 2471
2472 if (bnx2x_link_test(bp, is_serdes) != 0) {
cf2c1df6
MS		 2473 if (!IS_MF(bp))
2474 buf[6] = 1;
2475 else
2476 buf[2] = 1;
633ac363
DK		 2477 etest->flags |= ETH_TEST_FL_FAILED;
2478 }
de0c62db
DK		 2479
2480#ifdef BNX2X_EXTRA_DEBUG
2481 bnx2x_panic_dump(bp);
2482#endif
2483}
2484
de0c62db
DK		 2485#define IS_PORT_STAT(i) \
2486 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2487#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2488#define IS_MF_MODE_STAT(bp) \
2489 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2490
619c5cb6
VZ		 2491/* ethtool statistics are displayed for all regular ethernet queues and the
2492 * fcoe L2 queue if not disabled
2493 */
1191cb83 2494static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2495{
2496 return BNX2X_NUM_ETH_QUEUES(bp);
2497}
2498
de0c62db
DK		 2499static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2500{
2501 struct bnx2x *bp = netdev_priv(dev);
2502 int i, num_stats;
2503
2504 switch (stringset) {
2505 case ETH_SS_STATS:
2506 if (is_multi(bp)) {
619c5cb6 2507 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2508 BNX2X_NUM_Q_STATS;
2509 } else
2510 num_stats = 0;
2511 if (IS_MF_MODE_STAT(bp)) {
2512 for (i = 0; i < BNX2X_NUM_STATS; i++)
2513 if (IS_FUNC_STAT(i))
2514 num_stats++;
2515 } else
2516 num_stats += BNX2X_NUM_STATS;
2517
de0c62db
DK		 2518 return num_stats;
2519
2520 case ETH_SS_TEST:
cf2c1df6 2521 return BNX2X_NUM_TESTS(bp);
de0c62db
DK		 2522
2523 default:
2524 return -EINVAL;
2525 }
2526}
2527
2528static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2529{
2530 struct bnx2x *bp = netdev_priv(dev);
cf2c1df6 2531 int i, j, k, offset, start;
ec6ba945 2532 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2533
2534 switch (stringset) {
2535 case ETH_SS_STATS:
d5e83632 2536 k = 0;
de0c62db 2537 if (is_multi(bp)) {
619c5cb6 2538 for_each_eth_queue(bp, i) {
ec6ba945 2539 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2540 sprintf(queue_name, "%d", i);
de0c62db 2541 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2542 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2543 ETH_GSTRING_LEN,
2544 bnx2x_q_stats_arr[j].string,
2545 queue_name);
de0c62db
DK		 2546 k += BNX2X_NUM_Q_STATS;
2547 }
de0c62db 2548 }
d5e83632
YM		 2549
2550
2551 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2552 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2553 continue;
2554 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2555 bnx2x_stats_arr[i].string);
2556 j++;
2557 }
2558
de0c62db
DK		 2559 break;
2560
2561 case ETH_SS_TEST:
cf2c1df6
MS		 2562 /* First 4 tests cannot be done in MF mode */
2563 if (!IS_MF(bp))
2564 start = 0;
2565 else
2566 start = 4;
2567 for (i = 0, j = start; j < (start + BNX2X_NUM_TESTS(bp));
2568 i++, j++) {
2569 offset = sprintf(buf+32*i, "%s",
2570 bnx2x_tests_str_arr[j]);
2571 *(buf+offset) = '\0';
2572 }
de0c62db
DK		 2573 break;
2574 }
2575}
2576
2577static void bnx2x_get_ethtool_stats(struct net_device *dev,
2578 struct ethtool_stats *stats, u64 *buf)
2579{
2580 struct bnx2x *bp = netdev_priv(dev);
2581 u32 *hw_stats, *offset;
d5e83632 2582 int i, j, k = 0;
de0c62db
DK		 2583
2584 if (is_multi(bp)) {
619c5cb6 2585 for_each_eth_queue(bp, i) {
15192a8c 2586 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 2587 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2588 if (bnx2x_q_stats_arr[j].size == 0) {
2589 /* skip this counter */
2590 buf[k + j] = 0;
2591 continue;
2592 }
2593 offset = (hw_stats +
2594 bnx2x_q_stats_arr[j].offset);
2595 if (bnx2x_q_stats_arr[j].size == 4) {
2596 /* 4-byte counter */
2597 buf[k + j] = (u64) *offset;
2598 continue;
2599 }
2600 /* 8-byte counter */
2601 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2602 }
2603 k += BNX2X_NUM_Q_STATS;
2604 }
d5e83632
YM		 2605 }
2606
2607 hw_stats = (u32 *)&bp->eth_stats;
2608 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2609 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2610 continue;
2611 if (bnx2x_stats_arr[i].size == 0) {
2612 /* skip this counter */
2613 buf[k + j] = 0;
2614 j++;
2615 continue;
de0c62db 2616 }
d5e83632
YM		 2617 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2618 if (bnx2x_stats_arr[i].size == 4) {
2619 /* 4-byte counter */
2620 buf[k + j] = (u64) *offset;
de0c62db 2621 j++;
d5e83632 2622 continue;
de0c62db 2623 }
d5e83632
YM		 2624 /* 8-byte counter */
2625 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2626 j++;
de0c62db
DK		 2627 }
2628}
2629
32d36134 2630static int bnx2x_set_phys_id(struct net_device *dev,
2631 enum ethtool_phys_id_state state)
de0c62db
DK		 2632{
2633 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2634
51c1a580
MS		 2635 if (!netif_running(dev)) {
2636 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2637 "cannot access eeprom when the interface is down\n");
32d36134 2638 return -EAGAIN;
51c1a580 2639 }
de0c62db 2640
51c1a580
MS		 2641 if (!bp->port.pmf) {
2642 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2643 return -EOPNOTSUPP;
51c1a580 2644 }
de0c62db 2645
32d36134 2646 switch (state) {
2647 case ETHTOOL_ID_ACTIVE:
fce55922 2648 return 1; /* cycle on/off once per second */
de0c62db 2649
32d36134 2650 case ETHTOOL_ID_ON:
2651 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2652 LED_MODE_ON, SPEED_1000);
32d36134 2653 break;
de0c62db 2654
32d36134 2655 case ETHTOOL_ID_OFF:
2656 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2657 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2658
32d36134 2659 break;
2660
2661 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2662 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2663 LED_MODE_OPER,
2664 bp->link_vars.line_speed);
32d36134 2665 }
de0c62db
DK		 2666
2667 return 0;
2668}
2669
5d317c6a
MS		 2670static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2671{
2672
2673 switch (info->flow_type) {
2674 case TCP_V4_FLOW:
2675 case TCP_V6_FLOW:
2676 info->data = RXH_IP_SRC | RXH_IP_DST |
2677 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2678 break;
2679 case UDP_V4_FLOW:
2680 if (bp->rss_conf_obj.udp_rss_v4)
2681 info->data = RXH_IP_SRC | RXH_IP_DST |
2682 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2683 else
2684 info->data = RXH_IP_SRC | RXH_IP_DST;
2685 break;
2686 case UDP_V6_FLOW:
2687 if (bp->rss_conf_obj.udp_rss_v6)
2688 info->data = RXH_IP_SRC | RXH_IP_DST |
2689 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2690 else
2691 info->data = RXH_IP_SRC | RXH_IP_DST;
2692 break;
2693 case IPV4_FLOW:
2694 case IPV6_FLOW:
2695 info->data = RXH_IP_SRC | RXH_IP_DST;
2696 break;
2697 default:
2698 info->data = 0;
2699 break;
2700 }
2701
2702 return 0;
2703}
2704
ab532cf3 2705static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2706 u32 *rules __always_unused)
ab532cf3
TH		 2707{
2708 struct bnx2x *bp = netdev_priv(dev);
2709
2710 switch (info->cmd) {
2711 case ETHTOOL_GRXRINGS:
2712 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2713 return 0;
5d317c6a
MS		 2714 case ETHTOOL_GRXFH:
2715 return bnx2x_get_rss_flags(bp, info);
2716 default:
2717 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2718 return -EOPNOTSUPP;
2719 }
2720}
2721
2722static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2723{
2724 int udp_rss_requested;
2725
2726 DP(BNX2X_MSG_ETHTOOL,
2727 "Set rss flags command parameters: flow type = %d, data = %llu\n",
2728 info->flow_type, info->data);
2729
2730 switch (info->flow_type) {
2731 case TCP_V4_FLOW:
2732 case TCP_V6_FLOW:
2733 /* For TCP only 4-tupple hash is supported */
2734 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2735 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2736 DP(BNX2X_MSG_ETHTOOL,
2737 "Command parameters not supported\n");
2738 return -EINVAL;
2739 } else {
2740 return 0;
2741 }
2742
2743 case UDP_V4_FLOW:
2744 case UDP_V6_FLOW:
2745 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2746 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2747 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2748 udp_rss_requested = 1;
2749 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2750 udp_rss_requested = 0;
2751 else
2752 return -EINVAL;
2753 if ((info->flow_type == UDP_V4_FLOW) &&
2754 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2755 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2756 DP(BNX2X_MSG_ETHTOOL,
2757 "rss re-configured, UDP 4-tupple %s\n",
2758 udp_rss_requested ? "enabled" : "disabled");
2759 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2760 } else if ((info->flow_type == UDP_V6_FLOW) &&
2761 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
2762 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
2763 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2764 DP(BNX2X_MSG_ETHTOOL,
2765 "rss re-configured, UDP 4-tupple %s\n",
2766 udp_rss_requested ? "enabled" : "disabled");
2767 } else {
2768 return 0;
2769 }
2770 case IPV4_FLOW:
2771 case IPV6_FLOW:
2772 /* For IP only 2-tupple hash is supported */
2773 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
2774 DP(BNX2X_MSG_ETHTOOL,
2775 "Command parameters not supported\n");
2776 return -EINVAL;
2777 } else {
2778 return 0;
2779 }
2780 case SCTP_V4_FLOW:
2781 case AH_ESP_V4_FLOW:
2782 case AH_V4_FLOW:
2783 case ESP_V4_FLOW:
2784 case SCTP_V6_FLOW:
2785 case AH_ESP_V6_FLOW:
2786 case AH_V6_FLOW:
2787 case ESP_V6_FLOW:
2788 case IP_USER_FLOW:
2789 case ETHER_FLOW:
2790 /* RSS is not supported for these protocols */
2791 if (info->data) {
2792 DP(BNX2X_MSG_ETHTOOL,
2793 "Command parameters not supported\n");
2794 return -EINVAL;
2795 } else {
2796 return 0;
2797 }
2798 default:
2799 return -EINVAL;
2800 }
2801}
2802
2803static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
2804{
2805 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 2806
5d317c6a
MS		 2807 switch (info->cmd) {
2808 case ETHTOOL_SRXFH:
2809 return bnx2x_set_rss_flags(bp, info);
ab532cf3 2810 default:
51c1a580 2811 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 2812 return -EOPNOTSUPP;
2813 }
2814}
2815
7850f63f
BH		 2816static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2817{
96305234 2818 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 2819}
2820
2821static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 2822{
2823 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 2824 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2825 size_t i;
ab532cf3 2826
619c5cb6
VZ		 2827 /* Get the current configuration of the RSS indirection table */
2828 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2829
2830 /*
2831 * We can't use a memcpy() as an internal storage of an
2832 * indirection table is a u8 array while indir->ring_index
2833 * points to an array of u32.
2834 *
2835 * Indirection table contains the FW Client IDs, so we need to
2836 * align the returned table to the Client ID of the leading RSS
2837 * queue.
2838 */
7850f63f
BH		 2839 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2840 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 2841
ab532cf3
TH		 2842 return 0;
2843}
2844
7850f63f 2845static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 2846{
2847 struct bnx2x *bp = netdev_priv(dev);
2848 size_t i;
619c5cb6
VZ		 2849
2850 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 2851 /*
2852 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2853 * as an internal storage of an indirection table is a u8 array
2854 * while indir->ring_index points to an array of u32.
2855 *
2856 * Indirection table contains the FW Client IDs, so we need to
2857 * align the received table to the Client ID of the leading RSS
2858 * queue
2859 */
5d317c6a 2860 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 2861 }
ab532cf3 2862
5d317c6a 2863 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 2864}
2865
0e8d2ec5
MS		 2866/**
2867 * bnx2x_get_channels - gets the number of RSS queues.
2868 *
2869 * @dev: net device
2870 * @channels: returns the number of max / current queues
2871 */
2872static void bnx2x_get_channels(struct net_device *dev,
2873 struct ethtool_channels *channels)
2874{
2875 struct bnx2x *bp = netdev_priv(dev);
2876
2877 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
2878 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
2879}
2880
2881/**
2882 * bnx2x_change_num_queues - change the number of RSS queues.
2883 *
2884 * @bp: bnx2x private structure
2885 *
2886 * Re-configure interrupt mode to get the new number of MSI-X
2887 * vectors and re-add NAPI objects.
2888 */
2889static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
2890{
0e8d2ec5
MS		 2891 bnx2x_disable_msi(bp);
2892 BNX2X_NUM_QUEUES(bp) = num_rss + NON_ETH_CONTEXT_USE;
2893 bnx2x_set_int_mode(bp);
0e8d2ec5
MS		 2894}
2895
2896/**
2897 * bnx2x_set_channels - sets the number of RSS queues.
2898 *
2899 * @dev: net device
2900 * @channels: includes the number of queues requested
2901 */
2902static int bnx2x_set_channels(struct net_device *dev,
2903 struct ethtool_channels *channels)
2904{
2905 struct bnx2x *bp = netdev_priv(dev);
2906
2907
2908 DP(BNX2X_MSG_ETHTOOL,
2909 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
2910 channels->rx_count, channels->tx_count, channels->other_count,
2911 channels->combined_count);
2912
2913 /* We don't support separate rx / tx channels.
2914 * We don't allow setting 'other' channels.
2915 */
2916 if (channels->rx_count || channels->tx_count || channels->other_count
2917 || (channels->combined_count == 0) ||
2918 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
2919 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
2920 return -EINVAL;
2921 }
2922
2923 /* Check if there was a change in the active parameters */
2924 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
2925 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
2926 return 0;
2927 }
2928
2929 /* Set the requested number of queues in bp context.
2930 * Note that the actual number of queues created during load may be
2931 * less than requested if memory is low.
2932 */
2933 if (unlikely(!netif_running(dev))) {
2934 bnx2x_change_num_queues(bp, channels->combined_count);
2935 return 0;
2936 }
2937 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2938 bnx2x_change_num_queues(bp, channels->combined_count);
2939 return bnx2x_nic_load(bp, LOAD_NORMAL);
2940}
2941
de0c62db
DK		 2942static const struct ethtool_ops bnx2x_ethtool_ops = {
2943 .get_settings = bnx2x_get_settings,
2944 .set_settings = bnx2x_set_settings,
2945 .get_drvinfo = bnx2x_get_drvinfo,
2946 .get_regs_len = bnx2x_get_regs_len,
2947 .get_regs = bnx2x_get_regs,
2948 .get_wol = bnx2x_get_wol,
2949 .set_wol = bnx2x_set_wol,
2950 .get_msglevel = bnx2x_get_msglevel,
2951 .set_msglevel = bnx2x_set_msglevel,
2952 .nway_reset = bnx2x_nway_reset,
2953 .get_link = bnx2x_get_link,
2954 .get_eeprom_len = bnx2x_get_eeprom_len,
2955 .get_eeprom = bnx2x_get_eeprom,
2956 .set_eeprom = bnx2x_set_eeprom,
2957 .get_coalesce = bnx2x_get_coalesce,
2958 .set_coalesce = bnx2x_set_coalesce,
2959 .get_ringparam = bnx2x_get_ringparam,
2960 .set_ringparam = bnx2x_set_ringparam,
2961 .get_pauseparam = bnx2x_get_pauseparam,
2962 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2963 .self_test = bnx2x_self_test,
2964 .get_sset_count = bnx2x_get_sset_count,
2965 .get_strings = bnx2x_get_strings,
32d36134 2966 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2967 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 2968 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 2969 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 2970 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 2971 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2972 .set_rxfh_indir = bnx2x_set_rxfh_indir,
0e8d2ec5
MS		 2973 .get_channels = bnx2x_get_channels,
2974 .set_channels = bnx2x_set_channels,
24ea818e
YM		 2975 .get_module_info = bnx2x_get_module_info,
2976 .get_module_eeprom = bnx2x_get_module_eeprom,
e9939c80
YM		 2977 .get_eee = bnx2x_get_eee,
2978 .set_eee = bnx2x_set_eee,
be53ce1e 2979 .get_ts_info = ethtool_op_get_ts_info,
de0c62db
DK		 2980};
2981
2982void bnx2x_set_ethtool_ops(struct net_device *netdev)
2983{
2984 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2985}
kernel source for telekom puls (alcatel/mediatek)