projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mlx4_en: Byte Queue Limit support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 66};
67
68#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70static const struct {
71 long offset;
72 int size;
73 u32 flags;
74#define STATS_FLAGS_PORT 1
75#define STATS_FLAGS_FUNC 2
76#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78} bnx2x_stats_arr[] = {
79/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 107 { STATS_OFFSET32(pfc_frames_received_hi),
108 8, STATS_FLAGS_PORT, "pfc_frames_received" },
109 { STATS_OFFSET32(pfc_frames_sent_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 111 { STATS_OFFSET32(brb_drop_hi),
112 8, STATS_FLAGS_PORT, "rx_brb_discard" },
113 { STATS_OFFSET32(brb_truncate_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
115 { STATS_OFFSET32(pause_frames_received_hi),
116 8, STATS_FLAGS_PORT, "rx_pause_frames" },
117 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
118 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
119 { STATS_OFFSET32(nig_timer_max),
120 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
121/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
122 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
123 { STATS_OFFSET32(rx_skb_alloc_failed),
124 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
125 { STATS_OFFSET32(hw_csum_err),
126 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
127
128 { STATS_OFFSET32(total_bytes_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bytes" },
130 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
131 8, STATS_FLAGS_PORT, "tx_error_bytes" },
132 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
134 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
136 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
138 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
139 8, STATS_FLAGS_PORT, "tx_mac_errors" },
140 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
141 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
142/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
143 8, STATS_FLAGS_PORT, "tx_single_collisions" },
144 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
147 8, STATS_FLAGS_PORT, "tx_deferred" },
148 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
150 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_late_collisions" },
152 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_total_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
155 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
157 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
159 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
161 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
162/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
163 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
164 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
165 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
166 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
168 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 169 8, STATS_FLAGS_PORT, "tx_pause_frames" },
170 { STATS_OFFSET32(total_tpa_aggregations_hi),
171 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
172 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
174 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 175 8, STATS_FLAGS_FUNC, "tpa_bytes"},
176 { STATS_OFFSET32(recoverable_error),
177 4, STATS_FLAGS_FUNC, "recoverable_errors" },
178 { STATS_OFFSET32(unrecoverable_error),
179 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
ec6ba945
VZ		 180};
181
182#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 183static int bnx2x_get_port_type(struct bnx2x *bp)
184{
185 int port_type;
186 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
187 switch (bp->link_params.phy[phy_idx].media_type) {
188 case ETH_PHY_SFP_FIBER:
189 case ETH_PHY_XFP_FIBER:
190 case ETH_PHY_KR:
191 case ETH_PHY_CX4:
192 port_type = PORT_FIBRE;
193 break;
194 case ETH_PHY_DA_TWINAX:
195 port_type = PORT_DA;
196 break;
197 case ETH_PHY_BASE_T:
198 port_type = PORT_TP;
199 break;
200 case ETH_PHY_NOT_PRESENT:
201 port_type = PORT_NONE;
202 break;
203 case ETH_PHY_UNSPECIFIED:
204 default:
205 port_type = PORT_OTHER;
206 break;
207 }
208 return port_type;
209}
ec6ba945 210
de0c62db
DK		 211static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
212{
213 struct bnx2x *bp = netdev_priv(dev);
a22f0788 214 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 215
a22f0788
YR		 216 /* Dual Media boards present all available port types */
217 cmd->supported = bp->port.supported[cfg_idx] |
218 (bp->port.supported[cfg_idx ^ 1] &
219 (SUPPORTED_TP | SUPPORTED_FIBRE));
220 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db 221
38298461
YM		 222 if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
223 if (!(bp->flags & MF_FUNC_DIS)) {
224 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
225 cmd->duplex = bp->link_vars.duplex;
226 } else {
227 ethtool_cmd_speed_set(
228 cmd, bp->link_params.req_line_speed[cfg_idx]);
229 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
230 }
231
232 if (IS_MF(bp) && !BP_NOMCP(bp))
233 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 234 } else {
38298461
YM		 235 cmd->duplex = DUPLEX_UNKNOWN;
236 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 237 }
f2e0899f 238
1ac9e428 239 cmd->port = bnx2x_get_port_type(bp);
a22f0788 240
de0c62db
DK		 241 cmd->phy_address = bp->mdio.prtad;
242 cmd->transceiver = XCVR_INTERNAL;
243
a22f0788 244 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 245 cmd->autoneg = AUTONEG_ENABLE;
246 else
247 cmd->autoneg = AUTONEG_DISABLE;
248
9e7e8399
MY		 249 /* Publish LP advertised speeds and FC */
250 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
251 u32 status = bp->link_vars.link_status;
252
253 cmd->lp_advertising |= ADVERTISED_Autoneg;
254 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
255 cmd->lp_advertising |= ADVERTISED_Pause;
256 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
257 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
258
259 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
260 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
261 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
262 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
263 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
264 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
265 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
266 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
267 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
268 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
269 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
270 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
271 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
272 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
273 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
274 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
275 }
276
de0c62db
DK		 277 cmd->maxtxpkt = 0;
278 cmd->maxrxpkt = 0;
279
51c1a580 280 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 281 " supported 0x%x advertising 0x%x speed %u\n"
282 " duplex %d port %d phy_address %d transceiver %d\n"
283 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 284 cmd->cmd, cmd->supported, cmd->advertising,
285 ethtool_cmd_speed(cmd),
de0c62db
DK		 286 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
287 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
288
289 return 0;
290}
291
292static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
293{
294 struct bnx2x *bp = netdev_priv(dev);
a22f0788 295 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 296 u32 speed;
de0c62db 297
0793f83f 298 if (IS_MF_SD(bp))
de0c62db
DK		 299 return 0;
300
51c1a580 301 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 302 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 303 " duplex %d port %d phy_address %d transceiver %d\n"
304 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 305 cmd->cmd, cmd->supported, cmd->advertising,
306 ethtool_cmd_speed(cmd),
de0c62db
DK		 307 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
308 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
309
b3337e4c 310 speed = ethtool_cmd_speed(cmd);
0793f83f 311
38298461
YM		 312 /* If recieved a request for an unknown duplex, assume full*/
313 if (cmd->duplex == DUPLEX_UNKNOWN)
314 cmd->duplex = DUPLEX_FULL;
315
0793f83f 316 if (IS_MF_SI(bp)) {
e3835b99 317 u32 part;
0793f83f
DK		 318 u32 line_speed = bp->link_vars.line_speed;
319
320 /* use 10G if no link detected */
321 if (!line_speed)
322 line_speed = 10000;
323
324 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 325 DP(BNX2X_MSG_ETHTOOL,
326 "To set speed BC %X or higher is required, please upgrade BC\n",
327 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 328 return -EINVAL;
329 }
e3835b99 330
faa6fcbb 331 part = (speed * 100) / line_speed;
e3835b99 332
faa6fcbb 333 if (line_speed < speed || !part) {
51c1a580
MS		 334 DP(BNX2X_MSG_ETHTOOL,
335 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 336 return -EINVAL;
337 }
0793f83f 338
e3835b99
DK		 339 if (bp->state != BNX2X_STATE_OPEN)
340 /* store value for following "load" */
341 bp->pending_max = part;
342 else
343 bnx2x_update_max_mf_config(bp, part);
0793f83f 344
0793f83f
DK		 345 return 0;
346 }
347
a22f0788
YR		 348 cfg_idx = bnx2x_get_link_cfg_idx(bp);
349 old_multi_phy_config = bp->link_params.multi_phy_config;
350 switch (cmd->port) {
351 case PORT_TP:
352 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
353 break; /* no port change */
354
355 if (!(bp->port.supported[0] & SUPPORTED_TP ||
356 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 357 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 358 return -EINVAL;
359 }
360 bp->link_params.multi_phy_config &=
361 ~PORT_HW_CFG_PHY_SELECTION_MASK;
362 if (bp->link_params.multi_phy_config &
363 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
364 bp->link_params.multi_phy_config |=
365 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
366 else
367 bp->link_params.multi_phy_config |=
368 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
369 break;
370 case PORT_FIBRE:
bfdb5823 371 case PORT_DA:
a22f0788
YR		 372 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
373 break; /* no port change */
374
375 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
376 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 377 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 378 return -EINVAL;
379 }
380 bp->link_params.multi_phy_config &=
381 ~PORT_HW_CFG_PHY_SELECTION_MASK;
382 if (bp->link_params.multi_phy_config &
383 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
384 bp->link_params.multi_phy_config |=
385 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
386 else
387 bp->link_params.multi_phy_config |=
388 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
389 break;
390 default:
51c1a580 391 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 392 return -EINVAL;
393 }
2f751a80 394 /* Save new config in case command complete successully */
a22f0788
YR		 395 new_multi_phy_config = bp->link_params.multi_phy_config;
396 /* Get the new cfg_idx */
397 cfg_idx = bnx2x_get_link_cfg_idx(bp);
398 /* Restore old config in case command failed */
399 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 400 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 401
de0c62db 402 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 403 u32 an_supported_speed = bp->port.supported[cfg_idx];
404 if (bp->link_params.phy[EXT_PHY1].type ==
405 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
406 an_supported_speed |= (SUPPORTED_100baseT_Half |
407 SUPPORTED_100baseT_Full);
a22f0788 408 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 409 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 410 return -EINVAL;
411 }
412
413 /* advertise the requested speed and duplex if supported */
75318327 414 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 415 DP(BNX2X_MSG_ETHTOOL,
416 "Advertisement parameters are not supported\n");
8d661637
YR		 417 return -EINVAL;
418 }
de0c62db 419
a22f0788 420 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 421 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
422 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 423 cmd->advertising);
8d661637
YR		 424 if (cmd->advertising) {
425
426 bp->link_params.speed_cap_mask[cfg_idx] = 0;
427 if (cmd->advertising & ADVERTISED_10baseT_Half) {
428 bp->link_params.speed_cap_mask[cfg_idx] |=
429 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
430 }
431 if (cmd->advertising & ADVERTISED_10baseT_Full)
432 bp->link_params.speed_cap_mask[cfg_idx] |=
433 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 434
8d661637
YR		 435 if (cmd->advertising & ADVERTISED_100baseT_Full)
436 bp->link_params.speed_cap_mask[cfg_idx] |=
437 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
438
439 if (cmd->advertising & ADVERTISED_100baseT_Half) {
440 bp->link_params.speed_cap_mask[cfg_idx] |=
441 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
442 }
443 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
444 bp->link_params.speed_cap_mask[cfg_idx] |=
445 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
446 }
447 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
448 ADVERTISED_1000baseKX_Full))
449 bp->link_params.speed_cap_mask[cfg_idx] |=
450 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
451
452 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
453 ADVERTISED_10000baseKX4_Full |
454 ADVERTISED_10000baseKR_Full))
455 bp->link_params.speed_cap_mask[cfg_idx] |=
456 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
457 }
de0c62db
DK		 458 } else { /* forced speed */
459 /* advertise the requested speed and duplex if supported */
a22f0788 460 switch (speed) {
de0c62db
DK		 461 case SPEED_10:
462 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 463 if (!(bp->port.supported[cfg_idx] &
de0c62db 464 SUPPORTED_10baseT_Full)) {
51c1a580 465 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 466 "10M full not supported\n");
467 return -EINVAL;
468 }
469
470 advertising = (ADVERTISED_10baseT_Full |
471 ADVERTISED_TP);
472 } else {
a22f0788 473 if (!(bp->port.supported[cfg_idx] &
de0c62db 474 SUPPORTED_10baseT_Half)) {
51c1a580 475 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 476 "10M half not supported\n");
477 return -EINVAL;
478 }
479
480 advertising = (ADVERTISED_10baseT_Half |
481 ADVERTISED_TP);
482 }
483 break;
484
485 case SPEED_100:
486 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 487 if (!(bp->port.supported[cfg_idx] &
de0c62db 488 SUPPORTED_100baseT_Full)) {
51c1a580 489 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 490 "100M full not supported\n");
491 return -EINVAL;
492 }
493
494 advertising = (ADVERTISED_100baseT_Full |
495 ADVERTISED_TP);
496 } else {
a22f0788 497 if (!(bp->port.supported[cfg_idx] &
de0c62db 498 SUPPORTED_100baseT_Half)) {
51c1a580 499 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 500 "100M half not supported\n");
501 return -EINVAL;
502 }
503
504 advertising = (ADVERTISED_100baseT_Half |
505 ADVERTISED_TP);
506 }
507 break;
508
509 case SPEED_1000:
510 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 511 DP(BNX2X_MSG_ETHTOOL,
512 "1G half not supported\n");
de0c62db
DK		 513 return -EINVAL;
514 }
515
a22f0788
YR		 516 if (!(bp->port.supported[cfg_idx] &
517 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 518 DP(BNX2X_MSG_ETHTOOL,
519 "1G full not supported\n");
de0c62db
DK		 520 return -EINVAL;
521 }
522
523 advertising = (ADVERTISED_1000baseT_Full |
524 ADVERTISED_TP);
525 break;
526
527 case SPEED_2500:
528 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 529 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 530 "2.5G half not supported\n");
531 return -EINVAL;
532 }
533
a22f0788
YR		 534 if (!(bp->port.supported[cfg_idx]
535 & SUPPORTED_2500baseX_Full)) {
51c1a580 536 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 537 "2.5G full not supported\n");
538 return -EINVAL;
539 }
540
541 advertising = (ADVERTISED_2500baseX_Full |
542 ADVERTISED_TP);
543 break;
544
545 case SPEED_10000:
546 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 547 DP(BNX2X_MSG_ETHTOOL,
548 "10G half not supported\n");
de0c62db
DK		 549 return -EINVAL;
550 }
551
a22f0788
YR		 552 if (!(bp->port.supported[cfg_idx]
553 & SUPPORTED_10000baseT_Full)) {
51c1a580
MS		 554 DP(BNX2X_MSG_ETHTOOL,
555 "10G full not supported\n");
de0c62db
DK		 556 return -EINVAL;
557 }
558
559 advertising = (ADVERTISED_10000baseT_Full |
560 ADVERTISED_FIBRE);
561 break;
562
563 default:
51c1a580 564 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 565 return -EINVAL;
566 }
567
a22f0788
YR		 568 bp->link_params.req_line_speed[cfg_idx] = speed;
569 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
570 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 571 }
572
51c1a580 573 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 574 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 575 bp->link_params.req_line_speed[cfg_idx],
576 bp->link_params.req_duplex[cfg_idx],
577 bp->port.advertising[cfg_idx]);
de0c62db 578
a22f0788
YR		 579 /* Set new config */
580 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 581 if (netif_running(dev)) {
582 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
583 bnx2x_link_set(bp);
584 }
585
586 return 0;
587}
588
589#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
590#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 591#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 592#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
593#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
594
595static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
596 const struct reg_addr *reg_info)
597{
598 if (CHIP_IS_E1(bp))
599 return IS_E1_ONLINE(reg_info->info);
600 else if (CHIP_IS_E1H(bp))
601 return IS_E1H_ONLINE(reg_info->info);
602 else if (CHIP_IS_E2(bp))
603 return IS_E2_ONLINE(reg_info->info);
604 else if (CHIP_IS_E3A0(bp))
605 return IS_E3_ONLINE(reg_info->info);
606 else if (CHIP_IS_E3B0(bp))
607 return IS_E3B0_ONLINE(reg_info->info);
608 else
609 return false;
610}
611
612/******* Paged registers info selectors ********/
613static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
614{
615 if (CHIP_IS_E2(bp))
616 return page_vals_e2;
617 else if (CHIP_IS_E3(bp))
618 return page_vals_e3;
619 else
620 return NULL;
621}
622
623static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
624{
625 if (CHIP_IS_E2(bp))
626 return PAGE_MODE_VALUES_E2;
627 else if (CHIP_IS_E3(bp))
628 return PAGE_MODE_VALUES_E3;
629 else
630 return 0;
631}
632
633static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
634{
635 if (CHIP_IS_E2(bp))
636 return page_write_regs_e2;
637 else if (CHIP_IS_E3(bp))
638 return page_write_regs_e3;
639 else
640 return NULL;
641}
642
643static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
644{
645 if (CHIP_IS_E2(bp))
646 return PAGE_WRITE_REGS_E2;
647 else if (CHIP_IS_E3(bp))
648 return PAGE_WRITE_REGS_E3;
649 else
650 return 0;
651}
652
653static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
654{
655 if (CHIP_IS_E2(bp))
656 return page_read_regs_e2;
657 else if (CHIP_IS_E3(bp))
658 return page_read_regs_e3;
659 else
660 return NULL;
661}
662
663static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
664{
665 if (CHIP_IS_E2(bp))
666 return PAGE_READ_REGS_E2;
667 else if (CHIP_IS_E3(bp))
668 return PAGE_READ_REGS_E3;
669 else
670 return 0;
671}
672
673static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
674{
675 int num_pages = __bnx2x_get_page_reg_num(bp);
676 int page_write_num = __bnx2x_get_page_write_num(bp);
677 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
678 int page_read_num = __bnx2x_get_page_read_num(bp);
679 int regdump_len = 0;
680 int i, j, k;
681
682 for (i = 0; i < REGS_COUNT; i++)
683 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
684 regdump_len += reg_addrs[i].size;
685
686 for (i = 0; i < num_pages; i++)
687 for (j = 0; j < page_write_num; j++)
688 for (k = 0; k < page_read_num; k++)
689 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
690 regdump_len += page_read_addr[k].size;
691
692 return regdump_len;
693}
de0c62db
DK		 694
695static int bnx2x_get_regs_len(struct net_device *dev)
696{
697 struct bnx2x *bp = netdev_priv(dev);
698 int regdump_len = 0;
de0c62db 699
0fea29c1 700 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 701 regdump_len *= 4;
702 regdump_len += sizeof(struct dump_hdr);
703
704 return regdump_len;
705}
706
0fea29c1
VZ		 707/**
708 * bnx2x_read_pages_regs - read "paged" registers
709 *
710 * @bp device handle
711 * @p output buffer
712 *
713 * Reads "paged" memories: memories that may only be read by first writing to a
714 * specific address ("write address") and then reading from a specific address
715 * ("read address"). There may be more than one write address per "page" and
716 * more than one read address per write address.
717 */
718static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 719{
720 u32 i, j, k, n;
0fea29c1
VZ		 721 /* addresses of the paged registers */
722 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
723 /* number of paged registers */
724 int num_pages = __bnx2x_get_page_reg_num(bp);
725 /* write addresses */
726 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
727 /* number of write addresses */
728 int write_num = __bnx2x_get_page_write_num(bp);
729 /* read addresses info */
730 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
731 /* number of read addresses */
732 int read_num = __bnx2x_get_page_read_num(bp);
733
734 for (i = 0; i < num_pages; i++) {
735 for (j = 0; j < write_num; j++) {
736 REG_WR(bp, write_addr[j], page_addr[i]);
737 for (k = 0; k < read_num; k++)
738 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 739 for (n = 0; n <
0fea29c1 740 read_addr[k].size; n++)
f2e0899f 741 *p++ = REG_RD(bp,
0fea29c1 742 read_addr[k].addr + n*4);
f2e0899f
DK		 743 }
744 }
745}
746
0fea29c1
VZ		 747static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
748{
749 u32 i, j;
750
751 /* Read the regular registers */
752 for (i = 0; i < REGS_COUNT; i++)
753 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
754 for (j = 0; j < reg_addrs[i].size; j++)
755 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
756
757 /* Read "paged" registes */
758 bnx2x_read_pages_regs(bp, p);
759}
760
de0c62db
DK		 761static void bnx2x_get_regs(struct net_device *dev,
762 struct ethtool_regs *regs, void *_p)
763{
0fea29c1 764 u32 *p = _p;
de0c62db
DK		 765 struct bnx2x *bp = netdev_priv(dev);
766 struct dump_hdr dump_hdr = {0};
767
768 regs->version = 0;
769 memset(p, 0, regs->len);
770
771 if (!netif_running(bp->dev))
772 return;
773
4a33bc03
VZ		 774 /* Disable parity attentions as long as following dump may
775 * cause false alarms by reading never written registers. We
776 * will re-enable parity attentions right after the dump.
777 */
778 bnx2x_disable_blocks_parity(bp);
779
de0c62db
DK		 780 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
781 dump_hdr.dump_sign = dump_sign_all;
782 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
783 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
784 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
785 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 786
787 if (CHIP_IS_E1(bp))
788 dump_hdr.info = RI_E1_ONLINE;
789 else if (CHIP_IS_E1H(bp))
790 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 791 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 792 dump_hdr.info = RI_E2_ONLINE |
793 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 794
795 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
796 p += dump_hdr.hdr_size + 1;
797
0fea29c1
VZ		 798 /* Actually read the registers */
799 __bnx2x_get_regs(bp, p);
800
4a33bc03
VZ		 801 /* Re-enable parity attentions */
802 bnx2x_clear_blocks_parity(bp);
c9ee9206 803 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 804}
805
de0c62db
DK		 806static void bnx2x_get_drvinfo(struct net_device *dev,
807 struct ethtool_drvinfo *info)
808{
809 struct bnx2x *bp = netdev_priv(dev);
810 u8 phy_fw_ver[PHY_FW_VER_LEN];
811
68aad78c
RJ		 812 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
813 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db
DK		 814
815 phy_fw_ver[0] = '\0';
a1e785e0
MY		 816 bnx2x_get_ext_phy_fw_version(&bp->link_params,
817 phy_fw_ver, PHY_FW_VER_LEN);
68aad78c 818 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
de0c62db
DK		 819 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
820 "bc %d.%d.%d%s%s",
821 (bp->common.bc_ver & 0xff0000) >> 16,
822 (bp->common.bc_ver & 0xff00) >> 8,
823 (bp->common.bc_ver & 0xff),
824 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
68aad78c 825 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db
DK		 826 info->n_stats = BNX2X_NUM_STATS;
827 info->testinfo_len = BNX2X_NUM_TESTS;
828 info->eedump_len = bp->common.flash_size;
829 info->regdump_len = bnx2x_get_regs_len(dev);
830}
831
832static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
833{
834 struct bnx2x *bp = netdev_priv(dev);
835
836 if (bp->flags & NO_WOL_FLAG) {
837 wol->supported = 0;
838 wol->wolopts = 0;
839 } else {
840 wol->supported = WAKE_MAGIC;
841 if (bp->wol)
842 wol->wolopts = WAKE_MAGIC;
843 else
844 wol->wolopts = 0;
845 }
846 memset(&wol->sopass, 0, sizeof(wol->sopass));
847}
848
849static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
850{
851 struct bnx2x *bp = netdev_priv(dev);
852
51c1a580
MS		 853 if (wol->wolopts & ~WAKE_MAGIC) {
854 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 855 return -EINVAL;
51c1a580 856 }
de0c62db
DK		 857
858 if (wol->wolopts & WAKE_MAGIC) {
51c1a580
MS		 859 if (bp->flags & NO_WOL_FLAG) {
860 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 861 return -EINVAL;
51c1a580 862 }
de0c62db
DK		 863 bp->wol = 1;
864 } else
865 bp->wol = 0;
866
867 return 0;
868}
869
870static u32 bnx2x_get_msglevel(struct net_device *dev)
871{
872 struct bnx2x *bp = netdev_priv(dev);
873
874 return bp->msg_enable;
875}
876
877static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
878{
879 struct bnx2x *bp = netdev_priv(dev);
880
7a25cc73
DK		 881 if (capable(CAP_NET_ADMIN)) {
882 /* dump MCP trace */
883 if (level & BNX2X_MSG_MCP)
884 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 885 bp->msg_enable = level;
7a25cc73 886 }
de0c62db
DK		 887}
888
889static int bnx2x_nway_reset(struct net_device *dev)
890{
891 struct bnx2x *bp = netdev_priv(dev);
892
893 if (!bp->port.pmf)
894 return 0;
895
896 if (netif_running(dev)) {
897 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
898 bnx2x_link_set(bp);
899 }
900
901 return 0;
902}
903
904static u32 bnx2x_get_link(struct net_device *dev)
905{
906 struct bnx2x *bp = netdev_priv(dev);
907
f2e0899f 908 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 909 return 0;
910
911 return bp->link_vars.link_up;
912}
913
914static int bnx2x_get_eeprom_len(struct net_device *dev)
915{
916 struct bnx2x *bp = netdev_priv(dev);
917
918 return bp->common.flash_size;
919}
920
f16da43b
AE		 921/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
922 * we done things the other way around, if two pfs from the same port would
923 * attempt to access nvram at the same time, we could run into a scenario such
924 * as:
925 * pf A takes the port lock.
926 * pf B succeeds in taking the same lock since they are from the same port.
927 * pf A takes the per pf misc lock. Performs eeprom access.
928 * pf A finishes. Unlocks the per pf misc lock.
929 * Pf B takes the lock and proceeds to perform it's own access.
930 * pf A unlocks the per port lock, while pf B is still working (!).
931 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
932 * acess corrupted by pf B).*
933 */
de0c62db
DK		 934static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
935{
936 int port = BP_PORT(bp);
937 int count, i;
f16da43b
AE		 938 u32 val;
939
940 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
941 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 942
943 /* adjust timeout for emulation/FPGA */
754a2f52 944 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 945 if (CHIP_REV_IS_SLOW(bp))
946 count *= 100;
947
948 /* request access to nvram interface */
949 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
950 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
951
952 for (i = 0; i < count*10; i++) {
953 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
954 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
955 break;
956
957 udelay(5);
958 }
959
960 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 961 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
962 "cannot get access to nvram interface\n");
de0c62db
DK		 963 return -EBUSY;
964 }
965
966 return 0;
967}
968
969static int bnx2x_release_nvram_lock(struct bnx2x *bp)
970{
971 int port = BP_PORT(bp);
972 int count, i;
f16da43b 973 u32 val;
de0c62db
DK		 974
975 /* adjust timeout for emulation/FPGA */
754a2f52 976 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 977 if (CHIP_REV_IS_SLOW(bp))
978 count *= 100;
979
980 /* relinquish nvram interface */
981 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
982 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
983
984 for (i = 0; i < count*10; i++) {
985 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
986 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
987 break;
988
989 udelay(5);
990 }
991
992 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 993 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
994 "cannot free access to nvram interface\n");
de0c62db
DK		 995 return -EBUSY;
996 }
997
f16da43b
AE		 998 /* release HW lock: protect against other PFs in PF Direct Assignment */
999 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1000 return 0;
1001}
1002
1003static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1004{
1005 u32 val;
1006
1007 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1008
1009 /* enable both bits, even on read */
1010 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1011 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1012 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1013}
1014
1015static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1016{
1017 u32 val;
1018
1019 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1020
1021 /* disable both bits, even after read */
1022 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1023 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1024 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1025}
1026
1027static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1028 u32 cmd_flags)
1029{
1030 int count, i, rc;
1031 u32 val;
1032
1033 /* build the command word */
1034 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1035
1036 /* need to clear DONE bit separately */
1037 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1038
1039 /* address of the NVRAM to read from */
1040 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1041 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1042
1043 /* issue a read command */
1044 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1045
1046 /* adjust timeout for emulation/FPGA */
754a2f52 1047 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1048 if (CHIP_REV_IS_SLOW(bp))
1049 count *= 100;
1050
1051 /* wait for completion */
1052 *ret_val = 0;
1053 rc = -EBUSY;
1054 for (i = 0; i < count; i++) {
1055 udelay(5);
1056 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1057
1058 if (val & MCPR_NVM_COMMAND_DONE) {
1059 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1060 /* we read nvram data in cpu order
1061 * but ethtool sees it as an array of bytes
1062 * converting to big-endian will do the work */
1063 *ret_val = cpu_to_be32(val);
1064 rc = 0;
1065 break;
1066 }
1067 }
51c1a580
MS		 1068 if (rc == -EBUSY)
1069 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1070 "nvram read timeout expired\n");
de0c62db
DK		 1071 return rc;
1072}
1073
1074static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1075 int buf_size)
1076{
1077 int rc;
1078 u32 cmd_flags;
1079 __be32 val;
1080
1081 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1082 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1083 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1084 offset, buf_size);
1085 return -EINVAL;
1086 }
1087
1088 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1089 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1090 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1091 offset, buf_size, bp->common.flash_size);
1092 return -EINVAL;
1093 }
1094
1095 /* request access to nvram interface */
1096 rc = bnx2x_acquire_nvram_lock(bp);
1097 if (rc)
1098 return rc;
1099
1100 /* enable access to nvram interface */
1101 bnx2x_enable_nvram_access(bp);
1102
1103 /* read the first word(s) */
1104 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1105 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1106 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1107 memcpy(ret_buf, &val, 4);
1108
1109 /* advance to the next dword */
1110 offset += sizeof(u32);
1111 ret_buf += sizeof(u32);
1112 buf_size -= sizeof(u32);
1113 cmd_flags = 0;
1114 }
1115
1116 if (rc == 0) {
1117 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1118 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1119 memcpy(ret_buf, &val, 4);
1120 }
1121
1122 /* disable access to nvram interface */
1123 bnx2x_disable_nvram_access(bp);
1124 bnx2x_release_nvram_lock(bp);
1125
1126 return rc;
1127}
1128
1129static int bnx2x_get_eeprom(struct net_device *dev,
1130 struct ethtool_eeprom *eeprom, u8 *eebuf)
1131{
1132 struct bnx2x *bp = netdev_priv(dev);
1133 int rc;
1134
51c1a580
MS		 1135 if (!netif_running(dev)) {
1136 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1137 "cannot access eeprom when the interface is down\n");
de0c62db 1138 return -EAGAIN;
51c1a580 1139 }
de0c62db 1140
51c1a580 1141 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1142 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1143 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1144 eeprom->len, eeprom->len);
1145
1146 /* parameters already validated in ethtool_get_eeprom */
1147
1148 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1149
1150 return rc;
1151}
1152
1153static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1154 u32 cmd_flags)
1155{
1156 int count, i, rc;
1157
1158 /* build the command word */
1159 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1160
1161 /* need to clear DONE bit separately */
1162 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1163
1164 /* write the data */
1165 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1166
1167 /* address of the NVRAM to write to */
1168 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1169 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1170
1171 /* issue the write command */
1172 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1173
1174 /* adjust timeout for emulation/FPGA */
754a2f52 1175 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1176 if (CHIP_REV_IS_SLOW(bp))
1177 count *= 100;
1178
1179 /* wait for completion */
1180 rc = -EBUSY;
1181 for (i = 0; i < count; i++) {
1182 udelay(5);
1183 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1184 if (val & MCPR_NVM_COMMAND_DONE) {
1185 rc = 0;
1186 break;
1187 }
1188 }
1189
51c1a580
MS		 1190 if (rc == -EBUSY)
1191 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1192 "nvram write timeout expired\n");
de0c62db
DK		 1193 return rc;
1194}
1195
1196#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1197
1198static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1199 int buf_size)
1200{
1201 int rc;
1202 u32 cmd_flags;
1203 u32 align_offset;
1204 __be32 val;
1205
1206 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1207 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1208 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1209 offset, buf_size, bp->common.flash_size);
1210 return -EINVAL;
1211 }
1212
1213 /* request access to nvram interface */
1214 rc = bnx2x_acquire_nvram_lock(bp);
1215 if (rc)
1216 return rc;
1217
1218 /* enable access to nvram interface */
1219 bnx2x_enable_nvram_access(bp);
1220
1221 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1222 align_offset = (offset & ~0x03);
1223 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1224
1225 if (rc == 0) {
1226 val &= ~(0xff << BYTE_OFFSET(offset));
1227 val |= (*data_buf << BYTE_OFFSET(offset));
1228
1229 /* nvram data is returned as an array of bytes
1230 * convert it back to cpu order */
1231 val = be32_to_cpu(val);
1232
1233 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1234 cmd_flags);
1235 }
1236
1237 /* disable access to nvram interface */
1238 bnx2x_disable_nvram_access(bp);
1239 bnx2x_release_nvram_lock(bp);
1240
1241 return rc;
1242}
1243
1244static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1245 int buf_size)
1246{
1247 int rc;
1248 u32 cmd_flags;
1249 u32 val;
1250 u32 written_so_far;
1251
1252 if (buf_size == 1) /* ethtool */
1253 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1254
1255 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1256 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1257 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1258 offset, buf_size);
1259 return -EINVAL;
1260 }
1261
1262 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1263 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1264 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1265 offset, buf_size, bp->common.flash_size);
1266 return -EINVAL;
1267 }
1268
1269 /* request access to nvram interface */
1270 rc = bnx2x_acquire_nvram_lock(bp);
1271 if (rc)
1272 return rc;
1273
1274 /* enable access to nvram interface */
1275 bnx2x_enable_nvram_access(bp);
1276
1277 written_so_far = 0;
1278 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1279 while ((written_so_far < buf_size) && (rc == 0)) {
1280 if (written_so_far == (buf_size - sizeof(u32)))
1281 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1282 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1283 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1284 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1285 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1286
1287 memcpy(&val, data_buf, 4);
1288
1289 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1290
1291 /* advance to the next dword */
1292 offset += sizeof(u32);
1293 data_buf += sizeof(u32);
1294 written_so_far += sizeof(u32);
1295 cmd_flags = 0;
1296 }
1297
1298 /* disable access to nvram interface */
1299 bnx2x_disable_nvram_access(bp);
1300 bnx2x_release_nvram_lock(bp);
1301
1302 return rc;
1303}
1304
1305static int bnx2x_set_eeprom(struct net_device *dev,
1306 struct ethtool_eeprom *eeprom, u8 *eebuf)
1307{
1308 struct bnx2x *bp = netdev_priv(dev);
1309 int port = BP_PORT(bp);
1310 int rc = 0;
e10bc84d 1311 u32 ext_phy_config;
51c1a580
MS		 1312 if (!netif_running(dev)) {
1313 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1314 "cannot access eeprom when the interface is down\n");
de0c62db 1315 return -EAGAIN;
51c1a580 1316 }
de0c62db 1317
51c1a580 1318 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1319 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1320 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1321 eeprom->len, eeprom->len);
1322
1323 /* parameters already validated in ethtool_set_eeprom */
1324
1325 /* PHY eeprom can be accessed only by the PMF */
1326 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1327 !bp->port.pmf) {
1328 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1329 "wrong magic or interface is not pmf\n");
de0c62db 1330 return -EINVAL;
51c1a580 1331 }
de0c62db 1332
e10bc84d
YR		 1333 ext_phy_config =
1334 SHMEM_RD(bp,
1335 dev_info.port_hw_config[port].external_phy_config);
1336
de0c62db
DK		 1337 if (eeprom->magic == 0x50485950) {
1338 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1339 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1340
1341 bnx2x_acquire_phy_lock(bp);
1342 rc |= bnx2x_link_reset(&bp->link_params,
1343 &bp->link_vars, 0);
e10bc84d 1344 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1345 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1346 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1347 MISC_REGISTERS_GPIO_HIGH, port);
1348 bnx2x_release_phy_lock(bp);
1349 bnx2x_link_report(bp);
1350
1351 } else if (eeprom->magic == 0x50485952) {
1352 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1353 if (bp->state == BNX2X_STATE_OPEN) {
1354 bnx2x_acquire_phy_lock(bp);
1355 rc |= bnx2x_link_reset(&bp->link_params,
1356 &bp->link_vars, 1);
1357
1358 rc |= bnx2x_phy_init(&bp->link_params,
1359 &bp->link_vars);
1360 bnx2x_release_phy_lock(bp);
1361 bnx2x_calc_fc_adv(bp);
1362 }
1363 } else if (eeprom->magic == 0x53985943) {
1364 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1365 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1366 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1367
1368 /* DSP Remove Download Mode */
1369 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1370 MISC_REGISTERS_GPIO_LOW, port);
1371
1372 bnx2x_acquire_phy_lock(bp);
1373
e10bc84d
YR		 1374 bnx2x_sfx7101_sp_sw_reset(bp,
1375 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1376
1377 /* wait 0.5 sec to allow it to run */
1378 msleep(500);
1379 bnx2x_ext_phy_hw_reset(bp, port);
1380 msleep(500);
1381 bnx2x_release_phy_lock(bp);
1382 }
1383 } else
1384 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1385
1386 return rc;
1387}
f85582f8 1388
de0c62db
DK		 1389static int bnx2x_get_coalesce(struct net_device *dev,
1390 struct ethtool_coalesce *coal)
1391{
1392 struct bnx2x *bp = netdev_priv(dev);
1393
1394 memset(coal, 0, sizeof(struct ethtool_coalesce));
1395
1396 coal->rx_coalesce_usecs = bp->rx_ticks;
1397 coal->tx_coalesce_usecs = bp->tx_ticks;
1398
1399 return 0;
1400}
1401
1402static int bnx2x_set_coalesce(struct net_device *dev,
1403 struct ethtool_coalesce *coal)
1404{
1405 struct bnx2x *bp = netdev_priv(dev);
1406
1407 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1408 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1409 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1410
1411 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1412 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1413 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1414
1415 if (netif_running(dev))
1416 bnx2x_update_coalesce(bp);
1417
1418 return 0;
1419}
1420
1421static void bnx2x_get_ringparam(struct net_device *dev,
1422 struct ethtool_ringparam *ering)
1423{
1424 struct bnx2x *bp = netdev_priv(dev);
1425
1426 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1427
25141580
DK		 1428 if (bp->rx_ring_size)
1429 ering->rx_pending = bp->rx_ring_size;
1430 else
c2188952 1431 ering->rx_pending = MAX_RX_AVAIL;
25141580 1432
de0c62db
DK		 1433 ering->tx_max_pending = MAX_TX_AVAIL;
1434 ering->tx_pending = bp->tx_ring_size;
1435}
1436
1437static int bnx2x_set_ringparam(struct net_device *dev,
1438 struct ethtool_ringparam *ering)
1439{
1440 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1441
1442 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1443 DP(BNX2X_MSG_ETHTOOL,
1444 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1445 return -EAGAIN;
1446 }
1447
1448 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1449 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1450 MIN_RX_SIZE_TPA)) ||
de0c62db 1451 (ering->tx_pending > MAX_TX_AVAIL) ||
51c1a580
MS		 1452 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1453 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1454 return -EINVAL;
51c1a580 1455 }
de0c62db
DK		 1456
1457 bp->rx_ring_size = ering->rx_pending;
1458 bp->tx_ring_size = ering->tx_pending;
1459
a9fccec7 1460 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1461}
1462
1463static void bnx2x_get_pauseparam(struct net_device *dev,
1464 struct ethtool_pauseparam *epause)
1465{
1466 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1467 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1468 int cfg_reg;
1469
a22f0788
YR		 1470 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1471 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1472
9e7e8399 1473 if (!epause->autoneg)
241fb5d2 1474 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1475 else
1476 cfg_reg = bp->link_params.req_fc_auto_adv;
1477
1478 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1479 BNX2X_FLOW_CTRL_RX);
9e7e8399 1480 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1481 BNX2X_FLOW_CTRL_TX);
1482
51c1a580 1483 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1484 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1485 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1486}
1487
1488static int bnx2x_set_pauseparam(struct net_device *dev,
1489 struct ethtool_pauseparam *epause)
1490{
1491 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1492 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1493 if (IS_MF(bp))
de0c62db
DK		 1494 return 0;
1495
51c1a580 1496 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1497 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1498 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1499
a22f0788 1500 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1501
1502 if (epause->rx_pause)
a22f0788 1503 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1504
1505 if (epause->tx_pause)
a22f0788 1506 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1507
a22f0788
YR		 1508 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1509 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1510
1511 if (epause->autoneg) {
a22f0788 1512 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1513 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1514 return -EINVAL;
1515 }
1516
a22f0788
YR		 1517 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1518 bp->link_params.req_flow_ctrl[cfg_idx] =
1519 BNX2X_FLOW_CTRL_AUTO;
1520 }
de0c62db
DK		 1521 }
1522
51c1a580 1523 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1524 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1525
1526 if (netif_running(dev)) {
1527 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1528 bnx2x_link_set(bp);
1529 }
1530
1531 return 0;
1532}
1533
de0c62db
DK		 1534static const struct {
1535 char string[ETH_GSTRING_LEN];
1536} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1537 { "register_test (offline)" },
1538 { "memory_test (offline)" },
1539 { "loopback_test (offline)" },
1540 { "nvram_test (online)" },
1541 { "interrupt_test (online)" },
1542 { "link_test (online)" },
1543 { "idle check (online)" }
1544};
1545
619c5cb6
VZ		 1546enum {
1547 BNX2X_CHIP_E1_OFST = 0,
1548 BNX2X_CHIP_E1H_OFST,
1549 BNX2X_CHIP_E2_OFST,
1550 BNX2X_CHIP_E3_OFST,
1551 BNX2X_CHIP_E3B0_OFST,
1552 BNX2X_CHIP_MAX_OFST
1553};
1554
1555#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1556#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1557#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1558#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1559#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1560
1561#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1562#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1563
de0c62db
DK		 1564static int bnx2x_test_registers(struct bnx2x *bp)
1565{
1566 int idx, i, rc = -ENODEV;
619c5cb6 1567 u32 wr_val = 0, hw;
de0c62db
DK		 1568 int port = BP_PORT(bp);
1569 static const struct {
619c5cb6 1570 u32 hw;
de0c62db
DK		 1571 u32 offset0;
1572 u32 offset1;
1573 u32 mask;
1574 } reg_tbl[] = {
619c5cb6
VZ		 1575/* 0 */ { BNX2X_CHIP_MASK_ALL,
1576 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1577 { BNX2X_CHIP_MASK_ALL,
1578 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1579 { BNX2X_CHIP_MASK_E1X,
1580 HC_REG_AGG_INT_0, 4, 0x000003ff },
1581 { BNX2X_CHIP_MASK_ALL,
1582 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1583 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1584 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1585 { BNX2X_CHIP_MASK_E3B0,
1586 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1587 { BNX2X_CHIP_MASK_ALL,
1588 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1589 { BNX2X_CHIP_MASK_ALL,
1590 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1591 { BNX2X_CHIP_MASK_ALL,
1592 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1593 { BNX2X_CHIP_MASK_ALL,
1594 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1595/* 10 */ { BNX2X_CHIP_MASK_ALL,
1596 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1597 { BNX2X_CHIP_MASK_ALL,
1598 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1599 { BNX2X_CHIP_MASK_ALL,
1600 QM_REG_CONNNUM_0, 4, 0x000fffff },
1601 { BNX2X_CHIP_MASK_ALL,
1602 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1603 { BNX2X_CHIP_MASK_ALL,
1604 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1605 { BNX2X_CHIP_MASK_ALL,
1606 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1607 { BNX2X_CHIP_MASK_ALL,
1608 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1609 { BNX2X_CHIP_MASK_ALL,
1610 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1611 { BNX2X_CHIP_MASK_ALL,
1612 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1613 { BNX2X_CHIP_MASK_ALL,
1614 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1615/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1616 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1617 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1618 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1619 { BNX2X_CHIP_MASK_ALL,
1620 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1621 { BNX2X_CHIP_MASK_ALL,
1622 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1623 { BNX2X_CHIP_MASK_ALL,
1624 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1625 { BNX2X_CHIP_MASK_ALL,
1626 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1627 { BNX2X_CHIP_MASK_ALL,
1628 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1629 { BNX2X_CHIP_MASK_ALL,
1630 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1631 { BNX2X_CHIP_MASK_ALL,
1632 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1633 { BNX2X_CHIP_MASK_ALL,
1634 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1635/* 30 */ { BNX2X_CHIP_MASK_ALL,
1636 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1637 { BNX2X_CHIP_MASK_ALL,
1638 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1639 { BNX2X_CHIP_MASK_ALL,
1640 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1641 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1642 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1643 { BNX2X_CHIP_MASK_ALL,
1644 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1645 { BNX2X_CHIP_MASK_ALL,
1646 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1647 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1648 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1649 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1650 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1651
1652 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1653 };
1654
51c1a580
MS		 1655 if (!netif_running(bp->dev)) {
1656 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1657 "cannot access eeprom when the interface is down\n");
de0c62db 1658 return rc;
51c1a580 1659 }
de0c62db 1660
619c5cb6
VZ		 1661 if (CHIP_IS_E1(bp))
1662 hw = BNX2X_CHIP_MASK_E1;
1663 else if (CHIP_IS_E1H(bp))
1664 hw = BNX2X_CHIP_MASK_E1H;
1665 else if (CHIP_IS_E2(bp))
1666 hw = BNX2X_CHIP_MASK_E2;
1667 else if (CHIP_IS_E3B0(bp))
1668 hw = BNX2X_CHIP_MASK_E3B0;
1669 else /* e3 A0 */
1670 hw = BNX2X_CHIP_MASK_E3;
1671
de0c62db
DK		 1672 /* Repeat the test twice:
1673 First by writing 0x00000000, second by writing 0xffffffff */
1674 for (idx = 0; idx < 2; idx++) {
1675
1676 switch (idx) {
1677 case 0:
1678 wr_val = 0;
1679 break;
1680 case 1:
1681 wr_val = 0xffffffff;
1682 break;
1683 }
1684
1685 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1686 u32 offset, mask, save_val, val;
619c5cb6 1687 if (!(hw & reg_tbl[i].hw))
f2e0899f 1688 continue;
de0c62db
DK		 1689
1690 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1691 mask = reg_tbl[i].mask;
1692
1693 save_val = REG_RD(bp, offset);
1694
ec6ba945 1695 REG_WR(bp, offset, wr_val & mask);
f85582f8 1696
de0c62db
DK		 1697 val = REG_RD(bp, offset);
1698
1699 /* Restore the original register's value */
1700 REG_WR(bp, offset, save_val);
1701
1702 /* verify value is as expected */
1703 if ((val & mask) != (wr_val & mask)) {
51c1a580 1704 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1705 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1706 offset, val, wr_val, mask);
1707 goto test_reg_exit;
1708 }
1709 }
1710 }
1711
1712 rc = 0;
1713
1714test_reg_exit:
1715 return rc;
1716}
1717
1718static int bnx2x_test_memory(struct bnx2x *bp)
1719{
1720 int i, j, rc = -ENODEV;
619c5cb6 1721 u32 val, index;
de0c62db
DK		 1722 static const struct {
1723 u32 offset;
1724 int size;
1725 } mem_tbl[] = {
1726 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1727 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1728 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1729 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1730 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1731 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1732 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1733
1734 { 0xffffffff, 0 }
1735 };
619c5cb6 1736
de0c62db
DK		 1737 static const struct {
1738 char *name;
1739 u32 offset;
619c5cb6 1740 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1741 } prty_tbl[] = {
619c5cb6
VZ		 1742 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1743 {0x3ffc0, 0, 0, 0} },
1744 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1745 {0x2, 0x2, 0, 0} },
1746 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1747 {0, 0, 0, 0} },
1748 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1749 {0x3ffc0, 0, 0, 0} },
1750 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1751 {0x3ffc0, 0, 0, 0} },
1752 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1753 {0x3ffc1, 0, 0, 0} },
1754
1755 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1756 };
1757
51c1a580
MS		 1758 if (!netif_running(bp->dev)) {
1759 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1760 "cannot access eeprom when the interface is down\n");
de0c62db 1761 return rc;
51c1a580 1762 }
de0c62db 1763
619c5cb6
VZ		 1764 if (CHIP_IS_E1(bp))
1765 index = BNX2X_CHIP_E1_OFST;
1766 else if (CHIP_IS_E1H(bp))
1767 index = BNX2X_CHIP_E1H_OFST;
1768 else if (CHIP_IS_E2(bp))
1769 index = BNX2X_CHIP_E2_OFST;
1770 else /* e3 */
1771 index = BNX2X_CHIP_E3_OFST;
1772
f2e0899f
DK		 1773 /* pre-Check the parity status */
1774 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1775 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1776 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1777 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 1778 "%s is 0x%x\n", prty_tbl[i].name, val);
1779 goto test_mem_exit;
1780 }
1781 }
1782
de0c62db
DK		 1783 /* Go through all the memories */
1784 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1785 for (j = 0; j < mem_tbl[i].size; j++)
1786 REG_RD(bp, mem_tbl[i].offset + j*4);
1787
1788 /* Check the parity status */
1789 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1790 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1791 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1792 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1793 "%s is 0x%x\n", prty_tbl[i].name, val);
1794 goto test_mem_exit;
1795 }
1796 }
1797
1798 rc = 0;
1799
1800test_mem_exit:
1801 return rc;
1802}
1803
a22f0788 1804static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1805{
f2e0899f 1806 int cnt = 1400;
de0c62db 1807
619c5cb6 1808 if (link_up) {
a22f0788 1809 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 1810 msleep(20);
1811
1812 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 1813 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
619c5cb6 1814 }
de0c62db
DK		 1815}
1816
619c5cb6 1817static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 1818{
1819 unsigned int pkt_size, num_pkts, i;
1820 struct sk_buff *skb;
1821 unsigned char *packet;
1822 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1823 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
6383c0b3 1824 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
de0c62db
DK		 1825 u16 tx_start_idx, tx_idx;
1826 u16 rx_start_idx, rx_idx;
b0700b1e 1827 u16 pkt_prod, bd_prod;
de0c62db
DK		 1828 struct sw_tx_bd *tx_buf;
1829 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1830 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1831 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1832 dma_addr_t mapping;
1833 union eth_rx_cqe *cqe;
619c5cb6 1834 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 1835 struct sw_rx_bd *rx_buf;
1836 u16 len;
1837 int rc = -ENODEV;
e52fcb24 1838 u8 *data;
73dbb5e1 1839 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
de0c62db
DK		 1840
1841 /* check the loopback mode */
1842 switch (loopback_mode) {
1843 case BNX2X_PHY_LOOPBACK:
de6eae1f 1844 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1845 return -EINVAL;
1846 break;
1847 case BNX2X_MAC_LOOPBACK:
32911333
YR		 1848 if (CHIP_IS_E3(bp)) {
1849 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1850 if (bp->port.supported[cfg_idx] &
1851 (SUPPORTED_10000baseT_Full |
1852 SUPPORTED_20000baseMLD2_Full |
1853 SUPPORTED_20000baseKR2_Full))
1854 bp->link_params.loopback_mode = LOOPBACK_XMAC;
1855 else
1856 bp->link_params.loopback_mode = LOOPBACK_UMAC;
1857 } else
1858 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1859
de0c62db
DK		 1860 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1861 break;
1862 default:
51c1a580 1863 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 1864 return -EINVAL;
1865 }
1866
1867 /* prepare the loopback packet */
1868 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1869 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 1870 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 1871 if (!skb) {
51c1a580 1872 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 1873 rc = -ENOMEM;
1874 goto test_loopback_exit;
1875 }
1876 packet = skb_put(skb, pkt_size);
1877 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1878 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1879 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1880 for (i = ETH_HLEN; i < pkt_size; i++)
1881 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 1882 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1883 skb_headlen(skb), DMA_TO_DEVICE);
1884 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1885 rc = -ENOMEM;
1886 dev_kfree_skb(skb);
51c1a580 1887 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 1888 goto test_loopback_exit;
1889 }
de0c62db
DK		 1890
1891 /* send the loopback packet */
1892 num_pkts = 0;
6383c0b3 1893 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1894 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1895
73dbb5e1
DK		 1896 netdev_tx_sent_queue(txq, skb->len);
1897
6383c0b3
AE		 1898 pkt_prod = txdata->tx_pkt_prod++;
1899 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1900 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 1901 tx_buf->skb = skb;
1902 tx_buf->flags = 0;
1903
6383c0b3
AE		 1904 bd_prod = TX_BD(txdata->tx_bd_prod);
1905 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 1906 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1907 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1908 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1909 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1910 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1911 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1912 SET_FLAG(tx_start_bd->general_data,
1913 ETH_TX_START_BD_ETH_ADDR_TYPE,
1914 UNICAST_ADDRESS);
1915 SET_FLAG(tx_start_bd->general_data,
1916 ETH_TX_START_BD_HDR_NBDS,
1917 1);
de0c62db
DK		 1918
1919 /* turn on parsing and get a BD */
1920 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 1921
6383c0b3
AE		 1922 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1923 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1924
f2e0899f 1925 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1926 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1927
1928 wmb();
1929
6383c0b3 1930 txdata->tx_db.data.prod += 2;
de0c62db 1931 barrier();
6383c0b3 1932 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 1933
1934 mmiowb();
619c5cb6 1935 barrier();
de0c62db
DK		 1936
1937 num_pkts++;
6383c0b3 1938 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 1939
1940 udelay(100);
1941
6383c0b3 1942 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1943 if (tx_idx != tx_start_idx + num_pkts)
1944 goto test_loopback_exit;
1945
f2e0899f
DK		 1946 /* Unlike HC IGU won't generate an interrupt for status block
1947 * updates that have been performed while interrupts were
1948 * disabled.
1949 */
e1210d12
ED		 1950 if (bp->common.int_block == INT_BLOCK_IGU) {
1951 /* Disable local BHes to prevent a dead-lock situation between
1952 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1953 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1954 */
1955 local_bh_disable();
6383c0b3 1956 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 1957 local_bh_enable();
1958 }
f2e0899f 1959
de0c62db
DK		 1960 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1961 if (rx_idx != rx_start_idx + num_pkts)
1962 goto test_loopback_exit;
1963
b0700b1e 1964 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 1965 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 1966 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1967 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 1968 goto test_loopback_rx_exit;
1969
621b4d66 1970 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 1971 if (len != pkt_size)
1972 goto test_loopback_rx_exit;
1973
1974 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 1975 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 1976 dma_unmap_addr(rx_buf, mapping),
1977 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 1978 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 1979 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 1980 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 1981 goto test_loopback_rx_exit;
1982
1983 rc = 0;
1984
1985test_loopback_rx_exit:
1986
1987 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1988 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1989 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1990 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1991
1992 /* Update producers */
1993 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1994 fp_rx->rx_sge_prod);
1995
1996test_loopback_exit:
1997 bp->link_params.loopback_mode = LOOPBACK_NONE;
1998
1999 return rc;
2000}
2001
619c5cb6 2002static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2003{
2004 int rc = 0, res;
2005
2006 if (BP_NOMCP(bp))
2007 return rc;
2008
2009 if (!netif_running(bp->dev))
2010 return BNX2X_LOOPBACK_FAILED;
2011
2012 bnx2x_netif_stop(bp, 1);
2013 bnx2x_acquire_phy_lock(bp);
2014
619c5cb6 2015 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2016 if (res) {
51c1a580 2017 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2018 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2019 }
2020
619c5cb6 2021 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2022 if (res) {
51c1a580 2023 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2024 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2025 }
2026
2027 bnx2x_release_phy_lock(bp);
2028 bnx2x_netif_start(bp);
2029
2030 return rc;
2031}
2032
2033#define CRC32_RESIDUAL 0xdebb20e3
2034
2035static int bnx2x_test_nvram(struct bnx2x *bp)
2036{
2037 static const struct {
2038 int offset;
2039 int size;
2040 } nvram_tbl[] = {
2041 { 0, 0x14 }, /* bootstrap */
2042 { 0x14, 0xec }, /* dir */
2043 { 0x100, 0x350 }, /* manuf_info */
2044 { 0x450, 0xf0 }, /* feature_info */
2045 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2046 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2047 { 0, 0 }
2048 };
afa13b4b
MY		 2049 __be32 *buf;
2050 u8 *data;
de0c62db
DK		 2051 int i, rc;
2052 u32 magic, crc;
2053
2054 if (BP_NOMCP(bp))
2055 return 0;
2056
afa13b4b
MY		 2057 buf = kmalloc(0x350, GFP_KERNEL);
2058 if (!buf) {
51c1a580 2059 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2060 rc = -ENOMEM;
2061 goto test_nvram_exit;
2062 }
2063 data = (u8 *)buf;
2064
de0c62db
DK		 2065 rc = bnx2x_nvram_read(bp, 0, data, 4);
2066 if (rc) {
51c1a580
MS		 2067 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2068 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2069 goto test_nvram_exit;
2070 }
2071
2072 magic = be32_to_cpu(buf[0]);
2073 if (magic != 0x669955aa) {
51c1a580
MS		 2074 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2075 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2076 rc = -ENODEV;
2077 goto test_nvram_exit;
2078 }
2079
2080 for (i = 0; nvram_tbl[i].size; i++) {
2081
2082 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2083 nvram_tbl[i].size);
2084 if (rc) {
51c1a580 2085 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2086 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2087 goto test_nvram_exit;
2088 }
2089
2090 crc = ether_crc_le(nvram_tbl[i].size, data);
2091 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2092 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2093 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2094 rc = -ENODEV;
2095 goto test_nvram_exit;
2096 }
2097 }
2098
2099test_nvram_exit:
afa13b4b 2100 kfree(buf);
de0c62db
DK		 2101 return rc;
2102}
2103
619c5cb6 2104/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2105static int bnx2x_test_intr(struct bnx2x *bp)
2106{
3b603066 2107 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2108
51c1a580
MS		 2109 if (!netif_running(bp->dev)) {
2110 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2111 "cannot access eeprom when the interface is down\n");
de0c62db 2112 return -ENODEV;
51c1a580 2113 }
de0c62db 2114
619c5cb6
VZ		 2115 params.q_obj = &bp->fp->q_obj;
2116 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2117
619c5cb6
VZ		 2118 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2119
2120 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2121}
2122
2123static void bnx2x_self_test(struct net_device *dev,
2124 struct ethtool_test *etest, u64 *buf)
2125{
2126 struct bnx2x *bp = netdev_priv(dev);
a22f0788 2127 u8 is_serdes;
de0c62db 2128 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2129 netdev_err(bp->dev,
2130 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2131 etest->flags |= ETH_TEST_FL_FAILED;
2132 return;
2133 }
2134
2135 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
2136
2137 if (!netif_running(dev))
2138 return;
2139
2140 /* offline tests are not supported in MF mode */
fb3bff17 2141 if (IS_MF(bp))
de0c62db 2142 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 2143 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 2144
2145 if (etest->flags & ETH_TEST_FL_OFFLINE) {
2146 int port = BP_PORT(bp);
2147 u32 val;
2148 u8 link_up;
2149
2150 /* save current value of input enable for TX port IF */
2151 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2152 /* disable input for TX port IF */
2153 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2154
a22f0788
YR		 2155 link_up = bp->link_vars.link_up;
2156
de0c62db
DK		 2157 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2158 bnx2x_nic_load(bp, LOAD_DIAG);
2159 /* wait until link state is restored */
619c5cb6 2160 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2161
2162 if (bnx2x_test_registers(bp) != 0) {
2163 buf[0] = 1;
2164 etest->flags |= ETH_TEST_FL_FAILED;
2165 }
2166 if (bnx2x_test_memory(bp) != 0) {
2167 buf[1] = 1;
2168 etest->flags |= ETH_TEST_FL_FAILED;
2169 }
f85582f8 2170
619c5cb6 2171 buf[2] = bnx2x_test_loopback(bp);
de0c62db
DK		 2172 if (buf[2] != 0)
2173 etest->flags |= ETH_TEST_FL_FAILED;
2174
2175 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2176
2177 /* restore input for TX port IF */
2178 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2179
2180 bnx2x_nic_load(bp, LOAD_NORMAL);
2181 /* wait until link state is restored */
a22f0788 2182 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2183 }
2184 if (bnx2x_test_nvram(bp) != 0) {
2185 buf[3] = 1;
2186 etest->flags |= ETH_TEST_FL_FAILED;
2187 }
2188 if (bnx2x_test_intr(bp) != 0) {
2189 buf[4] = 1;
2190 etest->flags |= ETH_TEST_FL_FAILED;
2191 }
633ac363
DK		 2192
2193 if (bnx2x_link_test(bp, is_serdes) != 0) {
2194 buf[5] = 1;
2195 etest->flags |= ETH_TEST_FL_FAILED;
2196 }
de0c62db
DK		 2197
2198#ifdef BNX2X_EXTRA_DEBUG
2199 bnx2x_panic_dump(bp);
2200#endif
2201}
2202
de0c62db
DK		 2203#define IS_PORT_STAT(i) \
2204 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2205#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2206#define IS_MF_MODE_STAT(bp) \
2207 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2208
619c5cb6
VZ		 2209/* ethtool statistics are displayed for all regular ethernet queues and the
2210 * fcoe L2 queue if not disabled
2211 */
2212static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2213{
2214 return BNX2X_NUM_ETH_QUEUES(bp);
2215}
2216
de0c62db
DK		 2217static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2218{
2219 struct bnx2x *bp = netdev_priv(dev);
2220 int i, num_stats;
2221
2222 switch (stringset) {
2223 case ETH_SS_STATS:
2224 if (is_multi(bp)) {
619c5cb6 2225 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2226 BNX2X_NUM_Q_STATS;
2227 } else
2228 num_stats = 0;
2229 if (IS_MF_MODE_STAT(bp)) {
2230 for (i = 0; i < BNX2X_NUM_STATS; i++)
2231 if (IS_FUNC_STAT(i))
2232 num_stats++;
2233 } else
2234 num_stats += BNX2X_NUM_STATS;
2235
de0c62db
DK		 2236 return num_stats;
2237
2238 case ETH_SS_TEST:
2239 return BNX2X_NUM_TESTS;
2240
2241 default:
2242 return -EINVAL;
2243 }
2244}
2245
2246static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2247{
2248 struct bnx2x *bp = netdev_priv(dev);
2249 int i, j, k;
ec6ba945 2250 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2251
2252 switch (stringset) {
2253 case ETH_SS_STATS:
d5e83632 2254 k = 0;
de0c62db 2255 if (is_multi(bp)) {
619c5cb6 2256 for_each_eth_queue(bp, i) {
ec6ba945 2257 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2258 sprintf(queue_name, "%d", i);
de0c62db 2259 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2260 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2261 ETH_GSTRING_LEN,
2262 bnx2x_q_stats_arr[j].string,
2263 queue_name);
de0c62db
DK		 2264 k += BNX2X_NUM_Q_STATS;
2265 }
de0c62db 2266 }
d5e83632
YM		 2267
2268
2269 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2270 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2271 continue;
2272 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2273 bnx2x_stats_arr[i].string);
2274 j++;
2275 }
2276
de0c62db
DK		 2277 break;
2278
2279 case ETH_SS_TEST:
2280 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2281 break;
2282 }
2283}
2284
2285static void bnx2x_get_ethtool_stats(struct net_device *dev,
2286 struct ethtool_stats *stats, u64 *buf)
2287{
2288 struct bnx2x *bp = netdev_priv(dev);
2289 u32 *hw_stats, *offset;
d5e83632 2290 int i, j, k = 0;
de0c62db
DK		 2291
2292 if (is_multi(bp)) {
619c5cb6 2293 for_each_eth_queue(bp, i) {
de0c62db
DK		 2294 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2295 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2296 if (bnx2x_q_stats_arr[j].size == 0) {
2297 /* skip this counter */
2298 buf[k + j] = 0;
2299 continue;
2300 }
2301 offset = (hw_stats +
2302 bnx2x_q_stats_arr[j].offset);
2303 if (bnx2x_q_stats_arr[j].size == 4) {
2304 /* 4-byte counter */
2305 buf[k + j] = (u64) *offset;
2306 continue;
2307 }
2308 /* 8-byte counter */
2309 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2310 }
2311 k += BNX2X_NUM_Q_STATS;
2312 }
d5e83632
YM		 2313 }
2314
2315 hw_stats = (u32 *)&bp->eth_stats;
2316 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2317 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2318 continue;
2319 if (bnx2x_stats_arr[i].size == 0) {
2320 /* skip this counter */
2321 buf[k + j] = 0;
2322 j++;
2323 continue;
de0c62db 2324 }
d5e83632
YM		 2325 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2326 if (bnx2x_stats_arr[i].size == 4) {
2327 /* 4-byte counter */
2328 buf[k + j] = (u64) *offset;
de0c62db 2329 j++;
d5e83632 2330 continue;
de0c62db 2331 }
d5e83632
YM		 2332 /* 8-byte counter */
2333 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2334 j++;
de0c62db
DK		 2335 }
2336}
2337
32d36134 2338static int bnx2x_set_phys_id(struct net_device *dev,
2339 enum ethtool_phys_id_state state)
de0c62db
DK		 2340{
2341 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2342
51c1a580
MS		 2343 if (!netif_running(dev)) {
2344 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2345 "cannot access eeprom when the interface is down\n");
32d36134 2346 return -EAGAIN;
51c1a580 2347 }
de0c62db 2348
51c1a580
MS		 2349 if (!bp->port.pmf) {
2350 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2351 return -EOPNOTSUPP;
51c1a580 2352 }
de0c62db 2353
32d36134 2354 switch (state) {
2355 case ETHTOOL_ID_ACTIVE:
fce55922 2356 return 1; /* cycle on/off once per second */
de0c62db 2357
32d36134 2358 case ETHTOOL_ID_ON:
2359 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2360 LED_MODE_ON, SPEED_1000);
32d36134 2361 break;
de0c62db 2362
32d36134 2363 case ETHTOOL_ID_OFF:
2364 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2365 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2366
32d36134 2367 break;
2368
2369 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2370 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2371 LED_MODE_OPER,
2372 bp->link_vars.line_speed);
32d36134 2373 }
de0c62db
DK		 2374
2375 return 0;
2376}
2377
ab532cf3 2378static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2379 u32 *rules __always_unused)
ab532cf3
TH		 2380{
2381 struct bnx2x *bp = netdev_priv(dev);
2382
2383 switch (info->cmd) {
2384 case ETHTOOL_GRXRINGS:
2385 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2386 return 0;
2387
2388 default:
51c1a580 2389 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 2390 return -EOPNOTSUPP;
2391 }
2392}
2393
7850f63f
BH		 2394static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2395{
96305234 2396 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 2397}
2398
2399static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 2400{
2401 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 2402 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2403 size_t i;
ab532cf3 2404
619c5cb6
VZ		 2405 /* Get the current configuration of the RSS indirection table */
2406 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2407
2408 /*
2409 * We can't use a memcpy() as an internal storage of an
2410 * indirection table is a u8 array while indir->ring_index
2411 * points to an array of u32.
2412 *
2413 * Indirection table contains the FW Client IDs, so we need to
2414 * align the returned table to the Client ID of the leading RSS
2415 * queue.
2416 */
7850f63f
BH		 2417 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2418 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 2419
ab532cf3
TH		 2420 return 0;
2421}
2422
7850f63f 2423static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 2424{
2425 struct bnx2x *bp = netdev_priv(dev);
2426 size_t i;
619c5cb6 2427 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
619c5cb6
VZ		 2428
2429 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 2430 /*
2431 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2432 * as an internal storage of an indirection table is a u8 array
2433 * while indir->ring_index points to an array of u32.
2434 *
2435 * Indirection table contains the FW Client IDs, so we need to
2436 * align the received table to the Client ID of the leading RSS
2437 * queue
2438 */
7850f63f 2439 ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 2440 }
ab532cf3 2441
96305234 2442 return bnx2x_config_rss_eth(bp, ind_table, false);
ab532cf3
TH		 2443}
2444
de0c62db
DK		 2445static const struct ethtool_ops bnx2x_ethtool_ops = {
2446 .get_settings = bnx2x_get_settings,
2447 .set_settings = bnx2x_set_settings,
2448 .get_drvinfo = bnx2x_get_drvinfo,
2449 .get_regs_len = bnx2x_get_regs_len,
2450 .get_regs = bnx2x_get_regs,
2451 .get_wol = bnx2x_get_wol,
2452 .set_wol = bnx2x_set_wol,
2453 .get_msglevel = bnx2x_get_msglevel,
2454 .set_msglevel = bnx2x_set_msglevel,
2455 .nway_reset = bnx2x_nway_reset,
2456 .get_link = bnx2x_get_link,
2457 .get_eeprom_len = bnx2x_get_eeprom_len,
2458 .get_eeprom = bnx2x_get_eeprom,
2459 .set_eeprom = bnx2x_set_eeprom,
2460 .get_coalesce = bnx2x_get_coalesce,
2461 .set_coalesce = bnx2x_set_coalesce,
2462 .get_ringparam = bnx2x_get_ringparam,
2463 .set_ringparam = bnx2x_set_ringparam,
2464 .get_pauseparam = bnx2x_get_pauseparam,
2465 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2466 .self_test = bnx2x_self_test,
2467 .get_sset_count = bnx2x_get_sset_count,
2468 .get_strings = bnx2x_get_strings,
32d36134 2469 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2470 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 2471 .get_rxnfc = bnx2x_get_rxnfc,
7850f63f 2472 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 2473 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2474 .set_rxfh_indir = bnx2x_set_rxfh_indir,
de0c62db
DK		 2475};
2476
2477void bnx2x_set_ethtool_ops(struct net_device *netdev)
2478{
2479 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2480}
kernel source for telekom puls (alcatel/mediatek)