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bnx2x: Allow up to 63 RSS queues
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 66};
67
68#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70static const struct {
71 long offset;
72 int size;
73 u32 flags;
74#define STATS_FLAGS_PORT 1
75#define STATS_FLAGS_FUNC 2
76#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78} bnx2x_stats_arr[] = {
79/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 107 { STATS_OFFSET32(pfc_frames_received_hi),
108 8, STATS_FLAGS_PORT, "pfc_frames_received" },
109 { STATS_OFFSET32(pfc_frames_sent_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 111 { STATS_OFFSET32(brb_drop_hi),
112 8, STATS_FLAGS_PORT, "rx_brb_discard" },
113 { STATS_OFFSET32(brb_truncate_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
115 { STATS_OFFSET32(pause_frames_received_hi),
116 8, STATS_FLAGS_PORT, "rx_pause_frames" },
117 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
118 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
119 { STATS_OFFSET32(nig_timer_max),
120 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
121/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
122 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
123 { STATS_OFFSET32(rx_skb_alloc_failed),
124 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
125 { STATS_OFFSET32(hw_csum_err),
126 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
127
128 { STATS_OFFSET32(total_bytes_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bytes" },
130 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
131 8, STATS_FLAGS_PORT, "tx_error_bytes" },
132 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
134 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
136 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
138 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
139 8, STATS_FLAGS_PORT, "tx_mac_errors" },
140 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
141 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
142/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
143 8, STATS_FLAGS_PORT, "tx_single_collisions" },
144 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
147 8, STATS_FLAGS_PORT, "tx_deferred" },
148 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
150 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_late_collisions" },
152 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_total_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
155 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
157 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
159 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
161 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
162/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
163 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
164 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
165 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
166 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
168 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 169 8, STATS_FLAGS_PORT, "tx_pause_frames" },
170 { STATS_OFFSET32(total_tpa_aggregations_hi),
171 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
172 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
174 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 175 8, STATS_FLAGS_FUNC, "tpa_bytes"},
176 { STATS_OFFSET32(recoverable_error),
177 4, STATS_FLAGS_FUNC, "recoverable_errors" },
178 { STATS_OFFSET32(unrecoverable_error),
179 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
e9939c80
YM		 180 { STATS_OFFSET32(eee_tx_lpi),
181 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 182};
183
184#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 185static int bnx2x_get_port_type(struct bnx2x *bp)
186{
187 int port_type;
188 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
189 switch (bp->link_params.phy[phy_idx].media_type) {
190 case ETH_PHY_SFP_FIBER:
191 case ETH_PHY_XFP_FIBER:
192 case ETH_PHY_KR:
193 case ETH_PHY_CX4:
194 port_type = PORT_FIBRE;
195 break;
196 case ETH_PHY_DA_TWINAX:
197 port_type = PORT_DA;
198 break;
199 case ETH_PHY_BASE_T:
200 port_type = PORT_TP;
201 break;
202 case ETH_PHY_NOT_PRESENT:
203 port_type = PORT_NONE;
204 break;
205 case ETH_PHY_UNSPECIFIED:
206 default:
207 port_type = PORT_OTHER;
208 break;
209 }
210 return port_type;
211}
ec6ba945 212
de0c62db
DK		 213static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
214{
215 struct bnx2x *bp = netdev_priv(dev);
a22f0788 216 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 217
a22f0788
YR		 218 /* Dual Media boards present all available port types */
219 cmd->supported = bp->port.supported[cfg_idx] |
220 (bp->port.supported[cfg_idx ^ 1] &
221 (SUPPORTED_TP | SUPPORTED_FIBRE));
222 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db 223
38298461
YM		 224 if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
225 if (!(bp->flags & MF_FUNC_DIS)) {
226 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
227 cmd->duplex = bp->link_vars.duplex;
228 } else {
229 ethtool_cmd_speed_set(
230 cmd, bp->link_params.req_line_speed[cfg_idx]);
231 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
232 }
233
234 if (IS_MF(bp) && !BP_NOMCP(bp))
235 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 236 } else {
38298461
YM		 237 cmd->duplex = DUPLEX_UNKNOWN;
238 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 239 }
f2e0899f 240
1ac9e428 241 cmd->port = bnx2x_get_port_type(bp);
a22f0788 242
de0c62db
DK		 243 cmd->phy_address = bp->mdio.prtad;
244 cmd->transceiver = XCVR_INTERNAL;
245
a22f0788 246 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 247 cmd->autoneg = AUTONEG_ENABLE;
248 else
249 cmd->autoneg = AUTONEG_DISABLE;
250
9e7e8399
MY		 251 /* Publish LP advertised speeds and FC */
252 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
253 u32 status = bp->link_vars.link_status;
254
255 cmd->lp_advertising |= ADVERTISED_Autoneg;
256 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
257 cmd->lp_advertising |= ADVERTISED_Pause;
258 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
259 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
260
261 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
262 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
263 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
264 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
265 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
266 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
267 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
268 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
269 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
270 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
271 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
272 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
273 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
274 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
275 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
276 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
277 }
278
de0c62db
DK		 279 cmd->maxtxpkt = 0;
280 cmd->maxrxpkt = 0;
281
51c1a580 282 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 283 " supported 0x%x advertising 0x%x speed %u\n"
284 " duplex %d port %d phy_address %d transceiver %d\n"
285 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 286 cmd->cmd, cmd->supported, cmd->advertising,
287 ethtool_cmd_speed(cmd),
de0c62db
DK		 288 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
289 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
290
291 return 0;
292}
293
294static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
295{
296 struct bnx2x *bp = netdev_priv(dev);
a22f0788 297 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 298 u32 speed;
de0c62db 299
0793f83f 300 if (IS_MF_SD(bp))
de0c62db
DK		 301 return 0;
302
51c1a580 303 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 304 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 305 " duplex %d port %d phy_address %d transceiver %d\n"
306 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 307 cmd->cmd, cmd->supported, cmd->advertising,
308 ethtool_cmd_speed(cmd),
de0c62db
DK		 309 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
310 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
311
b3337e4c 312 speed = ethtool_cmd_speed(cmd);
0793f83f 313
38298461
YM		 314 /* If recieved a request for an unknown duplex, assume full*/
315 if (cmd->duplex == DUPLEX_UNKNOWN)
316 cmd->duplex = DUPLEX_FULL;
317
0793f83f 318 if (IS_MF_SI(bp)) {
e3835b99 319 u32 part;
0793f83f
DK		 320 u32 line_speed = bp->link_vars.line_speed;
321
322 /* use 10G if no link detected */
323 if (!line_speed)
324 line_speed = 10000;
325
326 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 327 DP(BNX2X_MSG_ETHTOOL,
328 "To set speed BC %X or higher is required, please upgrade BC\n",
329 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 330 return -EINVAL;
331 }
e3835b99 332
faa6fcbb 333 part = (speed * 100) / line_speed;
e3835b99 334
faa6fcbb 335 if (line_speed < speed || !part) {
51c1a580
MS		 336 DP(BNX2X_MSG_ETHTOOL,
337 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 338 return -EINVAL;
339 }
0793f83f 340
e3835b99
DK		 341 if (bp->state != BNX2X_STATE_OPEN)
342 /* store value for following "load" */
343 bp->pending_max = part;
344 else
345 bnx2x_update_max_mf_config(bp, part);
0793f83f 346
0793f83f
DK		 347 return 0;
348 }
349
a22f0788
YR		 350 cfg_idx = bnx2x_get_link_cfg_idx(bp);
351 old_multi_phy_config = bp->link_params.multi_phy_config;
352 switch (cmd->port) {
353 case PORT_TP:
354 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
355 break; /* no port change */
356
357 if (!(bp->port.supported[0] & SUPPORTED_TP ||
358 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 359 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 360 return -EINVAL;
361 }
362 bp->link_params.multi_phy_config &=
363 ~PORT_HW_CFG_PHY_SELECTION_MASK;
364 if (bp->link_params.multi_phy_config &
365 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
366 bp->link_params.multi_phy_config |=
367 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
368 else
369 bp->link_params.multi_phy_config |=
370 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
371 break;
372 case PORT_FIBRE:
bfdb5823 373 case PORT_DA:
a22f0788
YR		 374 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
375 break; /* no port change */
376
377 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
378 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 379 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 380 return -EINVAL;
381 }
382 bp->link_params.multi_phy_config &=
383 ~PORT_HW_CFG_PHY_SELECTION_MASK;
384 if (bp->link_params.multi_phy_config &
385 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
386 bp->link_params.multi_phy_config |=
387 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
388 else
389 bp->link_params.multi_phy_config |=
390 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
391 break;
392 default:
51c1a580 393 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 394 return -EINVAL;
395 }
2f751a80 396 /* Save new config in case command complete successully */
a22f0788
YR		 397 new_multi_phy_config = bp->link_params.multi_phy_config;
398 /* Get the new cfg_idx */
399 cfg_idx = bnx2x_get_link_cfg_idx(bp);
400 /* Restore old config in case command failed */
401 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 402 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 403
de0c62db 404 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 405 u32 an_supported_speed = bp->port.supported[cfg_idx];
406 if (bp->link_params.phy[EXT_PHY1].type ==
407 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
408 an_supported_speed |= (SUPPORTED_100baseT_Half |
409 SUPPORTED_100baseT_Full);
a22f0788 410 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 411 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 412 return -EINVAL;
413 }
414
415 /* advertise the requested speed and duplex if supported */
75318327 416 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 417 DP(BNX2X_MSG_ETHTOOL,
418 "Advertisement parameters are not supported\n");
8d661637
YR		 419 return -EINVAL;
420 }
de0c62db 421
a22f0788 422 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 423 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
424 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 425 cmd->advertising);
8d661637
YR		 426 if (cmd->advertising) {
427
428 bp->link_params.speed_cap_mask[cfg_idx] = 0;
429 if (cmd->advertising & ADVERTISED_10baseT_Half) {
430 bp->link_params.speed_cap_mask[cfg_idx] |=
431 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
432 }
433 if (cmd->advertising & ADVERTISED_10baseT_Full)
434 bp->link_params.speed_cap_mask[cfg_idx] |=
435 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 436
8d661637
YR		 437 if (cmd->advertising & ADVERTISED_100baseT_Full)
438 bp->link_params.speed_cap_mask[cfg_idx] |=
439 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
440
441 if (cmd->advertising & ADVERTISED_100baseT_Half) {
442 bp->link_params.speed_cap_mask[cfg_idx] |=
443 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
444 }
445 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
446 bp->link_params.speed_cap_mask[cfg_idx] |=
447 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
448 }
449 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
450 ADVERTISED_1000baseKX_Full))
451 bp->link_params.speed_cap_mask[cfg_idx] |=
452 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
453
454 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
455 ADVERTISED_10000baseKX4_Full |
456 ADVERTISED_10000baseKR_Full))
457 bp->link_params.speed_cap_mask[cfg_idx] |=
458 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
459 }
de0c62db
DK		 460 } else { /* forced speed */
461 /* advertise the requested speed and duplex if supported */
a22f0788 462 switch (speed) {
de0c62db
DK		 463 case SPEED_10:
464 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 465 if (!(bp->port.supported[cfg_idx] &
de0c62db 466 SUPPORTED_10baseT_Full)) {
51c1a580 467 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 468 "10M full not supported\n");
469 return -EINVAL;
470 }
471
472 advertising = (ADVERTISED_10baseT_Full |
473 ADVERTISED_TP);
474 } else {
a22f0788 475 if (!(bp->port.supported[cfg_idx] &
de0c62db 476 SUPPORTED_10baseT_Half)) {
51c1a580 477 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 478 "10M half not supported\n");
479 return -EINVAL;
480 }
481
482 advertising = (ADVERTISED_10baseT_Half |
483 ADVERTISED_TP);
484 }
485 break;
486
487 case SPEED_100:
488 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 489 if (!(bp->port.supported[cfg_idx] &
de0c62db 490 SUPPORTED_100baseT_Full)) {
51c1a580 491 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 492 "100M full not supported\n");
493 return -EINVAL;
494 }
495
496 advertising = (ADVERTISED_100baseT_Full |
497 ADVERTISED_TP);
498 } else {
a22f0788 499 if (!(bp->port.supported[cfg_idx] &
de0c62db 500 SUPPORTED_100baseT_Half)) {
51c1a580 501 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 502 "100M half not supported\n");
503 return -EINVAL;
504 }
505
506 advertising = (ADVERTISED_100baseT_Half |
507 ADVERTISED_TP);
508 }
509 break;
510
511 case SPEED_1000:
512 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 513 DP(BNX2X_MSG_ETHTOOL,
514 "1G half not supported\n");
de0c62db
DK		 515 return -EINVAL;
516 }
517
a22f0788
YR		 518 if (!(bp->port.supported[cfg_idx] &
519 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 520 DP(BNX2X_MSG_ETHTOOL,
521 "1G full not supported\n");
de0c62db
DK		 522 return -EINVAL;
523 }
524
525 advertising = (ADVERTISED_1000baseT_Full |
526 ADVERTISED_TP);
527 break;
528
529 case SPEED_2500:
530 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 531 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 532 "2.5G half not supported\n");
533 return -EINVAL;
534 }
535
a22f0788
YR		 536 if (!(bp->port.supported[cfg_idx]
537 & SUPPORTED_2500baseX_Full)) {
51c1a580 538 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 539 "2.5G full not supported\n");
540 return -EINVAL;
541 }
542
543 advertising = (ADVERTISED_2500baseX_Full |
544 ADVERTISED_TP);
545 break;
546
547 case SPEED_10000:
548 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 549 DP(BNX2X_MSG_ETHTOOL,
550 "10G half not supported\n");
de0c62db
DK		 551 return -EINVAL;
552 }
553
a22f0788
YR		 554 if (!(bp->port.supported[cfg_idx]
555 & SUPPORTED_10000baseT_Full)) {
51c1a580
MS		 556 DP(BNX2X_MSG_ETHTOOL,
557 "10G full not supported\n");
de0c62db
DK		 558 return -EINVAL;
559 }
560
561 advertising = (ADVERTISED_10000baseT_Full |
562 ADVERTISED_FIBRE);
563 break;
564
565 default:
51c1a580 566 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 567 return -EINVAL;
568 }
569
a22f0788
YR		 570 bp->link_params.req_line_speed[cfg_idx] = speed;
571 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
572 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 573 }
574
51c1a580 575 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 576 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 577 bp->link_params.req_line_speed[cfg_idx],
578 bp->link_params.req_duplex[cfg_idx],
579 bp->port.advertising[cfg_idx]);
de0c62db 580
a22f0788
YR		 581 /* Set new config */
582 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 583 if (netif_running(dev)) {
584 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
585 bnx2x_link_set(bp);
586 }
587
588 return 0;
589}
590
591#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
592#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 593#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 594#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
595#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
596
1191cb83
ED		 597static bool bnx2x_is_reg_online(struct bnx2x *bp,
598 const struct reg_addr *reg_info)
0fea29c1
VZ		 599{
600 if (CHIP_IS_E1(bp))
601 return IS_E1_ONLINE(reg_info->info);
602 else if (CHIP_IS_E1H(bp))
603 return IS_E1H_ONLINE(reg_info->info);
604 else if (CHIP_IS_E2(bp))
605 return IS_E2_ONLINE(reg_info->info);
606 else if (CHIP_IS_E3A0(bp))
607 return IS_E3_ONLINE(reg_info->info);
608 else if (CHIP_IS_E3B0(bp))
609 return IS_E3B0_ONLINE(reg_info->info);
610 else
611 return false;
612}
613
614/******* Paged registers info selectors ********/
1191cb83 615static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 616{
617 if (CHIP_IS_E2(bp))
618 return page_vals_e2;
619 else if (CHIP_IS_E3(bp))
620 return page_vals_e3;
621 else
622 return NULL;
623}
624
1191cb83 625static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 626{
627 if (CHIP_IS_E2(bp))
628 return PAGE_MODE_VALUES_E2;
629 else if (CHIP_IS_E3(bp))
630 return PAGE_MODE_VALUES_E3;
631 else
632 return 0;
633}
634
1191cb83 635static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 636{
637 if (CHIP_IS_E2(bp))
638 return page_write_regs_e2;
639 else if (CHIP_IS_E3(bp))
640 return page_write_regs_e3;
641 else
642 return NULL;
643}
644
1191cb83 645static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 646{
647 if (CHIP_IS_E2(bp))
648 return PAGE_WRITE_REGS_E2;
649 else if (CHIP_IS_E3(bp))
650 return PAGE_WRITE_REGS_E3;
651 else
652 return 0;
653}
654
1191cb83 655static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 656{
657 if (CHIP_IS_E2(bp))
658 return page_read_regs_e2;
659 else if (CHIP_IS_E3(bp))
660 return page_read_regs_e3;
661 else
662 return NULL;
663}
664
1191cb83 665static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 666{
667 if (CHIP_IS_E2(bp))
668 return PAGE_READ_REGS_E2;
669 else if (CHIP_IS_E3(bp))
670 return PAGE_READ_REGS_E3;
671 else
672 return 0;
673}
674
1191cb83 675static int __bnx2x_get_regs_len(struct bnx2x *bp)
0fea29c1
VZ		 676{
677 int num_pages = __bnx2x_get_page_reg_num(bp);
678 int page_write_num = __bnx2x_get_page_write_num(bp);
679 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
680 int page_read_num = __bnx2x_get_page_read_num(bp);
681 int regdump_len = 0;
682 int i, j, k;
683
684 for (i = 0; i < REGS_COUNT; i++)
685 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
686 regdump_len += reg_addrs[i].size;
687
688 for (i = 0; i < num_pages; i++)
689 for (j = 0; j < page_write_num; j++)
690 for (k = 0; k < page_read_num; k++)
691 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
692 regdump_len += page_read_addr[k].size;
693
694 return regdump_len;
695}
de0c62db
DK		 696
697static int bnx2x_get_regs_len(struct net_device *dev)
698{
699 struct bnx2x *bp = netdev_priv(dev);
700 int regdump_len = 0;
de0c62db 701
0fea29c1 702 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 703 regdump_len *= 4;
704 regdump_len += sizeof(struct dump_hdr);
705
706 return regdump_len;
707}
708
0fea29c1
VZ		 709/**
710 * bnx2x_read_pages_regs - read "paged" registers
711 *
712 * @bp device handle
713 * @p output buffer
714 *
715 * Reads "paged" memories: memories that may only be read by first writing to a
716 * specific address ("write address") and then reading from a specific address
717 * ("read address"). There may be more than one write address per "page" and
718 * more than one read address per write address.
719 */
1191cb83 720static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 721{
722 u32 i, j, k, n;
0fea29c1
VZ		 723 /* addresses of the paged registers */
724 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
725 /* number of paged registers */
726 int num_pages = __bnx2x_get_page_reg_num(bp);
727 /* write addresses */
728 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
729 /* number of write addresses */
730 int write_num = __bnx2x_get_page_write_num(bp);
731 /* read addresses info */
732 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
733 /* number of read addresses */
734 int read_num = __bnx2x_get_page_read_num(bp);
735
736 for (i = 0; i < num_pages; i++) {
737 for (j = 0; j < write_num; j++) {
738 REG_WR(bp, write_addr[j], page_addr[i]);
739 for (k = 0; k < read_num; k++)
740 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 741 for (n = 0; n <
0fea29c1 742 read_addr[k].size; n++)
f2e0899f 743 *p++ = REG_RD(bp,
0fea29c1 744 read_addr[k].addr + n*4);
f2e0899f
DK		 745 }
746 }
747}
748
1191cb83 749static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
0fea29c1
VZ		 750{
751 u32 i, j;
752
753 /* Read the regular registers */
754 for (i = 0; i < REGS_COUNT; i++)
755 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
756 for (j = 0; j < reg_addrs[i].size; j++)
757 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
758
759 /* Read "paged" registes */
760 bnx2x_read_pages_regs(bp, p);
761}
762
de0c62db
DK		 763static void bnx2x_get_regs(struct net_device *dev,
764 struct ethtool_regs *regs, void *_p)
765{
0fea29c1 766 u32 *p = _p;
de0c62db
DK		 767 struct bnx2x *bp = netdev_priv(dev);
768 struct dump_hdr dump_hdr = {0};
769
770 regs->version = 0;
771 memset(p, 0, regs->len);
772
773 if (!netif_running(bp->dev))
774 return;
775
4a33bc03
VZ		 776 /* Disable parity attentions as long as following dump may
777 * cause false alarms by reading never written registers. We
778 * will re-enable parity attentions right after the dump.
779 */
780 bnx2x_disable_blocks_parity(bp);
781
de0c62db
DK		 782 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
783 dump_hdr.dump_sign = dump_sign_all;
784 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
785 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
786 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
787 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 788
789 if (CHIP_IS_E1(bp))
790 dump_hdr.info = RI_E1_ONLINE;
791 else if (CHIP_IS_E1H(bp))
792 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 793 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 794 dump_hdr.info = RI_E2_ONLINE |
795 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 796
797 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
798 p += dump_hdr.hdr_size + 1;
799
0fea29c1
VZ		 800 /* Actually read the registers */
801 __bnx2x_get_regs(bp, p);
802
4a33bc03
VZ		 803 /* Re-enable parity attentions */
804 bnx2x_clear_blocks_parity(bp);
c9ee9206 805 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 806}
807
de0c62db
DK		 808static void bnx2x_get_drvinfo(struct net_device *dev,
809 struct ethtool_drvinfo *info)
810{
811 struct bnx2x *bp = netdev_priv(dev);
812 u8 phy_fw_ver[PHY_FW_VER_LEN];
813
68aad78c
RJ		 814 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
815 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db
DK		 816
817 phy_fw_ver[0] = '\0';
a1e785e0
MY		 818 bnx2x_get_ext_phy_fw_version(&bp->link_params,
819 phy_fw_ver, PHY_FW_VER_LEN);
68aad78c 820 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
de0c62db
DK		 821 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
822 "bc %d.%d.%d%s%s",
823 (bp->common.bc_ver & 0xff0000) >> 16,
824 (bp->common.bc_ver & 0xff00) >> 8,
825 (bp->common.bc_ver & 0xff),
826 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
68aad78c 827 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 828 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 829 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 830 info->eedump_len = bp->common.flash_size;
831 info->regdump_len = bnx2x_get_regs_len(dev);
832}
833
834static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
835{
836 struct bnx2x *bp = netdev_priv(dev);
837
838 if (bp->flags & NO_WOL_FLAG) {
839 wol->supported = 0;
840 wol->wolopts = 0;
841 } else {
842 wol->supported = WAKE_MAGIC;
843 if (bp->wol)
844 wol->wolopts = WAKE_MAGIC;
845 else
846 wol->wolopts = 0;
847 }
848 memset(&wol->sopass, 0, sizeof(wol->sopass));
849}
850
851static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
852{
853 struct bnx2x *bp = netdev_priv(dev);
854
51c1a580
MS		 855 if (wol->wolopts & ~WAKE_MAGIC) {
856 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 857 return -EINVAL;
51c1a580 858 }
de0c62db
DK		 859
860 if (wol->wolopts & WAKE_MAGIC) {
51c1a580
MS		 861 if (bp->flags & NO_WOL_FLAG) {
862 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 863 return -EINVAL;
51c1a580 864 }
de0c62db
DK		 865 bp->wol = 1;
866 } else
867 bp->wol = 0;
868
869 return 0;
870}
871
872static u32 bnx2x_get_msglevel(struct net_device *dev)
873{
874 struct bnx2x *bp = netdev_priv(dev);
875
876 return bp->msg_enable;
877}
878
879static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
880{
881 struct bnx2x *bp = netdev_priv(dev);
882
7a25cc73
DK		 883 if (capable(CAP_NET_ADMIN)) {
884 /* dump MCP trace */
885 if (level & BNX2X_MSG_MCP)
886 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 887 bp->msg_enable = level;
7a25cc73 888 }
de0c62db
DK		 889}
890
891static int bnx2x_nway_reset(struct net_device *dev)
892{
893 struct bnx2x *bp = netdev_priv(dev);
894
895 if (!bp->port.pmf)
896 return 0;
897
898 if (netif_running(dev)) {
899 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
900 bnx2x_link_set(bp);
901 }
902
903 return 0;
904}
905
906static u32 bnx2x_get_link(struct net_device *dev)
907{
908 struct bnx2x *bp = netdev_priv(dev);
909
f2e0899f 910 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 911 return 0;
912
913 return bp->link_vars.link_up;
914}
915
916static int bnx2x_get_eeprom_len(struct net_device *dev)
917{
918 struct bnx2x *bp = netdev_priv(dev);
919
920 return bp->common.flash_size;
921}
922
f16da43b
AE		 923/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
924 * we done things the other way around, if two pfs from the same port would
925 * attempt to access nvram at the same time, we could run into a scenario such
926 * as:
927 * pf A takes the port lock.
928 * pf B succeeds in taking the same lock since they are from the same port.
929 * pf A takes the per pf misc lock. Performs eeprom access.
930 * pf A finishes. Unlocks the per pf misc lock.
931 * Pf B takes the lock and proceeds to perform it's own access.
932 * pf A unlocks the per port lock, while pf B is still working (!).
933 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
934 * acess corrupted by pf B).*
935 */
de0c62db
DK		 936static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
937{
938 int port = BP_PORT(bp);
939 int count, i;
f16da43b
AE		 940 u32 val;
941
942 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
943 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 944
945 /* adjust timeout for emulation/FPGA */
754a2f52 946 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 947 if (CHIP_REV_IS_SLOW(bp))
948 count *= 100;
949
950 /* request access to nvram interface */
951 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
952 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
953
954 for (i = 0; i < count*10; i++) {
955 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
956 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
957 break;
958
959 udelay(5);
960 }
961
962 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 963 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
964 "cannot get access to nvram interface\n");
de0c62db
DK		 965 return -EBUSY;
966 }
967
968 return 0;
969}
970
971static int bnx2x_release_nvram_lock(struct bnx2x *bp)
972{
973 int port = BP_PORT(bp);
974 int count, i;
f16da43b 975 u32 val;
de0c62db
DK		 976
977 /* adjust timeout for emulation/FPGA */
754a2f52 978 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 979 if (CHIP_REV_IS_SLOW(bp))
980 count *= 100;
981
982 /* relinquish nvram interface */
983 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
984 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
985
986 for (i = 0; i < count*10; i++) {
987 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
988 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
989 break;
990
991 udelay(5);
992 }
993
994 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 995 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
996 "cannot free access to nvram interface\n");
de0c62db
DK		 997 return -EBUSY;
998 }
999
f16da43b
AE		 1000 /* release HW lock: protect against other PFs in PF Direct Assignment */
1001 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1002 return 0;
1003}
1004
1005static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1006{
1007 u32 val;
1008
1009 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1010
1011 /* enable both bits, even on read */
1012 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1013 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1014 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1015}
1016
1017static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1018{
1019 u32 val;
1020
1021 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1022
1023 /* disable both bits, even after read */
1024 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1025 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1026 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1027}
1028
1029static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1030 u32 cmd_flags)
1031{
1032 int count, i, rc;
1033 u32 val;
1034
1035 /* build the command word */
1036 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1037
1038 /* need to clear DONE bit separately */
1039 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1040
1041 /* address of the NVRAM to read from */
1042 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1043 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1044
1045 /* issue a read command */
1046 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1047
1048 /* adjust timeout for emulation/FPGA */
754a2f52 1049 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1050 if (CHIP_REV_IS_SLOW(bp))
1051 count *= 100;
1052
1053 /* wait for completion */
1054 *ret_val = 0;
1055 rc = -EBUSY;
1056 for (i = 0; i < count; i++) {
1057 udelay(5);
1058 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1059
1060 if (val & MCPR_NVM_COMMAND_DONE) {
1061 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1062 /* we read nvram data in cpu order
1063 * but ethtool sees it as an array of bytes
1064 * converting to big-endian will do the work */
1065 *ret_val = cpu_to_be32(val);
1066 rc = 0;
1067 break;
1068 }
1069 }
51c1a580
MS		 1070 if (rc == -EBUSY)
1071 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1072 "nvram read timeout expired\n");
de0c62db
DK		 1073 return rc;
1074}
1075
1076static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1077 int buf_size)
1078{
1079 int rc;
1080 u32 cmd_flags;
1081 __be32 val;
1082
1083 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1084 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1085 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1086 offset, buf_size);
1087 return -EINVAL;
1088 }
1089
1090 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1091 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1092 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1093 offset, buf_size, bp->common.flash_size);
1094 return -EINVAL;
1095 }
1096
1097 /* request access to nvram interface */
1098 rc = bnx2x_acquire_nvram_lock(bp);
1099 if (rc)
1100 return rc;
1101
1102 /* enable access to nvram interface */
1103 bnx2x_enable_nvram_access(bp);
1104
1105 /* read the first word(s) */
1106 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1107 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1108 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1109 memcpy(ret_buf, &val, 4);
1110
1111 /* advance to the next dword */
1112 offset += sizeof(u32);
1113 ret_buf += sizeof(u32);
1114 buf_size -= sizeof(u32);
1115 cmd_flags = 0;
1116 }
1117
1118 if (rc == 0) {
1119 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1120 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1121 memcpy(ret_buf, &val, 4);
1122 }
1123
1124 /* disable access to nvram interface */
1125 bnx2x_disable_nvram_access(bp);
1126 bnx2x_release_nvram_lock(bp);
1127
1128 return rc;
1129}
1130
1131static int bnx2x_get_eeprom(struct net_device *dev,
1132 struct ethtool_eeprom *eeprom, u8 *eebuf)
1133{
1134 struct bnx2x *bp = netdev_priv(dev);
1135 int rc;
1136
51c1a580
MS		 1137 if (!netif_running(dev)) {
1138 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1139 "cannot access eeprom when the interface is down\n");
de0c62db 1140 return -EAGAIN;
51c1a580 1141 }
de0c62db 1142
51c1a580 1143 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1144 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1145 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1146 eeprom->len, eeprom->len);
1147
1148 /* parameters already validated in ethtool_get_eeprom */
1149
1150 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1151
1152 return rc;
1153}
1154
1155static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1156 u32 cmd_flags)
1157{
1158 int count, i, rc;
1159
1160 /* build the command word */
1161 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1162
1163 /* need to clear DONE bit separately */
1164 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1165
1166 /* write the data */
1167 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1168
1169 /* address of the NVRAM to write to */
1170 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1171 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1172
1173 /* issue the write command */
1174 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1175
1176 /* adjust timeout for emulation/FPGA */
754a2f52 1177 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1178 if (CHIP_REV_IS_SLOW(bp))
1179 count *= 100;
1180
1181 /* wait for completion */
1182 rc = -EBUSY;
1183 for (i = 0; i < count; i++) {
1184 udelay(5);
1185 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1186 if (val & MCPR_NVM_COMMAND_DONE) {
1187 rc = 0;
1188 break;
1189 }
1190 }
1191
51c1a580
MS		 1192 if (rc == -EBUSY)
1193 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1194 "nvram write timeout expired\n");
de0c62db
DK		 1195 return rc;
1196}
1197
1198#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1199
1200static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1201 int buf_size)
1202{
1203 int rc;
1204 u32 cmd_flags;
1205 u32 align_offset;
1206 __be32 val;
1207
1208 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1209 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1210 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1211 offset, buf_size, bp->common.flash_size);
1212 return -EINVAL;
1213 }
1214
1215 /* request access to nvram interface */
1216 rc = bnx2x_acquire_nvram_lock(bp);
1217 if (rc)
1218 return rc;
1219
1220 /* enable access to nvram interface */
1221 bnx2x_enable_nvram_access(bp);
1222
1223 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1224 align_offset = (offset & ~0x03);
1225 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1226
1227 if (rc == 0) {
1228 val &= ~(0xff << BYTE_OFFSET(offset));
1229 val |= (*data_buf << BYTE_OFFSET(offset));
1230
1231 /* nvram data is returned as an array of bytes
1232 * convert it back to cpu order */
1233 val = be32_to_cpu(val);
1234
1235 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1236 cmd_flags);
1237 }
1238
1239 /* disable access to nvram interface */
1240 bnx2x_disable_nvram_access(bp);
1241 bnx2x_release_nvram_lock(bp);
1242
1243 return rc;
1244}
1245
1246static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1247 int buf_size)
1248{
1249 int rc;
1250 u32 cmd_flags;
1251 u32 val;
1252 u32 written_so_far;
1253
1254 if (buf_size == 1) /* ethtool */
1255 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1256
1257 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1258 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1259 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1260 offset, buf_size);
1261 return -EINVAL;
1262 }
1263
1264 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1265 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1266 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1267 offset, buf_size, bp->common.flash_size);
1268 return -EINVAL;
1269 }
1270
1271 /* request access to nvram interface */
1272 rc = bnx2x_acquire_nvram_lock(bp);
1273 if (rc)
1274 return rc;
1275
1276 /* enable access to nvram interface */
1277 bnx2x_enable_nvram_access(bp);
1278
1279 written_so_far = 0;
1280 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1281 while ((written_so_far < buf_size) && (rc == 0)) {
1282 if (written_so_far == (buf_size - sizeof(u32)))
1283 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1284 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1285 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1286 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1287 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1288
1289 memcpy(&val, data_buf, 4);
1290
1291 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1292
1293 /* advance to the next dword */
1294 offset += sizeof(u32);
1295 data_buf += sizeof(u32);
1296 written_so_far += sizeof(u32);
1297 cmd_flags = 0;
1298 }
1299
1300 /* disable access to nvram interface */
1301 bnx2x_disable_nvram_access(bp);
1302 bnx2x_release_nvram_lock(bp);
1303
1304 return rc;
1305}
1306
1307static int bnx2x_set_eeprom(struct net_device *dev,
1308 struct ethtool_eeprom *eeprom, u8 *eebuf)
1309{
1310 struct bnx2x *bp = netdev_priv(dev);
1311 int port = BP_PORT(bp);
1312 int rc = 0;
e10bc84d 1313 u32 ext_phy_config;
51c1a580
MS		 1314 if (!netif_running(dev)) {
1315 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1316 "cannot access eeprom when the interface is down\n");
de0c62db 1317 return -EAGAIN;
51c1a580 1318 }
de0c62db 1319
51c1a580 1320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1321 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1322 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1323 eeprom->len, eeprom->len);
1324
1325 /* parameters already validated in ethtool_set_eeprom */
1326
1327 /* PHY eeprom can be accessed only by the PMF */
1328 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1329 !bp->port.pmf) {
1330 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1331 "wrong magic or interface is not pmf\n");
de0c62db 1332 return -EINVAL;
51c1a580 1333 }
de0c62db 1334
e10bc84d
YR		 1335 ext_phy_config =
1336 SHMEM_RD(bp,
1337 dev_info.port_hw_config[port].external_phy_config);
1338
de0c62db
DK		 1339 if (eeprom->magic == 0x50485950) {
1340 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1341 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1342
1343 bnx2x_acquire_phy_lock(bp);
1344 rc |= bnx2x_link_reset(&bp->link_params,
1345 &bp->link_vars, 0);
e10bc84d 1346 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1347 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1348 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1349 MISC_REGISTERS_GPIO_HIGH, port);
1350 bnx2x_release_phy_lock(bp);
1351 bnx2x_link_report(bp);
1352
1353 } else if (eeprom->magic == 0x50485952) {
1354 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1355 if (bp->state == BNX2X_STATE_OPEN) {
1356 bnx2x_acquire_phy_lock(bp);
1357 rc |= bnx2x_link_reset(&bp->link_params,
1358 &bp->link_vars, 1);
1359
1360 rc |= bnx2x_phy_init(&bp->link_params,
1361 &bp->link_vars);
1362 bnx2x_release_phy_lock(bp);
1363 bnx2x_calc_fc_adv(bp);
1364 }
1365 } else if (eeprom->magic == 0x53985943) {
1366 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1367 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1368 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1369
1370 /* DSP Remove Download Mode */
1371 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1372 MISC_REGISTERS_GPIO_LOW, port);
1373
1374 bnx2x_acquire_phy_lock(bp);
1375
e10bc84d
YR		 1376 bnx2x_sfx7101_sp_sw_reset(bp,
1377 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1378
1379 /* wait 0.5 sec to allow it to run */
1380 msleep(500);
1381 bnx2x_ext_phy_hw_reset(bp, port);
1382 msleep(500);
1383 bnx2x_release_phy_lock(bp);
1384 }
1385 } else
1386 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1387
1388 return rc;
1389}
f85582f8 1390
de0c62db
DK		 1391static int bnx2x_get_coalesce(struct net_device *dev,
1392 struct ethtool_coalesce *coal)
1393{
1394 struct bnx2x *bp = netdev_priv(dev);
1395
1396 memset(coal, 0, sizeof(struct ethtool_coalesce));
1397
1398 coal->rx_coalesce_usecs = bp->rx_ticks;
1399 coal->tx_coalesce_usecs = bp->tx_ticks;
1400
1401 return 0;
1402}
1403
1404static int bnx2x_set_coalesce(struct net_device *dev,
1405 struct ethtool_coalesce *coal)
1406{
1407 struct bnx2x *bp = netdev_priv(dev);
1408
1409 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1410 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1411 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1412
1413 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1414 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1415 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1416
1417 if (netif_running(dev))
1418 bnx2x_update_coalesce(bp);
1419
1420 return 0;
1421}
1422
1423static void bnx2x_get_ringparam(struct net_device *dev,
1424 struct ethtool_ringparam *ering)
1425{
1426 struct bnx2x *bp = netdev_priv(dev);
1427
1428 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1429
25141580
DK		 1430 if (bp->rx_ring_size)
1431 ering->rx_pending = bp->rx_ring_size;
1432 else
c2188952 1433 ering->rx_pending = MAX_RX_AVAIL;
25141580 1434
a3348722 1435 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1436 ering->tx_pending = bp->tx_ring_size;
1437}
1438
1439static int bnx2x_set_ringparam(struct net_device *dev,
1440 struct ethtool_ringparam *ering)
1441{
1442 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1443
1444 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1445 DP(BNX2X_MSG_ETHTOOL,
1446 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1447 return -EAGAIN;
1448 }
1449
1450 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1451 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1452 MIN_RX_SIZE_TPA)) ||
a3348722 1453 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1454 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1455 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1456 return -EINVAL;
51c1a580 1457 }
de0c62db
DK		 1458
1459 bp->rx_ring_size = ering->rx_pending;
1460 bp->tx_ring_size = ering->tx_pending;
1461
a9fccec7 1462 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1463}
1464
1465static void bnx2x_get_pauseparam(struct net_device *dev,
1466 struct ethtool_pauseparam *epause)
1467{
1468 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1469 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1470 int cfg_reg;
1471
a22f0788
YR		 1472 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1473 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1474
9e7e8399 1475 if (!epause->autoneg)
241fb5d2 1476 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1477 else
1478 cfg_reg = bp->link_params.req_fc_auto_adv;
1479
1480 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1481 BNX2X_FLOW_CTRL_RX);
9e7e8399 1482 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1483 BNX2X_FLOW_CTRL_TX);
1484
51c1a580 1485 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1486 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1487 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1488}
1489
1490static int bnx2x_set_pauseparam(struct net_device *dev,
1491 struct ethtool_pauseparam *epause)
1492{
1493 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1494 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1495 if (IS_MF(bp))
de0c62db
DK		 1496 return 0;
1497
51c1a580 1498 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1499 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1500 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1501
a22f0788 1502 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1503
1504 if (epause->rx_pause)
a22f0788 1505 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1506
1507 if (epause->tx_pause)
a22f0788 1508 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1509
a22f0788
YR		 1510 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1511 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1512
1513 if (epause->autoneg) {
a22f0788 1514 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1515 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1516 return -EINVAL;
1517 }
1518
a22f0788
YR		 1519 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1520 bp->link_params.req_flow_ctrl[cfg_idx] =
1521 BNX2X_FLOW_CTRL_AUTO;
1522 }
de0c62db
DK		 1523 }
1524
51c1a580 1525 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1526 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1527
1528 if (netif_running(dev)) {
1529 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1530 bnx2x_link_set(bp);
1531 }
1532
1533 return 0;
1534}
1535
cf2c1df6
MS		 1536char *bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF] = {
1537 "register_test (offline) ",
1538 "memory_test (offline) ",
1539 "int_loopback_test (offline)",
1540 "ext_loopback_test (offline)",
1541 "nvram_test (online) ",
1542 "interrupt_test (online) ",
1543 "link_test (online) "
de0c62db
DK		 1544};
1545
e9939c80
YM		 1546static u32 bnx2x_eee_to_adv(u32 eee_adv)
1547{
1548 u32 modes = 0;
1549
1550 if (eee_adv & SHMEM_EEE_100M_ADV)
1551 modes |= ADVERTISED_100baseT_Full;
1552 if (eee_adv & SHMEM_EEE_1G_ADV)
1553 modes |= ADVERTISED_1000baseT_Full;
1554 if (eee_adv & SHMEM_EEE_10G_ADV)
1555 modes |= ADVERTISED_10000baseT_Full;
1556
1557 return modes;
1558}
1559
1560static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1561{
1562 u32 eee_adv = 0;
1563 if (modes & ADVERTISED_100baseT_Full)
1564 eee_adv |= SHMEM_EEE_100M_ADV;
1565 if (modes & ADVERTISED_1000baseT_Full)
1566 eee_adv |= SHMEM_EEE_1G_ADV;
1567 if (modes & ADVERTISED_10000baseT_Full)
1568 eee_adv |= SHMEM_EEE_10G_ADV;
1569
1570 return eee_adv << shift;
1571}
1572
1573static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1574{
1575 struct bnx2x *bp = netdev_priv(dev);
1576 u32 eee_cfg;
1577
1578 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1579 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1580 return -EOPNOTSUPP;
1581 }
1582
1583 eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1584
1585 edata->supported =
1586 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1587 SHMEM_EEE_SUPPORTED_SHIFT);
1588
1589 edata->advertised =
1590 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1591 SHMEM_EEE_ADV_STATUS_SHIFT);
1592 edata->lp_advertised =
1593 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1594 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1595
1596 /* SHMEM value is in 16u units --> Convert to 1u units. */
1597 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1598
1599 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1600 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1601 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1602
1603 return 0;
1604}
1605
1606static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1607{
1608 struct bnx2x *bp = netdev_priv(dev);
1609 u32 eee_cfg;
1610 u32 advertised;
1611
1612 if (IS_MF(bp))
1613 return 0;
1614
1615 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1616 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1617 return -EOPNOTSUPP;
1618 }
1619
1620 eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1621
1622 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1623 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1624 return -EOPNOTSUPP;
1625 }
1626
1627 advertised = bnx2x_adv_to_eee(edata->advertised,
1628 SHMEM_EEE_ADV_STATUS_SHIFT);
1629 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1630 DP(BNX2X_MSG_ETHTOOL,
1631 "Direct manipulation of EEE advertisment is not supported\n");
1632 return -EINVAL;
1633 }
1634
1635 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1636 DP(BNX2X_MSG_ETHTOOL,
1637 "Maximal Tx Lpi timer supported is %x(u)\n",
1638 EEE_MODE_TIMER_MASK);
1639 return -EINVAL;
1640 }
1641 if (edata->tx_lpi_enabled &&
1642 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1643 DP(BNX2X_MSG_ETHTOOL,
1644 "Minimal Tx Lpi timer supported is %d(u)\n",
1645 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1646 return -EINVAL;
1647 }
1648
1649 /* All is well; Apply changes*/
1650 if (edata->eee_enabled)
1651 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1652 else
1653 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1654
1655 if (edata->tx_lpi_enabled)
1656 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1657 else
1658 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1659
1660 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1661 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1662 EEE_MODE_TIMER_MASK) |
1663 EEE_MODE_OVERRIDE_NVRAM |
1664 EEE_MODE_OUTPUT_TIME;
1665
1666 /* Restart link to propogate changes */
1667 if (netif_running(dev)) {
1668 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1669 bnx2x_link_set(bp);
1670 }
1671
1672 return 0;
1673}
1674
1675
619c5cb6
VZ		 1676enum {
1677 BNX2X_CHIP_E1_OFST = 0,
1678 BNX2X_CHIP_E1H_OFST,
1679 BNX2X_CHIP_E2_OFST,
1680 BNX2X_CHIP_E3_OFST,
1681 BNX2X_CHIP_E3B0_OFST,
1682 BNX2X_CHIP_MAX_OFST
1683};
1684
1685#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1686#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1687#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1688#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1689#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1690
1691#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1692#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1693
de0c62db
DK		 1694static int bnx2x_test_registers(struct bnx2x *bp)
1695{
1696 int idx, i, rc = -ENODEV;
619c5cb6 1697 u32 wr_val = 0, hw;
de0c62db
DK		 1698 int port = BP_PORT(bp);
1699 static const struct {
619c5cb6 1700 u32 hw;
de0c62db
DK		 1701 u32 offset0;
1702 u32 offset1;
1703 u32 mask;
1704 } reg_tbl[] = {
619c5cb6
VZ		 1705/* 0 */ { BNX2X_CHIP_MASK_ALL,
1706 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1707 { BNX2X_CHIP_MASK_ALL,
1708 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1709 { BNX2X_CHIP_MASK_E1X,
1710 HC_REG_AGG_INT_0, 4, 0x000003ff },
1711 { BNX2X_CHIP_MASK_ALL,
1712 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1713 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1714 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1715 { BNX2X_CHIP_MASK_E3B0,
1716 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1717 { BNX2X_CHIP_MASK_ALL,
1718 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1719 { BNX2X_CHIP_MASK_ALL,
1720 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1721 { BNX2X_CHIP_MASK_ALL,
1722 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1723 { BNX2X_CHIP_MASK_ALL,
1724 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1725/* 10 */ { BNX2X_CHIP_MASK_ALL,
1726 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1727 { BNX2X_CHIP_MASK_ALL,
1728 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1729 { BNX2X_CHIP_MASK_ALL,
1730 QM_REG_CONNNUM_0, 4, 0x000fffff },
1731 { BNX2X_CHIP_MASK_ALL,
1732 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1733 { BNX2X_CHIP_MASK_ALL,
1734 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1735 { BNX2X_CHIP_MASK_ALL,
1736 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1737 { BNX2X_CHIP_MASK_ALL,
1738 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1739 { BNX2X_CHIP_MASK_ALL,
1740 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1741 { BNX2X_CHIP_MASK_ALL,
1742 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1743 { BNX2X_CHIP_MASK_ALL,
1744 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1745/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1746 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1747 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1748 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1749 { BNX2X_CHIP_MASK_ALL,
1750 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1751 { BNX2X_CHIP_MASK_ALL,
1752 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1753 { BNX2X_CHIP_MASK_ALL,
1754 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1755 { BNX2X_CHIP_MASK_ALL,
1756 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1757 { BNX2X_CHIP_MASK_ALL,
1758 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1759 { BNX2X_CHIP_MASK_ALL,
1760 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1761 { BNX2X_CHIP_MASK_ALL,
1762 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1763 { BNX2X_CHIP_MASK_ALL,
1764 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1765/* 30 */ { BNX2X_CHIP_MASK_ALL,
1766 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1767 { BNX2X_CHIP_MASK_ALL,
1768 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1769 { BNX2X_CHIP_MASK_ALL,
1770 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1771 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1772 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1773 { BNX2X_CHIP_MASK_ALL,
1774 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1775 { BNX2X_CHIP_MASK_ALL,
1776 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1777 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1778 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1779 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1780 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1781
1782 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1783 };
1784
51c1a580
MS		 1785 if (!netif_running(bp->dev)) {
1786 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1787 "cannot access eeprom when the interface is down\n");
de0c62db 1788 return rc;
51c1a580 1789 }
de0c62db 1790
619c5cb6
VZ		 1791 if (CHIP_IS_E1(bp))
1792 hw = BNX2X_CHIP_MASK_E1;
1793 else if (CHIP_IS_E1H(bp))
1794 hw = BNX2X_CHIP_MASK_E1H;
1795 else if (CHIP_IS_E2(bp))
1796 hw = BNX2X_CHIP_MASK_E2;
1797 else if (CHIP_IS_E3B0(bp))
1798 hw = BNX2X_CHIP_MASK_E3B0;
1799 else /* e3 A0 */
1800 hw = BNX2X_CHIP_MASK_E3;
1801
de0c62db
DK		 1802 /* Repeat the test twice:
1803 First by writing 0x00000000, second by writing 0xffffffff */
1804 for (idx = 0; idx < 2; idx++) {
1805
1806 switch (idx) {
1807 case 0:
1808 wr_val = 0;
1809 break;
1810 case 1:
1811 wr_val = 0xffffffff;
1812 break;
1813 }
1814
1815 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1816 u32 offset, mask, save_val, val;
619c5cb6 1817 if (!(hw & reg_tbl[i].hw))
f2e0899f 1818 continue;
de0c62db
DK		 1819
1820 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1821 mask = reg_tbl[i].mask;
1822
1823 save_val = REG_RD(bp, offset);
1824
ec6ba945 1825 REG_WR(bp, offset, wr_val & mask);
f85582f8 1826
de0c62db
DK		 1827 val = REG_RD(bp, offset);
1828
1829 /* Restore the original register's value */
1830 REG_WR(bp, offset, save_val);
1831
1832 /* verify value is as expected */
1833 if ((val & mask) != (wr_val & mask)) {
51c1a580 1834 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1835 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1836 offset, val, wr_val, mask);
1837 goto test_reg_exit;
1838 }
1839 }
1840 }
1841
1842 rc = 0;
1843
1844test_reg_exit:
1845 return rc;
1846}
1847
1848static int bnx2x_test_memory(struct bnx2x *bp)
1849{
1850 int i, j, rc = -ENODEV;
619c5cb6 1851 u32 val, index;
de0c62db
DK		 1852 static const struct {
1853 u32 offset;
1854 int size;
1855 } mem_tbl[] = {
1856 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1857 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1858 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1859 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1860 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1861 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1862 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1863
1864 { 0xffffffff, 0 }
1865 };
619c5cb6 1866
de0c62db
DK		 1867 static const struct {
1868 char *name;
1869 u32 offset;
619c5cb6 1870 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1871 } prty_tbl[] = {
619c5cb6
VZ		 1872 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1873 {0x3ffc0, 0, 0, 0} },
1874 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1875 {0x2, 0x2, 0, 0} },
1876 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1877 {0, 0, 0, 0} },
1878 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1879 {0x3ffc0, 0, 0, 0} },
1880 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1881 {0x3ffc0, 0, 0, 0} },
1882 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1883 {0x3ffc1, 0, 0, 0} },
1884
1885 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1886 };
1887
51c1a580
MS		 1888 if (!netif_running(bp->dev)) {
1889 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1890 "cannot access eeprom when the interface is down\n");
de0c62db 1891 return rc;
51c1a580 1892 }
de0c62db 1893
619c5cb6
VZ		 1894 if (CHIP_IS_E1(bp))
1895 index = BNX2X_CHIP_E1_OFST;
1896 else if (CHIP_IS_E1H(bp))
1897 index = BNX2X_CHIP_E1H_OFST;
1898 else if (CHIP_IS_E2(bp))
1899 index = BNX2X_CHIP_E2_OFST;
1900 else /* e3 */
1901 index = BNX2X_CHIP_E3_OFST;
1902
f2e0899f
DK		 1903 /* pre-Check the parity status */
1904 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1905 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1906 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1907 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 1908 "%s is 0x%x\n", prty_tbl[i].name, val);
1909 goto test_mem_exit;
1910 }
1911 }
1912
de0c62db
DK		 1913 /* Go through all the memories */
1914 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1915 for (j = 0; j < mem_tbl[i].size; j++)
1916 REG_RD(bp, mem_tbl[i].offset + j*4);
1917
1918 /* Check the parity status */
1919 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1920 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1921 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1922 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1923 "%s is 0x%x\n", prty_tbl[i].name, val);
1924 goto test_mem_exit;
1925 }
1926 }
1927
1928 rc = 0;
1929
1930test_mem_exit:
1931 return rc;
1932}
1933
a22f0788 1934static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1935{
f2e0899f 1936 int cnt = 1400;
de0c62db 1937
619c5cb6 1938 if (link_up) {
a22f0788 1939 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 1940 msleep(20);
1941
1942 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 1943 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 1944
1945 cnt = 1400;
1946 while (!bp->link_vars.link_up && cnt--)
1947 msleep(20);
1948
1949 if (cnt <= 0 && !bp->link_vars.link_up)
1950 DP(BNX2X_MSG_ETHTOOL,
1951 "Timeout waiting for link init\n");
619c5cb6 1952 }
de0c62db
DK		 1953}
1954
619c5cb6 1955static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 1956{
1957 unsigned int pkt_size, num_pkts, i;
1958 struct sk_buff *skb;
1959 unsigned char *packet;
1960 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1961 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 1962 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 1963 u16 tx_start_idx, tx_idx;
1964 u16 rx_start_idx, rx_idx;
b0700b1e 1965 u16 pkt_prod, bd_prod;
de0c62db
DK		 1966 struct sw_tx_bd *tx_buf;
1967 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1968 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1969 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1970 dma_addr_t mapping;
1971 union eth_rx_cqe *cqe;
619c5cb6 1972 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 1973 struct sw_rx_bd *rx_buf;
1974 u16 len;
1975 int rc = -ENODEV;
e52fcb24 1976 u8 *data;
8970b2e4
MS		 1977 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
1978 txdata->txq_index);
de0c62db
DK		 1979
1980 /* check the loopback mode */
1981 switch (loopback_mode) {
1982 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 1983 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
1984 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 1985 return -EINVAL;
8970b2e4 1986 }
de0c62db
DK		 1987 break;
1988 case BNX2X_MAC_LOOPBACK:
32911333
YR		 1989 if (CHIP_IS_E3(bp)) {
1990 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1991 if (bp->port.supported[cfg_idx] &
1992 (SUPPORTED_10000baseT_Full |
1993 SUPPORTED_20000baseMLD2_Full |
1994 SUPPORTED_20000baseKR2_Full))
1995 bp->link_params.loopback_mode = LOOPBACK_XMAC;
1996 else
1997 bp->link_params.loopback_mode = LOOPBACK_UMAC;
1998 } else
1999 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2000
de0c62db
DK		 2001 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2002 break;
8970b2e4
MS		 2003 case BNX2X_EXT_LOOPBACK:
2004 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2005 DP(BNX2X_MSG_ETHTOOL,
2006 "Can't configure external loopback\n");
2007 return -EINVAL;
2008 }
2009 break;
de0c62db 2010 default:
51c1a580 2011 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2012 return -EINVAL;
2013 }
2014
2015 /* prepare the loopback packet */
2016 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2017 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2018 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2019 if (!skb) {
51c1a580 2020 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2021 rc = -ENOMEM;
2022 goto test_loopback_exit;
2023 }
2024 packet = skb_put(skb, pkt_size);
2025 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2026 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2027 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2028 for (i = ETH_HLEN; i < pkt_size; i++)
2029 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2030 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2031 skb_headlen(skb), DMA_TO_DEVICE);
2032 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2033 rc = -ENOMEM;
2034 dev_kfree_skb(skb);
51c1a580 2035 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2036 goto test_loopback_exit;
2037 }
de0c62db
DK		 2038
2039 /* send the loopback packet */
2040 num_pkts = 0;
6383c0b3 2041 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2042 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2043
73dbb5e1
DK		 2044 netdev_tx_sent_queue(txq, skb->len);
2045
6383c0b3
AE		 2046 pkt_prod = txdata->tx_pkt_prod++;
2047 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2048 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2049 tx_buf->skb = skb;
2050 tx_buf->flags = 0;
2051
6383c0b3
AE		 2052 bd_prod = TX_BD(txdata->tx_bd_prod);
2053 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2054 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2055 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2056 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2057 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2058 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2059 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2060 SET_FLAG(tx_start_bd->general_data,
2061 ETH_TX_START_BD_ETH_ADDR_TYPE,
2062 UNICAST_ADDRESS);
2063 SET_FLAG(tx_start_bd->general_data,
2064 ETH_TX_START_BD_HDR_NBDS,
2065 1);
de0c62db
DK		 2066
2067 /* turn on parsing and get a BD */
2068 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2069
6383c0b3
AE		 2070 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2071 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 2072
f2e0899f 2073 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 2074 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 2075
2076 wmb();
2077
6383c0b3 2078 txdata->tx_db.data.prod += 2;
de0c62db 2079 barrier();
6383c0b3 2080 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2081
2082 mmiowb();
619c5cb6 2083 barrier();
de0c62db
DK		 2084
2085 num_pkts++;
6383c0b3 2086 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2087
2088 udelay(100);
2089
6383c0b3 2090 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2091 if (tx_idx != tx_start_idx + num_pkts)
2092 goto test_loopback_exit;
2093
f2e0899f
DK		 2094 /* Unlike HC IGU won't generate an interrupt for status block
2095 * updates that have been performed while interrupts were
2096 * disabled.
2097 */
e1210d12
ED		 2098 if (bp->common.int_block == INT_BLOCK_IGU) {
2099 /* Disable local BHes to prevent a dead-lock situation between
2100 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2101 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2102 */
2103 local_bh_disable();
6383c0b3 2104 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2105 local_bh_enable();
2106 }
f2e0899f 2107
de0c62db
DK		 2108 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2109 if (rx_idx != rx_start_idx + num_pkts)
2110 goto test_loopback_exit;
2111
b0700b1e 2112 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2113 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2114 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2115 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2116 goto test_loopback_rx_exit;
2117
621b4d66 2118 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2119 if (len != pkt_size)
2120 goto test_loopback_rx_exit;
2121
2122 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2123 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2124 dma_unmap_addr(rx_buf, mapping),
2125 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2126 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2127 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2128 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2129 goto test_loopback_rx_exit;
2130
2131 rc = 0;
2132
2133test_loopback_rx_exit:
2134
2135 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2136 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2137 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2138 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2139
2140 /* Update producers */
2141 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2142 fp_rx->rx_sge_prod);
2143
2144test_loopback_exit:
2145 bp->link_params.loopback_mode = LOOPBACK_NONE;
2146
2147 return rc;
2148}
2149
619c5cb6 2150static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2151{
2152 int rc = 0, res;
2153
2154 if (BP_NOMCP(bp))
2155 return rc;
2156
2157 if (!netif_running(bp->dev))
2158 return BNX2X_LOOPBACK_FAILED;
2159
2160 bnx2x_netif_stop(bp, 1);
2161 bnx2x_acquire_phy_lock(bp);
2162
619c5cb6 2163 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2164 if (res) {
51c1a580 2165 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2166 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2167 }
2168
619c5cb6 2169 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2170 if (res) {
51c1a580 2171 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2172 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2173 }
2174
2175 bnx2x_release_phy_lock(bp);
2176 bnx2x_netif_start(bp);
2177
2178 return rc;
2179}
2180
8970b2e4
MS		 2181static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2182{
2183 int rc;
2184 u8 is_serdes =
2185 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2186
2187 if (BP_NOMCP(bp))
2188 return -ENODEV;
2189
2190 if (!netif_running(bp->dev))
2191 return BNX2X_EXT_LOOPBACK_FAILED;
2192
2193 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2194 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2195 if (rc) {
2196 DP(BNX2X_MSG_ETHTOOL,
2197 "Can't perform self-test, nic_load (for external lb) failed\n");
2198 return -ENODEV;
2199 }
2200 bnx2x_wait_for_link(bp, 1, is_serdes);
2201
2202 bnx2x_netif_stop(bp, 1);
2203
2204 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2205 if (rc)
2206 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2207
2208 bnx2x_netif_start(bp);
2209
2210 return rc;
2211}
2212
de0c62db
DK		 2213#define CRC32_RESIDUAL 0xdebb20e3
2214
2215static int bnx2x_test_nvram(struct bnx2x *bp)
2216{
2217 static const struct {
2218 int offset;
2219 int size;
2220 } nvram_tbl[] = {
2221 { 0, 0x14 }, /* bootstrap */
2222 { 0x14, 0xec }, /* dir */
2223 { 0x100, 0x350 }, /* manuf_info */
2224 { 0x450, 0xf0 }, /* feature_info */
2225 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2226 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2227 { 0, 0 }
2228 };
afa13b4b
MY		 2229 __be32 *buf;
2230 u8 *data;
de0c62db
DK		 2231 int i, rc;
2232 u32 magic, crc;
2233
2234 if (BP_NOMCP(bp))
2235 return 0;
2236
afa13b4b
MY		 2237 buf = kmalloc(0x350, GFP_KERNEL);
2238 if (!buf) {
51c1a580 2239 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2240 rc = -ENOMEM;
2241 goto test_nvram_exit;
2242 }
2243 data = (u8 *)buf;
2244
de0c62db
DK		 2245 rc = bnx2x_nvram_read(bp, 0, data, 4);
2246 if (rc) {
51c1a580
MS		 2247 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2248 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2249 goto test_nvram_exit;
2250 }
2251
2252 magic = be32_to_cpu(buf[0]);
2253 if (magic != 0x669955aa) {
51c1a580
MS		 2254 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2255 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2256 rc = -ENODEV;
2257 goto test_nvram_exit;
2258 }
2259
2260 for (i = 0; nvram_tbl[i].size; i++) {
2261
2262 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2263 nvram_tbl[i].size);
2264 if (rc) {
51c1a580 2265 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2266 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2267 goto test_nvram_exit;
2268 }
2269
2270 crc = ether_crc_le(nvram_tbl[i].size, data);
2271 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2272 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2273 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2274 rc = -ENODEV;
2275 goto test_nvram_exit;
2276 }
2277 }
2278
2279test_nvram_exit:
afa13b4b 2280 kfree(buf);
de0c62db
DK		 2281 return rc;
2282}
2283
619c5cb6 2284/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2285static int bnx2x_test_intr(struct bnx2x *bp)
2286{
3b603066 2287 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2288
51c1a580
MS		 2289 if (!netif_running(bp->dev)) {
2290 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2291 "cannot access eeprom when the interface is down\n");
de0c62db 2292 return -ENODEV;
51c1a580 2293 }
de0c62db 2294
15192a8c 2295 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2296 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2297
619c5cb6
VZ		 2298 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2299
2300 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2301}
2302
2303static void bnx2x_self_test(struct net_device *dev,
2304 struct ethtool_test *etest, u64 *buf)
2305{
2306 struct bnx2x *bp = netdev_priv(dev);
a22f0788 2307 u8 is_serdes;
cf2c1df6
MS		 2308 int rc;
2309
de0c62db 2310 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2311 netdev_err(bp->dev,
2312 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2313 etest->flags |= ETH_TEST_FL_FAILED;
2314 return;
2315 }
8970b2e4
MS		 2316 DP(BNX2X_MSG_ETHTOOL,
2317 "Self-test command parameters: offline = %d, external_lb = %d\n",
2318 (etest->flags & ETH_TEST_FL_OFFLINE),
2319 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2320
cf2c1df6 2321 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2322
cf2c1df6
MS		 2323 if (!netif_running(dev)) {
2324 DP(BNX2X_MSG_ETHTOOL,
2325 "Can't perform self-test when interface is down\n");
de0c62db 2326 return;
cf2c1df6 2327 }
de0c62db 2328
a22f0788 2329 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db 2330
cf2c1df6
MS		 2331 /* offline tests are not supported in MF mode */
2332 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2333 int port = BP_PORT(bp);
2334 u32 val;
2335 u8 link_up;
2336
2337 /* save current value of input enable for TX port IF */
2338 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2339 /* disable input for TX port IF */
2340 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2341
a22f0788
YR		 2342 link_up = bp->link_vars.link_up;
2343
de0c62db 2344 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
cf2c1df6
MS		 2345 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2346 if (rc) {
2347 etest->flags |= ETH_TEST_FL_FAILED;
2348 DP(BNX2X_MSG_ETHTOOL,
2349 "Can't perform self-test, nic_load (for offline) failed\n");
2350 return;
2351 }
2352
de0c62db 2353 /* wait until link state is restored */
619c5cb6 2354 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2355
2356 if (bnx2x_test_registers(bp) != 0) {
2357 buf[0] = 1;
2358 etest->flags |= ETH_TEST_FL_FAILED;
2359 }
2360 if (bnx2x_test_memory(bp) != 0) {
2361 buf[1] = 1;
2362 etest->flags |= ETH_TEST_FL_FAILED;
2363 }
f85582f8 2364
8970b2e4 2365 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2366 if (buf[2] != 0)
2367 etest->flags |= ETH_TEST_FL_FAILED;
2368
8970b2e4
MS		 2369 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2370 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2371 if (buf[3] != 0)
2372 etest->flags |= ETH_TEST_FL_FAILED;
2373 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2374 }
2375
de0c62db
DK		 2376 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2377
2378 /* restore input for TX port IF */
2379 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2380 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2381 if (rc) {
2382 etest->flags |= ETH_TEST_FL_FAILED;
2383 DP(BNX2X_MSG_ETHTOOL,
2384 "Can't perform self-test, nic_load (for online) failed\n");
2385 return;
2386 }
de0c62db 2387 /* wait until link state is restored */
a22f0788 2388 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2389 }
2390 if (bnx2x_test_nvram(bp) != 0) {
cf2c1df6
MS		 2391 if (!IS_MF(bp))
2392 buf[4] = 1;
2393 else
2394 buf[0] = 1;
de0c62db
DK		 2395 etest->flags |= ETH_TEST_FL_FAILED;
2396 }
2397 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 2398 if (!IS_MF(bp))
2399 buf[5] = 1;
2400 else
2401 buf[1] = 1;
de0c62db
DK		 2402 etest->flags |= ETH_TEST_FL_FAILED;
2403 }
633ac363
DK		 2404
2405 if (bnx2x_link_test(bp, is_serdes) != 0) {
cf2c1df6
MS		 2406 if (!IS_MF(bp))
2407 buf[6] = 1;
2408 else
2409 buf[2] = 1;
633ac363
DK		 2410 etest->flags |= ETH_TEST_FL_FAILED;
2411 }
de0c62db
DK		 2412
2413#ifdef BNX2X_EXTRA_DEBUG
2414 bnx2x_panic_dump(bp);
2415#endif
2416}
2417
de0c62db
DK		 2418#define IS_PORT_STAT(i) \
2419 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2420#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2421#define IS_MF_MODE_STAT(bp) \
2422 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2423
619c5cb6
VZ		 2424/* ethtool statistics are displayed for all regular ethernet queues and the
2425 * fcoe L2 queue if not disabled
2426 */
1191cb83 2427static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2428{
2429 return BNX2X_NUM_ETH_QUEUES(bp);
2430}
2431
de0c62db
DK		 2432static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2433{
2434 struct bnx2x *bp = netdev_priv(dev);
2435 int i, num_stats;
2436
2437 switch (stringset) {
2438 case ETH_SS_STATS:
2439 if (is_multi(bp)) {
619c5cb6 2440 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2441 BNX2X_NUM_Q_STATS;
2442 } else
2443 num_stats = 0;
2444 if (IS_MF_MODE_STAT(bp)) {
2445 for (i = 0; i < BNX2X_NUM_STATS; i++)
2446 if (IS_FUNC_STAT(i))
2447 num_stats++;
2448 } else
2449 num_stats += BNX2X_NUM_STATS;
2450
de0c62db
DK		 2451 return num_stats;
2452
2453 case ETH_SS_TEST:
cf2c1df6 2454 return BNX2X_NUM_TESTS(bp);
de0c62db
DK		 2455
2456 default:
2457 return -EINVAL;
2458 }
2459}
2460
2461static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2462{
2463 struct bnx2x *bp = netdev_priv(dev);
cf2c1df6 2464 int i, j, k, offset, start;
ec6ba945 2465 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2466
2467 switch (stringset) {
2468 case ETH_SS_STATS:
d5e83632 2469 k = 0;
de0c62db 2470 if (is_multi(bp)) {
619c5cb6 2471 for_each_eth_queue(bp, i) {
ec6ba945 2472 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2473 sprintf(queue_name, "%d", i);
de0c62db 2474 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2475 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2476 ETH_GSTRING_LEN,
2477 bnx2x_q_stats_arr[j].string,
2478 queue_name);
de0c62db
DK		 2479 k += BNX2X_NUM_Q_STATS;
2480 }
de0c62db 2481 }
d5e83632
YM		 2482
2483
2484 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2485 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2486 continue;
2487 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2488 bnx2x_stats_arr[i].string);
2489 j++;
2490 }
2491
de0c62db
DK		 2492 break;
2493
2494 case ETH_SS_TEST:
cf2c1df6
MS		 2495 /* First 4 tests cannot be done in MF mode */
2496 if (!IS_MF(bp))
2497 start = 0;
2498 else
2499 start = 4;
2500 for (i = 0, j = start; j < (start + BNX2X_NUM_TESTS(bp));
2501 i++, j++) {
2502 offset = sprintf(buf+32*i, "%s",
2503 bnx2x_tests_str_arr[j]);
2504 *(buf+offset) = '\0';
2505 }
de0c62db
DK		 2506 break;
2507 }
2508}
2509
2510static void bnx2x_get_ethtool_stats(struct net_device *dev,
2511 struct ethtool_stats *stats, u64 *buf)
2512{
2513 struct bnx2x *bp = netdev_priv(dev);
2514 u32 *hw_stats, *offset;
d5e83632 2515 int i, j, k = 0;
de0c62db
DK		 2516
2517 if (is_multi(bp)) {
619c5cb6 2518 for_each_eth_queue(bp, i) {
15192a8c 2519 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 2520 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2521 if (bnx2x_q_stats_arr[j].size == 0) {
2522 /* skip this counter */
2523 buf[k + j] = 0;
2524 continue;
2525 }
2526 offset = (hw_stats +
2527 bnx2x_q_stats_arr[j].offset);
2528 if (bnx2x_q_stats_arr[j].size == 4) {
2529 /* 4-byte counter */
2530 buf[k + j] = (u64) *offset;
2531 continue;
2532 }
2533 /* 8-byte counter */
2534 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2535 }
2536 k += BNX2X_NUM_Q_STATS;
2537 }
d5e83632
YM		 2538 }
2539
2540 hw_stats = (u32 *)&bp->eth_stats;
2541 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2542 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2543 continue;
2544 if (bnx2x_stats_arr[i].size == 0) {
2545 /* skip this counter */
2546 buf[k + j] = 0;
2547 j++;
2548 continue;
de0c62db 2549 }
d5e83632
YM		 2550 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2551 if (bnx2x_stats_arr[i].size == 4) {
2552 /* 4-byte counter */
2553 buf[k + j] = (u64) *offset;
de0c62db 2554 j++;
d5e83632 2555 continue;
de0c62db 2556 }
d5e83632
YM		 2557 /* 8-byte counter */
2558 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2559 j++;
de0c62db
DK		 2560 }
2561}
2562
32d36134 2563static int bnx2x_set_phys_id(struct net_device *dev,
2564 enum ethtool_phys_id_state state)
de0c62db
DK		 2565{
2566 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2567
51c1a580
MS		 2568 if (!netif_running(dev)) {
2569 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2570 "cannot access eeprom when the interface is down\n");
32d36134 2571 return -EAGAIN;
51c1a580 2572 }
de0c62db 2573
51c1a580
MS		 2574 if (!bp->port.pmf) {
2575 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2576 return -EOPNOTSUPP;
51c1a580 2577 }
de0c62db 2578
32d36134 2579 switch (state) {
2580 case ETHTOOL_ID_ACTIVE:
fce55922 2581 return 1; /* cycle on/off once per second */
de0c62db 2582
32d36134 2583 case ETHTOOL_ID_ON:
2584 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2585 LED_MODE_ON, SPEED_1000);
32d36134 2586 break;
de0c62db 2587
32d36134 2588 case ETHTOOL_ID_OFF:
2589 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2590 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2591
32d36134 2592 break;
2593
2594 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2595 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2596 LED_MODE_OPER,
2597 bp->link_vars.line_speed);
32d36134 2598 }
de0c62db
DK		 2599
2600 return 0;
2601}
2602
5d317c6a
MS		 2603static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2604{
2605
2606 switch (info->flow_type) {
2607 case TCP_V4_FLOW:
2608 case TCP_V6_FLOW:
2609 info->data = RXH_IP_SRC | RXH_IP_DST |
2610 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2611 break;
2612 case UDP_V4_FLOW:
2613 if (bp->rss_conf_obj.udp_rss_v4)
2614 info->data = RXH_IP_SRC | RXH_IP_DST |
2615 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2616 else
2617 info->data = RXH_IP_SRC | RXH_IP_DST;
2618 break;
2619 case UDP_V6_FLOW:
2620 if (bp->rss_conf_obj.udp_rss_v6)
2621 info->data = RXH_IP_SRC | RXH_IP_DST |
2622 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2623 else
2624 info->data = RXH_IP_SRC | RXH_IP_DST;
2625 break;
2626 case IPV4_FLOW:
2627 case IPV6_FLOW:
2628 info->data = RXH_IP_SRC | RXH_IP_DST;
2629 break;
2630 default:
2631 info->data = 0;
2632 break;
2633 }
2634
2635 return 0;
2636}
2637
ab532cf3 2638static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2639 u32 *rules __always_unused)
ab532cf3
TH		 2640{
2641 struct bnx2x *bp = netdev_priv(dev);
2642
2643 switch (info->cmd) {
2644 case ETHTOOL_GRXRINGS:
2645 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2646 return 0;
5d317c6a
MS		 2647 case ETHTOOL_GRXFH:
2648 return bnx2x_get_rss_flags(bp, info);
2649 default:
2650 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2651 return -EOPNOTSUPP;
2652 }
2653}
2654
2655static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2656{
2657 int udp_rss_requested;
2658
2659 DP(BNX2X_MSG_ETHTOOL,
2660 "Set rss flags command parameters: flow type = %d, data = %llu\n",
2661 info->flow_type, info->data);
2662
2663 switch (info->flow_type) {
2664 case TCP_V4_FLOW:
2665 case TCP_V6_FLOW:
2666 /* For TCP only 4-tupple hash is supported */
2667 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2668 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2669 DP(BNX2X_MSG_ETHTOOL,
2670 "Command parameters not supported\n");
2671 return -EINVAL;
2672 } else {
2673 return 0;
2674 }
2675
2676 case UDP_V4_FLOW:
2677 case UDP_V6_FLOW:
2678 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2679 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2680 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2681 udp_rss_requested = 1;
2682 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2683 udp_rss_requested = 0;
2684 else
2685 return -EINVAL;
2686 if ((info->flow_type == UDP_V4_FLOW) &&
2687 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2688 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2689 DP(BNX2X_MSG_ETHTOOL,
2690 "rss re-configured, UDP 4-tupple %s\n",
2691 udp_rss_requested ? "enabled" : "disabled");
2692 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2693 } else if ((info->flow_type == UDP_V6_FLOW) &&
2694 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
2695 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
2696 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2697 DP(BNX2X_MSG_ETHTOOL,
2698 "rss re-configured, UDP 4-tupple %s\n",
2699 udp_rss_requested ? "enabled" : "disabled");
2700 } else {
2701 return 0;
2702 }
2703 case IPV4_FLOW:
2704 case IPV6_FLOW:
2705 /* For IP only 2-tupple hash is supported */
2706 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
2707 DP(BNX2X_MSG_ETHTOOL,
2708 "Command parameters not supported\n");
2709 return -EINVAL;
2710 } else {
2711 return 0;
2712 }
2713 case SCTP_V4_FLOW:
2714 case AH_ESP_V4_FLOW:
2715 case AH_V4_FLOW:
2716 case ESP_V4_FLOW:
2717 case SCTP_V6_FLOW:
2718 case AH_ESP_V6_FLOW:
2719 case AH_V6_FLOW:
2720 case ESP_V6_FLOW:
2721 case IP_USER_FLOW:
2722 case ETHER_FLOW:
2723 /* RSS is not supported for these protocols */
2724 if (info->data) {
2725 DP(BNX2X_MSG_ETHTOOL,
2726 "Command parameters not supported\n");
2727 return -EINVAL;
2728 } else {
2729 return 0;
2730 }
2731 default:
2732 return -EINVAL;
2733 }
2734}
2735
2736static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
2737{
2738 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 2739
5d317c6a
MS		 2740 switch (info->cmd) {
2741 case ETHTOOL_SRXFH:
2742 return bnx2x_set_rss_flags(bp, info);
ab532cf3 2743 default:
51c1a580 2744 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 2745 return -EOPNOTSUPP;
2746 }
2747}
2748
7850f63f
BH		 2749static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2750{
96305234 2751 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 2752}
2753
2754static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 2755{
2756 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 2757 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2758 size_t i;
ab532cf3 2759
619c5cb6
VZ		 2760 /* Get the current configuration of the RSS indirection table */
2761 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2762
2763 /*
2764 * We can't use a memcpy() as an internal storage of an
2765 * indirection table is a u8 array while indir->ring_index
2766 * points to an array of u32.
2767 *
2768 * Indirection table contains the FW Client IDs, so we need to
2769 * align the returned table to the Client ID of the leading RSS
2770 * queue.
2771 */
7850f63f
BH		 2772 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2773 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 2774
ab532cf3
TH		 2775 return 0;
2776}
2777
7850f63f 2778static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 2779{
2780 struct bnx2x *bp = netdev_priv(dev);
2781 size_t i;
619c5cb6
VZ		 2782
2783 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 2784 /*
2785 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2786 * as an internal storage of an indirection table is a u8 array
2787 * while indir->ring_index points to an array of u32.
2788 *
2789 * Indirection table contains the FW Client IDs, so we need to
2790 * align the received table to the Client ID of the leading RSS
2791 * queue
2792 */
5d317c6a 2793 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 2794 }
ab532cf3 2795
5d317c6a 2796 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 2797}
2798
de0c62db
DK		 2799static const struct ethtool_ops bnx2x_ethtool_ops = {
2800 .get_settings = bnx2x_get_settings,
2801 .set_settings = bnx2x_set_settings,
2802 .get_drvinfo = bnx2x_get_drvinfo,
2803 .get_regs_len = bnx2x_get_regs_len,
2804 .get_regs = bnx2x_get_regs,
2805 .get_wol = bnx2x_get_wol,
2806 .set_wol = bnx2x_set_wol,
2807 .get_msglevel = bnx2x_get_msglevel,
2808 .set_msglevel = bnx2x_set_msglevel,
2809 .nway_reset = bnx2x_nway_reset,
2810 .get_link = bnx2x_get_link,
2811 .get_eeprom_len = bnx2x_get_eeprom_len,
2812 .get_eeprom = bnx2x_get_eeprom,
2813 .set_eeprom = bnx2x_set_eeprom,
2814 .get_coalesce = bnx2x_get_coalesce,
2815 .set_coalesce = bnx2x_set_coalesce,
2816 .get_ringparam = bnx2x_get_ringparam,
2817 .set_ringparam = bnx2x_set_ringparam,
2818 .get_pauseparam = bnx2x_get_pauseparam,
2819 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2820 .self_test = bnx2x_self_test,
2821 .get_sset_count = bnx2x_get_sset_count,
2822 .get_strings = bnx2x_get_strings,
32d36134 2823 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2824 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 2825 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 2826 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 2827 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 2828 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2829 .set_rxfh_indir = bnx2x_set_rxfh_indir,
e9939c80
YM		 2830 .get_eee = bnx2x_get_eee,
2831 .set_eee = bnx2x_set_eee,
de0c62db
DK		 2832};
2833
2834void bnx2x_set_ethtool_ops(struct net_device *netdev)
2835{
2836 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2837}
kernel source for telekom puls (alcatel/mediatek)