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net: can: remove custom hex_to_bin()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/crc32.h>
22
23
24#include "bnx2x.h"
25#include "bnx2x_cmn.h"
26#include "bnx2x_dump.h"
4a33bc03 27#include "bnx2x_init.h"
042181f5 28#include "bnx2x_sp.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 66};
67
68#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70static const struct {
71 long offset;
72 int size;
73 u32 flags;
74#define STATS_FLAGS_PORT 1
75#define STATS_FLAGS_FUNC 2
76#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78} bnx2x_stats_arr[] = {
79/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
ec6ba945
VZ		 107 { STATS_OFFSET32(brb_drop_hi),
108 8, STATS_FLAGS_PORT, "rx_brb_discard" },
109 { STATS_OFFSET32(brb_truncate_hi),
110 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
111 { STATS_OFFSET32(pause_frames_received_hi),
112 8, STATS_FLAGS_PORT, "rx_pause_frames" },
113 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
114 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
115 { STATS_OFFSET32(nig_timer_max),
116 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
117/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
118 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
119 { STATS_OFFSET32(rx_skb_alloc_failed),
120 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
121 { STATS_OFFSET32(hw_csum_err),
122 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
123
124 { STATS_OFFSET32(total_bytes_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_bytes" },
126 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
127 8, STATS_FLAGS_PORT, "tx_error_bytes" },
128 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
130 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
132 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
134 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
135 8, STATS_FLAGS_PORT, "tx_mac_errors" },
136 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
137 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
138/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
139 8, STATS_FLAGS_PORT, "tx_single_collisions" },
140 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
141 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
143 8, STATS_FLAGS_PORT, "tx_deferred" },
144 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
147 8, STATS_FLAGS_PORT, "tx_late_collisions" },
148 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_total_collisions" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
151 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
153 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
155 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
157 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
158/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
159 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
160 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
161 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
162 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
163 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
164 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 165 8, STATS_FLAGS_PORT, "tx_pause_frames" },
166 { STATS_OFFSET32(total_tpa_aggregations_hi),
167 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
168 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
169 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
170 { STATS_OFFSET32(total_tpa_bytes_hi),
171 8, STATS_FLAGS_FUNC, "tpa_bytes"}
ec6ba945
VZ		 172};
173
174#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 175static int bnx2x_get_port_type(struct bnx2x *bp)
176{
177 int port_type;
178 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
179 switch (bp->link_params.phy[phy_idx].media_type) {
180 case ETH_PHY_SFP_FIBER:
181 case ETH_PHY_XFP_FIBER:
182 case ETH_PHY_KR:
183 case ETH_PHY_CX4:
184 port_type = PORT_FIBRE;
185 break;
186 case ETH_PHY_DA_TWINAX:
187 port_type = PORT_DA;
188 break;
189 case ETH_PHY_BASE_T:
190 port_type = PORT_TP;
191 break;
192 case ETH_PHY_NOT_PRESENT:
193 port_type = PORT_NONE;
194 break;
195 case ETH_PHY_UNSPECIFIED:
196 default:
197 port_type = PORT_OTHER;
198 break;
199 }
200 return port_type;
201}
ec6ba945 202
de0c62db
DK		 203static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
204{
205 struct bnx2x *bp = netdev_priv(dev);
a22f0788 206 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 207
a22f0788
YR		 208 /* Dual Media boards present all available port types */
209 cmd->supported = bp->port.supported[cfg_idx] |
210 (bp->port.supported[cfg_idx ^ 1] &
211 (SUPPORTED_TP | SUPPORTED_FIBRE));
212 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db
DK		 213
214 if ((bp->state == BNX2X_STATE_OPEN) &&
215 !(bp->flags & MF_FUNC_DIS) &&
216 (bp->link_vars.link_up)) {
b3337e4c 217 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 218 cmd->duplex = bp->link_vars.duplex;
de0c62db 219 } else {
b3337e4c
DD		 220 ethtool_cmd_speed_set(
221 cmd, bp->link_params.req_line_speed[cfg_idx]);
a22f0788 222 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
de0c62db 223 }
f2e0899f 224
0793f83f 225 if (IS_MF(bp))
b3337e4c 226 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 227
1ac9e428 228 cmd->port = bnx2x_get_port_type(bp);
a22f0788 229
de0c62db
DK		 230 cmd->phy_address = bp->mdio.prtad;
231 cmd->transceiver = XCVR_INTERNAL;
232
a22f0788 233 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 234 cmd->autoneg = AUTONEG_ENABLE;
235 else
236 cmd->autoneg = AUTONEG_DISABLE;
237
238 cmd->maxtxpkt = 0;
239 cmd->maxrxpkt = 0;
240
241 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
b3337e4c 242 DP_LEVEL " supported 0x%x advertising 0x%x speed %u\n"
de0c62db
DK		 243 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
244 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 245 cmd->cmd, cmd->supported, cmd->advertising,
246 ethtool_cmd_speed(cmd),
de0c62db
DK		 247 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
248 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
249
250 return 0;
251}
252
253static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
254{
255 struct bnx2x *bp = netdev_priv(dev);
a22f0788 256 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 257 u32 speed;
de0c62db 258
0793f83f 259 if (IS_MF_SD(bp))
de0c62db
DK		 260 return 0;
261
262 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
b3337e4c 263 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 264 " duplex %d port %d phy_address %d transceiver %d\n"
265 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 266 cmd->cmd, cmd->supported, cmd->advertising,
267 ethtool_cmd_speed(cmd),
de0c62db
DK		 268 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
269 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
270
b3337e4c 271 speed = ethtool_cmd_speed(cmd);
0793f83f
DK		 272
273 if (IS_MF_SI(bp)) {
e3835b99 274 u32 part;
0793f83f
DK		 275 u32 line_speed = bp->link_vars.line_speed;
276
277 /* use 10G if no link detected */
278 if (!line_speed)
279 line_speed = 10000;
280
281 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
282 BNX2X_DEV_INFO("To set speed BC %X or higher "
283 "is required, please upgrade BC\n",
284 REQ_BC_VER_4_SET_MF_BW);
285 return -EINVAL;
286 }
e3835b99 287
faa6fcbb 288 part = (speed * 100) / line_speed;
e3835b99 289
faa6fcbb
DK		 290 if (line_speed < speed || !part) {
291 BNX2X_DEV_INFO("Speed setting should be in a range "
292 "from 1%% to 100%% "
293 "of actual line speed\n");
0793f83f
DK		 294 return -EINVAL;
295 }
0793f83f 296
e3835b99
DK		 297 if (bp->state != BNX2X_STATE_OPEN)
298 /* store value for following "load" */
299 bp->pending_max = part;
300 else
301 bnx2x_update_max_mf_config(bp, part);
0793f83f 302
0793f83f
DK		 303 return 0;
304 }
305
a22f0788
YR		 306 cfg_idx = bnx2x_get_link_cfg_idx(bp);
307 old_multi_phy_config = bp->link_params.multi_phy_config;
308 switch (cmd->port) {
309 case PORT_TP:
310 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
311 break; /* no port change */
312
313 if (!(bp->port.supported[0] & SUPPORTED_TP ||
314 bp->port.supported[1] & SUPPORTED_TP)) {
315 DP(NETIF_MSG_LINK, "Unsupported port type\n");
316 return -EINVAL;
317 }
318 bp->link_params.multi_phy_config &=
319 ~PORT_HW_CFG_PHY_SELECTION_MASK;
320 if (bp->link_params.multi_phy_config &
321 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
322 bp->link_params.multi_phy_config |=
323 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
324 else
325 bp->link_params.multi_phy_config |=
326 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
327 break;
328 case PORT_FIBRE:
329 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
330 break; /* no port change */
331
332 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
333 bp->port.supported[1] & SUPPORTED_FIBRE)) {
334 DP(NETIF_MSG_LINK, "Unsupported port type\n");
335 return -EINVAL;
336 }
337 bp->link_params.multi_phy_config &=
338 ~PORT_HW_CFG_PHY_SELECTION_MASK;
339 if (bp->link_params.multi_phy_config &
340 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
341 bp->link_params.multi_phy_config |=
342 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
343 else
344 bp->link_params.multi_phy_config |=
345 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
346 break;
347 default:
348 DP(NETIF_MSG_LINK, "Unsupported port type\n");
349 return -EINVAL;
350 }
351 /* Save new config in case command complete successuly */
352 new_multi_phy_config = bp->link_params.multi_phy_config;
353 /* Get the new cfg_idx */
354 cfg_idx = bnx2x_get_link_cfg_idx(bp);
355 /* Restore old config in case command failed */
356 bp->link_params.multi_phy_config = old_multi_phy_config;
357 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
358
de0c62db 359 if (cmd->autoneg == AUTONEG_ENABLE) {
a22f0788 360 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 361 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
362 return -EINVAL;
363 }
364
365 /* advertise the requested speed and duplex if supported */
a22f0788 366 cmd->advertising &= bp->port.supported[cfg_idx];
de0c62db 367
a22f0788
YR		 368 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
369 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
370 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
de0c62db
DK		 371 cmd->advertising);
372
373 } else { /* forced speed */
374 /* advertise the requested speed and duplex if supported */
a22f0788 375 switch (speed) {
de0c62db
DK		 376 case SPEED_10:
377 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 378 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 379 SUPPORTED_10baseT_Full)) {
380 DP(NETIF_MSG_LINK,
381 "10M full not supported\n");
382 return -EINVAL;
383 }
384
385 advertising = (ADVERTISED_10baseT_Full |
386 ADVERTISED_TP);
387 } else {
a22f0788 388 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 389 SUPPORTED_10baseT_Half)) {
390 DP(NETIF_MSG_LINK,
391 "10M half not supported\n");
392 return -EINVAL;
393 }
394
395 advertising = (ADVERTISED_10baseT_Half |
396 ADVERTISED_TP);
397 }
398 break;
399
400 case SPEED_100:
401 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 402 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 403 SUPPORTED_100baseT_Full)) {
404 DP(NETIF_MSG_LINK,
405 "100M full not supported\n");
406 return -EINVAL;
407 }
408
409 advertising = (ADVERTISED_100baseT_Full |
410 ADVERTISED_TP);
411 } else {
a22f0788 412 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 413 SUPPORTED_100baseT_Half)) {
414 DP(NETIF_MSG_LINK,
415 "100M half not supported\n");
416 return -EINVAL;
417 }
418
419 advertising = (ADVERTISED_100baseT_Half |
420 ADVERTISED_TP);
421 }
422 break;
423
424 case SPEED_1000:
425 if (cmd->duplex != DUPLEX_FULL) {
426 DP(NETIF_MSG_LINK, "1G half not supported\n");
427 return -EINVAL;
428 }
429
a22f0788
YR		 430 if (!(bp->port.supported[cfg_idx] &
431 SUPPORTED_1000baseT_Full)) {
de0c62db
DK		 432 DP(NETIF_MSG_LINK, "1G full not supported\n");
433 return -EINVAL;
434 }
435
436 advertising = (ADVERTISED_1000baseT_Full |
437 ADVERTISED_TP);
438 break;
439
440 case SPEED_2500:
441 if (cmd->duplex != DUPLEX_FULL) {
442 DP(NETIF_MSG_LINK,
443 "2.5G half not supported\n");
444 return -EINVAL;
445 }
446
a22f0788
YR		 447 if (!(bp->port.supported[cfg_idx]
448 & SUPPORTED_2500baseX_Full)) {
de0c62db
DK		 449 DP(NETIF_MSG_LINK,
450 "2.5G full not supported\n");
451 return -EINVAL;
452 }
453
454 advertising = (ADVERTISED_2500baseX_Full |
455 ADVERTISED_TP);
456 break;
457
458 case SPEED_10000:
459 if (cmd->duplex != DUPLEX_FULL) {
460 DP(NETIF_MSG_LINK, "10G half not supported\n");
461 return -EINVAL;
462 }
463
a22f0788
YR		 464 if (!(bp->port.supported[cfg_idx]
465 & SUPPORTED_10000baseT_Full)) {
de0c62db
DK		 466 DP(NETIF_MSG_LINK, "10G full not supported\n");
467 return -EINVAL;
468 }
469
470 advertising = (ADVERTISED_10000baseT_Full |
471 ADVERTISED_FIBRE);
472 break;
473
474 default:
b3337e4c 475 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
de0c62db
DK		 476 return -EINVAL;
477 }
478
a22f0788
YR		 479 bp->link_params.req_line_speed[cfg_idx] = speed;
480 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
481 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 482 }
483
484 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
485 DP_LEVEL " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 486 bp->link_params.req_line_speed[cfg_idx],
487 bp->link_params.req_duplex[cfg_idx],
488 bp->port.advertising[cfg_idx]);
de0c62db 489
a22f0788
YR		 490 /* Set new config */
491 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 492 if (netif_running(dev)) {
493 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
494 bnx2x_link_set(bp);
495 }
496
497 return 0;
498}
499
500#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
501#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 502#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
de0c62db
DK		 503
504static int bnx2x_get_regs_len(struct net_device *dev)
505{
506 struct bnx2x *bp = netdev_priv(dev);
507 int regdump_len = 0;
4a33bc03 508 int i, j, k;
de0c62db
DK		 509
510 if (CHIP_IS_E1(bp)) {
511 for (i = 0; i < REGS_COUNT; i++)
512 if (IS_E1_ONLINE(reg_addrs[i].info))
513 regdump_len += reg_addrs[i].size;
514
515 for (i = 0; i < WREGS_COUNT_E1; i++)
516 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
517 regdump_len += wreg_addrs_e1[i].size *
518 (1 + wreg_addrs_e1[i].read_regs_count);
519
f2e0899f 520 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 521 for (i = 0; i < REGS_COUNT; i++)
522 if (IS_E1H_ONLINE(reg_addrs[i].info))
523 regdump_len += reg_addrs[i].size;
524
525 for (i = 0; i < WREGS_COUNT_E1H; i++)
526 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
527 regdump_len += wreg_addrs_e1h[i].size *
528 (1 + wreg_addrs_e1h[i].read_regs_count);
619c5cb6 529 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 530 for (i = 0; i < REGS_COUNT; i++)
531 if (IS_E2_ONLINE(reg_addrs[i].info))
532 regdump_len += reg_addrs[i].size;
533
534 for (i = 0; i < WREGS_COUNT_E2; i++)
535 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
536 regdump_len += wreg_addrs_e2[i].size *
537 (1 + wreg_addrs_e2[i].read_regs_count);
4a33bc03
VZ		 538
539 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
540 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
541 for (k = 0; k < PAGE_READ_REGS_E2; k++)
542 if (IS_E2_ONLINE(page_read_regs_e2[k].
543 info))
544 regdump_len +=
545 page_read_regs_e2[k].size;
546 }
de0c62db
DK		 547 }
548 regdump_len *= 4;
549 regdump_len += sizeof(struct dump_hdr);
550
551 return regdump_len;
552}
553
f2e0899f
DK		 554static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
555{
556 u32 i, j, k, n;
557
558 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
559 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
560 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
561 for (k = 0; k < PAGE_READ_REGS_E2; k++)
562 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
563 for (n = 0; n <
564 page_read_regs_e2[k].size; n++)
565 *p++ = REG_RD(bp,
566 page_read_regs_e2[k].addr + n*4);
567 }
568 }
569}
570
de0c62db
DK		 571static void bnx2x_get_regs(struct net_device *dev,
572 struct ethtool_regs *regs, void *_p)
573{
574 u32 *p = _p, i, j;
575 struct bnx2x *bp = netdev_priv(dev);
576 struct dump_hdr dump_hdr = {0};
577
578 regs->version = 0;
579 memset(p, 0, regs->len);
580
581 if (!netif_running(bp->dev))
582 return;
583
4a33bc03
VZ		 584 /* Disable parity attentions as long as following dump may
585 * cause false alarms by reading never written registers. We
586 * will re-enable parity attentions right after the dump.
587 */
588 bnx2x_disable_blocks_parity(bp);
589
de0c62db
DK		 590 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
591 dump_hdr.dump_sign = dump_sign_all;
592 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
593 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
594 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
595 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 596
597 if (CHIP_IS_E1(bp))
598 dump_hdr.info = RI_E1_ONLINE;
599 else if (CHIP_IS_E1H(bp))
600 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 601 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 602 dump_hdr.info = RI_E2_ONLINE |
603 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 604
605 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
606 p += dump_hdr.hdr_size + 1;
607
608 if (CHIP_IS_E1(bp)) {
609 for (i = 0; i < REGS_COUNT; i++)
610 if (IS_E1_ONLINE(reg_addrs[i].info))
611 for (j = 0; j < reg_addrs[i].size; j++)
612 *p++ = REG_RD(bp,
613 reg_addrs[i].addr + j*4);
614
f2e0899f 615 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 616 for (i = 0; i < REGS_COUNT; i++)
617 if (IS_E1H_ONLINE(reg_addrs[i].info))
618 for (j = 0; j < reg_addrs[i].size; j++)
619 *p++ = REG_RD(bp,
620 reg_addrs[i].addr + j*4);
f2e0899f 621
619c5cb6 622 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 623 for (i = 0; i < REGS_COUNT; i++)
624 if (IS_E2_ONLINE(reg_addrs[i].info))
625 for (j = 0; j < reg_addrs[i].size; j++)
626 *p++ = REG_RD(bp,
627 reg_addrs[i].addr + j*4);
628
619c5cb6
VZ		 629 if (CHIP_IS_E2(bp))
630 bnx2x_read_pages_regs_e2(bp, p);
631 else
632 /* E3 paged registers read is unimplemented yet */
633 WARN_ON(1);
de0c62db 634 }
4a33bc03
VZ		 635 /* Re-enable parity attentions */
636 bnx2x_clear_blocks_parity(bp);
c9ee9206 637 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 638}
639
de0c62db
DK		 640static void bnx2x_get_drvinfo(struct net_device *dev,
641 struct ethtool_drvinfo *info)
642{
643 struct bnx2x *bp = netdev_priv(dev);
644 u8 phy_fw_ver[PHY_FW_VER_LEN];
645
646 strcpy(info->driver, DRV_MODULE_NAME);
647 strcpy(info->version, DRV_MODULE_VERSION);
648
649 phy_fw_ver[0] = '\0';
650 if (bp->port.pmf) {
651 bnx2x_acquire_phy_lock(bp);
652 bnx2x_get_ext_phy_fw_version(&bp->link_params,
653 (bp->state != BNX2X_STATE_CLOSED),
654 phy_fw_ver, PHY_FW_VER_LEN);
655 bnx2x_release_phy_lock(bp);
656 }
657
658 strncpy(info->fw_version, bp->fw_ver, 32);
659 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
660 "bc %d.%d.%d%s%s",
661 (bp->common.bc_ver & 0xff0000) >> 16,
662 (bp->common.bc_ver & 0xff00) >> 8,
663 (bp->common.bc_ver & 0xff),
664 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
665 strcpy(info->bus_info, pci_name(bp->pdev));
666 info->n_stats = BNX2X_NUM_STATS;
667 info->testinfo_len = BNX2X_NUM_TESTS;
668 info->eedump_len = bp->common.flash_size;
669 info->regdump_len = bnx2x_get_regs_len(dev);
670}
671
672static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
673{
674 struct bnx2x *bp = netdev_priv(dev);
675
676 if (bp->flags & NO_WOL_FLAG) {
677 wol->supported = 0;
678 wol->wolopts = 0;
679 } else {
680 wol->supported = WAKE_MAGIC;
681 if (bp->wol)
682 wol->wolopts = WAKE_MAGIC;
683 else
684 wol->wolopts = 0;
685 }
686 memset(&wol->sopass, 0, sizeof(wol->sopass));
687}
688
689static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
690{
691 struct bnx2x *bp = netdev_priv(dev);
692
693 if (wol->wolopts & ~WAKE_MAGIC)
694 return -EINVAL;
695
696 if (wol->wolopts & WAKE_MAGIC) {
697 if (bp->flags & NO_WOL_FLAG)
698 return -EINVAL;
699
700 bp->wol = 1;
701 } else
702 bp->wol = 0;
703
704 return 0;
705}
706
707static u32 bnx2x_get_msglevel(struct net_device *dev)
708{
709 struct bnx2x *bp = netdev_priv(dev);
710
711 return bp->msg_enable;
712}
713
714static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
715{
716 struct bnx2x *bp = netdev_priv(dev);
717
7a25cc73
DK		 718 if (capable(CAP_NET_ADMIN)) {
719 /* dump MCP trace */
720 if (level & BNX2X_MSG_MCP)
721 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 722 bp->msg_enable = level;
7a25cc73 723 }
de0c62db
DK		 724}
725
726static int bnx2x_nway_reset(struct net_device *dev)
727{
728 struct bnx2x *bp = netdev_priv(dev);
729
730 if (!bp->port.pmf)
731 return 0;
732
733 if (netif_running(dev)) {
734 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
735 bnx2x_link_set(bp);
736 }
737
738 return 0;
739}
740
741static u32 bnx2x_get_link(struct net_device *dev)
742{
743 struct bnx2x *bp = netdev_priv(dev);
744
f2e0899f 745 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 746 return 0;
747
748 return bp->link_vars.link_up;
749}
750
751static int bnx2x_get_eeprom_len(struct net_device *dev)
752{
753 struct bnx2x *bp = netdev_priv(dev);
754
755 return bp->common.flash_size;
756}
757
758static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
759{
760 int port = BP_PORT(bp);
761 int count, i;
762 u32 val = 0;
763
764 /* adjust timeout for emulation/FPGA */
754a2f52 765 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 766 if (CHIP_REV_IS_SLOW(bp))
767 count *= 100;
768
769 /* request access to nvram interface */
770 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
771 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
772
773 for (i = 0; i < count*10; i++) {
774 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
775 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
776 break;
777
778 udelay(5);
779 }
780
781 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
782 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
783 return -EBUSY;
784 }
785
786 return 0;
787}
788
789static int bnx2x_release_nvram_lock(struct bnx2x *bp)
790{
791 int port = BP_PORT(bp);
792 int count, i;
793 u32 val = 0;
794
795 /* adjust timeout for emulation/FPGA */
754a2f52 796 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 797 if (CHIP_REV_IS_SLOW(bp))
798 count *= 100;
799
800 /* relinquish nvram interface */
801 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
802 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
803
804 for (i = 0; i < count*10; i++) {
805 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
806 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
807 break;
808
809 udelay(5);
810 }
811
812 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
813 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
814 return -EBUSY;
815 }
816
817 return 0;
818}
819
820static void bnx2x_enable_nvram_access(struct bnx2x *bp)
821{
822 u32 val;
823
824 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
825
826 /* enable both bits, even on read */
827 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
828 (val | MCPR_NVM_ACCESS_ENABLE_EN |
829 MCPR_NVM_ACCESS_ENABLE_WR_EN));
830}
831
832static void bnx2x_disable_nvram_access(struct bnx2x *bp)
833{
834 u32 val;
835
836 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
837
838 /* disable both bits, even after read */
839 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
840 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
841 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
842}
843
844static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
845 u32 cmd_flags)
846{
847 int count, i, rc;
848 u32 val;
849
850 /* build the command word */
851 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
852
853 /* need to clear DONE bit separately */
854 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
855
856 /* address of the NVRAM to read from */
857 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
858 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
859
860 /* issue a read command */
861 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
862
863 /* adjust timeout for emulation/FPGA */
754a2f52 864 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 865 if (CHIP_REV_IS_SLOW(bp))
866 count *= 100;
867
868 /* wait for completion */
869 *ret_val = 0;
870 rc = -EBUSY;
871 for (i = 0; i < count; i++) {
872 udelay(5);
873 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
874
875 if (val & MCPR_NVM_COMMAND_DONE) {
876 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
877 /* we read nvram data in cpu order
878 * but ethtool sees it as an array of bytes
879 * converting to big-endian will do the work */
880 *ret_val = cpu_to_be32(val);
881 rc = 0;
882 break;
883 }
884 }
885
886 return rc;
887}
888
889static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
890 int buf_size)
891{
892 int rc;
893 u32 cmd_flags;
894 __be32 val;
895
896 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
897 DP(BNX2X_MSG_NVM,
898 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
899 offset, buf_size);
900 return -EINVAL;
901 }
902
903 if (offset + buf_size > bp->common.flash_size) {
904 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
905 " buf_size (0x%x) > flash_size (0x%x)\n",
906 offset, buf_size, bp->common.flash_size);
907 return -EINVAL;
908 }
909
910 /* request access to nvram interface */
911 rc = bnx2x_acquire_nvram_lock(bp);
912 if (rc)
913 return rc;
914
915 /* enable access to nvram interface */
916 bnx2x_enable_nvram_access(bp);
917
918 /* read the first word(s) */
919 cmd_flags = MCPR_NVM_COMMAND_FIRST;
920 while ((buf_size > sizeof(u32)) && (rc == 0)) {
921 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
922 memcpy(ret_buf, &val, 4);
923
924 /* advance to the next dword */
925 offset += sizeof(u32);
926 ret_buf += sizeof(u32);
927 buf_size -= sizeof(u32);
928 cmd_flags = 0;
929 }
930
931 if (rc == 0) {
932 cmd_flags |= MCPR_NVM_COMMAND_LAST;
933 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
934 memcpy(ret_buf, &val, 4);
935 }
936
937 /* disable access to nvram interface */
938 bnx2x_disable_nvram_access(bp);
939 bnx2x_release_nvram_lock(bp);
940
941 return rc;
942}
943
944static int bnx2x_get_eeprom(struct net_device *dev,
945 struct ethtool_eeprom *eeprom, u8 *eebuf)
946{
947 struct bnx2x *bp = netdev_priv(dev);
948 int rc;
949
950 if (!netif_running(dev))
951 return -EAGAIN;
952
953 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
954 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
955 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
956 eeprom->len, eeprom->len);
957
958 /* parameters already validated in ethtool_get_eeprom */
959
960 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
961
962 return rc;
963}
964
965static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
966 u32 cmd_flags)
967{
968 int count, i, rc;
969
970 /* build the command word */
971 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
972
973 /* need to clear DONE bit separately */
974 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
975
976 /* write the data */
977 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
978
979 /* address of the NVRAM to write to */
980 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
981 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
982
983 /* issue the write command */
984 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
985
986 /* adjust timeout for emulation/FPGA */
754a2f52 987 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 988 if (CHIP_REV_IS_SLOW(bp))
989 count *= 100;
990
991 /* wait for completion */
992 rc = -EBUSY;
993 for (i = 0; i < count; i++) {
994 udelay(5);
995 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
996 if (val & MCPR_NVM_COMMAND_DONE) {
997 rc = 0;
998 break;
999 }
1000 }
1001
1002 return rc;
1003}
1004
1005#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1006
1007static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1008 int buf_size)
1009{
1010 int rc;
1011 u32 cmd_flags;
1012 u32 align_offset;
1013 __be32 val;
1014
1015 if (offset + buf_size > bp->common.flash_size) {
1016 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1017 " buf_size (0x%x) > flash_size (0x%x)\n",
1018 offset, buf_size, bp->common.flash_size);
1019 return -EINVAL;
1020 }
1021
1022 /* request access to nvram interface */
1023 rc = bnx2x_acquire_nvram_lock(bp);
1024 if (rc)
1025 return rc;
1026
1027 /* enable access to nvram interface */
1028 bnx2x_enable_nvram_access(bp);
1029
1030 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1031 align_offset = (offset & ~0x03);
1032 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1033
1034 if (rc == 0) {
1035 val &= ~(0xff << BYTE_OFFSET(offset));
1036 val |= (*data_buf << BYTE_OFFSET(offset));
1037
1038 /* nvram data is returned as an array of bytes
1039 * convert it back to cpu order */
1040 val = be32_to_cpu(val);
1041
1042 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1043 cmd_flags);
1044 }
1045
1046 /* disable access to nvram interface */
1047 bnx2x_disable_nvram_access(bp);
1048 bnx2x_release_nvram_lock(bp);
1049
1050 return rc;
1051}
1052
1053static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1054 int buf_size)
1055{
1056 int rc;
1057 u32 cmd_flags;
1058 u32 val;
1059 u32 written_so_far;
1060
1061 if (buf_size == 1) /* ethtool */
1062 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1063
1064 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1065 DP(BNX2X_MSG_NVM,
1066 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1067 offset, buf_size);
1068 return -EINVAL;
1069 }
1070
1071 if (offset + buf_size > bp->common.flash_size) {
1072 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1073 " buf_size (0x%x) > flash_size (0x%x)\n",
1074 offset, buf_size, bp->common.flash_size);
1075 return -EINVAL;
1076 }
1077
1078 /* request access to nvram interface */
1079 rc = bnx2x_acquire_nvram_lock(bp);
1080 if (rc)
1081 return rc;
1082
1083 /* enable access to nvram interface */
1084 bnx2x_enable_nvram_access(bp);
1085
1086 written_so_far = 0;
1087 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1088 while ((written_so_far < buf_size) && (rc == 0)) {
1089 if (written_so_far == (buf_size - sizeof(u32)))
1090 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1091 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1092 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1093 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1094 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1095
1096 memcpy(&val, data_buf, 4);
1097
1098 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1099
1100 /* advance to the next dword */
1101 offset += sizeof(u32);
1102 data_buf += sizeof(u32);
1103 written_so_far += sizeof(u32);
1104 cmd_flags = 0;
1105 }
1106
1107 /* disable access to nvram interface */
1108 bnx2x_disable_nvram_access(bp);
1109 bnx2x_release_nvram_lock(bp);
1110
1111 return rc;
1112}
1113
1114static int bnx2x_set_eeprom(struct net_device *dev,
1115 struct ethtool_eeprom *eeprom, u8 *eebuf)
1116{
1117 struct bnx2x *bp = netdev_priv(dev);
1118 int port = BP_PORT(bp);
1119 int rc = 0;
e10bc84d 1120 u32 ext_phy_config;
de0c62db
DK		 1121 if (!netif_running(dev))
1122 return -EAGAIN;
1123
1124 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1125 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1126 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1127 eeprom->len, eeprom->len);
1128
1129 /* parameters already validated in ethtool_set_eeprom */
1130
1131 /* PHY eeprom can be accessed only by the PMF */
1132 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1133 !bp->port.pmf)
1134 return -EINVAL;
1135
e10bc84d
YR		 1136 ext_phy_config =
1137 SHMEM_RD(bp,
1138 dev_info.port_hw_config[port].external_phy_config);
1139
de0c62db
DK		 1140 if (eeprom->magic == 0x50485950) {
1141 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1142 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1143
1144 bnx2x_acquire_phy_lock(bp);
1145 rc |= bnx2x_link_reset(&bp->link_params,
1146 &bp->link_vars, 0);
e10bc84d 1147 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1148 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1149 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1150 MISC_REGISTERS_GPIO_HIGH, port);
1151 bnx2x_release_phy_lock(bp);
1152 bnx2x_link_report(bp);
1153
1154 } else if (eeprom->magic == 0x50485952) {
1155 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1156 if (bp->state == BNX2X_STATE_OPEN) {
1157 bnx2x_acquire_phy_lock(bp);
1158 rc |= bnx2x_link_reset(&bp->link_params,
1159 &bp->link_vars, 1);
1160
1161 rc |= bnx2x_phy_init(&bp->link_params,
1162 &bp->link_vars);
1163 bnx2x_release_phy_lock(bp);
1164 bnx2x_calc_fc_adv(bp);
1165 }
1166 } else if (eeprom->magic == 0x53985943) {
1167 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1168 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1169 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1170
1171 /* DSP Remove Download Mode */
1172 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1173 MISC_REGISTERS_GPIO_LOW, port);
1174
1175 bnx2x_acquire_phy_lock(bp);
1176
e10bc84d
YR		 1177 bnx2x_sfx7101_sp_sw_reset(bp,
1178 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1179
1180 /* wait 0.5 sec to allow it to run */
1181 msleep(500);
1182 bnx2x_ext_phy_hw_reset(bp, port);
1183 msleep(500);
1184 bnx2x_release_phy_lock(bp);
1185 }
1186 } else
1187 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1188
1189 return rc;
1190}
f85582f8 1191
de0c62db
DK		 1192static int bnx2x_get_coalesce(struct net_device *dev,
1193 struct ethtool_coalesce *coal)
1194{
1195 struct bnx2x *bp = netdev_priv(dev);
1196
1197 memset(coal, 0, sizeof(struct ethtool_coalesce));
1198
1199 coal->rx_coalesce_usecs = bp->rx_ticks;
1200 coal->tx_coalesce_usecs = bp->tx_ticks;
1201
1202 return 0;
1203}
1204
1205static int bnx2x_set_coalesce(struct net_device *dev,
1206 struct ethtool_coalesce *coal)
1207{
1208 struct bnx2x *bp = netdev_priv(dev);
1209
1210 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1211 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1212 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1213
1214 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1215 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1216 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1217
1218 if (netif_running(dev))
1219 bnx2x_update_coalesce(bp);
1220
1221 return 0;
1222}
1223
1224static void bnx2x_get_ringparam(struct net_device *dev,
1225 struct ethtool_ringparam *ering)
1226{
1227 struct bnx2x *bp = netdev_priv(dev);
1228
1229 ering->rx_max_pending = MAX_RX_AVAIL;
1230 ering->rx_mini_max_pending = 0;
1231 ering->rx_jumbo_max_pending = 0;
1232
25141580
DK		 1233 if (bp->rx_ring_size)
1234 ering->rx_pending = bp->rx_ring_size;
1235 else
1236 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1237 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1238 else
1239 ering->rx_pending = MAX_RX_AVAIL;
1240
de0c62db
DK		 1241 ering->rx_mini_pending = 0;
1242 ering->rx_jumbo_pending = 0;
1243
1244 ering->tx_max_pending = MAX_TX_AVAIL;
1245 ering->tx_pending = bp->tx_ring_size;
1246}
1247
1248static int bnx2x_set_ringparam(struct net_device *dev,
1249 struct ethtool_ringparam *ering)
1250{
1251 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1252
1253 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1254 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1255 return -EAGAIN;
1256 }
1257
1258 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1259 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1260 MIN_RX_SIZE_TPA)) ||
de0c62db
DK		 1261 (ering->tx_pending > MAX_TX_AVAIL) ||
1262 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1263 return -EINVAL;
1264
1265 bp->rx_ring_size = ering->rx_pending;
1266 bp->tx_ring_size = ering->tx_pending;
1267
a9fccec7 1268 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1269}
1270
1271static void bnx2x_get_pauseparam(struct net_device *dev,
1272 struct ethtool_pauseparam *epause)
1273{
1274 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 1275 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1276 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1277 BNX2X_FLOW_CTRL_AUTO);
de0c62db
DK		 1278
1279 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1280 BNX2X_FLOW_CTRL_RX);
1281 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1282 BNX2X_FLOW_CTRL_TX);
1283
1284 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1285 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1286 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1287}
1288
1289static int bnx2x_set_pauseparam(struct net_device *dev,
1290 struct ethtool_pauseparam *epause)
1291{
1292 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1293 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1294 if (IS_MF(bp))
de0c62db
DK		 1295 return 0;
1296
1297 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1298 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1299 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1300
a22f0788 1301 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1302
1303 if (epause->rx_pause)
a22f0788 1304 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1305
1306 if (epause->tx_pause)
a22f0788 1307 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1308
a22f0788
YR		 1309 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1310 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1311
1312 if (epause->autoneg) {
a22f0788 1313 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 1314 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1315 return -EINVAL;
1316 }
1317
a22f0788
YR		 1318 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1319 bp->link_params.req_flow_ctrl[cfg_idx] =
1320 BNX2X_FLOW_CTRL_AUTO;
1321 }
de0c62db
DK		 1322 }
1323
1324 DP(NETIF_MSG_LINK,
a22f0788 1325 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1326
1327 if (netif_running(dev)) {
1328 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1329 bnx2x_link_set(bp);
1330 }
1331
1332 return 0;
1333}
1334
de0c62db
DK		 1335static const struct {
1336 char string[ETH_GSTRING_LEN];
1337} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1338 { "register_test (offline)" },
1339 { "memory_test (offline)" },
1340 { "loopback_test (offline)" },
1341 { "nvram_test (online)" },
1342 { "interrupt_test (online)" },
1343 { "link_test (online)" },
1344 { "idle check (online)" }
1345};
1346
619c5cb6
VZ		 1347enum {
1348 BNX2X_CHIP_E1_OFST = 0,
1349 BNX2X_CHIP_E1H_OFST,
1350 BNX2X_CHIP_E2_OFST,
1351 BNX2X_CHIP_E3_OFST,
1352 BNX2X_CHIP_E3B0_OFST,
1353 BNX2X_CHIP_MAX_OFST
1354};
1355
1356#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1357#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1358#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1359#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1360#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1361
1362#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1363#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1364
de0c62db
DK		 1365static int bnx2x_test_registers(struct bnx2x *bp)
1366{
1367 int idx, i, rc = -ENODEV;
619c5cb6 1368 u32 wr_val = 0, hw;
de0c62db
DK		 1369 int port = BP_PORT(bp);
1370 static const struct {
619c5cb6 1371 u32 hw;
de0c62db
DK		 1372 u32 offset0;
1373 u32 offset1;
1374 u32 mask;
1375 } reg_tbl[] = {
619c5cb6
VZ		 1376/* 0 */ { BNX2X_CHIP_MASK_ALL,
1377 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1378 { BNX2X_CHIP_MASK_ALL,
1379 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1380 { BNX2X_CHIP_MASK_E1X,
1381 HC_REG_AGG_INT_0, 4, 0x000003ff },
1382 { BNX2X_CHIP_MASK_ALL,
1383 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1384 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1385 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1386 { BNX2X_CHIP_MASK_E3B0,
1387 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1388 { BNX2X_CHIP_MASK_ALL,
1389 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1390 { BNX2X_CHIP_MASK_ALL,
1391 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1392 { BNX2X_CHIP_MASK_ALL,
1393 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1394 { BNX2X_CHIP_MASK_ALL,
1395 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1396/* 10 */ { BNX2X_CHIP_MASK_ALL,
1397 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1398 { BNX2X_CHIP_MASK_ALL,
1399 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1400 { BNX2X_CHIP_MASK_ALL,
1401 QM_REG_CONNNUM_0, 4, 0x000fffff },
1402 { BNX2X_CHIP_MASK_ALL,
1403 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1404 { BNX2X_CHIP_MASK_ALL,
1405 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1406 { BNX2X_CHIP_MASK_ALL,
1407 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1408 { BNX2X_CHIP_MASK_ALL,
1409 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1410 { BNX2X_CHIP_MASK_ALL,
1411 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1412 { BNX2X_CHIP_MASK_ALL,
1413 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1414 { BNX2X_CHIP_MASK_ALL,
1415 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1416/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1417 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1418 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1419 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1420 { BNX2X_CHIP_MASK_ALL,
1421 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1422 { BNX2X_CHIP_MASK_ALL,
1423 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1424 { BNX2X_CHIP_MASK_ALL,
1425 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1426 { BNX2X_CHIP_MASK_ALL,
1427 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1428 { BNX2X_CHIP_MASK_ALL,
1429 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1430 { BNX2X_CHIP_MASK_ALL,
1431 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1432 { BNX2X_CHIP_MASK_ALL,
1433 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1434 { BNX2X_CHIP_MASK_ALL,
1435 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1436/* 30 */ { BNX2X_CHIP_MASK_ALL,
1437 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1438 { BNX2X_CHIP_MASK_ALL,
1439 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1440 { BNX2X_CHIP_MASK_ALL,
1441 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1442 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1443 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1444 { BNX2X_CHIP_MASK_ALL,
1445 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1446 { BNX2X_CHIP_MASK_ALL,
1447 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1448 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1449 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1450 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1451 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1452
1453 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1454 };
1455
1456 if (!netif_running(bp->dev))
1457 return rc;
1458
619c5cb6
VZ		 1459 if (CHIP_IS_E1(bp))
1460 hw = BNX2X_CHIP_MASK_E1;
1461 else if (CHIP_IS_E1H(bp))
1462 hw = BNX2X_CHIP_MASK_E1H;
1463 else if (CHIP_IS_E2(bp))
1464 hw = BNX2X_CHIP_MASK_E2;
1465 else if (CHIP_IS_E3B0(bp))
1466 hw = BNX2X_CHIP_MASK_E3B0;
1467 else /* e3 A0 */
1468 hw = BNX2X_CHIP_MASK_E3;
1469
de0c62db
DK		 1470 /* Repeat the test twice:
1471 First by writing 0x00000000, second by writing 0xffffffff */
1472 for (idx = 0; idx < 2; idx++) {
1473
1474 switch (idx) {
1475 case 0:
1476 wr_val = 0;
1477 break;
1478 case 1:
1479 wr_val = 0xffffffff;
1480 break;
1481 }
1482
1483 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1484 u32 offset, mask, save_val, val;
619c5cb6 1485 if (!(hw & reg_tbl[i].hw))
f2e0899f 1486 continue;
de0c62db
DK		 1487
1488 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1489 mask = reg_tbl[i].mask;
1490
1491 save_val = REG_RD(bp, offset);
1492
ec6ba945 1493 REG_WR(bp, offset, wr_val & mask);
f85582f8 1494
de0c62db
DK		 1495 val = REG_RD(bp, offset);
1496
1497 /* Restore the original register's value */
1498 REG_WR(bp, offset, save_val);
1499
1500 /* verify value is as expected */
1501 if ((val & mask) != (wr_val & mask)) {
619c5cb6 1502 DP(NETIF_MSG_HW,
de0c62db
DK		 1503 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1504 offset, val, wr_val, mask);
1505 goto test_reg_exit;
1506 }
1507 }
1508 }
1509
1510 rc = 0;
1511
1512test_reg_exit:
1513 return rc;
1514}
1515
1516static int bnx2x_test_memory(struct bnx2x *bp)
1517{
1518 int i, j, rc = -ENODEV;
619c5cb6 1519 u32 val, index;
de0c62db
DK		 1520 static const struct {
1521 u32 offset;
1522 int size;
1523 } mem_tbl[] = {
1524 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1525 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1526 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1527 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1528 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1529 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1530 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1531
1532 { 0xffffffff, 0 }
1533 };
619c5cb6 1534
de0c62db
DK		 1535 static const struct {
1536 char *name;
1537 u32 offset;
619c5cb6 1538 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1539 } prty_tbl[] = {
619c5cb6
VZ		 1540 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1541 {0x3ffc0, 0, 0, 0} },
1542 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1543 {0x2, 0x2, 0, 0} },
1544 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1545 {0, 0, 0, 0} },
1546 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1547 {0x3ffc0, 0, 0, 0} },
1548 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1549 {0x3ffc0, 0, 0, 0} },
1550 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1551 {0x3ffc1, 0, 0, 0} },
1552
1553 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1554 };
1555
1556 if (!netif_running(bp->dev))
1557 return rc;
1558
619c5cb6
VZ		 1559 if (CHIP_IS_E1(bp))
1560 index = BNX2X_CHIP_E1_OFST;
1561 else if (CHIP_IS_E1H(bp))
1562 index = BNX2X_CHIP_E1H_OFST;
1563 else if (CHIP_IS_E2(bp))
1564 index = BNX2X_CHIP_E2_OFST;
1565 else /* e3 */
1566 index = BNX2X_CHIP_E3_OFST;
1567
f2e0899f
DK		 1568 /* pre-Check the parity status */
1569 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1570 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1571 if (val & ~(prty_tbl[i].hw_mask[index])) {
f2e0899f
DK		 1572 DP(NETIF_MSG_HW,
1573 "%s is 0x%x\n", prty_tbl[i].name, val);
1574 goto test_mem_exit;
1575 }
1576 }
1577
de0c62db
DK		 1578 /* Go through all the memories */
1579 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1580 for (j = 0; j < mem_tbl[i].size; j++)
1581 REG_RD(bp, mem_tbl[i].offset + j*4);
1582
1583 /* Check the parity status */
1584 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1585 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1586 if (val & ~(prty_tbl[i].hw_mask[index])) {
de0c62db
DK		 1587 DP(NETIF_MSG_HW,
1588 "%s is 0x%x\n", prty_tbl[i].name, val);
1589 goto test_mem_exit;
1590 }
1591 }
1592
1593 rc = 0;
1594
1595test_mem_exit:
1596 return rc;
1597}
1598
a22f0788 1599static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1600{
f2e0899f 1601 int cnt = 1400;
de0c62db 1602
619c5cb6 1603 if (link_up) {
a22f0788 1604 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 1605 msleep(20);
1606
1607 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1608 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1609 }
de0c62db
DK		 1610}
1611
619c5cb6 1612static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 1613{
1614 unsigned int pkt_size, num_pkts, i;
1615 struct sk_buff *skb;
1616 unsigned char *packet;
1617 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1618 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
6383c0b3 1619 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
de0c62db
DK		 1620 u16 tx_start_idx, tx_idx;
1621 u16 rx_start_idx, rx_idx;
619c5cb6 1622 u16 pkt_prod, bd_prod, rx_comp_cons;
de0c62db
DK		 1623 struct sw_tx_bd *tx_buf;
1624 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1625 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1626 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1627 dma_addr_t mapping;
1628 union eth_rx_cqe *cqe;
619c5cb6 1629 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 1630 struct sw_rx_bd *rx_buf;
1631 u16 len;
1632 int rc = -ENODEV;
1633
1634 /* check the loopback mode */
1635 switch (loopback_mode) {
1636 case BNX2X_PHY_LOOPBACK:
de6eae1f 1637 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1638 return -EINVAL;
1639 break;
1640 case BNX2X_MAC_LOOPBACK:
619c5cb6
VZ		 1641 bp->link_params.loopback_mode = CHIP_IS_E3(bp) ?
1642 LOOPBACK_XMAC : LOOPBACK_BMAC;
de0c62db
DK		 1643 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1644 break;
1645 default:
1646 return -EINVAL;
1647 }
1648
1649 /* prepare the loopback packet */
1650 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1651 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 1652 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db
DK		 1653 if (!skb) {
1654 rc = -ENOMEM;
1655 goto test_loopback_exit;
1656 }
1657 packet = skb_put(skb, pkt_size);
1658 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1659 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1660 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1661 for (i = ETH_HLEN; i < pkt_size; i++)
1662 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 1663 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1664 skb_headlen(skb), DMA_TO_DEVICE);
1665 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1666 rc = -ENOMEM;
1667 dev_kfree_skb(skb);
1668 BNX2X_ERR("Unable to map SKB\n");
1669 goto test_loopback_exit;
1670 }
de0c62db
DK		 1671
1672 /* send the loopback packet */
1673 num_pkts = 0;
6383c0b3 1674 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1675 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1676
6383c0b3
AE		 1677 pkt_prod = txdata->tx_pkt_prod++;
1678 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1679 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 1680 tx_buf->skb = skb;
1681 tx_buf->flags = 0;
1682
6383c0b3
AE		 1683 bd_prod = TX_BD(txdata->tx_bd_prod);
1684 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 1685 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1686 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1687 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1688 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1689 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1690 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1691 SET_FLAG(tx_start_bd->general_data,
1692 ETH_TX_START_BD_ETH_ADDR_TYPE,
1693 UNICAST_ADDRESS);
1694 SET_FLAG(tx_start_bd->general_data,
1695 ETH_TX_START_BD_HDR_NBDS,
1696 1);
de0c62db
DK		 1697
1698 /* turn on parsing and get a BD */
1699 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 1700
6383c0b3
AE		 1701 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1702 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1703
f2e0899f 1704 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1705 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1706
1707 wmb();
1708
6383c0b3 1709 txdata->tx_db.data.prod += 2;
de0c62db 1710 barrier();
6383c0b3 1711 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 1712
1713 mmiowb();
619c5cb6 1714 barrier();
de0c62db
DK		 1715
1716 num_pkts++;
6383c0b3 1717 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 1718
1719 udelay(100);
1720
6383c0b3 1721 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1722 if (tx_idx != tx_start_idx + num_pkts)
1723 goto test_loopback_exit;
1724
f2e0899f
DK		 1725 /* Unlike HC IGU won't generate an interrupt for status block
1726 * updates that have been performed while interrupts were
1727 * disabled.
1728 */
e1210d12
ED		 1729 if (bp->common.int_block == INT_BLOCK_IGU) {
1730 /* Disable local BHes to prevent a dead-lock situation between
1731 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1732 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1733 */
1734 local_bh_disable();
6383c0b3 1735 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 1736 local_bh_enable();
1737 }
f2e0899f 1738
de0c62db
DK		 1739 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1740 if (rx_idx != rx_start_idx + num_pkts)
1741 goto test_loopback_exit;
1742
619c5cb6
VZ		 1743 rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1744 cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
de0c62db 1745 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 1746 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1747 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 1748 goto test_loopback_rx_exit;
1749
1750 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1751 if (len != pkt_size)
1752 goto test_loopback_rx_exit;
1753
1754 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
619c5cb6
VZ		 1755 dma_sync_single_for_device(&bp->pdev->dev,
1756 dma_unmap_addr(rx_buf, mapping),
1757 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
de0c62db
DK		 1758 skb = rx_buf->skb;
1759 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1760 for (i = ETH_HLEN; i < pkt_size; i++)
1761 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1762 goto test_loopback_rx_exit;
1763
1764 rc = 0;
1765
1766test_loopback_rx_exit:
1767
1768 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1769 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1770 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1771 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1772
1773 /* Update producers */
1774 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1775 fp_rx->rx_sge_prod);
1776
1777test_loopback_exit:
1778 bp->link_params.loopback_mode = LOOPBACK_NONE;
1779
1780 return rc;
1781}
1782
619c5cb6 1783static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 1784{
1785 int rc = 0, res;
1786
1787 if (BP_NOMCP(bp))
1788 return rc;
1789
1790 if (!netif_running(bp->dev))
1791 return BNX2X_LOOPBACK_FAILED;
1792
1793 bnx2x_netif_stop(bp, 1);
1794 bnx2x_acquire_phy_lock(bp);
1795
619c5cb6 1796 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db
DK		 1797 if (res) {
1798 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1799 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1800 }
1801
619c5cb6 1802 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db
DK		 1803 if (res) {
1804 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1805 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1806 }
1807
1808 bnx2x_release_phy_lock(bp);
1809 bnx2x_netif_start(bp);
1810
1811 return rc;
1812}
1813
1814#define CRC32_RESIDUAL 0xdebb20e3
1815
1816static int bnx2x_test_nvram(struct bnx2x *bp)
1817{
1818 static const struct {
1819 int offset;
1820 int size;
1821 } nvram_tbl[] = {
1822 { 0, 0x14 }, /* bootstrap */
1823 { 0x14, 0xec }, /* dir */
1824 { 0x100, 0x350 }, /* manuf_info */
1825 { 0x450, 0xf0 }, /* feature_info */
1826 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 1827 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 1828 { 0, 0 }
1829 };
1830 __be32 buf[0x350 / 4];
1831 u8 *data = (u8 *)buf;
1832 int i, rc;
1833 u32 magic, crc;
1834
1835 if (BP_NOMCP(bp))
1836 return 0;
1837
1838 rc = bnx2x_nvram_read(bp, 0, data, 4);
1839 if (rc) {
1840 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1841 goto test_nvram_exit;
1842 }
1843
1844 magic = be32_to_cpu(buf[0]);
1845 if (magic != 0x669955aa) {
1846 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1847 rc = -ENODEV;
1848 goto test_nvram_exit;
1849 }
1850
1851 for (i = 0; nvram_tbl[i].size; i++) {
1852
1853 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1854 nvram_tbl[i].size);
1855 if (rc) {
1856 DP(NETIF_MSG_PROBE,
1857 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1858 goto test_nvram_exit;
1859 }
1860
1861 crc = ether_crc_le(nvram_tbl[i].size, data);
1862 if (crc != CRC32_RESIDUAL) {
1863 DP(NETIF_MSG_PROBE,
1864 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1865 rc = -ENODEV;
1866 goto test_nvram_exit;
1867 }
1868 }
1869
1870test_nvram_exit:
1871 return rc;
1872}
1873
619c5cb6 1874/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 1875static int bnx2x_test_intr(struct bnx2x *bp)
1876{
619c5cb6 1877 struct bnx2x_queue_state_params params = {0};
de0c62db
DK		 1878
1879 if (!netif_running(bp->dev))
1880 return -ENODEV;
1881
619c5cb6
VZ		 1882 params.q_obj = &bp->fp->q_obj;
1883 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 1884
619c5cb6
VZ		 1885 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1886
1887 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 1888}
1889
1890static void bnx2x_self_test(struct net_device *dev,
1891 struct ethtool_test *etest, u64 *buf)
1892{
1893 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1894 u8 is_serdes;
de0c62db
DK		 1895 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1896 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1897 etest->flags |= ETH_TEST_FL_FAILED;
1898 return;
1899 }
1900
1901 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1902
1903 if (!netif_running(dev))
1904 return;
1905
1906 /* offline tests are not supported in MF mode */
fb3bff17 1907 if (IS_MF(bp))
de0c62db 1908 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 1909 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 1910
1911 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1912 int port = BP_PORT(bp);
1913 u32 val;
1914 u8 link_up;
1915
1916 /* save current value of input enable for TX port IF */
1917 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1918 /* disable input for TX port IF */
1919 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1920
a22f0788
YR		 1921 link_up = bp->link_vars.link_up;
1922
de0c62db
DK		 1923 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1924 bnx2x_nic_load(bp, LOAD_DIAG);
1925 /* wait until link state is restored */
619c5cb6 1926 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 1927
1928 if (bnx2x_test_registers(bp) != 0) {
1929 buf[0] = 1;
1930 etest->flags |= ETH_TEST_FL_FAILED;
1931 }
1932 if (bnx2x_test_memory(bp) != 0) {
1933 buf[1] = 1;
1934 etest->flags |= ETH_TEST_FL_FAILED;
1935 }
f85582f8 1936
619c5cb6 1937 buf[2] = bnx2x_test_loopback(bp);
de0c62db
DK		 1938 if (buf[2] != 0)
1939 etest->flags |= ETH_TEST_FL_FAILED;
1940
1941 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1942
1943 /* restore input for TX port IF */
1944 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1945
1946 bnx2x_nic_load(bp, LOAD_NORMAL);
1947 /* wait until link state is restored */
a22f0788 1948 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1949 }
1950 if (bnx2x_test_nvram(bp) != 0) {
1951 buf[3] = 1;
1952 etest->flags |= ETH_TEST_FL_FAILED;
1953 }
1954 if (bnx2x_test_intr(bp) != 0) {
1955 buf[4] = 1;
1956 etest->flags |= ETH_TEST_FL_FAILED;
1957 }
633ac363
DK		 1958
1959 if (bnx2x_link_test(bp, is_serdes) != 0) {
1960 buf[5] = 1;
1961 etest->flags |= ETH_TEST_FL_FAILED;
1962 }
de0c62db
DK		 1963
1964#ifdef BNX2X_EXTRA_DEBUG
1965 bnx2x_panic_dump(bp);
1966#endif
1967}
1968
de0c62db
DK		 1969#define IS_PORT_STAT(i) \
1970 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1971#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 1972#define IS_MF_MODE_STAT(bp) \
1973 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 1974
619c5cb6
VZ		 1975/* ethtool statistics are displayed for all regular ethernet queues and the
1976 * fcoe L2 queue if not disabled
1977 */
1978static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
1979{
1980 return BNX2X_NUM_ETH_QUEUES(bp);
1981}
1982
de0c62db
DK		 1983static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1984{
1985 struct bnx2x *bp = netdev_priv(dev);
1986 int i, num_stats;
1987
1988 switch (stringset) {
1989 case ETH_SS_STATS:
1990 if (is_multi(bp)) {
619c5cb6 1991 num_stats = bnx2x_num_stat_queues(bp) *
ec6ba945 1992 BNX2X_NUM_Q_STATS;
fb3bff17 1993 if (!IS_MF_MODE_STAT(bp))
de0c62db
DK		 1994 num_stats += BNX2X_NUM_STATS;
1995 } else {
fb3bff17 1996 if (IS_MF_MODE_STAT(bp)) {
de0c62db
DK		 1997 num_stats = 0;
1998 for (i = 0; i < BNX2X_NUM_STATS; i++)
1999 if (IS_FUNC_STAT(i))
2000 num_stats++;
2001 } else
2002 num_stats = BNX2X_NUM_STATS;
2003 }
2004 return num_stats;
2005
2006 case ETH_SS_TEST:
2007 return BNX2X_NUM_TESTS;
2008
2009 default:
2010 return -EINVAL;
2011 }
2012}
2013
2014static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2015{
2016 struct bnx2x *bp = netdev_priv(dev);
2017 int i, j, k;
ec6ba945 2018 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2019
2020 switch (stringset) {
2021 case ETH_SS_STATS:
2022 if (is_multi(bp)) {
2023 k = 0;
619c5cb6 2024 for_each_eth_queue(bp, i) {
ec6ba945 2025 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2026 sprintf(queue_name, "%d", i);
de0c62db 2027 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2028 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2029 ETH_GSTRING_LEN,
2030 bnx2x_q_stats_arr[j].string,
2031 queue_name);
de0c62db
DK		 2032 k += BNX2X_NUM_Q_STATS;
2033 }
fb3bff17 2034 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 2035 break;
2036 for (j = 0; j < BNX2X_NUM_STATS; j++)
2037 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2038 bnx2x_stats_arr[j].string);
2039 } else {
2040 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2041 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2042 continue;
2043 strcpy(buf + j*ETH_GSTRING_LEN,
2044 bnx2x_stats_arr[i].string);
2045 j++;
2046 }
2047 }
2048 break;
2049
2050 case ETH_SS_TEST:
2051 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2052 break;
2053 }
2054}
2055
2056static void bnx2x_get_ethtool_stats(struct net_device *dev,
2057 struct ethtool_stats *stats, u64 *buf)
2058{
2059 struct bnx2x *bp = netdev_priv(dev);
2060 u32 *hw_stats, *offset;
2061 int i, j, k;
2062
2063 if (is_multi(bp)) {
2064 k = 0;
619c5cb6 2065 for_each_eth_queue(bp, i) {
de0c62db
DK		 2066 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2067 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2068 if (bnx2x_q_stats_arr[j].size == 0) {
2069 /* skip this counter */
2070 buf[k + j] = 0;
2071 continue;
2072 }
2073 offset = (hw_stats +
2074 bnx2x_q_stats_arr[j].offset);
2075 if (bnx2x_q_stats_arr[j].size == 4) {
2076 /* 4-byte counter */
2077 buf[k + j] = (u64) *offset;
2078 continue;
2079 }
2080 /* 8-byte counter */
2081 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2082 }
2083 k += BNX2X_NUM_Q_STATS;
2084 }
fb3bff17 2085 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 2086 return;
2087 hw_stats = (u32 *)&bp->eth_stats;
2088 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2089 if (bnx2x_stats_arr[j].size == 0) {
2090 /* skip this counter */
2091 buf[k + j] = 0;
2092 continue;
2093 }
2094 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2095 if (bnx2x_stats_arr[j].size == 4) {
2096 /* 4-byte counter */
2097 buf[k + j] = (u64) *offset;
2098 continue;
2099 }
2100 /* 8-byte counter */
2101 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2102 }
2103 } else {
2104 hw_stats = (u32 *)&bp->eth_stats;
2105 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2106 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2107 continue;
2108 if (bnx2x_stats_arr[i].size == 0) {
2109 /* skip this counter */
2110 buf[j] = 0;
2111 j++;
2112 continue;
2113 }
2114 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2115 if (bnx2x_stats_arr[i].size == 4) {
2116 /* 4-byte counter */
2117 buf[j] = (u64) *offset;
2118 j++;
2119 continue;
2120 }
2121 /* 8-byte counter */
2122 buf[j] = HILO_U64(*offset, *(offset + 1));
2123 j++;
2124 }
2125 }
2126}
2127
32d36134 2128static int bnx2x_set_phys_id(struct net_device *dev,
2129 enum ethtool_phys_id_state state)
de0c62db
DK		 2130{
2131 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 2132
2133 if (!netif_running(dev))
32d36134 2134 return -EAGAIN;
de0c62db
DK		 2135
2136 if (!bp->port.pmf)
32d36134 2137 return -EOPNOTSUPP;
de0c62db 2138
32d36134 2139 switch (state) {
2140 case ETHTOOL_ID_ACTIVE:
fce55922 2141 return 1; /* cycle on/off once per second */
de0c62db 2142
32d36134 2143 case ETHTOOL_ID_ON:
2144 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2145 LED_MODE_ON, SPEED_1000);
32d36134 2146 break;
de0c62db 2147
32d36134 2148 case ETHTOOL_ID_OFF:
2149 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2150 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2151
32d36134 2152 break;
2153
2154 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2155 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2156 LED_MODE_OPER,
2157 bp->link_vars.line_speed);
32d36134 2158 }
de0c62db
DK		 2159
2160 return 0;
2161}
2162
ab532cf3
TH		 2163static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2164 void *rules __always_unused)
2165{
2166 struct bnx2x *bp = netdev_priv(dev);
2167
2168 switch (info->cmd) {
2169 case ETHTOOL_GRXRINGS:
2170 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2171 return 0;
2172
2173 default:
2174 return -EOPNOTSUPP;
2175 }
2176}
2177
2178static int bnx2x_get_rxfh_indir(struct net_device *dev,
2179 struct ethtool_rxfh_indir *indir)
2180{
2181 struct bnx2x *bp = netdev_priv(dev);
2182 size_t copy_size =
619c5cb6
VZ		 2183 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE);
2184 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2185 size_t i;
ab532cf3
TH		 2186
2187 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2188 return -EOPNOTSUPP;
2189
619c5cb6
VZ		 2190 /* Get the current configuration of the RSS indirection table */
2191 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2192
2193 /*
2194 * We can't use a memcpy() as an internal storage of an
2195 * indirection table is a u8 array while indir->ring_index
2196 * points to an array of u32.
2197 *
2198 * Indirection table contains the FW Client IDs, so we need to
2199 * align the returned table to the Client ID of the leading RSS
2200 * queue.
2201 */
2202 for (i = 0; i < copy_size; i++)
2203 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id;
2204
2205 indir->size = T_ETH_INDIRECTION_TABLE_SIZE;
2206
ab532cf3
TH		 2207 return 0;
2208}
2209
2210static int bnx2x_set_rxfh_indir(struct net_device *dev,
2211 const struct ethtool_rxfh_indir *indir)
2212{
2213 struct bnx2x *bp = netdev_priv(dev);
2214 size_t i;
619c5cb6
VZ		 2215 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2216 u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
ab532cf3
TH		 2217
2218 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2219 return -EOPNOTSUPP;
2220
619c5cb6
VZ		 2221 /* validate the size */
2222 if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE)
ab532cf3 2223 return -EINVAL;
619c5cb6
VZ		 2224
2225 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2226 /* validate the indices */
2227 if (indir->ring_index[i] >= num_eth_queues)
ab532cf3 2228 return -EINVAL;
619c5cb6
VZ		 2229 /*
2230 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2231 * as an internal storage of an indirection table is a u8 array
2232 * while indir->ring_index points to an array of u32.
2233 *
2234 * Indirection table contains the FW Client IDs, so we need to
2235 * align the received table to the Client ID of the leading RSS
2236 * queue
2237 */
2238 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id;
2239 }
ab532cf3 2240
619c5cb6 2241 return bnx2x_config_rss_pf(bp, ind_table, false);
ab532cf3
TH		 2242}
2243
de0c62db
DK		 2244static const struct ethtool_ops bnx2x_ethtool_ops = {
2245 .get_settings = bnx2x_get_settings,
2246 .set_settings = bnx2x_set_settings,
2247 .get_drvinfo = bnx2x_get_drvinfo,
2248 .get_regs_len = bnx2x_get_regs_len,
2249 .get_regs = bnx2x_get_regs,
2250 .get_wol = bnx2x_get_wol,
2251 .set_wol = bnx2x_set_wol,
2252 .get_msglevel = bnx2x_get_msglevel,
2253 .set_msglevel = bnx2x_set_msglevel,
2254 .nway_reset = bnx2x_nway_reset,
2255 .get_link = bnx2x_get_link,
2256 .get_eeprom_len = bnx2x_get_eeprom_len,
2257 .get_eeprom = bnx2x_get_eeprom,
2258 .set_eeprom = bnx2x_set_eeprom,
2259 .get_coalesce = bnx2x_get_coalesce,
2260 .set_coalesce = bnx2x_set_coalesce,
2261 .get_ringparam = bnx2x_get_ringparam,
2262 .set_ringparam = bnx2x_set_ringparam,
2263 .get_pauseparam = bnx2x_get_pauseparam,
2264 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2265 .self_test = bnx2x_self_test,
2266 .get_sset_count = bnx2x_get_sset_count,
2267 .get_strings = bnx2x_get_strings,
32d36134 2268 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2269 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3
TH		 2270 .get_rxnfc = bnx2x_get_rxnfc,
2271 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2272 .set_rxfh_indir = bnx2x_set_rxfh_indir,
de0c62db
DK		 2273};
2274
2275void bnx2x_set_ethtool_ops(struct net_device *netdev)
2276{
2277 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2278}
kernel source for telekom puls (alcatel/mediatek)