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bnx2x: fix vlan-mac memory leak
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
c96bdc0c
DK		 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
ec6ba945
VZ		 68};
69
70#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72static const struct {
73 long offset;
74 int size;
75 u32 flags;
76#define STATS_FLAGS_PORT 1
77#define STATS_FLAGS_FUNC 2
78#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80} bnx2x_stats_arr[] = {
81/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
c96bdc0c
DK		 182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
e9939c80
YM		 184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
07ba6af4 189
1ac9e428
YR		 190static int bnx2x_get_port_type(struct bnx2x *bp)
191{
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217}
ec6ba945 218
de0c62db
DK		 219static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
220{
221 struct bnx2x *bp = netdev_priv(dev);
a22f0788 222 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 223
a22f0788
YR		 224 /* Dual Media boards present all available port types */
225 cmd->supported = bp->port.supported[cfg_idx] |
226 (bp->port.supported[cfg_idx ^ 1] &
227 (SUPPORTED_TP | SUPPORTED_FIBRE));
228 cmd->advertising = bp->port.advertising[cfg_idx];
dbef807e
YM		 229 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
230 ETH_PHY_SFP_1G_FIBER) {
231 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
232 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
233 }
de0c62db 234
59694f00
YM		 235 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
236 !(bp->flags & MF_FUNC_DIS)) {
2de67439 237 cmd->duplex = bp->link_vars.duplex;
38298461
YM		 238
239 if (IS_MF(bp) && !BP_NOMCP(bp))
240 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
59694f00
YM		 241 else
242 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 243 } else {
38298461
YM		 244 cmd->duplex = DUPLEX_UNKNOWN;
245 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 246 }
f2e0899f 247
1ac9e428 248 cmd->port = bnx2x_get_port_type(bp);
a22f0788 249
de0c62db
DK		 250 cmd->phy_address = bp->mdio.prtad;
251 cmd->transceiver = XCVR_INTERNAL;
252
a22f0788 253 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 254 cmd->autoneg = AUTONEG_ENABLE;
255 else
256 cmd->autoneg = AUTONEG_DISABLE;
257
9e7e8399
MY		 258 /* Publish LP advertised speeds and FC */
259 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
260 u32 status = bp->link_vars.link_status;
261
262 cmd->lp_advertising |= ADVERTISED_Autoneg;
263 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
264 cmd->lp_advertising |= ADVERTISED_Pause;
265 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
266 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
267
268 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
269 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
270 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
271 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
272 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
273 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
274 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
275 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
276 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
277 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
278 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
279 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
280 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
281 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
282 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
283 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
be94bea7
YR		 284 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
285 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
9e7e8399
MY		 286 }
287
de0c62db
DK		 288 cmd->maxtxpkt = 0;
289 cmd->maxrxpkt = 0;
290
51c1a580 291 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 292 " supported 0x%x advertising 0x%x speed %u\n"
293 " duplex %d port %d phy_address %d transceiver %d\n"
294 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 295 cmd->cmd, cmd->supported, cmd->advertising,
296 ethtool_cmd_speed(cmd),
de0c62db
DK		 297 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
298 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
299
300 return 0;
301}
302
303static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
304{
305 struct bnx2x *bp = netdev_priv(dev);
a22f0788 306 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 307 u32 speed, phy_idx;
de0c62db 308
0793f83f 309 if (IS_MF_SD(bp))
de0c62db
DK		 310 return 0;
311
51c1a580 312 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 313 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 314 " duplex %d port %d phy_address %d transceiver %d\n"
315 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 316 cmd->cmd, cmd->supported, cmd->advertising,
317 ethtool_cmd_speed(cmd),
de0c62db
DK		 318 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
319 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
320
b3337e4c 321 speed = ethtool_cmd_speed(cmd);
0793f83f 322
38298461
YM		 323 /* If recieved a request for an unknown duplex, assume full*/
324 if (cmd->duplex == DUPLEX_UNKNOWN)
325 cmd->duplex = DUPLEX_FULL;
326
0793f83f 327 if (IS_MF_SI(bp)) {
e3835b99 328 u32 part;
0793f83f
DK		 329 u32 line_speed = bp->link_vars.line_speed;
330
331 /* use 10G if no link detected */
332 if (!line_speed)
333 line_speed = 10000;
334
335 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 336 DP(BNX2X_MSG_ETHTOOL,
337 "To set speed BC %X or higher is required, please upgrade BC\n",
338 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 339 return -EINVAL;
340 }
e3835b99 341
faa6fcbb 342 part = (speed * 100) / line_speed;
e3835b99 343
faa6fcbb 344 if (line_speed < speed || !part) {
51c1a580
MS		 345 DP(BNX2X_MSG_ETHTOOL,
346 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 347 return -EINVAL;
348 }
0793f83f 349
e3835b99
DK		 350 if (bp->state != BNX2X_STATE_OPEN)
351 /* store value for following "load" */
352 bp->pending_max = part;
353 else
354 bnx2x_update_max_mf_config(bp, part);
0793f83f 355
0793f83f
DK		 356 return 0;
357 }
358
a22f0788
YR		 359 cfg_idx = bnx2x_get_link_cfg_idx(bp);
360 old_multi_phy_config = bp->link_params.multi_phy_config;
361 switch (cmd->port) {
362 case PORT_TP:
363 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
364 break; /* no port change */
365
366 if (!(bp->port.supported[0] & SUPPORTED_TP ||
367 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 368 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 369 return -EINVAL;
370 }
371 bp->link_params.multi_phy_config &=
372 ~PORT_HW_CFG_PHY_SELECTION_MASK;
373 if (bp->link_params.multi_phy_config &
374 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
375 bp->link_params.multi_phy_config |=
376 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
377 else
378 bp->link_params.multi_phy_config |=
379 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
380 break;
381 case PORT_FIBRE:
bfdb5823 382 case PORT_DA:
a22f0788
YR		 383 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
384 break; /* no port change */
385
386 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
387 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 388 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 389 return -EINVAL;
390 }
391 bp->link_params.multi_phy_config &=
392 ~PORT_HW_CFG_PHY_SELECTION_MASK;
393 if (bp->link_params.multi_phy_config &
394 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
395 bp->link_params.multi_phy_config |=
396 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
397 else
398 bp->link_params.multi_phy_config |=
399 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
400 break;
401 default:
51c1a580 402 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 403 return -EINVAL;
404 }
2de67439 405 /* Save new config in case command complete successfully */
a22f0788
YR		 406 new_multi_phy_config = bp->link_params.multi_phy_config;
407 /* Get the new cfg_idx */
408 cfg_idx = bnx2x_get_link_cfg_idx(bp);
409 /* Restore old config in case command failed */
410 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 411 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 412
de0c62db 413 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 414 u32 an_supported_speed = bp->port.supported[cfg_idx];
415 if (bp->link_params.phy[EXT_PHY1].type ==
416 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
417 an_supported_speed |= (SUPPORTED_100baseT_Half |
418 SUPPORTED_100baseT_Full);
a22f0788 419 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 420 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 421 return -EINVAL;
422 }
423
424 /* advertise the requested speed and duplex if supported */
75318327 425 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 426 DP(BNX2X_MSG_ETHTOOL,
427 "Advertisement parameters are not supported\n");
8d661637
YR		 428 return -EINVAL;
429 }
de0c62db 430
a22f0788 431 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 432 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
433 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 434 cmd->advertising);
8d661637
YR		 435 if (cmd->advertising) {
436
437 bp->link_params.speed_cap_mask[cfg_idx] = 0;
438 if (cmd->advertising & ADVERTISED_10baseT_Half) {
439 bp->link_params.speed_cap_mask[cfg_idx] |=
440 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
441 }
442 if (cmd->advertising & ADVERTISED_10baseT_Full)
443 bp->link_params.speed_cap_mask[cfg_idx] |=
444 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 445
8d661637
YR		 446 if (cmd->advertising & ADVERTISED_100baseT_Full)
447 bp->link_params.speed_cap_mask[cfg_idx] |=
448 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
449
450 if (cmd->advertising & ADVERTISED_100baseT_Half) {
451 bp->link_params.speed_cap_mask[cfg_idx] |=
452 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
453 }
454 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
455 bp->link_params.speed_cap_mask[cfg_idx] |=
456 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
457 }
458 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
459 ADVERTISED_1000baseKX_Full))
460 bp->link_params.speed_cap_mask[cfg_idx] |=
461 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
462
463 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
464 ADVERTISED_10000baseKX4_Full |
465 ADVERTISED_10000baseKR_Full))
466 bp->link_params.speed_cap_mask[cfg_idx] |=
467 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
be94bea7
YR		 468
469 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
470 bp->link_params.speed_cap_mask[cfg_idx] |=
471 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
8d661637 472 }
de0c62db
DK		 473 } else { /* forced speed */
474 /* advertise the requested speed and duplex if supported */
a22f0788 475 switch (speed) {
de0c62db
DK		 476 case SPEED_10:
477 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 478 if (!(bp->port.supported[cfg_idx] &
de0c62db 479 SUPPORTED_10baseT_Full)) {
51c1a580 480 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 481 "10M full not supported\n");
482 return -EINVAL;
483 }
484
485 advertising = (ADVERTISED_10baseT_Full |
486 ADVERTISED_TP);
487 } else {
a22f0788 488 if (!(bp->port.supported[cfg_idx] &
de0c62db 489 SUPPORTED_10baseT_Half)) {
51c1a580 490 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 491 "10M half not supported\n");
492 return -EINVAL;
493 }
494
495 advertising = (ADVERTISED_10baseT_Half |
496 ADVERTISED_TP);
497 }
498 break;
499
500 case SPEED_100:
501 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 502 if (!(bp->port.supported[cfg_idx] &
de0c62db 503 SUPPORTED_100baseT_Full)) {
51c1a580 504 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 505 "100M full not supported\n");
506 return -EINVAL;
507 }
508
509 advertising = (ADVERTISED_100baseT_Full |
510 ADVERTISED_TP);
511 } else {
a22f0788 512 if (!(bp->port.supported[cfg_idx] &
de0c62db 513 SUPPORTED_100baseT_Half)) {
51c1a580 514 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 515 "100M half not supported\n");
516 return -EINVAL;
517 }
518
519 advertising = (ADVERTISED_100baseT_Half |
520 ADVERTISED_TP);
521 }
522 break;
523
524 case SPEED_1000:
525 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 526 DP(BNX2X_MSG_ETHTOOL,
527 "1G half not supported\n");
de0c62db
DK		 528 return -EINVAL;
529 }
530
a22f0788
YR		 531 if (!(bp->port.supported[cfg_idx] &
532 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 533 DP(BNX2X_MSG_ETHTOOL,
534 "1G full not supported\n");
de0c62db
DK		 535 return -EINVAL;
536 }
537
538 advertising = (ADVERTISED_1000baseT_Full |
539 ADVERTISED_TP);
540 break;
541
542 case SPEED_2500:
543 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 544 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 545 "2.5G half not supported\n");
546 return -EINVAL;
547 }
548
a22f0788
YR		 549 if (!(bp->port.supported[cfg_idx]
550 & SUPPORTED_2500baseX_Full)) {
51c1a580 551 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 552 "2.5G full not supported\n");
553 return -EINVAL;
554 }
555
556 advertising = (ADVERTISED_2500baseX_Full |
557 ADVERTISED_TP);
558 break;
559
560 case SPEED_10000:
561 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 562 DP(BNX2X_MSG_ETHTOOL,
563 "10G half not supported\n");
de0c62db
DK		 564 return -EINVAL;
565 }
dbef807e 566 phy_idx = bnx2x_get_cur_phy_idx(bp);
a22f0788 567 if (!(bp->port.supported[cfg_idx]
dbef807e
YM		 568 & SUPPORTED_10000baseT_Full) ||
569 (bp->link_params.phy[phy_idx].media_type ==
570 ETH_PHY_SFP_1G_FIBER)) {
51c1a580
MS		 571 DP(BNX2X_MSG_ETHTOOL,
572 "10G full not supported\n");
de0c62db
DK		 573 return -EINVAL;
574 }
575
576 advertising = (ADVERTISED_10000baseT_Full |
577 ADVERTISED_FIBRE);
578 break;
579
580 default:
51c1a580 581 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 582 return -EINVAL;
583 }
584
a22f0788
YR		 585 bp->link_params.req_line_speed[cfg_idx] = speed;
586 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
587 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 588 }
589
51c1a580 590 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 591 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 592 bp->link_params.req_line_speed[cfg_idx],
593 bp->link_params.req_duplex[cfg_idx],
594 bp->port.advertising[cfg_idx]);
de0c62db 595
a22f0788
YR		 596 /* Set new config */
597 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 598 if (netif_running(dev)) {
599 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
600 bnx2x_link_set(bp);
601 }
602
603 return 0;
604}
605
07ba6af4
MS		 606#define DUMP_ALL_PRESETS 0x1FFF
607#define DUMP_MAX_PRESETS 13
0fea29c1 608
07ba6af4 609static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
0fea29c1
VZ		 610{
611 if (CHIP_IS_E1(bp))
07ba6af4 612 return dump_num_registers[0][preset-1];
0fea29c1 613 else if (CHIP_IS_E1H(bp))
07ba6af4 614 return dump_num_registers[1][preset-1];
0fea29c1 615 else if (CHIP_IS_E2(bp))
07ba6af4 616 return dump_num_registers[2][preset-1];
0fea29c1 617 else if (CHIP_IS_E3A0(bp))
07ba6af4 618 return dump_num_registers[3][preset-1];
0fea29c1 619 else if (CHIP_IS_E3B0(bp))
07ba6af4 620 return dump_num_registers[4][preset-1];
0fea29c1 621 else
07ba6af4
MS		 622 return 0;
623}
624
625static int __bnx2x_get_regs_len(struct bnx2x *bp)
626{
627 u32 preset_idx;
628 int regdump_len = 0;
629
630 /* Calculate the total preset regs length */
631 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
632 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
633
634 return regdump_len;
635}
636
637static int bnx2x_get_regs_len(struct net_device *dev)
638{
639 struct bnx2x *bp = netdev_priv(dev);
640 int regdump_len = 0;
641
642 regdump_len = __bnx2x_get_regs_len(bp);
643 regdump_len *= 4;
644 regdump_len += sizeof(struct dump_header);
645
646 return regdump_len;
0fea29c1
VZ		 647}
648
07ba6af4
MS		 649#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
650#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
651#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
652#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
653#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
654
655#define IS_REG_IN_PRESET(presets, idx) \
656 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
657
0fea29c1 658/******* Paged registers info selectors ********/
1191cb83 659static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 660{
661 if (CHIP_IS_E2(bp))
662 return page_vals_e2;
663 else if (CHIP_IS_E3(bp))
664 return page_vals_e3;
665 else
666 return NULL;
667}
668
1191cb83 669static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 670{
671 if (CHIP_IS_E2(bp))
672 return PAGE_MODE_VALUES_E2;
673 else if (CHIP_IS_E3(bp))
674 return PAGE_MODE_VALUES_E3;
675 else
676 return 0;
677}
678
1191cb83 679static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 680{
681 if (CHIP_IS_E2(bp))
682 return page_write_regs_e2;
683 else if (CHIP_IS_E3(bp))
684 return page_write_regs_e3;
685 else
686 return NULL;
687}
688
1191cb83 689static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 690{
691 if (CHIP_IS_E2(bp))
692 return PAGE_WRITE_REGS_E2;
693 else if (CHIP_IS_E3(bp))
694 return PAGE_WRITE_REGS_E3;
695 else
696 return 0;
697}
698
1191cb83 699static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 700{
701 if (CHIP_IS_E2(bp))
702 return page_read_regs_e2;
703 else if (CHIP_IS_E3(bp))
704 return page_read_regs_e3;
705 else
706 return NULL;
707}
708
1191cb83 709static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 710{
711 if (CHIP_IS_E2(bp))
712 return PAGE_READ_REGS_E2;
713 else if (CHIP_IS_E3(bp))
714 return PAGE_READ_REGS_E3;
715 else
716 return 0;
717}
718
07ba6af4
MS		 719static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
720 const struct reg_addr *reg_info)
0fea29c1 721{
07ba6af4
MS		 722 if (CHIP_IS_E1(bp))
723 return IS_E1_REG(reg_info->chips);
724 else if (CHIP_IS_E1H(bp))
725 return IS_E1H_REG(reg_info->chips);
726 else if (CHIP_IS_E2(bp))
727 return IS_E2_REG(reg_info->chips);
728 else if (CHIP_IS_E3A0(bp))
729 return IS_E3A0_REG(reg_info->chips);
730 else if (CHIP_IS_E3B0(bp))
731 return IS_E3B0_REG(reg_info->chips);
732 else
733 return false;
0fea29c1 734}
de0c62db 735
de0c62db 736
07ba6af4
MS		 737static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
738 const struct wreg_addr *wreg_info)
739{
740 if (CHIP_IS_E1(bp))
741 return IS_E1_REG(wreg_info->chips);
742 else if (CHIP_IS_E1H(bp))
743 return IS_E1H_REG(wreg_info->chips);
744 else if (CHIP_IS_E2(bp))
745 return IS_E2_REG(wreg_info->chips);
746 else if (CHIP_IS_E3A0(bp))
747 return IS_E3A0_REG(wreg_info->chips);
748 else if (CHIP_IS_E3B0(bp))
749 return IS_E3B0_REG(wreg_info->chips);
750 else
751 return false;
de0c62db
DK		 752}
753
0fea29c1
VZ		 754/**
755 * bnx2x_read_pages_regs - read "paged" registers
756 *
757 * @bp device handle
758 * @p output buffer
759 *
2de67439
YM		 760 * Reads "paged" memories: memories that may only be read by first writing to a
761 * specific address ("write address") and then reading from a specific address
762 * ("read address"). There may be more than one write address per "page" and
763 * more than one read address per write address.
0fea29c1 764 */
07ba6af4 765static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
f2e0899f
DK		 766{
767 u32 i, j, k, n;
07ba6af4 768
0fea29c1
VZ		 769 /* addresses of the paged registers */
770 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
771 /* number of paged registers */
772 int num_pages = __bnx2x_get_page_reg_num(bp);
773 /* write addresses */
774 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
775 /* number of write addresses */
776 int write_num = __bnx2x_get_page_write_num(bp);
777 /* read addresses info */
778 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
779 /* number of read addresses */
780 int read_num = __bnx2x_get_page_read_num(bp);
07ba6af4 781 u32 addr, size;
0fea29c1
VZ		 782
783 for (i = 0; i < num_pages; i++) {
784 for (j = 0; j < write_num; j++) {
785 REG_WR(bp, write_addr[j], page_addr[i]);
07ba6af4
MS		 786
787 for (k = 0; k < read_num; k++) {
788 if (IS_REG_IN_PRESET(read_addr[k].presets,
789 preset)) {
790 size = read_addr[k].size;
791 for (n = 0; n < size; n++) {
792 addr = read_addr[k].addr + n*4;
793 *p++ = REG_RD(bp, addr);
794 }
795 }
796 }
f2e0899f
DK		 797 }
798 }
799}
800
07ba6af4 801static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
0fea29c1 802{
07ba6af4
MS		 803 u32 i, j, addr;
804 const struct wreg_addr *wreg_addr_p = NULL;
805
806 if (CHIP_IS_E1(bp))
807 wreg_addr_p = &wreg_addr_e1;
808 else if (CHIP_IS_E1H(bp))
809 wreg_addr_p = &wreg_addr_e1h;
810 else if (CHIP_IS_E2(bp))
811 wreg_addr_p = &wreg_addr_e2;
812 else if (CHIP_IS_E3A0(bp))
813 wreg_addr_p = &wreg_addr_e3;
814 else if (CHIP_IS_E3B0(bp))
815 wreg_addr_p = &wreg_addr_e3b0;
816
817 /* Read the idle_chk registers */
818 for (i = 0; i < IDLE_REGS_COUNT; i++) {
819 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
820 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
821 for (j = 0; j < idle_reg_addrs[i].size; j++)
822 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
823 }
824 }
0fea29c1
VZ		 825
826 /* Read the regular registers */
07ba6af4
MS		 827 for (i = 0; i < REGS_COUNT; i++) {
828 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
829 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
0fea29c1
VZ		 830 for (j = 0; j < reg_addrs[i].size; j++)
831 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
07ba6af4
MS		 832 }
833 }
834
835 /* Read the CAM registers */
836 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
837 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
838 for (i = 0; i < wreg_addr_p->size; i++) {
839 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
840
841 /* In case of wreg_addr register, read additional
842 registers from read_regs array
843 */
844 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
845 addr = *(wreg_addr_p->read_regs);
846 *p++ = REG_RD(bp, addr + j*4);
847 }
848 }
849 }
850
851 /* Paged registers are supported in E2 & E3 only */
852 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
853 /* Read "paged" registes */
854 bnx2x_read_pages_regs(bp, p, preset);
855 }
856
857 return 0;
858}
859
860static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
861{
862 u32 preset_idx;
0fea29c1 863
07ba6af4
MS		 864 /* Read all registers, by reading all preset registers */
865 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
866 /* Skip presets with IOR */
867 if ((preset_idx == 2) ||
868 (preset_idx == 5) ||
869 (preset_idx == 8) ||
870 (preset_idx == 11))
871 continue;
872 __bnx2x_get_preset_regs(bp, p, preset_idx);
873 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
874 }
0fea29c1
VZ		 875}
876
de0c62db
DK		 877static void bnx2x_get_regs(struct net_device *dev,
878 struct ethtool_regs *regs, void *_p)
879{
0fea29c1 880 u32 *p = _p;
de0c62db 881 struct bnx2x *bp = netdev_priv(dev);
07ba6af4 882 struct dump_header dump_hdr = {0};
de0c62db 883
07ba6af4 884 regs->version = 2;
de0c62db
DK		 885 memset(p, 0, regs->len);
886
887 if (!netif_running(bp->dev))
888 return;
889
4a33bc03
VZ		 890 /* Disable parity attentions as long as following dump may
891 * cause false alarms by reading never written registers. We
892 * will re-enable parity attentions right after the dump.
893 */
07ba6af4
MS		 894
895 /* Disable parity on path 0 */
896 bnx2x_pretend_func(bp, 0);
4a33bc03
VZ		 897 bnx2x_disable_blocks_parity(bp);
898
07ba6af4
MS		 899 /* Disable parity on path 1 */
900 bnx2x_pretend_func(bp, 1);
901 bnx2x_disable_blocks_parity(bp);
f2e0899f 902
07ba6af4
MS		 903 /* Return to current function */
904 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
de0c62db 905
07ba6af4
MS		 906 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
907 dump_hdr.preset = DUMP_ALL_PRESETS;
908 dump_hdr.version = BNX2X_DUMP_VERSION;
909
910 /* dump_meta_data presents OR of CHIP and PATH. */
911 if (CHIP_IS_E1(bp)) {
912 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
913 } else if (CHIP_IS_E1H(bp)) {
914 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
915 } else if (CHIP_IS_E2(bp)) {
916 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
917 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
918 } else if (CHIP_IS_E3A0(bp)) {
919 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
920 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
921 } else if (CHIP_IS_E3B0(bp)) {
922 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
923 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
924 }
925
926 memcpy(p, &dump_hdr, sizeof(struct dump_header));
927 p += dump_hdr.header_size + 1;
de0c62db 928
0fea29c1
VZ		 929 /* Actually read the registers */
930 __bnx2x_get_regs(bp, p);
931
07ba6af4
MS		 932 /* Re-enable parity attentions on path 0 */
933 bnx2x_pretend_func(bp, 0);
934 bnx2x_clear_blocks_parity(bp);
935 bnx2x_enable_blocks_parity(bp);
936
937 /* Re-enable parity attentions on path 1 */
938 bnx2x_pretend_func(bp, 1);
4a33bc03 939 bnx2x_clear_blocks_parity(bp);
c9ee9206 940 bnx2x_enable_blocks_parity(bp);
07ba6af4
MS		 941
942 /* Return to current function */
943 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
944}
945
946static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
947{
948 struct bnx2x *bp = netdev_priv(dev);
949 int regdump_len = 0;
950
951 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
952 regdump_len *= 4;
953 regdump_len += sizeof(struct dump_header);
954
955 return regdump_len;
956}
957
958static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
959{
960 struct bnx2x *bp = netdev_priv(dev);
961
962 /* Use the ethtool_dump "flag" field as the dump preset index */
963 bp->dump_preset_idx = val->flag;
964 return 0;
965}
966
967static int bnx2x_get_dump_flag(struct net_device *dev,
968 struct ethtool_dump *dump)
969{
970 struct bnx2x *bp = netdev_priv(dev);
971
972 /* Calculate the requested preset idx length */
973 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
974 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
975 bp->dump_preset_idx, dump->len);
976
977 dump->flag = ETHTOOL_GET_DUMP_DATA;
978 return 0;
979}
980
981static int bnx2x_get_dump_data(struct net_device *dev,
982 struct ethtool_dump *dump,
983 void *buffer)
984{
985 u32 *p = buffer;
986 struct bnx2x *bp = netdev_priv(dev);
987 struct dump_header dump_hdr = {0};
988
989 memset(p, 0, dump->len);
990
991 /* Disable parity attentions as long as following dump may
992 * cause false alarms by reading never written registers. We
993 * will re-enable parity attentions right after the dump.
994 */
995
996 /* Disable parity on path 0 */
997 bnx2x_pretend_func(bp, 0);
998 bnx2x_disable_blocks_parity(bp);
999
1000 /* Disable parity on path 1 */
1001 bnx2x_pretend_func(bp, 1);
1002 bnx2x_disable_blocks_parity(bp);
1003
1004 /* Return to current function */
1005 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1006
1007 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1008 dump_hdr.preset = bp->dump_preset_idx;
1009 dump_hdr.version = BNX2X_DUMP_VERSION;
1010
1011 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1012
1013 /* dump_meta_data presents OR of CHIP and PATH. */
1014 if (CHIP_IS_E1(bp)) {
1015 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1016 } else if (CHIP_IS_E1H(bp)) {
1017 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1018 } else if (CHIP_IS_E2(bp)) {
1019 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1020 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1021 } else if (CHIP_IS_E3A0(bp)) {
1022 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1023 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1024 } else if (CHIP_IS_E3B0(bp)) {
1025 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1026 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1027 }
1028
1029 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1030 p += dump_hdr.header_size + 1;
1031
1032 /* Actually read the registers */
1033 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1034
1035 /* Re-enable parity attentions on path 0 */
1036 bnx2x_pretend_func(bp, 0);
1037 bnx2x_clear_blocks_parity(bp);
1038 bnx2x_enable_blocks_parity(bp);
1039
1040 /* Re-enable parity attentions on path 1 */
1041 bnx2x_pretend_func(bp, 1);
1042 bnx2x_clear_blocks_parity(bp);
1043 bnx2x_enable_blocks_parity(bp);
1044
1045 /* Return to current function */
1046 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1047
1048 return 0;
de0c62db
DK		 1049}
1050
de0c62db
DK		 1051static void bnx2x_get_drvinfo(struct net_device *dev,
1052 struct ethtool_drvinfo *info)
1053{
1054 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1055
68aad78c
RJ		 1056 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1057 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db 1058
8ca5e17e
AE		 1059 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1060
68aad78c 1061 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 1062 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 1063 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 1064 info->eedump_len = bp->common.flash_size;
1065 info->regdump_len = bnx2x_get_regs_len(dev);
1066}
1067
1068static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1069{
1070 struct bnx2x *bp = netdev_priv(dev);
1071
1072 if (bp->flags & NO_WOL_FLAG) {
1073 wol->supported = 0;
1074 wol->wolopts = 0;
1075 } else {
1076 wol->supported = WAKE_MAGIC;
1077 if (bp->wol)
1078 wol->wolopts = WAKE_MAGIC;
1079 else
1080 wol->wolopts = 0;
1081 }
1082 memset(&wol->sopass, 0, sizeof(wol->sopass));
1083}
1084
1085static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1086{
1087 struct bnx2x *bp = netdev_priv(dev);
1088
51c1a580 1089 if (wol->wolopts & ~WAKE_MAGIC) {
2de67439 1090 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1091 return -EINVAL;
51c1a580 1092 }
de0c62db
DK		 1093
1094 if (wol->wolopts & WAKE_MAGIC) {
51c1a580 1095 if (bp->flags & NO_WOL_FLAG) {
2de67439 1096 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
de0c62db 1097 return -EINVAL;
51c1a580 1098 }
de0c62db
DK		 1099 bp->wol = 1;
1100 } else
1101 bp->wol = 0;
1102
1103 return 0;
1104}
1105
1106static u32 bnx2x_get_msglevel(struct net_device *dev)
1107{
1108 struct bnx2x *bp = netdev_priv(dev);
1109
1110 return bp->msg_enable;
1111}
1112
1113static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1114{
1115 struct bnx2x *bp = netdev_priv(dev);
1116
7a25cc73
DK		 1117 if (capable(CAP_NET_ADMIN)) {
1118 /* dump MCP trace */
ad5afc89 1119 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
7a25cc73 1120 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 1121 bp->msg_enable = level;
7a25cc73 1122 }
de0c62db
DK		 1123}
1124
1125static int bnx2x_nway_reset(struct net_device *dev)
1126{
1127 struct bnx2x *bp = netdev_priv(dev);
1128
1129 if (!bp->port.pmf)
1130 return 0;
1131
1132 if (netif_running(dev)) {
1133 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1134 bnx2x_force_link_reset(bp);
de0c62db
DK		 1135 bnx2x_link_set(bp);
1136 }
1137
1138 return 0;
1139}
1140
1141static u32 bnx2x_get_link(struct net_device *dev)
1142{
1143 struct bnx2x *bp = netdev_priv(dev);
1144
f2e0899f 1145 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 1146 return 0;
1147
1148 return bp->link_vars.link_up;
1149}
1150
1151static int bnx2x_get_eeprom_len(struct net_device *dev)
1152{
1153 struct bnx2x *bp = netdev_priv(dev);
1154
1155 return bp->common.flash_size;
1156}
1157
f16da43b
AE		 1158/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
1159 * we done things the other way around, if two pfs from the same port would
1160 * attempt to access nvram at the same time, we could run into a scenario such
1161 * as:
1162 * pf A takes the port lock.
1163 * pf B succeeds in taking the same lock since they are from the same port.
1164 * pf A takes the per pf misc lock. Performs eeprom access.
1165 * pf A finishes. Unlocks the per pf misc lock.
1166 * Pf B takes the lock and proceeds to perform it's own access.
1167 * pf A unlocks the per port lock, while pf B is still working (!).
1168 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
2de67439 1169 * access corrupted by pf B)
f16da43b 1170 */
de0c62db
DK		 1171static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1172{
1173 int port = BP_PORT(bp);
1174 int count, i;
f16da43b
AE		 1175 u32 val;
1176
1177 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1178 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1179
1180 /* adjust timeout for emulation/FPGA */
754a2f52 1181 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1182 if (CHIP_REV_IS_SLOW(bp))
1183 count *= 100;
1184
1185 /* request access to nvram interface */
1186 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1187 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1188
1189 for (i = 0; i < count*10; i++) {
1190 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1191 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1192 break;
1193
1194 udelay(5);
1195 }
1196
1197 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 1198 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1199 "cannot get access to nvram interface\n");
de0c62db
DK		 1200 return -EBUSY;
1201 }
1202
1203 return 0;
1204}
1205
1206static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1207{
1208 int port = BP_PORT(bp);
1209 int count, i;
f16da43b 1210 u32 val;
de0c62db
DK		 1211
1212 /* adjust timeout for emulation/FPGA */
754a2f52 1213 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1214 if (CHIP_REV_IS_SLOW(bp))
1215 count *= 100;
1216
1217 /* relinquish nvram interface */
1218 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1219 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1220
1221 for (i = 0; i < count*10; i++) {
1222 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1223 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1224 break;
1225
1226 udelay(5);
1227 }
1228
1229 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 1230 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1231 "cannot free access to nvram interface\n");
de0c62db
DK		 1232 return -EBUSY;
1233 }
1234
f16da43b
AE		 1235 /* release HW lock: protect against other PFs in PF Direct Assignment */
1236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1237 return 0;
1238}
1239
1240static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1241{
1242 u32 val;
1243
1244 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1245
1246 /* enable both bits, even on read */
1247 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1248 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1249 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1250}
1251
1252static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1253{
1254 u32 val;
1255
1256 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1257
1258 /* disable both bits, even after read */
1259 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1260 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1261 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1262}
1263
1264static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1265 u32 cmd_flags)
1266{
1267 int count, i, rc;
1268 u32 val;
1269
1270 /* build the command word */
1271 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1272
1273 /* need to clear DONE bit separately */
1274 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1275
1276 /* address of the NVRAM to read from */
1277 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1278 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1279
1280 /* issue a read command */
1281 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1282
1283 /* adjust timeout for emulation/FPGA */
754a2f52 1284 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1285 if (CHIP_REV_IS_SLOW(bp))
1286 count *= 100;
1287
1288 /* wait for completion */
1289 *ret_val = 0;
1290 rc = -EBUSY;
1291 for (i = 0; i < count; i++) {
1292 udelay(5);
1293 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1294
1295 if (val & MCPR_NVM_COMMAND_DONE) {
1296 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1297 /* we read nvram data in cpu order
1298 * but ethtool sees it as an array of bytes
07ba6af4
MS		 1299 * converting to big-endian will do the work
1300 */
de0c62db
DK		 1301 *ret_val = cpu_to_be32(val);
1302 rc = 0;
1303 break;
1304 }
1305 }
51c1a580
MS		 1306 if (rc == -EBUSY)
1307 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1308 "nvram read timeout expired\n");
de0c62db
DK		 1309 return rc;
1310}
1311
1312static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1313 int buf_size)
1314{
1315 int rc;
1316 u32 cmd_flags;
1317 __be32 val;
1318
1319 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1321 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1322 offset, buf_size);
1323 return -EINVAL;
1324 }
1325
1326 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1327 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1328 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1329 offset, buf_size, bp->common.flash_size);
1330 return -EINVAL;
1331 }
1332
1333 /* request access to nvram interface */
1334 rc = bnx2x_acquire_nvram_lock(bp);
1335 if (rc)
1336 return rc;
1337
1338 /* enable access to nvram interface */
1339 bnx2x_enable_nvram_access(bp);
1340
1341 /* read the first word(s) */
1342 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1343 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1344 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1345 memcpy(ret_buf, &val, 4);
1346
1347 /* advance to the next dword */
1348 offset += sizeof(u32);
1349 ret_buf += sizeof(u32);
1350 buf_size -= sizeof(u32);
1351 cmd_flags = 0;
1352 }
1353
1354 if (rc == 0) {
1355 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1356 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1357 memcpy(ret_buf, &val, 4);
1358 }
1359
1360 /* disable access to nvram interface */
1361 bnx2x_disable_nvram_access(bp);
1362 bnx2x_release_nvram_lock(bp);
1363
1364 return rc;
1365}
1366
1367static int bnx2x_get_eeprom(struct net_device *dev,
1368 struct ethtool_eeprom *eeprom, u8 *eebuf)
1369{
1370 struct bnx2x *bp = netdev_priv(dev);
1371 int rc;
1372
51c1a580
MS		 1373 if (!netif_running(dev)) {
1374 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1375 "cannot access eeprom when the interface is down\n");
de0c62db 1376 return -EAGAIN;
51c1a580 1377 }
de0c62db 1378
51c1a580 1379 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1380 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1381 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1382 eeprom->len, eeprom->len);
1383
1384 /* parameters already validated in ethtool_get_eeprom */
1385
1386 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1387
1388 return rc;
1389}
1390
24ea818e
YM		 1391static int bnx2x_get_module_eeprom(struct net_device *dev,
1392 struct ethtool_eeprom *ee,
1393 u8 *data)
1394{
1395 struct bnx2x *bp = netdev_priv(dev);
1396 int rc = 0, phy_idx;
1397 u8 *user_data = data;
1398 int remaining_len = ee->len, xfer_size;
1399 unsigned int page_off = ee->offset;
1400
1401 if (!netif_running(dev)) {
1402 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1403 "cannot access eeprom when the interface is down\n");
1404 return -EAGAIN;
1405 }
1406
1407 phy_idx = bnx2x_get_cur_phy_idx(bp);
1408 bnx2x_acquire_phy_lock(bp);
1409 while (!rc && remaining_len > 0) {
1410 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1411 SFP_EEPROM_PAGE_SIZE : remaining_len;
1412 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1413 &bp->link_params,
1414 page_off,
1415 xfer_size,
1416 user_data);
1417 remaining_len -= xfer_size;
1418 user_data += xfer_size;
1419 page_off += xfer_size;
1420 }
1421
1422 bnx2x_release_phy_lock(bp);
1423 return rc;
1424}
1425
1426static int bnx2x_get_module_info(struct net_device *dev,
1427 struct ethtool_modinfo *modinfo)
1428{
1429 struct bnx2x *bp = netdev_priv(dev);
1430 int phy_idx;
1431 if (!netif_running(dev)) {
1432 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1433 "cannot access eeprom when the interface is down\n");
1434 return -EAGAIN;
1435 }
1436
1437 phy_idx = bnx2x_get_cur_phy_idx(bp);
1438 switch (bp->link_params.phy[phy_idx].media_type) {
1439 case ETH_PHY_SFPP_10G_FIBER:
1440 case ETH_PHY_SFP_1G_FIBER:
1441 case ETH_PHY_DA_TWINAX:
1442 modinfo->type = ETH_MODULE_SFF_8079;
1443 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1444 return 0;
1445 default:
1446 return -EOPNOTSUPP;
1447 }
1448}
1449
de0c62db
DK		 1450static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1451 u32 cmd_flags)
1452{
1453 int count, i, rc;
1454
1455 /* build the command word */
1456 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1457
1458 /* need to clear DONE bit separately */
1459 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1460
1461 /* write the data */
1462 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1463
1464 /* address of the NVRAM to write to */
1465 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1466 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1467
1468 /* issue the write command */
1469 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1470
1471 /* adjust timeout for emulation/FPGA */
754a2f52 1472 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1473 if (CHIP_REV_IS_SLOW(bp))
1474 count *= 100;
1475
1476 /* wait for completion */
1477 rc = -EBUSY;
1478 for (i = 0; i < count; i++) {
1479 udelay(5);
1480 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1481 if (val & MCPR_NVM_COMMAND_DONE) {
1482 rc = 0;
1483 break;
1484 }
1485 }
1486
51c1a580
MS		 1487 if (rc == -EBUSY)
1488 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1489 "nvram write timeout expired\n");
de0c62db
DK		 1490 return rc;
1491}
1492
1493#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1494
1495static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1496 int buf_size)
1497{
1498 int rc;
1499 u32 cmd_flags;
1500 u32 align_offset;
1501 __be32 val;
1502
1503 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1504 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1505 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1506 offset, buf_size, bp->common.flash_size);
1507 return -EINVAL;
1508 }
1509
1510 /* request access to nvram interface */
1511 rc = bnx2x_acquire_nvram_lock(bp);
1512 if (rc)
1513 return rc;
1514
1515 /* enable access to nvram interface */
1516 bnx2x_enable_nvram_access(bp);
1517
1518 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1519 align_offset = (offset & ~0x03);
1520 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1521
1522 if (rc == 0) {
1523 val &= ~(0xff << BYTE_OFFSET(offset));
1524 val |= (*data_buf << BYTE_OFFSET(offset));
1525
1526 /* nvram data is returned as an array of bytes
07ba6af4
MS		 1527 * convert it back to cpu order
1528 */
de0c62db
DK		 1529 val = be32_to_cpu(val);
1530
1531 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1532 cmd_flags);
1533 }
1534
1535 /* disable access to nvram interface */
1536 bnx2x_disable_nvram_access(bp);
1537 bnx2x_release_nvram_lock(bp);
1538
1539 return rc;
1540}
1541
1542static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1543 int buf_size)
1544{
1545 int rc;
1546 u32 cmd_flags;
1547 u32 val;
1548 u32 written_so_far;
1549
1550 if (buf_size == 1) /* ethtool */
1551 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1552
1553 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1554 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1555 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1556 offset, buf_size);
1557 return -EINVAL;
1558 }
1559
1560 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1561 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1562 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1563 offset, buf_size, bp->common.flash_size);
1564 return -EINVAL;
1565 }
1566
1567 /* request access to nvram interface */
1568 rc = bnx2x_acquire_nvram_lock(bp);
1569 if (rc)
1570 return rc;
1571
1572 /* enable access to nvram interface */
1573 bnx2x_enable_nvram_access(bp);
1574
1575 written_so_far = 0;
1576 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1577 while ((written_so_far < buf_size) && (rc == 0)) {
1578 if (written_so_far == (buf_size - sizeof(u32)))
1579 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1580 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1581 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1582 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1583 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1584
1585 memcpy(&val, data_buf, 4);
1586
1587 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1588
1589 /* advance to the next dword */
1590 offset += sizeof(u32);
1591 data_buf += sizeof(u32);
1592 written_so_far += sizeof(u32);
1593 cmd_flags = 0;
1594 }
1595
1596 /* disable access to nvram interface */
1597 bnx2x_disable_nvram_access(bp);
1598 bnx2x_release_nvram_lock(bp);
1599
1600 return rc;
1601}
1602
1603static int bnx2x_set_eeprom(struct net_device *dev,
1604 struct ethtool_eeprom *eeprom, u8 *eebuf)
1605{
1606 struct bnx2x *bp = netdev_priv(dev);
1607 int port = BP_PORT(bp);
1608 int rc = 0;
e10bc84d 1609 u32 ext_phy_config;
51c1a580
MS		 1610 if (!netif_running(dev)) {
1611 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1612 "cannot access eeprom when the interface is down\n");
de0c62db 1613 return -EAGAIN;
51c1a580 1614 }
de0c62db 1615
51c1a580 1616 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1617 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1618 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1619 eeprom->len, eeprom->len);
1620
1621 /* parameters already validated in ethtool_set_eeprom */
1622
1623 /* PHY eeprom can be accessed only by the PMF */
1624 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1625 !bp->port.pmf) {
1626 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1627 "wrong magic or interface is not pmf\n");
de0c62db 1628 return -EINVAL;
51c1a580 1629 }
de0c62db 1630
e10bc84d
YR		 1631 ext_phy_config =
1632 SHMEM_RD(bp,
1633 dev_info.port_hw_config[port].external_phy_config);
1634
de0c62db
DK		 1635 if (eeprom->magic == 0x50485950) {
1636 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1637 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1638
1639 bnx2x_acquire_phy_lock(bp);
1640 rc |= bnx2x_link_reset(&bp->link_params,
1641 &bp->link_vars, 0);
e10bc84d 1642 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1643 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1644 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1645 MISC_REGISTERS_GPIO_HIGH, port);
1646 bnx2x_release_phy_lock(bp);
1647 bnx2x_link_report(bp);
1648
1649 } else if (eeprom->magic == 0x50485952) {
1650 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1651 if (bp->state == BNX2X_STATE_OPEN) {
1652 bnx2x_acquire_phy_lock(bp);
1653 rc |= bnx2x_link_reset(&bp->link_params,
1654 &bp->link_vars, 1);
1655
1656 rc |= bnx2x_phy_init(&bp->link_params,
1657 &bp->link_vars);
1658 bnx2x_release_phy_lock(bp);
1659 bnx2x_calc_fc_adv(bp);
1660 }
1661 } else if (eeprom->magic == 0x53985943) {
1662 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1663 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1664 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1665
1666 /* DSP Remove Download Mode */
1667 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1668 MISC_REGISTERS_GPIO_LOW, port);
1669
1670 bnx2x_acquire_phy_lock(bp);
1671
e10bc84d
YR		 1672 bnx2x_sfx7101_sp_sw_reset(bp,
1673 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1674
1675 /* wait 0.5 sec to allow it to run */
1676 msleep(500);
1677 bnx2x_ext_phy_hw_reset(bp, port);
1678 msleep(500);
1679 bnx2x_release_phy_lock(bp);
1680 }
1681 } else
1682 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1683
1684 return rc;
1685}
f85582f8 1686
de0c62db
DK		 1687static int bnx2x_get_coalesce(struct net_device *dev,
1688 struct ethtool_coalesce *coal)
1689{
1690 struct bnx2x *bp = netdev_priv(dev);
1691
1692 memset(coal, 0, sizeof(struct ethtool_coalesce));
1693
1694 coal->rx_coalesce_usecs = bp->rx_ticks;
1695 coal->tx_coalesce_usecs = bp->tx_ticks;
1696
1697 return 0;
1698}
1699
1700static int bnx2x_set_coalesce(struct net_device *dev,
1701 struct ethtool_coalesce *coal)
1702{
1703 struct bnx2x *bp = netdev_priv(dev);
1704
1705 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1706 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1707 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1708
1709 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1710 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1711 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1712
1713 if (netif_running(dev))
1714 bnx2x_update_coalesce(bp);
1715
1716 return 0;
1717}
1718
1719static void bnx2x_get_ringparam(struct net_device *dev,
1720 struct ethtool_ringparam *ering)
1721{
1722 struct bnx2x *bp = netdev_priv(dev);
1723
1724 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1725
25141580
DK		 1726 if (bp->rx_ring_size)
1727 ering->rx_pending = bp->rx_ring_size;
1728 else
c2188952 1729 ering->rx_pending = MAX_RX_AVAIL;
25141580 1730
a3348722 1731 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1732 ering->tx_pending = bp->tx_ring_size;
1733}
1734
1735static int bnx2x_set_ringparam(struct net_device *dev,
1736 struct ethtool_ringparam *ering)
1737{
1738 struct bnx2x *bp = netdev_priv(dev);
de0c62db 1739
04c46736
YM		 1740 DP(BNX2X_MSG_ETHTOOL,
1741 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1742 ering->rx_pending, ering->tx_pending);
1743
de0c62db 1744 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1745 DP(BNX2X_MSG_ETHTOOL,
1746 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1747 return -EAGAIN;
1748 }
1749
1750 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1751 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1752 MIN_RX_SIZE_TPA)) ||
a3348722 1753 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1754 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1755 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1756 return -EINVAL;
51c1a580 1757 }
de0c62db
DK		 1758
1759 bp->rx_ring_size = ering->rx_pending;
1760 bp->tx_ring_size = ering->tx_pending;
1761
a9fccec7 1762 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1763}
1764
1765static void bnx2x_get_pauseparam(struct net_device *dev,
1766 struct ethtool_pauseparam *epause)
1767{
1768 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1769 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1770 int cfg_reg;
1771
a22f0788
YR		 1772 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1773 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1774
9e7e8399 1775 if (!epause->autoneg)
241fb5d2 1776 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1777 else
1778 cfg_reg = bp->link_params.req_fc_auto_adv;
1779
1780 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1781 BNX2X_FLOW_CTRL_RX);
9e7e8399 1782 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1783 BNX2X_FLOW_CTRL_TX);
1784
51c1a580 1785 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1786 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1787 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1788}
1789
1790static int bnx2x_set_pauseparam(struct net_device *dev,
1791 struct ethtool_pauseparam *epause)
1792{
1793 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1794 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1795 if (IS_MF(bp))
de0c62db
DK		 1796 return 0;
1797
51c1a580 1798 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1799 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1800 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1801
a22f0788 1802 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1803
1804 if (epause->rx_pause)
a22f0788 1805 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1806
1807 if (epause->tx_pause)
a22f0788 1808 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1809
a22f0788
YR		 1810 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1811 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1812
1813 if (epause->autoneg) {
a22f0788 1814 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1815 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1816 return -EINVAL;
1817 }
1818
a22f0788
YR		 1819 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1820 bp->link_params.req_flow_ctrl[cfg_idx] =
1821 BNX2X_FLOW_CTRL_AUTO;
1822 }
5cd75f0c
YR		 1823 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1824 if (epause->rx_pause)
1825 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1826
1827 if (epause->tx_pause)
1828 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
de0c62db
DK		 1829 }
1830
51c1a580 1831 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1832 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1833
1834 if (netif_running(dev)) {
1835 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1836 bnx2x_link_set(bp);
1837 }
1838
1839 return 0;
1840}
1841
5889335c 1842static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
cf2c1df6
MS		 1843 "register_test (offline) ",
1844 "memory_test (offline) ",
1845 "int_loopback_test (offline)",
1846 "ext_loopback_test (offline)",
1847 "nvram_test (online) ",
1848 "interrupt_test (online) ",
1849 "link_test (online) "
de0c62db
DK		 1850};
1851
e9939c80
YM		 1852static u32 bnx2x_eee_to_adv(u32 eee_adv)
1853{
1854 u32 modes = 0;
1855
1856 if (eee_adv & SHMEM_EEE_100M_ADV)
1857 modes |= ADVERTISED_100baseT_Full;
1858 if (eee_adv & SHMEM_EEE_1G_ADV)
1859 modes |= ADVERTISED_1000baseT_Full;
1860 if (eee_adv & SHMEM_EEE_10G_ADV)
1861 modes |= ADVERTISED_10000baseT_Full;
1862
1863 return modes;
1864}
1865
1866static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1867{
1868 u32 eee_adv = 0;
1869 if (modes & ADVERTISED_100baseT_Full)
1870 eee_adv |= SHMEM_EEE_100M_ADV;
1871 if (modes & ADVERTISED_1000baseT_Full)
1872 eee_adv |= SHMEM_EEE_1G_ADV;
1873 if (modes & ADVERTISED_10000baseT_Full)
1874 eee_adv |= SHMEM_EEE_10G_ADV;
1875
1876 return eee_adv << shift;
1877}
1878
1879static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1880{
1881 struct bnx2x *bp = netdev_priv(dev);
1882 u32 eee_cfg;
1883
1884 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1885 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1886 return -EOPNOTSUPP;
1887 }
1888
08e9acc2 1889 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1890
1891 edata->supported =
1892 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1893 SHMEM_EEE_SUPPORTED_SHIFT);
1894
1895 edata->advertised =
1896 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1897 SHMEM_EEE_ADV_STATUS_SHIFT);
1898 edata->lp_advertised =
1899 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1900 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1901
1902 /* SHMEM value is in 16u units --> Convert to 1u units. */
1903 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1904
1905 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1906 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1907 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1908
1909 return 0;
1910}
1911
1912static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1913{
1914 struct bnx2x *bp = netdev_priv(dev);
1915 u32 eee_cfg;
1916 u32 advertised;
1917
1918 if (IS_MF(bp))
1919 return 0;
1920
1921 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1922 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1923 return -EOPNOTSUPP;
1924 }
1925
08e9acc2 1926 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1927
1928 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1929 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1930 return -EOPNOTSUPP;
1931 }
1932
1933 advertised = bnx2x_adv_to_eee(edata->advertised,
1934 SHMEM_EEE_ADV_STATUS_SHIFT);
1935 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1936 DP(BNX2X_MSG_ETHTOOL,
efc7ce03 1937 "Direct manipulation of EEE advertisement is not supported\n");
e9939c80
YM		 1938 return -EINVAL;
1939 }
1940
1941 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1942 DP(BNX2X_MSG_ETHTOOL,
1943 "Maximal Tx Lpi timer supported is %x(u)\n",
1944 EEE_MODE_TIMER_MASK);
1945 return -EINVAL;
1946 }
1947 if (edata->tx_lpi_enabled &&
1948 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1949 DP(BNX2X_MSG_ETHTOOL,
1950 "Minimal Tx Lpi timer supported is %d(u)\n",
1951 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1952 return -EINVAL;
1953 }
1954
1955 /* All is well; Apply changes*/
1956 if (edata->eee_enabled)
1957 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1958 else
1959 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1960
1961 if (edata->tx_lpi_enabled)
1962 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1963 else
1964 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1965
1966 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1967 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1968 EEE_MODE_TIMER_MASK) |
1969 EEE_MODE_OVERRIDE_NVRAM |
1970 EEE_MODE_OUTPUT_TIME;
1971
1972 /* Restart link to propogate changes */
1973 if (netif_running(dev)) {
1974 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1975 bnx2x_force_link_reset(bp);
e9939c80
YM		 1976 bnx2x_link_set(bp);
1977 }
1978
1979 return 0;
1980}
1981
619c5cb6
VZ		 1982enum {
1983 BNX2X_CHIP_E1_OFST = 0,
1984 BNX2X_CHIP_E1H_OFST,
1985 BNX2X_CHIP_E2_OFST,
1986 BNX2X_CHIP_E3_OFST,
1987 BNX2X_CHIP_E3B0_OFST,
1988 BNX2X_CHIP_MAX_OFST
1989};
1990
1991#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1992#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1993#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1994#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1995#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1996
1997#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1998#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1999
de0c62db
DK		 2000static int bnx2x_test_registers(struct bnx2x *bp)
2001{
2002 int idx, i, rc = -ENODEV;
619c5cb6 2003 u32 wr_val = 0, hw;
de0c62db
DK		 2004 int port = BP_PORT(bp);
2005 static const struct {
619c5cb6 2006 u32 hw;
de0c62db
DK		 2007 u32 offset0;
2008 u32 offset1;
2009 u32 mask;
2010 } reg_tbl[] = {
619c5cb6
VZ		 2011/* 0 */ { BNX2X_CHIP_MASK_ALL,
2012 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2013 { BNX2X_CHIP_MASK_ALL,
2014 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2015 { BNX2X_CHIP_MASK_E1X,
2016 HC_REG_AGG_INT_0, 4, 0x000003ff },
2017 { BNX2X_CHIP_MASK_ALL,
2018 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2019 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2020 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2021 { BNX2X_CHIP_MASK_E3B0,
2022 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2023 { BNX2X_CHIP_MASK_ALL,
2024 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2025 { BNX2X_CHIP_MASK_ALL,
2026 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2027 { BNX2X_CHIP_MASK_ALL,
2028 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2029 { BNX2X_CHIP_MASK_ALL,
2030 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2031/* 10 */ { BNX2X_CHIP_MASK_ALL,
2032 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2033 { BNX2X_CHIP_MASK_ALL,
2034 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2035 { BNX2X_CHIP_MASK_ALL,
2036 QM_REG_CONNNUM_0, 4, 0x000fffff },
2037 { BNX2X_CHIP_MASK_ALL,
2038 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2039 { BNX2X_CHIP_MASK_ALL,
2040 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2041 { BNX2X_CHIP_MASK_ALL,
2042 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2043 { BNX2X_CHIP_MASK_ALL,
2044 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2045 { BNX2X_CHIP_MASK_ALL,
2046 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2047 { BNX2X_CHIP_MASK_ALL,
2048 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2049 { BNX2X_CHIP_MASK_ALL,
2050 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2051/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2052 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2053 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2054 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2055 { BNX2X_CHIP_MASK_ALL,
2056 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2057 { BNX2X_CHIP_MASK_ALL,
2058 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2059 { BNX2X_CHIP_MASK_ALL,
2060 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2061 { BNX2X_CHIP_MASK_ALL,
2062 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2063 { BNX2X_CHIP_MASK_ALL,
2064 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2065 { BNX2X_CHIP_MASK_ALL,
2066 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2067 { BNX2X_CHIP_MASK_ALL,
2068 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2069 { BNX2X_CHIP_MASK_ALL,
2070 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2071/* 30 */ { BNX2X_CHIP_MASK_ALL,
2072 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2073 { BNX2X_CHIP_MASK_ALL,
2074 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2075 { BNX2X_CHIP_MASK_ALL,
2076 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2077 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2078 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2079 { BNX2X_CHIP_MASK_ALL,
2080 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2081 { BNX2X_CHIP_MASK_ALL,
2082 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2083 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2084 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2085 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2086 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2087
2088 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 2089 };
2090
51c1a580
MS		 2091 if (!netif_running(bp->dev)) {
2092 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2093 "cannot access eeprom when the interface is down\n");
de0c62db 2094 return rc;
51c1a580 2095 }
de0c62db 2096
619c5cb6
VZ		 2097 if (CHIP_IS_E1(bp))
2098 hw = BNX2X_CHIP_MASK_E1;
2099 else if (CHIP_IS_E1H(bp))
2100 hw = BNX2X_CHIP_MASK_E1H;
2101 else if (CHIP_IS_E2(bp))
2102 hw = BNX2X_CHIP_MASK_E2;
2103 else if (CHIP_IS_E3B0(bp))
2104 hw = BNX2X_CHIP_MASK_E3B0;
2105 else /* e3 A0 */
2106 hw = BNX2X_CHIP_MASK_E3;
2107
de0c62db 2108 /* Repeat the test twice:
07ba6af4
MS		 2109 * First by writing 0x00000000, second by writing 0xffffffff
2110 */
de0c62db
DK		 2111 for (idx = 0; idx < 2; idx++) {
2112
2113 switch (idx) {
2114 case 0:
2115 wr_val = 0;
2116 break;
2117 case 1:
2118 wr_val = 0xffffffff;
2119 break;
2120 }
2121
2122 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2123 u32 offset, mask, save_val, val;
619c5cb6 2124 if (!(hw & reg_tbl[i].hw))
f2e0899f 2125 continue;
de0c62db
DK		 2126
2127 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2128 mask = reg_tbl[i].mask;
2129
2130 save_val = REG_RD(bp, offset);
2131
ec6ba945 2132 REG_WR(bp, offset, wr_val & mask);
f85582f8 2133
de0c62db
DK		 2134 val = REG_RD(bp, offset);
2135
2136 /* Restore the original register's value */
2137 REG_WR(bp, offset, save_val);
2138
2139 /* verify value is as expected */
2140 if ((val & mask) != (wr_val & mask)) {
51c1a580 2141 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2142 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2143 offset, val, wr_val, mask);
2144 goto test_reg_exit;
2145 }
2146 }
2147 }
2148
2149 rc = 0;
2150
2151test_reg_exit:
2152 return rc;
2153}
2154
2155static int bnx2x_test_memory(struct bnx2x *bp)
2156{
2157 int i, j, rc = -ENODEV;
619c5cb6 2158 u32 val, index;
de0c62db
DK		 2159 static const struct {
2160 u32 offset;
2161 int size;
2162 } mem_tbl[] = {
2163 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2164 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2165 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2166 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2167 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2168 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2169 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2170
2171 { 0xffffffff, 0 }
2172 };
619c5cb6 2173
de0c62db
DK		 2174 static const struct {
2175 char *name;
2176 u32 offset;
619c5cb6 2177 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 2178 } prty_tbl[] = {
619c5cb6
VZ		 2179 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2180 {0x3ffc0, 0, 0, 0} },
2181 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2182 {0x2, 0x2, 0, 0} },
2183 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2184 {0, 0, 0, 0} },
2185 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2186 {0x3ffc0, 0, 0, 0} },
2187 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2188 {0x3ffc0, 0, 0, 0} },
2189 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2190 {0x3ffc1, 0, 0, 0} },
2191
2192 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 2193 };
2194
51c1a580
MS		 2195 if (!netif_running(bp->dev)) {
2196 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2197 "cannot access eeprom when the interface is down\n");
de0c62db 2198 return rc;
51c1a580 2199 }
de0c62db 2200
619c5cb6
VZ		 2201 if (CHIP_IS_E1(bp))
2202 index = BNX2X_CHIP_E1_OFST;
2203 else if (CHIP_IS_E1H(bp))
2204 index = BNX2X_CHIP_E1H_OFST;
2205 else if (CHIP_IS_E2(bp))
2206 index = BNX2X_CHIP_E2_OFST;
2207 else /* e3 */
2208 index = BNX2X_CHIP_E3_OFST;
2209
f2e0899f
DK		 2210 /* pre-Check the parity status */
2211 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2212 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2213 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2214 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 2215 "%s is 0x%x\n", prty_tbl[i].name, val);
2216 goto test_mem_exit;
2217 }
2218 }
2219
de0c62db
DK		 2220 /* Go through all the memories */
2221 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2222 for (j = 0; j < mem_tbl[i].size; j++)
2223 REG_RD(bp, mem_tbl[i].offset + j*4);
2224
2225 /* Check the parity status */
2226 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2227 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2228 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2229 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2230 "%s is 0x%x\n", prty_tbl[i].name, val);
2231 goto test_mem_exit;
2232 }
2233 }
2234
2235 rc = 0;
2236
2237test_mem_exit:
2238 return rc;
2239}
2240
a22f0788 2241static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 2242{
f2e0899f 2243 int cnt = 1400;
de0c62db 2244
619c5cb6 2245 if (link_up) {
a22f0788 2246 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 2247 msleep(20);
2248
2249 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 2250 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 2251
2252 cnt = 1400;
2253 while (!bp->link_vars.link_up && cnt--)
2254 msleep(20);
2255
2256 if (cnt <= 0 && !bp->link_vars.link_up)
2257 DP(BNX2X_MSG_ETHTOOL,
2258 "Timeout waiting for link init\n");
619c5cb6 2259 }
de0c62db
DK		 2260}
2261
619c5cb6 2262static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 2263{
2264 unsigned int pkt_size, num_pkts, i;
2265 struct sk_buff *skb;
2266 unsigned char *packet;
2267 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2268 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 2269 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 2270 u16 tx_start_idx, tx_idx;
2271 u16 rx_start_idx, rx_idx;
b0700b1e 2272 u16 pkt_prod, bd_prod;
de0c62db
DK		 2273 struct sw_tx_bd *tx_buf;
2274 struct eth_tx_start_bd *tx_start_bd;
de0c62db
DK		 2275 dma_addr_t mapping;
2276 union eth_rx_cqe *cqe;
619c5cb6 2277 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 2278 struct sw_rx_bd *rx_buf;
2279 u16 len;
2280 int rc = -ENODEV;
e52fcb24 2281 u8 *data;
8970b2e4
MS		 2282 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2283 txdata->txq_index);
de0c62db
DK		 2284
2285 /* check the loopback mode */
2286 switch (loopback_mode) {
2287 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 2288 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2289 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 2290 return -EINVAL;
8970b2e4 2291 }
de0c62db
DK		 2292 break;
2293 case BNX2X_MAC_LOOPBACK:
32911333
YR		 2294 if (CHIP_IS_E3(bp)) {
2295 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2296 if (bp->port.supported[cfg_idx] &
2297 (SUPPORTED_10000baseT_Full |
2298 SUPPORTED_20000baseMLD2_Full |
2299 SUPPORTED_20000baseKR2_Full))
2300 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2301 else
2302 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2303 } else
2304 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2305
de0c62db
DK		 2306 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2307 break;
8970b2e4
MS		 2308 case BNX2X_EXT_LOOPBACK:
2309 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2310 DP(BNX2X_MSG_ETHTOOL,
2311 "Can't configure external loopback\n");
2312 return -EINVAL;
2313 }
2314 break;
de0c62db 2315 default:
51c1a580 2316 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2317 return -EINVAL;
2318 }
2319
2320 /* prepare the loopback packet */
2321 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2322 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2323 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2324 if (!skb) {
51c1a580 2325 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2326 rc = -ENOMEM;
2327 goto test_loopback_exit;
2328 }
2329 packet = skb_put(skb, pkt_size);
2330 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2331 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2332 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2333 for (i = ETH_HLEN; i < pkt_size; i++)
2334 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2335 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2336 skb_headlen(skb), DMA_TO_DEVICE);
2337 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2338 rc = -ENOMEM;
2339 dev_kfree_skb(skb);
51c1a580 2340 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2341 goto test_loopback_exit;
2342 }
de0c62db
DK		 2343
2344 /* send the loopback packet */
2345 num_pkts = 0;
6383c0b3 2346 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2347 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2348
73dbb5e1
DK		 2349 netdev_tx_sent_queue(txq, skb->len);
2350
6383c0b3
AE		 2351 pkt_prod = txdata->tx_pkt_prod++;
2352 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2353 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2354 tx_buf->skb = skb;
2355 tx_buf->flags = 0;
2356
6383c0b3
AE		 2357 bd_prod = TX_BD(txdata->tx_bd_prod);
2358 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2359 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2360 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2361 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2362 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2363 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2364 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2365 SET_FLAG(tx_start_bd->general_data,
2366 ETH_TX_START_BD_HDR_NBDS,
2367 1);
96bed4b9
YM		 2368 SET_FLAG(tx_start_bd->general_data,
2369 ETH_TX_START_BD_PARSE_NBDS,
2370 0);
de0c62db
DK		 2371
2372 /* turn on parsing and get a BD */
2373 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2374
96bed4b9
YM		 2375 if (CHIP_IS_E1x(bp)) {
2376 u16 global_data = 0;
2377 struct eth_tx_parse_bd_e1x *pbd_e1x =
2378 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2379 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2380 SET_FLAG(global_data,
2381 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2382 pbd_e1x->global_data = cpu_to_le16(global_data);
2383 } else {
2384 u32 parsing_data = 0;
2385 struct eth_tx_parse_bd_e2 *pbd_e2 =
2386 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2387 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2388 SET_FLAG(parsing_data,
2389 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2390 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2391 }
de0c62db
DK		 2392 wmb();
2393
6383c0b3 2394 txdata->tx_db.data.prod += 2;
de0c62db 2395 barrier();
6383c0b3 2396 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2397
2398 mmiowb();
619c5cb6 2399 barrier();
de0c62db
DK		 2400
2401 num_pkts++;
6383c0b3 2402 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2403
2404 udelay(100);
2405
6383c0b3 2406 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2407 if (tx_idx != tx_start_idx + num_pkts)
2408 goto test_loopback_exit;
2409
f2e0899f
DK		 2410 /* Unlike HC IGU won't generate an interrupt for status block
2411 * updates that have been performed while interrupts were
2412 * disabled.
2413 */
e1210d12
ED		 2414 if (bp->common.int_block == INT_BLOCK_IGU) {
2415 /* Disable local BHes to prevent a dead-lock situation between
2416 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2417 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2418 */
2419 local_bh_disable();
6383c0b3 2420 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2421 local_bh_enable();
2422 }
f2e0899f 2423
de0c62db
DK		 2424 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2425 if (rx_idx != rx_start_idx + num_pkts)
2426 goto test_loopback_exit;
2427
b0700b1e 2428 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2429 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2430 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2431 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2432 goto test_loopback_rx_exit;
2433
621b4d66 2434 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2435 if (len != pkt_size)
2436 goto test_loopback_rx_exit;
2437
2438 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2439 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2440 dma_unmap_addr(rx_buf, mapping),
2441 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2442 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2443 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2444 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2445 goto test_loopback_rx_exit;
2446
2447 rc = 0;
2448
2449test_loopback_rx_exit:
2450
2451 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2452 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2453 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2454 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2455
2456 /* Update producers */
2457 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2458 fp_rx->rx_sge_prod);
2459
2460test_loopback_exit:
2461 bp->link_params.loopback_mode = LOOPBACK_NONE;
2462
2463 return rc;
2464}
2465
619c5cb6 2466static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2467{
2468 int rc = 0, res;
2469
2470 if (BP_NOMCP(bp))
2471 return rc;
2472
2473 if (!netif_running(bp->dev))
2474 return BNX2X_LOOPBACK_FAILED;
2475
2476 bnx2x_netif_stop(bp, 1);
2477 bnx2x_acquire_phy_lock(bp);
2478
619c5cb6 2479 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2480 if (res) {
51c1a580 2481 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2482 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2483 }
2484
619c5cb6 2485 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2486 if (res) {
51c1a580 2487 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2488 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2489 }
2490
2491 bnx2x_release_phy_lock(bp);
2492 bnx2x_netif_start(bp);
2493
2494 return rc;
2495}
2496
8970b2e4
MS		 2497static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2498{
2499 int rc;
2500 u8 is_serdes =
2501 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2502
2503 if (BP_NOMCP(bp))
2504 return -ENODEV;
2505
2506 if (!netif_running(bp->dev))
2507 return BNX2X_EXT_LOOPBACK_FAILED;
2508
5d07d868 2509 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
8970b2e4
MS		 2510 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2511 if (rc) {
2512 DP(BNX2X_MSG_ETHTOOL,
2513 "Can't perform self-test, nic_load (for external lb) failed\n");
2514 return -ENODEV;
2515 }
2516 bnx2x_wait_for_link(bp, 1, is_serdes);
2517
2518 bnx2x_netif_stop(bp, 1);
2519
2520 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2521 if (rc)
2522 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2523
2524 bnx2x_netif_start(bp);
2525
2526 return rc;
2527}
2528
de0c62db
DK		 2529#define CRC32_RESIDUAL 0xdebb20e3
2530
2531static int bnx2x_test_nvram(struct bnx2x *bp)
2532{
2533 static const struct {
2534 int offset;
2535 int size;
2536 } nvram_tbl[] = {
2537 { 0, 0x14 }, /* bootstrap */
2538 { 0x14, 0xec }, /* dir */
2539 { 0x100, 0x350 }, /* manuf_info */
2540 { 0x450, 0xf0 }, /* feature_info */
2541 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2542 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2543 { 0, 0 }
2544 };
afa13b4b
MY		 2545 __be32 *buf;
2546 u8 *data;
de0c62db
DK		 2547 int i, rc;
2548 u32 magic, crc;
2549
2550 if (BP_NOMCP(bp))
2551 return 0;
2552
afa13b4b
MY		 2553 buf = kmalloc(0x350, GFP_KERNEL);
2554 if (!buf) {
51c1a580 2555 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2556 rc = -ENOMEM;
2557 goto test_nvram_exit;
2558 }
2559 data = (u8 *)buf;
2560
de0c62db
DK		 2561 rc = bnx2x_nvram_read(bp, 0, data, 4);
2562 if (rc) {
51c1a580
MS		 2563 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2564 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2565 goto test_nvram_exit;
2566 }
2567
2568 magic = be32_to_cpu(buf[0]);
2569 if (magic != 0x669955aa) {
51c1a580
MS		 2570 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2571 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2572 rc = -ENODEV;
2573 goto test_nvram_exit;
2574 }
2575
2576 for (i = 0; nvram_tbl[i].size; i++) {
2577
2578 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2579 nvram_tbl[i].size);
2580 if (rc) {
51c1a580 2581 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2582 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2583 goto test_nvram_exit;
2584 }
2585
2586 crc = ether_crc_le(nvram_tbl[i].size, data);
2587 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2588 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2589 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2590 rc = -ENODEV;
2591 goto test_nvram_exit;
2592 }
2593 }
2594
2595test_nvram_exit:
afa13b4b 2596 kfree(buf);
de0c62db
DK		 2597 return rc;
2598}
2599
619c5cb6 2600/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2601static int bnx2x_test_intr(struct bnx2x *bp)
2602{
3b603066 2603 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2604
51c1a580
MS		 2605 if (!netif_running(bp->dev)) {
2606 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2607 "cannot access eeprom when the interface is down\n");
de0c62db 2608 return -ENODEV;
51c1a580 2609 }
de0c62db 2610
15192a8c 2611 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2612 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2613
619c5cb6
VZ		 2614 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2615
2616 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2617}
2618
2619static void bnx2x_self_test(struct net_device *dev,
2620 struct ethtool_test *etest, u64 *buf)
2621{
2622 struct bnx2x *bp = netdev_priv(dev);
a336ca7c
YR		 2623 u8 is_serdes, link_up;
2624 int rc, cnt = 0;
cf2c1df6 2625
de0c62db 2626 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2627 netdev_err(bp->dev,
2628 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2629 etest->flags |= ETH_TEST_FL_FAILED;
2630 return;
2631 }
2de67439 2632
8970b2e4
MS		 2633 DP(BNX2X_MSG_ETHTOOL,
2634 "Self-test command parameters: offline = %d, external_lb = %d\n",
2635 (etest->flags & ETH_TEST_FL_OFFLINE),
2636 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2637
cf2c1df6 2638 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2639
cf2c1df6
MS		 2640 if (!netif_running(dev)) {
2641 DP(BNX2X_MSG_ETHTOOL,
2642 "Can't perform self-test when interface is down\n");
de0c62db 2643 return;
cf2c1df6 2644 }
de0c62db 2645
a22f0788 2646 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
a336ca7c 2647 link_up = bp->link_vars.link_up;
cf2c1df6
MS		 2648 /* offline tests are not supported in MF mode */
2649 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2650 int port = BP_PORT(bp);
2651 u32 val;
de0c62db
DK		 2652
2653 /* save current value of input enable for TX port IF */
2654 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2655 /* disable input for TX port IF */
2656 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2657
5d07d868 2658 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
cf2c1df6
MS		 2659 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2660 if (rc) {
2661 etest->flags |= ETH_TEST_FL_FAILED;
2662 DP(BNX2X_MSG_ETHTOOL,
2663 "Can't perform self-test, nic_load (for offline) failed\n");
2664 return;
2665 }
2666
de0c62db 2667 /* wait until link state is restored */
619c5cb6 2668 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2669
2670 if (bnx2x_test_registers(bp) != 0) {
2671 buf[0] = 1;
2672 etest->flags |= ETH_TEST_FL_FAILED;
2673 }
2674 if (bnx2x_test_memory(bp) != 0) {
2675 buf[1] = 1;
2676 etest->flags |= ETH_TEST_FL_FAILED;
2677 }
f85582f8 2678
8970b2e4 2679 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2680 if (buf[2] != 0)
2681 etest->flags |= ETH_TEST_FL_FAILED;
2682
8970b2e4
MS		 2683 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2684 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2685 if (buf[3] != 0)
2686 etest->flags |= ETH_TEST_FL_FAILED;
2687 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2688 }
2689
5d07d868 2690 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
de0c62db
DK		 2691
2692 /* restore input for TX port IF */
2693 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2694 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2695 if (rc) {
2696 etest->flags |= ETH_TEST_FL_FAILED;
2697 DP(BNX2X_MSG_ETHTOOL,
2698 "Can't perform self-test, nic_load (for online) failed\n");
2699 return;
2700 }
de0c62db 2701 /* wait until link state is restored */
a22f0788 2702 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2703 }
2704 if (bnx2x_test_nvram(bp) != 0) {
cf2c1df6
MS		 2705 if (!IS_MF(bp))
2706 buf[4] = 1;
2707 else
2708 buf[0] = 1;
de0c62db
DK		 2709 etest->flags |= ETH_TEST_FL_FAILED;
2710 }
2711 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 2712 if (!IS_MF(bp))
2713 buf[5] = 1;
2714 else
2715 buf[1] = 1;
de0c62db
DK		 2716 etest->flags |= ETH_TEST_FL_FAILED;
2717 }
633ac363 2718
a336ca7c
YR		 2719 if (link_up) {
2720 cnt = 100;
2721 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2722 msleep(20);
2723 }
2724
2725 if (!cnt) {
cf2c1df6
MS		 2726 if (!IS_MF(bp))
2727 buf[6] = 1;
2728 else
2729 buf[2] = 1;
633ac363
DK		 2730 etest->flags |= ETH_TEST_FL_FAILED;
2731 }
de0c62db
DK		 2732}
2733
de0c62db
DK		 2734#define IS_PORT_STAT(i) \
2735 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2736#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2737#define IS_MF_MODE_STAT(bp) \
2738 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2739
619c5cb6
VZ		 2740/* ethtool statistics are displayed for all regular ethernet queues and the
2741 * fcoe L2 queue if not disabled
2742 */
1191cb83 2743static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2744{
2745 return BNX2X_NUM_ETH_QUEUES(bp);
2746}
2747
de0c62db
DK		 2748static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2749{
2750 struct bnx2x *bp = netdev_priv(dev);
2751 int i, num_stats;
2752
2753 switch (stringset) {
2754 case ETH_SS_STATS:
2755 if (is_multi(bp)) {
619c5cb6 2756 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2757 BNX2X_NUM_Q_STATS;
2758 } else
2759 num_stats = 0;
2760 if (IS_MF_MODE_STAT(bp)) {
2761 for (i = 0; i < BNX2X_NUM_STATS; i++)
2762 if (IS_FUNC_STAT(i))
2763 num_stats++;
2764 } else
2765 num_stats += BNX2X_NUM_STATS;
2766
de0c62db
DK		 2767 return num_stats;
2768
2769 case ETH_SS_TEST:
cf2c1df6 2770 return BNX2X_NUM_TESTS(bp);
de0c62db
DK		 2771
2772 default:
2773 return -EINVAL;
2774 }
2775}
2776
2777static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2778{
2779 struct bnx2x *bp = netdev_priv(dev);
5889335c 2780 int i, j, k, start;
ec6ba945 2781 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2782
2783 switch (stringset) {
2784 case ETH_SS_STATS:
d5e83632 2785 k = 0;
de0c62db 2786 if (is_multi(bp)) {
619c5cb6 2787 for_each_eth_queue(bp, i) {
ec6ba945 2788 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2789 sprintf(queue_name, "%d", i);
de0c62db 2790 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2791 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2792 ETH_GSTRING_LEN,
2793 bnx2x_q_stats_arr[j].string,
2794 queue_name);
de0c62db
DK		 2795 k += BNX2X_NUM_Q_STATS;
2796 }
de0c62db 2797 }
d5e83632
YM		 2798
2799
2800 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2801 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2802 continue;
2803 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2804 bnx2x_stats_arr[i].string);
2805 j++;
2806 }
2807
de0c62db
DK		 2808 break;
2809
2810 case ETH_SS_TEST:
cf2c1df6
MS		 2811 /* First 4 tests cannot be done in MF mode */
2812 if (!IS_MF(bp))
2813 start = 0;
2814 else
2815 start = 4;
5889335c
MS		 2816 memcpy(buf, bnx2x_tests_str_arr + start,
2817 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
de0c62db
DK		 2818 }
2819}
2820
2821static void bnx2x_get_ethtool_stats(struct net_device *dev,
2822 struct ethtool_stats *stats, u64 *buf)
2823{
2824 struct bnx2x *bp = netdev_priv(dev);
2825 u32 *hw_stats, *offset;
d5e83632 2826 int i, j, k = 0;
de0c62db
DK		 2827
2828 if (is_multi(bp)) {
619c5cb6 2829 for_each_eth_queue(bp, i) {
15192a8c 2830 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 2831 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2832 if (bnx2x_q_stats_arr[j].size == 0) {
2833 /* skip this counter */
2834 buf[k + j] = 0;
2835 continue;
2836 }
2837 offset = (hw_stats +
2838 bnx2x_q_stats_arr[j].offset);
2839 if (bnx2x_q_stats_arr[j].size == 4) {
2840 /* 4-byte counter */
2841 buf[k + j] = (u64) *offset;
2842 continue;
2843 }
2844 /* 8-byte counter */
2845 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2846 }
2847 k += BNX2X_NUM_Q_STATS;
2848 }
d5e83632
YM		 2849 }
2850
2851 hw_stats = (u32 *)&bp->eth_stats;
2852 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2853 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2854 continue;
2855 if (bnx2x_stats_arr[i].size == 0) {
2856 /* skip this counter */
2857 buf[k + j] = 0;
2858 j++;
2859 continue;
de0c62db 2860 }
d5e83632
YM		 2861 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2862 if (bnx2x_stats_arr[i].size == 4) {
2863 /* 4-byte counter */
2864 buf[k + j] = (u64) *offset;
de0c62db 2865 j++;
d5e83632 2866 continue;
de0c62db 2867 }
d5e83632
YM		 2868 /* 8-byte counter */
2869 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2870 j++;
de0c62db
DK		 2871 }
2872}
2873
32d36134 2874static int bnx2x_set_phys_id(struct net_device *dev,
2875 enum ethtool_phys_id_state state)
de0c62db
DK		 2876{
2877 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2878
51c1a580
MS		 2879 if (!netif_running(dev)) {
2880 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2881 "cannot access eeprom when the interface is down\n");
32d36134 2882 return -EAGAIN;
51c1a580 2883 }
de0c62db 2884
51c1a580
MS		 2885 if (!bp->port.pmf) {
2886 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2887 return -EOPNOTSUPP;
51c1a580 2888 }
de0c62db 2889
32d36134 2890 switch (state) {
2891 case ETHTOOL_ID_ACTIVE:
fce55922 2892 return 1; /* cycle on/off once per second */
de0c62db 2893
32d36134 2894 case ETHTOOL_ID_ON:
8203c4b6 2895 bnx2x_acquire_phy_lock(bp);
32d36134 2896 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2897 LED_MODE_ON, SPEED_1000);
8203c4b6 2898 bnx2x_release_phy_lock(bp);
32d36134 2899 break;
de0c62db 2900
32d36134 2901 case ETHTOOL_ID_OFF:
8203c4b6 2902 bnx2x_acquire_phy_lock(bp);
32d36134 2903 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2904 LED_MODE_FRONT_PANEL_OFF, 0);
8203c4b6 2905 bnx2x_release_phy_lock(bp);
32d36134 2906 break;
2907
2908 case ETHTOOL_ID_INACTIVE:
8203c4b6 2909 bnx2x_acquire_phy_lock(bp);
e1943424
DM		 2910 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2911 LED_MODE_OPER,
2912 bp->link_vars.line_speed);
8203c4b6 2913 bnx2x_release_phy_lock(bp);
32d36134 2914 }
de0c62db
DK		 2915
2916 return 0;
2917}
2918
5d317c6a
MS		 2919static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2920{
2921
2922 switch (info->flow_type) {
2923 case TCP_V4_FLOW:
2924 case TCP_V6_FLOW:
2925 info->data = RXH_IP_SRC | RXH_IP_DST |
2926 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2927 break;
2928 case UDP_V4_FLOW:
2929 if (bp->rss_conf_obj.udp_rss_v4)
2930 info->data = RXH_IP_SRC | RXH_IP_DST |
2931 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2932 else
2933 info->data = RXH_IP_SRC | RXH_IP_DST;
2934 break;
2935 case UDP_V6_FLOW:
2936 if (bp->rss_conf_obj.udp_rss_v6)
2937 info->data = RXH_IP_SRC | RXH_IP_DST |
2938 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2939 else
2940 info->data = RXH_IP_SRC | RXH_IP_DST;
2941 break;
2942 case IPV4_FLOW:
2943 case IPV6_FLOW:
2944 info->data = RXH_IP_SRC | RXH_IP_DST;
2945 break;
2946 default:
2947 info->data = 0;
2948 break;
2949 }
2950
2951 return 0;
2952}
2953
ab532cf3 2954static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2955 u32 *rules __always_unused)
ab532cf3
TH		 2956{
2957 struct bnx2x *bp = netdev_priv(dev);
2958
2959 switch (info->cmd) {
2960 case ETHTOOL_GRXRINGS:
2961 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2962 return 0;
5d317c6a
MS		 2963 case ETHTOOL_GRXFH:
2964 return bnx2x_get_rss_flags(bp, info);
2965 default:
2966 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2967 return -EOPNOTSUPP;
2968 }
2969}
2970
2971static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2972{
2973 int udp_rss_requested;
2974
2975 DP(BNX2X_MSG_ETHTOOL,
2976 "Set rss flags command parameters: flow type = %d, data = %llu\n",
2977 info->flow_type, info->data);
2978
2979 switch (info->flow_type) {
2980 case TCP_V4_FLOW:
2981 case TCP_V6_FLOW:
2982 /* For TCP only 4-tupple hash is supported */
2983 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2984 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2985 DP(BNX2X_MSG_ETHTOOL,
2986 "Command parameters not supported\n");
2987 return -EINVAL;
5d317c6a 2988 }
2de67439 2989 return 0;
5d317c6a
MS		 2990
2991 case UDP_V4_FLOW:
2992 case UDP_V6_FLOW:
2993 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2994 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2de67439 2995 RXH_L4_B_0_1 | RXH_L4_B_2_3))
5d317c6a
MS		 2996 udp_rss_requested = 1;
2997 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2998 udp_rss_requested = 0;
2999 else
3000 return -EINVAL;
3001 if ((info->flow_type == UDP_V4_FLOW) &&
3002 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3003 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3004 DP(BNX2X_MSG_ETHTOOL,
3005 "rss re-configured, UDP 4-tupple %s\n",
3006 udp_rss_requested ? "enabled" : "disabled");
3007 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3008 } else if ((info->flow_type == UDP_V6_FLOW) &&
3009 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3010 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
5d317c6a
MS		 3011 DP(BNX2X_MSG_ETHTOOL,
3012 "rss re-configured, UDP 4-tupple %s\n",
3013 udp_rss_requested ? "enabled" : "disabled");
337da3e3 3014 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
5d317c6a 3015 }
924d75ab
YM		 3016 return 0;
3017
5d317c6a
MS		 3018 case IPV4_FLOW:
3019 case IPV6_FLOW:
3020 /* For IP only 2-tupple hash is supported */
3021 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3022 DP(BNX2X_MSG_ETHTOOL,
3023 "Command parameters not supported\n");
3024 return -EINVAL;
5d317c6a 3025 }
924d75ab
YM		 3026 return 0;
3027
5d317c6a
MS		 3028 case SCTP_V4_FLOW:
3029 case AH_ESP_V4_FLOW:
3030 case AH_V4_FLOW:
3031 case ESP_V4_FLOW:
3032 case SCTP_V6_FLOW:
3033 case AH_ESP_V6_FLOW:
3034 case AH_V6_FLOW:
3035 case ESP_V6_FLOW:
3036 case IP_USER_FLOW:
3037 case ETHER_FLOW:
3038 /* RSS is not supported for these protocols */
3039 if (info->data) {
3040 DP(BNX2X_MSG_ETHTOOL,
3041 "Command parameters not supported\n");
3042 return -EINVAL;
5d317c6a 3043 }
924d75ab
YM		 3044 return 0;
3045
5d317c6a
MS		 3046 default:
3047 return -EINVAL;
3048 }
3049}
3050
3051static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3052{
3053 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 3054
5d317c6a
MS		 3055 switch (info->cmd) {
3056 case ETHTOOL_SRXFH:
3057 return bnx2x_set_rss_flags(bp, info);
ab532cf3 3058 default:
51c1a580 3059 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 3060 return -EOPNOTSUPP;
3061 }
3062}
3063
7850f63f
BH		 3064static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3065{
96305234 3066 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 3067}
3068
3069static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 3070{
3071 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 3072 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3073 size_t i;
ab532cf3 3074
619c5cb6
VZ		 3075 /* Get the current configuration of the RSS indirection table */
3076 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3077
3078 /*
3079 * We can't use a memcpy() as an internal storage of an
3080 * indirection table is a u8 array while indir->ring_index
3081 * points to an array of u32.
3082 *
3083 * Indirection table contains the FW Client IDs, so we need to
3084 * align the returned table to the Client ID of the leading RSS
3085 * queue.
3086 */
7850f63f
BH		 3087 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3088 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 3089
ab532cf3
TH		 3090 return 0;
3091}
3092
7850f63f 3093static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 3094{
3095 struct bnx2x *bp = netdev_priv(dev);
3096 size_t i;
619c5cb6
VZ		 3097
3098 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 3099 /*
3100 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3101 * as an internal storage of an indirection table is a u8 array
3102 * while indir->ring_index points to an array of u32.
3103 *
3104 * Indirection table contains the FW Client IDs, so we need to
3105 * align the received table to the Client ID of the leading RSS
3106 * queue
3107 */
5d317c6a 3108 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 3109 }
ab532cf3 3110
5d317c6a 3111 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 3112}
3113
0e8d2ec5
MS		 3114/**
3115 * bnx2x_get_channels - gets the number of RSS queues.
3116 *
3117 * @dev: net device
3118 * @channels: returns the number of max / current queues
3119 */
3120static void bnx2x_get_channels(struct net_device *dev,
3121 struct ethtool_channels *channels)
3122{
3123 struct bnx2x *bp = netdev_priv(dev);
3124
3125 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3126 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3127}
3128
3129/**
3130 * bnx2x_change_num_queues - change the number of RSS queues.
3131 *
3132 * @bp: bnx2x private structure
3133 *
3134 * Re-configure interrupt mode to get the new number of MSI-X
3135 * vectors and re-add NAPI objects.
3136 */
3137static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3138{
0e8d2ec5 3139 bnx2x_disable_msi(bp);
55c11941
MS		 3140 bp->num_ethernet_queues = num_rss;
3141 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3142 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
0e8d2ec5 3143 bnx2x_set_int_mode(bp);
0e8d2ec5
MS		 3144}
3145
3146/**
3147 * bnx2x_set_channels - sets the number of RSS queues.
3148 *
3149 * @dev: net device
3150 * @channels: includes the number of queues requested
3151 */
3152static int bnx2x_set_channels(struct net_device *dev,
3153 struct ethtool_channels *channels)
3154{
3155 struct bnx2x *bp = netdev_priv(dev);
3156
3157
3158 DP(BNX2X_MSG_ETHTOOL,
3159 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3160 channels->rx_count, channels->tx_count, channels->other_count,
3161 channels->combined_count);
3162
3163 /* We don't support separate rx / tx channels.
3164 * We don't allow setting 'other' channels.
3165 */
3166 if (channels->rx_count || channels->tx_count || channels->other_count
3167 || (channels->combined_count == 0) ||
3168 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3169 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3170 return -EINVAL;
3171 }
3172
3173 /* Check if there was a change in the active parameters */
3174 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3175 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3176 return 0;
3177 }
3178
3179 /* Set the requested number of queues in bp context.
3180 * Note that the actual number of queues created during load may be
3181 * less than requested if memory is low.
3182 */
3183 if (unlikely(!netif_running(dev))) {
3184 bnx2x_change_num_queues(bp, channels->combined_count);
3185 return 0;
3186 }
5d07d868 3187 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
0e8d2ec5
MS		 3188 bnx2x_change_num_queues(bp, channels->combined_count);
3189 return bnx2x_nic_load(bp, LOAD_NORMAL);
3190}
3191
de0c62db
DK		 3192static const struct ethtool_ops bnx2x_ethtool_ops = {
3193 .get_settings = bnx2x_get_settings,
3194 .set_settings = bnx2x_set_settings,
3195 .get_drvinfo = bnx2x_get_drvinfo,
3196 .get_regs_len = bnx2x_get_regs_len,
3197 .get_regs = bnx2x_get_regs,
07ba6af4
MS		 3198 .get_dump_flag = bnx2x_get_dump_flag,
3199 .get_dump_data = bnx2x_get_dump_data,
3200 .set_dump = bnx2x_set_dump,
de0c62db
DK		 3201 .get_wol = bnx2x_get_wol,
3202 .set_wol = bnx2x_set_wol,
3203 .get_msglevel = bnx2x_get_msglevel,
3204 .set_msglevel = bnx2x_set_msglevel,
3205 .nway_reset = bnx2x_nway_reset,
3206 .get_link = bnx2x_get_link,
3207 .get_eeprom_len = bnx2x_get_eeprom_len,
3208 .get_eeprom = bnx2x_get_eeprom,
3209 .set_eeprom = bnx2x_set_eeprom,
3210 .get_coalesce = bnx2x_get_coalesce,
3211 .set_coalesce = bnx2x_set_coalesce,
3212 .get_ringparam = bnx2x_get_ringparam,
3213 .set_ringparam = bnx2x_set_ringparam,
3214 .get_pauseparam = bnx2x_get_pauseparam,
3215 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 3216 .self_test = bnx2x_self_test,
3217 .get_sset_count = bnx2x_get_sset_count,
3218 .get_strings = bnx2x_get_strings,
32d36134 3219 .set_phys_id = bnx2x_set_phys_id,
de0c62db 3220 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 3221 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 3222 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 3223 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 3224 .get_rxfh_indir = bnx2x_get_rxfh_indir,
3225 .set_rxfh_indir = bnx2x_set_rxfh_indir,
0e8d2ec5
MS		 3226 .get_channels = bnx2x_get_channels,
3227 .set_channels = bnx2x_set_channels,
24ea818e
YM		 3228 .get_module_info = bnx2x_get_module_info,
3229 .get_module_eeprom = bnx2x_get_module_eeprom,
e9939c80
YM		 3230 .get_eee = bnx2x_get_eee,
3231 .set_eee = bnx2x_set_eee,
be53ce1e 3232 .get_ts_info = ethtool_op_get_ts_info,
de0c62db
DK		 3233};
3234
3235void bnx2x_set_ethtool_ops(struct net_device *netdev)
3236{
3237 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3238}
kernel source for telekom puls (alcatel/mediatek)