projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
bnx2x: Filter packets on FCoE rings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
c96bdc0c
DK		 65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
ec6ba945
VZ		 68};
69
70#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72static const struct {
73 long offset;
74 int size;
75 u32 flags;
76#define STATS_FLAGS_PORT 1
77#define STATS_FLAGS_FUNC 2
78#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80} bnx2x_stats_arr[] = {
81/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
c96bdc0c
DK		 182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
e9939c80
YM		 184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 189static int bnx2x_get_port_type(struct bnx2x *bp)
190{
191 int port_type;
192 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
193 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 194 case ETH_PHY_SFPP_10G_FIBER:
195 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 196 case ETH_PHY_XFP_FIBER:
197 case ETH_PHY_KR:
198 case ETH_PHY_CX4:
199 port_type = PORT_FIBRE;
200 break;
201 case ETH_PHY_DA_TWINAX:
202 port_type = PORT_DA;
203 break;
204 case ETH_PHY_BASE_T:
205 port_type = PORT_TP;
206 break;
207 case ETH_PHY_NOT_PRESENT:
208 port_type = PORT_NONE;
209 break;
210 case ETH_PHY_UNSPECIFIED:
211 default:
212 port_type = PORT_OTHER;
213 break;
214 }
215 return port_type;
216}
ec6ba945 217
de0c62db
DK		 218static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
219{
220 struct bnx2x *bp = netdev_priv(dev);
a22f0788 221 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 222
a22f0788
YR		 223 /* Dual Media boards present all available port types */
224 cmd->supported = bp->port.supported[cfg_idx] |
225 (bp->port.supported[cfg_idx ^ 1] &
226 (SUPPORTED_TP | SUPPORTED_FIBRE));
227 cmd->advertising = bp->port.advertising[cfg_idx];
dbef807e
YM		 228 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
229 ETH_PHY_SFP_1G_FIBER) {
230 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
231 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
232 }
de0c62db 233
38298461
YM		 234 if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
235 if (!(bp->flags & MF_FUNC_DIS)) {
236 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
237 cmd->duplex = bp->link_vars.duplex;
238 } else {
239 ethtool_cmd_speed_set(
240 cmd, bp->link_params.req_line_speed[cfg_idx]);
241 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
242 }
243
244 if (IS_MF(bp) && !BP_NOMCP(bp))
245 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 246 } else {
38298461
YM		 247 cmd->duplex = DUPLEX_UNKNOWN;
248 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 249 }
f2e0899f 250
1ac9e428 251 cmd->port = bnx2x_get_port_type(bp);
a22f0788 252
de0c62db
DK		 253 cmd->phy_address = bp->mdio.prtad;
254 cmd->transceiver = XCVR_INTERNAL;
255
a22f0788 256 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 257 cmd->autoneg = AUTONEG_ENABLE;
258 else
259 cmd->autoneg = AUTONEG_DISABLE;
260
9e7e8399
MY		 261 /* Publish LP advertised speeds and FC */
262 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
263 u32 status = bp->link_vars.link_status;
264
265 cmd->lp_advertising |= ADVERTISED_Autoneg;
266 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
267 cmd->lp_advertising |= ADVERTISED_Pause;
268 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
269 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
270
271 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
272 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
273 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
274 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
275 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
276 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
277 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
278 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
279 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
280 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
281 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
282 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
283 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
284 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
285 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
286 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
287 }
288
de0c62db
DK		 289 cmd->maxtxpkt = 0;
290 cmd->maxrxpkt = 0;
291
51c1a580 292 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 293 " supported 0x%x advertising 0x%x speed %u\n"
294 " duplex %d port %d phy_address %d transceiver %d\n"
295 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 296 cmd->cmd, cmd->supported, cmd->advertising,
297 ethtool_cmd_speed(cmd),
de0c62db
DK		 298 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
299 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
300
301 return 0;
302}
303
304static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
305{
306 struct bnx2x *bp = netdev_priv(dev);
a22f0788 307 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 308 u32 speed, phy_idx;
de0c62db 309
0793f83f 310 if (IS_MF_SD(bp))
de0c62db
DK		 311 return 0;
312
51c1a580 313 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 314 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 315 " duplex %d port %d phy_address %d transceiver %d\n"
316 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 317 cmd->cmd, cmd->supported, cmd->advertising,
318 ethtool_cmd_speed(cmd),
de0c62db
DK		 319 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
320 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
321
b3337e4c 322 speed = ethtool_cmd_speed(cmd);
0793f83f 323
38298461
YM		 324 /* If recieved a request for an unknown duplex, assume full*/
325 if (cmd->duplex == DUPLEX_UNKNOWN)
326 cmd->duplex = DUPLEX_FULL;
327
0793f83f 328 if (IS_MF_SI(bp)) {
e3835b99 329 u32 part;
0793f83f
DK		 330 u32 line_speed = bp->link_vars.line_speed;
331
332 /* use 10G if no link detected */
333 if (!line_speed)
334 line_speed = 10000;
335
336 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 337 DP(BNX2X_MSG_ETHTOOL,
338 "To set speed BC %X or higher is required, please upgrade BC\n",
339 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 340 return -EINVAL;
341 }
e3835b99 342
faa6fcbb 343 part = (speed * 100) / line_speed;
e3835b99 344
faa6fcbb 345 if (line_speed < speed || !part) {
51c1a580
MS		 346 DP(BNX2X_MSG_ETHTOOL,
347 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 348 return -EINVAL;
349 }
0793f83f 350
e3835b99
DK		 351 if (bp->state != BNX2X_STATE_OPEN)
352 /* store value for following "load" */
353 bp->pending_max = part;
354 else
355 bnx2x_update_max_mf_config(bp, part);
0793f83f 356
0793f83f
DK		 357 return 0;
358 }
359
a22f0788
YR		 360 cfg_idx = bnx2x_get_link_cfg_idx(bp);
361 old_multi_phy_config = bp->link_params.multi_phy_config;
362 switch (cmd->port) {
363 case PORT_TP:
364 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
365 break; /* no port change */
366
367 if (!(bp->port.supported[0] & SUPPORTED_TP ||
368 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 369 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 370 return -EINVAL;
371 }
372 bp->link_params.multi_phy_config &=
373 ~PORT_HW_CFG_PHY_SELECTION_MASK;
374 if (bp->link_params.multi_phy_config &
375 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
376 bp->link_params.multi_phy_config |=
377 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
378 else
379 bp->link_params.multi_phy_config |=
380 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
381 break;
382 case PORT_FIBRE:
bfdb5823 383 case PORT_DA:
a22f0788
YR		 384 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
385 break; /* no port change */
386
387 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
388 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 389 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 390 return -EINVAL;
391 }
392 bp->link_params.multi_phy_config &=
393 ~PORT_HW_CFG_PHY_SELECTION_MASK;
394 if (bp->link_params.multi_phy_config &
395 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
396 bp->link_params.multi_phy_config |=
397 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
398 else
399 bp->link_params.multi_phy_config |=
400 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
401 break;
402 default:
51c1a580 403 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 404 return -EINVAL;
405 }
2f751a80 406 /* Save new config in case command complete successully */
a22f0788
YR		 407 new_multi_phy_config = bp->link_params.multi_phy_config;
408 /* Get the new cfg_idx */
409 cfg_idx = bnx2x_get_link_cfg_idx(bp);
410 /* Restore old config in case command failed */
411 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 412 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 413
de0c62db 414 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 415 u32 an_supported_speed = bp->port.supported[cfg_idx];
416 if (bp->link_params.phy[EXT_PHY1].type ==
417 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
418 an_supported_speed |= (SUPPORTED_100baseT_Half |
419 SUPPORTED_100baseT_Full);
a22f0788 420 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 421 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 422 return -EINVAL;
423 }
424
425 /* advertise the requested speed and duplex if supported */
75318327 426 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 427 DP(BNX2X_MSG_ETHTOOL,
428 "Advertisement parameters are not supported\n");
8d661637
YR		 429 return -EINVAL;
430 }
de0c62db 431
a22f0788 432 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 433 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
434 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 435 cmd->advertising);
8d661637
YR		 436 if (cmd->advertising) {
437
438 bp->link_params.speed_cap_mask[cfg_idx] = 0;
439 if (cmd->advertising & ADVERTISED_10baseT_Half) {
440 bp->link_params.speed_cap_mask[cfg_idx] |=
441 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
442 }
443 if (cmd->advertising & ADVERTISED_10baseT_Full)
444 bp->link_params.speed_cap_mask[cfg_idx] |=
445 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 446
8d661637
YR		 447 if (cmd->advertising & ADVERTISED_100baseT_Full)
448 bp->link_params.speed_cap_mask[cfg_idx] |=
449 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
450
451 if (cmd->advertising & ADVERTISED_100baseT_Half) {
452 bp->link_params.speed_cap_mask[cfg_idx] |=
453 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
454 }
455 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
456 bp->link_params.speed_cap_mask[cfg_idx] |=
457 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
458 }
459 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
460 ADVERTISED_1000baseKX_Full))
461 bp->link_params.speed_cap_mask[cfg_idx] |=
462 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
463
464 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
465 ADVERTISED_10000baseKX4_Full |
466 ADVERTISED_10000baseKR_Full))
467 bp->link_params.speed_cap_mask[cfg_idx] |=
468 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
469 }
de0c62db
DK		 470 } else { /* forced speed */
471 /* advertise the requested speed and duplex if supported */
a22f0788 472 switch (speed) {
de0c62db
DK		 473 case SPEED_10:
474 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 475 if (!(bp->port.supported[cfg_idx] &
de0c62db 476 SUPPORTED_10baseT_Full)) {
51c1a580 477 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 478 "10M full not supported\n");
479 return -EINVAL;
480 }
481
482 advertising = (ADVERTISED_10baseT_Full |
483 ADVERTISED_TP);
484 } else {
a22f0788 485 if (!(bp->port.supported[cfg_idx] &
de0c62db 486 SUPPORTED_10baseT_Half)) {
51c1a580 487 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 488 "10M half not supported\n");
489 return -EINVAL;
490 }
491
492 advertising = (ADVERTISED_10baseT_Half |
493 ADVERTISED_TP);
494 }
495 break;
496
497 case SPEED_100:
498 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 499 if (!(bp->port.supported[cfg_idx] &
de0c62db 500 SUPPORTED_100baseT_Full)) {
51c1a580 501 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 502 "100M full not supported\n");
503 return -EINVAL;
504 }
505
506 advertising = (ADVERTISED_100baseT_Full |
507 ADVERTISED_TP);
508 } else {
a22f0788 509 if (!(bp->port.supported[cfg_idx] &
de0c62db 510 SUPPORTED_100baseT_Half)) {
51c1a580 511 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 512 "100M half not supported\n");
513 return -EINVAL;
514 }
515
516 advertising = (ADVERTISED_100baseT_Half |
517 ADVERTISED_TP);
518 }
519 break;
520
521 case SPEED_1000:
522 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 523 DP(BNX2X_MSG_ETHTOOL,
524 "1G half not supported\n");
de0c62db
DK		 525 return -EINVAL;
526 }
527
a22f0788
YR		 528 if (!(bp->port.supported[cfg_idx] &
529 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 530 DP(BNX2X_MSG_ETHTOOL,
531 "1G full not supported\n");
de0c62db
DK		 532 return -EINVAL;
533 }
534
535 advertising = (ADVERTISED_1000baseT_Full |
536 ADVERTISED_TP);
537 break;
538
539 case SPEED_2500:
540 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 541 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 542 "2.5G half not supported\n");
543 return -EINVAL;
544 }
545
a22f0788
YR		 546 if (!(bp->port.supported[cfg_idx]
547 & SUPPORTED_2500baseX_Full)) {
51c1a580 548 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 549 "2.5G full not supported\n");
550 return -EINVAL;
551 }
552
553 advertising = (ADVERTISED_2500baseX_Full |
554 ADVERTISED_TP);
555 break;
556
557 case SPEED_10000:
558 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 559 DP(BNX2X_MSG_ETHTOOL,
560 "10G half not supported\n");
de0c62db
DK		 561 return -EINVAL;
562 }
dbef807e 563 phy_idx = bnx2x_get_cur_phy_idx(bp);
a22f0788 564 if (!(bp->port.supported[cfg_idx]
dbef807e
YM		 565 & SUPPORTED_10000baseT_Full) ||
566 (bp->link_params.phy[phy_idx].media_type ==
567 ETH_PHY_SFP_1G_FIBER)) {
51c1a580
MS		 568 DP(BNX2X_MSG_ETHTOOL,
569 "10G full not supported\n");
de0c62db
DK		 570 return -EINVAL;
571 }
572
573 advertising = (ADVERTISED_10000baseT_Full |
574 ADVERTISED_FIBRE);
575 break;
576
577 default:
51c1a580 578 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 579 return -EINVAL;
580 }
581
a22f0788
YR		 582 bp->link_params.req_line_speed[cfg_idx] = speed;
583 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
584 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 585 }
586
51c1a580 587 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 588 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 589 bp->link_params.req_line_speed[cfg_idx],
590 bp->link_params.req_duplex[cfg_idx],
591 bp->port.advertising[cfg_idx]);
de0c62db 592
a22f0788
YR		 593 /* Set new config */
594 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 595 if (netif_running(dev)) {
596 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
597 bnx2x_link_set(bp);
598 }
599
600 return 0;
601}
602
603#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
604#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 605#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 606#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
607#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
608
1191cb83
ED		 609static bool bnx2x_is_reg_online(struct bnx2x *bp,
610 const struct reg_addr *reg_info)
0fea29c1
VZ		 611{
612 if (CHIP_IS_E1(bp))
613 return IS_E1_ONLINE(reg_info->info);
614 else if (CHIP_IS_E1H(bp))
615 return IS_E1H_ONLINE(reg_info->info);
616 else if (CHIP_IS_E2(bp))
617 return IS_E2_ONLINE(reg_info->info);
618 else if (CHIP_IS_E3A0(bp))
619 return IS_E3_ONLINE(reg_info->info);
620 else if (CHIP_IS_E3B0(bp))
621 return IS_E3B0_ONLINE(reg_info->info);
622 else
623 return false;
624}
625
626/******* Paged registers info selectors ********/
1191cb83 627static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 628{
629 if (CHIP_IS_E2(bp))
630 return page_vals_e2;
631 else if (CHIP_IS_E3(bp))
632 return page_vals_e3;
633 else
634 return NULL;
635}
636
1191cb83 637static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 638{
639 if (CHIP_IS_E2(bp))
640 return PAGE_MODE_VALUES_E2;
641 else if (CHIP_IS_E3(bp))
642 return PAGE_MODE_VALUES_E3;
643 else
644 return 0;
645}
646
1191cb83 647static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 648{
649 if (CHIP_IS_E2(bp))
650 return page_write_regs_e2;
651 else if (CHIP_IS_E3(bp))
652 return page_write_regs_e3;
653 else
654 return NULL;
655}
656
1191cb83 657static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 658{
659 if (CHIP_IS_E2(bp))
660 return PAGE_WRITE_REGS_E2;
661 else if (CHIP_IS_E3(bp))
662 return PAGE_WRITE_REGS_E3;
663 else
664 return 0;
665}
666
1191cb83 667static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 668{
669 if (CHIP_IS_E2(bp))
670 return page_read_regs_e2;
671 else if (CHIP_IS_E3(bp))
672 return page_read_regs_e3;
673 else
674 return NULL;
675}
676
1191cb83 677static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 678{
679 if (CHIP_IS_E2(bp))
680 return PAGE_READ_REGS_E2;
681 else if (CHIP_IS_E3(bp))
682 return PAGE_READ_REGS_E3;
683 else
684 return 0;
685}
686
1191cb83 687static int __bnx2x_get_regs_len(struct bnx2x *bp)
0fea29c1
VZ		 688{
689 int num_pages = __bnx2x_get_page_reg_num(bp);
690 int page_write_num = __bnx2x_get_page_write_num(bp);
691 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
692 int page_read_num = __bnx2x_get_page_read_num(bp);
693 int regdump_len = 0;
694 int i, j, k;
695
696 for (i = 0; i < REGS_COUNT; i++)
697 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
698 regdump_len += reg_addrs[i].size;
699
700 for (i = 0; i < num_pages; i++)
701 for (j = 0; j < page_write_num; j++)
702 for (k = 0; k < page_read_num; k++)
703 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
704 regdump_len += page_read_addr[k].size;
705
706 return regdump_len;
707}
de0c62db
DK		 708
709static int bnx2x_get_regs_len(struct net_device *dev)
710{
711 struct bnx2x *bp = netdev_priv(dev);
712 int regdump_len = 0;
de0c62db 713
0fea29c1 714 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 715 regdump_len *= 4;
716 regdump_len += sizeof(struct dump_hdr);
717
718 return regdump_len;
719}
720
0fea29c1
VZ		 721/**
722 * bnx2x_read_pages_regs - read "paged" registers
723 *
724 * @bp device handle
725 * @p output buffer
726 *
727 * Reads "paged" memories: memories that may only be read by first writing to a
728 * specific address ("write address") and then reading from a specific address
729 * ("read address"). There may be more than one write address per "page" and
730 * more than one read address per write address.
731 */
1191cb83 732static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 733{
734 u32 i, j, k, n;
0fea29c1
VZ		 735 /* addresses of the paged registers */
736 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
737 /* number of paged registers */
738 int num_pages = __bnx2x_get_page_reg_num(bp);
739 /* write addresses */
740 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
741 /* number of write addresses */
742 int write_num = __bnx2x_get_page_write_num(bp);
743 /* read addresses info */
744 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
745 /* number of read addresses */
746 int read_num = __bnx2x_get_page_read_num(bp);
747
748 for (i = 0; i < num_pages; i++) {
749 for (j = 0; j < write_num; j++) {
750 REG_WR(bp, write_addr[j], page_addr[i]);
751 for (k = 0; k < read_num; k++)
752 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 753 for (n = 0; n <
0fea29c1 754 read_addr[k].size; n++)
f2e0899f 755 *p++ = REG_RD(bp,
0fea29c1 756 read_addr[k].addr + n*4);
f2e0899f
DK		 757 }
758 }
759}
760
1191cb83 761static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
0fea29c1
VZ		 762{
763 u32 i, j;
764
765 /* Read the regular registers */
766 for (i = 0; i < REGS_COUNT; i++)
767 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
768 for (j = 0; j < reg_addrs[i].size; j++)
769 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
770
771 /* Read "paged" registes */
772 bnx2x_read_pages_regs(bp, p);
773}
774
de0c62db
DK		 775static void bnx2x_get_regs(struct net_device *dev,
776 struct ethtool_regs *regs, void *_p)
777{
0fea29c1 778 u32 *p = _p;
de0c62db
DK		 779 struct bnx2x *bp = netdev_priv(dev);
780 struct dump_hdr dump_hdr = {0};
781
2ace9510 782 regs->version = 1;
de0c62db
DK		 783 memset(p, 0, regs->len);
784
785 if (!netif_running(bp->dev))
786 return;
787
4a33bc03
VZ		 788 /* Disable parity attentions as long as following dump may
789 * cause false alarms by reading never written registers. We
790 * will re-enable parity attentions right after the dump.
791 */
792 bnx2x_disable_blocks_parity(bp);
793
de0c62db
DK		 794 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
795 dump_hdr.dump_sign = dump_sign_all;
796 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
797 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
798 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
799 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 800
801 if (CHIP_IS_E1(bp))
802 dump_hdr.info = RI_E1_ONLINE;
803 else if (CHIP_IS_E1H(bp))
804 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 805 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 806 dump_hdr.info = RI_E2_ONLINE |
807 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 808
809 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
810 p += dump_hdr.hdr_size + 1;
811
0fea29c1
VZ		 812 /* Actually read the registers */
813 __bnx2x_get_regs(bp, p);
814
4a33bc03
VZ		 815 /* Re-enable parity attentions */
816 bnx2x_clear_blocks_parity(bp);
c9ee9206 817 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 818}
819
de0c62db
DK		 820static void bnx2x_get_drvinfo(struct net_device *dev,
821 struct ethtool_drvinfo *info)
822{
823 struct bnx2x *bp = netdev_priv(dev);
824 u8 phy_fw_ver[PHY_FW_VER_LEN];
825
68aad78c
RJ		 826 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
827 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db
DK		 828
829 phy_fw_ver[0] = '\0';
a1e785e0
MY		 830 bnx2x_get_ext_phy_fw_version(&bp->link_params,
831 phy_fw_ver, PHY_FW_VER_LEN);
68aad78c 832 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
de0c62db
DK		 833 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
834 "bc %d.%d.%d%s%s",
835 (bp->common.bc_ver & 0xff0000) >> 16,
836 (bp->common.bc_ver & 0xff00) >> 8,
837 (bp->common.bc_ver & 0xff),
838 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
68aad78c 839 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 840 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 841 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 842 info->eedump_len = bp->common.flash_size;
843 info->regdump_len = bnx2x_get_regs_len(dev);
844}
845
846static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
847{
848 struct bnx2x *bp = netdev_priv(dev);
849
850 if (bp->flags & NO_WOL_FLAG) {
851 wol->supported = 0;
852 wol->wolopts = 0;
853 } else {
854 wol->supported = WAKE_MAGIC;
855 if (bp->wol)
856 wol->wolopts = WAKE_MAGIC;
857 else
858 wol->wolopts = 0;
859 }
860 memset(&wol->sopass, 0, sizeof(wol->sopass));
861}
862
863static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
864{
865 struct bnx2x *bp = netdev_priv(dev);
866
51c1a580
MS		 867 if (wol->wolopts & ~WAKE_MAGIC) {
868 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 869 return -EINVAL;
51c1a580 870 }
de0c62db
DK		 871
872 if (wol->wolopts & WAKE_MAGIC) {
51c1a580
MS		 873 if (bp->flags & NO_WOL_FLAG) {
874 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 875 return -EINVAL;
51c1a580 876 }
de0c62db
DK		 877 bp->wol = 1;
878 } else
879 bp->wol = 0;
880
881 return 0;
882}
883
884static u32 bnx2x_get_msglevel(struct net_device *dev)
885{
886 struct bnx2x *bp = netdev_priv(dev);
887
888 return bp->msg_enable;
889}
890
891static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
892{
893 struct bnx2x *bp = netdev_priv(dev);
894
7a25cc73
DK		 895 if (capable(CAP_NET_ADMIN)) {
896 /* dump MCP trace */
897 if (level & BNX2X_MSG_MCP)
898 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 899 bp->msg_enable = level;
7a25cc73 900 }
de0c62db
DK		 901}
902
903static int bnx2x_nway_reset(struct net_device *dev)
904{
905 struct bnx2x *bp = netdev_priv(dev);
906
907 if (!bp->port.pmf)
908 return 0;
909
910 if (netif_running(dev)) {
911 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 912 bnx2x_force_link_reset(bp);
de0c62db
DK		 913 bnx2x_link_set(bp);
914 }
915
916 return 0;
917}
918
919static u32 bnx2x_get_link(struct net_device *dev)
920{
921 struct bnx2x *bp = netdev_priv(dev);
922
f2e0899f 923 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 924 return 0;
925
926 return bp->link_vars.link_up;
927}
928
929static int bnx2x_get_eeprom_len(struct net_device *dev)
930{
931 struct bnx2x *bp = netdev_priv(dev);
932
933 return bp->common.flash_size;
934}
935
f16da43b
AE		 936/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
937 * we done things the other way around, if two pfs from the same port would
938 * attempt to access nvram at the same time, we could run into a scenario such
939 * as:
940 * pf A takes the port lock.
941 * pf B succeeds in taking the same lock since they are from the same port.
942 * pf A takes the per pf misc lock. Performs eeprom access.
943 * pf A finishes. Unlocks the per pf misc lock.
944 * Pf B takes the lock and proceeds to perform it's own access.
945 * pf A unlocks the per port lock, while pf B is still working (!).
946 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
947 * acess corrupted by pf B).*
948 */
de0c62db
DK		 949static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
950{
951 int port = BP_PORT(bp);
952 int count, i;
f16da43b
AE		 953 u32 val;
954
955 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
956 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 957
958 /* adjust timeout for emulation/FPGA */
754a2f52 959 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 960 if (CHIP_REV_IS_SLOW(bp))
961 count *= 100;
962
963 /* request access to nvram interface */
964 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
965 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
966
967 for (i = 0; i < count*10; i++) {
968 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
969 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
970 break;
971
972 udelay(5);
973 }
974
975 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 976 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
977 "cannot get access to nvram interface\n");
de0c62db
DK		 978 return -EBUSY;
979 }
980
981 return 0;
982}
983
984static int bnx2x_release_nvram_lock(struct bnx2x *bp)
985{
986 int port = BP_PORT(bp);
987 int count, i;
f16da43b 988 u32 val;
de0c62db
DK		 989
990 /* adjust timeout for emulation/FPGA */
754a2f52 991 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 992 if (CHIP_REV_IS_SLOW(bp))
993 count *= 100;
994
995 /* relinquish nvram interface */
996 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
997 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
998
999 for (i = 0; i < count*10; i++) {
1000 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1001 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1002 break;
1003
1004 udelay(5);
1005 }
1006
1007 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 1008 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1009 "cannot free access to nvram interface\n");
de0c62db
DK		 1010 return -EBUSY;
1011 }
1012
f16da43b
AE		 1013 /* release HW lock: protect against other PFs in PF Direct Assignment */
1014 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1015 return 0;
1016}
1017
1018static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1019{
1020 u32 val;
1021
1022 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1023
1024 /* enable both bits, even on read */
1025 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1026 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1027 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1028}
1029
1030static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1031{
1032 u32 val;
1033
1034 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1035
1036 /* disable both bits, even after read */
1037 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1038 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1039 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1040}
1041
1042static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1043 u32 cmd_flags)
1044{
1045 int count, i, rc;
1046 u32 val;
1047
1048 /* build the command word */
1049 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1050
1051 /* need to clear DONE bit separately */
1052 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1053
1054 /* address of the NVRAM to read from */
1055 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1056 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1057
1058 /* issue a read command */
1059 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1060
1061 /* adjust timeout for emulation/FPGA */
754a2f52 1062 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1063 if (CHIP_REV_IS_SLOW(bp))
1064 count *= 100;
1065
1066 /* wait for completion */
1067 *ret_val = 0;
1068 rc = -EBUSY;
1069 for (i = 0; i < count; i++) {
1070 udelay(5);
1071 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1072
1073 if (val & MCPR_NVM_COMMAND_DONE) {
1074 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1075 /* we read nvram data in cpu order
1076 * but ethtool sees it as an array of bytes
1077 * converting to big-endian will do the work */
1078 *ret_val = cpu_to_be32(val);
1079 rc = 0;
1080 break;
1081 }
1082 }
51c1a580
MS		 1083 if (rc == -EBUSY)
1084 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1085 "nvram read timeout expired\n");
de0c62db
DK		 1086 return rc;
1087}
1088
1089static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1090 int buf_size)
1091{
1092 int rc;
1093 u32 cmd_flags;
1094 __be32 val;
1095
1096 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1097 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1098 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1099 offset, buf_size);
1100 return -EINVAL;
1101 }
1102
1103 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1104 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1105 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1106 offset, buf_size, bp->common.flash_size);
1107 return -EINVAL;
1108 }
1109
1110 /* request access to nvram interface */
1111 rc = bnx2x_acquire_nvram_lock(bp);
1112 if (rc)
1113 return rc;
1114
1115 /* enable access to nvram interface */
1116 bnx2x_enable_nvram_access(bp);
1117
1118 /* read the first word(s) */
1119 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1120 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1121 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1122 memcpy(ret_buf, &val, 4);
1123
1124 /* advance to the next dword */
1125 offset += sizeof(u32);
1126 ret_buf += sizeof(u32);
1127 buf_size -= sizeof(u32);
1128 cmd_flags = 0;
1129 }
1130
1131 if (rc == 0) {
1132 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1133 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1134 memcpy(ret_buf, &val, 4);
1135 }
1136
1137 /* disable access to nvram interface */
1138 bnx2x_disable_nvram_access(bp);
1139 bnx2x_release_nvram_lock(bp);
1140
1141 return rc;
1142}
1143
1144static int bnx2x_get_eeprom(struct net_device *dev,
1145 struct ethtool_eeprom *eeprom, u8 *eebuf)
1146{
1147 struct bnx2x *bp = netdev_priv(dev);
1148 int rc;
1149
51c1a580
MS		 1150 if (!netif_running(dev)) {
1151 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1152 "cannot access eeprom when the interface is down\n");
de0c62db 1153 return -EAGAIN;
51c1a580 1154 }
de0c62db 1155
51c1a580 1156 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1157 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1158 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1159 eeprom->len, eeprom->len);
1160
1161 /* parameters already validated in ethtool_get_eeprom */
1162
1163 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1164
1165 return rc;
1166}
1167
24ea818e
YM		 1168static int bnx2x_get_module_eeprom(struct net_device *dev,
1169 struct ethtool_eeprom *ee,
1170 u8 *data)
1171{
1172 struct bnx2x *bp = netdev_priv(dev);
1173 int rc = 0, phy_idx;
1174 u8 *user_data = data;
1175 int remaining_len = ee->len, xfer_size;
1176 unsigned int page_off = ee->offset;
1177
1178 if (!netif_running(dev)) {
1179 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1180 "cannot access eeprom when the interface is down\n");
1181 return -EAGAIN;
1182 }
1183
1184 phy_idx = bnx2x_get_cur_phy_idx(bp);
1185 bnx2x_acquire_phy_lock(bp);
1186 while (!rc && remaining_len > 0) {
1187 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1188 SFP_EEPROM_PAGE_SIZE : remaining_len;
1189 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1190 &bp->link_params,
1191 page_off,
1192 xfer_size,
1193 user_data);
1194 remaining_len -= xfer_size;
1195 user_data += xfer_size;
1196 page_off += xfer_size;
1197 }
1198
1199 bnx2x_release_phy_lock(bp);
1200 return rc;
1201}
1202
1203static int bnx2x_get_module_info(struct net_device *dev,
1204 struct ethtool_modinfo *modinfo)
1205{
1206 struct bnx2x *bp = netdev_priv(dev);
1207 int phy_idx;
1208 if (!netif_running(dev)) {
1209 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1210 "cannot access eeprom when the interface is down\n");
1211 return -EAGAIN;
1212 }
1213
1214 phy_idx = bnx2x_get_cur_phy_idx(bp);
1215 switch (bp->link_params.phy[phy_idx].media_type) {
1216 case ETH_PHY_SFPP_10G_FIBER:
1217 case ETH_PHY_SFP_1G_FIBER:
1218 case ETH_PHY_DA_TWINAX:
1219 modinfo->type = ETH_MODULE_SFF_8079;
1220 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1221 return 0;
1222 default:
1223 return -EOPNOTSUPP;
1224 }
1225}
1226
de0c62db
DK		 1227static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1228 u32 cmd_flags)
1229{
1230 int count, i, rc;
1231
1232 /* build the command word */
1233 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1234
1235 /* need to clear DONE bit separately */
1236 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1237
1238 /* write the data */
1239 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1240
1241 /* address of the NVRAM to write to */
1242 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1243 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1244
1245 /* issue the write command */
1246 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1247
1248 /* adjust timeout for emulation/FPGA */
754a2f52 1249 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1250 if (CHIP_REV_IS_SLOW(bp))
1251 count *= 100;
1252
1253 /* wait for completion */
1254 rc = -EBUSY;
1255 for (i = 0; i < count; i++) {
1256 udelay(5);
1257 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1258 if (val & MCPR_NVM_COMMAND_DONE) {
1259 rc = 0;
1260 break;
1261 }
1262 }
1263
51c1a580
MS		 1264 if (rc == -EBUSY)
1265 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1266 "nvram write timeout expired\n");
de0c62db
DK		 1267 return rc;
1268}
1269
1270#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1271
1272static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1273 int buf_size)
1274{
1275 int rc;
1276 u32 cmd_flags;
1277 u32 align_offset;
1278 __be32 val;
1279
1280 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1281 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1282 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1283 offset, buf_size, bp->common.flash_size);
1284 return -EINVAL;
1285 }
1286
1287 /* request access to nvram interface */
1288 rc = bnx2x_acquire_nvram_lock(bp);
1289 if (rc)
1290 return rc;
1291
1292 /* enable access to nvram interface */
1293 bnx2x_enable_nvram_access(bp);
1294
1295 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1296 align_offset = (offset & ~0x03);
1297 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1298
1299 if (rc == 0) {
1300 val &= ~(0xff << BYTE_OFFSET(offset));
1301 val |= (*data_buf << BYTE_OFFSET(offset));
1302
1303 /* nvram data is returned as an array of bytes
1304 * convert it back to cpu order */
1305 val = be32_to_cpu(val);
1306
1307 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1308 cmd_flags);
1309 }
1310
1311 /* disable access to nvram interface */
1312 bnx2x_disable_nvram_access(bp);
1313 bnx2x_release_nvram_lock(bp);
1314
1315 return rc;
1316}
1317
1318static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1319 int buf_size)
1320{
1321 int rc;
1322 u32 cmd_flags;
1323 u32 val;
1324 u32 written_so_far;
1325
1326 if (buf_size == 1) /* ethtool */
1327 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1328
1329 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1330 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1331 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1332 offset, buf_size);
1333 return -EINVAL;
1334 }
1335
1336 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1337 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1338 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1339 offset, buf_size, bp->common.flash_size);
1340 return -EINVAL;
1341 }
1342
1343 /* request access to nvram interface */
1344 rc = bnx2x_acquire_nvram_lock(bp);
1345 if (rc)
1346 return rc;
1347
1348 /* enable access to nvram interface */
1349 bnx2x_enable_nvram_access(bp);
1350
1351 written_so_far = 0;
1352 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1353 while ((written_so_far < buf_size) && (rc == 0)) {
1354 if (written_so_far == (buf_size - sizeof(u32)))
1355 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1356 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1357 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1358 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1359 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1360
1361 memcpy(&val, data_buf, 4);
1362
1363 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1364
1365 /* advance to the next dword */
1366 offset += sizeof(u32);
1367 data_buf += sizeof(u32);
1368 written_so_far += sizeof(u32);
1369 cmd_flags = 0;
1370 }
1371
1372 /* disable access to nvram interface */
1373 bnx2x_disable_nvram_access(bp);
1374 bnx2x_release_nvram_lock(bp);
1375
1376 return rc;
1377}
1378
1379static int bnx2x_set_eeprom(struct net_device *dev,
1380 struct ethtool_eeprom *eeprom, u8 *eebuf)
1381{
1382 struct bnx2x *bp = netdev_priv(dev);
1383 int port = BP_PORT(bp);
1384 int rc = 0;
e10bc84d 1385 u32 ext_phy_config;
51c1a580
MS		 1386 if (!netif_running(dev)) {
1387 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1388 "cannot access eeprom when the interface is down\n");
de0c62db 1389 return -EAGAIN;
51c1a580 1390 }
de0c62db 1391
51c1a580 1392 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1393 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1394 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1395 eeprom->len, eeprom->len);
1396
1397 /* parameters already validated in ethtool_set_eeprom */
1398
1399 /* PHY eeprom can be accessed only by the PMF */
1400 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1401 !bp->port.pmf) {
1402 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1403 "wrong magic or interface is not pmf\n");
de0c62db 1404 return -EINVAL;
51c1a580 1405 }
de0c62db 1406
e10bc84d
YR		 1407 ext_phy_config =
1408 SHMEM_RD(bp,
1409 dev_info.port_hw_config[port].external_phy_config);
1410
de0c62db
DK		 1411 if (eeprom->magic == 0x50485950) {
1412 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1413 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1414
1415 bnx2x_acquire_phy_lock(bp);
1416 rc |= bnx2x_link_reset(&bp->link_params,
1417 &bp->link_vars, 0);
e10bc84d 1418 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1419 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1420 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1421 MISC_REGISTERS_GPIO_HIGH, port);
1422 bnx2x_release_phy_lock(bp);
1423 bnx2x_link_report(bp);
1424
1425 } else if (eeprom->magic == 0x50485952) {
1426 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1427 if (bp->state == BNX2X_STATE_OPEN) {
1428 bnx2x_acquire_phy_lock(bp);
1429 rc |= bnx2x_link_reset(&bp->link_params,
1430 &bp->link_vars, 1);
1431
1432 rc |= bnx2x_phy_init(&bp->link_params,
1433 &bp->link_vars);
1434 bnx2x_release_phy_lock(bp);
1435 bnx2x_calc_fc_adv(bp);
1436 }
1437 } else if (eeprom->magic == 0x53985943) {
1438 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1439 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1440 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1441
1442 /* DSP Remove Download Mode */
1443 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1444 MISC_REGISTERS_GPIO_LOW, port);
1445
1446 bnx2x_acquire_phy_lock(bp);
1447
e10bc84d
YR		 1448 bnx2x_sfx7101_sp_sw_reset(bp,
1449 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1450
1451 /* wait 0.5 sec to allow it to run */
1452 msleep(500);
1453 bnx2x_ext_phy_hw_reset(bp, port);
1454 msleep(500);
1455 bnx2x_release_phy_lock(bp);
1456 }
1457 } else
1458 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1459
1460 return rc;
1461}
f85582f8 1462
de0c62db
DK		 1463static int bnx2x_get_coalesce(struct net_device *dev,
1464 struct ethtool_coalesce *coal)
1465{
1466 struct bnx2x *bp = netdev_priv(dev);
1467
1468 memset(coal, 0, sizeof(struct ethtool_coalesce));
1469
1470 coal->rx_coalesce_usecs = bp->rx_ticks;
1471 coal->tx_coalesce_usecs = bp->tx_ticks;
1472
1473 return 0;
1474}
1475
1476static int bnx2x_set_coalesce(struct net_device *dev,
1477 struct ethtool_coalesce *coal)
1478{
1479 struct bnx2x *bp = netdev_priv(dev);
1480
1481 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1482 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1483 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1484
1485 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1486 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1487 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1488
1489 if (netif_running(dev))
1490 bnx2x_update_coalesce(bp);
1491
1492 return 0;
1493}
1494
1495static void bnx2x_get_ringparam(struct net_device *dev,
1496 struct ethtool_ringparam *ering)
1497{
1498 struct bnx2x *bp = netdev_priv(dev);
1499
1500 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1501
25141580
DK		 1502 if (bp->rx_ring_size)
1503 ering->rx_pending = bp->rx_ring_size;
1504 else
c2188952 1505 ering->rx_pending = MAX_RX_AVAIL;
25141580 1506
a3348722 1507 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1508 ering->tx_pending = bp->tx_ring_size;
1509}
1510
1511static int bnx2x_set_ringparam(struct net_device *dev,
1512 struct ethtool_ringparam *ering)
1513{
1514 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1515
1516 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1517 DP(BNX2X_MSG_ETHTOOL,
1518 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1519 return -EAGAIN;
1520 }
1521
1522 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1523 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1524 MIN_RX_SIZE_TPA)) ||
a3348722 1525 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1526 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1527 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1528 return -EINVAL;
51c1a580 1529 }
de0c62db
DK		 1530
1531 bp->rx_ring_size = ering->rx_pending;
1532 bp->tx_ring_size = ering->tx_pending;
1533
a9fccec7 1534 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1535}
1536
1537static void bnx2x_get_pauseparam(struct net_device *dev,
1538 struct ethtool_pauseparam *epause)
1539{
1540 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1541 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1542 int cfg_reg;
1543
a22f0788
YR		 1544 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1545 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1546
9e7e8399 1547 if (!epause->autoneg)
241fb5d2 1548 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1549 else
1550 cfg_reg = bp->link_params.req_fc_auto_adv;
1551
1552 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1553 BNX2X_FLOW_CTRL_RX);
9e7e8399 1554 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1555 BNX2X_FLOW_CTRL_TX);
1556
51c1a580 1557 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1558 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1559 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1560}
1561
1562static int bnx2x_set_pauseparam(struct net_device *dev,
1563 struct ethtool_pauseparam *epause)
1564{
1565 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1566 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1567 if (IS_MF(bp))
de0c62db
DK		 1568 return 0;
1569
51c1a580 1570 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1571 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1572 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1573
a22f0788 1574 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1575
1576 if (epause->rx_pause)
a22f0788 1577 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1578
1579 if (epause->tx_pause)
a22f0788 1580 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1581
a22f0788
YR		 1582 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1583 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1584
1585 if (epause->autoneg) {
a22f0788 1586 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1587 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1588 return -EINVAL;
1589 }
1590
a22f0788
YR		 1591 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1592 bp->link_params.req_flow_ctrl[cfg_idx] =
1593 BNX2X_FLOW_CTRL_AUTO;
1594 }
5cd75f0c
YR		 1595 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1596 if (epause->rx_pause)
1597 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1598
1599 if (epause->tx_pause)
1600 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
de0c62db
DK		 1601 }
1602
51c1a580 1603 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1604 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1605
1606 if (netif_running(dev)) {
1607 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1608 bnx2x_link_set(bp);
1609 }
1610
1611 return 0;
1612}
1613
5889335c 1614static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
cf2c1df6
MS		 1615 "register_test (offline) ",
1616 "memory_test (offline) ",
1617 "int_loopback_test (offline)",
1618 "ext_loopback_test (offline)",
1619 "nvram_test (online) ",
1620 "interrupt_test (online) ",
1621 "link_test (online) "
de0c62db
DK		 1622};
1623
e9939c80
YM		 1624static u32 bnx2x_eee_to_adv(u32 eee_adv)
1625{
1626 u32 modes = 0;
1627
1628 if (eee_adv & SHMEM_EEE_100M_ADV)
1629 modes |= ADVERTISED_100baseT_Full;
1630 if (eee_adv & SHMEM_EEE_1G_ADV)
1631 modes |= ADVERTISED_1000baseT_Full;
1632 if (eee_adv & SHMEM_EEE_10G_ADV)
1633 modes |= ADVERTISED_10000baseT_Full;
1634
1635 return modes;
1636}
1637
1638static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1639{
1640 u32 eee_adv = 0;
1641 if (modes & ADVERTISED_100baseT_Full)
1642 eee_adv |= SHMEM_EEE_100M_ADV;
1643 if (modes & ADVERTISED_1000baseT_Full)
1644 eee_adv |= SHMEM_EEE_1G_ADV;
1645 if (modes & ADVERTISED_10000baseT_Full)
1646 eee_adv |= SHMEM_EEE_10G_ADV;
1647
1648 return eee_adv << shift;
1649}
1650
1651static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1652{
1653 struct bnx2x *bp = netdev_priv(dev);
1654 u32 eee_cfg;
1655
1656 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1657 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1658 return -EOPNOTSUPP;
1659 }
1660
08e9acc2 1661 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1662
1663 edata->supported =
1664 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1665 SHMEM_EEE_SUPPORTED_SHIFT);
1666
1667 edata->advertised =
1668 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1669 SHMEM_EEE_ADV_STATUS_SHIFT);
1670 edata->lp_advertised =
1671 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1672 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1673
1674 /* SHMEM value is in 16u units --> Convert to 1u units. */
1675 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1676
1677 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1678 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1679 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1680
1681 return 0;
1682}
1683
1684static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1685{
1686 struct bnx2x *bp = netdev_priv(dev);
1687 u32 eee_cfg;
1688 u32 advertised;
1689
1690 if (IS_MF(bp))
1691 return 0;
1692
1693 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1694 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1695 return -EOPNOTSUPP;
1696 }
1697
08e9acc2 1698 eee_cfg = bp->link_vars.eee_status;
e9939c80
YM		 1699
1700 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1701 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1702 return -EOPNOTSUPP;
1703 }
1704
1705 advertised = bnx2x_adv_to_eee(edata->advertised,
1706 SHMEM_EEE_ADV_STATUS_SHIFT);
1707 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1708 DP(BNX2X_MSG_ETHTOOL,
efc7ce03 1709 "Direct manipulation of EEE advertisement is not supported\n");
e9939c80
YM		 1710 return -EINVAL;
1711 }
1712
1713 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1714 DP(BNX2X_MSG_ETHTOOL,
1715 "Maximal Tx Lpi timer supported is %x(u)\n",
1716 EEE_MODE_TIMER_MASK);
1717 return -EINVAL;
1718 }
1719 if (edata->tx_lpi_enabled &&
1720 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1721 DP(BNX2X_MSG_ETHTOOL,
1722 "Minimal Tx Lpi timer supported is %d(u)\n",
1723 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1724 return -EINVAL;
1725 }
1726
1727 /* All is well; Apply changes*/
1728 if (edata->eee_enabled)
1729 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1730 else
1731 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1732
1733 if (edata->tx_lpi_enabled)
1734 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1735 else
1736 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1737
1738 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1739 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1740 EEE_MODE_TIMER_MASK) |
1741 EEE_MODE_OVERRIDE_NVRAM |
1742 EEE_MODE_OUTPUT_TIME;
1743
1744 /* Restart link to propogate changes */
1745 if (netif_running(dev)) {
1746 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
5d07d868 1747 bnx2x_force_link_reset(bp);
e9939c80
YM		 1748 bnx2x_link_set(bp);
1749 }
1750
1751 return 0;
1752}
1753
1754
619c5cb6
VZ		 1755enum {
1756 BNX2X_CHIP_E1_OFST = 0,
1757 BNX2X_CHIP_E1H_OFST,
1758 BNX2X_CHIP_E2_OFST,
1759 BNX2X_CHIP_E3_OFST,
1760 BNX2X_CHIP_E3B0_OFST,
1761 BNX2X_CHIP_MAX_OFST
1762};
1763
1764#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1765#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1766#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1767#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1768#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1769
1770#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1771#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1772
de0c62db
DK		 1773static int bnx2x_test_registers(struct bnx2x *bp)
1774{
1775 int idx, i, rc = -ENODEV;
619c5cb6 1776 u32 wr_val = 0, hw;
de0c62db
DK		 1777 int port = BP_PORT(bp);
1778 static const struct {
619c5cb6 1779 u32 hw;
de0c62db
DK		 1780 u32 offset0;
1781 u32 offset1;
1782 u32 mask;
1783 } reg_tbl[] = {
619c5cb6
VZ		 1784/* 0 */ { BNX2X_CHIP_MASK_ALL,
1785 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1786 { BNX2X_CHIP_MASK_ALL,
1787 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1788 { BNX2X_CHIP_MASK_E1X,
1789 HC_REG_AGG_INT_0, 4, 0x000003ff },
1790 { BNX2X_CHIP_MASK_ALL,
1791 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1792 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1793 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1794 { BNX2X_CHIP_MASK_E3B0,
1795 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1796 { BNX2X_CHIP_MASK_ALL,
1797 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1798 { BNX2X_CHIP_MASK_ALL,
1799 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1800 { BNX2X_CHIP_MASK_ALL,
1801 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1802 { BNX2X_CHIP_MASK_ALL,
1803 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1804/* 10 */ { BNX2X_CHIP_MASK_ALL,
1805 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1806 { BNX2X_CHIP_MASK_ALL,
1807 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1808 { BNX2X_CHIP_MASK_ALL,
1809 QM_REG_CONNNUM_0, 4, 0x000fffff },
1810 { BNX2X_CHIP_MASK_ALL,
1811 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1812 { BNX2X_CHIP_MASK_ALL,
1813 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1814 { BNX2X_CHIP_MASK_ALL,
1815 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1816 { BNX2X_CHIP_MASK_ALL,
1817 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1818 { BNX2X_CHIP_MASK_ALL,
1819 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1820 { BNX2X_CHIP_MASK_ALL,
1821 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1822 { BNX2X_CHIP_MASK_ALL,
1823 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1824/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1825 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1826 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1827 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1828 { BNX2X_CHIP_MASK_ALL,
1829 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1830 { BNX2X_CHIP_MASK_ALL,
1831 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1832 { BNX2X_CHIP_MASK_ALL,
1833 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1834 { BNX2X_CHIP_MASK_ALL,
1835 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1836 { BNX2X_CHIP_MASK_ALL,
1837 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1838 { BNX2X_CHIP_MASK_ALL,
1839 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1840 { BNX2X_CHIP_MASK_ALL,
1841 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1842 { BNX2X_CHIP_MASK_ALL,
1843 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1844/* 30 */ { BNX2X_CHIP_MASK_ALL,
1845 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1846 { BNX2X_CHIP_MASK_ALL,
1847 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1848 { BNX2X_CHIP_MASK_ALL,
1849 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1850 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1851 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1852 { BNX2X_CHIP_MASK_ALL,
1853 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1854 { BNX2X_CHIP_MASK_ALL,
1855 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1856 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1857 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1858 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1859 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1860
1861 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1862 };
1863
51c1a580
MS		 1864 if (!netif_running(bp->dev)) {
1865 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1866 "cannot access eeprom when the interface is down\n");
de0c62db 1867 return rc;
51c1a580 1868 }
de0c62db 1869
619c5cb6
VZ		 1870 if (CHIP_IS_E1(bp))
1871 hw = BNX2X_CHIP_MASK_E1;
1872 else if (CHIP_IS_E1H(bp))
1873 hw = BNX2X_CHIP_MASK_E1H;
1874 else if (CHIP_IS_E2(bp))
1875 hw = BNX2X_CHIP_MASK_E2;
1876 else if (CHIP_IS_E3B0(bp))
1877 hw = BNX2X_CHIP_MASK_E3B0;
1878 else /* e3 A0 */
1879 hw = BNX2X_CHIP_MASK_E3;
1880
de0c62db
DK		 1881 /* Repeat the test twice:
1882 First by writing 0x00000000, second by writing 0xffffffff */
1883 for (idx = 0; idx < 2; idx++) {
1884
1885 switch (idx) {
1886 case 0:
1887 wr_val = 0;
1888 break;
1889 case 1:
1890 wr_val = 0xffffffff;
1891 break;
1892 }
1893
1894 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1895 u32 offset, mask, save_val, val;
619c5cb6 1896 if (!(hw & reg_tbl[i].hw))
f2e0899f 1897 continue;
de0c62db
DK		 1898
1899 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1900 mask = reg_tbl[i].mask;
1901
1902 save_val = REG_RD(bp, offset);
1903
ec6ba945 1904 REG_WR(bp, offset, wr_val & mask);
f85582f8 1905
de0c62db
DK		 1906 val = REG_RD(bp, offset);
1907
1908 /* Restore the original register's value */
1909 REG_WR(bp, offset, save_val);
1910
1911 /* verify value is as expected */
1912 if ((val & mask) != (wr_val & mask)) {
51c1a580 1913 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1914 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1915 offset, val, wr_val, mask);
1916 goto test_reg_exit;
1917 }
1918 }
1919 }
1920
1921 rc = 0;
1922
1923test_reg_exit:
1924 return rc;
1925}
1926
1927static int bnx2x_test_memory(struct bnx2x *bp)
1928{
1929 int i, j, rc = -ENODEV;
619c5cb6 1930 u32 val, index;
de0c62db
DK		 1931 static const struct {
1932 u32 offset;
1933 int size;
1934 } mem_tbl[] = {
1935 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1936 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1937 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1938 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1939 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1940 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1941 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1942
1943 { 0xffffffff, 0 }
1944 };
619c5cb6 1945
de0c62db
DK		 1946 static const struct {
1947 char *name;
1948 u32 offset;
619c5cb6 1949 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1950 } prty_tbl[] = {
619c5cb6
VZ		 1951 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1952 {0x3ffc0, 0, 0, 0} },
1953 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1954 {0x2, 0x2, 0, 0} },
1955 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1956 {0, 0, 0, 0} },
1957 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1958 {0x3ffc0, 0, 0, 0} },
1959 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1960 {0x3ffc0, 0, 0, 0} },
1961 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1962 {0x3ffc1, 0, 0, 0} },
1963
1964 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1965 };
1966
51c1a580
MS		 1967 if (!netif_running(bp->dev)) {
1968 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1969 "cannot access eeprom when the interface is down\n");
de0c62db 1970 return rc;
51c1a580 1971 }
de0c62db 1972
619c5cb6
VZ		 1973 if (CHIP_IS_E1(bp))
1974 index = BNX2X_CHIP_E1_OFST;
1975 else if (CHIP_IS_E1H(bp))
1976 index = BNX2X_CHIP_E1H_OFST;
1977 else if (CHIP_IS_E2(bp))
1978 index = BNX2X_CHIP_E2_OFST;
1979 else /* e3 */
1980 index = BNX2X_CHIP_E3_OFST;
1981
f2e0899f
DK		 1982 /* pre-Check the parity status */
1983 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1984 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1985 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1986 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 1987 "%s is 0x%x\n", prty_tbl[i].name, val);
1988 goto test_mem_exit;
1989 }
1990 }
1991
de0c62db
DK		 1992 /* Go through all the memories */
1993 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1994 for (j = 0; j < mem_tbl[i].size; j++)
1995 REG_RD(bp, mem_tbl[i].offset + j*4);
1996
1997 /* Check the parity status */
1998 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1999 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 2000 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 2001 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 2002 "%s is 0x%x\n", prty_tbl[i].name, val);
2003 goto test_mem_exit;
2004 }
2005 }
2006
2007 rc = 0;
2008
2009test_mem_exit:
2010 return rc;
2011}
2012
a22f0788 2013static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 2014{
f2e0899f 2015 int cnt = 1400;
de0c62db 2016
619c5cb6 2017 if (link_up) {
a22f0788 2018 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 2019 msleep(20);
2020
2021 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 2022 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 2023
2024 cnt = 1400;
2025 while (!bp->link_vars.link_up && cnt--)
2026 msleep(20);
2027
2028 if (cnt <= 0 && !bp->link_vars.link_up)
2029 DP(BNX2X_MSG_ETHTOOL,
2030 "Timeout waiting for link init\n");
619c5cb6 2031 }
de0c62db
DK		 2032}
2033
619c5cb6 2034static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 2035{
2036 unsigned int pkt_size, num_pkts, i;
2037 struct sk_buff *skb;
2038 unsigned char *packet;
2039 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2040 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 2041 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 2042 u16 tx_start_idx, tx_idx;
2043 u16 rx_start_idx, rx_idx;
b0700b1e 2044 u16 pkt_prod, bd_prod;
de0c62db
DK		 2045 struct sw_tx_bd *tx_buf;
2046 struct eth_tx_start_bd *tx_start_bd;
de0c62db
DK		 2047 dma_addr_t mapping;
2048 union eth_rx_cqe *cqe;
619c5cb6 2049 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 2050 struct sw_rx_bd *rx_buf;
2051 u16 len;
2052 int rc = -ENODEV;
e52fcb24 2053 u8 *data;
8970b2e4
MS		 2054 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2055 txdata->txq_index);
de0c62db
DK		 2056
2057 /* check the loopback mode */
2058 switch (loopback_mode) {
2059 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 2060 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2061 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 2062 return -EINVAL;
8970b2e4 2063 }
de0c62db
DK		 2064 break;
2065 case BNX2X_MAC_LOOPBACK:
32911333
YR		 2066 if (CHIP_IS_E3(bp)) {
2067 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2068 if (bp->port.supported[cfg_idx] &
2069 (SUPPORTED_10000baseT_Full |
2070 SUPPORTED_20000baseMLD2_Full |
2071 SUPPORTED_20000baseKR2_Full))
2072 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2073 else
2074 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2075 } else
2076 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2077
de0c62db
DK		 2078 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2079 break;
8970b2e4
MS		 2080 case BNX2X_EXT_LOOPBACK:
2081 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2082 DP(BNX2X_MSG_ETHTOOL,
2083 "Can't configure external loopback\n");
2084 return -EINVAL;
2085 }
2086 break;
de0c62db 2087 default:
51c1a580 2088 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2089 return -EINVAL;
2090 }
2091
2092 /* prepare the loopback packet */
2093 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2094 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2095 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2096 if (!skb) {
51c1a580 2097 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2098 rc = -ENOMEM;
2099 goto test_loopback_exit;
2100 }
2101 packet = skb_put(skb, pkt_size);
2102 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2103 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2104 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2105 for (i = ETH_HLEN; i < pkt_size; i++)
2106 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2107 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2108 skb_headlen(skb), DMA_TO_DEVICE);
2109 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2110 rc = -ENOMEM;
2111 dev_kfree_skb(skb);
51c1a580 2112 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2113 goto test_loopback_exit;
2114 }
de0c62db
DK		 2115
2116 /* send the loopback packet */
2117 num_pkts = 0;
6383c0b3 2118 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2119 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2120
73dbb5e1
DK		 2121 netdev_tx_sent_queue(txq, skb->len);
2122
6383c0b3
AE		 2123 pkt_prod = txdata->tx_pkt_prod++;
2124 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2125 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2126 tx_buf->skb = skb;
2127 tx_buf->flags = 0;
2128
6383c0b3
AE		 2129 bd_prod = TX_BD(txdata->tx_bd_prod);
2130 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2131 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2132 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2133 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2134 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2135 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2136 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2137 SET_FLAG(tx_start_bd->general_data,
2138 ETH_TX_START_BD_HDR_NBDS,
2139 1);
96bed4b9
YM		 2140 SET_FLAG(tx_start_bd->general_data,
2141 ETH_TX_START_BD_PARSE_NBDS,
2142 0);
de0c62db
DK		 2143
2144 /* turn on parsing and get a BD */
2145 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2146
96bed4b9
YM		 2147 if (CHIP_IS_E1x(bp)) {
2148 u16 global_data = 0;
2149 struct eth_tx_parse_bd_e1x *pbd_e1x =
2150 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2151 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2152 SET_FLAG(global_data,
2153 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2154 pbd_e1x->global_data = cpu_to_le16(global_data);
2155 } else {
2156 u32 parsing_data = 0;
2157 struct eth_tx_parse_bd_e2 *pbd_e2 =
2158 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2159 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2160 SET_FLAG(parsing_data,
2161 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2162 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2163 }
de0c62db
DK		 2164 wmb();
2165
6383c0b3 2166 txdata->tx_db.data.prod += 2;
de0c62db 2167 barrier();
6383c0b3 2168 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2169
2170 mmiowb();
619c5cb6 2171 barrier();
de0c62db
DK		 2172
2173 num_pkts++;
6383c0b3 2174 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2175
2176 udelay(100);
2177
6383c0b3 2178 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2179 if (tx_idx != tx_start_idx + num_pkts)
2180 goto test_loopback_exit;
2181
f2e0899f
DK		 2182 /* Unlike HC IGU won't generate an interrupt for status block
2183 * updates that have been performed while interrupts were
2184 * disabled.
2185 */
e1210d12
ED		 2186 if (bp->common.int_block == INT_BLOCK_IGU) {
2187 /* Disable local BHes to prevent a dead-lock situation between
2188 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2189 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2190 */
2191 local_bh_disable();
6383c0b3 2192 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2193 local_bh_enable();
2194 }
f2e0899f 2195
de0c62db
DK		 2196 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2197 if (rx_idx != rx_start_idx + num_pkts)
2198 goto test_loopback_exit;
2199
b0700b1e 2200 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2201 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2202 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2203 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2204 goto test_loopback_rx_exit;
2205
621b4d66 2206 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2207 if (len != pkt_size)
2208 goto test_loopback_rx_exit;
2209
2210 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2211 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2212 dma_unmap_addr(rx_buf, mapping),
2213 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2214 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2215 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2216 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2217 goto test_loopback_rx_exit;
2218
2219 rc = 0;
2220
2221test_loopback_rx_exit:
2222
2223 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2224 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2225 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2226 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2227
2228 /* Update producers */
2229 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2230 fp_rx->rx_sge_prod);
2231
2232test_loopback_exit:
2233 bp->link_params.loopback_mode = LOOPBACK_NONE;
2234
2235 return rc;
2236}
2237
619c5cb6 2238static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2239{
2240 int rc = 0, res;
2241
2242 if (BP_NOMCP(bp))
2243 return rc;
2244
2245 if (!netif_running(bp->dev))
2246 return BNX2X_LOOPBACK_FAILED;
2247
2248 bnx2x_netif_stop(bp, 1);
2249 bnx2x_acquire_phy_lock(bp);
2250
619c5cb6 2251 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2252 if (res) {
51c1a580 2253 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2254 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2255 }
2256
619c5cb6 2257 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2258 if (res) {
51c1a580 2259 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2260 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2261 }
2262
2263 bnx2x_release_phy_lock(bp);
2264 bnx2x_netif_start(bp);
2265
2266 return rc;
2267}
2268
8970b2e4
MS		 2269static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2270{
2271 int rc;
2272 u8 is_serdes =
2273 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2274
2275 if (BP_NOMCP(bp))
2276 return -ENODEV;
2277
2278 if (!netif_running(bp->dev))
2279 return BNX2X_EXT_LOOPBACK_FAILED;
2280
5d07d868 2281 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
8970b2e4
MS		 2282 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2283 if (rc) {
2284 DP(BNX2X_MSG_ETHTOOL,
2285 "Can't perform self-test, nic_load (for external lb) failed\n");
2286 return -ENODEV;
2287 }
2288 bnx2x_wait_for_link(bp, 1, is_serdes);
2289
2290 bnx2x_netif_stop(bp, 1);
2291
2292 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2293 if (rc)
2294 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2295
2296 bnx2x_netif_start(bp);
2297
2298 return rc;
2299}
2300
de0c62db
DK		 2301#define CRC32_RESIDUAL 0xdebb20e3
2302
2303static int bnx2x_test_nvram(struct bnx2x *bp)
2304{
2305 static const struct {
2306 int offset;
2307 int size;
2308 } nvram_tbl[] = {
2309 { 0, 0x14 }, /* bootstrap */
2310 { 0x14, 0xec }, /* dir */
2311 { 0x100, 0x350 }, /* manuf_info */
2312 { 0x450, 0xf0 }, /* feature_info */
2313 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2314 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2315 { 0, 0 }
2316 };
afa13b4b
MY		 2317 __be32 *buf;
2318 u8 *data;
de0c62db
DK		 2319 int i, rc;
2320 u32 magic, crc;
2321
2322 if (BP_NOMCP(bp))
2323 return 0;
2324
afa13b4b
MY		 2325 buf = kmalloc(0x350, GFP_KERNEL);
2326 if (!buf) {
51c1a580 2327 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2328 rc = -ENOMEM;
2329 goto test_nvram_exit;
2330 }
2331 data = (u8 *)buf;
2332
de0c62db
DK		 2333 rc = bnx2x_nvram_read(bp, 0, data, 4);
2334 if (rc) {
51c1a580
MS		 2335 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2336 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2337 goto test_nvram_exit;
2338 }
2339
2340 magic = be32_to_cpu(buf[0]);
2341 if (magic != 0x669955aa) {
51c1a580
MS		 2342 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2343 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2344 rc = -ENODEV;
2345 goto test_nvram_exit;
2346 }
2347
2348 for (i = 0; nvram_tbl[i].size; i++) {
2349
2350 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2351 nvram_tbl[i].size);
2352 if (rc) {
51c1a580 2353 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2354 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2355 goto test_nvram_exit;
2356 }
2357
2358 crc = ether_crc_le(nvram_tbl[i].size, data);
2359 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2360 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2361 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2362 rc = -ENODEV;
2363 goto test_nvram_exit;
2364 }
2365 }
2366
2367test_nvram_exit:
afa13b4b 2368 kfree(buf);
de0c62db
DK		 2369 return rc;
2370}
2371
619c5cb6 2372/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2373static int bnx2x_test_intr(struct bnx2x *bp)
2374{
3b603066 2375 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2376
51c1a580
MS		 2377 if (!netif_running(bp->dev)) {
2378 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2379 "cannot access eeprom when the interface is down\n");
de0c62db 2380 return -ENODEV;
51c1a580 2381 }
de0c62db 2382
15192a8c 2383 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2384 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2385
619c5cb6
VZ		 2386 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2387
2388 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2389}
2390
2391static void bnx2x_self_test(struct net_device *dev,
2392 struct ethtool_test *etest, u64 *buf)
2393{
2394 struct bnx2x *bp = netdev_priv(dev);
a22f0788 2395 u8 is_serdes;
cf2c1df6
MS		 2396 int rc;
2397
de0c62db 2398 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2399 netdev_err(bp->dev,
2400 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2401 etest->flags |= ETH_TEST_FL_FAILED;
2402 return;
2403 }
8970b2e4
MS		 2404 DP(BNX2X_MSG_ETHTOOL,
2405 "Self-test command parameters: offline = %d, external_lb = %d\n",
2406 (etest->flags & ETH_TEST_FL_OFFLINE),
2407 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2408
cf2c1df6 2409 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2410
cf2c1df6
MS		 2411 if (!netif_running(dev)) {
2412 DP(BNX2X_MSG_ETHTOOL,
2413 "Can't perform self-test when interface is down\n");
de0c62db 2414 return;
cf2c1df6 2415 }
de0c62db 2416
a22f0788 2417 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db 2418
cf2c1df6
MS		 2419 /* offline tests are not supported in MF mode */
2420 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2421 int port = BP_PORT(bp);
2422 u32 val;
2423 u8 link_up;
2424
2425 /* save current value of input enable for TX port IF */
2426 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2427 /* disable input for TX port IF */
2428 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2429
a22f0788
YR		 2430 link_up = bp->link_vars.link_up;
2431
5d07d868 2432 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
cf2c1df6
MS		 2433 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2434 if (rc) {
2435 etest->flags |= ETH_TEST_FL_FAILED;
2436 DP(BNX2X_MSG_ETHTOOL,
2437 "Can't perform self-test, nic_load (for offline) failed\n");
2438 return;
2439 }
2440
de0c62db 2441 /* wait until link state is restored */
619c5cb6 2442 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2443
2444 if (bnx2x_test_registers(bp) != 0) {
2445 buf[0] = 1;
2446 etest->flags |= ETH_TEST_FL_FAILED;
2447 }
2448 if (bnx2x_test_memory(bp) != 0) {
2449 buf[1] = 1;
2450 etest->flags |= ETH_TEST_FL_FAILED;
2451 }
f85582f8 2452
8970b2e4 2453 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2454 if (buf[2] != 0)
2455 etest->flags |= ETH_TEST_FL_FAILED;
2456
8970b2e4
MS		 2457 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2458 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2459 if (buf[3] != 0)
2460 etest->flags |= ETH_TEST_FL_FAILED;
2461 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2462 }
2463
5d07d868 2464 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
de0c62db
DK		 2465
2466 /* restore input for TX port IF */
2467 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2468 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2469 if (rc) {
2470 etest->flags |= ETH_TEST_FL_FAILED;
2471 DP(BNX2X_MSG_ETHTOOL,
2472 "Can't perform self-test, nic_load (for online) failed\n");
2473 return;
2474 }
de0c62db 2475 /* wait until link state is restored */
a22f0788 2476 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2477 }
2478 if (bnx2x_test_nvram(bp) != 0) {
cf2c1df6
MS		 2479 if (!IS_MF(bp))
2480 buf[4] = 1;
2481 else
2482 buf[0] = 1;
de0c62db
DK		 2483 etest->flags |= ETH_TEST_FL_FAILED;
2484 }
2485 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 2486 if (!IS_MF(bp))
2487 buf[5] = 1;
2488 else
2489 buf[1] = 1;
de0c62db
DK		 2490 etest->flags |= ETH_TEST_FL_FAILED;
2491 }
633ac363
DK		 2492
2493 if (bnx2x_link_test(bp, is_serdes) != 0) {
cf2c1df6
MS		 2494 if (!IS_MF(bp))
2495 buf[6] = 1;
2496 else
2497 buf[2] = 1;
633ac363
DK		 2498 etest->flags |= ETH_TEST_FL_FAILED;
2499 }
de0c62db
DK		 2500
2501#ifdef BNX2X_EXTRA_DEBUG
2502 bnx2x_panic_dump(bp);
2503#endif
2504}
2505
de0c62db
DK		 2506#define IS_PORT_STAT(i) \
2507 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2508#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2509#define IS_MF_MODE_STAT(bp) \
2510 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2511
619c5cb6
VZ		 2512/* ethtool statistics are displayed for all regular ethernet queues and the
2513 * fcoe L2 queue if not disabled
2514 */
1191cb83 2515static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2516{
2517 return BNX2X_NUM_ETH_QUEUES(bp);
2518}
2519
de0c62db
DK		 2520static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2521{
2522 struct bnx2x *bp = netdev_priv(dev);
2523 int i, num_stats;
2524
2525 switch (stringset) {
2526 case ETH_SS_STATS:
2527 if (is_multi(bp)) {
619c5cb6 2528 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2529 BNX2X_NUM_Q_STATS;
2530 } else
2531 num_stats = 0;
2532 if (IS_MF_MODE_STAT(bp)) {
2533 for (i = 0; i < BNX2X_NUM_STATS; i++)
2534 if (IS_FUNC_STAT(i))
2535 num_stats++;
2536 } else
2537 num_stats += BNX2X_NUM_STATS;
2538
de0c62db
DK		 2539 return num_stats;
2540
2541 case ETH_SS_TEST:
cf2c1df6 2542 return BNX2X_NUM_TESTS(bp);
de0c62db
DK		 2543
2544 default:
2545 return -EINVAL;
2546 }
2547}
2548
2549static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2550{
2551 struct bnx2x *bp = netdev_priv(dev);
5889335c 2552 int i, j, k, start;
ec6ba945 2553 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2554
2555 switch (stringset) {
2556 case ETH_SS_STATS:
d5e83632 2557 k = 0;
de0c62db 2558 if (is_multi(bp)) {
619c5cb6 2559 for_each_eth_queue(bp, i) {
ec6ba945 2560 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2561 sprintf(queue_name, "%d", i);
de0c62db 2562 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2563 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2564 ETH_GSTRING_LEN,
2565 bnx2x_q_stats_arr[j].string,
2566 queue_name);
de0c62db
DK		 2567 k += BNX2X_NUM_Q_STATS;
2568 }
de0c62db 2569 }
d5e83632
YM		 2570
2571
2572 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2573 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2574 continue;
2575 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2576 bnx2x_stats_arr[i].string);
2577 j++;
2578 }
2579
de0c62db
DK		 2580 break;
2581
2582 case ETH_SS_TEST:
cf2c1df6
MS		 2583 /* First 4 tests cannot be done in MF mode */
2584 if (!IS_MF(bp))
2585 start = 0;
2586 else
2587 start = 4;
5889335c
MS		 2588 memcpy(buf, bnx2x_tests_str_arr + start,
2589 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
de0c62db
DK		 2590 }
2591}
2592
2593static void bnx2x_get_ethtool_stats(struct net_device *dev,
2594 struct ethtool_stats *stats, u64 *buf)
2595{
2596 struct bnx2x *bp = netdev_priv(dev);
2597 u32 *hw_stats, *offset;
d5e83632 2598 int i, j, k = 0;
de0c62db
DK		 2599
2600 if (is_multi(bp)) {
619c5cb6 2601 for_each_eth_queue(bp, i) {
15192a8c 2602 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 2603 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2604 if (bnx2x_q_stats_arr[j].size == 0) {
2605 /* skip this counter */
2606 buf[k + j] = 0;
2607 continue;
2608 }
2609 offset = (hw_stats +
2610 bnx2x_q_stats_arr[j].offset);
2611 if (bnx2x_q_stats_arr[j].size == 4) {
2612 /* 4-byte counter */
2613 buf[k + j] = (u64) *offset;
2614 continue;
2615 }
2616 /* 8-byte counter */
2617 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2618 }
2619 k += BNX2X_NUM_Q_STATS;
2620 }
d5e83632
YM		 2621 }
2622
2623 hw_stats = (u32 *)&bp->eth_stats;
2624 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2625 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2626 continue;
2627 if (bnx2x_stats_arr[i].size == 0) {
2628 /* skip this counter */
2629 buf[k + j] = 0;
2630 j++;
2631 continue;
de0c62db 2632 }
d5e83632
YM		 2633 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2634 if (bnx2x_stats_arr[i].size == 4) {
2635 /* 4-byte counter */
2636 buf[k + j] = (u64) *offset;
de0c62db 2637 j++;
d5e83632 2638 continue;
de0c62db 2639 }
d5e83632
YM		 2640 /* 8-byte counter */
2641 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2642 j++;
de0c62db
DK		 2643 }
2644}
2645
32d36134 2646static int bnx2x_set_phys_id(struct net_device *dev,
2647 enum ethtool_phys_id_state state)
de0c62db
DK		 2648{
2649 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2650
51c1a580
MS		 2651 if (!netif_running(dev)) {
2652 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2653 "cannot access eeprom when the interface is down\n");
32d36134 2654 return -EAGAIN;
51c1a580 2655 }
de0c62db 2656
51c1a580
MS		 2657 if (!bp->port.pmf) {
2658 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2659 return -EOPNOTSUPP;
51c1a580 2660 }
de0c62db 2661
32d36134 2662 switch (state) {
2663 case ETHTOOL_ID_ACTIVE:
fce55922 2664 return 1; /* cycle on/off once per second */
de0c62db 2665
32d36134 2666 case ETHTOOL_ID_ON:
8203c4b6 2667 bnx2x_acquire_phy_lock(bp);
32d36134 2668 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2669 LED_MODE_ON, SPEED_1000);
8203c4b6 2670 bnx2x_release_phy_lock(bp);
32d36134 2671 break;
de0c62db 2672
32d36134 2673 case ETHTOOL_ID_OFF:
8203c4b6 2674 bnx2x_acquire_phy_lock(bp);
32d36134 2675 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2676 LED_MODE_FRONT_PANEL_OFF, 0);
8203c4b6 2677 bnx2x_release_phy_lock(bp);
32d36134 2678 break;
2679
2680 case ETHTOOL_ID_INACTIVE:
8203c4b6 2681 bnx2x_acquire_phy_lock(bp);
e1943424
DM		 2682 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2683 LED_MODE_OPER,
2684 bp->link_vars.line_speed);
8203c4b6 2685 bnx2x_release_phy_lock(bp);
32d36134 2686 }
de0c62db
DK		 2687
2688 return 0;
2689}
2690
5d317c6a
MS		 2691static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2692{
2693
2694 switch (info->flow_type) {
2695 case TCP_V4_FLOW:
2696 case TCP_V6_FLOW:
2697 info->data = RXH_IP_SRC | RXH_IP_DST |
2698 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2699 break;
2700 case UDP_V4_FLOW:
2701 if (bp->rss_conf_obj.udp_rss_v4)
2702 info->data = RXH_IP_SRC | RXH_IP_DST |
2703 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2704 else
2705 info->data = RXH_IP_SRC | RXH_IP_DST;
2706 break;
2707 case UDP_V6_FLOW:
2708 if (bp->rss_conf_obj.udp_rss_v6)
2709 info->data = RXH_IP_SRC | RXH_IP_DST |
2710 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2711 else
2712 info->data = RXH_IP_SRC | RXH_IP_DST;
2713 break;
2714 case IPV4_FLOW:
2715 case IPV6_FLOW:
2716 info->data = RXH_IP_SRC | RXH_IP_DST;
2717 break;
2718 default:
2719 info->data = 0;
2720 break;
2721 }
2722
2723 return 0;
2724}
2725
ab532cf3 2726static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2727 u32 *rules __always_unused)
ab532cf3
TH		 2728{
2729 struct bnx2x *bp = netdev_priv(dev);
2730
2731 switch (info->cmd) {
2732 case ETHTOOL_GRXRINGS:
2733 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2734 return 0;
5d317c6a
MS		 2735 case ETHTOOL_GRXFH:
2736 return bnx2x_get_rss_flags(bp, info);
2737 default:
2738 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2739 return -EOPNOTSUPP;
2740 }
2741}
2742
2743static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2744{
2745 int udp_rss_requested;
2746
2747 DP(BNX2X_MSG_ETHTOOL,
2748 "Set rss flags command parameters: flow type = %d, data = %llu\n",
2749 info->flow_type, info->data);
2750
2751 switch (info->flow_type) {
2752 case TCP_V4_FLOW:
2753 case TCP_V6_FLOW:
2754 /* For TCP only 4-tupple hash is supported */
2755 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2756 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2757 DP(BNX2X_MSG_ETHTOOL,
2758 "Command parameters not supported\n");
2759 return -EINVAL;
2760 } else {
2761 return 0;
2762 }
2763
2764 case UDP_V4_FLOW:
2765 case UDP_V6_FLOW:
2766 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2767 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2768 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2769 udp_rss_requested = 1;
2770 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2771 udp_rss_requested = 0;
2772 else
2773 return -EINVAL;
2774 if ((info->flow_type == UDP_V4_FLOW) &&
2775 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2776 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2777 DP(BNX2X_MSG_ETHTOOL,
2778 "rss re-configured, UDP 4-tupple %s\n",
2779 udp_rss_requested ? "enabled" : "disabled");
2780 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2781 } else if ((info->flow_type == UDP_V6_FLOW) &&
2782 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
2783 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
2784 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2785 DP(BNX2X_MSG_ETHTOOL,
2786 "rss re-configured, UDP 4-tupple %s\n",
2787 udp_rss_requested ? "enabled" : "disabled");
2788 } else {
2789 return 0;
2790 }
2791 case IPV4_FLOW:
2792 case IPV6_FLOW:
2793 /* For IP only 2-tupple hash is supported */
2794 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
2795 DP(BNX2X_MSG_ETHTOOL,
2796 "Command parameters not supported\n");
2797 return -EINVAL;
2798 } else {
2799 return 0;
2800 }
2801 case SCTP_V4_FLOW:
2802 case AH_ESP_V4_FLOW:
2803 case AH_V4_FLOW:
2804 case ESP_V4_FLOW:
2805 case SCTP_V6_FLOW:
2806 case AH_ESP_V6_FLOW:
2807 case AH_V6_FLOW:
2808 case ESP_V6_FLOW:
2809 case IP_USER_FLOW:
2810 case ETHER_FLOW:
2811 /* RSS is not supported for these protocols */
2812 if (info->data) {
2813 DP(BNX2X_MSG_ETHTOOL,
2814 "Command parameters not supported\n");
2815 return -EINVAL;
2816 } else {
2817 return 0;
2818 }
2819 default:
2820 return -EINVAL;
2821 }
2822}
2823
2824static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
2825{
2826 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 2827
5d317c6a
MS		 2828 switch (info->cmd) {
2829 case ETHTOOL_SRXFH:
2830 return bnx2x_set_rss_flags(bp, info);
ab532cf3 2831 default:
51c1a580 2832 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 2833 return -EOPNOTSUPP;
2834 }
2835}
2836
7850f63f
BH		 2837static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2838{
96305234 2839 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 2840}
2841
2842static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 2843{
2844 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 2845 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2846 size_t i;
ab532cf3 2847
619c5cb6
VZ		 2848 /* Get the current configuration of the RSS indirection table */
2849 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2850
2851 /*
2852 * We can't use a memcpy() as an internal storage of an
2853 * indirection table is a u8 array while indir->ring_index
2854 * points to an array of u32.
2855 *
2856 * Indirection table contains the FW Client IDs, so we need to
2857 * align the returned table to the Client ID of the leading RSS
2858 * queue.
2859 */
7850f63f
BH		 2860 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2861 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 2862
ab532cf3
TH		 2863 return 0;
2864}
2865
7850f63f 2866static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 2867{
2868 struct bnx2x *bp = netdev_priv(dev);
2869 size_t i;
619c5cb6
VZ		 2870
2871 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 2872 /*
2873 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2874 * as an internal storage of an indirection table is a u8 array
2875 * while indir->ring_index points to an array of u32.
2876 *
2877 * Indirection table contains the FW Client IDs, so we need to
2878 * align the received table to the Client ID of the leading RSS
2879 * queue
2880 */
5d317c6a 2881 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 2882 }
ab532cf3 2883
5d317c6a 2884 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 2885}
2886
0e8d2ec5
MS		 2887/**
2888 * bnx2x_get_channels - gets the number of RSS queues.
2889 *
2890 * @dev: net device
2891 * @channels: returns the number of max / current queues
2892 */
2893static void bnx2x_get_channels(struct net_device *dev,
2894 struct ethtool_channels *channels)
2895{
2896 struct bnx2x *bp = netdev_priv(dev);
2897
2898 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
2899 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
2900}
2901
2902/**
2903 * bnx2x_change_num_queues - change the number of RSS queues.
2904 *
2905 * @bp: bnx2x private structure
2906 *
2907 * Re-configure interrupt mode to get the new number of MSI-X
2908 * vectors and re-add NAPI objects.
2909 */
2910static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
2911{
0e8d2ec5 2912 bnx2x_disable_msi(bp);
55c11941
MS		 2913 bp->num_ethernet_queues = num_rss;
2914 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
2915 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
0e8d2ec5 2916 bnx2x_set_int_mode(bp);
0e8d2ec5
MS		 2917}
2918
2919/**
2920 * bnx2x_set_channels - sets the number of RSS queues.
2921 *
2922 * @dev: net device
2923 * @channels: includes the number of queues requested
2924 */
2925static int bnx2x_set_channels(struct net_device *dev,
2926 struct ethtool_channels *channels)
2927{
2928 struct bnx2x *bp = netdev_priv(dev);
2929
2930
2931 DP(BNX2X_MSG_ETHTOOL,
2932 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
2933 channels->rx_count, channels->tx_count, channels->other_count,
2934 channels->combined_count);
2935
2936 /* We don't support separate rx / tx channels.
2937 * We don't allow setting 'other' channels.
2938 */
2939 if (channels->rx_count || channels->tx_count || channels->other_count
2940 || (channels->combined_count == 0) ||
2941 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
2942 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
2943 return -EINVAL;
2944 }
2945
2946 /* Check if there was a change in the active parameters */
2947 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
2948 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
2949 return 0;
2950 }
2951
2952 /* Set the requested number of queues in bp context.
2953 * Note that the actual number of queues created during load may be
2954 * less than requested if memory is low.
2955 */
2956 if (unlikely(!netif_running(dev))) {
2957 bnx2x_change_num_queues(bp, channels->combined_count);
2958 return 0;
2959 }
5d07d868 2960 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
0e8d2ec5
MS		 2961 bnx2x_change_num_queues(bp, channels->combined_count);
2962 return bnx2x_nic_load(bp, LOAD_NORMAL);
2963}
2964
de0c62db
DK		 2965static const struct ethtool_ops bnx2x_ethtool_ops = {
2966 .get_settings = bnx2x_get_settings,
2967 .set_settings = bnx2x_set_settings,
2968 .get_drvinfo = bnx2x_get_drvinfo,
2969 .get_regs_len = bnx2x_get_regs_len,
2970 .get_regs = bnx2x_get_regs,
2971 .get_wol = bnx2x_get_wol,
2972 .set_wol = bnx2x_set_wol,
2973 .get_msglevel = bnx2x_get_msglevel,
2974 .set_msglevel = bnx2x_set_msglevel,
2975 .nway_reset = bnx2x_nway_reset,
2976 .get_link = bnx2x_get_link,
2977 .get_eeprom_len = bnx2x_get_eeprom_len,
2978 .get_eeprom = bnx2x_get_eeprom,
2979 .set_eeprom = bnx2x_set_eeprom,
2980 .get_coalesce = bnx2x_get_coalesce,
2981 .set_coalesce = bnx2x_set_coalesce,
2982 .get_ringparam = bnx2x_get_ringparam,
2983 .set_ringparam = bnx2x_set_ringparam,
2984 .get_pauseparam = bnx2x_get_pauseparam,
2985 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2986 .self_test = bnx2x_self_test,
2987 .get_sset_count = bnx2x_get_sset_count,
2988 .get_strings = bnx2x_get_strings,
32d36134 2989 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2990 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 2991 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 2992 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 2993 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 2994 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2995 .set_rxfh_indir = bnx2x_set_rxfh_indir,
0e8d2ec5
MS		 2996 .get_channels = bnx2x_get_channels,
2997 .set_channels = bnx2x_set_channels,
24ea818e
YM		 2998 .get_module_info = bnx2x_get_module_info,
2999 .get_module_eeprom = bnx2x_get_module_eeprom,
e9939c80
YM		 3000 .get_eee = bnx2x_get_eee,
3001 .set_eee = bnx2x_set_eee,
be53ce1e 3002 .get_ts_info = ethtool_op_get_ts_info,
de0c62db
DK		 3003};
3004
3005void bnx2x_set_ethtool_ops(struct net_device *netdev)
3006{
3007 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3008}
kernel source for telekom puls (alcatel/mediatek)