Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
1da177e4 | 19 | #include <asm/glue.h> |
1da177e4 | 20 | #include <asm/vfpmacros.h> |
a09e64fb | 21 | #include <mach/entry-macro.S> |
d6551e88 | 22 | #include <asm/thread_notify.h> |
c4c5716e | 23 | #include <asm/unwind.h> |
cc20d429 | 24 | #include <asm/unistd.h> |
f159f4ed | 25 | #include <asm/tls.h> |
1da177e4 LT |
26 | |
27 | #include "entry-header.S" | |
cd544ce7 | 28 | #include <asm/entry-macro-multi.S> |
1da177e4 | 29 | |
187a51ad RK |
30 | /* |
31 | * Interrupt handling. Preserves r7, r8, r9 | |
32 | */ | |
33 | .macro irq_handler | |
52108641 | 34 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
35 | ldr r5, =handle_arch_irq | |
36 | mov r0, sp | |
37 | ldr r5, [r5] | |
38 | adr lr, BSYM(9997f) | |
39 | teq r5, #0 | |
40 | movne pc, r5 | |
37ee16ae | 41 | #endif |
cd544ce7 | 42 | arch_irq_handler_default |
f00ec48f | 43 | 9997: |
187a51ad RK |
44 | .endm |
45 | ||
785d3cd2 NP |
46 | #ifdef CONFIG_KPROBES |
47 | .section .kprobes.text,"ax",%progbits | |
48 | #else | |
49 | .text | |
50 | #endif | |
51 | ||
1da177e4 LT |
52 | /* |
53 | * Invalid mode handlers | |
54 | */ | |
ccea7a19 RK |
55 | .macro inv_entry, reason |
56 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
57 | ARM( stmib sp, {r1 - lr} ) |
58 | THUMB( stmia sp, {r0 - r12} ) | |
59 | THUMB( str sp, [sp, #S_SP] ) | |
60 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
61 | mov r1, #\reason |
62 | .endm | |
63 | ||
64 | __pabt_invalid: | |
ccea7a19 RK |
65 | inv_entry BAD_PREFETCH |
66 | b common_invalid | |
93ed3970 | 67 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
68 | |
69 | __dabt_invalid: | |
ccea7a19 RK |
70 | inv_entry BAD_DATA |
71 | b common_invalid | |
93ed3970 | 72 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
73 | |
74 | __irq_invalid: | |
ccea7a19 RK |
75 | inv_entry BAD_IRQ |
76 | b common_invalid | |
93ed3970 | 77 | ENDPROC(__irq_invalid) |
1da177e4 LT |
78 | |
79 | __und_invalid: | |
ccea7a19 RK |
80 | inv_entry BAD_UNDEFINSTR |
81 | ||
82 | @ | |
83 | @ XXX fall through to common_invalid | |
84 | @ | |
85 | ||
86 | @ | |
87 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
88 | @ | |
89 | common_invalid: | |
90 | zero_fp | |
91 | ||
92 | ldmia r0, {r4 - r6} | |
93 | add r0, sp, #S_PC @ here for interlock avoidance | |
94 | mov r7, #-1 @ "" "" "" "" | |
95 | str r4, [sp] @ save preserved r0 | |
96 | stmia r0, {r5 - r7} @ lr_<exception>, | |
97 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 98 | |
1da177e4 | 99 | mov r0, sp |
1da177e4 | 100 | b bad_mode |
93ed3970 | 101 | ENDPROC(__und_invalid) |
1da177e4 LT |
102 | |
103 | /* | |
104 | * SVC mode handlers | |
105 | */ | |
2dede2d8 NP |
106 | |
107 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
108 | #define SPFIX(code...) code | |
109 | #else | |
110 | #define SPFIX(code...) | |
111 | #endif | |
112 | ||
d30a0c8b | 113 | .macro svc_entry, stack_hole=0 |
c4c5716e CM |
114 | UNWIND(.fnstart ) |
115 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
116 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
117 | #ifdef CONFIG_THUMB2_KERNEL | |
118 | SPFIX( str r0, [sp] ) @ temporarily saved | |
119 | SPFIX( mov r0, sp ) | |
120 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
121 | SPFIX( ldr r0, [sp] ) @ restored | |
122 | #else | |
2dede2d8 | 123 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
124 | #endif |
125 | SPFIX( subeq sp, sp, #4 ) | |
126 | stmia sp, {r1 - r12} | |
ccea7a19 RK |
127 | |
128 | ldmia r0, {r1 - r3} | |
b86040a5 | 129 | add r5, sp, #S_SP - 4 @ here for interlock avoidance |
ccea7a19 | 130 | mov r4, #-1 @ "" "" "" "" |
b86040a5 CM |
131 | add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
132 | SPFIX( addeq r0, r0, #4 ) | |
133 | str r1, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
134 | @ from the exception stack |
135 | ||
1da177e4 LT |
136 | mov r1, lr |
137 | ||
138 | @ | |
139 | @ We are now ready to fill in the remaining blanks on the stack: | |
140 | @ | |
141 | @ r0 - sp_svc | |
142 | @ r1 - lr_svc | |
143 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
144 | @ r3 - spsr_<exception> | |
145 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
146 | @ | |
147 | stmia r5, {r0 - r4} | |
148 | .endm | |
149 | ||
150 | .align 5 | |
151 | __dabt_svc: | |
ccea7a19 | 152 | svc_entry |
1da177e4 LT |
153 | |
154 | @ | |
155 | @ get ready to re-enable interrupts if appropriate | |
156 | @ | |
157 | mrs r9, cpsr | |
158 | tst r3, #PSR_I_BIT | |
159 | biceq r9, r9, #PSR_I_BIT | |
160 | ||
161 | @ | |
162 | @ Call the processor-specific abort handler: | |
163 | @ | |
164 | @ r2 - aborted context pc | |
165 | @ r3 - aborted context cpsr | |
166 | @ | |
167 | @ The abort handler must return the aborted address in r0, and | |
168 | @ the fault status register in r1. r9 must be preserved. | |
169 | @ | |
48d7927b | 170 | #ifdef MULTI_DABORT |
1da177e4 LT |
171 | ldr r4, .LCprocfns |
172 | mov lr, pc | |
48d7927b | 173 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
1da177e4 | 174 | #else |
48d7927b | 175 | bl CPU_DABORT_HANDLER |
1da177e4 LT |
176 | #endif |
177 | ||
178 | @ | |
179 | @ set desired IRQ state, then call main handler | |
180 | @ | |
7e202696 | 181 | debug_entry r1 |
1da177e4 LT |
182 | msr cpsr_c, r9 |
183 | mov r2, sp | |
184 | bl do_DataAbort | |
185 | ||
186 | @ | |
187 | @ IRQs off again before pulling preserved data off the stack | |
188 | @ | |
ac78884e | 189 | disable_irq_notrace |
1da177e4 LT |
190 | |
191 | @ | |
192 | @ restore SPSR and restart the instruction | |
193 | @ | |
b86040a5 CM |
194 | ldr r2, [sp, #S_PSR] |
195 | svc_exit r2 @ return from exception | |
c4c5716e | 196 | UNWIND(.fnend ) |
93ed3970 | 197 | ENDPROC(__dabt_svc) |
1da177e4 LT |
198 | |
199 | .align 5 | |
200 | __irq_svc: | |
ccea7a19 RK |
201 | svc_entry |
202 | ||
ac78884e RK |
203 | #ifdef CONFIG_TRACE_IRQFLAGS |
204 | bl trace_hardirqs_off | |
205 | #endif | |
1da177e4 | 206 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
207 | get_thread_info tsk |
208 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
209 | add r7, r8, #1 @ increment it | |
210 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 211 | #endif |
ccea7a19 | 212 | |
187a51ad | 213 | irq_handler |
1da177e4 | 214 | #ifdef CONFIG_PREEMPT |
28fab1a2 | 215 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count |
706fdd9f | 216 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
217 | teq r8, #0 @ if preempt count != 0 |
218 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
219 | tst r0, #_TIF_NEED_RESCHED |
220 | blne svc_preempt | |
1da177e4 | 221 | #endif |
b86040a5 | 222 | ldr r4, [sp, #S_PSR] @ irqs are already disabled |
7ad1bcb2 | 223 | #ifdef CONFIG_TRACE_IRQFLAGS |
b86040a5 | 224 | tst r4, #PSR_I_BIT |
7ad1bcb2 RK |
225 | bleq trace_hardirqs_on |
226 | #endif | |
b86040a5 | 227 | svc_exit r4 @ return from exception |
c4c5716e | 228 | UNWIND(.fnend ) |
93ed3970 | 229 | ENDPROC(__irq_svc) |
1da177e4 LT |
230 | |
231 | .ltorg | |
232 | ||
233 | #ifdef CONFIG_PREEMPT | |
234 | svc_preempt: | |
28fab1a2 | 235 | mov r8, lr |
1da177e4 | 236 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 237 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 238 | tst r0, #_TIF_NEED_RESCHED |
28fab1a2 | 239 | moveq pc, r8 @ go again |
1da177e4 LT |
240 | b 1b |
241 | #endif | |
242 | ||
243 | .align 5 | |
244 | __und_svc: | |
d30a0c8b NP |
245 | #ifdef CONFIG_KPROBES |
246 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
247 | @ it obviously needs free stack space which then will belong to | |
248 | @ the saved context. | |
249 | svc_entry 64 | |
250 | #else | |
ccea7a19 | 251 | svc_entry |
d30a0c8b | 252 | #endif |
1da177e4 LT |
253 | |
254 | @ | |
255 | @ call emulation code, which returns using r9 if it has emulated | |
256 | @ the instruction, or the more conventional lr if we are to treat | |
257 | @ this as a real undefined instruction | |
258 | @ | |
259 | @ r0 - instruction | |
260 | @ | |
83e686ea | 261 | #ifndef CONFIG_THUMB2_KERNEL |
1da177e4 | 262 | ldr r0, [r2, #-4] |
83e686ea CM |
263 | #else |
264 | ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2 | |
265 | and r9, r0, #0xf800 | |
266 | cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 | |
267 | ldrhhs r9, [r2] @ bottom 16 bits | |
268 | orrhs r0, r9, r0, lsl #16 | |
269 | #endif | |
b86040a5 | 270 | adr r9, BSYM(1f) |
1da177e4 LT |
271 | bl call_fpe |
272 | ||
273 | mov r0, sp @ struct pt_regs *regs | |
274 | bl do_undefinstr | |
275 | ||
276 | @ | |
277 | @ IRQs off again before pulling preserved data off the stack | |
278 | @ | |
ac78884e | 279 | 1: disable_irq_notrace |
1da177e4 LT |
280 | |
281 | @ | |
282 | @ restore SPSR and restart the instruction | |
283 | @ | |
b86040a5 CM |
284 | ldr r2, [sp, #S_PSR] @ Get SVC cpsr |
285 | svc_exit r2 @ return from exception | |
c4c5716e | 286 | UNWIND(.fnend ) |
93ed3970 | 287 | ENDPROC(__und_svc) |
1da177e4 LT |
288 | |
289 | .align 5 | |
290 | __pabt_svc: | |
ccea7a19 | 291 | svc_entry |
1da177e4 LT |
292 | |
293 | @ | |
294 | @ re-enable interrupts if appropriate | |
295 | @ | |
296 | mrs r9, cpsr | |
297 | tst r3, #PSR_I_BIT | |
298 | biceq r9, r9, #PSR_I_BIT | |
1da177e4 | 299 | |
48d7927b | 300 | mov r0, r2 @ pass address of aborted instruction. |
4fb28474 | 301 | #ifdef MULTI_PABORT |
48d7927b PB |
302 | ldr r4, .LCprocfns |
303 | mov lr, pc | |
304 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | |
305 | #else | |
4fb28474 | 306 | bl CPU_PABORT_HANDLER |
48d7927b | 307 | #endif |
7e202696 | 308 | debug_entry r1 |
48d7927b | 309 | msr cpsr_c, r9 @ Maybe enable interrupts |
4fb28474 | 310 | mov r2, sp @ regs |
1da177e4 LT |
311 | bl do_PrefetchAbort @ call abort handler |
312 | ||
313 | @ | |
314 | @ IRQs off again before pulling preserved data off the stack | |
315 | @ | |
ac78884e | 316 | disable_irq_notrace |
1da177e4 LT |
317 | |
318 | @ | |
319 | @ restore SPSR and restart the instruction | |
320 | @ | |
b86040a5 CM |
321 | ldr r2, [sp, #S_PSR] |
322 | svc_exit r2 @ return from exception | |
c4c5716e | 323 | UNWIND(.fnend ) |
93ed3970 | 324 | ENDPROC(__pabt_svc) |
1da177e4 LT |
325 | |
326 | .align 5 | |
49f680ea RK |
327 | .LCcralign: |
328 | .word cr_alignment | |
48d7927b | 329 | #ifdef MULTI_DABORT |
1da177e4 LT |
330 | .LCprocfns: |
331 | .word processor | |
332 | #endif | |
333 | .LCfp: | |
334 | .word fp_enter | |
1da177e4 LT |
335 | |
336 | /* | |
337 | * User mode handlers | |
2dede2d8 NP |
338 | * |
339 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 340 | */ |
2dede2d8 NP |
341 | |
342 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
343 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
344 | #endif | |
345 | ||
ccea7a19 | 346 | .macro usr_entry |
c4c5716e CM |
347 | UNWIND(.fnstart ) |
348 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 349 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
350 | ARM( stmib sp, {r1 - r12} ) |
351 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 RK |
352 | |
353 | ldmia r0, {r1 - r3} | |
354 | add r0, sp, #S_PC @ here for interlock avoidance | |
355 | mov r4, #-1 @ "" "" "" "" | |
356 | ||
357 | str r1, [sp] @ save the "real" r0 copied | |
358 | @ from the exception stack | |
1da177e4 LT |
359 | |
360 | @ | |
361 | @ We are now ready to fill in the remaining blanks on the stack: | |
362 | @ | |
363 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
364 | @ r3 - spsr_<exception> | |
365 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
366 | @ | |
367 | @ Also, separately save sp_usr and lr_usr | |
368 | @ | |
ccea7a19 | 369 | stmia r0, {r2 - r4} |
b86040a5 CM |
370 | ARM( stmdb r0, {sp, lr}^ ) |
371 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 LT |
372 | |
373 | @ | |
374 | @ Enable the alignment trap while in kernel mode | |
375 | @ | |
49f680ea | 376 | alignment_trap r0 |
1da177e4 LT |
377 | |
378 | @ | |
379 | @ Clear FP to mark the first stack frame | |
380 | @ | |
381 | zero_fp | |
382 | .endm | |
383 | ||
b49c0f24 NP |
384 | .macro kuser_cmpxchg_check |
385 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
386 | #ifndef CONFIG_MMU | |
387 | #warning "NPTL on non MMU needs fixing" | |
388 | #else | |
389 | @ Make sure our user space atomic helper is restarted | |
390 | @ if it was interrupted in a critical region. Here we | |
391 | @ perform a quick test inline since it should be false | |
392 | @ 99.9999% of the time. The rest is done out of line. | |
393 | cmp r2, #TASK_SIZE | |
394 | blhs kuser_cmpxchg_fixup | |
395 | #endif | |
396 | #endif | |
397 | .endm | |
398 | ||
1da177e4 LT |
399 | .align 5 |
400 | __dabt_usr: | |
ccea7a19 | 401 | usr_entry |
b49c0f24 | 402 | kuser_cmpxchg_check |
1da177e4 LT |
403 | |
404 | @ | |
405 | @ Call the processor-specific abort handler: | |
406 | @ | |
407 | @ r2 - aborted context pc | |
408 | @ r3 - aborted context cpsr | |
409 | @ | |
410 | @ The abort handler must return the aborted address in r0, and | |
411 | @ the fault status register in r1. | |
412 | @ | |
48d7927b | 413 | #ifdef MULTI_DABORT |
1da177e4 LT |
414 | ldr r4, .LCprocfns |
415 | mov lr, pc | |
48d7927b | 416 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
1da177e4 | 417 | #else |
48d7927b | 418 | bl CPU_DABORT_HANDLER |
1da177e4 LT |
419 | #endif |
420 | ||
421 | @ | |
422 | @ IRQs on, then call the main handler | |
423 | @ | |
7e202696 | 424 | debug_entry r1 |
1ec42c0c | 425 | enable_irq |
1da177e4 | 426 | mov r2, sp |
b86040a5 | 427 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 428 | b do_DataAbort |
c4c5716e | 429 | UNWIND(.fnend ) |
93ed3970 | 430 | ENDPROC(__dabt_usr) |
1da177e4 LT |
431 | |
432 | .align 5 | |
433 | __irq_usr: | |
ccea7a19 | 434 | usr_entry |
b49c0f24 | 435 | kuser_cmpxchg_check |
1da177e4 | 436 | |
706fdd9f | 437 | get_thread_info tsk |
1da177e4 | 438 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
439 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
440 | add r7, r8, #1 @ increment it | |
441 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 442 | #endif |
ccea7a19 | 443 | |
187a51ad | 444 | irq_handler |
1da177e4 | 445 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
446 | ldr r0, [tsk, #TI_PREEMPT] |
447 | str r8, [tsk, #TI_PREEMPT] | |
1da177e4 | 448 | teq r0, r7 |
b86040a5 CM |
449 | ARM( strne r0, [r0, -r0] ) |
450 | THUMB( movne r0, #0 ) | |
451 | THUMB( strne r0, [r0] ) | |
1da177e4 | 452 | #endif |
ccea7a19 | 453 | |
1da177e4 LT |
454 | mov why, #0 |
455 | b ret_to_user | |
c4c5716e | 456 | UNWIND(.fnend ) |
93ed3970 | 457 | ENDPROC(__irq_usr) |
1da177e4 LT |
458 | |
459 | .ltorg | |
460 | ||
461 | .align 5 | |
462 | __und_usr: | |
ccea7a19 | 463 | usr_entry |
1da177e4 | 464 | |
1da177e4 LT |
465 | @ |
466 | @ fall through to the emulation code, which returns using r9 if | |
467 | @ it has emulated the instruction, or the more conventional lr | |
468 | @ if we are to treat this as a real undefined instruction | |
469 | @ | |
470 | @ r0 - instruction | |
471 | @ | |
b86040a5 CM |
472 | adr r9, BSYM(ret_from_exception) |
473 | adr lr, BSYM(__und_usr_unknown) | |
cb170a45 | 474 | tst r3, #PSR_T_BIT @ Thumb mode? |
b86040a5 | 475 | itet eq @ explicit IT needed for the 1f label |
cb170a45 PB |
476 | subeq r4, r2, #4 @ ARM instr at LR - 4 |
477 | subne r4, r2, #2 @ Thumb instr at LR - 2 | |
478 | 1: ldreqt r0, [r4] | |
26584853 CM |
479 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
480 | reveq r0, r0 @ little endian instruction | |
481 | #endif | |
cb170a45 PB |
482 | beq call_fpe |
483 | @ Thumb instruction | |
484 | #if __LINUX_ARM_ARCH__ >= 7 | |
b86040a5 CM |
485 | 2: |
486 | ARM( ldrht r5, [r4], #2 ) | |
487 | THUMB( ldrht r5, [r4] ) | |
488 | THUMB( add r4, r4, #2 ) | |
cb170a45 PB |
489 | and r0, r5, #0xf800 @ mask bits 111x x... .... .... |
490 | cmp r0, #0xe800 @ 32bit instruction if xx != 0 | |
491 | blo __und_usr_unknown | |
492 | 3: ldrht r0, [r4] | |
493 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | |
494 | orr r0, r0, r5, lsl #16 | |
495 | #else | |
496 | b __und_usr_unknown | |
497 | #endif | |
c4c5716e | 498 | UNWIND(.fnend ) |
93ed3970 | 499 | ENDPROC(__und_usr) |
cb170a45 | 500 | |
1da177e4 LT |
501 | @ |
502 | @ fallthrough to call_fpe | |
503 | @ | |
504 | ||
505 | /* | |
506 | * The out of line fixup for the ldrt above. | |
507 | */ | |
4260415f | 508 | .pushsection .fixup, "ax" |
cb170a45 | 509 | 4: mov pc, r9 |
4260415f RK |
510 | .popsection |
511 | .pushsection __ex_table,"a" | |
cb170a45 PB |
512 | .long 1b, 4b |
513 | #if __LINUX_ARM_ARCH__ >= 7 | |
514 | .long 2b, 4b | |
515 | .long 3b, 4b | |
516 | #endif | |
4260415f | 517 | .popsection |
1da177e4 LT |
518 | |
519 | /* | |
520 | * Check whether the instruction is a co-processor instruction. | |
521 | * If yes, we need to call the relevant co-processor handler. | |
522 | * | |
523 | * Note that we don't do a full check here for the co-processor | |
524 | * instructions; all instructions with bit 27 set are well | |
525 | * defined. The only instructions that should fault are the | |
526 | * co-processor instructions. However, we have to watch out | |
527 | * for the ARM6/ARM7 SWI bug. | |
528 | * | |
b5872db4 CM |
529 | * NEON is a special case that has to be handled here. Not all |
530 | * NEON instructions are co-processor instructions, so we have | |
531 | * to make a special case of checking for them. Plus, there's | |
532 | * five groups of them, so we have a table of mask/opcode pairs | |
533 | * to check against, and if any match then we branch off into the | |
534 | * NEON handler code. | |
535 | * | |
1da177e4 LT |
536 | * Emulators may wish to make use of the following registers: |
537 | * r0 = instruction opcode. | |
538 | * r2 = PC+4 | |
db6ccbb6 | 539 | * r9 = normal "successful" return address |
1da177e4 | 540 | * r10 = this threads thread_info structure. |
db6ccbb6 | 541 | * lr = unrecognised instruction return address |
1da177e4 | 542 | */ |
cb170a45 PB |
543 | @ |
544 | @ Fall-through from Thumb-2 __und_usr | |
545 | @ | |
546 | #ifdef CONFIG_NEON | |
547 | adr r6, .LCneon_thumb_opcodes | |
548 | b 2f | |
549 | #endif | |
1da177e4 | 550 | call_fpe: |
b5872db4 | 551 | #ifdef CONFIG_NEON |
cb170a45 | 552 | adr r6, .LCneon_arm_opcodes |
b5872db4 CM |
553 | 2: |
554 | ldr r7, [r6], #4 @ mask value | |
555 | cmp r7, #0 @ end mask? | |
556 | beq 1f | |
557 | and r8, r0, r7 | |
558 | ldr r7, [r6], #4 @ opcode bits matching in mask | |
559 | cmp r8, r7 @ NEON instruction? | |
560 | bne 2b | |
561 | get_thread_info r10 | |
562 | mov r7, #1 | |
563 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
564 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
565 | b do_vfp @ let VFP handler handle this | |
566 | 1: | |
567 | #endif | |
1da177e4 | 568 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 569 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
1da177e4 LT |
570 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
571 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
572 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
573 | #endif | |
574 | moveq pc, lr | |
575 | get_thread_info r10 @ get current thread | |
576 | and r8, r0, #0x00000f00 @ mask out CP number | |
b86040a5 | 577 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
578 | mov r7, #1 |
579 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
580 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
581 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
582 | #ifdef CONFIG_IWMMXT |
583 | @ Test if we need to give access to iWMMXt coprocessors | |
584 | ldr r5, [r10, #TI_FLAGS] | |
585 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
586 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
587 | bcs iwmmxt_task_enable | |
588 | #endif | |
b86040a5 CM |
589 | ARM( add pc, pc, r8, lsr #6 ) |
590 | THUMB( lsl r8, r8, #2 ) | |
591 | THUMB( add pc, r8 ) | |
592 | nop | |
593 | ||
a771fe6e | 594 | movw_pc lr @ CP#0 |
b86040a5 CM |
595 | W(b) do_fpe @ CP#1 (FPE) |
596 | W(b) do_fpe @ CP#2 (FPE) | |
a771fe6e | 597 | movw_pc lr @ CP#3 |
c17fad11 LB |
598 | #ifdef CONFIG_CRUNCH |
599 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
600 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
601 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
602 | #else | |
a771fe6e CM |
603 | movw_pc lr @ CP#4 |
604 | movw_pc lr @ CP#5 | |
605 | movw_pc lr @ CP#6 | |
c17fad11 | 606 | #endif |
a771fe6e CM |
607 | movw_pc lr @ CP#7 |
608 | movw_pc lr @ CP#8 | |
609 | movw_pc lr @ CP#9 | |
1da177e4 | 610 | #ifdef CONFIG_VFP |
b86040a5 CM |
611 | W(b) do_vfp @ CP#10 (VFP) |
612 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 613 | #else |
a771fe6e CM |
614 | movw_pc lr @ CP#10 (VFP) |
615 | movw_pc lr @ CP#11 (VFP) | |
1da177e4 | 616 | #endif |
a771fe6e CM |
617 | movw_pc lr @ CP#12 |
618 | movw_pc lr @ CP#13 | |
619 | movw_pc lr @ CP#14 (Debug) | |
620 | movw_pc lr @ CP#15 (Control) | |
1da177e4 | 621 | |
b5872db4 CM |
622 | #ifdef CONFIG_NEON |
623 | .align 6 | |
624 | ||
cb170a45 | 625 | .LCneon_arm_opcodes: |
b5872db4 CM |
626 | .word 0xfe000000 @ mask |
627 | .word 0xf2000000 @ opcode | |
628 | ||
629 | .word 0xff100000 @ mask | |
630 | .word 0xf4000000 @ opcode | |
631 | ||
cb170a45 PB |
632 | .word 0x00000000 @ mask |
633 | .word 0x00000000 @ opcode | |
634 | ||
635 | .LCneon_thumb_opcodes: | |
636 | .word 0xef000000 @ mask | |
637 | .word 0xef000000 @ opcode | |
638 | ||
639 | .word 0xff100000 @ mask | |
640 | .word 0xf9000000 @ opcode | |
641 | ||
b5872db4 CM |
642 | .word 0x00000000 @ mask |
643 | .word 0x00000000 @ opcode | |
644 | #endif | |
645 | ||
1da177e4 | 646 | do_fpe: |
5d25ac03 | 647 | enable_irq |
1da177e4 LT |
648 | ldr r4, .LCfp |
649 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
650 | ldr pc, [r4] @ Call FP module USR entry point | |
651 | ||
652 | /* | |
653 | * The FP module is called with these registers set: | |
654 | * r0 = instruction | |
655 | * r2 = PC+4 | |
656 | * r9 = normal "successful" return address | |
657 | * r10 = FP workspace | |
658 | * lr = unrecognised FP instruction return address | |
659 | */ | |
660 | ||
124efc27 | 661 | .pushsection .data |
1da177e4 | 662 | ENTRY(fp_enter) |
db6ccbb6 | 663 | .word no_fp |
124efc27 | 664 | .popsection |
1da177e4 | 665 | |
83e686ea CM |
666 | ENTRY(no_fp) |
667 | mov pc, lr | |
668 | ENDPROC(no_fp) | |
db6ccbb6 RK |
669 | |
670 | __und_usr_unknown: | |
ecbab71c | 671 | enable_irq |
1da177e4 | 672 | mov r0, sp |
b86040a5 | 673 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 674 | b do_undefinstr |
93ed3970 | 675 | ENDPROC(__und_usr_unknown) |
1da177e4 LT |
676 | |
677 | .align 5 | |
678 | __pabt_usr: | |
ccea7a19 | 679 | usr_entry |
1da177e4 | 680 | |
48d7927b | 681 | mov r0, r2 @ pass address of aborted instruction. |
4fb28474 | 682 | #ifdef MULTI_PABORT |
48d7927b PB |
683 | ldr r4, .LCprocfns |
684 | mov lr, pc | |
685 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | |
686 | #else | |
4fb28474 | 687 | bl CPU_PABORT_HANDLER |
48d7927b | 688 | #endif |
7e202696 | 689 | debug_entry r1 |
1ec42c0c | 690 | enable_irq @ Enable interrupts |
4fb28474 | 691 | mov r2, sp @ regs |
1da177e4 | 692 | bl do_PrefetchAbort @ call abort handler |
c4c5716e | 693 | UNWIND(.fnend ) |
1da177e4 LT |
694 | /* fall through */ |
695 | /* | |
696 | * This is the return code to user mode for abort handlers | |
697 | */ | |
698 | ENTRY(ret_from_exception) | |
c4c5716e CM |
699 | UNWIND(.fnstart ) |
700 | UNWIND(.cantunwind ) | |
1da177e4 LT |
701 | get_thread_info tsk |
702 | mov why, #0 | |
703 | b ret_to_user | |
c4c5716e | 704 | UNWIND(.fnend ) |
93ed3970 CM |
705 | ENDPROC(__pabt_usr) |
706 | ENDPROC(ret_from_exception) | |
1da177e4 LT |
707 | |
708 | /* | |
709 | * Register switch for ARMv3 and ARMv4 processors | |
710 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
711 | * previous and next are guaranteed not to be the same. | |
712 | */ | |
713 | ENTRY(__switch_to) | |
c4c5716e CM |
714 | UNWIND(.fnstart ) |
715 | UNWIND(.cantunwind ) | |
1da177e4 LT |
716 | add ip, r1, #TI_CPU_SAVE |
717 | ldr r3, [r2, #TI_TP_VALUE] | |
b86040a5 CM |
718 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
719 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
720 | THUMB( str sp, [ip], #4 ) | |
721 | THUMB( str lr, [ip], #4 ) | |
247055aa | 722 | #ifdef CONFIG_CPU_USE_DOMAINS |
d6551e88 | 723 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 724 | #endif |
f159f4ed | 725 | set_tls r3, r4, r5 |
df0698be NP |
726 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
727 | ldr r7, [r2, #TI_TASK] | |
728 | ldr r8, =__stack_chk_guard | |
729 | ldr r7, [r7, #TSK_STACK_CANARY] | |
730 | #endif | |
247055aa | 731 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 732 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 733 | #endif |
d6551e88 RK |
734 | mov r5, r0 |
735 | add r4, r2, #TI_CPU_SAVE | |
736 | ldr r0, =thread_notify_head | |
737 | mov r1, #THREAD_NOTIFY_SWITCH | |
738 | bl atomic_notifier_call_chain | |
df0698be NP |
739 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
740 | str r7, [r8] | |
741 | #endif | |
b86040a5 | 742 | THUMB( mov ip, r4 ) |
d6551e88 | 743 | mov r0, r5 |
b86040a5 CM |
744 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
745 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
746 | THUMB( ldr sp, [ip], #4 ) | |
747 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 748 | UNWIND(.fnend ) |
93ed3970 | 749 | ENDPROC(__switch_to) |
1da177e4 LT |
750 | |
751 | __INIT | |
2d2669b6 NP |
752 | |
753 | /* | |
754 | * User helpers. | |
755 | * | |
756 | * These are segment of kernel provided user code reachable from user space | |
757 | * at a fixed address in kernel memory. This is used to provide user space | |
758 | * with some operations which require kernel help because of unimplemented | |
759 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
760 | * this code to be executed directly in user mode for best efficiency but | |
761 | * which is too intimate with the kernel counter part to be left to user | |
762 | * libraries. In fact this code might even differ from one CPU to another | |
763 | * depending on the available instruction set and restrictions like on | |
764 | * SMP systems. In other words, the kernel reserves the right to change | |
765 | * this code as needed without warning. Only the entry points and their | |
766 | * results are guaranteed to be stable. | |
767 | * | |
768 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
769 | * vector page. New segments (if ever needed) must be added in front of | |
770 | * existing ones. This mechanism should be used only for things that are | |
771 | * really small and justified, and not be abused freely. | |
772 | * | |
773 | * User space is expected to implement those things inline when optimizing | |
774 | * for a processor that has the necessary native support, but only if such | |
775 | * resulting binaries are already to be incompatible with earlier ARM | |
776 | * processors due to the use of unsupported instructions other than what | |
777 | * is provided here. In other words don't make binaries unable to run on | |
778 | * earlier processors just for the sake of not using these kernel helpers | |
779 | * if your compiled code is not going to use the new instructions for other | |
780 | * purpose. | |
781 | */ | |
b86040a5 | 782 | THUMB( .arm ) |
2d2669b6 | 783 | |
ba9b5d76 NP |
784 | .macro usr_ret, reg |
785 | #ifdef CONFIG_ARM_THUMB | |
786 | bx \reg | |
787 | #else | |
788 | mov pc, \reg | |
789 | #endif | |
790 | .endm | |
791 | ||
2d2669b6 NP |
792 | .align 5 |
793 | .globl __kuser_helper_start | |
794 | __kuser_helper_start: | |
795 | ||
7c612bfd NP |
796 | /* |
797 | * Reference prototype: | |
798 | * | |
799 | * void __kernel_memory_barrier(void) | |
800 | * | |
801 | * Input: | |
802 | * | |
803 | * lr = return address | |
804 | * | |
805 | * Output: | |
806 | * | |
807 | * none | |
808 | * | |
809 | * Clobbered: | |
810 | * | |
b49c0f24 | 811 | * none |
7c612bfd NP |
812 | * |
813 | * Definition and user space usage example: | |
814 | * | |
815 | * typedef void (__kernel_dmb_t)(void); | |
816 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
817 | * | |
818 | * Apply any needed memory barrier to preserve consistency with data modified | |
819 | * manually and __kuser_cmpxchg usage. | |
820 | * | |
821 | * This could be used as follows: | |
822 | * | |
823 | * #define __kernel_dmb() \ | |
824 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 825 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
826 | */ |
827 | ||
828 | __kuser_memory_barrier: @ 0xffff0fa0 | |
ed3768a8 | 829 | smp_dmb arm |
ba9b5d76 | 830 | usr_ret lr |
7c612bfd NP |
831 | |
832 | .align 5 | |
833 | ||
2d2669b6 NP |
834 | /* |
835 | * Reference prototype: | |
836 | * | |
837 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
838 | * | |
839 | * Input: | |
840 | * | |
841 | * r0 = oldval | |
842 | * r1 = newval | |
843 | * r2 = ptr | |
844 | * lr = return address | |
845 | * | |
846 | * Output: | |
847 | * | |
848 | * r0 = returned value (zero or non-zero) | |
849 | * C flag = set if r0 == 0, clear if r0 != 0 | |
850 | * | |
851 | * Clobbered: | |
852 | * | |
853 | * r3, ip, flags | |
854 | * | |
855 | * Definition and user space usage example: | |
856 | * | |
857 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
858 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
859 | * | |
860 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
861 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
862 | * The C flag is also set if *ptr was changed to allow for assembly | |
863 | * optimization in the calling code. | |
864 | * | |
5964eae8 NP |
865 | * Notes: |
866 | * | |
867 | * - This routine already includes memory barriers as needed. | |
868 | * | |
2d2669b6 NP |
869 | * For example, a user space atomic_add implementation could look like this: |
870 | * | |
871 | * #define atomic_add(ptr, val) \ | |
872 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
873 | * register unsigned int __result asm("r1"); \ | |
874 | * asm volatile ( \ | |
875 | * "1: @ atomic_add\n\t" \ | |
876 | * "ldr r0, [r2]\n\t" \ | |
877 | * "mov r3, #0xffff0fff\n\t" \ | |
878 | * "add lr, pc, #4\n\t" \ | |
879 | * "add r1, r0, %2\n\t" \ | |
880 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
881 | * "bcc 1b" \ | |
882 | * : "=&r" (__result) \ | |
883 | * : "r" (__ptr), "rIL" (val) \ | |
884 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
885 | * __result; }) | |
886 | */ | |
887 | ||
888 | __kuser_cmpxchg: @ 0xffff0fc0 | |
889 | ||
dcef1f63 | 890 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 891 | |
dcef1f63 NP |
892 | /* |
893 | * Poor you. No fast solution possible... | |
894 | * The kernel itself must perform the operation. | |
895 | * A special ghost syscall is used for that (see traps.c). | |
896 | */ | |
5e097445 | 897 | stmfd sp!, {r7, lr} |
55afd264 | 898 | ldr r7, 1f @ it's 20 bits |
cc20d429 | 899 | swi __ARM_NR_cmpxchg |
5e097445 | 900 | ldmfd sp!, {r7, pc} |
cc20d429 | 901 | 1: .word __ARM_NR_cmpxchg |
dcef1f63 NP |
902 | |
903 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 904 | |
b49c0f24 NP |
905 | #ifdef CONFIG_MMU |
906 | ||
2d2669b6 | 907 | /* |
b49c0f24 NP |
908 | * The only thing that can break atomicity in this cmpxchg |
909 | * implementation is either an IRQ or a data abort exception | |
910 | * causing another process/thread to be scheduled in the middle | |
911 | * of the critical sequence. To prevent this, code is added to | |
912 | * the IRQ and data abort exception handlers to set the pc back | |
913 | * to the beginning of the critical section if it is found to be | |
914 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 915 | */ |
b49c0f24 NP |
916 | 1: ldr r3, [r2] @ load current val |
917 | subs r3, r3, r0 @ compare with oldval | |
918 | 2: streq r1, [r2] @ store newval if eq | |
919 | rsbs r0, r3, #0 @ set return val and C flag | |
920 | usr_ret lr | |
921 | ||
922 | .text | |
923 | kuser_cmpxchg_fixup: | |
924 | @ Called from kuser_cmpxchg_check macro. | |
925 | @ r2 = address of interrupted insn (must be preserved). | |
926 | @ sp = saved regs. r7 and r8 are clobbered. | |
927 | @ 1b = first critical insn, 2b = last critical insn. | |
928 | @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. | |
929 | mov r7, #0xffff0fff | |
930 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
931 | subs r8, r2, r7 | |
932 | rsbcss r8, r8, #(2b - 1b) | |
933 | strcs r7, [sp, #S_PC] | |
934 | mov pc, lr | |
935 | .previous | |
936 | ||
49bca4c2 NP |
937 | #else |
938 | #warning "NPTL on non MMU needs fixing" | |
939 | mov r0, #-1 | |
940 | adds r0, r0, #0 | |
ba9b5d76 | 941 | usr_ret lr |
b49c0f24 | 942 | #endif |
2d2669b6 NP |
943 | |
944 | #else | |
945 | ||
ed3768a8 | 946 | smp_dmb arm |
b49c0f24 | 947 | 1: ldrex r3, [r2] |
2d2669b6 NP |
948 | subs r3, r3, r0 |
949 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
950 | teqeq r3, #1 |
951 | beq 1b | |
2d2669b6 | 952 | rsbs r0, r3, #0 |
b49c0f24 | 953 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
954 | ALT_SMP(b __kuser_memory_barrier) |
955 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
956 | |
957 | #endif | |
958 | ||
959 | .align 5 | |
960 | ||
961 | /* | |
962 | * Reference prototype: | |
963 | * | |
964 | * int __kernel_get_tls(void) | |
965 | * | |
966 | * Input: | |
967 | * | |
968 | * lr = return address | |
969 | * | |
970 | * Output: | |
971 | * | |
972 | * r0 = TLS value | |
973 | * | |
974 | * Clobbered: | |
975 | * | |
b49c0f24 | 976 | * none |
2d2669b6 NP |
977 | * |
978 | * Definition and user space usage example: | |
979 | * | |
980 | * typedef int (__kernel_get_tls_t)(void); | |
981 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
982 | * | |
983 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
984 | * | |
985 | * This could be used as follows: | |
986 | * | |
987 | * #define __kernel_get_tls() \ | |
988 | * ({ register unsigned int __val asm("r0"); \ | |
989 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
990 | * : "=r" (__val) : : "lr","cc" ); \ | |
991 | * __val; }) | |
992 | */ | |
993 | ||
994 | __kuser_get_tls: @ 0xffff0fe0 | |
f159f4ed | 995 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 996 | usr_ret lr |
f159f4ed TL |
997 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
998 | .rep 4 | |
999 | .word 0 @ 0xffff0ff0 software TLS value, then | |
1000 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 NP |
1001 | |
1002 | /* | |
1003 | * Reference declaration: | |
1004 | * | |
1005 | * extern unsigned int __kernel_helper_version; | |
1006 | * | |
1007 | * Definition and user space usage example: | |
1008 | * | |
1009 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
1010 | * | |
1011 | * User space may read this to determine the curent number of helpers | |
1012 | * available. | |
1013 | */ | |
1014 | ||
1015 | __kuser_helper_version: @ 0xffff0ffc | |
1016 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
1017 | ||
1018 | .globl __kuser_helper_end | |
1019 | __kuser_helper_end: | |
1020 | ||
b86040a5 | 1021 | THUMB( .thumb ) |
2d2669b6 | 1022 | |
1da177e4 LT |
1023 | /* |
1024 | * Vector stubs. | |
1025 | * | |
7933523d RK |
1026 | * This code is copied to 0xffff0200 so we can use branches in the |
1027 | * vectors, rather than ldr's. Note that this code must not | |
1028 | * exceed 0x300 bytes. | |
1da177e4 LT |
1029 | * |
1030 | * Common stub entry macro: | |
1031 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1032 | * |
1033 | * SP points to a minimal amount of processor-private memory, the address | |
1034 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1035 | */ |
b7ec4795 | 1036 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1037 | .align 5 |
1038 | ||
1039 | vector_\name: | |
1da177e4 LT |
1040 | .if \correction |
1041 | sub lr, lr, #\correction | |
1042 | .endif | |
ccea7a19 RK |
1043 | |
1044 | @ | |
1045 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1046 | @ (parent CPSR) | |
1047 | @ | |
1048 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1049 | mrs lr, spsr |
ccea7a19 RK |
1050 | str lr, [sp, #8] @ save spsr |
1051 | ||
1da177e4 | 1052 | @ |
ccea7a19 | 1053 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1054 | @ |
ccea7a19 | 1055 | mrs r0, cpsr |
b86040a5 | 1056 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1057 | msr spsr_cxsf, r0 |
1da177e4 | 1058 | |
ccea7a19 RK |
1059 | @ |
1060 | @ the branch table must immediately follow this code | |
1061 | @ | |
ccea7a19 | 1062 | and lr, lr, #0x0f |
b86040a5 CM |
1063 | THUMB( adr r0, 1f ) |
1064 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1065 | mov r0, sp |
b86040a5 | 1066 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1067 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1068 | ENDPROC(vector_\name) |
88987ef9 CM |
1069 | |
1070 | .align 2 | |
1071 | @ handler addresses follow this label | |
1072 | 1: | |
1da177e4 LT |
1073 | .endm |
1074 | ||
7933523d | 1075 | .globl __stubs_start |
1da177e4 LT |
1076 | __stubs_start: |
1077 | /* | |
1078 | * Interrupt dispatcher | |
1079 | */ | |
b7ec4795 | 1080 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1081 | |
1082 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1083 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1084 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1085 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1086 | .long __irq_invalid @ 4 | |
1087 | .long __irq_invalid @ 5 | |
1088 | .long __irq_invalid @ 6 | |
1089 | .long __irq_invalid @ 7 | |
1090 | .long __irq_invalid @ 8 | |
1091 | .long __irq_invalid @ 9 | |
1092 | .long __irq_invalid @ a | |
1093 | .long __irq_invalid @ b | |
1094 | .long __irq_invalid @ c | |
1095 | .long __irq_invalid @ d | |
1096 | .long __irq_invalid @ e | |
1097 | .long __irq_invalid @ f | |
1098 | ||
1099 | /* | |
1100 | * Data abort dispatcher | |
1101 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1102 | */ | |
b7ec4795 | 1103 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1104 | |
1105 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1106 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1107 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1108 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1109 | .long __dabt_invalid @ 4 | |
1110 | .long __dabt_invalid @ 5 | |
1111 | .long __dabt_invalid @ 6 | |
1112 | .long __dabt_invalid @ 7 | |
1113 | .long __dabt_invalid @ 8 | |
1114 | .long __dabt_invalid @ 9 | |
1115 | .long __dabt_invalid @ a | |
1116 | .long __dabt_invalid @ b | |
1117 | .long __dabt_invalid @ c | |
1118 | .long __dabt_invalid @ d | |
1119 | .long __dabt_invalid @ e | |
1120 | .long __dabt_invalid @ f | |
1121 | ||
1122 | /* | |
1123 | * Prefetch abort dispatcher | |
1124 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1125 | */ | |
b7ec4795 | 1126 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1127 | |
1128 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1129 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1130 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1131 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1132 | .long __pabt_invalid @ 4 | |
1133 | .long __pabt_invalid @ 5 | |
1134 | .long __pabt_invalid @ 6 | |
1135 | .long __pabt_invalid @ 7 | |
1136 | .long __pabt_invalid @ 8 | |
1137 | .long __pabt_invalid @ 9 | |
1138 | .long __pabt_invalid @ a | |
1139 | .long __pabt_invalid @ b | |
1140 | .long __pabt_invalid @ c | |
1141 | .long __pabt_invalid @ d | |
1142 | .long __pabt_invalid @ e | |
1143 | .long __pabt_invalid @ f | |
1144 | ||
1145 | /* | |
1146 | * Undef instr entry dispatcher | |
1147 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1148 | */ | |
b7ec4795 | 1149 | vector_stub und, UND_MODE |
1da177e4 LT |
1150 | |
1151 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1152 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1153 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1154 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1155 | .long __und_invalid @ 4 | |
1156 | .long __und_invalid @ 5 | |
1157 | .long __und_invalid @ 6 | |
1158 | .long __und_invalid @ 7 | |
1159 | .long __und_invalid @ 8 | |
1160 | .long __und_invalid @ 9 | |
1161 | .long __und_invalid @ a | |
1162 | .long __und_invalid @ b | |
1163 | .long __und_invalid @ c | |
1164 | .long __und_invalid @ d | |
1165 | .long __und_invalid @ e | |
1166 | .long __und_invalid @ f | |
1167 | ||
1168 | .align 5 | |
1169 | ||
1170 | /*============================================================================= | |
1171 | * Undefined FIQs | |
1172 | *----------------------------------------------------------------------------- | |
1173 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1174 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1175 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1176 | * damage alert! I don't think that we can execute any code in here in any | |
1177 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1178 | * get out of that mode without clobbering one register. | |
1179 | */ | |
1180 | vector_fiq: | |
1181 | disable_fiq | |
1182 | subs pc, lr, #4 | |
1183 | ||
1184 | /*============================================================================= | |
1185 | * Address exception handler | |
1186 | *----------------------------------------------------------------------------- | |
1187 | * These aren't too critical. | |
1188 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1189 | */ | |
1190 | ||
1191 | vector_addrexcptn: | |
1192 | b vector_addrexcptn | |
1193 | ||
1194 | /* | |
1195 | * We group all the following data together to optimise | |
1196 | * for CPUs with separate I & D caches. | |
1197 | */ | |
1198 | .align 5 | |
1199 | ||
1200 | .LCvswi: | |
1201 | .word vector_swi | |
1202 | ||
7933523d | 1203 | .globl __stubs_end |
1da177e4 LT |
1204 | __stubs_end: |
1205 | ||
7933523d | 1206 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1207 | |
7933523d RK |
1208 | .globl __vectors_start |
1209 | __vectors_start: | |
b86040a5 CM |
1210 | ARM( swi SYS_ERROR0 ) |
1211 | THUMB( svc #0 ) | |
1212 | THUMB( nop ) | |
1213 | W(b) vector_und + stubs_offset | |
1214 | W(ldr) pc, .LCvswi + stubs_offset | |
1215 | W(b) vector_pabt + stubs_offset | |
1216 | W(b) vector_dabt + stubs_offset | |
1217 | W(b) vector_addrexcptn + stubs_offset | |
1218 | W(b) vector_irq + stubs_offset | |
1219 | W(b) vector_fiq + stubs_offset | |
7933523d RK |
1220 | |
1221 | .globl __vectors_end | |
1222 | __vectors_end: | |
1da177e4 LT |
1223 | |
1224 | .data | |
1225 | ||
1da177e4 LT |
1226 | .globl cr_alignment |
1227 | .globl cr_no_alignment | |
1228 | cr_alignment: | |
1229 | .space 4 | |
1230 | cr_no_alignment: | |
1231 | .space 4 | |
52108641 | 1232 | |
1233 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1234 | .globl handle_arch_irq | |
1235 | handle_arch_irq: | |
1236 | .space 4 | |
1237 | #endif |