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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes | |
15 | * it to save wrong values... Be aware! | |
16 | */ | |
17 | #include <linux/config.h> | |
1da177e4 | 18 | |
f09b9979 | 19 | #include <asm/memory.h> |
1da177e4 | 20 | #include <asm/glue.h> |
1da177e4 | 21 | #include <asm/vfpmacros.h> |
bce495d8 | 22 | #include <asm/arch/entry-macro.S> |
1da177e4 LT |
23 | |
24 | #include "entry-header.S" | |
25 | ||
187a51ad RK |
26 | /* |
27 | * Interrupt handling. Preserves r7, r8, r9 | |
28 | */ | |
29 | .macro irq_handler | |
30 | 1: get_irqnr_and_base r0, r6, r5, lr | |
31 | movne r1, sp | |
32 | @ | |
33 | @ routine called with r0 = irq number, r1 = struct pt_regs * | |
34 | @ | |
35 | adrne lr, 1b | |
36 | bne asm_do_IRQ | |
791be9b9 RK |
37 | |
38 | #ifdef CONFIG_SMP | |
39 | /* | |
40 | * XXX | |
41 | * | |
42 | * this macro assumes that irqstat (r6) and base (r5) are | |
43 | * preserved from get_irqnr_and_base above | |
44 | */ | |
45 | test_for_ipi r0, r6, r5, lr | |
46 | movne r0, sp | |
47 | adrne lr, 1b | |
48 | bne do_IPI | |
37ee16ae RK |
49 | |
50 | #ifdef CONFIG_LOCAL_TIMERS | |
51 | test_for_ltirq r0, r6, r5, lr | |
52 | movne r0, sp | |
53 | adrne lr, 1b | |
54 | bne do_local_timer | |
55 | #endif | |
791be9b9 RK |
56 | #endif |
57 | ||
187a51ad RK |
58 | .endm |
59 | ||
1da177e4 LT |
60 | /* |
61 | * Invalid mode handlers | |
62 | */ | |
ccea7a19 RK |
63 | .macro inv_entry, reason |
64 | sub sp, sp, #S_FRAME_SIZE | |
65 | stmib sp, {r1 - lr} | |
1da177e4 LT |
66 | mov r1, #\reason |
67 | .endm | |
68 | ||
69 | __pabt_invalid: | |
ccea7a19 RK |
70 | inv_entry BAD_PREFETCH |
71 | b common_invalid | |
1da177e4 LT |
72 | |
73 | __dabt_invalid: | |
ccea7a19 RK |
74 | inv_entry BAD_DATA |
75 | b common_invalid | |
1da177e4 LT |
76 | |
77 | __irq_invalid: | |
ccea7a19 RK |
78 | inv_entry BAD_IRQ |
79 | b common_invalid | |
1da177e4 LT |
80 | |
81 | __und_invalid: | |
ccea7a19 RK |
82 | inv_entry BAD_UNDEFINSTR |
83 | ||
84 | @ | |
85 | @ XXX fall through to common_invalid | |
86 | @ | |
87 | ||
88 | @ | |
89 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
90 | @ | |
91 | common_invalid: | |
92 | zero_fp | |
93 | ||
94 | ldmia r0, {r4 - r6} | |
95 | add r0, sp, #S_PC @ here for interlock avoidance | |
96 | mov r7, #-1 @ "" "" "" "" | |
97 | str r4, [sp] @ save preserved r0 | |
98 | stmia r0, {r5 - r7} @ lr_<exception>, | |
99 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 100 | |
1da177e4 | 101 | mov r0, sp |
ccea7a19 | 102 | and r2, r6, #0x1f |
1da177e4 LT |
103 | b bad_mode |
104 | ||
105 | /* | |
106 | * SVC mode handlers | |
107 | */ | |
ccea7a19 | 108 | .macro svc_entry |
1da177e4 | 109 | sub sp, sp, #S_FRAME_SIZE |
ccea7a19 RK |
110 | stmib sp, {r1 - r12} |
111 | ||
112 | ldmia r0, {r1 - r3} | |
113 | add r5, sp, #S_SP @ here for interlock avoidance | |
114 | mov r4, #-1 @ "" "" "" "" | |
115 | add r0, sp, #S_FRAME_SIZE @ "" "" "" "" | |
116 | str r1, [sp] @ save the "real" r0 copied | |
117 | @ from the exception stack | |
118 | ||
1da177e4 LT |
119 | mov r1, lr |
120 | ||
121 | @ | |
122 | @ We are now ready to fill in the remaining blanks on the stack: | |
123 | @ | |
124 | @ r0 - sp_svc | |
125 | @ r1 - lr_svc | |
126 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
127 | @ r3 - spsr_<exception> | |
128 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
129 | @ | |
130 | stmia r5, {r0 - r4} | |
131 | .endm | |
132 | ||
133 | .align 5 | |
134 | __dabt_svc: | |
ccea7a19 | 135 | svc_entry |
1da177e4 LT |
136 | |
137 | @ | |
138 | @ get ready to re-enable interrupts if appropriate | |
139 | @ | |
140 | mrs r9, cpsr | |
141 | tst r3, #PSR_I_BIT | |
142 | biceq r9, r9, #PSR_I_BIT | |
143 | ||
144 | @ | |
145 | @ Call the processor-specific abort handler: | |
146 | @ | |
147 | @ r2 - aborted context pc | |
148 | @ r3 - aborted context cpsr | |
149 | @ | |
150 | @ The abort handler must return the aborted address in r0, and | |
151 | @ the fault status register in r1. r9 must be preserved. | |
152 | @ | |
153 | #ifdef MULTI_ABORT | |
154 | ldr r4, .LCprocfns | |
155 | mov lr, pc | |
156 | ldr pc, [r4] | |
157 | #else | |
158 | bl CPU_ABORT_HANDLER | |
159 | #endif | |
160 | ||
161 | @ | |
162 | @ set desired IRQ state, then call main handler | |
163 | @ | |
164 | msr cpsr_c, r9 | |
165 | mov r2, sp | |
166 | bl do_DataAbort | |
167 | ||
168 | @ | |
169 | @ IRQs off again before pulling preserved data off the stack | |
170 | @ | |
1ec42c0c | 171 | disable_irq |
1da177e4 LT |
172 | |
173 | @ | |
174 | @ restore SPSR and restart the instruction | |
175 | @ | |
176 | ldr r0, [sp, #S_PSR] | |
177 | msr spsr_cxsf, r0 | |
178 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
179 | ||
180 | .align 5 | |
181 | __irq_svc: | |
ccea7a19 RK |
182 | svc_entry |
183 | ||
1da177e4 | 184 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
185 | get_thread_info tsk |
186 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
187 | add r7, r8, #1 @ increment it | |
188 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 189 | #endif |
ccea7a19 | 190 | |
187a51ad | 191 | irq_handler |
1da177e4 | 192 | #ifdef CONFIG_PREEMPT |
706fdd9f | 193 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
1da177e4 LT |
194 | tst r0, #_TIF_NEED_RESCHED |
195 | blne svc_preempt | |
196 | preempt_return: | |
706fdd9f RK |
197 | ldr r0, [tsk, #TI_PREEMPT] @ read preempt value |
198 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | |
1da177e4 | 199 | teq r0, r7 |
1da177e4 LT |
200 | strne r0, [r0, -r0] @ bug() |
201 | #endif | |
202 | ldr r0, [sp, #S_PSR] @ irqs are already disabled | |
203 | msr spsr_cxsf, r0 | |
204 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
205 | ||
206 | .ltorg | |
207 | ||
208 | #ifdef CONFIG_PREEMPT | |
209 | svc_preempt: | |
706fdd9f | 210 | teq r8, #0 @ was preempt count = 0 |
1da177e4 LT |
211 | ldreq r6, .LCirq_stat |
212 | movne pc, lr @ no | |
213 | ldr r0, [r6, #4] @ local_irq_count | |
214 | ldr r1, [r6, #8] @ local_bh_count | |
215 | adds r0, r0, r1 | |
216 | movne pc, lr | |
217 | mov r7, #0 @ preempt_schedule_irq | |
706fdd9f | 218 | str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 |
1da177e4 | 219 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 220 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 LT |
221 | tst r0, #_TIF_NEED_RESCHED |
222 | beq preempt_return @ go again | |
223 | b 1b | |
224 | #endif | |
225 | ||
226 | .align 5 | |
227 | __und_svc: | |
ccea7a19 | 228 | svc_entry |
1da177e4 LT |
229 | |
230 | @ | |
231 | @ call emulation code, which returns using r9 if it has emulated | |
232 | @ the instruction, or the more conventional lr if we are to treat | |
233 | @ this as a real undefined instruction | |
234 | @ | |
235 | @ r0 - instruction | |
236 | @ | |
237 | ldr r0, [r2, #-4] | |
238 | adr r9, 1f | |
239 | bl call_fpe | |
240 | ||
241 | mov r0, sp @ struct pt_regs *regs | |
242 | bl do_undefinstr | |
243 | ||
244 | @ | |
245 | @ IRQs off again before pulling preserved data off the stack | |
246 | @ | |
1ec42c0c | 247 | 1: disable_irq |
1da177e4 LT |
248 | |
249 | @ | |
250 | @ restore SPSR and restart the instruction | |
251 | @ | |
252 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr | |
253 | msr spsr_cxsf, lr | |
254 | ldmia sp, {r0 - pc}^ @ Restore SVC registers | |
255 | ||
256 | .align 5 | |
257 | __pabt_svc: | |
ccea7a19 | 258 | svc_entry |
1da177e4 LT |
259 | |
260 | @ | |
261 | @ re-enable interrupts if appropriate | |
262 | @ | |
263 | mrs r9, cpsr | |
264 | tst r3, #PSR_I_BIT | |
265 | biceq r9, r9, #PSR_I_BIT | |
266 | msr cpsr_c, r9 | |
267 | ||
268 | @ | |
269 | @ set args, then call main handler | |
270 | @ | |
271 | @ r0 - address of faulting instruction | |
272 | @ r1 - pointer to registers on stack | |
273 | @ | |
274 | mov r0, r2 @ address (pc) | |
275 | mov r1, sp @ regs | |
276 | bl do_PrefetchAbort @ call abort handler | |
277 | ||
278 | @ | |
279 | @ IRQs off again before pulling preserved data off the stack | |
280 | @ | |
1ec42c0c | 281 | disable_irq |
1da177e4 LT |
282 | |
283 | @ | |
284 | @ restore SPSR and restart the instruction | |
285 | @ | |
286 | ldr r0, [sp, #S_PSR] | |
287 | msr spsr_cxsf, r0 | |
288 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
289 | ||
290 | .align 5 | |
49f680ea RK |
291 | .LCcralign: |
292 | .word cr_alignment | |
1da177e4 LT |
293 | #ifdef MULTI_ABORT |
294 | .LCprocfns: | |
295 | .word processor | |
296 | #endif | |
297 | .LCfp: | |
298 | .word fp_enter | |
299 | #ifdef CONFIG_PREEMPT | |
300 | .LCirq_stat: | |
301 | .word irq_stat | |
302 | #endif | |
303 | ||
304 | /* | |
305 | * User mode handlers | |
306 | */ | |
ccea7a19 RK |
307 | .macro usr_entry |
308 | sub sp, sp, #S_FRAME_SIZE | |
309 | stmib sp, {r1 - r12} | |
310 | ||
311 | ldmia r0, {r1 - r3} | |
312 | add r0, sp, #S_PC @ here for interlock avoidance | |
313 | mov r4, #-1 @ "" "" "" "" | |
314 | ||
315 | str r1, [sp] @ save the "real" r0 copied | |
316 | @ from the exception stack | |
1da177e4 | 317 | |
dcef1f63 | 318 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 319 | @ make sure our user space atomic helper is aborted |
f09b9979 | 320 | cmp r2, #TASK_SIZE |
2d2669b6 NP |
321 | bichs r3, r3, #PSR_Z_BIT |
322 | #endif | |
323 | ||
1da177e4 LT |
324 | @ |
325 | @ We are now ready to fill in the remaining blanks on the stack: | |
326 | @ | |
327 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
328 | @ r3 - spsr_<exception> | |
329 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
330 | @ | |
331 | @ Also, separately save sp_usr and lr_usr | |
332 | @ | |
ccea7a19 RK |
333 | stmia r0, {r2 - r4} |
334 | stmdb r0, {sp, lr}^ | |
1da177e4 LT |
335 | |
336 | @ | |
337 | @ Enable the alignment trap while in kernel mode | |
338 | @ | |
49f680ea | 339 | alignment_trap r0 |
1da177e4 LT |
340 | |
341 | @ | |
342 | @ Clear FP to mark the first stack frame | |
343 | @ | |
344 | zero_fp | |
345 | .endm | |
346 | ||
347 | .align 5 | |
348 | __dabt_usr: | |
ccea7a19 | 349 | usr_entry |
1da177e4 LT |
350 | |
351 | @ | |
352 | @ Call the processor-specific abort handler: | |
353 | @ | |
354 | @ r2 - aborted context pc | |
355 | @ r3 - aborted context cpsr | |
356 | @ | |
357 | @ The abort handler must return the aborted address in r0, and | |
358 | @ the fault status register in r1. | |
359 | @ | |
360 | #ifdef MULTI_ABORT | |
361 | ldr r4, .LCprocfns | |
362 | mov lr, pc | |
363 | ldr pc, [r4] | |
364 | #else | |
365 | bl CPU_ABORT_HANDLER | |
366 | #endif | |
367 | ||
368 | @ | |
369 | @ IRQs on, then call the main handler | |
370 | @ | |
1ec42c0c | 371 | enable_irq |
1da177e4 LT |
372 | mov r2, sp |
373 | adr lr, ret_from_exception | |
374 | b do_DataAbort | |
375 | ||
376 | .align 5 | |
377 | __irq_usr: | |
ccea7a19 | 378 | usr_entry |
1da177e4 | 379 | |
706fdd9f | 380 | get_thread_info tsk |
1da177e4 | 381 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
382 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
383 | add r7, r8, #1 @ increment it | |
384 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 385 | #endif |
ccea7a19 | 386 | |
187a51ad | 387 | irq_handler |
1da177e4 | 388 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
389 | ldr r0, [tsk, #TI_PREEMPT] |
390 | str r8, [tsk, #TI_PREEMPT] | |
1da177e4 | 391 | teq r0, r7 |
1da177e4 | 392 | strne r0, [r0, -r0] |
1da177e4 | 393 | #endif |
ccea7a19 | 394 | |
1da177e4 LT |
395 | mov why, #0 |
396 | b ret_to_user | |
397 | ||
398 | .ltorg | |
399 | ||
400 | .align 5 | |
401 | __und_usr: | |
ccea7a19 | 402 | usr_entry |
1da177e4 LT |
403 | |
404 | tst r3, #PSR_T_BIT @ Thumb mode? | |
405 | bne fpundefinstr @ ignore FP | |
406 | sub r4, r2, #4 | |
407 | ||
408 | @ | |
409 | @ fall through to the emulation code, which returns using r9 if | |
410 | @ it has emulated the instruction, or the more conventional lr | |
411 | @ if we are to treat this as a real undefined instruction | |
412 | @ | |
413 | @ r0 - instruction | |
414 | @ | |
415 | 1: ldrt r0, [r4] | |
416 | adr r9, ret_from_exception | |
417 | adr lr, fpundefinstr | |
418 | @ | |
419 | @ fallthrough to call_fpe | |
420 | @ | |
421 | ||
422 | /* | |
423 | * The out of line fixup for the ldrt above. | |
424 | */ | |
425 | .section .fixup, "ax" | |
426 | 2: mov pc, r9 | |
427 | .previous | |
428 | .section __ex_table,"a" | |
429 | .long 1b, 2b | |
430 | .previous | |
431 | ||
432 | /* | |
433 | * Check whether the instruction is a co-processor instruction. | |
434 | * If yes, we need to call the relevant co-processor handler. | |
435 | * | |
436 | * Note that we don't do a full check here for the co-processor | |
437 | * instructions; all instructions with bit 27 set are well | |
438 | * defined. The only instructions that should fault are the | |
439 | * co-processor instructions. However, we have to watch out | |
440 | * for the ARM6/ARM7 SWI bug. | |
441 | * | |
442 | * Emulators may wish to make use of the following registers: | |
443 | * r0 = instruction opcode. | |
444 | * r2 = PC+4 | |
445 | * r10 = this threads thread_info structure. | |
446 | */ | |
447 | call_fpe: | |
448 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 | |
449 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) | |
450 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
451 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
452 | #endif | |
453 | moveq pc, lr | |
454 | get_thread_info r10 @ get current thread | |
455 | and r8, r0, #0x00000f00 @ mask out CP number | |
456 | mov r7, #1 | |
457 | add r6, r10, #TI_USED_CP | |
458 | strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] | |
459 | #ifdef CONFIG_IWMMXT | |
460 | @ Test if we need to give access to iWMMXt coprocessors | |
461 | ldr r5, [r10, #TI_FLAGS] | |
462 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
463 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
464 | bcs iwmmxt_task_enable | |
465 | #endif | |
1ec42c0c | 466 | enable_irq |
1da177e4 LT |
467 | add pc, pc, r8, lsr #6 |
468 | mov r0, r0 | |
469 | ||
470 | mov pc, lr @ CP#0 | |
471 | b do_fpe @ CP#1 (FPE) | |
472 | b do_fpe @ CP#2 (FPE) | |
473 | mov pc, lr @ CP#3 | |
474 | mov pc, lr @ CP#4 | |
475 | mov pc, lr @ CP#5 | |
476 | mov pc, lr @ CP#6 | |
477 | mov pc, lr @ CP#7 | |
478 | mov pc, lr @ CP#8 | |
479 | mov pc, lr @ CP#9 | |
480 | #ifdef CONFIG_VFP | |
481 | b do_vfp @ CP#10 (VFP) | |
482 | b do_vfp @ CP#11 (VFP) | |
483 | #else | |
484 | mov pc, lr @ CP#10 (VFP) | |
485 | mov pc, lr @ CP#11 (VFP) | |
486 | #endif | |
487 | mov pc, lr @ CP#12 | |
488 | mov pc, lr @ CP#13 | |
489 | mov pc, lr @ CP#14 (Debug) | |
490 | mov pc, lr @ CP#15 (Control) | |
491 | ||
492 | do_fpe: | |
493 | ldr r4, .LCfp | |
494 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
495 | ldr pc, [r4] @ Call FP module USR entry point | |
496 | ||
497 | /* | |
498 | * The FP module is called with these registers set: | |
499 | * r0 = instruction | |
500 | * r2 = PC+4 | |
501 | * r9 = normal "successful" return address | |
502 | * r10 = FP workspace | |
503 | * lr = unrecognised FP instruction return address | |
504 | */ | |
505 | ||
506 | .data | |
507 | ENTRY(fp_enter) | |
508 | .word fpundefinstr | |
509 | .text | |
510 | ||
511 | fpundefinstr: | |
512 | mov r0, sp | |
513 | adr lr, ret_from_exception | |
514 | b do_undefinstr | |
515 | ||
516 | .align 5 | |
517 | __pabt_usr: | |
ccea7a19 | 518 | usr_entry |
1da177e4 | 519 | |
1ec42c0c | 520 | enable_irq @ Enable interrupts |
1da177e4 LT |
521 | mov r0, r2 @ address (pc) |
522 | mov r1, sp @ regs | |
523 | bl do_PrefetchAbort @ call abort handler | |
524 | /* fall through */ | |
525 | /* | |
526 | * This is the return code to user mode for abort handlers | |
527 | */ | |
528 | ENTRY(ret_from_exception) | |
529 | get_thread_info tsk | |
530 | mov why, #0 | |
531 | b ret_to_user | |
532 | ||
533 | /* | |
534 | * Register switch for ARMv3 and ARMv4 processors | |
535 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
536 | * previous and next are guaranteed not to be the same. | |
537 | */ | |
538 | ENTRY(__switch_to) | |
539 | add ip, r1, #TI_CPU_SAVE | |
540 | ldr r3, [r2, #TI_TP_VALUE] | |
541 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack | |
afeb90ca HC |
542 | #ifndef CONFIG_MMU |
543 | add r2, r2, #TI_CPU_DOMAIN | |
544 | #else | |
1da177e4 | 545 | ldr r6, [r2, #TI_CPU_DOMAIN]! |
afeb90ca | 546 | #endif |
b876386e RK |
547 | #if __LINUX_ARM_ARCH__ >= 6 |
548 | #ifdef CONFIG_CPU_MPCORE | |
549 | clrex | |
550 | #else | |
73394322 | 551 | strex r5, r4, [ip] @ Clear exclusive monitor |
b876386e RK |
552 | #endif |
553 | #endif | |
1da177e4 LT |
554 | #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT) |
555 | mra r4, r5, acc0 | |
556 | stmia ip, {r4, r5} | |
557 | #endif | |
4b0e07a5 | 558 | #if defined(CONFIG_HAS_TLS_REG) |
2d2669b6 | 559 | mcr p15, 0, r3, c13, c0, 3 @ set TLS register |
4b0e07a5 | 560 | #elif !defined(CONFIG_TLS_REG_EMUL) |
1da177e4 | 561 | mov r4, #0xffff0fff |
2d2669b6 NP |
562 | str r3, [r4, #-15] @ TLS val at 0xffff0ff0 |
563 | #endif | |
afeb90ca | 564 | #ifdef CONFIG_MMU |
1da177e4 | 565 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
afeb90ca | 566 | #endif |
1da177e4 LT |
567 | #ifdef CONFIG_VFP |
568 | @ Always disable VFP so we can lazily save/restore the old | |
569 | @ state. This occurs in the context of the previous thread. | |
570 | VFPFMRX r4, FPEXC | |
571 | bic r4, r4, #FPEXC_ENABLE | |
572 | VFPFMXR FPEXC, r4 | |
573 | #endif | |
574 | #if defined(CONFIG_IWMMXT) | |
575 | bl iwmmxt_task_switch | |
576 | #elif defined(CONFIG_CPU_XSCALE) | |
577 | add r4, r2, #40 @ cpu_context_save->extra | |
578 | ldmib r4, {r4, r5} | |
579 | mar acc0, r4, r5 | |
580 | #endif | |
581 | ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously | |
582 | ||
583 | __INIT | |
2d2669b6 NP |
584 | |
585 | /* | |
586 | * User helpers. | |
587 | * | |
588 | * These are segment of kernel provided user code reachable from user space | |
589 | * at a fixed address in kernel memory. This is used to provide user space | |
590 | * with some operations which require kernel help because of unimplemented | |
591 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
592 | * this code to be executed directly in user mode for best efficiency but | |
593 | * which is too intimate with the kernel counter part to be left to user | |
594 | * libraries. In fact this code might even differ from one CPU to another | |
595 | * depending on the available instruction set and restrictions like on | |
596 | * SMP systems. In other words, the kernel reserves the right to change | |
597 | * this code as needed without warning. Only the entry points and their | |
598 | * results are guaranteed to be stable. | |
599 | * | |
600 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
601 | * vector page. New segments (if ever needed) must be added in front of | |
602 | * existing ones. This mechanism should be used only for things that are | |
603 | * really small and justified, and not be abused freely. | |
604 | * | |
605 | * User space is expected to implement those things inline when optimizing | |
606 | * for a processor that has the necessary native support, but only if such | |
607 | * resulting binaries are already to be incompatible with earlier ARM | |
608 | * processors due to the use of unsupported instructions other than what | |
609 | * is provided here. In other words don't make binaries unable to run on | |
610 | * earlier processors just for the sake of not using these kernel helpers | |
611 | * if your compiled code is not going to use the new instructions for other | |
612 | * purpose. | |
613 | */ | |
614 | ||
615 | .align 5 | |
616 | .globl __kuser_helper_start | |
617 | __kuser_helper_start: | |
618 | ||
7c612bfd NP |
619 | /* |
620 | * Reference prototype: | |
621 | * | |
622 | * void __kernel_memory_barrier(void) | |
623 | * | |
624 | * Input: | |
625 | * | |
626 | * lr = return address | |
627 | * | |
628 | * Output: | |
629 | * | |
630 | * none | |
631 | * | |
632 | * Clobbered: | |
633 | * | |
634 | * the Z flag might be lost | |
635 | * | |
636 | * Definition and user space usage example: | |
637 | * | |
638 | * typedef void (__kernel_dmb_t)(void); | |
639 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
640 | * | |
641 | * Apply any needed memory barrier to preserve consistency with data modified | |
642 | * manually and __kuser_cmpxchg usage. | |
643 | * | |
644 | * This could be used as follows: | |
645 | * | |
646 | * #define __kernel_dmb() \ | |
647 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
648 | * : : : "lr","cc" ) | |
649 | */ | |
650 | ||
651 | __kuser_memory_barrier: @ 0xffff0fa0 | |
652 | ||
653 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) | |
654 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
655 | #endif | |
656 | mov pc, lr | |
657 | ||
658 | .align 5 | |
659 | ||
2d2669b6 NP |
660 | /* |
661 | * Reference prototype: | |
662 | * | |
663 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
664 | * | |
665 | * Input: | |
666 | * | |
667 | * r0 = oldval | |
668 | * r1 = newval | |
669 | * r2 = ptr | |
670 | * lr = return address | |
671 | * | |
672 | * Output: | |
673 | * | |
674 | * r0 = returned value (zero or non-zero) | |
675 | * C flag = set if r0 == 0, clear if r0 != 0 | |
676 | * | |
677 | * Clobbered: | |
678 | * | |
679 | * r3, ip, flags | |
680 | * | |
681 | * Definition and user space usage example: | |
682 | * | |
683 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
684 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
685 | * | |
686 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
687 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
688 | * The C flag is also set if *ptr was changed to allow for assembly | |
689 | * optimization in the calling code. | |
690 | * | |
7c612bfd NP |
691 | * Note: this routine already includes memory barriers as needed. |
692 | * | |
2d2669b6 NP |
693 | * For example, a user space atomic_add implementation could look like this: |
694 | * | |
695 | * #define atomic_add(ptr, val) \ | |
696 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
697 | * register unsigned int __result asm("r1"); \ | |
698 | * asm volatile ( \ | |
699 | * "1: @ atomic_add\n\t" \ | |
700 | * "ldr r0, [r2]\n\t" \ | |
701 | * "mov r3, #0xffff0fff\n\t" \ | |
702 | * "add lr, pc, #4\n\t" \ | |
703 | * "add r1, r0, %2\n\t" \ | |
704 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
705 | * "bcc 1b" \ | |
706 | * : "=&r" (__result) \ | |
707 | * : "r" (__ptr), "rIL" (val) \ | |
708 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
709 | * __result; }) | |
710 | */ | |
711 | ||
712 | __kuser_cmpxchg: @ 0xffff0fc0 | |
713 | ||
dcef1f63 | 714 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 715 | |
dcef1f63 NP |
716 | /* |
717 | * Poor you. No fast solution possible... | |
718 | * The kernel itself must perform the operation. | |
719 | * A special ghost syscall is used for that (see traps.c). | |
720 | */ | |
721 | swi #0x9ffff0 | |
722 | mov pc, lr | |
723 | ||
724 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 NP |
725 | |
726 | /* | |
727 | * Theory of operation: | |
728 | * | |
729 | * We set the Z flag before loading oldval. If ever an exception | |
730 | * occurs we can not be sure the loaded value will still be the same | |
731 | * when the exception returns, therefore the user exception handler | |
732 | * will clear the Z flag whenever the interrupted user code was | |
733 | * actually from the kernel address space (see the usr_entry macro). | |
734 | * | |
735 | * The post-increment on the str is used to prevent a race with an | |
736 | * exception happening just after the str instruction which would | |
737 | * clear the Z flag although the exchange was done. | |
738 | */ | |
739 | teq ip, ip @ set Z flag | |
740 | ldr ip, [r2] @ load current val | |
741 | add r3, r2, #1 @ prepare store ptr | |
742 | teqeq ip, r0 @ compare with oldval if still allowed | |
743 | streq r1, [r3, #-1]! @ store newval if still allowed | |
744 | subs r0, r2, r3 @ if r2 == r3 the str occured | |
745 | mov pc, lr | |
746 | ||
747 | #else | |
748 | ||
7c612bfd NP |
749 | #ifdef CONFIG_SMP |
750 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
751 | #endif | |
2d2669b6 NP |
752 | ldrex r3, [r2] |
753 | subs r3, r3, r0 | |
754 | strexeq r3, r1, [r2] | |
755 | rsbs r0, r3, #0 | |
7c612bfd NP |
756 | #ifdef CONFIG_SMP |
757 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
758 | #endif | |
2d2669b6 NP |
759 | mov pc, lr |
760 | ||
761 | #endif | |
762 | ||
763 | .align 5 | |
764 | ||
765 | /* | |
766 | * Reference prototype: | |
767 | * | |
768 | * int __kernel_get_tls(void) | |
769 | * | |
770 | * Input: | |
771 | * | |
772 | * lr = return address | |
773 | * | |
774 | * Output: | |
775 | * | |
776 | * r0 = TLS value | |
777 | * | |
778 | * Clobbered: | |
779 | * | |
780 | * the Z flag might be lost | |
781 | * | |
782 | * Definition and user space usage example: | |
783 | * | |
784 | * typedef int (__kernel_get_tls_t)(void); | |
785 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
786 | * | |
787 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
788 | * | |
789 | * This could be used as follows: | |
790 | * | |
791 | * #define __kernel_get_tls() \ | |
792 | * ({ register unsigned int __val asm("r0"); \ | |
793 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
794 | * : "=r" (__val) : : "lr","cc" ); \ | |
795 | * __val; }) | |
796 | */ | |
797 | ||
798 | __kuser_get_tls: @ 0xffff0fe0 | |
799 | ||
4b0e07a5 | 800 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
2d2669b6 NP |
801 | |
802 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 | |
803 | mov pc, lr | |
804 | ||
805 | #else | |
806 | ||
807 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register | |
808 | mov pc, lr | |
809 | ||
810 | #endif | |
811 | ||
812 | .rep 5 | |
813 | .word 0 @ pad up to __kuser_helper_version | |
814 | .endr | |
815 | ||
816 | /* | |
817 | * Reference declaration: | |
818 | * | |
819 | * extern unsigned int __kernel_helper_version; | |
820 | * | |
821 | * Definition and user space usage example: | |
822 | * | |
823 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
824 | * | |
825 | * User space may read this to determine the curent number of helpers | |
826 | * available. | |
827 | */ | |
828 | ||
829 | __kuser_helper_version: @ 0xffff0ffc | |
830 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
831 | ||
832 | .globl __kuser_helper_end | |
833 | __kuser_helper_end: | |
834 | ||
835 | ||
1da177e4 LT |
836 | /* |
837 | * Vector stubs. | |
838 | * | |
7933523d RK |
839 | * This code is copied to 0xffff0200 so we can use branches in the |
840 | * vectors, rather than ldr's. Note that this code must not | |
841 | * exceed 0x300 bytes. | |
1da177e4 LT |
842 | * |
843 | * Common stub entry macro: | |
844 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
845 | * |
846 | * SP points to a minimal amount of processor-private memory, the address | |
847 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 848 | */ |
b7ec4795 | 849 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
850 | .align 5 |
851 | ||
852 | vector_\name: | |
1da177e4 LT |
853 | .if \correction |
854 | sub lr, lr, #\correction | |
855 | .endif | |
ccea7a19 RK |
856 | |
857 | @ | |
858 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
859 | @ (parent CPSR) | |
860 | @ | |
861 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 862 | mrs lr, spsr |
ccea7a19 RK |
863 | str lr, [sp, #8] @ save spsr |
864 | ||
1da177e4 | 865 | @ |
ccea7a19 | 866 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 867 | @ |
ccea7a19 | 868 | mrs r0, cpsr |
b7ec4795 | 869 | eor r0, r0, #(\mode ^ SVC_MODE) |
ccea7a19 | 870 | msr spsr_cxsf, r0 |
1da177e4 | 871 | |
ccea7a19 RK |
872 | @ |
873 | @ the branch table must immediately follow this code | |
874 | @ | |
ccea7a19 | 875 | and lr, lr, #0x0f |
b7ec4795 | 876 | mov r0, sp |
1da177e4 | 877 | ldr lr, [pc, lr, lsl #2] |
ccea7a19 | 878 | movs pc, lr @ branch to handler in SVC mode |
1da177e4 LT |
879 | .endm |
880 | ||
7933523d | 881 | .globl __stubs_start |
1da177e4 LT |
882 | __stubs_start: |
883 | /* | |
884 | * Interrupt dispatcher | |
885 | */ | |
b7ec4795 | 886 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
887 | |
888 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
889 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
890 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
891 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
892 | .long __irq_invalid @ 4 | |
893 | .long __irq_invalid @ 5 | |
894 | .long __irq_invalid @ 6 | |
895 | .long __irq_invalid @ 7 | |
896 | .long __irq_invalid @ 8 | |
897 | .long __irq_invalid @ 9 | |
898 | .long __irq_invalid @ a | |
899 | .long __irq_invalid @ b | |
900 | .long __irq_invalid @ c | |
901 | .long __irq_invalid @ d | |
902 | .long __irq_invalid @ e | |
903 | .long __irq_invalid @ f | |
904 | ||
905 | /* | |
906 | * Data abort dispatcher | |
907 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
908 | */ | |
b7ec4795 | 909 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
910 | |
911 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
912 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
913 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
914 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
915 | .long __dabt_invalid @ 4 | |
916 | .long __dabt_invalid @ 5 | |
917 | .long __dabt_invalid @ 6 | |
918 | .long __dabt_invalid @ 7 | |
919 | .long __dabt_invalid @ 8 | |
920 | .long __dabt_invalid @ 9 | |
921 | .long __dabt_invalid @ a | |
922 | .long __dabt_invalid @ b | |
923 | .long __dabt_invalid @ c | |
924 | .long __dabt_invalid @ d | |
925 | .long __dabt_invalid @ e | |
926 | .long __dabt_invalid @ f | |
927 | ||
928 | /* | |
929 | * Prefetch abort dispatcher | |
930 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
931 | */ | |
b7ec4795 | 932 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
933 | |
934 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
935 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
936 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
937 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
938 | .long __pabt_invalid @ 4 | |
939 | .long __pabt_invalid @ 5 | |
940 | .long __pabt_invalid @ 6 | |
941 | .long __pabt_invalid @ 7 | |
942 | .long __pabt_invalid @ 8 | |
943 | .long __pabt_invalid @ 9 | |
944 | .long __pabt_invalid @ a | |
945 | .long __pabt_invalid @ b | |
946 | .long __pabt_invalid @ c | |
947 | .long __pabt_invalid @ d | |
948 | .long __pabt_invalid @ e | |
949 | .long __pabt_invalid @ f | |
950 | ||
951 | /* | |
952 | * Undef instr entry dispatcher | |
953 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
954 | */ | |
b7ec4795 | 955 | vector_stub und, UND_MODE |
1da177e4 LT |
956 | |
957 | .long __und_usr @ 0 (USR_26 / USR_32) | |
958 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
959 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
960 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
961 | .long __und_invalid @ 4 | |
962 | .long __und_invalid @ 5 | |
963 | .long __und_invalid @ 6 | |
964 | .long __und_invalid @ 7 | |
965 | .long __und_invalid @ 8 | |
966 | .long __und_invalid @ 9 | |
967 | .long __und_invalid @ a | |
968 | .long __und_invalid @ b | |
969 | .long __und_invalid @ c | |
970 | .long __und_invalid @ d | |
971 | .long __und_invalid @ e | |
972 | .long __und_invalid @ f | |
973 | ||
974 | .align 5 | |
975 | ||
976 | /*============================================================================= | |
977 | * Undefined FIQs | |
978 | *----------------------------------------------------------------------------- | |
979 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
980 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
981 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
982 | * damage alert! I don't think that we can execute any code in here in any | |
983 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
984 | * get out of that mode without clobbering one register. | |
985 | */ | |
986 | vector_fiq: | |
987 | disable_fiq | |
988 | subs pc, lr, #4 | |
989 | ||
990 | /*============================================================================= | |
991 | * Address exception handler | |
992 | *----------------------------------------------------------------------------- | |
993 | * These aren't too critical. | |
994 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
995 | */ | |
996 | ||
997 | vector_addrexcptn: | |
998 | b vector_addrexcptn | |
999 | ||
1000 | /* | |
1001 | * We group all the following data together to optimise | |
1002 | * for CPUs with separate I & D caches. | |
1003 | */ | |
1004 | .align 5 | |
1005 | ||
1006 | .LCvswi: | |
1007 | .word vector_swi | |
1008 | ||
7933523d | 1009 | .globl __stubs_end |
1da177e4 LT |
1010 | __stubs_end: |
1011 | ||
7933523d | 1012 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1013 | |
7933523d RK |
1014 | .globl __vectors_start |
1015 | __vectors_start: | |
1da177e4 | 1016 | swi SYS_ERROR0 |
7933523d RK |
1017 | b vector_und + stubs_offset |
1018 | ldr pc, .LCvswi + stubs_offset | |
1019 | b vector_pabt + stubs_offset | |
1020 | b vector_dabt + stubs_offset | |
1021 | b vector_addrexcptn + stubs_offset | |
1022 | b vector_irq + stubs_offset | |
1023 | b vector_fiq + stubs_offset | |
1024 | ||
1025 | .globl __vectors_end | |
1026 | __vectors_end: | |
1da177e4 LT |
1027 | |
1028 | .data | |
1029 | ||
1da177e4 LT |
1030 | .globl cr_alignment |
1031 | .globl cr_no_alignment | |
1032 | cr_alignment: | |
1033 | .space 4 | |
1034 | cr_no_alignment: | |
1035 | .space 4 |