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[SCSI] qla2xxx: Fail initialization if unable to load RISC code.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
2d70c103
NB		 44int ql2xenableclass2;
45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
1da177e4 50int ql2xlogintimeout = 20;
f2019cb1 51module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 52MODULE_PARM_DESC(ql2xlogintimeout,
53 "Login timeout value in seconds.");
54
a7b61842 55int qlport_down_retry;
f2019cb1 56module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 57MODULE_PARM_DESC(qlport_down_retry,
900d9f98 58 "Maximum number of command retries to a port that returns "
1da177e4
LT		 59 "a PORT-DOWN status.");
60
1da177e4
LT		 61int ql2xplogiabsentdevice;
62module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
63MODULE_PARM_DESC(ql2xplogiabsentdevice,
64 "Option to enable PLOGI to devices that are not present after "
900d9f98 65 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 66 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
67
1da177e4 68int ql2xloginretrycount = 0;
f2019cb1 69module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 70MODULE_PARM_DESC(ql2xloginretrycount,
71 "Specify an alternate value for the NVRAM login retry count.");
72
a7a167bf 73int ql2xallocfwdump = 1;
f2019cb1 74module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 75MODULE_PARM_DESC(ql2xallocfwdump,
76 "Option to enable allocation of memory for a firmware dump "
77 "during HBA initialization. Memory allocation requirements "
78 "vary by ISP type. Default is 1 - allocate memory.");
79
11010fec 80int ql2xextended_error_logging;
27d94035 81module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 82MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 83 "Option to enable extended error logging,\n"
84 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
85 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
86 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
87 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
88 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
89 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
90 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
91 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
92 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 93 "\t\t0x1e400000 - Preferred value for capturing essential "
94 "debug information (equivalent to old "
95 "ql2xextended_error_logging=1).\n"
3ce8866c 96 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 97
a9083016 98int ql2xshiftctondsd = 6;
f2019cb1 99module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 100MODULE_PARM_DESC(ql2xshiftctondsd,
101 "Set to control shifting of command type processing "
102 "based on total number of SG elements.");
103
1da177e4
LT		 104static void qla2x00_free_device(scsi_qla_host_t *);
105
7e47e5ca 106int ql2xfdmienable=1;
f2019cb1 107module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 108MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 109 "Enables FDMI registrations. "
110 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 111
df7baa50
AV		 112#define MAX_Q_DEPTH 32
113static int ql2xmaxqdepth = MAX_Q_DEPTH;
114module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
115MODULE_PARM_DESC(ql2xmaxqdepth,
116 "Maximum queue depth to report for target devices.");
117
bad75002 118/* Do not change the value of this after module load */
8cb2049c 119int ql2xenabledif = 0;
bad75002
AE		 120module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xenabledif,
122 " Enable T10-CRC-DIF "
8cb2049c
AE		 123 " Default is 0 - No DIF Support. 1 - Enable it"
124 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 125
8cb2049c 126int ql2xenablehba_err_chk = 2;
bad75002
AE		 127module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
128MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 129 " Enable T10-CRC-DIF Error isolation by HBA:\n"
130 " Default is 1.\n"
131 " 0 -- Error isolation disabled\n"
132 " 1 -- Error isolation enabled only for DIX Type 0\n"
133 " 2 -- Error isolation enabled for all Types\n");
bad75002 134
e5896bd5 135int ql2xiidmaenable=1;
f2019cb1 136module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 137MODULE_PARM_DESC(ql2xiidmaenable,
138 "Enables iIDMA settings "
139 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
140
73208dfd 141int ql2xmaxqueues = 1;
f2019cb1 142module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 143MODULE_PARM_DESC(ql2xmaxqueues,
144 "Enables MQ settings "
ae68230c
JP		 145 "Default is 1 for single queue. Set it to number "
146 "of queues in MQ mode.");
68ca949c
AC		 147
148int ql2xmultique_tag;
f2019cb1 149module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 150MODULE_PARM_DESC(ql2xmultique_tag,
151 "Enables CPU affinity settings for the driver "
152 "Default is 0 for no affinity of request and response IO. "
153 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 154
155int ql2xfwloadbin;
86e45bf6 156module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
82515920
AV		 202uint ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, uint, S_IRUGO);
204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
1da177e4 221/*
fa2a1ce5 222 * SCSI host template entry points
1da177e4
LT		 223 */
224static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 225static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 226static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
227static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 228static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 229static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 230static int qla2xxx_eh_abort(struct scsi_cmnd *);
231static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 232static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 233static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
234static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 235
e881a172 236static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 237static int qla2x00_change_queue_type(struct scsi_device *, int);
238
a5326f86 239struct scsi_host_template qla2xxx_driver_template = {
1da177e4 240 .module = THIS_MODULE,
cb63067a 241 .name = QLA2XXX_DRIVER_NAME,
a5326f86 242 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 243
244 .eh_abort_handler = qla2xxx_eh_abort,
245 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 246 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 247 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
248 .eh_host_reset_handler = qla2xxx_eh_host_reset,
249
250 .slave_configure = qla2xxx_slave_configure,
251
252 .slave_alloc = qla2xxx_slave_alloc,
253 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 254 .scan_finished = qla2xxx_scan_finished,
255 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 256 .change_queue_depth = qla2x00_change_queue_depth,
257 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 258 .this_id = -1,
259 .cmd_per_lun = 3,
260 .use_clustering = ENABLE_CLUSTERING,
261 .sg_tablesize = SG_ALL,
262
263 .max_sectors = 0xFFFF,
afb046e2 264 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 265
266 .supported_mode = MODE_INITIATOR,
fca29703
AV		 267};
268
1da177e4 269static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 270struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 271
1da177e4
LT		 272/* TODO Convert to inlines
273 *
274 * Timer routines
275 */
1da177e4 276
2c3dfe3f 277__inline__ void
e315cd28 278qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 279{
e315cd28
AC		 280 init_timer(&vha->timer);
281 vha->timer.expires = jiffies + interval * HZ;
282 vha->timer.data = (unsigned long)vha;
283 vha->timer.function = (void (*)(unsigned long))func;
284 add_timer(&vha->timer);
285 vha->timer_active = 1;
1da177e4
LT		 286}
287
288static inline void
e315cd28 289qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 290{
a9083016 291 /* Currently used for 82XX only. */
7c3df132
SK		 292 if (vha->device_flags & DFLG_DEV_FAILED) {
293 ql_dbg(ql_dbg_timer, vha, 0x600d,
294 "Device in a failed state, returning.\n");
a9083016 295 return;
7c3df132 296 }
a9083016 297
e315cd28 298 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 299}
300
a824ebb3 301static __inline__ void
e315cd28 302qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 303{
e315cd28
AC		 304 del_timer_sync(&vha->timer);
305 vha->timer_active = 0;
1da177e4
LT		 306}
307
1da177e4
LT		 308static int qla2x00_do_dpc(void *data);
309
310static void qla2x00_rst_aen(scsi_qla_host_t *);
311
73208dfd
AC		 312static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
313 struct req_que **, struct rsp_que **);
e30d1756 314static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 315static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 316
1da177e4 317/* -------------------------------------------------------------------------- */
9a347ff4
CD		 318static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
319 struct rsp_que *rsp)
73208dfd 320{
7c3df132 321 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 322 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 323 GFP_KERNEL);
324 if (!ha->req_q_map) {
7c3df132
SK		 325 ql_log(ql_log_fatal, vha, 0x003b,
326 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 327 goto fail_req_map;
328 }
329
2afa19a9 330 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 331 GFP_KERNEL);
332 if (!ha->rsp_q_map) {
7c3df132
SK		 333 ql_log(ql_log_fatal, vha, 0x003c,
334 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 335 goto fail_rsp_map;
336 }
9a347ff4
CD		 337 /*
338 * Make sure we record at least the request and response queue zero in
339 * case we need to free them if part of the probe fails.
340 */
341 ha->rsp_q_map[0] = rsp;
342 ha->req_q_map[0] = req;
73208dfd
AC		 343 set_bit(0, ha->rsp_qid_map);
344 set_bit(0, ha->req_qid_map);
345 return 1;
346
347fail_rsp_map:
348 kfree(ha->req_q_map);
349 ha->req_q_map = NULL;
350fail_req_map:
351 return -ENOMEM;
352}
353
2afa19a9 354static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 355{
73208dfd
AC		 356 if (req && req->ring)
357 dma_free_coherent(&ha->pdev->dev,
358 (req->length + 1) * sizeof(request_t),
359 req->ring, req->dma);
360
361 kfree(req);
362 req = NULL;
363}
364
2afa19a9
AC		 365static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
366{
367 if (rsp && rsp->ring)
368 dma_free_coherent(&ha->pdev->dev,
369 (rsp->length + 1) * sizeof(response_t),
370 rsp->ring, rsp->dma);
371
372 kfree(rsp);
373 rsp = NULL;
374}
375
73208dfd
AC		 376static void qla2x00_free_queues(struct qla_hw_data *ha)
377{
378 struct req_que *req;
379 struct rsp_que *rsp;
380 int cnt;
381
2afa19a9 382 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 383 req = ha->req_q_map[cnt];
2afa19a9 384 qla2x00_free_req_que(ha, req);
73208dfd 385 }
73208dfd
AC		 386 kfree(ha->req_q_map);
387 ha->req_q_map = NULL;
2afa19a9
AC		 388
389 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
390 rsp = ha->rsp_q_map[cnt];
391 qla2x00_free_rsp_que(ha, rsp);
392 }
393 kfree(ha->rsp_q_map);
394 ha->rsp_q_map = NULL;
73208dfd
AC		 395}
396
68ca949c
AC		 397static int qla25xx_setup_mode(struct scsi_qla_host *vha)
398{
399 uint16_t options = 0;
400 int ques, req, ret;
401 struct qla_hw_data *ha = vha->hw;
402
7163ea81 403 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 404 ql_log(ql_log_warn, vha, 0x00d8,
405 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 406 goto fail;
407 }
68ca949c 408 if (ql2xmultique_tag) {
68ca949c
AC		 409 /* create a request queue for IO */
410 options |= BIT_7;
411 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
412 QLA_DEFAULT_QUE_QOS);
413 if (!req) {
7c3df132
SK		 414 ql_log(ql_log_warn, vha, 0x00e0,
415 "Failed to create request queue.\n");
68ca949c
AC		 416 goto fail;
417 }
278274d5 418 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 419 vha->req = ha->req_q_map[req];
420 options |= BIT_1;
421 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
422 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
423 if (!ret) {
7c3df132
SK		 424 ql_log(ql_log_warn, vha, 0x00e8,
425 "Failed to create response queue.\n");
68ca949c
AC		 426 goto fail2;
427 }
428 }
7163ea81 429 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 430 ql_dbg(ql_dbg_multiq, vha, 0xc007,
431 "CPU affinity mode enalbed, "
432 "no. of response queues:%d no. of request queues:%d.\n",
433 ha->max_rsp_queues, ha->max_req_queues);
434 ql_dbg(ql_dbg_init, vha, 0x00e9,
435 "CPU affinity mode enalbed, "
436 "no. of response queues:%d no. of request queues:%d.\n",
437 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 438 }
439 return 0;
440fail2:
441 qla25xx_delete_queues(vha);
7163ea81
AC		 442 destroy_workqueue(ha->wq);
443 ha->wq = NULL;
0cd33fcf 444 vha->req = ha->req_q_map[0];
68ca949c
AC		 445fail:
446 ha->mqenable = 0;
7163ea81
AC		 447 kfree(ha->req_q_map);
448 kfree(ha->rsp_q_map);
449 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 450 return 1;
451}
452
1da177e4 453static char *
e315cd28 454qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 455{
e315cd28 456 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 457 static char *pci_bus_modes[] = {
458 "33", "66", "100", "133",
459 };
460 uint16_t pci_bus;
461
462 strcpy(str, "PCI");
463 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
464 if (pci_bus) {
465 strcat(str, "-X (");
466 strcat(str, pci_bus_modes[pci_bus]);
467 } else {
468 pci_bus = (ha->pci_attr & BIT_8) >> 8;
469 strcat(str, " (");
470 strcat(str, pci_bus_modes[pci_bus]);
471 }
472 strcat(str, " MHz)");
473
474 return (str);
475}
476
fca29703 477static char *
e315cd28 478qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 479{
480 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 481 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 482 uint32_t pci_bus;
483 int pcie_reg;
484
e67f1321 485 pcie_reg = pci_pcie_cap(ha->pdev);
fca29703
AV		 486 if (pcie_reg) {
487 char lwstr[6];
488 uint16_t pcie_lstat, lspeed, lwidth;
489
e67f1321 490 pcie_reg += PCI_EXP_LNKCAP;
fca29703
AV		 491 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
492 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
493 lwidth = (pcie_lstat &
494 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
495
496 strcpy(str, "PCIe (");
497 if (lspeed == 1)
c87a0d8c 498 strcat(str, "2.5GT/s ");
c3a2f0df 499 else if (lspeed == 2)
c87a0d8c 500 strcat(str, "5.0GT/s ");
fca29703
AV		 501 else
502 strcat(str, "<unknown> ");
503 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
504 strcat(str, lwstr);
505
506 return str;
507 }
508
509 strcpy(str, "PCI");
510 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
511 if (pci_bus == 0 || pci_bus == 8) {
512 strcat(str, " (");
513 strcat(str, pci_bus_modes[pci_bus >> 3]);
514 } else {
515 strcat(str, "-X ");
516 if (pci_bus & BIT_2)
517 strcat(str, "Mode 2");
518 else
519 strcat(str, "Mode 1");
520 strcat(str, " (");
521 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
522 }
523 strcat(str, " MHz)");
524
525 return str;
526}
527
e5f82ab8 528static char *
e315cd28 529qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 530{
531 char un_str[10];
e315cd28 532 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 533
1da177e4
LT		 534 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
535 ha->fw_minor_version,
536 ha->fw_subminor_version);
537
538 if (ha->fw_attributes & BIT_9) {
539 strcat(str, "FLX");
540 return (str);
541 }
542
543 switch (ha->fw_attributes & 0xFF) {
544 case 0x7:
545 strcat(str, "EF");
546 break;
547 case 0x17:
548 strcat(str, "TP");
549 break;
550 case 0x37:
551 strcat(str, "IP");
552 break;
553 case 0x77:
554 strcat(str, "VI");
555 break;
556 default:
557 sprintf(un_str, "(%x)", ha->fw_attributes);
558 strcat(str, un_str);
559 break;
560 }
561 if (ha->fw_attributes & 0x100)
562 strcat(str, "X");
563
564 return (str);
565}
566
e5f82ab8 567static char *
e315cd28 568qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 569{
e315cd28 570 struct qla_hw_data *ha = vha->hw;
f0883ac6 571
3a03eb79
AV		 572 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
573 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 574 return str;
fca29703
AV		 575}
576
9ba56b95
GM		 577void
578qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 579{
9ba56b95
GM		 580 srb_t *sp = (srb_t *)ptr;
581 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
582 struct qla_hw_data *ha = sp->fcport->vha->hw;
583 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 584
9ba56b95
GM		 585 if (sp->flags & SRB_DMA_VALID) {
586 scsi_dma_unmap(cmd);
587 sp->flags &= ~SRB_DMA_VALID;
7c3df132 588 }
fca29703 589
9ba56b95
GM		 590 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
591 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
592 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
593 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
594 }
595
596 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
597 /* List assured to be having elements */
598 qla2x00_clean_dsd_pool(ha, sp);
599 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
600 }
601
602 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
603 dma_pool_free(ha->dl_dma_pool, ctx,
604 ((struct crc_context *)ctx)->crc_ctx_dma);
605 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
606 }
607
608 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
609 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 610
9ba56b95
GM		 611 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
612 ctx1->fcp_cmnd_dma);
613 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
614 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
615 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
616 mempool_free(ctx1, ha->ctx_mempool);
617 ctx1 = NULL;
618 }
619
620 CMD_SP(cmd) = NULL;
621 mempool_free(sp, ha->srb_mempool);
622}
623
624static void
625qla2x00_sp_compl(void *data, void *ptr, int res)
626{
627 struct qla_hw_data *ha = (struct qla_hw_data *)data;
628 srb_t *sp = (srb_t *)ptr;
629 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
630
631 cmd->result = res;
632
633 if (atomic_read(&sp->ref_count) == 0) {
634 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
635 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
636 sp, GET_CMD_SP(sp));
637 if (ql2xextended_error_logging & ql_dbg_io)
638 BUG();
639 return;
640 }
641 if (!atomic_dec_and_test(&sp->ref_count))
642 return;
643
644 qla2x00_sp_free_dma(ha, sp);
645 cmd->scsi_done(cmd);
fca29703
AV		 646}
647
1da177e4 648static int
f5e3e40b 649qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 650{
134ae078 651 scsi_qla_host_t *vha = shost_priv(host);
fca29703 652 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 653 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 654 struct qla_hw_data *ha = vha->hw;
655 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 656 srb_t *sp;
657 int rval;
658
85880801 659 if (ha->flags.eeh_busy) {
7c3df132 660 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 661 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 662 "PCI Channel IO permanent failure, exiting "
663 "cmd=%p.\n", cmd);
b9b12f73 664 cmd->result = DID_NO_CONNECT << 16;
7c3df132 665 } else {
5f28d2d7 666 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 667 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 668 cmd->result = DID_REQUEUE << 16;
7c3df132 669 }
14e660e6
SJ		 670 goto qc24_fail_command;
671 }
672
19a7b4ae
JSEC		 673 rval = fc_remote_port_chkready(rport);
674 if (rval) {
675 cmd->result = rval;
5f28d2d7 676 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 677 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
678 cmd, rval);
fca29703
AV		 679 goto qc24_fail_command;
680 }
681
bad75002
AE		 682 if (!vha->flags.difdix_supported &&
683 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 684 ql_dbg(ql_dbg_io, vha, 0x3004,
685 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
686 cmd);
bad75002
AE		 687 cmd->result = DID_NO_CONNECT << 16;
688 goto qc24_fail_command;
689 }
aa651be8
CD		 690
691 if (!fcport) {
692 cmd->result = DID_NO_CONNECT << 16;
693 goto qc24_fail_command;
694 }
695
fca29703
AV		 696 if (atomic_read(&fcport->state) != FCS_ONLINE) {
697 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 698 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 699 ql_dbg(ql_dbg_io, vha, 0x3005,
700 "Returning DNC, fcport_state=%d loop_state=%d.\n",
701 atomic_read(&fcport->state),
702 atomic_read(&base_vha->loop_state));
fca29703
AV		 703 cmd->result = DID_NO_CONNECT << 16;
704 goto qc24_fail_command;
705 }
7b594131 706 goto qc24_target_busy;
fca29703
AV		 707 }
708
9ba56b95 709 sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC);
fca29703 710 if (!sp)
f5e3e40b 711 goto qc24_host_busy;
fca29703 712
9ba56b95
GM		 713 sp->u.scmd.cmd = cmd;
714 sp->type = SRB_SCSI_CMD;
715 atomic_set(&sp->ref_count, 1);
716 CMD_SP(cmd) = (void *)sp;
717 sp->free = qla2x00_sp_free_dma;
718 sp->done = qla2x00_sp_compl;
719
e315cd28 720 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 721 if (rval != QLA_SUCCESS) {
722 ql_dbg(ql_dbg_io, vha, 0x3013,
723 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 724 goto qc24_host_busy_free_sp;
7c3df132 725 }
fca29703 726
fca29703
AV		 727 return 0;
728
729qc24_host_busy_free_sp:
9ba56b95 730 qla2x00_sp_free_dma(ha, sp);
fca29703 731
f5e3e40b 732qc24_host_busy:
fca29703
AV		 733 return SCSI_MLQUEUE_HOST_BUSY;
734
7b594131
MC		 735qc24_target_busy:
736 return SCSI_MLQUEUE_TARGET_BUSY;
737
fca29703 738qc24_fail_command:
f5e3e40b 739 cmd->scsi_done(cmd);
fca29703
AV		 740
741 return 0;
742}
743
1da177e4
LT		 744/*
745 * qla2x00_eh_wait_on_command
746 * Waits for the command to be returned by the Firmware for some
747 * max time.
748 *
749 * Input:
1da177e4 750 * cmd = Scsi Command to wait on.
1da177e4
LT		 751 *
752 * Return:
753 * Not Found : 0
754 * Found : 1
755 */
756static int
e315cd28 757qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 758{
fe74c71f
AV		 759#define ABORT_POLLING_PERIOD 1000
760#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 761 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 762 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
763 struct qla_hw_data *ha = vha->hw;
f4f051eb 764 int ret = QLA_SUCCESS;
1da177e4 765
85880801 766 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 767 ql_dbg(ql_dbg_taskm, vha, 0x8005,
768 "Return:eh_wait.\n");
85880801
AV		 769 return ret;
770 }
771
d970432c 772 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 773 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 774 }
775 if (CMD_SP(cmd))
776 ret = QLA_FUNCTION_FAILED;
1da177e4 777
f4f051eb 778 return ret;
1da177e4
LT		 779}
780
781/*
782 * qla2x00_wait_for_hba_online
fa2a1ce5 783 * Wait till the HBA is online after going through
1da177e4
LT		 784 * <= MAX_RETRIES_OF_ISP_ABORT or
785 * finally HBA is disabled ie marked offline
786 *
787 * Input:
788 * ha - pointer to host adapter structure
fa2a1ce5
AV		 789 *
790 * Note:
1da177e4
LT		 791 * Does context switching-Release SPIN_LOCK
792 * (if any) before calling this routine.
793 *
794 * Return:
795 * Success (Adapter is online) : 0
796 * Failed (Adapter is offline/disabled) : 1
797 */
854165f4 798int
e315cd28 799qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 800{
fca29703
AV		 801 int return_status;
802 unsigned long wait_online;
e315cd28
AC		 803 struct qla_hw_data *ha = vha->hw;
804 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 805
fa2a1ce5 806 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 807 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
808 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
809 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
810 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 811
812 msleep(1000);
813 }
e315cd28 814 if (base_vha->flags.online)
fa2a1ce5 815 return_status = QLA_SUCCESS;
1da177e4
LT		 816 else
817 return_status = QLA_FUNCTION_FAILED;
818
1da177e4
LT		 819 return (return_status);
820}
821
86fbee86
LC		 822/*
823 * qla2x00_wait_for_reset_ready
824 * Wait till the HBA is online after going through
825 * <= MAX_RETRIES_OF_ISP_ABORT or
826 * finally HBA is disabled ie marked offline or flash
827 * operations are in progress.
828 *
829 * Input:
830 * ha - pointer to host adapter structure
831 *
832 * Note:
833 * Does context switching-Release SPIN_LOCK
834 * (if any) before calling this routine.
835 *
836 * Return:
837 * Success (Adapter is online/no flash ops) : 0
838 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
839 */
3dbe756a 840static int
86fbee86
LC		 841qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
842{
843 int return_status;
844 unsigned long wait_online;
845 struct qla_hw_data *ha = vha->hw;
846 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
847
848 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
849 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
850 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
851 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
852 ha->optrom_state != QLA_SWAITING ||
853 ha->dpc_active) && time_before(jiffies, wait_online))
854 msleep(1000);
855
856 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
857 return_status = QLA_SUCCESS;
858 else
859 return_status = QLA_FUNCTION_FAILED;
860
7c3df132
SK		 861 ql_dbg(ql_dbg_taskm, vha, 0x8019,
862 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 863
864 return return_status;
865}
866
2533cf67
LC		 867int
868qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
869{
870 int return_status;
871 unsigned long wait_reset;
872 struct qla_hw_data *ha = vha->hw;
873 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
874
875 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
876 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
877 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
878 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
879 ha->dpc_active) && time_before(jiffies, wait_reset)) {
880
881 msleep(1000);
882
883 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
884 ha->flags.chip_reset_done)
885 break;
886 }
887 if (ha->flags.chip_reset_done)
888 return_status = QLA_SUCCESS;
889 else
890 return_status = QLA_FUNCTION_FAILED;
891
892 return return_status;
893}
894
083a469d
GM		 895static void
896sp_get(struct srb *sp)
897{
898 atomic_inc(&sp->ref_count);
899}
900
1da177e4
LT		 901/**************************************************************************
902* qla2xxx_eh_abort
903*
904* Description:
905* The abort function will abort the specified command.
906*
907* Input:
908* cmd = Linux SCSI command packet to be aborted.
909*
910* Returns:
911* Either SUCCESS or FAILED.
912*
913* Note:
2ea00202 914* Only return FAILED if command not returned by firmware.
1da177e4 915**************************************************************************/
e5f82ab8 916static int
1da177e4
LT		 917qla2xxx_eh_abort(struct scsi_cmnd *cmd)
918{
e315cd28 919 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 920 srb_t *sp;
4e98d3b8 921 int ret;
f4f051eb 922 unsigned int id, lun;
18e144d3 923 unsigned long flags;
2ea00202 924 int wait = 0;
e315cd28 925 struct qla_hw_data *ha = vha->hw;
1da177e4 926
f4f051eb 927 if (!CMD_SP(cmd))
2ea00202 928 return SUCCESS;
1da177e4 929
4e98d3b8
AV		 930 ret = fc_block_scsi_eh(cmd);
931 if (ret != 0)
932 return ret;
933 ret = SUCCESS;
934
f4f051eb
AV		 935 id = cmd->device->id;
936 lun = cmd->device->lun;
1da177e4 937
e315cd28 938 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 939 sp = (srb_t *) CMD_SP(cmd);
940 if (!sp) {
941 spin_unlock_irqrestore(&ha->hardware_lock, flags);
942 return SUCCESS;
943 }
1da177e4 944
7c3df132 945 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 946 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
947 vha->host_no, id, lun, sp, cmd);
17d98630 948
170babc3
MC		 949 /* Get a reference to the sp and drop the lock.*/
950 sp_get(sp);
083a469d 951
e315cd28 952 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 953 if (ha->isp_ops->abort_command(sp)) {
a55aac79 954 ret = FAILED;
7c3df132 955 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 956 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 957 } else {
7c3df132 958 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 959 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 960 wait = 1;
961 }
75942064
SK		 962
963 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 964 sp->done(ha, sp, 0);
75942064 965 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 966
bc91ade9
CD		 967 /* Did the command return during mailbox execution? */
968 if (ret == FAILED && !CMD_SP(cmd))
969 ret = SUCCESS;
970
f4f051eb 971 /* Wait for the command to be returned. */
2ea00202 972 if (wait) {
e315cd28 973 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 974 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 975 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 976 ret = FAILED;
f4f051eb 977 }
1da177e4 978 }
1da177e4 979
7c3df132 980 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 981 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
982 vha->host_no, id, lun, wait, ret);
1da177e4 983
f4f051eb
AV		 984 return ret;
985}
1da177e4 986
4d78c973 987int
e315cd28 988qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 989 unsigned int l, enum nexus_wait_type type)
f4f051eb 990{
17d98630 991 int cnt, match, status;
18e144d3 992 unsigned long flags;
e315cd28 993 struct qla_hw_data *ha = vha->hw;
73208dfd 994 struct req_que *req;
4d78c973 995 srb_t *sp;
9ba56b95 996 struct scsi_cmnd *cmd;
1da177e4 997
523ec773 998 status = QLA_SUCCESS;
17d98630 999
e315cd28 1000 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1001 req = vha->req;
17d98630
AC		 1002 for (cnt = 1; status == QLA_SUCCESS &&
1003 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1004 sp = req->outstanding_cmds[cnt];
1005 if (!sp)
523ec773 1006 continue;
9ba56b95 1007 if (sp->type != SRB_SCSI_CMD)
cf53b069 1008 continue;
17d98630
AC		 1009 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1010 continue;
1011 match = 0;
9ba56b95 1012 cmd = GET_CMD_SP(sp);
17d98630
AC		 1013 switch (type) {
1014 case WAIT_HOST:
1015 match = 1;
1016 break;
1017 case WAIT_TARGET:
9ba56b95 1018 match = cmd->device->id == t;
17d98630
AC		 1019 break;
1020 case WAIT_LUN:
9ba56b95
GM		 1021 match = (cmd->device->id == t &&
1022 cmd->device->lun == l);
17d98630 1023 break;
73208dfd 1024 }
17d98630
AC		 1025 if (!match)
1026 continue;
1027
1028 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1029 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1030 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1031 }
e315cd28 1032 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1033
1034 return status;
1da177e4
LT		 1035}
1036
523ec773
AV		 1037static char *reset_errors[] = {
1038 "HBA not online",
1039 "HBA not ready",
1040 "Task management failed",
1041 "Waiting for command completions",
1042};
1da177e4 1043
e5f82ab8 1044static int
523ec773 1045__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1046 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1047{
e315cd28 1048 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1049 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1050 int err;
1da177e4 1051
7c3df132 1052 if (!fcport) {
523ec773 1053 return FAILED;
7c3df132 1054 }
1da177e4 1055
4e98d3b8
AV		 1056 err = fc_block_scsi_eh(cmd);
1057 if (err != 0)
1058 return err;
1059
7c3df132 1060 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1061 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1062 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1063
523ec773 1064 err = 0;
7c3df132
SK		 1065 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1066 ql_log(ql_log_warn, vha, 0x800a,
1067 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1068 goto eh_reset_failed;
7c3df132 1069 }
523ec773 1070 err = 2;
2afa19a9 1071 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1072 != QLA_SUCCESS) {
1073 ql_log(ql_log_warn, vha, 0x800c,
1074 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1075 goto eh_reset_failed;
7c3df132 1076 }
523ec773 1077 err = 3;
e315cd28 1078 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1079 cmd->device->lun, type) != QLA_SUCCESS) {
1080 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1081 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1082 goto eh_reset_failed;
7c3df132 1083 }
523ec773 1084
7c3df132 1085 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1086 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1087 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1088
1089 return SUCCESS;
1090
4d78c973 1091eh_reset_failed:
7c3df132 1092 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1093 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1094 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1095 cmd);
523ec773
AV		 1096 return FAILED;
1097}
1da177e4 1098
523ec773
AV		 1099static int
1100qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1101{
e315cd28
AC		 1102 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1103 struct qla_hw_data *ha = vha->hw;
1da177e4 1104
523ec773
AV		 1105 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1106 ha->isp_ops->lun_reset);
1da177e4
LT		 1107}
1108
1da177e4 1109static int
523ec773 1110qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1111{
e315cd28
AC		 1112 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1113 struct qla_hw_data *ha = vha->hw;
1da177e4 1114
523ec773
AV		 1115 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1116 ha->isp_ops->target_reset);
1da177e4
LT		 1117}
1118
1da177e4
LT		 1119/**************************************************************************
1120* qla2xxx_eh_bus_reset
1121*
1122* Description:
1123* The bus reset function will reset the bus and abort any executing
1124* commands.
1125*
1126* Input:
1127* cmd = Linux SCSI command packet of the command that cause the
1128* bus reset.
1129*
1130* Returns:
1131* SUCCESS/FAILURE (defined as macro in scsi.h).
1132*
1133**************************************************************************/
e5f82ab8 1134static int
1da177e4
LT		 1135qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1136{
e315cd28 1137 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1138 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1139 int ret = FAILED;
f4f051eb 1140 unsigned int id, lun;
f4f051eb 1141
f4f051eb
AV		 1142 id = cmd->device->id;
1143 lun = cmd->device->lun;
1da177e4 1144
7c3df132 1145 if (!fcport) {
f4f051eb 1146 return ret;
7c3df132 1147 }
1da177e4 1148
4e98d3b8
AV		 1149 ret = fc_block_scsi_eh(cmd);
1150 if (ret != 0)
1151 return ret;
1152 ret = FAILED;
1153
7c3df132 1154 ql_log(ql_log_info, vha, 0x8012,
46270afe 1155 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1156
e315cd28 1157 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1158 ql_log(ql_log_fatal, vha, 0x8013,
1159 "Wait for hba online failed board disabled.\n");
f4f051eb 1160 goto eh_bus_reset_done;
1da177e4
LT		 1161 }
1162
ad537689
SK		 1163 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1164 ret = SUCCESS;
1165
f4f051eb
AV		 1166 if (ret == FAILED)
1167 goto eh_bus_reset_done;
1da177e4 1168
9a41a62b 1169 /* Flush outstanding commands. */
4d78c973 1170 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1171 QLA_SUCCESS) {
1172 ql_log(ql_log_warn, vha, 0x8014,
1173 "Wait for pending commands failed.\n");
9a41a62b 1174 ret = FAILED;
7c3df132 1175 }
1da177e4 1176
f4f051eb 1177eh_bus_reset_done:
7c3df132 1178 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1179 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1180 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1181
f4f051eb 1182 return ret;
1da177e4
LT		 1183}
1184
1185/**************************************************************************
1186* qla2xxx_eh_host_reset
1187*
1188* Description:
1189* The reset function will reset the Adapter.
1190*
1191* Input:
1192* cmd = Linux SCSI command packet of the command that cause the
1193* adapter reset.
1194*
1195* Returns:
1196* Either SUCCESS or FAILED.
1197*
1198* Note:
1199**************************************************************************/
e5f82ab8 1200static int
1da177e4
LT		 1201qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1202{
e315cd28 1203 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1204 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1205 int ret = FAILED;
f4f051eb 1206 unsigned int id, lun;
e315cd28 1207 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1208
f4f051eb
AV		 1209 id = cmd->device->id;
1210 lun = cmd->device->lun;
f4f051eb 1211
7c3df132 1212 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1213 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1214
86fbee86 1215 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1216 goto eh_host_reset_lock;
1da177e4 1217
e315cd28
AC		 1218 if (vha != base_vha) {
1219 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1220 goto eh_host_reset_lock;
e315cd28 1221 } else {
a9083016
GM		 1222 if (IS_QLA82XX(vha->hw)) {
1223 if (!qla82xx_fcoe_ctx_reset(vha)) {
1224 /* Ctx reset success */
1225 ret = SUCCESS;
1226 goto eh_host_reset_lock;
1227 }
1228 /* fall thru if ctx reset failed */
1229 }
68ca949c
AC		 1230 if (ha->wq)
1231 flush_workqueue(ha->wq);
1232
e315cd28 1233 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1234 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1235 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1236 /* failed. schedule dpc to try */
1237 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1238
7c3df132
SK		 1239 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1240 ql_log(ql_log_warn, vha, 0x802a,
1241 "wait for hba online failed.\n");
e315cd28 1242 goto eh_host_reset_lock;
7c3df132 1243 }
e315cd28
AC		 1244 }
1245 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1246 }
1da177e4 1247
e315cd28 1248 /* Waiting for command to be returned to OS.*/
4d78c973 1249 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1250 QLA_SUCCESS)
f4f051eb 1251 ret = SUCCESS;
1da177e4 1252
f4f051eb 1253eh_host_reset_lock:
cfb0919c
CD		 1254 ql_log(ql_log_info, vha, 0x8017,
1255 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1256 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1257
f4f051eb
AV		 1258 return ret;
1259}
1da177e4
LT		 1260
1261/*
1262* qla2x00_loop_reset
1263* Issue loop reset.
1264*
1265* Input:
1266* ha = adapter block pointer.
1267*
1268* Returns:
1269* 0 = success
1270*/
a4722cf2 1271int
e315cd28 1272qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1273{
0c8c39af 1274 int ret;
bdf79621 1275 struct fc_port *fcport;
e315cd28 1276 struct qla_hw_data *ha = vha->hw;
1da177e4 1277
f4c496c1 1278 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1279 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1280 if (fcport->port_type != FCT_TARGET)
1281 continue;
1282
1283 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1284 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1285 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1286 "Bus Reset failed: Target Reset=%d "
1287 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1288 }
1289 }
1290 }
1291
6246b8a1 1292 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
e315cd28 1293 ret = qla2x00_full_login_lip(vha);
0c8c39af 1294 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1295 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1296 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1297 }
1298 atomic_set(&vha->loop_state, LOOP_DOWN);
1299 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1300 qla2x00_mark_all_devices_lost(vha, 0);
0c8c39af
AV		 1301 }
1302
0d6e61bc 1303 if (ha->flags.enable_lip_reset) {
e315cd28 1304 ret = qla2x00_lip_reset(vha);
ad537689 1305 if (ret != QLA_SUCCESS)
7c3df132
SK		 1306 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1307 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1308 }
1309
1da177e4 1310 /* Issue marker command only when we are going to start the I/O */
e315cd28 1311 vha->marker_needed = 1;
1da177e4 1312
0c8c39af 1313 return QLA_SUCCESS;
1da177e4
LT		 1314}
1315
df4bf0bb 1316void
e315cd28 1317qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1318{
73208dfd 1319 int que, cnt;
df4bf0bb
AV		 1320 unsigned long flags;
1321 srb_t *sp;
e315cd28 1322 struct qla_hw_data *ha = vha->hw;
73208dfd 1323 struct req_que *req;
df4bf0bb
AV		 1324
1325 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1326 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1327 req = ha->req_q_map[que];
73208dfd
AC		 1328 if (!req)
1329 continue;
1330 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1331 sp = req->outstanding_cmds[cnt];
e612d465 1332 if (sp) {
73208dfd 1333 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1334 sp->done(vha, sp, res);
73208dfd 1335 }
df4bf0bb
AV		 1336 }
1337 }
1338 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1339}
1340
f4f051eb
AV		 1341static int
1342qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1343{
bdf79621 1344 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1345
19a7b4ae 1346 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1347 return -ENXIO;
bdf79621 1348
19a7b4ae 1349 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1350
f4f051eb
AV		 1351 return 0;
1352}
1da177e4 1353
f4f051eb
AV		 1354static int
1355qla2xxx_slave_configure(struct scsi_device *sdev)
1356{
e315cd28 1357 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1358 struct req_que *req = vha->req;
8482e118 1359
f4f051eb 1360 if (sdev->tagged_supported)
73208dfd 1361 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1362 else
73208dfd 1363 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1364 return 0;
1365}
1da177e4 1366
f4f051eb
AV		 1367static void
1368qla2xxx_slave_destroy(struct scsi_device *sdev)
1369{
1370 sdev->hostdata = NULL;
1da177e4
LT		 1371}
1372
c45dd305
GM		 1373static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1374{
1375 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1376
1377 if (!scsi_track_queue_full(sdev, qdepth))
1378 return;
1379
7c3df132 1380 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1381 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1382 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1383}
1384
1385static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1386{
1387 fc_port_t *fcport = sdev->hostdata;
1388 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1389 struct req_que *req = NULL;
1390
1391 req = vha->req;
1392 if (!req)
1393 return;
1394
1395 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1396 return;
1397
1398 if (sdev->ordered_tags)
1399 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1400 else
1401 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1402
7c3df132 1403 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1404 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1405 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1406}
1407
ce7e4af7 1408static int
e881a172 1409qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1410{
c45dd305
GM		 1411 switch (reason) {
1412 case SCSI_QDEPTH_DEFAULT:
1413 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1414 break;
1415 case SCSI_QDEPTH_QFULL:
1416 qla2x00_handle_queue_full(sdev, qdepth);
1417 break;
1418 case SCSI_QDEPTH_RAMP_UP:
1419 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1420 break;
1421 default:
08002af2 1422 return -EOPNOTSUPP;
c45dd305 1423 }
e881a172 1424
ce7e4af7
AV		 1425 return sdev->queue_depth;
1426}
1427
1428static int
1429qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1430{
1431 if (sdev->tagged_supported) {
1432 scsi_set_tag_type(sdev, tag_type);
1433 if (tag_type)
1434 scsi_activate_tcq(sdev, sdev->queue_depth);
1435 else
1436 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1437 } else
1438 tag_type = 0;
1439
1440 return tag_type;
1441}
1442
1da177e4
LT		 1443/**
1444 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1445 * @ha: HA context
1446 *
1447 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1448 * supported addressing method.
1449 */
1450static void
53303c42 1451qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1452{
7524f9b9 1453 /* Assume a 32bit DMA mask. */
1da177e4 1454 ha->flags.enable_64bit_addressing = 0;
1da177e4 1455
6a35528a 1456 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1457 /* Any upper-dword bits set? */
1458 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1459 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1460 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1461 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1462 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1463 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1464 return;
1da177e4 1465 }
1da177e4 1466 }
7524f9b9 1467
284901a9
YH		 1468 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1469 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1470}
1471
fd34f556 1472static void
e315cd28 1473qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1474{
1475 unsigned long flags = 0;
1476 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1477
1478 spin_lock_irqsave(&ha->hardware_lock, flags);
1479 ha->interrupts_on = 1;
1480 /* enable risc and host interrupts */
1481 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1482 RD_REG_WORD(&reg->ictrl);
1483 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1484
1485}
1486
1487static void
e315cd28 1488qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1489{
1490 unsigned long flags = 0;
1491 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1492
1493 spin_lock_irqsave(&ha->hardware_lock, flags);
1494 ha->interrupts_on = 0;
1495 /* disable risc and host interrupts */
1496 WRT_REG_WORD(&reg->ictrl, 0);
1497 RD_REG_WORD(&reg->ictrl);
1498 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1499}
1500
1501static void
e315cd28 1502qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1503{
1504 unsigned long flags = 0;
1505 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1506
1507 spin_lock_irqsave(&ha->hardware_lock, flags);
1508 ha->interrupts_on = 1;
1509 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1510 RD_REG_DWORD(&reg->ictrl);
1511 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1512}
1513
1514static void
e315cd28 1515qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1516{
1517 unsigned long flags = 0;
1518 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1519
124f85e6
AV		 1520 if (IS_NOPOLLING_TYPE(ha))
1521 return;
fd34f556
AV		 1522 spin_lock_irqsave(&ha->hardware_lock, flags);
1523 ha->interrupts_on = 0;
1524 WRT_REG_DWORD(&reg->ictrl, 0);
1525 RD_REG_DWORD(&reg->ictrl);
1526 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1527}
1528
706f457d
GM		 1529static int
1530qla2x00_iospace_config(struct qla_hw_data *ha)
1531{
1532 resource_size_t pio;
1533 uint16_t msix;
1534 int cpus;
1535
706f457d
GM		 1536 if (pci_request_selected_regions(ha->pdev, ha->bars,
1537 QLA2XXX_DRIVER_NAME)) {
1538 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1539 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1540 pci_name(ha->pdev));
1541 goto iospace_error_exit;
1542 }
1543 if (!(ha->bars & 1))
1544 goto skip_pio;
1545
1546 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1547 pio = pci_resource_start(ha->pdev, 0);
1548 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1549 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1550 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1551 "Invalid pci I/O region size (%s).\n",
1552 pci_name(ha->pdev));
1553 pio = 0;
1554 }
1555 } else {
1556 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1557 "Region #0 no a PIO resource (%s).\n",
1558 pci_name(ha->pdev));
1559 pio = 0;
1560 }
1561 ha->pio_address = pio;
1562 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1563 "PIO address=%llu.\n",
1564 (unsigned long long)ha->pio_address);
1565
1566skip_pio:
1567 /* Use MMIO operations for all accesses. */
1568 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1569 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1570 "Region #1 not an MMIO resource (%s), aborting.\n",
1571 pci_name(ha->pdev));
1572 goto iospace_error_exit;
1573 }
1574 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1575 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1576 "Invalid PCI mem region size (%s), aborting.\n",
1577 pci_name(ha->pdev));
1578 goto iospace_error_exit;
1579 }
1580
1581 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1582 if (!ha->iobase) {
1583 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1584 "Cannot remap MMIO (%s), aborting.\n",
1585 pci_name(ha->pdev));
1586 goto iospace_error_exit;
1587 }
1588
1589 /* Determine queue resources */
1590 ha->max_req_queues = ha->max_rsp_queues = 1;
1591 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1592 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1593 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1594 goto mqiobase_exit;
1595
1596 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1597 pci_resource_len(ha->pdev, 3));
1598 if (ha->mqiobase) {
1599 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1600 "MQIO Base=%p.\n", ha->mqiobase);
1601 /* Read MSIX vector size of the board */
1602 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1603 ha->msix_count = msix;
1604 /* Max queues are bounded by available msix vectors */
1605 /* queue 0 uses two msix vectors */
1606 if (ql2xmultique_tag) {
1607 cpus = num_online_cpus();
1608 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1609 (cpus + 1) : (ha->msix_count - 1);
1610 ha->max_req_queues = 2;
1611 } else if (ql2xmaxqueues > 1) {
1612 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1613 QLA_MQ_SIZE : ql2xmaxqueues;
1614 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1615 "QoS mode set, max no of request queues:%d.\n",
1616 ha->max_req_queues);
1617 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1618 "QoS mode set, max no of request queues:%d.\n",
1619 ha->max_req_queues);
1620 }
1621 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1622 "MSI-X vector count: %d.\n", msix);
1623 } else
1624 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1625 "BAR 3 not enabled.\n");
1626
1627mqiobase_exit:
1628 ha->msix_count = ha->max_rsp_queues + 1;
1629 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1630 "MSIX Count:%d.\n", ha->msix_count);
1631 return (0);
1632
1633iospace_error_exit:
1634 return (-ENOMEM);
1635}
1636
1637
6246b8a1
GM		 1638static int
1639qla83xx_iospace_config(struct qla_hw_data *ha)
1640{
1641 uint16_t msix;
1642 int cpus;
1643
1644 if (pci_request_selected_regions(ha->pdev, ha->bars,
1645 QLA2XXX_DRIVER_NAME)) {
1646 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1647 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1648 pci_name(ha->pdev));
1649
1650 goto iospace_error_exit;
1651 }
1652
1653 /* Use MMIO operations for all accesses. */
1654 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1655 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1656 "Invalid pci I/O region size (%s).\n",
1657 pci_name(ha->pdev));
1658 goto iospace_error_exit;
1659 }
1660 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1661 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1662 "Invalid PCI mem region size (%s), aborting\n",
1663 pci_name(ha->pdev));
1664 goto iospace_error_exit;
1665 }
1666
1667 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1668 if (!ha->iobase) {
1669 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1670 "Cannot remap MMIO (%s), aborting.\n",
1671 pci_name(ha->pdev));
1672 goto iospace_error_exit;
1673 }
1674
1675 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1676 /* 83XX 26XX always use MQ type access for queues
1677 * - mbar 2, a.k.a region 4 */
1678 ha->max_req_queues = ha->max_rsp_queues = 1;
1679 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1680 pci_resource_len(ha->pdev, 4));
1681
1682 if (!ha->mqiobase) {
1683 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1684 "BAR2/region4 not enabled\n");
1685 goto mqiobase_exit;
1686 }
1687
1688 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1689 pci_resource_len(ha->pdev, 2));
1690 if (ha->msixbase) {
1691 /* Read MSIX vector size of the board */
1692 pci_read_config_word(ha->pdev,
1693 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1694 ha->msix_count = msix;
1695 /* Max queues are bounded by available msix vectors */
1696 /* queue 0 uses two msix vectors */
1697 if (ql2xmultique_tag) {
1698 cpus = num_online_cpus();
1699 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1700 (cpus + 1) : (ha->msix_count - 1);
1701 ha->max_req_queues = 2;
1702 } else if (ql2xmaxqueues > 1) {
1703 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1704 QLA_MQ_SIZE : ql2xmaxqueues;
1705 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1706 "QoS mode set, max no of request queues:%d.\n",
1707 ha->max_req_queues);
1708 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1709 "QoS mode set, max no of request queues:%d.\n",
1710 ha->max_req_queues);
1711 }
1712 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1713 "MSI-X vector count: %d.\n", msix);
1714 } else
1715 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1716 "BAR 1 not enabled.\n");
1717
1718mqiobase_exit:
1719 ha->msix_count = ha->max_rsp_queues + 1;
1720 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1721 "MSIX Count:%d.\n", ha->msix_count);
1722 return 0;
1723
1724iospace_error_exit:
1725 return -ENOMEM;
1726}
1727
fd34f556
AV		 1728static struct isp_operations qla2100_isp_ops = {
1729 .pci_config = qla2100_pci_config,
1730 .reset_chip = qla2x00_reset_chip,
1731 .chip_diag = qla2x00_chip_diag,
1732 .config_rings = qla2x00_config_rings,
1733 .reset_adapter = qla2x00_reset_adapter,
1734 .nvram_config = qla2x00_nvram_config,
1735 .update_fw_options = qla2x00_update_fw_options,
1736 .load_risc = qla2x00_load_risc,
1737 .pci_info_str = qla2x00_pci_info_str,
1738 .fw_version_str = qla2x00_fw_version_str,
1739 .intr_handler = qla2100_intr_handler,
1740 .enable_intrs = qla2x00_enable_intrs,
1741 .disable_intrs = qla2x00_disable_intrs,
1742 .abort_command = qla2x00_abort_command,
523ec773
AV		 1743 .target_reset = qla2x00_abort_target,
1744 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1745 .fabric_login = qla2x00_login_fabric,
1746 .fabric_logout = qla2x00_fabric_logout,
1747 .calc_req_entries = qla2x00_calc_iocbs_32,
1748 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1749 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1750 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1751 .read_nvram = qla2x00_read_nvram_data,
1752 .write_nvram = qla2x00_write_nvram_data,
1753 .fw_dump = qla2100_fw_dump,
1754 .beacon_on = NULL,
1755 .beacon_off = NULL,
1756 .beacon_blink = NULL,
1757 .read_optrom = qla2x00_read_optrom_data,
1758 .write_optrom = qla2x00_write_optrom_data,
1759 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1760 .start_scsi = qla2x00_start_scsi,
a9083016 1761 .abort_isp = qla2x00_abort_isp,
706f457d 1762 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1763};
1764
1765static struct isp_operations qla2300_isp_ops = {
1766 .pci_config = qla2300_pci_config,
1767 .reset_chip = qla2x00_reset_chip,
1768 .chip_diag = qla2x00_chip_diag,
1769 .config_rings = qla2x00_config_rings,
1770 .reset_adapter = qla2x00_reset_adapter,
1771 .nvram_config = qla2x00_nvram_config,
1772 .update_fw_options = qla2x00_update_fw_options,
1773 .load_risc = qla2x00_load_risc,
1774 .pci_info_str = qla2x00_pci_info_str,
1775 .fw_version_str = qla2x00_fw_version_str,
1776 .intr_handler = qla2300_intr_handler,
1777 .enable_intrs = qla2x00_enable_intrs,
1778 .disable_intrs = qla2x00_disable_intrs,
1779 .abort_command = qla2x00_abort_command,
523ec773
AV		 1780 .target_reset = qla2x00_abort_target,
1781 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1782 .fabric_login = qla2x00_login_fabric,
1783 .fabric_logout = qla2x00_fabric_logout,
1784 .calc_req_entries = qla2x00_calc_iocbs_32,
1785 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1786 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1787 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1788 .read_nvram = qla2x00_read_nvram_data,
1789 .write_nvram = qla2x00_write_nvram_data,
1790 .fw_dump = qla2300_fw_dump,
1791 .beacon_on = qla2x00_beacon_on,
1792 .beacon_off = qla2x00_beacon_off,
1793 .beacon_blink = qla2x00_beacon_blink,
1794 .read_optrom = qla2x00_read_optrom_data,
1795 .write_optrom = qla2x00_write_optrom_data,
1796 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1797 .start_scsi = qla2x00_start_scsi,
a9083016 1798 .abort_isp = qla2x00_abort_isp,
706f457d 1799 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1800};
1801
1802static struct isp_operations qla24xx_isp_ops = {
1803 .pci_config = qla24xx_pci_config,
1804 .reset_chip = qla24xx_reset_chip,
1805 .chip_diag = qla24xx_chip_diag,
1806 .config_rings = qla24xx_config_rings,
1807 .reset_adapter = qla24xx_reset_adapter,
1808 .nvram_config = qla24xx_nvram_config,
1809 .update_fw_options = qla24xx_update_fw_options,
1810 .load_risc = qla24xx_load_risc,
1811 .pci_info_str = qla24xx_pci_info_str,
1812 .fw_version_str = qla24xx_fw_version_str,
1813 .intr_handler = qla24xx_intr_handler,
1814 .enable_intrs = qla24xx_enable_intrs,
1815 .disable_intrs = qla24xx_disable_intrs,
1816 .abort_command = qla24xx_abort_command,
523ec773
AV		 1817 .target_reset = qla24xx_abort_target,
1818 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1819 .fabric_login = qla24xx_login_fabric,
1820 .fabric_logout = qla24xx_fabric_logout,
1821 .calc_req_entries = NULL,
1822 .build_iocbs = NULL,
1823 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1824 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1825 .read_nvram = qla24xx_read_nvram_data,
1826 .write_nvram = qla24xx_write_nvram_data,
1827 .fw_dump = qla24xx_fw_dump,
1828 .beacon_on = qla24xx_beacon_on,
1829 .beacon_off = qla24xx_beacon_off,
1830 .beacon_blink = qla24xx_beacon_blink,
1831 .read_optrom = qla24xx_read_optrom_data,
1832 .write_optrom = qla24xx_write_optrom_data,
1833 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1834 .start_scsi = qla24xx_start_scsi,
a9083016 1835 .abort_isp = qla2x00_abort_isp,
706f457d 1836 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1837};
1838
c3a2f0df
AV		 1839static struct isp_operations qla25xx_isp_ops = {
1840 .pci_config = qla25xx_pci_config,
1841 .reset_chip = qla24xx_reset_chip,
1842 .chip_diag = qla24xx_chip_diag,
1843 .config_rings = qla24xx_config_rings,
1844 .reset_adapter = qla24xx_reset_adapter,
1845 .nvram_config = qla24xx_nvram_config,
1846 .update_fw_options = qla24xx_update_fw_options,
1847 .load_risc = qla24xx_load_risc,
1848 .pci_info_str = qla24xx_pci_info_str,
1849 .fw_version_str = qla24xx_fw_version_str,
1850 .intr_handler = qla24xx_intr_handler,
1851 .enable_intrs = qla24xx_enable_intrs,
1852 .disable_intrs = qla24xx_disable_intrs,
1853 .abort_command = qla24xx_abort_command,
523ec773
AV		 1854 .target_reset = qla24xx_abort_target,
1855 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1856 .fabric_login = qla24xx_login_fabric,
1857 .fabric_logout = qla24xx_fabric_logout,
1858 .calc_req_entries = NULL,
1859 .build_iocbs = NULL,
1860 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1861 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1862 .read_nvram = qla25xx_read_nvram_data,
1863 .write_nvram = qla25xx_write_nvram_data,
1864 .fw_dump = qla25xx_fw_dump,
1865 .beacon_on = qla24xx_beacon_on,
1866 .beacon_off = qla24xx_beacon_off,
1867 .beacon_blink = qla24xx_beacon_blink,
338c9161 1868 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1869 .write_optrom = qla24xx_write_optrom_data,
1870 .get_flash_version = qla24xx_get_flash_version,
bad75002 1871 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1872 .abort_isp = qla2x00_abort_isp,
706f457d 1873 .iospace_config = qla2x00_iospace_config,
c3a2f0df
AV		 1874};
1875
3a03eb79
AV		 1876static struct isp_operations qla81xx_isp_ops = {
1877 .pci_config = qla25xx_pci_config,
1878 .reset_chip = qla24xx_reset_chip,
1879 .chip_diag = qla24xx_chip_diag,
1880 .config_rings = qla24xx_config_rings,
1881 .reset_adapter = qla24xx_reset_adapter,
1882 .nvram_config = qla81xx_nvram_config,
1883 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1884 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1885 .pci_info_str = qla24xx_pci_info_str,
1886 .fw_version_str = qla24xx_fw_version_str,
1887 .intr_handler = qla24xx_intr_handler,
1888 .enable_intrs = qla24xx_enable_intrs,
1889 .disable_intrs = qla24xx_disable_intrs,
1890 .abort_command = qla24xx_abort_command,
1891 .target_reset = qla24xx_abort_target,
1892 .lun_reset = qla24xx_lun_reset,
1893 .fabric_login = qla24xx_login_fabric,
1894 .fabric_logout = qla24xx_fabric_logout,
1895 .calc_req_entries = NULL,
1896 .build_iocbs = NULL,
1897 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1898 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1899 .read_nvram = NULL,
1900 .write_nvram = NULL,
3a03eb79
AV		 1901 .fw_dump = qla81xx_fw_dump,
1902 .beacon_on = qla24xx_beacon_on,
1903 .beacon_off = qla24xx_beacon_off,
6246b8a1 1904 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1905 .read_optrom = qla25xx_read_optrom_data,
1906 .write_optrom = qla24xx_write_optrom_data,
1907 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1908 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1909 .abort_isp = qla2x00_abort_isp,
706f457d 1910 .iospace_config = qla2x00_iospace_config,
a9083016
GM		 1911};
1912
1913static struct isp_operations qla82xx_isp_ops = {
1914 .pci_config = qla82xx_pci_config,
1915 .reset_chip = qla82xx_reset_chip,
1916 .chip_diag = qla24xx_chip_diag,
1917 .config_rings = qla82xx_config_rings,
1918 .reset_adapter = qla24xx_reset_adapter,
1919 .nvram_config = qla81xx_nvram_config,
1920 .update_fw_options = qla24xx_update_fw_options,
1921 .load_risc = qla82xx_load_risc,
9d55ca66 1922 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1923 .fw_version_str = qla24xx_fw_version_str,
1924 .intr_handler = qla82xx_intr_handler,
1925 .enable_intrs = qla82xx_enable_intrs,
1926 .disable_intrs = qla82xx_disable_intrs,
1927 .abort_command = qla24xx_abort_command,
1928 .target_reset = qla24xx_abort_target,
1929 .lun_reset = qla24xx_lun_reset,
1930 .fabric_login = qla24xx_login_fabric,
1931 .fabric_logout = qla24xx_fabric_logout,
1932 .calc_req_entries = NULL,
1933 .build_iocbs = NULL,
1934 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1935 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1936 .read_nvram = qla24xx_read_nvram_data,
1937 .write_nvram = qla24xx_write_nvram_data,
1938 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1939 .beacon_on = qla82xx_beacon_on,
1940 .beacon_off = qla82xx_beacon_off,
1941 .beacon_blink = NULL,
a9083016
GM		 1942 .read_optrom = qla82xx_read_optrom_data,
1943 .write_optrom = qla82xx_write_optrom_data,
1944 .get_flash_version = qla24xx_get_flash_version,
1945 .start_scsi = qla82xx_start_scsi,
1946 .abort_isp = qla82xx_abort_isp,
706f457d 1947 .iospace_config = qla82xx_iospace_config,
3a03eb79
AV		 1948};
1949
6246b8a1
GM		 1950static struct isp_operations qla83xx_isp_ops = {
1951 .pci_config = qla25xx_pci_config,
1952 .reset_chip = qla24xx_reset_chip,
1953 .chip_diag = qla24xx_chip_diag,
1954 .config_rings = qla24xx_config_rings,
1955 .reset_adapter = qla24xx_reset_adapter,
1956 .nvram_config = qla81xx_nvram_config,
1957 .update_fw_options = qla81xx_update_fw_options,
1958 .load_risc = qla81xx_load_risc,
1959 .pci_info_str = qla24xx_pci_info_str,
1960 .fw_version_str = qla24xx_fw_version_str,
1961 .intr_handler = qla24xx_intr_handler,
1962 .enable_intrs = qla24xx_enable_intrs,
1963 .disable_intrs = qla24xx_disable_intrs,
1964 .abort_command = qla24xx_abort_command,
1965 .target_reset = qla24xx_abort_target,
1966 .lun_reset = qla24xx_lun_reset,
1967 .fabric_login = qla24xx_login_fabric,
1968 .fabric_logout = qla24xx_fabric_logout,
1969 .calc_req_entries = NULL,
1970 .build_iocbs = NULL,
1971 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1972 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1973 .read_nvram = NULL,
1974 .write_nvram = NULL,
1975 .fw_dump = qla83xx_fw_dump,
1976 .beacon_on = qla24xx_beacon_on,
1977 .beacon_off = qla24xx_beacon_off,
1978 .beacon_blink = qla83xx_beacon_blink,
1979 .read_optrom = qla25xx_read_optrom_data,
1980 .write_optrom = qla24xx_write_optrom_data,
1981 .get_flash_version = qla24xx_get_flash_version,
1982 .start_scsi = qla24xx_dif_start_scsi,
1983 .abort_isp = qla2x00_abort_isp,
1984 .iospace_config = qla83xx_iospace_config,
1985};
1986
ea5b6382 1987static inline void
e315cd28 1988qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 1989{
1990 ha->device_type = DT_EXTENDED_IDS;
1991 switch (ha->pdev->device) {
1992 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1993 ha->device_type |= DT_ISP2100;
1994 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1995 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 1996 break;
1997 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1998 ha->device_type |= DT_ISP2200;
1999 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2000 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2001 break;
2002 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2003 ha->device_type |= DT_ISP2300;
4a59f71d 2004 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2005 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2006 break;
2007 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2008 ha->device_type |= DT_ISP2312;
4a59f71d 2009 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2010 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2011 break;
2012 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2013 ha->device_type |= DT_ISP2322;
4a59f71d 2014 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2015 if (ha->pdev->subsystem_vendor == 0x1028 &&
2016 ha->pdev->subsystem_device == 0x0170)
2017 ha->device_type |= DT_OEM_001;
441d1072 2018 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2019 break;
2020 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2021 ha->device_type |= DT_ISP6312;
441d1072 2022 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2023 break;
2024 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2025 ha->device_type |= DT_ISP6322;
441d1072 2026 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2027 break;
2028 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2029 ha->device_type |= DT_ISP2422;
4a59f71d 2030 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2031 ha->device_type |= DT_FWI2;
c76f2c01 2032 ha->device_type |= DT_IIDMA;
441d1072 2033 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2034 break;
2035 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2036 ha->device_type |= DT_ISP2432;
4a59f71d 2037 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2038 ha->device_type |= DT_FWI2;
c76f2c01 2039 ha->device_type |= DT_IIDMA;
441d1072 2040 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2041 break;
4d4df193
HK		 2042 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2043 ha->device_type |= DT_ISP8432;
2044 ha->device_type |= DT_ZIO_SUPPORTED;
2045 ha->device_type |= DT_FWI2;
2046 ha->device_type |= DT_IIDMA;
2047 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2048 break;
044cc6c8
AV		 2049 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2050 ha->device_type |= DT_ISP5422;
e428924c 2051 ha->device_type |= DT_FWI2;
441d1072 2052 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2053 break;
044cc6c8
AV		 2054 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2055 ha->device_type |= DT_ISP5432;
e428924c 2056 ha->device_type |= DT_FWI2;
441d1072 2057 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2058 break;
c3a2f0df
AV		 2059 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2060 ha->device_type |= DT_ISP2532;
2061 ha->device_type |= DT_ZIO_SUPPORTED;
2062 ha->device_type |= DT_FWI2;
2063 ha->device_type |= DT_IIDMA;
441d1072 2064 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2065 break;
3a03eb79
AV		 2066 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2067 ha->device_type |= DT_ISP8001;
2068 ha->device_type |= DT_ZIO_SUPPORTED;
2069 ha->device_type |= DT_FWI2;
2070 ha->device_type |= DT_IIDMA;
2071 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2072 break;
a9083016
GM		 2073 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2074 ha->device_type |= DT_ISP8021;
2075 ha->device_type |= DT_ZIO_SUPPORTED;
2076 ha->device_type |= DT_FWI2;
2077 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2078 /* Initialize 82XX ISP flags */
2079 qla82xx_init_flags(ha);
2080 break;
6246b8a1
GM		 2081 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2082 ha->device_type |= DT_ISP2031;
2083 ha->device_type |= DT_ZIO_SUPPORTED;
2084 ha->device_type |= DT_FWI2;
2085 ha->device_type |= DT_IIDMA;
2086 ha->device_type |= DT_T10_PI;
2087 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2088 break;
2089 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2090 ha->device_type |= DT_ISP8031;
2091 ha->device_type |= DT_ZIO_SUPPORTED;
2092 ha->device_type |= DT_FWI2;
2093 ha->device_type |= DT_IIDMA;
2094 ha->device_type |= DT_T10_PI;
2095 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2096 break;
ea5b6382 2097 }
e5b68a61 2098
a9083016
GM		 2099 if (IS_QLA82XX(ha))
2100 ha->port_no = !(ha->portnum & 1);
2101 else
2102 /* Get adapter physical port no from interrupt pin register. */
2103 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2104
e5b68a61
AC		 2105 if (ha->port_no & 1)
2106 ha->flags.port0 = 1;
2107 else
2108 ha->flags.port0 = 0;
7c3df132 2109 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2110 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2111 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 2112}
2113
1e99e33a
AV		 2114static void
2115qla2xxx_scan_start(struct Scsi_Host *shost)
2116{
e315cd28 2117 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2118
cbc8eb67
AV		 2119 if (vha->hw->flags.running_gold_fw)
2120 return;
2121
e315cd28
AC		 2122 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2123 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2124 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2125 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2126}
2127
2128static int
2129qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2130{
e315cd28 2131 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2132
e315cd28 2133 if (!vha->host)
1e99e33a 2134 return 1;
e315cd28 2135 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2136 return 1;
2137
e315cd28 2138 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2139}
2140
1da177e4
LT		 2141/*
2142 * PCI driver interface
2143 */
7ee61397
AV		 2144static int __devinit
2145qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2146{
a1541d5a 2147 int ret = -ENODEV;
1da177e4 2148 struct Scsi_Host *host;
e315cd28
AC		 2149 scsi_qla_host_t *base_vha = NULL;
2150 struct qla_hw_data *ha;
29856e28 2151 char pci_info[30];
7d613ac6 2152 char fw_str[30], wq_name[30];
5433383e 2153 struct scsi_host_template *sht;
642ef983 2154 int bars, mem_only = 0;
e315cd28 2155 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2156 struct req_que *req = NULL;
2157 struct rsp_que *rsp = NULL;
1da177e4 2158
285d0321 2159 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2160 sht = &qla2xxx_driver_template;
5433383e 2161 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2162 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2163 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2164 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2165 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2166 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2167 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2168 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2169 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2170 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) {
285d0321 2171 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2172 mem_only = 1;
7c3df132
SK		 2173 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2174 "Mem only adapter.\n");
285d0321 2175 }
7c3df132
SK		 2176 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2177 "Bars=%d.\n", bars);
285d0321 2178
09483916
BH		 2179 if (mem_only) {
2180 if (pci_enable_device_mem(pdev))
2181 goto probe_out;
2182 } else {
2183 if (pci_enable_device(pdev))
2184 goto probe_out;
2185 }
285d0321 2186
0927678f
JB		 2187 /* This may fail but that's ok */
2188 pci_enable_pcie_error_reporting(pdev);
285d0321 2189
e315cd28
AC		 2190 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2191 if (!ha) {
7c3df132
SK		 2192 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2193 "Unable to allocate memory for ha.\n");
e315cd28 2194 goto probe_out;
1da177e4 2195 }
7c3df132
SK		 2196 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2197 "Memory allocated for ha=%p.\n", ha);
e315cd28 2198 ha->pdev = pdev;
2d70c103 2199 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2200
2201 /* Clear our data area */
285d0321 2202 ha->bars = bars;
09483916 2203 ha->mem_only = mem_only;
df4bf0bb 2204 spin_lock_init(&ha->hardware_lock);
339aa70e 2205 spin_lock_init(&ha->vport_slock);
a9b6f722 2206 mutex_init(&ha->selflogin_lock);
1da177e4 2207
ea5b6382
AV		 2208 /* Set ISP-type information. */
2209 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2210
2211 /* Set EEH reset type to fundamental if required by hba */
6246b8a1 2212 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha))
ca79cf66 2213 pdev->needs_freset = 1;
ca79cf66 2214
cba1e47f
CD		 2215 ha->prev_topology = 0;
2216 ha->init_cb_size = sizeof(init_cb_t);
2217 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2218 ha->optrom_size = OPTROM_SIZE_2300;
2219
abbd8870 2220 /* Assign ISP specific operations. */
1da177e4 2221 if (IS_QLA2100(ha)) {
642ef983 2222 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2223 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2224 req_length = REQUEST_ENTRY_CNT_2100;
2225 rsp_length = RESPONSE_ENTRY_CNT_2100;
2226 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2227 ha->gid_list_info_size = 4;
3a03eb79
AV		 2228 ha->flash_conf_off = ~0;
2229 ha->flash_data_off = ~0;
2230 ha->nvram_conf_off = ~0;
2231 ha->nvram_data_off = ~0;
fd34f556 2232 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2233 } else if (IS_QLA2200(ha)) {
642ef983 2234 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2235 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2236 req_length = REQUEST_ENTRY_CNT_2200;
2237 rsp_length = RESPONSE_ENTRY_CNT_2100;
2238 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2239 ha->gid_list_info_size = 4;
3a03eb79
AV		 2240 ha->flash_conf_off = ~0;
2241 ha->flash_data_off = ~0;
2242 ha->nvram_conf_off = ~0;
2243 ha->nvram_data_off = ~0;
fd34f556 2244 ha->isp_ops = &qla2100_isp_ops;
fca29703 2245 } else if (IS_QLA23XX(ha)) {
642ef983 2246 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2247 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2248 req_length = REQUEST_ENTRY_CNT_2200;
2249 rsp_length = RESPONSE_ENTRY_CNT_2300;
2250 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2251 ha->gid_list_info_size = 6;
854165f4
AV		 2252 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2253 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2254 ha->flash_conf_off = ~0;
2255 ha->flash_data_off = ~0;
2256 ha->nvram_conf_off = ~0;
2257 ha->nvram_data_off = ~0;
fd34f556 2258 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2259 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2260 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2261 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2262 req_length = REQUEST_ENTRY_CNT_24XX;
2263 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2264 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2265 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2266 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2267 ha->gid_list_info_size = 8;
854165f4 2268 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2269 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2270 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2271 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2272 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2273 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2274 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2275 } else if (IS_QLA25XX(ha)) {
642ef983 2276 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2277 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2278 req_length = REQUEST_ENTRY_CNT_24XX;
2279 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2280 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2281 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2282 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2283 ha->gid_list_info_size = 8;
2284 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2285 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2286 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2287 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2288 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2289 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2290 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2291 } else if (IS_QLA81XX(ha)) {
642ef983 2292 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2293 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2294 req_length = REQUEST_ENTRY_CNT_24XX;
2295 rsp_length = RESPONSE_ENTRY_CNT_2300;
2296 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2297 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2298 ha->gid_list_info_size = 8;
2299 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2300 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2301 ha->isp_ops = &qla81xx_isp_ops;
2302 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2303 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2304 ha->nvram_conf_off = ~0;
2305 ha->nvram_data_off = ~0;
a9083016 2306 } else if (IS_QLA82XX(ha)) {
642ef983 2307 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2308 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2309 req_length = REQUEST_ENTRY_CNT_82XX;
2310 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2311 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2312 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2313 ha->gid_list_info_size = 8;
2314 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2315 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2316 ha->isp_ops = &qla82xx_isp_ops;
2317 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2318 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2319 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2320 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2321 } else if (IS_QLA83XX(ha)) {
7d613ac6 2322 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2323 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2324 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2325 req_length = REQUEST_ENTRY_CNT_24XX;
2326 rsp_length = RESPONSE_ENTRY_CNT_2300;
2327 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2328 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2329 ha->gid_list_info_size = 8;
2330 ha->optrom_size = OPTROM_SIZE_83XX;
2331 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2332 ha->isp_ops = &qla83xx_isp_ops;
2333 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2334 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2335 ha->nvram_conf_off = ~0;
2336 ha->nvram_data_off = ~0;
1da177e4 2337 }
6246b8a1 2338
7c3df132
SK		 2339 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2340 "mbx_count=%d, req_length=%d, "
2341 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2342 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2343 "max_fibre_devices=%d.\n",
7c3df132
SK		 2344 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2345 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2346 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2347 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2348 "isp_ops=%p, flash_conf_off=%d, "
2349 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2350 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2351 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2352
2353 /* Configure PCI I/O space */
2354 ret = ha->isp_ops->iospace_config(ha);
2355 if (ret)
2356 goto probe_hw_failed;
2357
2358 ql_log_pci(ql_log_info, pdev, 0x001d,
2359 "Found an ISP%04X irq %d iobase 0x%p.\n",
2360 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2361 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2362 init_completion(&ha->mbx_cmd_comp);
2363 complete(&ha->mbx_cmd_comp);
2364 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2365 init_completion(&ha->dcbx_comp);
1da177e4 2366
2c3dfe3f 2367 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2368
53303c42 2369 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2370 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2371 "64 Bit addressing is %s.\n",
2372 ha->flags.enable_64bit_addressing ? "enable" :
2373 "disable");
73208dfd 2374 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2375 if (!ret) {
7c3df132
SK		 2376 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2377 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2378
e315cd28
AC		 2379 goto probe_hw_failed;
2380 }
2381
73208dfd 2382 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2383 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2384 req->max_q_depth = ql2xmaxqdepth;
2385
e315cd28
AC		 2386
2387 base_vha = qla2x00_create_host(sht, ha);
2388 if (!base_vha) {
a1541d5a 2389 ret = -ENOMEM;
6e9f21f3 2390 qla2x00_mem_free(ha);
2afa19a9
AC		 2391 qla2x00_free_req_que(ha, req);
2392 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2393 goto probe_hw_failed;
1da177e4
LT		 2394 }
2395
e315cd28
AC		 2396 pci_set_drvdata(pdev, base_vha);
2397
e315cd28 2398 host = base_vha->host;
2afa19a9 2399 base_vha->req = req;
73208dfd
AC		 2400 host->can_queue = req->length + 128;
2401 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2402 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2403 else
e315cd28
AC		 2404 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2405 base_vha->vp_idx;
58548cb5
GM		 2406
2407 /* Set the SG table size based on ISP type */
2408 if (!IS_FWI2_CAPABLE(ha)) {
2409 if (IS_QLA2100(ha))
2410 host->sg_tablesize = 32;
2411 } else {
2412 if (!IS_QLA82XX(ha))
2413 host->sg_tablesize = QLA_SG_ALL;
2414 }
7c3df132
SK		 2415 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2416 "can_queue=%d, req=%p, "
2417 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2418 host->can_queue, base_vha->req,
2419 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2420 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2421 host->cmd_per_lun = 3;
2422 host->unique_id = host->host_no;
e02587d7 2423 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2424 host->max_cmd_len = 32;
2425 else
2426 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2427 host->max_channel = MAX_BUSES - 1;
82515920 2428 host->max_lun = ql2xmaxlun;
e315cd28 2429 host->transportt = qla2xxx_transport_template;
9a069e19 2430 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2431
7c3df132
SK		 2432 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2433 "max_id=%d this_id=%d "
2434 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2435 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2436 host->this_id, host->cmd_per_lun, host->unique_id,
2437 host->max_cmd_len, host->max_channel, host->max_lun,
2438 host->transportt, sht->vendor_id);
2439
9a347ff4
CD		 2440que_init:
2441 /* Alloc arrays of request and response ring ptrs */
2442 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2443 ql_log(ql_log_fatal, base_vha, 0x003d,
2444 "Failed to allocate memory for queue pointers..."
2445 "aborting.\n");
2446 goto probe_init_failed;
2447 }
2448
2d70c103 2449 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2450
73208dfd
AC		 2451 /* Set up the irqs */
2452 ret = qla2x00_request_irqs(ha, rsp);
2453 if (ret)
6e9f21f3 2454 goto probe_init_failed;
90a86fc0
JC		 2455
2456 pci_save_state(pdev);
2457
9a347ff4 2458 /* Assign back pointers */
2afa19a9
AC		 2459 rsp->req = req;
2460 req->rsp = rsp;
9a347ff4 2461
08029990
AV		 2462 /* FWI2-capable only. */
2463 req->req_q_in = &ha->iobase->isp24.req_q_in;
2464 req->req_q_out = &ha->iobase->isp24.req_q_out;
2465 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2466 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2467 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2468 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2469 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2470 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2471 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2472 }
2473
a9083016
GM		 2474 if (IS_QLA82XX(ha)) {
2475 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2476 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2477 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2478 }
2479
7c3df132
SK		 2480 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2481 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2482 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2483 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2484 "req->req_q_in=%p req->req_q_out=%p "
2485 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2486 req->req_q_in, req->req_q_out,
2487 rsp->rsp_q_in, rsp->rsp_q_out);
2488 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2489 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2490 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2491 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2492 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2493 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2494
7c3df132
SK		 2495 if (qla2x00_initialize_adapter(base_vha)) {
2496 ql_log(ql_log_fatal, base_vha, 0x00d6,
2497 "Failed to initialize adapter - Adapter flags %x.\n",
2498 base_vha->device_flags);
1da177e4 2499
a9083016
GM		 2500 if (IS_QLA82XX(ha)) {
2501 qla82xx_idc_lock(ha);
2502 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2503 QLA8XXX_DEV_FAILED);
a9083016 2504 qla82xx_idc_unlock(ha);
7c3df132
SK		 2505 ql_log(ql_log_fatal, base_vha, 0x00d7,
2506 "HW State: FAILED.\n");
a9083016
GM		 2507 }
2508
a1541d5a 2509 ret = -ENODEV;
1da177e4
LT		 2510 goto probe_failed;
2511 }
2512
7163ea81
AC		 2513 if (ha->mqenable) {
2514 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2515 ql_log(ql_log_warn, base_vha, 0x00ec,
2516 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2517 goto que_init;
2518 }
2519 }
68ca949c 2520
cbc8eb67
AV		 2521 if (ha->flags.running_gold_fw)
2522 goto skip_dpc;
2523
1da177e4
LT		 2524 /*
2525 * Startup the kernel thread for this host adapter
2526 */
39a11240 2527 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2528 "%s_dpc", base_vha->host_str);
39a11240 2529 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2530 ql_log(ql_log_fatal, base_vha, 0x00ed,
2531 "Failed to start DPC thread.\n");
39a11240 2532 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2533 goto probe_failed;
2534 }
7c3df132
SK		 2535 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2536 "DPC thread started successfully.\n");
1da177e4 2537
2d70c103
NB		 2538 /*
2539 * If we're not coming up in initiator mode, we might sit for
2540 * a while without waking up the dpc thread, which leads to a
2541 * stuck process warning. So just kick the dpc once here and
2542 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2543 */
2544 qla2xxx_wake_dpc(base_vha);
2545
81178772
SK		 2546 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2547 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2548 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2549 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2550
2551 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2552 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2553 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2554 INIT_WORK(&ha->idc_state_handler,
2555 qla83xx_idc_state_handler_work);
2556 INIT_WORK(&ha->nic_core_unrecoverable,
2557 qla83xx_nic_core_unrecoverable_work);
2558 }
2559
cbc8eb67 2560skip_dpc:
e315cd28
AC		 2561 list_add_tail(&base_vha->list, &ha->vp_list);
2562 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2563
2564 /* Initialized the timer */
e315cd28 2565 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2566 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2567 "Started qla2x00_timer with "
2568 "interval=%d.\n", WATCH_INTERVAL);
2569 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2570 "Detected hba at address=%p.\n",
2571 ha);
d19044c3 2572
e02587d7 2573 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2574 if (ha->fw_attributes & BIT_4) {
8cb2049c 2575 int prot = 0;
bad75002 2576 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2577 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2578 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2579 if (ql2xenabledif == 1)
2580 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2581 scsi_host_set_prot(host,
8cb2049c 2582 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2583 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2584 | SHOST_DIF_TYPE3_PROTECTION
2585 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2586 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2587 | SHOST_DIX_TYPE3_PROTECTION);
2588 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2589 } else
2590 base_vha->flags.difdix_supported = 0;
2591 }
2592
a9083016
GM		 2593 ha->isp_ops->enable_intrs(ha);
2594
a1541d5a
AV		 2595 ret = scsi_add_host(host, &pdev->dev);
2596 if (ret)
2597 goto probe_failed;
2598
1486400f
MR		 2599 base_vha->flags.init_done = 1;
2600 base_vha->flags.online = 1;
2601
7c3df132
SK		 2602 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2603 "Init done and hba is online.\n");
2604
2d70c103
NB		 2605 if (qla_ini_mode_enabled(base_vha))
2606 scsi_scan_host(host);
2607 else
2608 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2609 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2610
e315cd28 2611 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2612
e315cd28 2613 qla2x00_init_host_attr(base_vha);
a1541d5a 2614
e315cd28 2615 qla2x00_dfs_setup(base_vha);
df613b96 2616
7c3df132
SK		 2617 ql_log(ql_log_info, base_vha, 0x00fb,
2618 "QLogic %s - %s.\n",
2619 ha->model_number, ha->model_desc ? ha->model_desc : "");
2620 ql_log(ql_log_info, base_vha, 0x00fc,
2621 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2622 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2623 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2624 base_vha->host_no,
e315cd28 2625 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2626
2d70c103
NB		 2627 qlt_add_target(ha, base_vha);
2628
1da177e4
LT		 2629 return 0;
2630
6e9f21f3 2631probe_init_failed:
2afa19a9 2632 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2633 ha->req_q_map[0] = NULL;
2634 clear_bit(0, ha->req_qid_map);
2afa19a9 2635 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2636 ha->rsp_q_map[0] = NULL;
2637 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2638 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2639
1da177e4 2640probe_failed:
b9978769
AV		 2641 if (base_vha->timer_active)
2642 qla2x00_stop_timer(base_vha);
2643 base_vha->flags.online = 0;
2644 if (ha->dpc_thread) {
2645 struct task_struct *t = ha->dpc_thread;
2646
2647 ha->dpc_thread = NULL;
2648 kthread_stop(t);
2649 }
2650
e315cd28 2651 qla2x00_free_device(base_vha);
1da177e4 2652
e315cd28 2653 scsi_host_put(base_vha->host);
1da177e4 2654
e315cd28 2655probe_hw_failed:
a9083016
GM		 2656 if (IS_QLA82XX(ha)) {
2657 qla82xx_idc_lock(ha);
2658 qla82xx_clear_drv_active(ha);
2659 qla82xx_idc_unlock(ha);
2660 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2661 if (!ql2xdbwr)
2662 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2663 } else {
2664 if (ha->iobase)
2665 iounmap(ha->iobase);
2666 }
e315cd28
AC		 2667 pci_release_selected_regions(ha->pdev, ha->bars);
2668 kfree(ha);
2669 ha = NULL;
1da177e4 2670
a1541d5a 2671probe_out:
e315cd28 2672 pci_disable_device(pdev);
a1541d5a 2673 return ret;
1da177e4 2674}
1da177e4 2675
2d70c103
NB		 2676static void
2677qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2678{
2679 struct qla_hw_data *ha = vha->hw;
2680 struct task_struct *t = ha->dpc_thread;
2681
2682 if (ha->dpc_thread == NULL)
2683 return;
2684 /*
2685 * qla2xxx_wake_dpc checks for ->dpc_thread
2686 * so we need to zero it out.
2687 */
2688 ha->dpc_thread = NULL;
2689 kthread_stop(t);
2690}
2691
e30d1756
MI		 2692static void
2693qla2x00_shutdown(struct pci_dev *pdev)
2694{
2695 scsi_qla_host_t *vha;
2696 struct qla_hw_data *ha;
2697
2698 vha = pci_get_drvdata(pdev);
2699 ha = vha->hw;
2700
2701 /* Turn-off FCE trace */
2702 if (ha->flags.fce_enabled) {
2703 qla2x00_disable_fce_trace(vha, NULL, NULL);
2704 ha->flags.fce_enabled = 0;
2705 }
2706
2707 /* Turn-off EFT trace */
2708 if (ha->eft)
2709 qla2x00_disable_eft_trace(vha);
2710
2711 /* Stop currently executing firmware. */
2712 qla2x00_try_to_stop_firmware(vha);
2713
2714 /* Turn adapter off line */
2715 vha->flags.online = 0;
2716
2717 /* turn-off interrupts on the card */
2718 if (ha->interrupts_on) {
2719 vha->flags.init_done = 0;
2720 ha->isp_ops->disable_intrs(ha);
2721 }
2722
2723 qla2x00_free_irqs(vha);
2724
2725 qla2x00_free_fw_dump(ha);
2726}
2727
4c993f76 2728static void
7ee61397 2729qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2730{
feafb7b1 2731 scsi_qla_host_t *base_vha, *vha;
e315cd28 2732 struct qla_hw_data *ha;
feafb7b1 2733 unsigned long flags;
e315cd28 2734
9a347ff4
CD		 2735 /*
2736 * If the PCI device is disabled that means that probe failed and any
2737 * resources should be have cleaned up on probe exit.
2738 */
2739 if (!atomic_read(&pdev->enable_cnt))
2740 return;
2741
e315cd28
AC		 2742 base_vha = pci_get_drvdata(pdev);
2743 ha = base_vha->hw;
2744
2d70c103
NB		 2745 ha->flags.host_shutting_down = 1;
2746
43ebf16d
AE		 2747 mutex_lock(&ha->vport_lock);
2748 while (ha->cur_vport_count) {
2749 struct Scsi_Host *scsi_host;
feafb7b1 2750
43ebf16d 2751 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2752
43ebf16d
AE		 2753 BUG_ON(base_vha->list.next == &ha->vp_list);
2754 /* This assumes first entry in ha->vp_list is always base vha */
2755 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2756 scsi_host = scsi_host_get(vha->host);
feafb7b1 2757
43ebf16d
AE		 2758 spin_unlock_irqrestore(&ha->vport_slock, flags);
2759 mutex_unlock(&ha->vport_lock);
2760
2761 fc_vport_terminate(vha->fc_vport);
2762 scsi_host_put(vha->host);
feafb7b1 2763
43ebf16d 2764 mutex_lock(&ha->vport_lock);
e315cd28 2765 }
43ebf16d 2766 mutex_unlock(&ha->vport_lock);
1da177e4 2767
7d613ac6
SV		 2768 if (IS_QLA8031(ha)) {
2769 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
2770 "Clearing fcoe driver presence.\n");
2771 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
2772 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
2773 "Error while clearing DRV-Presence.\n");
2774 }
2775
e315cd28 2776 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2777
b9978769
AV		 2778 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2779
e315cd28 2780 qla2x00_dfs_remove(base_vha);
c795c1e4 2781
e315cd28 2782 qla84xx_put_chip(base_vha);
c795c1e4 2783
b9978769
AV		 2784 /* Disable timer */
2785 if (base_vha->timer_active)
2786 qla2x00_stop_timer(base_vha);
2787
2788 base_vha->flags.online = 0;
2789
68ca949c
AC		 2790 /* Flush the work queue and remove it */
2791 if (ha->wq) {
2792 flush_workqueue(ha->wq);
2793 destroy_workqueue(ha->wq);
2794 ha->wq = NULL;
2795 }
2796
7d613ac6
SV		 2797 /* Cancel all work and destroy DPC workqueues */
2798 if (ha->dpc_lp_wq) {
2799 cancel_work_sync(&ha->idc_aen);
2800 destroy_workqueue(ha->dpc_lp_wq);
2801 ha->dpc_lp_wq = NULL;
2802 }
2803
2804 if (ha->dpc_hp_wq) {
2805 cancel_work_sync(&ha->nic_core_reset);
2806 cancel_work_sync(&ha->idc_state_handler);
2807 cancel_work_sync(&ha->nic_core_unrecoverable);
2808 destroy_workqueue(ha->dpc_hp_wq);
2809 ha->dpc_hp_wq = NULL;
2810 }
2811
b9978769
AV		 2812 /* Kill the kernel thread for this host */
2813 if (ha->dpc_thread) {
2814 struct task_struct *t = ha->dpc_thread;
2815
2816 /*
2817 * qla2xxx_wake_dpc checks for ->dpc_thread
2818 * so we need to zero it out.
2819 */
2820 ha->dpc_thread = NULL;
2821 kthread_stop(t);
2822 }
2d70c103 2823 qlt_remove_target(ha, base_vha);
b9978769 2824
e315cd28 2825 qla2x00_free_sysfs_attr(base_vha);
df613b96 2826
e315cd28 2827 fc_remove_host(base_vha->host);
4d4df193 2828
e315cd28 2829 scsi_remove_host(base_vha->host);
1da177e4 2830
e315cd28 2831 qla2x00_free_device(base_vha);
bdf79621 2832
e315cd28 2833 scsi_host_put(base_vha->host);
1da177e4 2834
a9083016 2835 if (IS_QLA82XX(ha)) {
b963752f
GM		 2836 qla82xx_idc_lock(ha);
2837 qla82xx_clear_drv_active(ha);
2838 qla82xx_idc_unlock(ha);
2839
a9083016
GM		 2840 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2841 if (!ql2xdbwr)
2842 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2843 } else {
2844 if (ha->iobase)
2845 iounmap(ha->iobase);
1da177e4 2846
a9083016
GM		 2847 if (ha->mqiobase)
2848 iounmap(ha->mqiobase);
6246b8a1
GM		 2849
2850 if (IS_QLA83XX(ha) && ha->msixbase)
2851 iounmap(ha->msixbase);
a9083016 2852 }
73208dfd 2853
e315cd28
AC		 2854 pci_release_selected_regions(ha->pdev, ha->bars);
2855 kfree(ha);
2856 ha = NULL;
1da177e4 2857
90a86fc0
JC		 2858 pci_disable_pcie_error_reporting(pdev);
2859
665db93b 2860 pci_disable_device(pdev);
1da177e4
LT		 2861 pci_set_drvdata(pdev, NULL);
2862}
1da177e4
LT		 2863
2864static void
e315cd28 2865qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2866{
e315cd28 2867 struct qla_hw_data *ha = vha->hw;
1da177e4 2868
85880801
AV		 2869 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2870
2871 /* Disable timer */
2872 if (vha->timer_active)
2873 qla2x00_stop_timer(vha);
2874
2d70c103 2875 qla2x00_stop_dpc_thread(vha);
85880801 2876
2afa19a9 2877 qla25xx_delete_queues(vha);
df613b96 2878 if (ha->flags.fce_enabled)
e315cd28 2879 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2880
a7a167bf 2881 if (ha->eft)
e315cd28 2882 qla2x00_disable_eft_trace(vha);
a7a167bf 2883
f6ef3b18 2884 /* Stop currently executing firmware. */
e315cd28 2885 qla2x00_try_to_stop_firmware(vha);
1da177e4 2886
85880801
AV		 2887 vha->flags.online = 0;
2888
f6ef3b18 2889 /* turn-off interrupts on the card */
a9083016
GM		 2890 if (ha->interrupts_on) {
2891 vha->flags.init_done = 0;
fd34f556 2892 ha->isp_ops->disable_intrs(ha);
a9083016 2893 }
f6ef3b18 2894
e315cd28 2895 qla2x00_free_irqs(vha);
1da177e4 2896
8867048b
CD		 2897 qla2x00_free_fcports(vha);
2898
e315cd28 2899 qla2x00_mem_free(ha);
73208dfd 2900
08de2844
GM		 2901 qla82xx_md_free(vha);
2902
73208dfd 2903 qla2x00_free_queues(ha);
1da177e4
LT		 2904}
2905
8867048b
CD		 2906void qla2x00_free_fcports(struct scsi_qla_host *vha)
2907{
2908 fc_port_t *fcport, *tfcport;
2909
2910 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2911 list_del(&fcport->list);
5f16b331 2912 qla2x00_clear_loop_id(fcport);
8867048b
CD		 2913 kfree(fcport);
2914 fcport = NULL;
2915 }
2916}
2917
d97994dc 2918static inline void
e315cd28 2919qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 2920 int defer)
2921{
d97994dc 2922 struct fc_rport *rport;
67becc00 2923 scsi_qla_host_t *base_vha;
044d78e1 2924 unsigned long flags;
d97994dc
AV		 2925
2926 if (!fcport->rport)
2927 return;
2928
2929 rport = fcport->rport;
2930 if (defer) {
67becc00 2931 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2932 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2933 fcport->drport = rport;
044d78e1 2934 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2935 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2936 qla2xxx_wake_dpc(base_vha);
2d70c103 2937 } else {
d97994dc 2938 fc_remote_port_delete(rport);
2d70c103
NB		 2939 qlt_fc_port_deleted(vha, fcport);
2940 }
d97994dc
AV		 2941}
2942
1da177e4
LT		 2943/*
2944 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2945 *
2946 * Input: ha = adapter block pointer. fcport = port structure pointer.
2947 *
2948 * Return: None.
2949 *
2950 * Context:
2951 */
e315cd28 2952void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2953 int do_login, int defer)
1da177e4 2954{
2c3dfe3f 2955 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 2956 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 2957 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2958 qla2x00_schedule_rport_del(vha, fcport, defer);
2959 }
fa2a1ce5 2960 /*
1da177e4
LT		 2961 * We may need to retry the login, so don't change the state of the
2962 * port but do the retries.
2963 */
2964 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2965 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2966
2967 if (!do_login)
2968 return;
2969
2970 if (fcport->login_retry == 0) {
e315cd28
AC		 2971 fcport->login_retry = vha->hw->login_retry_count;
2972 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2973
7c3df132
SK		 2974 ql_dbg(ql_dbg_disc, vha, 0x2067,
2975 "Port login retry "
1da177e4 2976 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2977 "id = 0x%04x retry cnt=%d.\n",
2978 fcport->port_name[0], fcport->port_name[1],
2979 fcport->port_name[2], fcport->port_name[3],
2980 fcport->port_name[4], fcport->port_name[5],
2981 fcport->port_name[6], fcport->port_name[7],
2982 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2983 }
2984}
2985
2986/*
2987 * qla2x00_mark_all_devices_lost
2988 * Updates fcport state when device goes offline.
2989 *
2990 * Input:
2991 * ha = adapter block pointer.
2992 * fcport = port structure pointer.
2993 *
2994 * Return:
2995 * None.
2996 *
2997 * Context:
2998 */
2999void
e315cd28 3000qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3001{
3002 fc_port_t *fcport;
3003
e315cd28 3004 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3005 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3006 continue;
0d6e61bc 3007
1da177e4
LT		 3008 /*
3009 * No point in marking the device as lost, if the device is
3010 * already DEAD.
3011 */
3012 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3013 continue;
e315cd28 3014 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3015 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3016 if (defer)
3017 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3018 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3019 qla2x00_schedule_rport_del(vha, fcport, defer);
3020 }
1da177e4
LT		 3021 }
3022}
3023
3024/*
3025* qla2x00_mem_alloc
3026* Allocates adapter memory.
3027*
3028* Returns:
3029* 0 = success.
e8711085 3030* !0 = failure.
1da177e4 3031*/
e8711085 3032static int
73208dfd
AC		 3033qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3034 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3035{
3036 char name[16];
1da177e4 3037
e8711085 3038 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3039 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3040 if (!ha->init_cb)
e315cd28 3041 goto fail;
e8711085 3042
2d70c103
NB		 3043 if (qlt_mem_alloc(ha) < 0)
3044 goto fail_free_init_cb;
3045
642ef983
CD		 3046 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3047 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3048 if (!ha->gid_list)
2d70c103 3049 goto fail_free_tgt_mem;
1da177e4 3050
e8711085
AV		 3051 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3052 if (!ha->srb_mempool)
e315cd28 3053 goto fail_free_gid_list;
e8711085 3054
a9083016
GM		 3055 if (IS_QLA82XX(ha)) {
3056 /* Allocate cache for CT6 Ctx. */
3057 if (!ctx_cachep) {
3058 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3059 sizeof(struct ct6_dsd), 0,
3060 SLAB_HWCACHE_ALIGN, NULL);
3061 if (!ctx_cachep)
3062 goto fail_free_gid_list;
3063 }
3064 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3065 ctx_cachep);
3066 if (!ha->ctx_mempool)
3067 goto fail_free_srb_mempool;
7c3df132
SK		 3068 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3069 "ctx_cachep=%p ctx_mempool=%p.\n",
3070 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3071 }
3072
e8711085
AV		 3073 /* Get memory for cached NVRAM */
3074 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3075 if (!ha->nvram)
a9083016 3076 goto fail_free_ctx_mempool;
e8711085 3077
e315cd28
AC		 3078 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3079 ha->pdev->device);
3080 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3081 DMA_POOL_SIZE, 8, 0);
3082 if (!ha->s_dma_pool)
3083 goto fail_free_nvram;
3084
7c3df132
SK		 3085 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3086 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3087 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3088
bad75002 3089 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3090 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3091 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3092 if (!ha->dl_dma_pool) {
7c3df132
SK		 3093 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3094 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3095 goto fail_s_dma_pool;
3096 }
3097
3098 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3099 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3100 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3101 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3102 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3103 goto fail_dl_dma_pool;
3104 }
7c3df132
SK		 3105 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3106 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3107 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3108 }
3109
e8711085
AV		 3110 /* Allocate memory for SNS commands */
3111 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3112 /* Get consistent memory allocated for SNS commands */
e8711085 3113 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3114 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3115 if (!ha->sns_cmd)
e315cd28 3116 goto fail_dma_pool;
7c3df132 3117 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3118 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3119 } else {
e315cd28 3120 /* Get consistent memory allocated for MS IOCB */
e8711085 3121 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3122 &ha->ms_iocb_dma);
e8711085 3123 if (!ha->ms_iocb)
e315cd28
AC		 3124 goto fail_dma_pool;
3125 /* Get consistent memory allocated for CT SNS commands */
e8711085 3126 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3127 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3128 if (!ha->ct_sns)
3129 goto fail_free_ms_iocb;
7c3df132
SK		 3130 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3131 "ms_iocb=%p ct_sns=%p.\n",
3132 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3133 }
3134
e315cd28 3135 /* Allocate memory for request ring */
73208dfd
AC		 3136 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3137 if (!*req) {
7c3df132
SK		 3138 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3139 "Failed to allocate memory for req.\n");
e315cd28
AC		 3140 goto fail_req;
3141 }
73208dfd
AC		 3142 (*req)->length = req_len;
3143 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3144 ((*req)->length + 1) * sizeof(request_t),
3145 &(*req)->dma, GFP_KERNEL);
3146 if (!(*req)->ring) {
7c3df132
SK		 3147 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3148 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3149 goto fail_req_ring;
3150 }
3151 /* Allocate memory for response ring */
73208dfd
AC		 3152 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3153 if (!*rsp) {
7c3df132
SK		 3154 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3155 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3156 goto fail_rsp;
3157 }
73208dfd
AC		 3158 (*rsp)->hw = ha;
3159 (*rsp)->length = rsp_len;
3160 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3161 ((*rsp)->length + 1) * sizeof(response_t),
3162 &(*rsp)->dma, GFP_KERNEL);
3163 if (!(*rsp)->ring) {
7c3df132
SK		 3164 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3165 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3166 goto fail_rsp_ring;
3167 }
73208dfd
AC		 3168 (*req)->rsp = *rsp;
3169 (*rsp)->req = *req;
7c3df132
SK		 3170 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3171 "req=%p req->length=%d req->ring=%p rsp=%p "
3172 "rsp->length=%d rsp->ring=%p.\n",
3173 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3174 (*rsp)->ring);
73208dfd
AC		 3175 /* Allocate memory for NVRAM data for vports */
3176 if (ha->nvram_npiv_size) {
3177 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3178 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3179 if (!ha->npiv_info) {
7c3df132
SK		 3180 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3181 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3182 goto fail_npiv_info;
3183 }
3184 } else
3185 ha->npiv_info = NULL;
e8711085 3186
b64b0e8f 3187 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3188 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3189 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3190 &ha->ex_init_cb_dma);
3191 if (!ha->ex_init_cb)
3192 goto fail_ex_init_cb;
7c3df132
SK		 3193 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3194 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3195 }
3196
a9083016
GM		 3197 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3198
5ff1d584
AV		 3199 /* Get consistent memory allocated for Async Port-Database. */
3200 if (!IS_FWI2_CAPABLE(ha)) {
3201 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3202 &ha->async_pd_dma);
3203 if (!ha->async_pd)
3204 goto fail_async_pd;
7c3df132
SK		 3205 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3206 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3207 }
3208
e315cd28 3209 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3210
3211 /* Allocate memory for our loop_id bitmap */
3212 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3213 GFP_KERNEL);
3214 if (!ha->loop_id_map)
3215 goto fail_async_pd;
3216 else {
3217 qla2x00_set_reserved_loop_ids(ha);
3218 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3219 "loop_id_map=%p. \n", ha->loop_id_map);
3220 }
3221
e315cd28
AC		 3222 return 1;
3223
5ff1d584
AV		 3224fail_async_pd:
3225 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3226fail_ex_init_cb:
3227 kfree(ha->npiv_info);
73208dfd
AC		 3228fail_npiv_info:
3229 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3230 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3231 (*rsp)->ring = NULL;
3232 (*rsp)->dma = 0;
e315cd28 3233fail_rsp_ring:
73208dfd 3234 kfree(*rsp);
e315cd28 3235fail_rsp:
73208dfd
AC		 3236 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3237 sizeof(request_t), (*req)->ring, (*req)->dma);
3238 (*req)->ring = NULL;
3239 (*req)->dma = 0;
e315cd28 3240fail_req_ring:
73208dfd 3241 kfree(*req);
e315cd28
AC		 3242fail_req:
3243 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3244 ha->ct_sns, ha->ct_sns_dma);
3245 ha->ct_sns = NULL;
3246 ha->ct_sns_dma = 0;
e8711085
AV		 3247fail_free_ms_iocb:
3248 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3249 ha->ms_iocb = NULL;
3250 ha->ms_iocb_dma = 0;
e315cd28 3251fail_dma_pool:
bad75002 3252 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3253 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3254 ha->fcp_cmnd_dma_pool = NULL;
3255 }
3256fail_dl_dma_pool:
bad75002 3257 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3258 dma_pool_destroy(ha->dl_dma_pool);
3259 ha->dl_dma_pool = NULL;
3260 }
3261fail_s_dma_pool:
e315cd28
AC		 3262 dma_pool_destroy(ha->s_dma_pool);
3263 ha->s_dma_pool = NULL;
e8711085
AV		 3264fail_free_nvram:
3265 kfree(ha->nvram);
3266 ha->nvram = NULL;
a9083016
GM		 3267fail_free_ctx_mempool:
3268 mempool_destroy(ha->ctx_mempool);
3269 ha->ctx_mempool = NULL;
e8711085
AV		 3270fail_free_srb_mempool:
3271 mempool_destroy(ha->srb_mempool);
3272 ha->srb_mempool = NULL;
e8711085 3273fail_free_gid_list:
642ef983
CD		 3274 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3275 ha->gid_list,
e315cd28 3276 ha->gid_list_dma);
e8711085
AV		 3277 ha->gid_list = NULL;
3278 ha->gid_list_dma = 0;
2d70c103
NB		 3279fail_free_tgt_mem:
3280 qlt_mem_free(ha);
e315cd28
AC		 3281fail_free_init_cb:
3282 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3283 ha->init_cb_dma);
3284 ha->init_cb = NULL;
3285 ha->init_cb_dma = 0;
e8711085 3286fail:
7c3df132
SK		 3287 ql_log(ql_log_fatal, NULL, 0x0030,
3288 "Memory allocation failure.\n");
e8711085 3289 return -ENOMEM;
1da177e4
LT		 3290}
3291
3292/*
e30d1756
MI		 3293* qla2x00_free_fw_dump
3294* Frees fw dump stuff.
1da177e4
LT		 3295*
3296* Input:
e30d1756 3297* ha = adapter block pointer.
1da177e4 3298*/
a824ebb3 3299static void
e30d1756 3300qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3301{
df613b96
AV		 3302 if (ha->fce)
3303 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3304 ha->fce_dma);
df613b96 3305
a7a167bf
AV		 3306 if (ha->fw_dump) {
3307 if (ha->eft)
3308 dma_free_coherent(&ha->pdev->dev,
e30d1756 3309 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3310 vfree(ha->fw_dump);
3311 }
e30d1756
MI		 3312 ha->fce = NULL;
3313 ha->fce_dma = 0;
3314 ha->eft = NULL;
3315 ha->eft_dma = 0;
3316 ha->fw_dump = NULL;
3317 ha->fw_dumped = 0;
3318 ha->fw_dump_reading = 0;
3319}
3320
3321/*
3322* qla2x00_mem_free
3323* Frees all adapter allocated memory.
3324*
3325* Input:
3326* ha = adapter block pointer.
3327*/
3328static void
3329qla2x00_mem_free(struct qla_hw_data *ha)
3330{
3331 qla2x00_free_fw_dump(ha);
3332
81178772
SK		 3333 if (ha->mctp_dump)
3334 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3335 ha->mctp_dump_dma);
3336
e30d1756
MI		 3337 if (ha->srb_mempool)
3338 mempool_destroy(ha->srb_mempool);
a7a167bf 3339
11bbc1d8
AV		 3340 if (ha->dcbx_tlv)
3341 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3342 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3343
ce0423f4
AV		 3344 if (ha->xgmac_data)
3345 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3346 ha->xgmac_data, ha->xgmac_data_dma);
3347
1da177e4
LT		 3348 if (ha->sns_cmd)
3349 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3350 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3351
3352 if (ha->ct_sns)
3353 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3354 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3355
88729e53
AV		 3356 if (ha->sfp_data)
3357 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3358
1da177e4
LT		 3359 if (ha->ms_iocb)
3360 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3361
b64b0e8f 3362 if (ha->ex_init_cb)
a9083016
GM		 3363 dma_pool_free(ha->s_dma_pool,
3364 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3365
5ff1d584
AV		 3366 if (ha->async_pd)
3367 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3368
1da177e4
LT		 3369 if (ha->s_dma_pool)
3370 dma_pool_destroy(ha->s_dma_pool);
3371
1da177e4 3372 if (ha->gid_list)
642ef983
CD		 3373 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3374 ha->gid_list, ha->gid_list_dma);
1da177e4 3375
a9083016
GM		 3376 if (IS_QLA82XX(ha)) {
3377 if (!list_empty(&ha->gbl_dsd_list)) {
3378 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3379
3380 /* clean up allocated prev pool */
3381 list_for_each_entry_safe(dsd_ptr,
3382 tdsd_ptr, &ha->gbl_dsd_list, list) {
3383 dma_pool_free(ha->dl_dma_pool,
3384 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3385 list_del(&dsd_ptr->list);
3386 kfree(dsd_ptr);
3387 }
3388 }
3389 }
3390
3391 if (ha->dl_dma_pool)
3392 dma_pool_destroy(ha->dl_dma_pool);
3393
3394 if (ha->fcp_cmnd_dma_pool)
3395 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3396
3397 if (ha->ctx_mempool)
3398 mempool_destroy(ha->ctx_mempool);
3399
2d70c103
NB		 3400 qlt_mem_free(ha);
3401
e315cd28
AC		 3402 if (ha->init_cb)
3403 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3404 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3405 vfree(ha->optrom_buffer);
3406 kfree(ha->nvram);
73208dfd 3407 kfree(ha->npiv_info);
7a67735b 3408 kfree(ha->swl);
5f16b331 3409 kfree(ha->loop_id_map);
1da177e4 3410
e8711085 3411 ha->srb_mempool = NULL;
a9083016 3412 ha->ctx_mempool = NULL;
1da177e4
LT		 3413 ha->sns_cmd = NULL;
3414 ha->sns_cmd_dma = 0;
3415 ha->ct_sns = NULL;
3416 ha->ct_sns_dma = 0;
3417 ha->ms_iocb = NULL;
3418 ha->ms_iocb_dma = 0;
1da177e4
LT		 3419 ha->init_cb = NULL;
3420 ha->init_cb_dma = 0;
b64b0e8f
AV		 3421 ha->ex_init_cb = NULL;
3422 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3423 ha->async_pd = NULL;
3424 ha->async_pd_dma = 0;
1da177e4
LT		 3425
3426 ha->s_dma_pool = NULL;
a9083016
GM		 3427 ha->dl_dma_pool = NULL;
3428 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3429
1da177e4
LT		 3430 ha->gid_list = NULL;
3431 ha->gid_list_dma = 0;
2d70c103
NB		 3432
3433 ha->tgt.atio_ring = NULL;
3434 ha->tgt.atio_dma = 0;
3435 ha->tgt.tgt_vp_map = NULL;
e315cd28 3436}
1da177e4 3437
e315cd28
AC		 3438struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3439 struct qla_hw_data *ha)
3440{
3441 struct Scsi_Host *host;
3442 struct scsi_qla_host *vha = NULL;
854165f4 3443
e315cd28
AC		 3444 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3445 if (host == NULL) {
7c3df132
SK		 3446 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3447 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3448 goto fail;
3449 }
3450
3451 /* Clear our data area */
3452 vha = shost_priv(host);
3453 memset(vha, 0, sizeof(scsi_qla_host_t));
3454
3455 vha->host = host;
3456 vha->host_no = host->host_no;
3457 vha->hw = ha;
3458
3459 INIT_LIST_HEAD(&vha->vp_fcports);
3460 INIT_LIST_HEAD(&vha->work_list);
3461 INIT_LIST_HEAD(&vha->list);
3462
f999f4c1
AV		 3463 spin_lock_init(&vha->work_lock);
3464
e315cd28 3465 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3466 ql_dbg(ql_dbg_init, vha, 0x0041,
3467 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3468 vha->host, vha->hw, vha,
3469 dev_name(&(ha->pdev->dev)));
3470
e315cd28
AC		 3471 return vha;
3472
3473fail:
3474 return vha;
1da177e4
LT		 3475}
3476
01ef66bb 3477static struct qla_work_evt *
f999f4c1 3478qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3479{
3480 struct qla_work_evt *e;
feafb7b1
AE		 3481 uint8_t bail;
3482
3483 QLA_VHA_MARK_BUSY(vha, bail);
3484 if (bail)
3485 return NULL;
0971de7f 3486
f999f4c1 3487 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3488 if (!e) {
3489 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3490 return NULL;
feafb7b1 3491 }
0971de7f
AV		 3492
3493 INIT_LIST_HEAD(&e->list);
3494 e->type = type;
3495 e->flags = QLA_EVT_FLAG_FREE;
3496 return e;
3497}
3498
01ef66bb 3499static int
f999f4c1 3500qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3501{
f999f4c1 3502 unsigned long flags;
0971de7f 3503
f999f4c1 3504 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3505 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3506 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3507 qla2xxx_wake_dpc(vha);
f999f4c1 3508
0971de7f
AV		 3509 return QLA_SUCCESS;
3510}
3511
3512int
e315cd28 3513qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3514 u32 data)
3515{
3516 struct qla_work_evt *e;
3517
f999f4c1 3518 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3519 if (!e)
3520 return QLA_FUNCTION_FAILED;
3521
3522 e->u.aen.code = code;
3523 e->u.aen.data = data;
f999f4c1 3524 return qla2x00_post_work(vha, e);
0971de7f
AV		 3525}
3526
8a659571
AV		 3527int
3528qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3529{
3530 struct qla_work_evt *e;
3531
f999f4c1 3532 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3533 if (!e)
3534 return QLA_FUNCTION_FAILED;
3535
3536 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3537 return qla2x00_post_work(vha, e);
8a659571
AV		 3538}
3539
ac280b67
AV		 3540#define qla2x00_post_async_work(name, type) \
3541int qla2x00_post_async_##name##_work( \
3542 struct scsi_qla_host *vha, \
3543 fc_port_t *fcport, uint16_t *data) \
3544{ \
3545 struct qla_work_evt *e; \
3546 \
3547 e = qla2x00_alloc_work(vha, type); \
3548 if (!e) \
3549 return QLA_FUNCTION_FAILED; \
3550 \
3551 e->u.logio.fcport = fcport; \
3552 if (data) { \
3553 e->u.logio.data[0] = data[0]; \
3554 e->u.logio.data[1] = data[1]; \
3555 } \
3556 return qla2x00_post_work(vha, e); \
3557}
3558
3559qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3560qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3561qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3562qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3563qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3564qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3565
3420d36c
AV		 3566int
3567qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3568{
3569 struct qla_work_evt *e;
3570
3571 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3572 if (!e)
3573 return QLA_FUNCTION_FAILED;
3574
3575 e->u.uevent.code = code;
3576 return qla2x00_post_work(vha, e);
3577}
3578
3579static void
3580qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3581{
3582 char event_string[40];
3583 char *envp[] = { event_string, NULL };
3584
3585 switch (code) {
3586 case QLA_UEVENT_CODE_FW_DUMP:
3587 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3588 vha->host_no);
3589 break;
3590 default:
3591 /* do nothing */
3592 break;
3593 }
3594 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3595}
3596
ac280b67 3597void
e315cd28 3598qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3599{
f999f4c1
AV		 3600 struct qla_work_evt *e, *tmp;
3601 unsigned long flags;
3602 LIST_HEAD(work);
0971de7f 3603
f999f4c1
AV		 3604 spin_lock_irqsave(&vha->work_lock, flags);
3605 list_splice_init(&vha->work_list, &work);
3606 spin_unlock_irqrestore(&vha->work_lock, flags);
3607
3608 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3609 list_del_init(&e->list);
0971de7f
AV		 3610
3611 switch (e->type) {
3612 case QLA_EVT_AEN:
e315cd28 3613 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3614 e->u.aen.code, e->u.aen.data);
3615 break;
8a659571
AV		 3616 case QLA_EVT_IDC_ACK:
3617 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3618 break;
ac280b67
AV		 3619 case QLA_EVT_ASYNC_LOGIN:
3620 qla2x00_async_login(vha, e->u.logio.fcport,
3621 e->u.logio.data);
3622 break;
3623 case QLA_EVT_ASYNC_LOGIN_DONE:
3624 qla2x00_async_login_done(vha, e->u.logio.fcport,
3625 e->u.logio.data);
3626 break;
3627 case QLA_EVT_ASYNC_LOGOUT:
3628 qla2x00_async_logout(vha, e->u.logio.fcport);
3629 break;
3630 case QLA_EVT_ASYNC_LOGOUT_DONE:
3631 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3632 e->u.logio.data);
3633 break;
5ff1d584
AV		 3634 case QLA_EVT_ASYNC_ADISC:
3635 qla2x00_async_adisc(vha, e->u.logio.fcport,
3636 e->u.logio.data);
3637 break;
3638 case QLA_EVT_ASYNC_ADISC_DONE:
3639 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3640 e->u.logio.data);
3641 break;
3420d36c
AV		 3642 case QLA_EVT_UEVENT:
3643 qla2x00_uevent_emit(vha, e->u.uevent.code);
3644 break;
0971de7f
AV		 3645 }
3646 if (e->flags & QLA_EVT_FLAG_FREE)
3647 kfree(e);
feafb7b1
AE		 3648
3649 /* For each work completed decrement vha ref count */
3650 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3651 }
e315cd28 3652}
f999f4c1 3653
e315cd28
AC		 3654/* Relogins all the fcports of a vport
3655 * Context: dpc thread
3656 */
3657void qla2x00_relogin(struct scsi_qla_host *vha)
3658{
3659 fc_port_t *fcport;
c6b2fca8 3660 int status;
e315cd28
AC		 3661 uint16_t next_loopid = 0;
3662 struct qla_hw_data *ha = vha->hw;
ac280b67 3663 uint16_t data[2];
e315cd28
AC		 3664
3665 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3666 /*
3667 * If the port is not ONLINE then try to login
3668 * to it if we haven't run out of retries.
3669 */
5ff1d584
AV		 3670 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3671 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3672 fcport->login_retry--;
e315cd28 3673 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3674 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3675 ha->isp_ops->fabric_logout(vha,
3676 fcport->loop_id,
3677 fcport->d_id.b.domain,
3678 fcport->d_id.b.area,
3679 fcport->d_id.b.al_pa);
3680
03bcfb57
JC		 3681 if (fcport->loop_id == FC_NO_LOOP_ID) {
3682 fcport->loop_id = next_loopid =
3683 ha->min_external_loopid;
3684 status = qla2x00_find_new_loop_id(
3685 vha, fcport);
3686 if (status != QLA_SUCCESS) {
3687 /* Ran out of IDs to use */
3688 break;
3689 }
3690 }
3691
ac280b67 3692 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3693 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3694 data[0] = 0;
3695 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3696 status = qla2x00_post_async_login_work(
3697 vha, fcport, data);
3698 if (status == QLA_SUCCESS)
3699 continue;
3700 /* Attempt a retry. */
3701 status = 1;
aaf4d3e2 3702 } else {
ac280b67
AV		 3703 status = qla2x00_fabric_login(vha,
3704 fcport, &next_loopid);
aaf4d3e2
SK		 3705 if (status == QLA_SUCCESS) {
3706 int status2;
3707 uint8_t opts;
3708
3709 opts = 0;
3710 if (fcport->flags &
3711 FCF_FCP2_DEVICE)
3712 opts |= BIT_1;
3713 status2 =
3714 qla2x00_get_port_database(
3715 vha, fcport,
3716 opts);
3717 if (status2 != QLA_SUCCESS)
3718 status = 1;
3719 }
3720 }
e315cd28
AC		 3721 } else
3722 status = qla2x00_local_device_login(vha,
3723 fcport);
3724
e315cd28
AC		 3725 if (status == QLA_SUCCESS) {
3726 fcport->old_loop_id = fcport->loop_id;
3727
7c3df132
SK		 3728 ql_dbg(ql_dbg_disc, vha, 0x2003,
3729 "Port login OK: logged in ID 0x%x.\n",
3730 fcport->loop_id);
e315cd28
AC		 3731
3732 qla2x00_update_fcport(vha, fcport);
3733
3734 } else if (status == 1) {
3735 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3736 /* retry the login again */
7c3df132
SK		 3737 ql_dbg(ql_dbg_disc, vha, 0x2007,
3738 "Retrying %d login again loop_id 0x%x.\n",
3739 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3740 } else {
3741 fcport->login_retry = 0;
3742 }
3743
3744 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 3745 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 3746 }
3747 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3748 break;
0971de7f 3749 }
0971de7f
AV		 3750}
3751
7d613ac6
SV		 3752/* Schedule work on any of the dpc-workqueues */
3753void
3754qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
3755{
3756 struct qla_hw_data *ha = base_vha->hw;
3757
3758 switch (work_code) {
3759 case MBA_IDC_AEN: /* 0x8200 */
3760 if (ha->dpc_lp_wq)
3761 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
3762 break;
3763
3764 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
3765 if (!ha->flags.nic_core_reset_hdlr_active) {
3766 if (ha->dpc_hp_wq)
3767 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
3768 } else
3769 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
3770 "NIC Core reset is already active. Skip "
3771 "scheduling it again.\n");
3772 break;
3773 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
3774 if (ha->dpc_hp_wq)
3775 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
3776 break;
3777 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
3778 if (ha->dpc_hp_wq)
3779 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
3780 break;
3781 default:
3782 ql_log(ql_log_warn, base_vha, 0xb05f,
3783 "Unknow work-code=0x%x.\n", work_code);
3784 }
3785
3786 return;
3787}
3788
3789/* Work: Perform NIC Core Unrecoverable state handling */
3790void
3791qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
3792{
3793 struct qla_hw_data *ha =
3794 container_of(work, struct qla_hw_data, nic_core_reset);
3795 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3796 uint32_t dev_state = 0;
3797
3798 qla83xx_idc_lock(base_vha, 0);
3799 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3800 qla83xx_reset_ownership(base_vha);
3801 if (ha->flags.nic_core_reset_owner) {
3802 ha->flags.nic_core_reset_owner = 0;
3803 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
3804 QLA8XXX_DEV_FAILED);
3805 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
3806 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
3807 }
3808 qla83xx_idc_unlock(base_vha, 0);
3809}
3810
3811/* Work: Execute IDC state handler */
3812void
3813qla83xx_idc_state_handler_work(struct work_struct *work)
3814{
3815 struct qla_hw_data *ha =
3816 container_of(work, struct qla_hw_data, nic_core_reset);
3817 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3818 uint32_t dev_state = 0;
3819
3820 qla83xx_idc_lock(base_vha, 0);
3821 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3822 if (dev_state == QLA8XXX_DEV_FAILED ||
3823 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
3824 qla83xx_idc_state_handler(base_vha);
3825 qla83xx_idc_unlock(base_vha, 0);
3826}
3827
3828int
3829qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
3830{
3831 int rval = QLA_SUCCESS;
3832 unsigned long heart_beat_wait = jiffies + (1 * HZ);
3833 uint32_t heart_beat_counter1, heart_beat_counter2;
3834
3835 do {
3836 if (time_after(jiffies, heart_beat_wait)) {
3837 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
3838 "Nic Core f/w is not alive.\n");
3839 rval = QLA_FUNCTION_FAILED;
3840 break;
3841 }
3842
3843 qla83xx_idc_lock(base_vha, 0);
3844 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
3845 &heart_beat_counter1);
3846 qla83xx_idc_unlock(base_vha, 0);
3847 msleep(100);
3848 qla83xx_idc_lock(base_vha, 0);
3849 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
3850 &heart_beat_counter2);
3851 qla83xx_idc_unlock(base_vha, 0);
3852 } while (heart_beat_counter1 == heart_beat_counter2);
3853
3854 return rval;
3855}
3856
3857/* Work: Perform NIC Core Reset handling */
3858void
3859qla83xx_nic_core_reset_work(struct work_struct *work)
3860{
3861 struct qla_hw_data *ha =
3862 container_of(work, struct qla_hw_data, nic_core_reset);
3863 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3864 uint32_t dev_state = 0;
3865
81178772
SK		 3866 if (IS_QLA2031(ha)) {
3867 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
3868 ql_log(ql_log_warn, base_vha, 0xb081,
3869 "Failed to dump mctp\n");
3870 return;
3871 }
3872
7d613ac6
SV		 3873 if (!ha->flags.nic_core_reset_hdlr_active) {
3874 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
3875 qla83xx_idc_lock(base_vha, 0);
3876 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
3877 &dev_state);
3878 qla83xx_idc_unlock(base_vha, 0);
3879 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
3880 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
3881 "Nic Core f/w is alive.\n");
3882 return;
3883 }
3884 }
3885
3886 ha->flags.nic_core_reset_hdlr_active = 1;
3887 if (qla83xx_nic_core_reset(base_vha)) {
3888 /* NIC Core reset failed. */
3889 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
3890 "NIC Core reset failed.\n");
3891 }
3892 ha->flags.nic_core_reset_hdlr_active = 0;
3893 }
3894}
3895
3896/* Work: Handle 8200 IDC aens */
3897void
3898qla83xx_service_idc_aen(struct work_struct *work)
3899{
3900 struct qla_hw_data *ha =
3901 container_of(work, struct qla_hw_data, idc_aen);
3902 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3903 uint32_t dev_state, idc_control;
3904
3905 qla83xx_idc_lock(base_vha, 0);
3906 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3907 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
3908 qla83xx_idc_unlock(base_vha, 0);
3909 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
3910 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
3911 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
3912 "Application requested NIC Core Reset.\n");
3913 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
3914 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
3915 QLA_SUCCESS) {
3916 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
3917 "Other protocol driver requested NIC Core Reset.\n");
3918 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
3919 }
3920 } else if (dev_state == QLA8XXX_DEV_FAILED ||
3921 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
3922 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
3923 }
3924}
3925
3926static void
3927qla83xx_wait_logic(void)
3928{
3929 int i;
3930
3931 /* Yield CPU */
3932 if (!in_interrupt()) {
3933 /*
3934 * Wait about 200ms before retrying again.
3935 * This controls the number of retries for single
3936 * lock operation.
3937 */
3938 msleep(100);
3939 schedule();
3940 } else {
3941 for (i = 0; i < 20; i++)
3942 cpu_relax(); /* This a nop instr on i386 */
3943 }
3944}
3945
3946int
3947qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
3948{
3949 int rval;
3950 uint32_t data;
3951 uint32_t idc_lck_rcvry_stage_mask = 0x3;
3952 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
3953 struct qla_hw_data *ha = base_vha->hw;
3954
3955 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
3956 if (rval)
3957 return rval;
3958
3959 if ((data & idc_lck_rcvry_stage_mask) > 0) {
3960 return QLA_SUCCESS;
3961 } else {
3962 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
3963 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
3964 data);
3965 if (rval)
3966 return rval;
3967
3968 msleep(200);
3969
3970 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
3971 &data);
3972 if (rval)
3973 return rval;
3974
3975 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
3976 data &= (IDC_LOCK_RECOVERY_STAGE2 |
3977 ~(idc_lck_rcvry_stage_mask));
3978 rval = qla83xx_wr_reg(base_vha,
3979 QLA83XX_IDC_LOCK_RECOVERY, data);
3980 if (rval)
3981 return rval;
3982
3983 /* Forcefully perform IDC UnLock */
3984 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
3985 &data);
3986 if (rval)
3987 return rval;
3988 /* Clear lock-id by setting 0xff */
3989 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
3990 0xff);
3991 if (rval)
3992 return rval;
3993 /* Clear lock-recovery by setting 0x0 */
3994 rval = qla83xx_wr_reg(base_vha,
3995 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
3996 if (rval)
3997 return rval;
3998 } else
3999 return QLA_SUCCESS;
4000 }
4001
4002 return rval;
4003}
4004
4005int
4006qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4007{
4008 int rval = QLA_SUCCESS;
4009 uint32_t o_drv_lockid, n_drv_lockid;
4010 unsigned long lock_recovery_timeout;
4011
4012 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4013retry_lockid:
4014 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4015 if (rval)
4016 goto exit;
4017
4018 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4019 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4020 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4021 return QLA_SUCCESS;
4022 else
4023 return QLA_FUNCTION_FAILED;
4024 }
4025
4026 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4027 if (rval)
4028 goto exit;
4029
4030 if (o_drv_lockid == n_drv_lockid) {
4031 qla83xx_wait_logic();
4032 goto retry_lockid;
4033 } else
4034 return QLA_SUCCESS;
4035
4036exit:
4037 return rval;
4038}
4039
4040void
4041qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4042{
4043 uint16_t options = (requester_id << 15) | BIT_6;
4044 uint32_t data;
4045 struct qla_hw_data *ha = base_vha->hw;
4046
4047 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4048retry_lock:
4049 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4050 == QLA_SUCCESS) {
4051 if (data) {
4052 /* Setting lock-id to our function-number */
4053 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4054 ha->portnum);
4055 } else {
4056 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4057 "Failed to acquire IDC lock. retrying...\n");
4058
4059 /* Retry/Perform IDC-Lock recovery */
4060 if (qla83xx_idc_lock_recovery(base_vha)
4061 == QLA_SUCCESS) {
4062 qla83xx_wait_logic();
4063 goto retry_lock;
4064 } else
4065 ql_log(ql_log_warn, base_vha, 0xb075,
4066 "IDC Lock recovery FAILED.\n");
4067 }
4068
4069 }
4070
4071 return;
4072
4073 /* XXX: IDC-lock implementation using access-control mbx */
4074retry_lock2:
4075 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4076 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4077 "Failed to acquire IDC lock. retrying...\n");
4078 /* Retry/Perform IDC-Lock recovery */
4079 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4080 qla83xx_wait_logic();
4081 goto retry_lock2;
4082 } else
4083 ql_log(ql_log_warn, base_vha, 0xb076,
4084 "IDC Lock recovery FAILED.\n");
4085 }
4086
4087 return;
4088}
4089
4090void
4091qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4092{
4093 uint16_t options = (requester_id << 15) | BIT_7, retry;
4094 uint32_t data;
4095 struct qla_hw_data *ha = base_vha->hw;
4096
4097 /* IDC-unlock implementation using driver-unlock/lock-id
4098 * remote registers
4099 */
4100 retry = 0;
4101retry_unlock:
4102 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4103 == QLA_SUCCESS) {
4104 if (data == ha->portnum) {
4105 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4106 /* Clearing lock-id by setting 0xff */
4107 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4108 } else if (retry < 10) {
4109 /* SV: XXX: IDC unlock retrying needed here? */
4110
4111 /* Retry for IDC-unlock */
4112 qla83xx_wait_logic();
4113 retry++;
4114 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4115 "Failed to release IDC lock, retyring=%d\n", retry);
4116 goto retry_unlock;
4117 }
4118 } else if (retry < 10) {
4119 /* Retry for IDC-unlock */
4120 qla83xx_wait_logic();
4121 retry++;
4122 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4123 "Failed to read drv-lockid, retyring=%d\n", retry);
4124 goto retry_unlock;
4125 }
4126
4127 return;
4128
4129 /* XXX: IDC-unlock implementation using access-control mbx */
4130 retry = 0;
4131retry_unlock2:
4132 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4133 if (retry < 10) {
4134 /* Retry for IDC-unlock */
4135 qla83xx_wait_logic();
4136 retry++;
4137 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4138 "Failed to release IDC lock, retyring=%d\n", retry);
4139 goto retry_unlock2;
4140 }
4141 }
4142
4143 return;
4144}
4145
4146int
4147__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4148{
4149 int rval = QLA_SUCCESS;
4150 struct qla_hw_data *ha = vha->hw;
4151 uint32_t drv_presence;
4152
4153 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4154 if (rval == QLA_SUCCESS) {
4155 drv_presence |= (1 << ha->portnum);
4156 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4157 drv_presence);
4158 }
4159
4160 return rval;
4161}
4162
4163int
4164qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4165{
4166 int rval = QLA_SUCCESS;
4167
4168 qla83xx_idc_lock(vha, 0);
4169 rval = __qla83xx_set_drv_presence(vha);
4170 qla83xx_idc_unlock(vha, 0);
4171
4172 return rval;
4173}
4174
4175int
4176__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4177{
4178 int rval = QLA_SUCCESS;
4179 struct qla_hw_data *ha = vha->hw;
4180 uint32_t drv_presence;
4181
4182 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4183 if (rval == QLA_SUCCESS) {
4184 drv_presence &= ~(1 << ha->portnum);
4185 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4186 drv_presence);
4187 }
4188
4189 return rval;
4190}
4191
4192int
4193qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4194{
4195 int rval = QLA_SUCCESS;
4196
4197 qla83xx_idc_lock(vha, 0);
4198 rval = __qla83xx_clear_drv_presence(vha);
4199 qla83xx_idc_unlock(vha, 0);
4200
4201 return rval;
4202}
4203
4204void
4205qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4206{
4207 struct qla_hw_data *ha = vha->hw;
4208 uint32_t drv_ack, drv_presence;
4209 unsigned long ack_timeout;
4210
4211 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4212 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4213 while (1) {
4214 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4215 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4216 if (drv_ack == drv_presence)
4217 break;
4218
4219 if (time_after_eq(jiffies, ack_timeout)) {
4220 ql_log(ql_log_warn, vha, 0xb067,
4221 "RESET ACK TIMEOUT! drv_presence=0x%x "
4222 "drv_ack=0x%x\n", drv_presence, drv_ack);
4223 /*
4224 * The function(s) which did not ack in time are forced
4225 * to withdraw any further participation in the IDC
4226 * reset.
4227 */
4228 if (drv_ack != drv_presence)
4229 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4230 drv_ack);
4231 break;
4232 }
4233
4234 qla83xx_idc_unlock(vha, 0);
4235 msleep(1000);
4236 qla83xx_idc_lock(vha, 0);
4237 }
4238
4239 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4240 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4241}
4242
4243int
4244qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4245{
4246 int rval = QLA_SUCCESS;
4247 uint32_t idc_control;
4248
4249 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4250 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4251
4252 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4253 __qla83xx_get_idc_control(vha, &idc_control);
4254 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4255 __qla83xx_set_idc_control(vha, 0);
4256
4257 qla83xx_idc_unlock(vha, 0);
4258 rval = qla83xx_restart_nic_firmware(vha);
4259 qla83xx_idc_lock(vha, 0);
4260
4261 if (rval != QLA_SUCCESS) {
4262 ql_log(ql_log_fatal, vha, 0xb06a,
4263 "Failed to restart NIC f/w.\n");
4264 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4265 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4266 } else {
4267 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4268 "Success in restarting nic f/w.\n");
4269 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4270 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4271 }
4272
4273 return rval;
4274}
4275
4276/* Assumes idc_lock always held on entry */
4277int
4278qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4279{
4280 struct qla_hw_data *ha = base_vha->hw;
4281 int rval = QLA_SUCCESS;
4282 unsigned long dev_init_timeout;
4283 uint32_t dev_state;
4284
4285 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4286 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4287
4288 while (1) {
4289
4290 if (time_after_eq(jiffies, dev_init_timeout)) {
4291 ql_log(ql_log_warn, base_vha, 0xb06e,
4292 "Initialization TIMEOUT!\n");
4293 /* Init timeout. Disable further NIC Core
4294 * communication.
4295 */
4296 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4297 QLA8XXX_DEV_FAILED);
4298 ql_log(ql_log_info, base_vha, 0xb06f,
4299 "HW State: FAILED.\n");
4300 }
4301
4302 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4303 switch (dev_state) {
4304 case QLA8XXX_DEV_READY:
4305 if (ha->flags.nic_core_reset_owner)
4306 qla83xx_idc_audit(base_vha,
4307 IDC_AUDIT_COMPLETION);
4308 ha->flags.nic_core_reset_owner = 0;
4309 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4310 "Reset_owner reset by 0x%x.\n",
4311 ha->portnum);
4312 goto exit;
4313 case QLA8XXX_DEV_COLD:
4314 if (ha->flags.nic_core_reset_owner)
4315 rval = qla83xx_device_bootstrap(base_vha);
4316 else {
4317 /* Wait for AEN to change device-state */
4318 qla83xx_idc_unlock(base_vha, 0);
4319 msleep(1000);
4320 qla83xx_idc_lock(base_vha, 0);
4321 }
4322 break;
4323 case QLA8XXX_DEV_INITIALIZING:
4324 /* Wait for AEN to change device-state */
4325 qla83xx_idc_unlock(base_vha, 0);
4326 msleep(1000);
4327 qla83xx_idc_lock(base_vha, 0);
4328 break;
4329 case QLA8XXX_DEV_NEED_RESET:
4330 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4331 qla83xx_need_reset_handler(base_vha);
4332 else {
4333 /* Wait for AEN to change device-state */
4334 qla83xx_idc_unlock(base_vha, 0);
4335 msleep(1000);
4336 qla83xx_idc_lock(base_vha, 0);
4337 }
4338 /* reset timeout value after need reset handler */
4339 dev_init_timeout = jiffies +
4340 (ha->fcoe_dev_init_timeout * HZ);
4341 break;
4342 case QLA8XXX_DEV_NEED_QUIESCENT:
4343 /* XXX: DEBUG for now */
4344 qla83xx_idc_unlock(base_vha, 0);
4345 msleep(1000);
4346 qla83xx_idc_lock(base_vha, 0);
4347 break;
4348 case QLA8XXX_DEV_QUIESCENT:
4349 /* XXX: DEBUG for now */
4350 if (ha->flags.quiesce_owner)
4351 goto exit;
4352
4353 qla83xx_idc_unlock(base_vha, 0);
4354 msleep(1000);
4355 qla83xx_idc_lock(base_vha, 0);
4356 dev_init_timeout = jiffies +
4357 (ha->fcoe_dev_init_timeout * HZ);
4358 break;
4359 case QLA8XXX_DEV_FAILED:
4360 if (ha->flags.nic_core_reset_owner)
4361 qla83xx_idc_audit(base_vha,
4362 IDC_AUDIT_COMPLETION);
4363 ha->flags.nic_core_reset_owner = 0;
4364 __qla83xx_clear_drv_presence(base_vha);
4365 qla83xx_idc_unlock(base_vha, 0);
4366 qla8xxx_dev_failed_handler(base_vha);
4367 rval = QLA_FUNCTION_FAILED;
4368 qla83xx_idc_lock(base_vha, 0);
4369 goto exit;
4370 case QLA8XXX_BAD_VALUE:
4371 qla83xx_idc_unlock(base_vha, 0);
4372 msleep(1000);
4373 qla83xx_idc_lock(base_vha, 0);
4374 break;
4375 default:
4376 ql_log(ql_log_warn, base_vha, 0xb071,
4377 "Unknow Device State: %x.\n", dev_state);
4378 qla83xx_idc_unlock(base_vha, 0);
4379 qla8xxx_dev_failed_handler(base_vha);
4380 rval = QLA_FUNCTION_FAILED;
4381 qla83xx_idc_lock(base_vha, 0);
4382 goto exit;
4383 }
4384 }
4385
4386exit:
4387 return rval;
4388}
4389
1da177e4
LT		 4390/**************************************************************************
4391* qla2x00_do_dpc
4392* This kernel thread is a task that is schedule by the interrupt handler
4393* to perform the background processing for interrupts.
4394*
4395* Notes:
4396* This task always run in the context of a kernel thread. It
4397* is kick-off by the driver's detect code and starts up
4398* up one per adapter. It immediately goes to sleep and waits for
4399* some fibre event. When either the interrupt handler or
4400* the timer routine detects a event it will one of the task
4401* bits then wake us up.
4402**************************************************************************/
4403static int
4404qla2x00_do_dpc(void *data)
4405{
2c3dfe3f 4406 int rval;
e315cd28
AC		 4407 scsi_qla_host_t *base_vha;
4408 struct qla_hw_data *ha;
1da177e4 4409
e315cd28
AC		 4410 ha = (struct qla_hw_data *)data;
4411 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4412
1da177e4
LT		 4413 set_user_nice(current, -20);
4414
563585ec 4415 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4416 while (!kthread_should_stop()) {
7c3df132
SK		 4417 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4418 "DPC handler sleeping.\n");
1da177e4 4419
39a11240
CH		 4420 schedule();
4421 __set_current_state(TASK_RUNNING);
1da177e4 4422
c142caf0
AV		 4423 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4424 goto end_loop;
1da177e4 4425
85880801 4426 if (ha->flags.eeh_busy) {
7c3df132
SK		 4427 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4428 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4429 goto end_loop;
85880801
AV		 4430 }
4431
1da177e4
LT		 4432 ha->dpc_active = 1;
4433
5f28d2d7
SK		 4434 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4435 "DPC handler waking up, dpc_flags=0x%lx.\n",
4436 base_vha->dpc_flags);
1da177e4 4437
e315cd28 4438 qla2x00_do_work(base_vha);
0971de7f 4439
a9083016
GM		 4440 if (IS_QLA82XX(ha)) {
4441 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4442 &base_vha->dpc_flags)) {
4443 qla82xx_idc_lock(ha);
4444 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 4445 QLA8XXX_DEV_FAILED);
a9083016 4446 qla82xx_idc_unlock(ha);
7c3df132
SK		 4447 ql_log(ql_log_info, base_vha, 0x4004,
4448 "HW State: FAILED.\n");
a9083016
GM		 4449 qla82xx_device_state_handler(base_vha);
4450 continue;
4451 }
4452
4453 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4454 &base_vha->dpc_flags)) {
4455
7c3df132
SK		 4456 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4457 "FCoE context reset scheduled.\n");
a9083016
GM		 4458 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4459 &base_vha->dpc_flags))) {
4460 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4461 /* FCoE-ctx reset failed.
4462 * Escalate to chip-reset
4463 */
4464 set_bit(ISP_ABORT_NEEDED,
4465 &base_vha->dpc_flags);
4466 }
4467 clear_bit(ABORT_ISP_ACTIVE,
4468 &base_vha->dpc_flags);
4469 }
4470
7c3df132
SK		 4471 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4472 "FCoE context reset end.\n");
a9083016
GM		 4473 }
4474 }
4475
e315cd28
AC		 4476 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4477 &base_vha->dpc_flags)) {
1da177e4 4478
7c3df132
SK		 4479 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4480 "ISP abort scheduled.\n");
1da177e4 4481 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4482 &base_vha->dpc_flags))) {
1da177e4 4483
a9083016 4484 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4485 /* failed. retry later */
4486 set_bit(ISP_ABORT_NEEDED,
e315cd28 4487 &base_vha->dpc_flags);
99363ef8 4488 }
e315cd28
AC		 4489 clear_bit(ABORT_ISP_ACTIVE,
4490 &base_vha->dpc_flags);
99363ef8
SJ		 4491 }
4492
7c3df132
SK		 4493 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4494 "ISP abort end.\n");
1da177e4
LT		 4495 }
4496
e315cd28
AC		 4497 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
4498 qla2x00_update_fcports(base_vha);
4499 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 4500 }
d97994dc 4501
2d70c103
NB		 4502 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4503 int ret;
4504 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4505 if (ret != QLA_SUCCESS)
4506 ql_log(ql_log_warn, base_vha, 0x121,
4507 "Failed to enable receiving of RSCN "
4508 "requests: 0x%x.\n", ret);
4509 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4510 }
4511
579d12b5 4512 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4513 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4514 "Quiescence mode scheduled.\n");
8fcd6b8b
CD		 4515 if (IS_QLA82XX(ha)) {
4516 qla82xx_device_state_handler(base_vha);
4517 clear_bit(ISP_QUIESCE_NEEDED,
4518 &base_vha->dpc_flags);
4519 if (!ha->flags.quiesce_owner) {
4520 qla2x00_perform_loop_resync(base_vha);
4521
4522 qla82xx_idc_lock(ha);
4523 qla82xx_clear_qsnt_ready(base_vha);
4524 qla82xx_idc_unlock(ha);
4525 }
4526 } else {
4527 clear_bit(ISP_QUIESCE_NEEDED,
4528 &base_vha->dpc_flags);
4529 qla2x00_quiesce_io(base_vha);
579d12b5 4530 }
7c3df132
SK		 4531 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4532 "Quiescence mode end.\n");
579d12b5
SK		 4533 }
4534
e315cd28
AC		 4535 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4536 &base_vha->dpc_flags) &&
4537 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4538
7c3df132
SK		 4539 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4540 "Reset marker scheduled.\n");
e315cd28
AC		 4541 qla2x00_rst_aen(base_vha);
4542 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4543 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4544 "Reset marker end.\n");
1da177e4
LT		 4545 }
4546
4547 /* Retry each device up to login retry count */
e315cd28
AC		 4548 if ((test_and_clear_bit(RELOGIN_NEEDED,
4549 &base_vha->dpc_flags)) &&
4550 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4551 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4552
7c3df132
SK		 4553 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4554 "Relogin scheduled.\n");
e315cd28 4555 qla2x00_relogin(base_vha);
7c3df132
SK		 4556 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4557 "Relogin end.\n");
1da177e4
LT		 4558 }
4559
e315cd28
AC		 4560 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
4561 &base_vha->dpc_flags)) {
1da177e4 4562
7c3df132
SK		 4563 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4564 "Loop resync scheduled.\n");
1da177e4
LT		 4565
4566 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4567 &base_vha->dpc_flags))) {
1da177e4 4568
e315cd28 4569 rval = qla2x00_loop_resync(base_vha);
1da177e4 4570
e315cd28
AC		 4571 clear_bit(LOOP_RESYNC_ACTIVE,
4572 &base_vha->dpc_flags);
1da177e4
LT		 4573 }
4574
7c3df132
SK		 4575 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4576 "Loop resync end.\n");
1da177e4
LT		 4577 }
4578
e315cd28
AC		 4579 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4580 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4581 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4582 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 4583 }
4584
1da177e4 4585 if (!ha->interrupts_on)
fd34f556 4586 ha->isp_ops->enable_intrs(ha);
1da177e4 4587
e315cd28
AC		 4588 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
4589 &base_vha->dpc_flags))
4590 ha->isp_ops->beacon_blink(base_vha);
f6df144c 4591
e315cd28 4592 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 4593
1da177e4 4594 ha->dpc_active = 0;
c142caf0 4595end_loop:
563585ec 4596 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 4597 } /* End of while(1) */
563585ec 4598 __set_current_state(TASK_RUNNING);
1da177e4 4599
7c3df132
SK		 4600 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
4601 "DPC handler exiting.\n");
1da177e4
LT		 4602
4603 /*
4604 * Make sure that nobody tries to wake us up again.
4605 */
1da177e4
LT		 4606 ha->dpc_active = 0;
4607
ac280b67
AV		 4608 /* Cleanup any residual CTX SRBs. */
4609 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4610
39a11240
CH		 4611 return 0;
4612}
4613
4614void
e315cd28 4615qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 4616{
e315cd28 4617 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 4618 struct task_struct *t = ha->dpc_thread;
4619
e315cd28 4620 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 4621 wake_up_process(t);
1da177e4
LT		 4622}
4623
1da177e4
LT		 4624/*
4625* qla2x00_rst_aen
4626* Processes asynchronous reset.
4627*
4628* Input:
4629* ha = adapter block pointer.
4630*/
4631static void
e315cd28 4632qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 4633{
e315cd28
AC		 4634 if (vha->flags.online && !vha->flags.reset_active &&
4635 !atomic_read(&vha->loop_down_timer) &&
4636 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 4637 do {
e315cd28 4638 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4639
4640 /*
4641 * Issue marker command only when we are going to start
4642 * the I/O.
4643 */
e315cd28
AC		 4644 vha->marker_needed = 1;
4645 } while (!atomic_read(&vha->loop_down_timer) &&
4646 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 4647 }
4648}
4649
1da177e4
LT		 4650/**************************************************************************
4651* qla2x00_timer
4652*
4653* Description:
4654* One second timer
4655*
4656* Context: Interrupt
4657***************************************************************************/
2c3dfe3f 4658void
e315cd28 4659qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 4660{
1da177e4 4661 unsigned long cpu_flags = 0;
1da177e4
LT		 4662 int start_dpc = 0;
4663 int index;
4664 srb_t *sp;
85880801 4665 uint16_t w;
e315cd28 4666 struct qla_hw_data *ha = vha->hw;
73208dfd 4667 struct req_que *req;
85880801 4668
a5b36321 4669 if (ha->flags.eeh_busy) {
7c3df132
SK		 4670 ql_dbg(ql_dbg_timer, vha, 0x6000,
4671 "EEH = %d, restarting timer.\n",
4672 ha->flags.eeh_busy);
a5b36321
LC		 4673 qla2x00_restart_timer(vha, WATCH_INTERVAL);
4674 return;
4675 }
4676
85880801
AV		 4677 /* Hardware read to raise pending EEH errors during mailbox waits. */
4678 if (!pci_channel_offline(ha->pdev))
4679 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 4680
cefcaba6
SK		 4681 /* Make sure qla82xx_watchdog is run only for physical port */
4682 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 4683 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
4684 start_dpc++;
4685 qla82xx_watchdog(vha);
4686 }
4687
1da177e4 4688 /* Loop down handler. */
e315cd28 4689 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 4690 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
4691 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 4692 && vha->flags.online) {
1da177e4 4693
e315cd28
AC		 4694 if (atomic_read(&vha->loop_down_timer) ==
4695 vha->loop_down_abort_time) {
1da177e4 4696
7c3df132
SK		 4697 ql_log(ql_log_info, vha, 0x6008,
4698 "Loop down - aborting the queues before time expires.\n");
1da177e4 4699
e315cd28
AC		 4700 if (!IS_QLA2100(ha) && vha->link_down_timeout)
4701 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 4702
f08b7251
AV		 4703 /*
4704 * Schedule an ISP abort to return any FCP2-device
4705 * commands.
4706 */
2c3dfe3f 4707 /* NPIV - scan physical port only */
e315cd28 4708 if (!vha->vp_idx) {
2c3dfe3f
SJ		 4709 spin_lock_irqsave(&ha->hardware_lock,
4710 cpu_flags);
73208dfd 4711 req = ha->req_q_map[0];
2c3dfe3f
SJ		 4712 for (index = 1;
4713 index < MAX_OUTSTANDING_COMMANDS;
4714 index++) {
4715 fc_port_t *sfcp;
4716
e315cd28 4717 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 4718 if (!sp)
4719 continue;
9ba56b95 4720 if (sp->type != SRB_SCSI_CMD)
cf53b069 4721 continue;
2c3dfe3f 4722 sfcp = sp->fcport;
f08b7251 4723 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 4724 continue;
bdf79621 4725
8f7daead
GM		 4726 if (IS_QLA82XX(ha))
4727 set_bit(FCOE_CTX_RESET_NEEDED,
4728 &vha->dpc_flags);
4729 else
4730 set_bit(ISP_ABORT_NEEDED,
e315cd28 4731 &vha->dpc_flags);
2c3dfe3f
SJ		 4732 break;
4733 }
4734 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 4735 cpu_flags);
1da177e4 4736 }
1da177e4
LT		 4737 start_dpc++;
4738 }
4739
4740 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 4741 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 4742 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 4743 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 4744 "Loop down - aborting ISP.\n");
4745
8f7daead
GM		 4746 if (IS_QLA82XX(ha))
4747 set_bit(FCOE_CTX_RESET_NEEDED,
4748 &vha->dpc_flags);
4749 else
4750 set_bit(ISP_ABORT_NEEDED,
4751 &vha->dpc_flags);
1da177e4
LT		 4752 }
4753 }
7c3df132
SK		 4754 ql_dbg(ql_dbg_timer, vha, 0x600a,
4755 "Loop down - seconds remaining %d.\n",
4756 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 4757 }
4758
cefcaba6
SK		 4759 /* Check if beacon LED needs to be blinked for physical host only */
4760 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 4761 /* There is no beacon_blink function for ISP82xx */
4762 if (!IS_QLA82XX(ha)) {
4763 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
4764 start_dpc++;
4765 }
f6df144c
AV		 4766 }
4767
550bf57d 4768 /* Process any deferred work. */
e315cd28 4769 if (!list_empty(&vha->work_list))
550bf57d
AV		 4770 start_dpc++;
4771
1da177e4 4772 /* Schedule the DPC routine if needed */
e315cd28
AC		 4773 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
4774 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
4775 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 4776 start_dpc ||
e315cd28
AC		 4777 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
4778 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 4779 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
4780 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 4781 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 4782 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
4783 ql_dbg(ql_dbg_timer, vha, 0x600b,
4784 "isp_abort_needed=%d loop_resync_needed=%d "
4785 "fcport_update_needed=%d start_dpc=%d "
4786 "reset_marker_needed=%d",
4787 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
4788 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
4789 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
4790 start_dpc,
4791 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
4792 ql_dbg(ql_dbg_timer, vha, 0x600c,
4793 "beacon_blink_needed=%d isp_unrecoverable=%d "
4794 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
4795 "relogin_needed=%d.\n",
4796 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
4797 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
4798 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
4799 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
4800 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 4801 qla2xxx_wake_dpc(vha);
7c3df132 4802 }
1da177e4 4803
e315cd28 4804 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 4805}
4806
5433383e
AV		 4807/* Firmware interface routines. */
4808
6246b8a1 4809#define FW_BLOBS 10
5433383e
AV		 4810#define FW_ISP21XX 0
4811#define FW_ISP22XX 1
4812#define FW_ISP2300 2
4813#define FW_ISP2322 3
48c02fde 4814#define FW_ISP24XX 4
c3a2f0df 4815#define FW_ISP25XX 5
3a03eb79 4816#define FW_ISP81XX 6
a9083016 4817#define FW_ISP82XX 7
6246b8a1
GM		 4818#define FW_ISP2031 8
4819#define FW_ISP8031 9
5433383e 4820
bb8ee499
AV		 4821#define FW_FILE_ISP21XX "ql2100_fw.bin"
4822#define FW_FILE_ISP22XX "ql2200_fw.bin"
4823#define FW_FILE_ISP2300 "ql2300_fw.bin"
4824#define FW_FILE_ISP2322 "ql2322_fw.bin"
4825#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 4826#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 4827#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 4828#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 4829#define FW_FILE_ISP2031 "ql2600_fw.bin"
4830#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 4831
e1e82b6f 4832static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 4833
4834static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 4835 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
4836 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
4837 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
4838 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
4839 { .name = FW_FILE_ISP24XX, },
c3a2f0df 4840 { .name = FW_FILE_ISP25XX, },
3a03eb79 4841 { .name = FW_FILE_ISP81XX, },
a9083016 4842 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 4843 { .name = FW_FILE_ISP2031, },
4844 { .name = FW_FILE_ISP8031, },
5433383e
AV		 4845};
4846
4847struct fw_blob *
e315cd28 4848qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 4849{
e315cd28 4850 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 4851 struct fw_blob *blob;
4852
5433383e
AV		 4853 if (IS_QLA2100(ha)) {
4854 blob = &qla_fw_blobs[FW_ISP21XX];
4855 } else if (IS_QLA2200(ha)) {
4856 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 4857 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 4858 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 4859 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 4860 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 4861 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 4862 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 4863 } else if (IS_QLA25XX(ha)) {
4864 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 4865 } else if (IS_QLA81XX(ha)) {
4866 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 4867 } else if (IS_QLA82XX(ha)) {
4868 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 4869 } else if (IS_QLA2031(ha)) {
4870 blob = &qla_fw_blobs[FW_ISP2031];
4871 } else if (IS_QLA8031(ha)) {
4872 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 4873 } else {
4874 return NULL;
5433383e
AV		 4875 }
4876
e1e82b6f 4877 mutex_lock(&qla_fw_lock);
5433383e
AV		 4878 if (blob->fw)
4879 goto out;
4880
4881 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4882 ql_log(ql_log_warn, vha, 0x0063,
4883 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4884 blob->fw = NULL;
4885 blob = NULL;
4886 goto out;
4887 }
4888
4889out:
e1e82b6f 4890 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4891 return blob;
4892}
4893
4894static void
4895qla2x00_release_firmware(void)
4896{
4897 int idx;
4898
e1e82b6f 4899 mutex_lock(&qla_fw_lock);
5433383e 4900 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 4901 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4902 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4903}
4904
14e660e6
SJ		 4905static pci_ers_result_t
4906qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4907{
85880801
AV		 4908 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4909 struct qla_hw_data *ha = vha->hw;
4910
7c3df132
SK		 4911 ql_dbg(ql_dbg_aer, vha, 0x9000,
4912 "PCI error detected, state %x.\n", state);
b9b12f73 4913
14e660e6
SJ		 4914 switch (state) {
4915 case pci_channel_io_normal:
85880801 4916 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4917 return PCI_ERS_RESULT_CAN_RECOVER;
4918 case pci_channel_io_frozen:
85880801 4919 ha->flags.eeh_busy = 1;
a5b36321
LC		 4920 /* For ISP82XX complete any pending mailbox cmd */
4921 if (IS_QLA82XX(ha)) {
7190575f 4922 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 4923 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
4924 qla82xx_clear_pending_mbx(vha);
a5b36321 4925 }
90a86fc0 4926 qla2x00_free_irqs(vha);
14e660e6 4927 pci_disable_device(pdev);
bddd2d65
LC		 4928 /* Return back all IOs */
4929 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4930 return PCI_ERS_RESULT_NEED_RESET;
4931 case pci_channel_io_perm_failure:
85880801
AV		 4932 ha->flags.pci_channel_io_perm_failure = 1;
4933 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4934 return PCI_ERS_RESULT_DISCONNECT;
4935 }
4936 return PCI_ERS_RESULT_NEED_RESET;
4937}
4938
4939static pci_ers_result_t
4940qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4941{
4942 int risc_paused = 0;
4943 uint32_t stat;
4944 unsigned long flags;
e315cd28
AC		 4945 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4946 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4947 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4948 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4949
bcc5b6d3
SK		 4950 if (IS_QLA82XX(ha))
4951 return PCI_ERS_RESULT_RECOVERED;
4952
14e660e6
SJ		 4953 spin_lock_irqsave(&ha->hardware_lock, flags);
4954 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4955 stat = RD_REG_DWORD(&reg->hccr);
4956 if (stat & HCCR_RISC_PAUSE)
4957 risc_paused = 1;
4958 } else if (IS_QLA23XX(ha)) {
4959 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4960 if (stat & HSR_RISC_PAUSED)
4961 risc_paused = 1;
4962 } else if (IS_FWI2_CAPABLE(ha)) {
4963 stat = RD_REG_DWORD(&reg24->host_status);
4964 if (stat & HSRX_RISC_PAUSED)
4965 risc_paused = 1;
4966 }
4967 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4968
4969 if (risc_paused) {
7c3df132
SK		 4970 ql_log(ql_log_info, base_vha, 0x9003,
4971 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4972 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4973
4974 return PCI_ERS_RESULT_NEED_RESET;
4975 } else
4976 return PCI_ERS_RESULT_RECOVERED;
4977}
4978
a5b36321
LC		 4979uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4980{
4981 uint32_t rval = QLA_FUNCTION_FAILED;
4982 uint32_t drv_active = 0;
4983 struct qla_hw_data *ha = base_vha->hw;
4984 int fn;
4985 struct pci_dev *other_pdev = NULL;
4986
7c3df132
SK		 4987 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4988 "Entered %s.\n", __func__);
a5b36321
LC		 4989
4990 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4991
4992 if (base_vha->flags.online) {
4993 /* Abort all outstanding commands,
4994 * so as to be requeued later */
4995 qla2x00_abort_isp_cleanup(base_vha);
4996 }
4997
4998
4999 fn = PCI_FUNC(ha->pdev->devfn);
5000 while (fn > 0) {
5001 fn--;
7c3df132
SK		 5002 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5003 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5004 other_pdev =
5005 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5006 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5007 fn));
5008
5009 if (!other_pdev)
5010 continue;
5011 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5012 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5013 "Found PCI func available and enable at 0x%x.\n",
5014 fn);
a5b36321
LC		 5015 pci_dev_put(other_pdev);
5016 break;
5017 }
5018 pci_dev_put(other_pdev);
5019 }
5020
5021 if (!fn) {
5022 /* Reset owner */
7c3df132
SK		 5023 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5024 "This devfn is reset owner = 0x%x.\n",
5025 ha->pdev->devfn);
a5b36321
LC		 5026 qla82xx_idc_lock(ha);
5027
5028 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5029 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5030
5031 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5032 QLA82XX_IDC_VERSION);
5033
5034 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5035 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5036 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5037
5038 qla82xx_idc_unlock(ha);
5039 /* Reset if device is not already reset
5040 * drv_active would be 0 if a reset has already been done
5041 */
5042 if (drv_active)
5043 rval = qla82xx_start_firmware(base_vha);
5044 else
5045 rval = QLA_SUCCESS;
5046 qla82xx_idc_lock(ha);
5047
5048 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5049 ql_log(ql_log_info, base_vha, 0x900b,
5050 "HW State: FAILED.\n");
a5b36321
LC		 5051 qla82xx_clear_drv_active(ha);
5052 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5053 QLA8XXX_DEV_FAILED);
a5b36321 5054 } else {
7c3df132
SK		 5055 ql_log(ql_log_info, base_vha, 0x900c,
5056 "HW State: READY.\n");
a5b36321 5057 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5058 QLA8XXX_DEV_READY);
a5b36321 5059 qla82xx_idc_unlock(ha);
7190575f 5060 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5061 rval = qla82xx_restart_isp(base_vha);
5062 qla82xx_idc_lock(ha);
5063 /* Clear driver state register */
5064 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5065 qla82xx_set_drv_active(base_vha);
5066 }
5067 qla82xx_idc_unlock(ha);
5068 } else {
7c3df132
SK		 5069 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5070 "This devfn is not reset owner = 0x%x.\n",
5071 ha->pdev->devfn);
a5b36321 5072 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5073 QLA8XXX_DEV_READY)) {
7190575f 5074 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5075 rval = qla82xx_restart_isp(base_vha);
5076 qla82xx_idc_lock(ha);
5077 qla82xx_set_drv_active(base_vha);
5078 qla82xx_idc_unlock(ha);
5079 }
5080 }
5081 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5082
5083 return rval;
5084}
5085
14e660e6
SJ		 5086static pci_ers_result_t
5087qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5088{
5089 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5090 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5091 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5092 struct rsp_que *rsp;
5093 int rc, retries = 10;
09483916 5094
7c3df132
SK		 5095 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5096 "Slot Reset.\n");
85880801 5097
90a86fc0
JC		 5098 /* Workaround: qla2xxx driver which access hardware earlier
5099 * needs error state to be pci_channel_io_online.
5100 * Otherwise mailbox command timesout.
5101 */
5102 pdev->error_state = pci_channel_io_normal;
5103
5104 pci_restore_state(pdev);
5105
8c1496bd
RL		 5106 /* pci_restore_state() clears the saved_state flag of the device
5107 * save restored state which resets saved_state flag
5108 */
5109 pci_save_state(pdev);
5110
09483916
BH		 5111 if (ha->mem_only)
5112 rc = pci_enable_device_mem(pdev);
5113 else
5114 rc = pci_enable_device(pdev);
14e660e6 5115
09483916 5116 if (rc) {
7c3df132 5117 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5118 "Can't re-enable PCI device after reset.\n");
a5b36321 5119 goto exit_slot_reset;
14e660e6 5120 }
14e660e6 5121
90a86fc0
JC		 5122 rsp = ha->rsp_q_map[0];
5123 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5124 goto exit_slot_reset;
90a86fc0 5125
e315cd28 5126 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5127 goto exit_slot_reset;
5128
5129 if (IS_QLA82XX(ha)) {
5130 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5131 ret = PCI_ERS_RESULT_RECOVERED;
5132 goto exit_slot_reset;
5133 } else
5134 goto exit_slot_reset;
5135 }
14e660e6 5136
90a86fc0
JC		 5137 while (ha->flags.mbox_busy && retries--)
5138 msleep(1000);
85880801 5139
e315cd28 5140 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5141 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5142 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5143 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5144
90a86fc0 5145
a5b36321 5146exit_slot_reset:
7c3df132
SK		 5147 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5148 "slot_reset return %x.\n", ret);
85880801 5149
14e660e6
SJ		 5150 return ret;
5151}
5152
5153static void
5154qla2xxx_pci_resume(struct pci_dev *pdev)
5155{
e315cd28
AC		 5156 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5157 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5158 int ret;
5159
7c3df132
SK		 5160 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5161 "pci_resume.\n");
85880801 5162
e315cd28 5163 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5164 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5165 ql_log(ql_log_fatal, base_vha, 0x9002,
5166 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5167 }
85880801 5168
3e46f031
LC		 5169 pci_cleanup_aer_uncorrect_error_status(pdev);
5170
85880801 5171 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5172}
5173
5174static struct pci_error_handlers qla2xxx_err_handler = {
5175 .error_detected = qla2xxx_pci_error_detected,
5176 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5177 .slot_reset = qla2xxx_pci_slot_reset,
5178 .resume = qla2xxx_pci_resume,
5179};
5180
5433383e 5181static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5182 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5183 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5184 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5185 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5186 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5187 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5188 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5189 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5190 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5191 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5192 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5195 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5196 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5197 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5198 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5433383e
AV		 5199 { 0 },
5200};
5201MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5202
fca29703 5203static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5204 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5205 .driver = {
5206 .owner = THIS_MODULE,
5207 },
fca29703 5208 .id_table = qla2xxx_pci_tbl,
7ee61397 5209 .probe = qla2x00_probe_one,
4c993f76 5210 .remove = qla2x00_remove_one,
e30d1756 5211 .shutdown = qla2x00_shutdown,
14e660e6 5212 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5213};
5214
6a03b4cd
HZ		 5215static struct file_operations apidev_fops = {
5216 .owner = THIS_MODULE,
6038f373 5217 .llseek = noop_llseek,
6a03b4cd
HZ		 5218};
5219
1da177e4
LT		 5220/**
5221 * qla2x00_module_init - Module initialization.
5222 **/
5223static int __init
5224qla2x00_module_init(void)
5225{
fca29703
AV		 5226 int ret = 0;
5227
1da177e4 5228 /* Allocate cache for SRBs. */
354d6b21 5229 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5230 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5231 if (srb_cachep == NULL) {
7c3df132
SK		 5232 ql_log(ql_log_fatal, NULL, 0x0001,
5233 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5234 return -ENOMEM;
5235 }
5236
2d70c103
NB		 5237 /* Initialize target kmem_cache and mem_pools */
5238 ret = qlt_init();
5239 if (ret < 0) {
5240 kmem_cache_destroy(srb_cachep);
5241 return ret;
5242 } else if (ret > 0) {
5243 /*
5244 * If initiator mode is explictly disabled by qlt_init(),
5245 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5246 * performing scsi_scan_target() during LOOP UP event.
5247 */
5248 qla2xxx_transport_functions.disable_target_scan = 1;
5249 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5250 }
5251
1da177e4
LT		 5252 /* Derive version string. */
5253 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5254 if (ql2xextended_error_logging)
0181944f
AV		 5255 strcat(qla2x00_version_str, "-debug");
5256
1c97a12a
AV		 5257 qla2xxx_transport_template =
5258 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5259 if (!qla2xxx_transport_template) {
5260 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5261 ql_log(ql_log_fatal, NULL, 0x0002,
5262 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5263 qlt_exit();
1da177e4 5264 return -ENODEV;
2c3dfe3f 5265 }
6a03b4cd
HZ		 5266
5267 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5268 if (apidev_major < 0) {
7c3df132
SK		 5269 ql_log(ql_log_fatal, NULL, 0x0003,
5270 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5271 }
5272
2c3dfe3f
SJ		 5273 qla2xxx_transport_vport_template =
5274 fc_attach_transport(&qla2xxx_transport_vport_functions);
5275 if (!qla2xxx_transport_vport_template) {
5276 kmem_cache_destroy(srb_cachep);
2d70c103 5277 qlt_exit();
2c3dfe3f 5278 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5279 ql_log(ql_log_fatal, NULL, 0x0004,
5280 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5281 return -ENODEV;
2c3dfe3f 5282 }
7c3df132
SK		 5283 ql_log(ql_log_info, NULL, 0x0005,
5284 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5285 qla2x00_version_str);
7ee61397 5286 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5287 if (ret) {
5288 kmem_cache_destroy(srb_cachep);
2d70c103 5289 qlt_exit();
fca29703 5290 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5291 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5292 ql_log(ql_log_fatal, NULL, 0x0006,
5293 "pci_register_driver failed...ret=%d Failing load!.\n",
5294 ret);
fca29703
AV		 5295 }
5296 return ret;
1da177e4
LT		 5297}
5298
5299/**
5300 * qla2x00_module_exit - Module cleanup.
5301 **/
5302static void __exit
5303qla2x00_module_exit(void)
5304{
6a03b4cd 5305 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5306 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5307 qla2x00_release_firmware();
354d6b21 5308 kmem_cache_destroy(srb_cachep);
2d70c103 5309 qlt_exit();
a9083016
GM		 5310 if (ctx_cachep)
5311 kmem_cache_destroy(ctx_cachep);
1da177e4 5312 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5313 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5314}
5315
5316module_init(qla2x00_module_init);
5317module_exit(qla2x00_module_exit);
5318
5319MODULE_AUTHOR("QLogic Corporation");
5320MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5321MODULE_LICENSE("GPL");
5322MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5323MODULE_FIRMWARE(FW_FILE_ISP21XX);
5324MODULE_FIRMWARE(FW_FILE_ISP22XX);
5325MODULE_FIRMWARE(FW_FILE_ISP2300);
5326MODULE_FIRMWARE(FW_FILE_ISP2322);
5327MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5328MODULE_FIRMWARE(FW_FILE_ISP25XX);
kernel source for telekom puls (alcatel/mediatek)