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[SCSI] qla2xxx: Proper completion to scsi-ml for scsi status task_set_full and busy.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22/*
23 * Driver version
24 */
25char qla2x00_version_str[40];
26
6a03b4cd
HZ		 27static int apidev_major;
28
1da177e4
LT		 29/*
30 * SRB allocation cache
31 */
e18b890b 32static struct kmem_cache *srb_cachep;
1da177e4 33
a9083016
GM		 34/*
35 * CT6 CTX allocation cache
36 */
37static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 38/*
39 * error level for logging
40 */
41int ql_errlev = ql_log_all;
a9083016 42
1da177e4 43int ql2xlogintimeout = 20;
f2019cb1 44module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
a7b61842 48int qlport_down_retry;
f2019cb1 49module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 50MODULE_PARM_DESC(qlport_down_retry,
900d9f98 51 "Maximum number of command retries to a port that returns "
1da177e4
LT		 52 "a PORT-DOWN status.");
53
1da177e4
LT		 54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
900d9f98 58 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
1da177e4 61int ql2xloginretrycount = 0;
f2019cb1 62module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
a7a167bf 66int ql2xallocfwdump = 1;
f2019cb1 67module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
11010fec 73int ql2xextended_error_logging;
27d94035 74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 75MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 86 "\t\t0x1e400000 - Preferred value for capturing essential "
87 "debug information (equivalent to old "
88 "ql2xextended_error_logging=1).\n"
3ce8866c 89 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 90
a9083016 91int ql2xshiftctondsd = 6;
f2019cb1 92module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 93MODULE_PARM_DESC(ql2xshiftctondsd,
94 "Set to control shifting of command type processing "
95 "based on total number of SG elements.");
96
1da177e4
LT		 97static void qla2x00_free_device(scsi_qla_host_t *);
98
7e47e5ca 99int ql2xfdmienable=1;
f2019cb1 100module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 101MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 102 "Enables FDMI registrations. "
103 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 104
df7baa50
AV		 105#define MAX_Q_DEPTH 32
106static int ql2xmaxqdepth = MAX_Q_DEPTH;
107module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
108MODULE_PARM_DESC(ql2xmaxqdepth,
109 "Maximum queue depth to report for target devices.");
110
bad75002 111/* Do not change the value of this after module load */
8cb2049c 112int ql2xenabledif = 0;
bad75002
AE		 113module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
114MODULE_PARM_DESC(ql2xenabledif,
115 " Enable T10-CRC-DIF "
8cb2049c
AE		 116 " Default is 0 - No DIF Support. 1 - Enable it"
117 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 118
8cb2049c 119int ql2xenablehba_err_chk = 2;
bad75002
AE		 120module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 122 " Enable T10-CRC-DIF Error isolation by HBA:\n"
123 " Default is 1.\n"
124 " 0 -- Error isolation disabled\n"
125 " 1 -- Error isolation enabled only for DIX Type 0\n"
126 " 2 -- Error isolation enabled for all Types\n");
bad75002 127
e5896bd5 128int ql2xiidmaenable=1;
f2019cb1 129module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 130MODULE_PARM_DESC(ql2xiidmaenable,
131 "Enables iIDMA settings "
132 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
133
73208dfd 134int ql2xmaxqueues = 1;
f2019cb1 135module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 136MODULE_PARM_DESC(ql2xmaxqueues,
137 "Enables MQ settings "
ae68230c
JP		 138 "Default is 1 for single queue. Set it to number "
139 "of queues in MQ mode.");
68ca949c
AC		 140
141int ql2xmultique_tag;
f2019cb1 142module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 143MODULE_PARM_DESC(ql2xmultique_tag,
144 "Enables CPU affinity settings for the driver "
145 "Default is 0 for no affinity of request and response IO. "
146 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 147
148int ql2xfwloadbin;
86e45bf6 149module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 150MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 151 "Option to specify location from which to load ISP firmware:.\n"
152 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 153 " interface.\n"
154 " 1 -- load firmware from flash.\n"
155 " 0 -- use default semantics.\n");
156
ae97c91e 157int ql2xetsenable;
f2019cb1 158module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 159MODULE_PARM_DESC(ql2xetsenable,
160 "Enables firmware ETS burst."
161 "Default is 0 - skip ETS enablement.");
162
6907869d 163int ql2xdbwr = 1;
86e45bf6 164module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 165MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 166 "Option to specify scheme for request queue posting.\n"
167 " 0 -- Regular doorbell.\n"
168 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 169
f4c496c1 170int ql2xtargetreset = 1;
f2019cb1 171module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 172MODULE_PARM_DESC(ql2xtargetreset,
173 "Enable target reset."
174 "Default is 1 - use hw defaults.");
175
4da26e16 176int ql2xgffidenable;
f2019cb1 177module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 178MODULE_PARM_DESC(ql2xgffidenable,
179 "Enables GFF_ID checks of port type. "
180 "Default is 0 - Do not use GFF_ID information.");
a9083016 181
3822263e 182int ql2xasynctmfenable;
f2019cb1 183module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 184MODULE_PARM_DESC(ql2xasynctmfenable,
185 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
186 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 187
188int ql2xdontresethba;
86e45bf6 189module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 190MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 191 "Option to specify reset behaviour.\n"
192 " 0 (Default) -- Reset on failure.\n"
193 " 1 -- Do not reset on failure.\n");
ed0de87c 194
82515920
AV		 195uint ql2xmaxlun = MAX_LUNS;
196module_param(ql2xmaxlun, uint, S_IRUGO);
197MODULE_PARM_DESC(ql2xmaxlun,
198 "Defines the maximum LU number to register with the SCSI "
199 "midlayer. Default is 65535.");
200
08de2844
GM		 201int ql2xmdcapmask = 0x1F;
202module_param(ql2xmdcapmask, int, S_IRUGO);
203MODULE_PARM_DESC(ql2xmdcapmask,
204 "Set the Minidump driver capture mask level. "
6e96fa7b 205 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 206
3aadff35 207int ql2xmdenable = 1;
08de2844
GM		 208module_param(ql2xmdenable, int, S_IRUGO);
209MODULE_PARM_DESC(ql2xmdenable,
210 "Enable/disable MiniDump. "
3aadff35
GM		 211 "0 - MiniDump disabled. "
212 "1 (Default) - MiniDump enabled.");
08de2844 213
1da177e4 214/*
fa2a1ce5 215 * SCSI host template entry points
1da177e4
LT		 216 */
217static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 218static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 219static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
220static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 221static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 222static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 223static int qla2xxx_eh_abort(struct scsi_cmnd *);
224static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 225static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 226static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
227static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 228
e881a172 229static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 230static int qla2x00_change_queue_type(struct scsi_device *, int);
231
a5326f86 232struct scsi_host_template qla2xxx_driver_template = {
1da177e4 233 .module = THIS_MODULE,
cb63067a 234 .name = QLA2XXX_DRIVER_NAME,
a5326f86 235 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 236
237 .eh_abort_handler = qla2xxx_eh_abort,
238 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 239 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 240 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
241 .eh_host_reset_handler = qla2xxx_eh_host_reset,
242
243 .slave_configure = qla2xxx_slave_configure,
244
245 .slave_alloc = qla2xxx_slave_alloc,
246 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 247 .scan_finished = qla2xxx_scan_finished,
248 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 249 .change_queue_depth = qla2x00_change_queue_depth,
250 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 251 .this_id = -1,
252 .cmd_per_lun = 3,
253 .use_clustering = ENABLE_CLUSTERING,
254 .sg_tablesize = SG_ALL,
255
256 .max_sectors = 0xFFFF,
afb046e2 257 .shost_attrs = qla2x00_host_attrs,
fca29703
AV		 258};
259
1da177e4 260static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 261struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 262
1da177e4
LT		 263/* TODO Convert to inlines
264 *
265 * Timer routines
266 */
1da177e4 267
2c3dfe3f 268__inline__ void
e315cd28 269qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 270{
e315cd28
AC		 271 init_timer(&vha->timer);
272 vha->timer.expires = jiffies + interval * HZ;
273 vha->timer.data = (unsigned long)vha;
274 vha->timer.function = (void (*)(unsigned long))func;
275 add_timer(&vha->timer);
276 vha->timer_active = 1;
1da177e4
LT		 277}
278
279static inline void
e315cd28 280qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 281{
a9083016 282 /* Currently used for 82XX only. */
7c3df132
SK		 283 if (vha->device_flags & DFLG_DEV_FAILED) {
284 ql_dbg(ql_dbg_timer, vha, 0x600d,
285 "Device in a failed state, returning.\n");
a9083016 286 return;
7c3df132 287 }
a9083016 288
e315cd28 289 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 290}
291
a824ebb3 292static __inline__ void
e315cd28 293qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 294{
e315cd28
AC		 295 del_timer_sync(&vha->timer);
296 vha->timer_active = 0;
1da177e4
LT		 297}
298
1da177e4
LT		 299static int qla2x00_do_dpc(void *data);
300
301static void qla2x00_rst_aen(scsi_qla_host_t *);
302
73208dfd
AC		 303static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
304 struct req_que **, struct rsp_que **);
e30d1756 305static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 306static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 307
1da177e4 308/* -------------------------------------------------------------------------- */
73208dfd
AC		 309static int qla2x00_alloc_queues(struct qla_hw_data *ha)
310{
7c3df132 311 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 312 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 313 GFP_KERNEL);
314 if (!ha->req_q_map) {
7c3df132
SK		 315 ql_log(ql_log_fatal, vha, 0x003b,
316 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 317 goto fail_req_map;
318 }
319
2afa19a9 320 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 321 GFP_KERNEL);
322 if (!ha->rsp_q_map) {
7c3df132
SK		 323 ql_log(ql_log_fatal, vha, 0x003c,
324 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 325 goto fail_rsp_map;
326 }
327 set_bit(0, ha->rsp_qid_map);
328 set_bit(0, ha->req_qid_map);
329 return 1;
330
331fail_rsp_map:
332 kfree(ha->req_q_map);
333 ha->req_q_map = NULL;
334fail_req_map:
335 return -ENOMEM;
336}
337
2afa19a9 338static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 339{
73208dfd
AC		 340 if (req && req->ring)
341 dma_free_coherent(&ha->pdev->dev,
342 (req->length + 1) * sizeof(request_t),
343 req->ring, req->dma);
344
345 kfree(req);
346 req = NULL;
347}
348
2afa19a9
AC		 349static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
350{
351 if (rsp && rsp->ring)
352 dma_free_coherent(&ha->pdev->dev,
353 (rsp->length + 1) * sizeof(response_t),
354 rsp->ring, rsp->dma);
355
356 kfree(rsp);
357 rsp = NULL;
358}
359
73208dfd
AC		 360static void qla2x00_free_queues(struct qla_hw_data *ha)
361{
362 struct req_que *req;
363 struct rsp_que *rsp;
364 int cnt;
365
2afa19a9 366 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 367 req = ha->req_q_map[cnt];
2afa19a9 368 qla2x00_free_req_que(ha, req);
73208dfd 369 }
73208dfd
AC		 370 kfree(ha->req_q_map);
371 ha->req_q_map = NULL;
2afa19a9
AC		 372
373 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
374 rsp = ha->rsp_q_map[cnt];
375 qla2x00_free_rsp_que(ha, rsp);
376 }
377 kfree(ha->rsp_q_map);
378 ha->rsp_q_map = NULL;
73208dfd
AC		 379}
380
68ca949c
AC		 381static int qla25xx_setup_mode(struct scsi_qla_host *vha)
382{
383 uint16_t options = 0;
384 int ques, req, ret;
385 struct qla_hw_data *ha = vha->hw;
386
7163ea81 387 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 388 ql_log(ql_log_warn, vha, 0x00d8,
389 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 390 goto fail;
391 }
68ca949c 392 if (ql2xmultique_tag) {
68ca949c
AC		 393 /* create a request queue for IO */
394 options |= BIT_7;
395 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
396 QLA_DEFAULT_QUE_QOS);
397 if (!req) {
7c3df132
SK		 398 ql_log(ql_log_warn, vha, 0x00e0,
399 "Failed to create request queue.\n");
68ca949c
AC		 400 goto fail;
401 }
278274d5 402 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 403 vha->req = ha->req_q_map[req];
404 options |= BIT_1;
405 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
406 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
407 if (!ret) {
7c3df132
SK		 408 ql_log(ql_log_warn, vha, 0x00e8,
409 "Failed to create response queue.\n");
68ca949c
AC		 410 goto fail2;
411 }
412 }
7163ea81 413 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 414 ql_dbg(ql_dbg_multiq, vha, 0xc007,
415 "CPU affinity mode enalbed, "
416 "no. of response queues:%d no. of request queues:%d.\n",
417 ha->max_rsp_queues, ha->max_req_queues);
418 ql_dbg(ql_dbg_init, vha, 0x00e9,
419 "CPU affinity mode enalbed, "
420 "no. of response queues:%d no. of request queues:%d.\n",
421 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 422 }
423 return 0;
424fail2:
425 qla25xx_delete_queues(vha);
7163ea81
AC		 426 destroy_workqueue(ha->wq);
427 ha->wq = NULL;
0cd33fcf 428 vha->req = ha->req_q_map[0];
68ca949c
AC		 429fail:
430 ha->mqenable = 0;
7163ea81
AC		 431 kfree(ha->req_q_map);
432 kfree(ha->rsp_q_map);
433 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 434 return 1;
435}
436
1da177e4 437static char *
e315cd28 438qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 439{
e315cd28 440 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 441 static char *pci_bus_modes[] = {
442 "33", "66", "100", "133",
443 };
444 uint16_t pci_bus;
445
446 strcpy(str, "PCI");
447 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
448 if (pci_bus) {
449 strcat(str, "-X (");
450 strcat(str, pci_bus_modes[pci_bus]);
451 } else {
452 pci_bus = (ha->pci_attr & BIT_8) >> 8;
453 strcat(str, " (");
454 strcat(str, pci_bus_modes[pci_bus]);
455 }
456 strcat(str, " MHz)");
457
458 return (str);
459}
460
fca29703 461static char *
e315cd28 462qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 463{
464 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 465 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 466 uint32_t pci_bus;
467 int pcie_reg;
468
469 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
470 if (pcie_reg) {
471 char lwstr[6];
472 uint16_t pcie_lstat, lspeed, lwidth;
473
474 pcie_reg += 0x12;
475 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
476 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
477 lwidth = (pcie_lstat &
478 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
479
480 strcpy(str, "PCIe (");
481 if (lspeed == 1)
c87a0d8c 482 strcat(str, "2.5GT/s ");
c3a2f0df 483 else if (lspeed == 2)
c87a0d8c 484 strcat(str, "5.0GT/s ");
fca29703
AV		 485 else
486 strcat(str, "<unknown> ");
487 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
488 strcat(str, lwstr);
489
490 return str;
491 }
492
493 strcpy(str, "PCI");
494 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
495 if (pci_bus == 0 || pci_bus == 8) {
496 strcat(str, " (");
497 strcat(str, pci_bus_modes[pci_bus >> 3]);
498 } else {
499 strcat(str, "-X ");
500 if (pci_bus & BIT_2)
501 strcat(str, "Mode 2");
502 else
503 strcat(str, "Mode 1");
504 strcat(str, " (");
505 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
506 }
507 strcat(str, " MHz)");
508
509 return str;
510}
511
e5f82ab8 512static char *
e315cd28 513qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 514{
515 char un_str[10];
e315cd28 516 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 517
1da177e4
LT		 518 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
519 ha->fw_minor_version,
520 ha->fw_subminor_version);
521
522 if (ha->fw_attributes & BIT_9) {
523 strcat(str, "FLX");
524 return (str);
525 }
526
527 switch (ha->fw_attributes & 0xFF) {
528 case 0x7:
529 strcat(str, "EF");
530 break;
531 case 0x17:
532 strcat(str, "TP");
533 break;
534 case 0x37:
535 strcat(str, "IP");
536 break;
537 case 0x77:
538 strcat(str, "VI");
539 break;
540 default:
541 sprintf(un_str, "(%x)", ha->fw_attributes);
542 strcat(str, un_str);
543 break;
544 }
545 if (ha->fw_attributes & 0x100)
546 strcat(str, "X");
547
548 return (str);
549}
550
e5f82ab8 551static char *
e315cd28 552qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 553{
e315cd28 554 struct qla_hw_data *ha = vha->hw;
f0883ac6 555
3a03eb79
AV		 556 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
557 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 558 return str;
fca29703
AV		 559}
560
9ba56b95
GM		 561void
562qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 563{
9ba56b95
GM		 564 srb_t *sp = (srb_t *)ptr;
565 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
566 struct qla_hw_data *ha = sp->fcport->vha->hw;
567 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 568
9ba56b95
GM		 569 if (sp->flags & SRB_DMA_VALID) {
570 scsi_dma_unmap(cmd);
571 sp->flags &= ~SRB_DMA_VALID;
7c3df132 572 }
fca29703 573
9ba56b95
GM		 574 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
575 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
576 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
577 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
578 }
579
580 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
581 /* List assured to be having elements */
582 qla2x00_clean_dsd_pool(ha, sp);
583 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
584 }
585
586 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
587 dma_pool_free(ha->dl_dma_pool, ctx,
588 ((struct crc_context *)ctx)->crc_ctx_dma);
589 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
590 }
591
592 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
593 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 594
9ba56b95
GM		 595 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
596 ctx1->fcp_cmnd_dma);
597 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
598 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
599 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
600 mempool_free(ctx1, ha->ctx_mempool);
601 ctx1 = NULL;
602 }
603
604 CMD_SP(cmd) = NULL;
605 mempool_free(sp, ha->srb_mempool);
606}
607
608static void
609qla2x00_sp_compl(void *data, void *ptr, int res)
610{
611 struct qla_hw_data *ha = (struct qla_hw_data *)data;
612 srb_t *sp = (srb_t *)ptr;
613 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
614
615 cmd->result = res;
616
617 if (atomic_read(&sp->ref_count) == 0) {
618 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
619 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
620 sp, GET_CMD_SP(sp));
621 if (ql2xextended_error_logging & ql_dbg_io)
622 BUG();
623 return;
624 }
625 if (!atomic_dec_and_test(&sp->ref_count))
626 return;
627
628 qla2x00_sp_free_dma(ha, sp);
629 cmd->scsi_done(cmd);
fca29703
AV		 630}
631
1da177e4 632static int
f5e3e40b 633qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 634{
134ae078 635 scsi_qla_host_t *vha = shost_priv(host);
fca29703 636 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 637 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 638 struct qla_hw_data *ha = vha->hw;
639 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 640 srb_t *sp;
641 int rval;
642
85880801 643 if (ha->flags.eeh_busy) {
7c3df132
SK		 644 if (ha->flags.pci_channel_io_perm_failure) {
645 ql_dbg(ql_dbg_io, vha, 0x3001,
646 "PCI Channel IO permanent failure, exiting "
647 "cmd=%p.\n", cmd);
b9b12f73 648 cmd->result = DID_NO_CONNECT << 16;
7c3df132
SK		 649 } else {
650 ql_dbg(ql_dbg_io, vha, 0x3002,
651 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 652 cmd->result = DID_REQUEUE << 16;
7c3df132 653 }
14e660e6
SJ		 654 goto qc24_fail_command;
655 }
656
19a7b4ae
JSEC		 657 rval = fc_remote_port_chkready(rport);
658 if (rval) {
659 cmd->result = rval;
7c3df132
SK		 660 ql_dbg(ql_dbg_io, vha, 0x3003,
661 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
662 cmd, rval);
fca29703
AV		 663 goto qc24_fail_command;
664 }
665
bad75002
AE		 666 if (!vha->flags.difdix_supported &&
667 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 668 ql_dbg(ql_dbg_io, vha, 0x3004,
669 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
670 cmd);
bad75002
AE		 671 cmd->result = DID_NO_CONNECT << 16;
672 goto qc24_fail_command;
673 }
aa651be8
CD		 674
675 if (!fcport) {
676 cmd->result = DID_NO_CONNECT << 16;
677 goto qc24_fail_command;
678 }
679
fca29703
AV		 680 if (atomic_read(&fcport->state) != FCS_ONLINE) {
681 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 682 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 683 ql_dbg(ql_dbg_io, vha, 0x3005,
684 "Returning DNC, fcport_state=%d loop_state=%d.\n",
685 atomic_read(&fcport->state),
686 atomic_read(&base_vha->loop_state));
fca29703
AV		 687 cmd->result = DID_NO_CONNECT << 16;
688 goto qc24_fail_command;
689 }
7b594131 690 goto qc24_target_busy;
fca29703
AV		 691 }
692
9ba56b95 693 sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC);
fca29703 694 if (!sp)
f5e3e40b 695 goto qc24_host_busy;
fca29703 696
9ba56b95
GM		 697 sp->u.scmd.cmd = cmd;
698 sp->type = SRB_SCSI_CMD;
699 atomic_set(&sp->ref_count, 1);
700 CMD_SP(cmd) = (void *)sp;
701 sp->free = qla2x00_sp_free_dma;
702 sp->done = qla2x00_sp_compl;
703
e315cd28 704 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 705 if (rval != QLA_SUCCESS) {
706 ql_dbg(ql_dbg_io, vha, 0x3013,
707 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 708 goto qc24_host_busy_free_sp;
7c3df132 709 }
fca29703 710
fca29703
AV		 711 return 0;
712
713qc24_host_busy_free_sp:
9ba56b95 714 qla2x00_sp_free_dma(ha, sp);
fca29703 715
f5e3e40b 716qc24_host_busy:
fca29703
AV		 717 return SCSI_MLQUEUE_HOST_BUSY;
718
7b594131
MC		 719qc24_target_busy:
720 return SCSI_MLQUEUE_TARGET_BUSY;
721
fca29703 722qc24_fail_command:
f5e3e40b 723 cmd->scsi_done(cmd);
fca29703
AV		 724
725 return 0;
726}
727
1da177e4
LT		 728/*
729 * qla2x00_eh_wait_on_command
730 * Waits for the command to be returned by the Firmware for some
731 * max time.
732 *
733 * Input:
1da177e4 734 * cmd = Scsi Command to wait on.
1da177e4
LT		 735 *
736 * Return:
737 * Not Found : 0
738 * Found : 1
739 */
740static int
e315cd28 741qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 742{
fe74c71f
AV		 743#define ABORT_POLLING_PERIOD 1000
744#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 745 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 746 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
747 struct qla_hw_data *ha = vha->hw;
f4f051eb 748 int ret = QLA_SUCCESS;
1da177e4 749
85880801 750 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 751 ql_dbg(ql_dbg_taskm, vha, 0x8005,
752 "Return:eh_wait.\n");
85880801
AV		 753 return ret;
754 }
755
d970432c 756 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 757 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 758 }
759 if (CMD_SP(cmd))
760 ret = QLA_FUNCTION_FAILED;
1da177e4 761
f4f051eb 762 return ret;
1da177e4
LT		 763}
764
765/*
766 * qla2x00_wait_for_hba_online
fa2a1ce5 767 * Wait till the HBA is online after going through
1da177e4
LT		 768 * <= MAX_RETRIES_OF_ISP_ABORT or
769 * finally HBA is disabled ie marked offline
770 *
771 * Input:
772 * ha - pointer to host adapter structure
fa2a1ce5
AV		 773 *
774 * Note:
1da177e4
LT		 775 * Does context switching-Release SPIN_LOCK
776 * (if any) before calling this routine.
777 *
778 * Return:
779 * Success (Adapter is online) : 0
780 * Failed (Adapter is offline/disabled) : 1
781 */
854165f4 782int
e315cd28 783qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 784{
fca29703
AV		 785 int return_status;
786 unsigned long wait_online;
e315cd28
AC		 787 struct qla_hw_data *ha = vha->hw;
788 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 789
fa2a1ce5 790 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 791 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
792 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
793 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
794 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 795
796 msleep(1000);
797 }
e315cd28 798 if (base_vha->flags.online)
fa2a1ce5 799 return_status = QLA_SUCCESS;
1da177e4
LT		 800 else
801 return_status = QLA_FUNCTION_FAILED;
802
1da177e4
LT		 803 return (return_status);
804}
805
86fbee86
LC		 806/*
807 * qla2x00_wait_for_reset_ready
808 * Wait till the HBA is online after going through
809 * <= MAX_RETRIES_OF_ISP_ABORT or
810 * finally HBA is disabled ie marked offline or flash
811 * operations are in progress.
812 *
813 * Input:
814 * ha - pointer to host adapter structure
815 *
816 * Note:
817 * Does context switching-Release SPIN_LOCK
818 * (if any) before calling this routine.
819 *
820 * Return:
821 * Success (Adapter is online/no flash ops) : 0
822 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
823 */
3dbe756a 824static int
86fbee86
LC		 825qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
826{
827 int return_status;
828 unsigned long wait_online;
829 struct qla_hw_data *ha = vha->hw;
830 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
831
832 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
833 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
834 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
835 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
836 ha->optrom_state != QLA_SWAITING ||
837 ha->dpc_active) && time_before(jiffies, wait_online))
838 msleep(1000);
839
840 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
841 return_status = QLA_SUCCESS;
842 else
843 return_status = QLA_FUNCTION_FAILED;
844
7c3df132
SK		 845 ql_dbg(ql_dbg_taskm, vha, 0x8019,
846 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 847
848 return return_status;
849}
850
2533cf67
LC		 851int
852qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
853{
854 int return_status;
855 unsigned long wait_reset;
856 struct qla_hw_data *ha = vha->hw;
857 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
858
859 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
860 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
861 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
862 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
863 ha->dpc_active) && time_before(jiffies, wait_reset)) {
864
865 msleep(1000);
866
867 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
868 ha->flags.chip_reset_done)
869 break;
870 }
871 if (ha->flags.chip_reset_done)
872 return_status = QLA_SUCCESS;
873 else
874 return_status = QLA_FUNCTION_FAILED;
875
876 return return_status;
877}
878
083a469d
GM		 879static void
880sp_get(struct srb *sp)
881{
882 atomic_inc(&sp->ref_count);
883}
884
1da177e4
LT		 885/**************************************************************************
886* qla2xxx_eh_abort
887*
888* Description:
889* The abort function will abort the specified command.
890*
891* Input:
892* cmd = Linux SCSI command packet to be aborted.
893*
894* Returns:
895* Either SUCCESS or FAILED.
896*
897* Note:
2ea00202 898* Only return FAILED if command not returned by firmware.
1da177e4 899**************************************************************************/
e5f82ab8 900static int
1da177e4
LT		 901qla2xxx_eh_abort(struct scsi_cmnd *cmd)
902{
e315cd28 903 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 904 srb_t *sp;
4e98d3b8 905 int ret;
f4f051eb 906 unsigned int id, lun;
18e144d3 907 unsigned long flags;
2ea00202 908 int wait = 0;
e315cd28 909 struct qla_hw_data *ha = vha->hw;
1da177e4 910
f4f051eb 911 if (!CMD_SP(cmd))
2ea00202 912 return SUCCESS;
1da177e4 913
4e98d3b8
AV		 914 ret = fc_block_scsi_eh(cmd);
915 if (ret != 0)
916 return ret;
917 ret = SUCCESS;
918
f4f051eb
AV		 919 id = cmd->device->id;
920 lun = cmd->device->lun;
1da177e4 921
e315cd28 922 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 923 sp = (srb_t *) CMD_SP(cmd);
924 if (!sp) {
925 spin_unlock_irqrestore(&ha->hardware_lock, flags);
926 return SUCCESS;
927 }
1da177e4 928
7c3df132 929 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 930 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
931 vha->host_no, id, lun, sp, cmd);
17d98630 932
170babc3
MC		 933 /* Get a reference to the sp and drop the lock.*/
934 sp_get(sp);
083a469d 935
e315cd28 936 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 937 if (ha->isp_ops->abort_command(sp)) {
a55aac79 938 ret = FAILED;
7c3df132 939 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 940 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 941 } else {
7c3df132 942 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 943 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 944 wait = 1;
945 }
75942064
SK		 946
947 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 948 sp->done(ha, sp, 0);
75942064 949 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 950
bc91ade9
CD		 951 /* Did the command return during mailbox execution? */
952 if (ret == FAILED && !CMD_SP(cmd))
953 ret = SUCCESS;
954
f4f051eb 955 /* Wait for the command to be returned. */
2ea00202 956 if (wait) {
e315cd28 957 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 958 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 959 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 960 ret = FAILED;
f4f051eb 961 }
1da177e4 962 }
1da177e4 963
7c3df132 964 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 965 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
966 vha->host_no, id, lun, wait, ret);
1da177e4 967
f4f051eb
AV		 968 return ret;
969}
1da177e4 970
4d78c973 971int
e315cd28 972qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 973 unsigned int l, enum nexus_wait_type type)
f4f051eb 974{
17d98630 975 int cnt, match, status;
18e144d3 976 unsigned long flags;
e315cd28 977 struct qla_hw_data *ha = vha->hw;
73208dfd 978 struct req_que *req;
4d78c973 979 srb_t *sp;
9ba56b95 980 struct scsi_cmnd *cmd;
1da177e4 981
523ec773 982 status = QLA_SUCCESS;
17d98630 983
e315cd28 984 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 985 req = vha->req;
17d98630
AC		 986 for (cnt = 1; status == QLA_SUCCESS &&
987 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
988 sp = req->outstanding_cmds[cnt];
989 if (!sp)
523ec773 990 continue;
9ba56b95 991 if (sp->type != SRB_SCSI_CMD)
cf53b069 992 continue;
17d98630
AC		 993 if (vha->vp_idx != sp->fcport->vha->vp_idx)
994 continue;
995 match = 0;
9ba56b95 996 cmd = GET_CMD_SP(sp);
17d98630
AC		 997 switch (type) {
998 case WAIT_HOST:
999 match = 1;
1000 break;
1001 case WAIT_TARGET:
9ba56b95 1002 match = cmd->device->id == t;
17d98630
AC		 1003 break;
1004 case WAIT_LUN:
9ba56b95
GM		 1005 match = (cmd->device->id == t &&
1006 cmd->device->lun == l);
17d98630 1007 break;
73208dfd 1008 }
17d98630
AC		 1009 if (!match)
1010 continue;
1011
1012 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1013 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1014 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1015 }
e315cd28 1016 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1017
1018 return status;
1da177e4
LT		 1019}
1020
523ec773
AV		 1021static char *reset_errors[] = {
1022 "HBA not online",
1023 "HBA not ready",
1024 "Task management failed",
1025 "Waiting for command completions",
1026};
1da177e4 1027
e5f82ab8 1028static int
523ec773 1029__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1030 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1031{
e315cd28 1032 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1033 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1034 int err;
1da177e4 1035
7c3df132 1036 if (!fcport) {
523ec773 1037 return FAILED;
7c3df132 1038 }
1da177e4 1039
4e98d3b8
AV		 1040 err = fc_block_scsi_eh(cmd);
1041 if (err != 0)
1042 return err;
1043
7c3df132 1044 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1045 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1046 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1047
523ec773 1048 err = 0;
7c3df132
SK		 1049 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1050 ql_log(ql_log_warn, vha, 0x800a,
1051 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1052 goto eh_reset_failed;
7c3df132 1053 }
523ec773 1054 err = 2;
2afa19a9 1055 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1056 != QLA_SUCCESS) {
1057 ql_log(ql_log_warn, vha, 0x800c,
1058 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1059 goto eh_reset_failed;
7c3df132 1060 }
523ec773 1061 err = 3;
e315cd28 1062 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1063 cmd->device->lun, type) != QLA_SUCCESS) {
1064 ql_log(ql_log_warn, vha, 0x800d,
1065 "wait for peding cmds failed for cmd=%p.\n", cmd);
523ec773 1066 goto eh_reset_failed;
7c3df132 1067 }
523ec773 1068
7c3df132 1069 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1070 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1071 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1072
1073 return SUCCESS;
1074
4d78c973 1075eh_reset_failed:
7c3df132 1076 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1077 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1078 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1079 cmd);
523ec773
AV		 1080 return FAILED;
1081}
1da177e4 1082
523ec773
AV		 1083static int
1084qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1085{
e315cd28
AC		 1086 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1087 struct qla_hw_data *ha = vha->hw;
1da177e4 1088
523ec773
AV		 1089 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1090 ha->isp_ops->lun_reset);
1da177e4
LT		 1091}
1092
1da177e4 1093static int
523ec773 1094qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1095{
e315cd28
AC		 1096 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1097 struct qla_hw_data *ha = vha->hw;
1da177e4 1098
523ec773
AV		 1099 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1100 ha->isp_ops->target_reset);
1da177e4
LT		 1101}
1102
1da177e4
LT		 1103/**************************************************************************
1104* qla2xxx_eh_bus_reset
1105*
1106* Description:
1107* The bus reset function will reset the bus and abort any executing
1108* commands.
1109*
1110* Input:
1111* cmd = Linux SCSI command packet of the command that cause the
1112* bus reset.
1113*
1114* Returns:
1115* SUCCESS/FAILURE (defined as macro in scsi.h).
1116*
1117**************************************************************************/
e5f82ab8 1118static int
1da177e4
LT		 1119qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1120{
e315cd28 1121 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1122 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1123 int ret = FAILED;
f4f051eb 1124 unsigned int id, lun;
f4f051eb 1125
f4f051eb
AV		 1126 id = cmd->device->id;
1127 lun = cmd->device->lun;
1da177e4 1128
7c3df132 1129 if (!fcport) {
f4f051eb 1130 return ret;
7c3df132 1131 }
1da177e4 1132
4e98d3b8
AV		 1133 ret = fc_block_scsi_eh(cmd);
1134 if (ret != 0)
1135 return ret;
1136 ret = FAILED;
1137
7c3df132 1138 ql_log(ql_log_info, vha, 0x8012,
cfb0919c 1139 "BUS RESET ISSUED nexus=%ld:%d%d.\n", vha->host_no, id, lun);
1da177e4 1140
e315cd28 1141 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1142 ql_log(ql_log_fatal, vha, 0x8013,
1143 "Wait for hba online failed board disabled.\n");
f4f051eb 1144 goto eh_bus_reset_done;
1da177e4
LT		 1145 }
1146
ad537689
SK		 1147 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1148 ret = SUCCESS;
1149
f4f051eb
AV		 1150 if (ret == FAILED)
1151 goto eh_bus_reset_done;
1da177e4 1152
9a41a62b 1153 /* Flush outstanding commands. */
4d78c973 1154 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1155 QLA_SUCCESS) {
1156 ql_log(ql_log_warn, vha, 0x8014,
1157 "Wait for pending commands failed.\n");
9a41a62b 1158 ret = FAILED;
7c3df132 1159 }
1da177e4 1160
f4f051eb 1161eh_bus_reset_done:
7c3df132 1162 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c
CD		 1163 "BUS RESET %s nexus=%ld:%d:%d.\n",
1164 (ret == FAILED) ? "FAILED" : "SUCCEDED", vha->host_no, id, lun);
1da177e4 1165
f4f051eb 1166 return ret;
1da177e4
LT		 1167}
1168
1169/**************************************************************************
1170* qla2xxx_eh_host_reset
1171*
1172* Description:
1173* The reset function will reset the Adapter.
1174*
1175* Input:
1176* cmd = Linux SCSI command packet of the command that cause the
1177* adapter reset.
1178*
1179* Returns:
1180* Either SUCCESS or FAILED.
1181*
1182* Note:
1183**************************************************************************/
e5f82ab8 1184static int
1da177e4
LT		 1185qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1186{
e315cd28 1187 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1188 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1189 int ret = FAILED;
f4f051eb 1190 unsigned int id, lun;
e315cd28 1191 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1192
f4f051eb
AV		 1193 id = cmd->device->id;
1194 lun = cmd->device->lun;
f4f051eb 1195
7c3df132 1196 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1197 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1198
86fbee86 1199 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1200 goto eh_host_reset_lock;
1da177e4 1201
e315cd28
AC		 1202 if (vha != base_vha) {
1203 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1204 goto eh_host_reset_lock;
e315cd28 1205 } else {
a9083016
GM		 1206 if (IS_QLA82XX(vha->hw)) {
1207 if (!qla82xx_fcoe_ctx_reset(vha)) {
1208 /* Ctx reset success */
1209 ret = SUCCESS;
1210 goto eh_host_reset_lock;
1211 }
1212 /* fall thru if ctx reset failed */
1213 }
68ca949c
AC		 1214 if (ha->wq)
1215 flush_workqueue(ha->wq);
1216
e315cd28 1217 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1218 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1219 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1220 /* failed. schedule dpc to try */
1221 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1222
7c3df132
SK		 1223 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1224 ql_log(ql_log_warn, vha, 0x802a,
1225 "wait for hba online failed.\n");
e315cd28 1226 goto eh_host_reset_lock;
7c3df132 1227 }
e315cd28
AC		 1228 }
1229 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1230 }
1da177e4 1231
e315cd28 1232 /* Waiting for command to be returned to OS.*/
4d78c973 1233 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1234 QLA_SUCCESS)
f4f051eb 1235 ret = SUCCESS;
1da177e4 1236
f4f051eb 1237eh_host_reset_lock:
cfb0919c
CD		 1238 ql_log(ql_log_info, vha, 0x8017,
1239 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1240 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1241
f4f051eb
AV		 1242 return ret;
1243}
1da177e4
LT		 1244
1245/*
1246* qla2x00_loop_reset
1247* Issue loop reset.
1248*
1249* Input:
1250* ha = adapter block pointer.
1251*
1252* Returns:
1253* 0 = success
1254*/
a4722cf2 1255int
e315cd28 1256qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1257{
0c8c39af 1258 int ret;
bdf79621 1259 struct fc_port *fcport;
e315cd28 1260 struct qla_hw_data *ha = vha->hw;
1da177e4 1261
f4c496c1 1262 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1263 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1264 if (fcport->port_type != FCT_TARGET)
1265 continue;
1266
1267 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1268 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1269 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1270 "Bus Reset failed: Target Reset=%d "
1271 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1272 }
1273 }
1274 }
1275
6246b8a1 1276 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
e315cd28 1277 ret = qla2x00_full_login_lip(vha);
0c8c39af 1278 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1279 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1280 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1281 }
1282 atomic_set(&vha->loop_state, LOOP_DOWN);
1283 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1284 qla2x00_mark_all_devices_lost(vha, 0);
0c8c39af
AV		 1285 }
1286
0d6e61bc 1287 if (ha->flags.enable_lip_reset) {
e315cd28 1288 ret = qla2x00_lip_reset(vha);
ad537689 1289 if (ret != QLA_SUCCESS)
7c3df132
SK		 1290 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1291 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1292 }
1293
1da177e4 1294 /* Issue marker command only when we are going to start the I/O */
e315cd28 1295 vha->marker_needed = 1;
1da177e4 1296
0c8c39af 1297 return QLA_SUCCESS;
1da177e4
LT		 1298}
1299
df4bf0bb 1300void
e315cd28 1301qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1302{
73208dfd 1303 int que, cnt;
df4bf0bb
AV		 1304 unsigned long flags;
1305 srb_t *sp;
e315cd28 1306 struct qla_hw_data *ha = vha->hw;
73208dfd 1307 struct req_que *req;
df4bf0bb
AV		 1308
1309 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1310 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1311 req = ha->req_q_map[que];
73208dfd
AC		 1312 if (!req)
1313 continue;
1314 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1315 sp = req->outstanding_cmds[cnt];
e612d465 1316 if (sp) {
73208dfd 1317 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1318 sp->done(vha, sp, res);
73208dfd 1319 }
df4bf0bb
AV		 1320 }
1321 }
1322 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1323}
1324
f4f051eb
AV		 1325static int
1326qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1327{
bdf79621 1328 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1329
19a7b4ae 1330 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1331 return -ENXIO;
bdf79621 1332
19a7b4ae 1333 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1334
f4f051eb
AV		 1335 return 0;
1336}
1da177e4 1337
f4f051eb
AV		 1338static int
1339qla2xxx_slave_configure(struct scsi_device *sdev)
1340{
e315cd28 1341 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1342 struct req_que *req = vha->req;
8482e118 1343
f4f051eb 1344 if (sdev->tagged_supported)
73208dfd 1345 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1346 else
73208dfd 1347 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1348 return 0;
1349}
1da177e4 1350
f4f051eb
AV		 1351static void
1352qla2xxx_slave_destroy(struct scsi_device *sdev)
1353{
1354 sdev->hostdata = NULL;
1da177e4
LT		 1355}
1356
c45dd305
GM		 1357static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1358{
1359 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1360
1361 if (!scsi_track_queue_full(sdev, qdepth))
1362 return;
1363
7c3df132 1364 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1365 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1366 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1367}
1368
1369static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1370{
1371 fc_port_t *fcport = sdev->hostdata;
1372 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1373 struct req_que *req = NULL;
1374
1375 req = vha->req;
1376 if (!req)
1377 return;
1378
1379 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1380 return;
1381
1382 if (sdev->ordered_tags)
1383 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1384 else
1385 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1386
7c3df132 1387 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1388 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1389 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1390}
1391
ce7e4af7 1392static int
e881a172 1393qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1394{
c45dd305
GM		 1395 switch (reason) {
1396 case SCSI_QDEPTH_DEFAULT:
1397 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1398 break;
1399 case SCSI_QDEPTH_QFULL:
1400 qla2x00_handle_queue_full(sdev, qdepth);
1401 break;
1402 case SCSI_QDEPTH_RAMP_UP:
1403 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1404 break;
1405 default:
08002af2 1406 return -EOPNOTSUPP;
c45dd305 1407 }
e881a172 1408
ce7e4af7
AV		 1409 return sdev->queue_depth;
1410}
1411
1412static int
1413qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1414{
1415 if (sdev->tagged_supported) {
1416 scsi_set_tag_type(sdev, tag_type);
1417 if (tag_type)
1418 scsi_activate_tcq(sdev, sdev->queue_depth);
1419 else
1420 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1421 } else
1422 tag_type = 0;
1423
1424 return tag_type;
1425}
1426
1da177e4
LT		 1427/**
1428 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1429 * @ha: HA context
1430 *
1431 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1432 * supported addressing method.
1433 */
1434static void
53303c42 1435qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1436{
7524f9b9 1437 /* Assume a 32bit DMA mask. */
1da177e4 1438 ha->flags.enable_64bit_addressing = 0;
1da177e4 1439
6a35528a 1440 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1441 /* Any upper-dword bits set? */
1442 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1443 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1444 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1445 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1446 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1447 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1448 return;
1da177e4 1449 }
1da177e4 1450 }
7524f9b9 1451
284901a9
YH		 1452 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1453 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1454}
1455
fd34f556 1456static void
e315cd28 1457qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1458{
1459 unsigned long flags = 0;
1460 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1461
1462 spin_lock_irqsave(&ha->hardware_lock, flags);
1463 ha->interrupts_on = 1;
1464 /* enable risc and host interrupts */
1465 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1466 RD_REG_WORD(&reg->ictrl);
1467 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1468
1469}
1470
1471static void
e315cd28 1472qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1473{
1474 unsigned long flags = 0;
1475 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1476
1477 spin_lock_irqsave(&ha->hardware_lock, flags);
1478 ha->interrupts_on = 0;
1479 /* disable risc and host interrupts */
1480 WRT_REG_WORD(&reg->ictrl, 0);
1481 RD_REG_WORD(&reg->ictrl);
1482 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1483}
1484
1485static void
e315cd28 1486qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1487{
1488 unsigned long flags = 0;
1489 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1490
1491 spin_lock_irqsave(&ha->hardware_lock, flags);
1492 ha->interrupts_on = 1;
1493 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1494 RD_REG_DWORD(&reg->ictrl);
1495 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1496}
1497
1498static void
e315cd28 1499qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1500{
1501 unsigned long flags = 0;
1502 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1503
124f85e6
AV		 1504 if (IS_NOPOLLING_TYPE(ha))
1505 return;
fd34f556
AV		 1506 spin_lock_irqsave(&ha->hardware_lock, flags);
1507 ha->interrupts_on = 0;
1508 WRT_REG_DWORD(&reg->ictrl, 0);
1509 RD_REG_DWORD(&reg->ictrl);
1510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1511}
1512
706f457d
GM		 1513static int
1514qla2x00_iospace_config(struct qla_hw_data *ha)
1515{
1516 resource_size_t pio;
1517 uint16_t msix;
1518 int cpus;
1519
706f457d
GM		 1520 if (pci_request_selected_regions(ha->pdev, ha->bars,
1521 QLA2XXX_DRIVER_NAME)) {
1522 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1523 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1524 pci_name(ha->pdev));
1525 goto iospace_error_exit;
1526 }
1527 if (!(ha->bars & 1))
1528 goto skip_pio;
1529
1530 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1531 pio = pci_resource_start(ha->pdev, 0);
1532 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1533 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1534 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1535 "Invalid pci I/O region size (%s).\n",
1536 pci_name(ha->pdev));
1537 pio = 0;
1538 }
1539 } else {
1540 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1541 "Region #0 no a PIO resource (%s).\n",
1542 pci_name(ha->pdev));
1543 pio = 0;
1544 }
1545 ha->pio_address = pio;
1546 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1547 "PIO address=%llu.\n",
1548 (unsigned long long)ha->pio_address);
1549
1550skip_pio:
1551 /* Use MMIO operations for all accesses. */
1552 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1553 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1554 "Region #1 not an MMIO resource (%s), aborting.\n",
1555 pci_name(ha->pdev));
1556 goto iospace_error_exit;
1557 }
1558 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1559 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1560 "Invalid PCI mem region size (%s), aborting.\n",
1561 pci_name(ha->pdev));
1562 goto iospace_error_exit;
1563 }
1564
1565 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1566 if (!ha->iobase) {
1567 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1568 "Cannot remap MMIO (%s), aborting.\n",
1569 pci_name(ha->pdev));
1570 goto iospace_error_exit;
1571 }
1572
1573 /* Determine queue resources */
1574 ha->max_req_queues = ha->max_rsp_queues = 1;
1575 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1576 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1577 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1578 goto mqiobase_exit;
1579
1580 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1581 pci_resource_len(ha->pdev, 3));
1582 if (ha->mqiobase) {
1583 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1584 "MQIO Base=%p.\n", ha->mqiobase);
1585 /* Read MSIX vector size of the board */
1586 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1587 ha->msix_count = msix;
1588 /* Max queues are bounded by available msix vectors */
1589 /* queue 0 uses two msix vectors */
1590 if (ql2xmultique_tag) {
1591 cpus = num_online_cpus();
1592 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1593 (cpus + 1) : (ha->msix_count - 1);
1594 ha->max_req_queues = 2;
1595 } else if (ql2xmaxqueues > 1) {
1596 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1597 QLA_MQ_SIZE : ql2xmaxqueues;
1598 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1599 "QoS mode set, max no of request queues:%d.\n",
1600 ha->max_req_queues);
1601 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1602 "QoS mode set, max no of request queues:%d.\n",
1603 ha->max_req_queues);
1604 }
1605 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1606 "MSI-X vector count: %d.\n", msix);
1607 } else
1608 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1609 "BAR 3 not enabled.\n");
1610
1611mqiobase_exit:
1612 ha->msix_count = ha->max_rsp_queues + 1;
1613 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1614 "MSIX Count:%d.\n", ha->msix_count);
1615 return (0);
1616
1617iospace_error_exit:
1618 return (-ENOMEM);
1619}
1620
1621
6246b8a1
GM		 1622static int
1623qla83xx_iospace_config(struct qla_hw_data *ha)
1624{
1625 uint16_t msix;
1626 int cpus;
1627
1628 if (pci_request_selected_regions(ha->pdev, ha->bars,
1629 QLA2XXX_DRIVER_NAME)) {
1630 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1631 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1632 pci_name(ha->pdev));
1633
1634 goto iospace_error_exit;
1635 }
1636
1637 /* Use MMIO operations for all accesses. */
1638 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1639 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1640 "Invalid pci I/O region size (%s).\n",
1641 pci_name(ha->pdev));
1642 goto iospace_error_exit;
1643 }
1644 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1645 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1646 "Invalid PCI mem region size (%s), aborting\n",
1647 pci_name(ha->pdev));
1648 goto iospace_error_exit;
1649 }
1650
1651 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1652 if (!ha->iobase) {
1653 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1654 "Cannot remap MMIO (%s), aborting.\n",
1655 pci_name(ha->pdev));
1656 goto iospace_error_exit;
1657 }
1658
1659 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1660 /* 83XX 26XX always use MQ type access for queues
1661 * - mbar 2, a.k.a region 4 */
1662 ha->max_req_queues = ha->max_rsp_queues = 1;
1663 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1664 pci_resource_len(ha->pdev, 4));
1665
1666 if (!ha->mqiobase) {
1667 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1668 "BAR2/region4 not enabled\n");
1669 goto mqiobase_exit;
1670 }
1671
1672 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1673 pci_resource_len(ha->pdev, 2));
1674 if (ha->msixbase) {
1675 /* Read MSIX vector size of the board */
1676 pci_read_config_word(ha->pdev,
1677 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1678 ha->msix_count = msix;
1679 /* Max queues are bounded by available msix vectors */
1680 /* queue 0 uses two msix vectors */
1681 if (ql2xmultique_tag) {
1682 cpus = num_online_cpus();
1683 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1684 (cpus + 1) : (ha->msix_count - 1);
1685 ha->max_req_queues = 2;
1686 } else if (ql2xmaxqueues > 1) {
1687 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1688 QLA_MQ_SIZE : ql2xmaxqueues;
1689 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1690 "QoS mode set, max no of request queues:%d.\n",
1691 ha->max_req_queues);
1692 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1693 "QoS mode set, max no of request queues:%d.\n",
1694 ha->max_req_queues);
1695 }
1696 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1697 "MSI-X vector count: %d.\n", msix);
1698 } else
1699 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1700 "BAR 1 not enabled.\n");
1701
1702mqiobase_exit:
1703 ha->msix_count = ha->max_rsp_queues + 1;
1704 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1705 "MSIX Count:%d.\n", ha->msix_count);
1706 return 0;
1707
1708iospace_error_exit:
1709 return -ENOMEM;
1710}
1711
fd34f556
AV		 1712static struct isp_operations qla2100_isp_ops = {
1713 .pci_config = qla2100_pci_config,
1714 .reset_chip = qla2x00_reset_chip,
1715 .chip_diag = qla2x00_chip_diag,
1716 .config_rings = qla2x00_config_rings,
1717 .reset_adapter = qla2x00_reset_adapter,
1718 .nvram_config = qla2x00_nvram_config,
1719 .update_fw_options = qla2x00_update_fw_options,
1720 .load_risc = qla2x00_load_risc,
1721 .pci_info_str = qla2x00_pci_info_str,
1722 .fw_version_str = qla2x00_fw_version_str,
1723 .intr_handler = qla2100_intr_handler,
1724 .enable_intrs = qla2x00_enable_intrs,
1725 .disable_intrs = qla2x00_disable_intrs,
1726 .abort_command = qla2x00_abort_command,
523ec773
AV		 1727 .target_reset = qla2x00_abort_target,
1728 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1729 .fabric_login = qla2x00_login_fabric,
1730 .fabric_logout = qla2x00_fabric_logout,
1731 .calc_req_entries = qla2x00_calc_iocbs_32,
1732 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1733 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1734 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1735 .read_nvram = qla2x00_read_nvram_data,
1736 .write_nvram = qla2x00_write_nvram_data,
1737 .fw_dump = qla2100_fw_dump,
1738 .beacon_on = NULL,
1739 .beacon_off = NULL,
1740 .beacon_blink = NULL,
1741 .read_optrom = qla2x00_read_optrom_data,
1742 .write_optrom = qla2x00_write_optrom_data,
1743 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1744 .start_scsi = qla2x00_start_scsi,
a9083016 1745 .abort_isp = qla2x00_abort_isp,
706f457d 1746 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1747};
1748
1749static struct isp_operations qla2300_isp_ops = {
1750 .pci_config = qla2300_pci_config,
1751 .reset_chip = qla2x00_reset_chip,
1752 .chip_diag = qla2x00_chip_diag,
1753 .config_rings = qla2x00_config_rings,
1754 .reset_adapter = qla2x00_reset_adapter,
1755 .nvram_config = qla2x00_nvram_config,
1756 .update_fw_options = qla2x00_update_fw_options,
1757 .load_risc = qla2x00_load_risc,
1758 .pci_info_str = qla2x00_pci_info_str,
1759 .fw_version_str = qla2x00_fw_version_str,
1760 .intr_handler = qla2300_intr_handler,
1761 .enable_intrs = qla2x00_enable_intrs,
1762 .disable_intrs = qla2x00_disable_intrs,
1763 .abort_command = qla2x00_abort_command,
523ec773
AV		 1764 .target_reset = qla2x00_abort_target,
1765 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1766 .fabric_login = qla2x00_login_fabric,
1767 .fabric_logout = qla2x00_fabric_logout,
1768 .calc_req_entries = qla2x00_calc_iocbs_32,
1769 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1770 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1771 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1772 .read_nvram = qla2x00_read_nvram_data,
1773 .write_nvram = qla2x00_write_nvram_data,
1774 .fw_dump = qla2300_fw_dump,
1775 .beacon_on = qla2x00_beacon_on,
1776 .beacon_off = qla2x00_beacon_off,
1777 .beacon_blink = qla2x00_beacon_blink,
1778 .read_optrom = qla2x00_read_optrom_data,
1779 .write_optrom = qla2x00_write_optrom_data,
1780 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1781 .start_scsi = qla2x00_start_scsi,
a9083016 1782 .abort_isp = qla2x00_abort_isp,
706f457d 1783 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1784};
1785
1786static struct isp_operations qla24xx_isp_ops = {
1787 .pci_config = qla24xx_pci_config,
1788 .reset_chip = qla24xx_reset_chip,
1789 .chip_diag = qla24xx_chip_diag,
1790 .config_rings = qla24xx_config_rings,
1791 .reset_adapter = qla24xx_reset_adapter,
1792 .nvram_config = qla24xx_nvram_config,
1793 .update_fw_options = qla24xx_update_fw_options,
1794 .load_risc = qla24xx_load_risc,
1795 .pci_info_str = qla24xx_pci_info_str,
1796 .fw_version_str = qla24xx_fw_version_str,
1797 .intr_handler = qla24xx_intr_handler,
1798 .enable_intrs = qla24xx_enable_intrs,
1799 .disable_intrs = qla24xx_disable_intrs,
1800 .abort_command = qla24xx_abort_command,
523ec773
AV		 1801 .target_reset = qla24xx_abort_target,
1802 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1803 .fabric_login = qla24xx_login_fabric,
1804 .fabric_logout = qla24xx_fabric_logout,
1805 .calc_req_entries = NULL,
1806 .build_iocbs = NULL,
1807 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1808 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1809 .read_nvram = qla24xx_read_nvram_data,
1810 .write_nvram = qla24xx_write_nvram_data,
1811 .fw_dump = qla24xx_fw_dump,
1812 .beacon_on = qla24xx_beacon_on,
1813 .beacon_off = qla24xx_beacon_off,
1814 .beacon_blink = qla24xx_beacon_blink,
1815 .read_optrom = qla24xx_read_optrom_data,
1816 .write_optrom = qla24xx_write_optrom_data,
1817 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1818 .start_scsi = qla24xx_start_scsi,
a9083016 1819 .abort_isp = qla2x00_abort_isp,
706f457d 1820 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1821};
1822
c3a2f0df
AV		 1823static struct isp_operations qla25xx_isp_ops = {
1824 .pci_config = qla25xx_pci_config,
1825 .reset_chip = qla24xx_reset_chip,
1826 .chip_diag = qla24xx_chip_diag,
1827 .config_rings = qla24xx_config_rings,
1828 .reset_adapter = qla24xx_reset_adapter,
1829 .nvram_config = qla24xx_nvram_config,
1830 .update_fw_options = qla24xx_update_fw_options,
1831 .load_risc = qla24xx_load_risc,
1832 .pci_info_str = qla24xx_pci_info_str,
1833 .fw_version_str = qla24xx_fw_version_str,
1834 .intr_handler = qla24xx_intr_handler,
1835 .enable_intrs = qla24xx_enable_intrs,
1836 .disable_intrs = qla24xx_disable_intrs,
1837 .abort_command = qla24xx_abort_command,
523ec773
AV		 1838 .target_reset = qla24xx_abort_target,
1839 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1840 .fabric_login = qla24xx_login_fabric,
1841 .fabric_logout = qla24xx_fabric_logout,
1842 .calc_req_entries = NULL,
1843 .build_iocbs = NULL,
1844 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1845 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1846 .read_nvram = qla25xx_read_nvram_data,
1847 .write_nvram = qla25xx_write_nvram_data,
1848 .fw_dump = qla25xx_fw_dump,
1849 .beacon_on = qla24xx_beacon_on,
1850 .beacon_off = qla24xx_beacon_off,
1851 .beacon_blink = qla24xx_beacon_blink,
338c9161 1852 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1853 .write_optrom = qla24xx_write_optrom_data,
1854 .get_flash_version = qla24xx_get_flash_version,
bad75002 1855 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1856 .abort_isp = qla2x00_abort_isp,
706f457d 1857 .iospace_config = qla2x00_iospace_config,
c3a2f0df
AV		 1858};
1859
3a03eb79
AV		 1860static struct isp_operations qla81xx_isp_ops = {
1861 .pci_config = qla25xx_pci_config,
1862 .reset_chip = qla24xx_reset_chip,
1863 .chip_diag = qla24xx_chip_diag,
1864 .config_rings = qla24xx_config_rings,
1865 .reset_adapter = qla24xx_reset_adapter,
1866 .nvram_config = qla81xx_nvram_config,
1867 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1868 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1869 .pci_info_str = qla24xx_pci_info_str,
1870 .fw_version_str = qla24xx_fw_version_str,
1871 .intr_handler = qla24xx_intr_handler,
1872 .enable_intrs = qla24xx_enable_intrs,
1873 .disable_intrs = qla24xx_disable_intrs,
1874 .abort_command = qla24xx_abort_command,
1875 .target_reset = qla24xx_abort_target,
1876 .lun_reset = qla24xx_lun_reset,
1877 .fabric_login = qla24xx_login_fabric,
1878 .fabric_logout = qla24xx_fabric_logout,
1879 .calc_req_entries = NULL,
1880 .build_iocbs = NULL,
1881 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1882 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1883 .read_nvram = NULL,
1884 .write_nvram = NULL,
3a03eb79
AV		 1885 .fw_dump = qla81xx_fw_dump,
1886 .beacon_on = qla24xx_beacon_on,
1887 .beacon_off = qla24xx_beacon_off,
6246b8a1 1888 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1889 .read_optrom = qla25xx_read_optrom_data,
1890 .write_optrom = qla24xx_write_optrom_data,
1891 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1892 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1893 .abort_isp = qla2x00_abort_isp,
706f457d 1894 .iospace_config = qla2x00_iospace_config,
a9083016
GM		 1895};
1896
1897static struct isp_operations qla82xx_isp_ops = {
1898 .pci_config = qla82xx_pci_config,
1899 .reset_chip = qla82xx_reset_chip,
1900 .chip_diag = qla24xx_chip_diag,
1901 .config_rings = qla82xx_config_rings,
1902 .reset_adapter = qla24xx_reset_adapter,
1903 .nvram_config = qla81xx_nvram_config,
1904 .update_fw_options = qla24xx_update_fw_options,
1905 .load_risc = qla82xx_load_risc,
1906 .pci_info_str = qla82xx_pci_info_str,
1907 .fw_version_str = qla24xx_fw_version_str,
1908 .intr_handler = qla82xx_intr_handler,
1909 .enable_intrs = qla82xx_enable_intrs,
1910 .disable_intrs = qla82xx_disable_intrs,
1911 .abort_command = qla24xx_abort_command,
1912 .target_reset = qla24xx_abort_target,
1913 .lun_reset = qla24xx_lun_reset,
1914 .fabric_login = qla24xx_login_fabric,
1915 .fabric_logout = qla24xx_fabric_logout,
1916 .calc_req_entries = NULL,
1917 .build_iocbs = NULL,
1918 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1919 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1920 .read_nvram = qla24xx_read_nvram_data,
1921 .write_nvram = qla24xx_write_nvram_data,
1922 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1923 .beacon_on = qla82xx_beacon_on,
1924 .beacon_off = qla82xx_beacon_off,
1925 .beacon_blink = NULL,
a9083016
GM		 1926 .read_optrom = qla82xx_read_optrom_data,
1927 .write_optrom = qla82xx_write_optrom_data,
1928 .get_flash_version = qla24xx_get_flash_version,
1929 .start_scsi = qla82xx_start_scsi,
1930 .abort_isp = qla82xx_abort_isp,
706f457d 1931 .iospace_config = qla82xx_iospace_config,
3a03eb79
AV		 1932};
1933
6246b8a1
GM		 1934static struct isp_operations qla83xx_isp_ops = {
1935 .pci_config = qla25xx_pci_config,
1936 .reset_chip = qla24xx_reset_chip,
1937 .chip_diag = qla24xx_chip_diag,
1938 .config_rings = qla24xx_config_rings,
1939 .reset_adapter = qla24xx_reset_adapter,
1940 .nvram_config = qla81xx_nvram_config,
1941 .update_fw_options = qla81xx_update_fw_options,
1942 .load_risc = qla81xx_load_risc,
1943 .pci_info_str = qla24xx_pci_info_str,
1944 .fw_version_str = qla24xx_fw_version_str,
1945 .intr_handler = qla24xx_intr_handler,
1946 .enable_intrs = qla24xx_enable_intrs,
1947 .disable_intrs = qla24xx_disable_intrs,
1948 .abort_command = qla24xx_abort_command,
1949 .target_reset = qla24xx_abort_target,
1950 .lun_reset = qla24xx_lun_reset,
1951 .fabric_login = qla24xx_login_fabric,
1952 .fabric_logout = qla24xx_fabric_logout,
1953 .calc_req_entries = NULL,
1954 .build_iocbs = NULL,
1955 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1956 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1957 .read_nvram = NULL,
1958 .write_nvram = NULL,
1959 .fw_dump = qla83xx_fw_dump,
1960 .beacon_on = qla24xx_beacon_on,
1961 .beacon_off = qla24xx_beacon_off,
1962 .beacon_blink = qla83xx_beacon_blink,
1963 .read_optrom = qla25xx_read_optrom_data,
1964 .write_optrom = qla24xx_write_optrom_data,
1965 .get_flash_version = qla24xx_get_flash_version,
1966 .start_scsi = qla24xx_dif_start_scsi,
1967 .abort_isp = qla2x00_abort_isp,
1968 .iospace_config = qla83xx_iospace_config,
1969};
1970
ea5b6382 1971static inline void
e315cd28 1972qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 1973{
1974 ha->device_type = DT_EXTENDED_IDS;
1975 switch (ha->pdev->device) {
1976 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1977 ha->device_type |= DT_ISP2100;
1978 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1979 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 1980 break;
1981 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1982 ha->device_type |= DT_ISP2200;
1983 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1984 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 1985 break;
1986 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1987 ha->device_type |= DT_ISP2300;
4a59f71d 1988 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1989 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1990 break;
1991 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1992 ha->device_type |= DT_ISP2312;
4a59f71d 1993 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1994 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1995 break;
1996 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1997 ha->device_type |= DT_ISP2322;
4a59f71d 1998 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 1999 if (ha->pdev->subsystem_vendor == 0x1028 &&
2000 ha->pdev->subsystem_device == 0x0170)
2001 ha->device_type |= DT_OEM_001;
441d1072 2002 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2003 break;
2004 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2005 ha->device_type |= DT_ISP6312;
441d1072 2006 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2007 break;
2008 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2009 ha->device_type |= DT_ISP6322;
441d1072 2010 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2011 break;
2012 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2013 ha->device_type |= DT_ISP2422;
4a59f71d 2014 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2015 ha->device_type |= DT_FWI2;
c76f2c01 2016 ha->device_type |= DT_IIDMA;
441d1072 2017 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2018 break;
2019 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2020 ha->device_type |= DT_ISP2432;
4a59f71d 2021 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2022 ha->device_type |= DT_FWI2;
c76f2c01 2023 ha->device_type |= DT_IIDMA;
441d1072 2024 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2025 break;
4d4df193
HK		 2026 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2027 ha->device_type |= DT_ISP8432;
2028 ha->device_type |= DT_ZIO_SUPPORTED;
2029 ha->device_type |= DT_FWI2;
2030 ha->device_type |= DT_IIDMA;
2031 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2032 break;
044cc6c8
AV		 2033 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2034 ha->device_type |= DT_ISP5422;
e428924c 2035 ha->device_type |= DT_FWI2;
441d1072 2036 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2037 break;
044cc6c8
AV		 2038 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2039 ha->device_type |= DT_ISP5432;
e428924c 2040 ha->device_type |= DT_FWI2;
441d1072 2041 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2042 break;
c3a2f0df
AV		 2043 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2044 ha->device_type |= DT_ISP2532;
2045 ha->device_type |= DT_ZIO_SUPPORTED;
2046 ha->device_type |= DT_FWI2;
2047 ha->device_type |= DT_IIDMA;
441d1072 2048 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2049 break;
3a03eb79
AV		 2050 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2051 ha->device_type |= DT_ISP8001;
2052 ha->device_type |= DT_ZIO_SUPPORTED;
2053 ha->device_type |= DT_FWI2;
2054 ha->device_type |= DT_IIDMA;
2055 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2056 break;
a9083016
GM		 2057 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2058 ha->device_type |= DT_ISP8021;
2059 ha->device_type |= DT_ZIO_SUPPORTED;
2060 ha->device_type |= DT_FWI2;
2061 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2062 /* Initialize 82XX ISP flags */
2063 qla82xx_init_flags(ha);
2064 break;
6246b8a1
GM		 2065 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2066 ha->device_type |= DT_ISP2031;
2067 ha->device_type |= DT_ZIO_SUPPORTED;
2068 ha->device_type |= DT_FWI2;
2069 ha->device_type |= DT_IIDMA;
2070 ha->device_type |= DT_T10_PI;
2071 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2072 break;
2073 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2074 ha->device_type |= DT_ISP8031;
2075 ha->device_type |= DT_ZIO_SUPPORTED;
2076 ha->device_type |= DT_FWI2;
2077 ha->device_type |= DT_IIDMA;
2078 ha->device_type |= DT_T10_PI;
2079 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2080 break;
ea5b6382 2081 }
e5b68a61 2082
a9083016
GM		 2083 if (IS_QLA82XX(ha))
2084 ha->port_no = !(ha->portnum & 1);
2085 else
2086 /* Get adapter physical port no from interrupt pin register. */
2087 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2088
e5b68a61
AC		 2089 if (ha->port_no & 1)
2090 ha->flags.port0 = 1;
2091 else
2092 ha->flags.port0 = 0;
7c3df132 2093 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2094 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2095 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 2096}
2097
1e99e33a
AV		 2098static void
2099qla2xxx_scan_start(struct Scsi_Host *shost)
2100{
e315cd28 2101 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2102
cbc8eb67
AV		 2103 if (vha->hw->flags.running_gold_fw)
2104 return;
2105
e315cd28
AC		 2106 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2107 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2108 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2109 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2110}
2111
2112static int
2113qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2114{
e315cd28 2115 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2116
e315cd28 2117 if (!vha->host)
1e99e33a 2118 return 1;
e315cd28 2119 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2120 return 1;
2121
e315cd28 2122 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2123}
2124
1da177e4
LT		 2125/*
2126 * PCI driver interface
2127 */
7ee61397
AV		 2128static int __devinit
2129qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2130{
a1541d5a 2131 int ret = -ENODEV;
1da177e4 2132 struct Scsi_Host *host;
e315cd28
AC		 2133 scsi_qla_host_t *base_vha = NULL;
2134 struct qla_hw_data *ha;
29856e28 2135 char pci_info[30];
1da177e4 2136 char fw_str[30];
5433383e 2137 struct scsi_host_template *sht;
642ef983 2138 int bars, mem_only = 0;
e315cd28 2139 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2140 struct req_que *req = NULL;
2141 struct rsp_que *rsp = NULL;
1da177e4 2142
285d0321 2143 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2144 sht = &qla2xxx_driver_template;
5433383e 2145 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2146 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2147 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2148 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2149 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2150 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2151 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2152 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2153 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2154 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) {
285d0321 2155 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2156 mem_only = 1;
7c3df132
SK		 2157 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2158 "Mem only adapter.\n");
285d0321 2159 }
7c3df132
SK		 2160 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2161 "Bars=%d.\n", bars);
285d0321 2162
09483916
BH		 2163 if (mem_only) {
2164 if (pci_enable_device_mem(pdev))
2165 goto probe_out;
2166 } else {
2167 if (pci_enable_device(pdev))
2168 goto probe_out;
2169 }
285d0321 2170
0927678f
JB		 2171 /* This may fail but that's ok */
2172 pci_enable_pcie_error_reporting(pdev);
285d0321 2173
e315cd28
AC		 2174 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2175 if (!ha) {
7c3df132
SK		 2176 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2177 "Unable to allocate memory for ha.\n");
e315cd28 2178 goto probe_out;
1da177e4 2179 }
7c3df132
SK		 2180 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2181 "Memory allocated for ha=%p.\n", ha);
e315cd28 2182 ha->pdev = pdev;
1da177e4
LT		 2183
2184 /* Clear our data area */
285d0321 2185 ha->bars = bars;
09483916 2186 ha->mem_only = mem_only;
df4bf0bb 2187 spin_lock_init(&ha->hardware_lock);
339aa70e 2188 spin_lock_init(&ha->vport_slock);
1da177e4 2189
ea5b6382
AV		 2190 /* Set ISP-type information. */
2191 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2192
2193 /* Set EEH reset type to fundamental if required by hba */
6246b8a1 2194 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha))
ca79cf66 2195 pdev->needs_freset = 1;
ca79cf66 2196
cba1e47f
CD		 2197 ha->prev_topology = 0;
2198 ha->init_cb_size = sizeof(init_cb_t);
2199 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2200 ha->optrom_size = OPTROM_SIZE_2300;
2201
abbd8870 2202 /* Assign ISP specific operations. */
1da177e4 2203 if (IS_QLA2100(ha)) {
642ef983 2204 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2205 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2206 req_length = REQUEST_ENTRY_CNT_2100;
2207 rsp_length = RESPONSE_ENTRY_CNT_2100;
2208 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2209 ha->gid_list_info_size = 4;
3a03eb79
AV		 2210 ha->flash_conf_off = ~0;
2211 ha->flash_data_off = ~0;
2212 ha->nvram_conf_off = ~0;
2213 ha->nvram_data_off = ~0;
fd34f556 2214 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2215 } else if (IS_QLA2200(ha)) {
642ef983 2216 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2217 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2218 req_length = REQUEST_ENTRY_CNT_2200;
2219 rsp_length = RESPONSE_ENTRY_CNT_2100;
2220 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2221 ha->gid_list_info_size = 4;
3a03eb79
AV		 2222 ha->flash_conf_off = ~0;
2223 ha->flash_data_off = ~0;
2224 ha->nvram_conf_off = ~0;
2225 ha->nvram_data_off = ~0;
fd34f556 2226 ha->isp_ops = &qla2100_isp_ops;
fca29703 2227 } else if (IS_QLA23XX(ha)) {
642ef983 2228 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2229 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2230 req_length = REQUEST_ENTRY_CNT_2200;
2231 rsp_length = RESPONSE_ENTRY_CNT_2300;
2232 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2233 ha->gid_list_info_size = 6;
854165f4
AV		 2234 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2235 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2236 ha->flash_conf_off = ~0;
2237 ha->flash_data_off = ~0;
2238 ha->nvram_conf_off = ~0;
2239 ha->nvram_data_off = ~0;
fd34f556 2240 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2241 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2242 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2243 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2244 req_length = REQUEST_ENTRY_CNT_24XX;
2245 rsp_length = RESPONSE_ENTRY_CNT_2300;
2246 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2247 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2248 ha->gid_list_info_size = 8;
854165f4 2249 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2250 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2251 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2252 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2253 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2254 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2255 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2256 } else if (IS_QLA25XX(ha)) {
642ef983 2257 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2258 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2259 req_length = REQUEST_ENTRY_CNT_24XX;
2260 rsp_length = RESPONSE_ENTRY_CNT_2300;
2261 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2262 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2263 ha->gid_list_info_size = 8;
2264 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2265 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2266 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2267 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2268 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2269 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2270 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2271 } else if (IS_QLA81XX(ha)) {
642ef983 2272 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2273 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2274 req_length = REQUEST_ENTRY_CNT_24XX;
2275 rsp_length = RESPONSE_ENTRY_CNT_2300;
2276 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2277 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2278 ha->gid_list_info_size = 8;
2279 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2280 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2281 ha->isp_ops = &qla81xx_isp_ops;
2282 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2283 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2284 ha->nvram_conf_off = ~0;
2285 ha->nvram_data_off = ~0;
a9083016 2286 } else if (IS_QLA82XX(ha)) {
642ef983 2287 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2288 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2289 req_length = REQUEST_ENTRY_CNT_82XX;
2290 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2291 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2292 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2293 ha->gid_list_info_size = 8;
2294 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2295 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2296 ha->isp_ops = &qla82xx_isp_ops;
2297 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2298 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2299 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2300 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2301 } else if (IS_QLA83XX(ha)) {
642ef983 2302 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2303 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2304 req_length = REQUEST_ENTRY_CNT_24XX;
2305 rsp_length = RESPONSE_ENTRY_CNT_2300;
2306 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2307 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2308 ha->gid_list_info_size = 8;
2309 ha->optrom_size = OPTROM_SIZE_83XX;
2310 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2311 ha->isp_ops = &qla83xx_isp_ops;
2312 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2313 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2314 ha->nvram_conf_off = ~0;
2315 ha->nvram_data_off = ~0;
1da177e4 2316 }
6246b8a1 2317
7c3df132
SK		 2318 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2319 "mbx_count=%d, req_length=%d, "
2320 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2321 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2322 "max_fibre_devices=%d.\n",
7c3df132
SK		 2323 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2324 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2325 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2326 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2327 "isp_ops=%p, flash_conf_off=%d, "
2328 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2329 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2330 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2331
2332 /* Configure PCI I/O space */
2333 ret = ha->isp_ops->iospace_config(ha);
2334 if (ret)
2335 goto probe_hw_failed;
2336
2337 ql_log_pci(ql_log_info, pdev, 0x001d,
2338 "Found an ISP%04X irq %d iobase 0x%p.\n",
2339 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2340 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2341 init_completion(&ha->mbx_cmd_comp);
2342 complete(&ha->mbx_cmd_comp);
2343 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2344 init_completion(&ha->dcbx_comp);
1da177e4 2345
2c3dfe3f 2346 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2347
53303c42 2348 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2349 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2350 "64 Bit addressing is %s.\n",
2351 ha->flags.enable_64bit_addressing ? "enable" :
2352 "disable");
73208dfd 2353 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2354 if (!ret) {
7c3df132
SK		 2355 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2356 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2357
e315cd28
AC		 2358 goto probe_hw_failed;
2359 }
2360
73208dfd 2361 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2362 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2363 req->max_q_depth = ql2xmaxqdepth;
2364
e315cd28
AC		 2365
2366 base_vha = qla2x00_create_host(sht, ha);
2367 if (!base_vha) {
a1541d5a 2368 ret = -ENOMEM;
6e9f21f3 2369 qla2x00_mem_free(ha);
2afa19a9
AC		 2370 qla2x00_free_req_que(ha, req);
2371 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2372 goto probe_hw_failed;
1da177e4
LT		 2373 }
2374
e315cd28
AC		 2375 pci_set_drvdata(pdev, base_vha);
2376
e315cd28 2377 host = base_vha->host;
2afa19a9 2378 base_vha->req = req;
73208dfd
AC		 2379 host->can_queue = req->length + 128;
2380 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2381 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2382 else
e315cd28
AC		 2383 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2384 base_vha->vp_idx;
58548cb5
GM		 2385
2386 /* Set the SG table size based on ISP type */
2387 if (!IS_FWI2_CAPABLE(ha)) {
2388 if (IS_QLA2100(ha))
2389 host->sg_tablesize = 32;
2390 } else {
2391 if (!IS_QLA82XX(ha))
2392 host->sg_tablesize = QLA_SG_ALL;
2393 }
7c3df132
SK		 2394 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2395 "can_queue=%d, req=%p, "
2396 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2397 host->can_queue, base_vha->req,
2398 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2399 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2400 host->this_id = 255;
2401 host->cmd_per_lun = 3;
2402 host->unique_id = host->host_no;
e02587d7 2403 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2404 host->max_cmd_len = 32;
2405 else
2406 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2407 host->max_channel = MAX_BUSES - 1;
82515920 2408 host->max_lun = ql2xmaxlun;
e315cd28 2409 host->transportt = qla2xxx_transport_template;
9a069e19 2410 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2411
7c3df132
SK		 2412 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2413 "max_id=%d this_id=%d "
2414 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2415 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2416 host->this_id, host->cmd_per_lun, host->unique_id,
2417 host->max_cmd_len, host->max_channel, host->max_lun,
2418 host->transportt, sht->vendor_id);
2419
73208dfd
AC		 2420 /* Set up the irqs */
2421 ret = qla2x00_request_irqs(ha, rsp);
2422 if (ret)
6e9f21f3 2423 goto probe_init_failed;
90a86fc0
JC		 2424
2425 pci_save_state(pdev);
2426
73208dfd 2427 /* Alloc arrays of request and response ring ptrs */
7163ea81 2428que_init:
73208dfd 2429 if (!qla2x00_alloc_queues(ha)) {
7c3df132
SK		 2430 ql_log(ql_log_fatal, base_vha, 0x003d,
2431 "Failed to allocate memory for queue pointers.. aborting.\n");
6e9f21f3 2432 goto probe_init_failed;
73208dfd 2433 }
a9083016 2434
73208dfd
AC		 2435 ha->rsp_q_map[0] = rsp;
2436 ha->req_q_map[0] = req;
2afa19a9
AC		 2437 rsp->req = req;
2438 req->rsp = rsp;
2439 set_bit(0, ha->req_qid_map);
2440 set_bit(0, ha->rsp_qid_map);
08029990
AV		 2441 /* FWI2-capable only. */
2442 req->req_q_in = &ha->iobase->isp24.req_q_in;
2443 req->req_q_out = &ha->iobase->isp24.req_q_out;
2444 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2445 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2446 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2447 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2448 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2449 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2450 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2451 }
2452
a9083016
GM		 2453 if (IS_QLA82XX(ha)) {
2454 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2455 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2456 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2457 }
2458
7c3df132
SK		 2459 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2460 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2461 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2462 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2463 "req->req_q_in=%p req->req_q_out=%p "
2464 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2465 req->req_q_in, req->req_q_out,
2466 rsp->rsp_q_in, rsp->rsp_q_out);
2467 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2468 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2469 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2470 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2471 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2472 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2473
7c3df132
SK		 2474 if (qla2x00_initialize_adapter(base_vha)) {
2475 ql_log(ql_log_fatal, base_vha, 0x00d6,
2476 "Failed to initialize adapter - Adapter flags %x.\n",
2477 base_vha->device_flags);
1da177e4 2478
a9083016
GM		 2479 if (IS_QLA82XX(ha)) {
2480 qla82xx_idc_lock(ha);
2481 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2482 QLA82XX_DEV_FAILED);
2483 qla82xx_idc_unlock(ha);
7c3df132
SK		 2484 ql_log(ql_log_fatal, base_vha, 0x00d7,
2485 "HW State: FAILED.\n");
a9083016
GM		 2486 }
2487
a1541d5a 2488 ret = -ENODEV;
1da177e4
LT		 2489 goto probe_failed;
2490 }
2491
7163ea81
AC		 2492 if (ha->mqenable) {
2493 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2494 ql_log(ql_log_warn, base_vha, 0x00ec,
2495 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2496 goto que_init;
2497 }
2498 }
68ca949c 2499
cbc8eb67
AV		 2500 if (ha->flags.running_gold_fw)
2501 goto skip_dpc;
2502
1da177e4
LT		 2503 /*
2504 * Startup the kernel thread for this host adapter
2505 */
39a11240 2506 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2507 "%s_dpc", base_vha->host_str);
39a11240 2508 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2509 ql_log(ql_log_fatal, base_vha, 0x00ed,
2510 "Failed to start DPC thread.\n");
39a11240 2511 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2512 goto probe_failed;
2513 }
7c3df132
SK		 2514 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2515 "DPC thread started successfully.\n");
1da177e4 2516
cbc8eb67 2517skip_dpc:
e315cd28
AC		 2518 list_add_tail(&base_vha->list, &ha->vp_list);
2519 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2520
2521 /* Initialized the timer */
e315cd28 2522 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2523 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2524 "Started qla2x00_timer with "
2525 "interval=%d.\n", WATCH_INTERVAL);
2526 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2527 "Detected hba at address=%p.\n",
2528 ha);
d19044c3 2529
e02587d7 2530 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2531 if (ha->fw_attributes & BIT_4) {
8cb2049c 2532 int prot = 0;
bad75002 2533 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2534 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2535 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2536 if (ql2xenabledif == 1)
2537 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2538 scsi_host_set_prot(host,
8cb2049c 2539 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2540 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2541 | SHOST_DIF_TYPE3_PROTECTION
2542 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2543 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2544 | SHOST_DIX_TYPE3_PROTECTION);
2545 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2546 } else
2547 base_vha->flags.difdix_supported = 0;
2548 }
2549
a9083016
GM		 2550 ha->isp_ops->enable_intrs(ha);
2551
a1541d5a
AV		 2552 ret = scsi_add_host(host, &pdev->dev);
2553 if (ret)
2554 goto probe_failed;
2555
1486400f
MR		 2556 base_vha->flags.init_done = 1;
2557 base_vha->flags.online = 1;
2558
7c3df132
SK		 2559 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2560 "Init done and hba is online.\n");
2561
1e99e33a
AV		 2562 scsi_scan_host(host);
2563
e315cd28 2564 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2565
e315cd28 2566 qla2x00_init_host_attr(base_vha);
a1541d5a 2567
e315cd28 2568 qla2x00_dfs_setup(base_vha);
df613b96 2569
7c3df132
SK		 2570 ql_log(ql_log_info, base_vha, 0x00fb,
2571 "QLogic %s - %s.\n",
2572 ha->model_number, ha->model_desc ? ha->model_desc : "");
2573 ql_log(ql_log_info, base_vha, 0x00fc,
2574 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2575 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2576 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2577 base_vha->host_no,
e315cd28 2578 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2579
1da177e4
LT		 2580 return 0;
2581
6e9f21f3 2582probe_init_failed:
2afa19a9
AC		 2583 qla2x00_free_req_que(ha, req);
2584 qla2x00_free_rsp_que(ha, rsp);
2585 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2586
1da177e4 2587probe_failed:
b9978769
AV		 2588 if (base_vha->timer_active)
2589 qla2x00_stop_timer(base_vha);
2590 base_vha->flags.online = 0;
2591 if (ha->dpc_thread) {
2592 struct task_struct *t = ha->dpc_thread;
2593
2594 ha->dpc_thread = NULL;
2595 kthread_stop(t);
2596 }
2597
e315cd28 2598 qla2x00_free_device(base_vha);
1da177e4 2599
e315cd28 2600 scsi_host_put(base_vha->host);
1da177e4 2601
e315cd28 2602probe_hw_failed:
a9083016
GM		 2603 if (IS_QLA82XX(ha)) {
2604 qla82xx_idc_lock(ha);
2605 qla82xx_clear_drv_active(ha);
2606 qla82xx_idc_unlock(ha);
2607 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2608 if (!ql2xdbwr)
2609 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2610 } else {
2611 if (ha->iobase)
2612 iounmap(ha->iobase);
2613 }
e315cd28
AC		 2614 pci_release_selected_regions(ha->pdev, ha->bars);
2615 kfree(ha);
2616 ha = NULL;
1da177e4 2617
a1541d5a 2618probe_out:
e315cd28 2619 pci_disable_device(pdev);
a1541d5a 2620 return ret;
1da177e4 2621}
1da177e4 2622
e30d1756
MI		 2623static void
2624qla2x00_shutdown(struct pci_dev *pdev)
2625{
2626 scsi_qla_host_t *vha;
2627 struct qla_hw_data *ha;
2628
2629 vha = pci_get_drvdata(pdev);
2630 ha = vha->hw;
2631
2632 /* Turn-off FCE trace */
2633 if (ha->flags.fce_enabled) {
2634 qla2x00_disable_fce_trace(vha, NULL, NULL);
2635 ha->flags.fce_enabled = 0;
2636 }
2637
2638 /* Turn-off EFT trace */
2639 if (ha->eft)
2640 qla2x00_disable_eft_trace(vha);
2641
2642 /* Stop currently executing firmware. */
2643 qla2x00_try_to_stop_firmware(vha);
2644
2645 /* Turn adapter off line */
2646 vha->flags.online = 0;
2647
2648 /* turn-off interrupts on the card */
2649 if (ha->interrupts_on) {
2650 vha->flags.init_done = 0;
2651 ha->isp_ops->disable_intrs(ha);
2652 }
2653
2654 qla2x00_free_irqs(vha);
2655
2656 qla2x00_free_fw_dump(ha);
2657}
2658
4c993f76 2659static void
7ee61397 2660qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2661{
feafb7b1 2662 scsi_qla_host_t *base_vha, *vha;
e315cd28 2663 struct qla_hw_data *ha;
feafb7b1 2664 unsigned long flags;
e315cd28
AC		 2665
2666 base_vha = pci_get_drvdata(pdev);
2667 ha = base_vha->hw;
2668
43ebf16d
AE		 2669 mutex_lock(&ha->vport_lock);
2670 while (ha->cur_vport_count) {
2671 struct Scsi_Host *scsi_host;
feafb7b1 2672
43ebf16d 2673 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2674
43ebf16d
AE		 2675 BUG_ON(base_vha->list.next == &ha->vp_list);
2676 /* This assumes first entry in ha->vp_list is always base vha */
2677 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2678 scsi_host = scsi_host_get(vha->host);
feafb7b1 2679
43ebf16d
AE		 2680 spin_unlock_irqrestore(&ha->vport_slock, flags);
2681 mutex_unlock(&ha->vport_lock);
2682
2683 fc_vport_terminate(vha->fc_vport);
2684 scsi_host_put(vha->host);
feafb7b1 2685
43ebf16d 2686 mutex_lock(&ha->vport_lock);
e315cd28 2687 }
43ebf16d 2688 mutex_unlock(&ha->vport_lock);
1da177e4 2689
e315cd28 2690 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2691
b9978769
AV		 2692 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2693
e315cd28 2694 qla2x00_dfs_remove(base_vha);
c795c1e4 2695
e315cd28 2696 qla84xx_put_chip(base_vha);
c795c1e4 2697
b9978769
AV		 2698 /* Disable timer */
2699 if (base_vha->timer_active)
2700 qla2x00_stop_timer(base_vha);
2701
2702 base_vha->flags.online = 0;
2703
68ca949c
AC		 2704 /* Flush the work queue and remove it */
2705 if (ha->wq) {
2706 flush_workqueue(ha->wq);
2707 destroy_workqueue(ha->wq);
2708 ha->wq = NULL;
2709 }
2710
b9978769
AV		 2711 /* Kill the kernel thread for this host */
2712 if (ha->dpc_thread) {
2713 struct task_struct *t = ha->dpc_thread;
2714
2715 /*
2716 * qla2xxx_wake_dpc checks for ->dpc_thread
2717 * so we need to zero it out.
2718 */
2719 ha->dpc_thread = NULL;
2720 kthread_stop(t);
2721 }
2722
e315cd28 2723 qla2x00_free_sysfs_attr(base_vha);
df613b96 2724
e315cd28 2725 fc_remove_host(base_vha->host);
4d4df193 2726
e315cd28 2727 scsi_remove_host(base_vha->host);
1da177e4 2728
e315cd28 2729 qla2x00_free_device(base_vha);
bdf79621 2730
e315cd28 2731 scsi_host_put(base_vha->host);
1da177e4 2732
a9083016 2733 if (IS_QLA82XX(ha)) {
b963752f
GM		 2734 qla82xx_idc_lock(ha);
2735 qla82xx_clear_drv_active(ha);
2736 qla82xx_idc_unlock(ha);
2737
a9083016
GM		 2738 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2739 if (!ql2xdbwr)
2740 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2741 } else {
2742 if (ha->iobase)
2743 iounmap(ha->iobase);
1da177e4 2744
a9083016
GM		 2745 if (ha->mqiobase)
2746 iounmap(ha->mqiobase);
6246b8a1
GM		 2747
2748 if (IS_QLA83XX(ha) && ha->msixbase)
2749 iounmap(ha->msixbase);
a9083016 2750 }
73208dfd 2751
e315cd28
AC		 2752 pci_release_selected_regions(ha->pdev, ha->bars);
2753 kfree(ha);
2754 ha = NULL;
1da177e4 2755
90a86fc0
JC		 2756 pci_disable_pcie_error_reporting(pdev);
2757
665db93b 2758 pci_disable_device(pdev);
1da177e4
LT		 2759 pci_set_drvdata(pdev, NULL);
2760}
1da177e4
LT		 2761
2762static void
e315cd28 2763qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2764{
e315cd28 2765 struct qla_hw_data *ha = vha->hw;
1da177e4 2766
85880801
AV		 2767 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2768
2769 /* Disable timer */
2770 if (vha->timer_active)
2771 qla2x00_stop_timer(vha);
2772
2773 /* Kill the kernel thread for this host */
2774 if (ha->dpc_thread) {
2775 struct task_struct *t = ha->dpc_thread;
2776
2777 /*
2778 * qla2xxx_wake_dpc checks for ->dpc_thread
2779 * so we need to zero it out.
2780 */
2781 ha->dpc_thread = NULL;
2782 kthread_stop(t);
2783 }
2784
2afa19a9
AC		 2785 qla25xx_delete_queues(vha);
2786
df613b96 2787 if (ha->flags.fce_enabled)
e315cd28 2788 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2789
a7a167bf 2790 if (ha->eft)
e315cd28 2791 qla2x00_disable_eft_trace(vha);
a7a167bf 2792
f6ef3b18 2793 /* Stop currently executing firmware. */
e315cd28 2794 qla2x00_try_to_stop_firmware(vha);
1da177e4 2795
85880801
AV		 2796 vha->flags.online = 0;
2797
f6ef3b18 2798 /* turn-off interrupts on the card */
a9083016
GM		 2799 if (ha->interrupts_on) {
2800 vha->flags.init_done = 0;
fd34f556 2801 ha->isp_ops->disable_intrs(ha);
a9083016 2802 }
f6ef3b18 2803
e315cd28 2804 qla2x00_free_irqs(vha);
1da177e4 2805
8867048b
CD		 2806 qla2x00_free_fcports(vha);
2807
e315cd28 2808 qla2x00_mem_free(ha);
73208dfd 2809
08de2844
GM		 2810 qla82xx_md_free(vha);
2811
73208dfd 2812 qla2x00_free_queues(ha);
1da177e4
LT		 2813}
2814
8867048b
CD		 2815void qla2x00_free_fcports(struct scsi_qla_host *vha)
2816{
2817 fc_port_t *fcport, *tfcport;
2818
2819 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2820 list_del(&fcport->list);
2821 kfree(fcport);
2822 fcport = NULL;
2823 }
2824}
2825
d97994dc 2826static inline void
e315cd28 2827qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 2828 int defer)
2829{
d97994dc 2830 struct fc_rport *rport;
67becc00 2831 scsi_qla_host_t *base_vha;
044d78e1 2832 unsigned long flags;
d97994dc
AV		 2833
2834 if (!fcport->rport)
2835 return;
2836
2837 rport = fcport->rport;
2838 if (defer) {
67becc00 2839 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2840 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2841 fcport->drport = rport;
044d78e1 2842 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2843 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2844 qla2xxx_wake_dpc(base_vha);
5f3a9a20 2845 } else
d97994dc 2846 fc_remote_port_delete(rport);
d97994dc
AV		 2847}
2848
1da177e4
LT		 2849/*
2850 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2851 *
2852 * Input: ha = adapter block pointer. fcport = port structure pointer.
2853 *
2854 * Return: None.
2855 *
2856 * Context:
2857 */
e315cd28 2858void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2859 int do_login, int defer)
1da177e4 2860{
2c3dfe3f 2861 if (atomic_read(&fcport->state) == FCS_ONLINE &&
e315cd28 2862 vha->vp_idx == fcport->vp_idx) {
ec426e10 2863 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2864 qla2x00_schedule_rport_del(vha, fcport, defer);
2865 }
fa2a1ce5 2866 /*
1da177e4
LT		 2867 * We may need to retry the login, so don't change the state of the
2868 * port but do the retries.
2869 */
2870 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2871 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2872
2873 if (!do_login)
2874 return;
2875
2876 if (fcport->login_retry == 0) {
e315cd28
AC		 2877 fcport->login_retry = vha->hw->login_retry_count;
2878 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2879
7c3df132
SK		 2880 ql_dbg(ql_dbg_disc, vha, 0x2067,
2881 "Port login retry "
1da177e4 2882 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2883 "id = 0x%04x retry cnt=%d.\n",
2884 fcport->port_name[0], fcport->port_name[1],
2885 fcport->port_name[2], fcport->port_name[3],
2886 fcport->port_name[4], fcport->port_name[5],
2887 fcport->port_name[6], fcport->port_name[7],
2888 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2889 }
2890}
2891
2892/*
2893 * qla2x00_mark_all_devices_lost
2894 * Updates fcport state when device goes offline.
2895 *
2896 * Input:
2897 * ha = adapter block pointer.
2898 * fcport = port structure pointer.
2899 *
2900 * Return:
2901 * None.
2902 *
2903 * Context:
2904 */
2905void
e315cd28 2906qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 2907{
2908 fc_port_t *fcport;
2909
e315cd28 2910 list_for_each_entry(fcport, &vha->vp_fcports, list) {
0d6e61bc 2911 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
1da177e4 2912 continue;
0d6e61bc 2913
1da177e4
LT		 2914 /*
2915 * No point in marking the device as lost, if the device is
2916 * already DEAD.
2917 */
2918 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2919 continue;
e315cd28 2920 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 2921 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 2922 if (defer)
2923 qla2x00_schedule_rport_del(vha, fcport, defer);
2924 else if (vha->vp_idx == fcport->vp_idx)
2925 qla2x00_schedule_rport_del(vha, fcport, defer);
2926 }
1da177e4
LT		 2927 }
2928}
2929
2930/*
2931* qla2x00_mem_alloc
2932* Allocates adapter memory.
2933*
2934* Returns:
2935* 0 = success.
e8711085 2936* !0 = failure.
1da177e4 2937*/
e8711085 2938static int
73208dfd
AC		 2939qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2940 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 2941{
2942 char name[16];
1da177e4 2943
e8711085 2944 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 2945 &ha->init_cb_dma, GFP_KERNEL);
e8711085 2946 if (!ha->init_cb)
e315cd28 2947 goto fail;
e8711085 2948
642ef983
CD		 2949 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
2950 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 2951 if (!ha->gid_list)
e8711085 2952 goto fail_free_init_cb;
1da177e4 2953
e8711085
AV		 2954 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2955 if (!ha->srb_mempool)
e315cd28 2956 goto fail_free_gid_list;
e8711085 2957
a9083016
GM		 2958 if (IS_QLA82XX(ha)) {
2959 /* Allocate cache for CT6 Ctx. */
2960 if (!ctx_cachep) {
2961 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2962 sizeof(struct ct6_dsd), 0,
2963 SLAB_HWCACHE_ALIGN, NULL);
2964 if (!ctx_cachep)
2965 goto fail_free_gid_list;
2966 }
2967 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2968 ctx_cachep);
2969 if (!ha->ctx_mempool)
2970 goto fail_free_srb_mempool;
7c3df132
SK		 2971 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2972 "ctx_cachep=%p ctx_mempool=%p.\n",
2973 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 2974 }
2975
e8711085
AV		 2976 /* Get memory for cached NVRAM */
2977 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2978 if (!ha->nvram)
a9083016 2979 goto fail_free_ctx_mempool;
e8711085 2980
e315cd28
AC		 2981 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2982 ha->pdev->device);
2983 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2984 DMA_POOL_SIZE, 8, 0);
2985 if (!ha->s_dma_pool)
2986 goto fail_free_nvram;
2987
7c3df132
SK		 2988 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2989 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2990 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2991
bad75002 2992 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2993 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2994 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2995 if (!ha->dl_dma_pool) {
7c3df132
SK		 2996 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2997 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 2998 goto fail_s_dma_pool;
2999 }
3000
3001 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3002 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3003 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3004 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3005 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3006 goto fail_dl_dma_pool;
3007 }
7c3df132
SK		 3008 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3009 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3010 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3011 }
3012
e8711085
AV		 3013 /* Allocate memory for SNS commands */
3014 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3015 /* Get consistent memory allocated for SNS commands */
e8711085 3016 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3017 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3018 if (!ha->sns_cmd)
e315cd28 3019 goto fail_dma_pool;
7c3df132 3020 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3021 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3022 } else {
e315cd28 3023 /* Get consistent memory allocated for MS IOCB */
e8711085 3024 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3025 &ha->ms_iocb_dma);
e8711085 3026 if (!ha->ms_iocb)
e315cd28
AC		 3027 goto fail_dma_pool;
3028 /* Get consistent memory allocated for CT SNS commands */
e8711085 3029 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3030 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3031 if (!ha->ct_sns)
3032 goto fail_free_ms_iocb;
7c3df132
SK		 3033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3034 "ms_iocb=%p ct_sns=%p.\n",
3035 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3036 }
3037
e315cd28 3038 /* Allocate memory for request ring */
73208dfd
AC		 3039 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3040 if (!*req) {
7c3df132
SK		 3041 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3042 "Failed to allocate memory for req.\n");
e315cd28
AC		 3043 goto fail_req;
3044 }
73208dfd
AC		 3045 (*req)->length = req_len;
3046 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3047 ((*req)->length + 1) * sizeof(request_t),
3048 &(*req)->dma, GFP_KERNEL);
3049 if (!(*req)->ring) {
7c3df132
SK		 3050 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3051 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3052 goto fail_req_ring;
3053 }
3054 /* Allocate memory for response ring */
73208dfd
AC		 3055 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3056 if (!*rsp) {
7c3df132
SK		 3057 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3058 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3059 goto fail_rsp;
3060 }
73208dfd
AC		 3061 (*rsp)->hw = ha;
3062 (*rsp)->length = rsp_len;
3063 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3064 ((*rsp)->length + 1) * sizeof(response_t),
3065 &(*rsp)->dma, GFP_KERNEL);
3066 if (!(*rsp)->ring) {
7c3df132
SK		 3067 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3068 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3069 goto fail_rsp_ring;
3070 }
73208dfd
AC		 3071 (*req)->rsp = *rsp;
3072 (*rsp)->req = *req;
7c3df132
SK		 3073 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3074 "req=%p req->length=%d req->ring=%p rsp=%p "
3075 "rsp->length=%d rsp->ring=%p.\n",
3076 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3077 (*rsp)->ring);
73208dfd
AC		 3078 /* Allocate memory for NVRAM data for vports */
3079 if (ha->nvram_npiv_size) {
3080 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3081 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3082 if (!ha->npiv_info) {
7c3df132
SK		 3083 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3084 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3085 goto fail_npiv_info;
3086 }
3087 } else
3088 ha->npiv_info = NULL;
e8711085 3089
b64b0e8f 3090 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3091 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3092 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3093 &ha->ex_init_cb_dma);
3094 if (!ha->ex_init_cb)
3095 goto fail_ex_init_cb;
7c3df132
SK		 3096 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3097 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3098 }
3099
a9083016
GM		 3100 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3101
5ff1d584
AV		 3102 /* Get consistent memory allocated for Async Port-Database. */
3103 if (!IS_FWI2_CAPABLE(ha)) {
3104 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3105 &ha->async_pd_dma);
3106 if (!ha->async_pd)
3107 goto fail_async_pd;
7c3df132
SK		 3108 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3109 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3110 }
3111
e315cd28
AC		 3112 INIT_LIST_HEAD(&ha->vp_list);
3113 return 1;
3114
5ff1d584
AV		 3115fail_async_pd:
3116 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3117fail_ex_init_cb:
3118 kfree(ha->npiv_info);
73208dfd
AC		 3119fail_npiv_info:
3120 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3121 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3122 (*rsp)->ring = NULL;
3123 (*rsp)->dma = 0;
e315cd28 3124fail_rsp_ring:
73208dfd 3125 kfree(*rsp);
e315cd28 3126fail_rsp:
73208dfd
AC		 3127 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3128 sizeof(request_t), (*req)->ring, (*req)->dma);
3129 (*req)->ring = NULL;
3130 (*req)->dma = 0;
e315cd28 3131fail_req_ring:
73208dfd 3132 kfree(*req);
e315cd28
AC		 3133fail_req:
3134 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3135 ha->ct_sns, ha->ct_sns_dma);
3136 ha->ct_sns = NULL;
3137 ha->ct_sns_dma = 0;
e8711085
AV		 3138fail_free_ms_iocb:
3139 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3140 ha->ms_iocb = NULL;
3141 ha->ms_iocb_dma = 0;
e315cd28 3142fail_dma_pool:
bad75002 3143 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3144 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3145 ha->fcp_cmnd_dma_pool = NULL;
3146 }
3147fail_dl_dma_pool:
bad75002 3148 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3149 dma_pool_destroy(ha->dl_dma_pool);
3150 ha->dl_dma_pool = NULL;
3151 }
3152fail_s_dma_pool:
e315cd28
AC		 3153 dma_pool_destroy(ha->s_dma_pool);
3154 ha->s_dma_pool = NULL;
e8711085
AV		 3155fail_free_nvram:
3156 kfree(ha->nvram);
3157 ha->nvram = NULL;
a9083016
GM		 3158fail_free_ctx_mempool:
3159 mempool_destroy(ha->ctx_mempool);
3160 ha->ctx_mempool = NULL;
e8711085
AV		 3161fail_free_srb_mempool:
3162 mempool_destroy(ha->srb_mempool);
3163 ha->srb_mempool = NULL;
e8711085 3164fail_free_gid_list:
642ef983
CD		 3165 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3166 ha->gid_list,
e315cd28 3167 ha->gid_list_dma);
e8711085
AV		 3168 ha->gid_list = NULL;
3169 ha->gid_list_dma = 0;
e315cd28
AC		 3170fail_free_init_cb:
3171 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3172 ha->init_cb_dma);
3173 ha->init_cb = NULL;
3174 ha->init_cb_dma = 0;
e8711085 3175fail:
7c3df132
SK		 3176 ql_log(ql_log_fatal, NULL, 0x0030,
3177 "Memory allocation failure.\n");
e8711085 3178 return -ENOMEM;
1da177e4
LT		 3179}
3180
3181/*
e30d1756
MI		 3182* qla2x00_free_fw_dump
3183* Frees fw dump stuff.
1da177e4
LT		 3184*
3185* Input:
e30d1756 3186* ha = adapter block pointer.
1da177e4 3187*/
a824ebb3 3188static void
e30d1756 3189qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3190{
df613b96
AV		 3191 if (ha->fce)
3192 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3193 ha->fce_dma);
df613b96 3194
a7a167bf
AV		 3195 if (ha->fw_dump) {
3196 if (ha->eft)
3197 dma_free_coherent(&ha->pdev->dev,
e30d1756 3198 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3199 vfree(ha->fw_dump);
3200 }
e30d1756
MI		 3201 ha->fce = NULL;
3202 ha->fce_dma = 0;
3203 ha->eft = NULL;
3204 ha->eft_dma = 0;
3205 ha->fw_dump = NULL;
3206 ha->fw_dumped = 0;
3207 ha->fw_dump_reading = 0;
3208}
3209
3210/*
3211* qla2x00_mem_free
3212* Frees all adapter allocated memory.
3213*
3214* Input:
3215* ha = adapter block pointer.
3216*/
3217static void
3218qla2x00_mem_free(struct qla_hw_data *ha)
3219{
3220 qla2x00_free_fw_dump(ha);
3221
3222 if (ha->srb_mempool)
3223 mempool_destroy(ha->srb_mempool);
a7a167bf 3224
11bbc1d8
AV		 3225 if (ha->dcbx_tlv)
3226 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3227 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3228
ce0423f4
AV		 3229 if (ha->xgmac_data)
3230 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3231 ha->xgmac_data, ha->xgmac_data_dma);
3232
1da177e4
LT		 3233 if (ha->sns_cmd)
3234 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3235 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3236
3237 if (ha->ct_sns)
3238 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3239 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3240
88729e53
AV		 3241 if (ha->sfp_data)
3242 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3243
1da177e4
LT		 3244 if (ha->ms_iocb)
3245 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3246
b64b0e8f 3247 if (ha->ex_init_cb)
a9083016
GM		 3248 dma_pool_free(ha->s_dma_pool,
3249 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3250
5ff1d584
AV		 3251 if (ha->async_pd)
3252 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3253
1da177e4
LT		 3254 if (ha->s_dma_pool)
3255 dma_pool_destroy(ha->s_dma_pool);
3256
1da177e4 3257 if (ha->gid_list)
642ef983
CD		 3258 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3259 ha->gid_list, ha->gid_list_dma);
1da177e4 3260
a9083016
GM		 3261 if (IS_QLA82XX(ha)) {
3262 if (!list_empty(&ha->gbl_dsd_list)) {
3263 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3264
3265 /* clean up allocated prev pool */
3266 list_for_each_entry_safe(dsd_ptr,
3267 tdsd_ptr, &ha->gbl_dsd_list, list) {
3268 dma_pool_free(ha->dl_dma_pool,
3269 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3270 list_del(&dsd_ptr->list);
3271 kfree(dsd_ptr);
3272 }
3273 }
3274 }
3275
3276 if (ha->dl_dma_pool)
3277 dma_pool_destroy(ha->dl_dma_pool);
3278
3279 if (ha->fcp_cmnd_dma_pool)
3280 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3281
3282 if (ha->ctx_mempool)
3283 mempool_destroy(ha->ctx_mempool);
3284
e315cd28
AC		 3285 if (ha->init_cb)
3286 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3287 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3288 vfree(ha->optrom_buffer);
3289 kfree(ha->nvram);
73208dfd 3290 kfree(ha->npiv_info);
7a67735b 3291 kfree(ha->swl);
1da177e4 3292
e8711085 3293 ha->srb_mempool = NULL;
a9083016 3294 ha->ctx_mempool = NULL;
1da177e4
LT		 3295 ha->sns_cmd = NULL;
3296 ha->sns_cmd_dma = 0;
3297 ha->ct_sns = NULL;
3298 ha->ct_sns_dma = 0;
3299 ha->ms_iocb = NULL;
3300 ha->ms_iocb_dma = 0;
1da177e4
LT		 3301 ha->init_cb = NULL;
3302 ha->init_cb_dma = 0;
b64b0e8f
AV		 3303 ha->ex_init_cb = NULL;
3304 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3305 ha->async_pd = NULL;
3306 ha->async_pd_dma = 0;
1da177e4
LT		 3307
3308 ha->s_dma_pool = NULL;
a9083016
GM		 3309 ha->dl_dma_pool = NULL;
3310 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3311
1da177e4
LT		 3312 ha->gid_list = NULL;
3313 ha->gid_list_dma = 0;
e315cd28 3314}
1da177e4 3315
e315cd28
AC		 3316struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3317 struct qla_hw_data *ha)
3318{
3319 struct Scsi_Host *host;
3320 struct scsi_qla_host *vha = NULL;
854165f4 3321
e315cd28
AC		 3322 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3323 if (host == NULL) {
7c3df132
SK		 3324 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3325 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3326 goto fail;
3327 }
3328
3329 /* Clear our data area */
3330 vha = shost_priv(host);
3331 memset(vha, 0, sizeof(scsi_qla_host_t));
3332
3333 vha->host = host;
3334 vha->host_no = host->host_no;
3335 vha->hw = ha;
3336
3337 INIT_LIST_HEAD(&vha->vp_fcports);
3338 INIT_LIST_HEAD(&vha->work_list);
3339 INIT_LIST_HEAD(&vha->list);
3340
f999f4c1
AV		 3341 spin_lock_init(&vha->work_lock);
3342
e315cd28 3343 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3344 ql_dbg(ql_dbg_init, vha, 0x0041,
3345 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3346 vha->host, vha->hw, vha,
3347 dev_name(&(ha->pdev->dev)));
3348
e315cd28
AC		 3349 return vha;
3350
3351fail:
3352 return vha;
1da177e4
LT		 3353}
3354
01ef66bb 3355static struct qla_work_evt *
f999f4c1 3356qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3357{
3358 struct qla_work_evt *e;
feafb7b1
AE		 3359 uint8_t bail;
3360
3361 QLA_VHA_MARK_BUSY(vha, bail);
3362 if (bail)
3363 return NULL;
0971de7f 3364
f999f4c1 3365 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3366 if (!e) {
3367 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3368 return NULL;
feafb7b1 3369 }
0971de7f
AV		 3370
3371 INIT_LIST_HEAD(&e->list);
3372 e->type = type;
3373 e->flags = QLA_EVT_FLAG_FREE;
3374 return e;
3375}
3376
01ef66bb 3377static int
f999f4c1 3378qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3379{
f999f4c1 3380 unsigned long flags;
0971de7f 3381
f999f4c1 3382 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3383 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3384 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3385 qla2xxx_wake_dpc(vha);
f999f4c1 3386
0971de7f
AV		 3387 return QLA_SUCCESS;
3388}
3389
3390int
e315cd28 3391qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3392 u32 data)
3393{
3394 struct qla_work_evt *e;
3395
f999f4c1 3396 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3397 if (!e)
3398 return QLA_FUNCTION_FAILED;
3399
3400 e->u.aen.code = code;
3401 e->u.aen.data = data;
f999f4c1 3402 return qla2x00_post_work(vha, e);
0971de7f
AV		 3403}
3404
8a659571
AV		 3405int
3406qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3407{
3408 struct qla_work_evt *e;
3409
f999f4c1 3410 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3411 if (!e)
3412 return QLA_FUNCTION_FAILED;
3413
3414 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3415 return qla2x00_post_work(vha, e);
8a659571
AV		 3416}
3417
ac280b67
AV		 3418#define qla2x00_post_async_work(name, type) \
3419int qla2x00_post_async_##name##_work( \
3420 struct scsi_qla_host *vha, \
3421 fc_port_t *fcport, uint16_t *data) \
3422{ \
3423 struct qla_work_evt *e; \
3424 \
3425 e = qla2x00_alloc_work(vha, type); \
3426 if (!e) \
3427 return QLA_FUNCTION_FAILED; \
3428 \
3429 e->u.logio.fcport = fcport; \
3430 if (data) { \
3431 e->u.logio.data[0] = data[0]; \
3432 e->u.logio.data[1] = data[1]; \
3433 } \
3434 return qla2x00_post_work(vha, e); \
3435}
3436
3437qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3438qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3439qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3440qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3441qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3442qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3443
3420d36c
AV		 3444int
3445qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3446{
3447 struct qla_work_evt *e;
3448
3449 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3450 if (!e)
3451 return QLA_FUNCTION_FAILED;
3452
3453 e->u.uevent.code = code;
3454 return qla2x00_post_work(vha, e);
3455}
3456
3457static void
3458qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3459{
3460 char event_string[40];
3461 char *envp[] = { event_string, NULL };
3462
3463 switch (code) {
3464 case QLA_UEVENT_CODE_FW_DUMP:
3465 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3466 vha->host_no);
3467 break;
3468 default:
3469 /* do nothing */
3470 break;
3471 }
3472 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3473}
3474
ac280b67 3475void
e315cd28 3476qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3477{
f999f4c1
AV		 3478 struct qla_work_evt *e, *tmp;
3479 unsigned long flags;
3480 LIST_HEAD(work);
0971de7f 3481
f999f4c1
AV		 3482 spin_lock_irqsave(&vha->work_lock, flags);
3483 list_splice_init(&vha->work_list, &work);
3484 spin_unlock_irqrestore(&vha->work_lock, flags);
3485
3486 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3487 list_del_init(&e->list);
0971de7f
AV		 3488
3489 switch (e->type) {
3490 case QLA_EVT_AEN:
e315cd28 3491 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3492 e->u.aen.code, e->u.aen.data);
3493 break;
8a659571
AV		 3494 case QLA_EVT_IDC_ACK:
3495 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3496 break;
ac280b67
AV		 3497 case QLA_EVT_ASYNC_LOGIN:
3498 qla2x00_async_login(vha, e->u.logio.fcport,
3499 e->u.logio.data);
3500 break;
3501 case QLA_EVT_ASYNC_LOGIN_DONE:
3502 qla2x00_async_login_done(vha, e->u.logio.fcport,
3503 e->u.logio.data);
3504 break;
3505 case QLA_EVT_ASYNC_LOGOUT:
3506 qla2x00_async_logout(vha, e->u.logio.fcport);
3507 break;
3508 case QLA_EVT_ASYNC_LOGOUT_DONE:
3509 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3510 e->u.logio.data);
3511 break;
5ff1d584
AV		 3512 case QLA_EVT_ASYNC_ADISC:
3513 qla2x00_async_adisc(vha, e->u.logio.fcport,
3514 e->u.logio.data);
3515 break;
3516 case QLA_EVT_ASYNC_ADISC_DONE:
3517 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3518 e->u.logio.data);
3519 break;
3420d36c
AV		 3520 case QLA_EVT_UEVENT:
3521 qla2x00_uevent_emit(vha, e->u.uevent.code);
3522 break;
0971de7f
AV		 3523 }
3524 if (e->flags & QLA_EVT_FLAG_FREE)
3525 kfree(e);
feafb7b1
AE		 3526
3527 /* For each work completed decrement vha ref count */
3528 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3529 }
e315cd28 3530}
f999f4c1 3531
e315cd28
AC		 3532/* Relogins all the fcports of a vport
3533 * Context: dpc thread
3534 */
3535void qla2x00_relogin(struct scsi_qla_host *vha)
3536{
3537 fc_port_t *fcport;
c6b2fca8 3538 int status;
e315cd28
AC		 3539 uint16_t next_loopid = 0;
3540 struct qla_hw_data *ha = vha->hw;
ac280b67 3541 uint16_t data[2];
e315cd28
AC		 3542
3543 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3544 /*
3545 * If the port is not ONLINE then try to login
3546 * to it if we haven't run out of retries.
3547 */
5ff1d584
AV		 3548 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3549 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3550 fcport->login_retry--;
e315cd28 3551 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3552 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3553 ha->isp_ops->fabric_logout(vha,
3554 fcport->loop_id,
3555 fcport->d_id.b.domain,
3556 fcport->d_id.b.area,
3557 fcport->d_id.b.al_pa);
3558
03bcfb57
JC		 3559 if (fcport->loop_id == FC_NO_LOOP_ID) {
3560 fcport->loop_id = next_loopid =
3561 ha->min_external_loopid;
3562 status = qla2x00_find_new_loop_id(
3563 vha, fcport);
3564 if (status != QLA_SUCCESS) {
3565 /* Ran out of IDs to use */
3566 break;
3567 }
3568 }
3569
ac280b67 3570 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3571 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3572 data[0] = 0;
3573 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3574 status = qla2x00_post_async_login_work(
3575 vha, fcport, data);
3576 if (status == QLA_SUCCESS)
3577 continue;
3578 /* Attempt a retry. */
3579 status = 1;
3580 } else
3581 status = qla2x00_fabric_login(vha,
3582 fcport, &next_loopid);
e315cd28
AC		 3583 } else
3584 status = qla2x00_local_device_login(vha,
3585 fcport);
3586
e315cd28
AC		 3587 if (status == QLA_SUCCESS) {
3588 fcport->old_loop_id = fcport->loop_id;
3589
7c3df132
SK		 3590 ql_dbg(ql_dbg_disc, vha, 0x2003,
3591 "Port login OK: logged in ID 0x%x.\n",
3592 fcport->loop_id);
e315cd28
AC		 3593
3594 qla2x00_update_fcport(vha, fcport);
3595
3596 } else if (status == 1) {
3597 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3598 /* retry the login again */
7c3df132
SK		 3599 ql_dbg(ql_dbg_disc, vha, 0x2007,
3600 "Retrying %d login again loop_id 0x%x.\n",
3601 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3602 } else {
3603 fcport->login_retry = 0;
3604 }
3605
3606 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3607 fcport->loop_id = FC_NO_LOOP_ID;
3608 }
3609 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3610 break;
0971de7f 3611 }
0971de7f
AV		 3612}
3613
1da177e4
LT		 3614/**************************************************************************
3615* qla2x00_do_dpc
3616* This kernel thread is a task that is schedule by the interrupt handler
3617* to perform the background processing for interrupts.
3618*
3619* Notes:
3620* This task always run in the context of a kernel thread. It
3621* is kick-off by the driver's detect code and starts up
3622* up one per adapter. It immediately goes to sleep and waits for
3623* some fibre event. When either the interrupt handler or
3624* the timer routine detects a event it will one of the task
3625* bits then wake us up.
3626**************************************************************************/
3627static int
3628qla2x00_do_dpc(void *data)
3629{
2c3dfe3f 3630 int rval;
e315cd28
AC		 3631 scsi_qla_host_t *base_vha;
3632 struct qla_hw_data *ha;
1da177e4 3633
e315cd28
AC		 3634 ha = (struct qla_hw_data *)data;
3635 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 3636
1da177e4
LT		 3637 set_user_nice(current, -20);
3638
563585ec 3639 set_current_state(TASK_INTERRUPTIBLE);
39a11240 3640 while (!kthread_should_stop()) {
7c3df132
SK		 3641 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3642 "DPC handler sleeping.\n");
1da177e4 3643
39a11240
CH		 3644 schedule();
3645 __set_current_state(TASK_RUNNING);
1da177e4 3646
c142caf0
AV		 3647 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
3648 goto end_loop;
1da177e4 3649
85880801 3650 if (ha->flags.eeh_busy) {
7c3df132
SK		 3651 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3652 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 3653 goto end_loop;
85880801
AV		 3654 }
3655
1da177e4
LT		 3656 ha->dpc_active = 1;
3657
c142caf0
AV		 3658 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3659 "DPC handler waking up.\n");
3660 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3661 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
1da177e4 3662
e315cd28 3663 qla2x00_do_work(base_vha);
0971de7f 3664
a9083016
GM		 3665 if (IS_QLA82XX(ha)) {
3666 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3667 &base_vha->dpc_flags)) {
3668 qla82xx_idc_lock(ha);
3669 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3670 QLA82XX_DEV_FAILED);
3671 qla82xx_idc_unlock(ha);
7c3df132
SK		 3672 ql_log(ql_log_info, base_vha, 0x4004,
3673 "HW State: FAILED.\n");
a9083016
GM		 3674 qla82xx_device_state_handler(base_vha);
3675 continue;
3676 }
3677
3678 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3679 &base_vha->dpc_flags)) {
3680
7c3df132
SK		 3681 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3682 "FCoE context reset scheduled.\n");
a9083016
GM		 3683 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3684 &base_vha->dpc_flags))) {
3685 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3686 /* FCoE-ctx reset failed.
3687 * Escalate to chip-reset
3688 */
3689 set_bit(ISP_ABORT_NEEDED,
3690 &base_vha->dpc_flags);
3691 }
3692 clear_bit(ABORT_ISP_ACTIVE,
3693 &base_vha->dpc_flags);
3694 }
3695
7c3df132
SK		 3696 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3697 "FCoE context reset end.\n");
a9083016
GM		 3698 }
3699 }
3700
e315cd28
AC		 3701 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3702 &base_vha->dpc_flags)) {
1da177e4 3703
7c3df132
SK		 3704 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3705 "ISP abort scheduled.\n");
1da177e4 3706 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 3707 &base_vha->dpc_flags))) {
1da177e4 3708
a9083016 3709 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 3710 /* failed. retry later */
3711 set_bit(ISP_ABORT_NEEDED,
e315cd28 3712 &base_vha->dpc_flags);
99363ef8 3713 }
e315cd28
AC		 3714 clear_bit(ABORT_ISP_ACTIVE,
3715 &base_vha->dpc_flags);
99363ef8
SJ		 3716 }
3717
7c3df132
SK		 3718 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3719 "ISP abort end.\n");
1da177e4
LT		 3720 }
3721
e315cd28
AC		 3722 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3723 qla2x00_update_fcports(base_vha);
3724 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 3725 }
d97994dc 3726
579d12b5 3727 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 3728 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3729 "Quiescence mode scheduled.\n");
579d12b5
SK		 3730 qla82xx_device_state_handler(base_vha);
3731 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3732 if (!ha->flags.quiesce_owner) {
3733 qla2x00_perform_loop_resync(base_vha);
3734
3735 qla82xx_idc_lock(ha);
3736 qla82xx_clear_qsnt_ready(base_vha);
3737 qla82xx_idc_unlock(ha);
3738 }
7c3df132
SK		 3739 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3740 "Quiescence mode end.\n");
579d12b5
SK		 3741 }
3742
e315cd28
AC		 3743 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3744 &base_vha->dpc_flags) &&
3745 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 3746
7c3df132
SK		 3747 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3748 "Reset marker scheduled.\n");
e315cd28
AC		 3749 qla2x00_rst_aen(base_vha);
3750 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 3751 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3752 "Reset marker end.\n");
1da177e4
LT		 3753 }
3754
3755 /* Retry each device up to login retry count */
e315cd28
AC		 3756 if ((test_and_clear_bit(RELOGIN_NEEDED,
3757 &base_vha->dpc_flags)) &&
3758 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3759 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 3760
7c3df132
SK		 3761 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3762 "Relogin scheduled.\n");
e315cd28 3763 qla2x00_relogin(base_vha);
7c3df132
SK		 3764 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3765 "Relogin end.\n");
1da177e4
LT		 3766 }
3767
e315cd28
AC		 3768 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3769 &base_vha->dpc_flags)) {
1da177e4 3770
7c3df132
SK		 3771 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3772 "Loop resync scheduled.\n");
1da177e4
LT		 3773
3774 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 3775 &base_vha->dpc_flags))) {
1da177e4 3776
e315cd28 3777 rval = qla2x00_loop_resync(base_vha);
1da177e4 3778
e315cd28
AC		 3779 clear_bit(LOOP_RESYNC_ACTIVE,
3780 &base_vha->dpc_flags);
1da177e4
LT		 3781 }
3782
7c3df132
SK		 3783 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3784 "Loop resync end.\n");
1da177e4
LT		 3785 }
3786
e315cd28
AC		 3787 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3788 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3789 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3790 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 3791 }
3792
1da177e4 3793 if (!ha->interrupts_on)
fd34f556 3794 ha->isp_ops->enable_intrs(ha);
1da177e4 3795
e315cd28
AC		 3796 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3797 &base_vha->dpc_flags))
3798 ha->isp_ops->beacon_blink(base_vha);
f6df144c 3799
e315cd28 3800 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 3801
1da177e4 3802 ha->dpc_active = 0;
c142caf0 3803end_loop:
563585ec 3804 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 3805 } /* End of while(1) */
563585ec 3806 __set_current_state(TASK_RUNNING);
1da177e4 3807
7c3df132
SK		 3808 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3809 "DPC handler exiting.\n");
1da177e4
LT		 3810
3811 /*
3812 * Make sure that nobody tries to wake us up again.
3813 */
1da177e4
LT		 3814 ha->dpc_active = 0;
3815
ac280b67
AV		 3816 /* Cleanup any residual CTX SRBs. */
3817 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3818
39a11240
CH		 3819 return 0;
3820}
3821
3822void
e315cd28 3823qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 3824{
e315cd28 3825 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 3826 struct task_struct *t = ha->dpc_thread;
3827
e315cd28 3828 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 3829 wake_up_process(t);
1da177e4
LT		 3830}
3831
1da177e4
LT		 3832/*
3833* qla2x00_rst_aen
3834* Processes asynchronous reset.
3835*
3836* Input:
3837* ha = adapter block pointer.
3838*/
3839static void
e315cd28 3840qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 3841{
e315cd28
AC		 3842 if (vha->flags.online && !vha->flags.reset_active &&
3843 !atomic_read(&vha->loop_down_timer) &&
3844 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 3845 do {
e315cd28 3846 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3847
3848 /*
3849 * Issue marker command only when we are going to start
3850 * the I/O.
3851 */
e315cd28
AC		 3852 vha->marker_needed = 1;
3853 } while (!atomic_read(&vha->loop_down_timer) &&
3854 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 3855 }
3856}
3857
1da177e4
LT		 3858/**************************************************************************
3859* qla2x00_timer
3860*
3861* Description:
3862* One second timer
3863*
3864* Context: Interrupt
3865***************************************************************************/
2c3dfe3f 3866void
e315cd28 3867qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 3868{
1da177e4 3869 unsigned long cpu_flags = 0;
1da177e4
LT		 3870 int start_dpc = 0;
3871 int index;
3872 srb_t *sp;
85880801 3873 uint16_t w;
e315cd28 3874 struct qla_hw_data *ha = vha->hw;
73208dfd 3875 struct req_que *req;
85880801 3876
a5b36321 3877 if (ha->flags.eeh_busy) {
7c3df132
SK		 3878 ql_dbg(ql_dbg_timer, vha, 0x6000,
3879 "EEH = %d, restarting timer.\n",
3880 ha->flags.eeh_busy);
a5b36321
LC		 3881 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3882 return;
3883 }
3884
85880801
AV		 3885 /* Hardware read to raise pending EEH errors during mailbox waits. */
3886 if (!pci_channel_offline(ha->pdev))
3887 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 3888
cefcaba6
SK		 3889 /* Make sure qla82xx_watchdog is run only for physical port */
3890 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 3891 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3892 start_dpc++;
3893 qla82xx_watchdog(vha);
3894 }
3895
1da177e4 3896 /* Loop down handler. */
e315cd28 3897 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 3898 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3899 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 3900 && vha->flags.online) {
1da177e4 3901
e315cd28
AC		 3902 if (atomic_read(&vha->loop_down_timer) ==
3903 vha->loop_down_abort_time) {
1da177e4 3904
7c3df132
SK		 3905 ql_log(ql_log_info, vha, 0x6008,
3906 "Loop down - aborting the queues before time expires.\n");
1da177e4 3907
e315cd28
AC		 3908 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3909 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 3910
f08b7251
AV		 3911 /*
3912 * Schedule an ISP abort to return any FCP2-device
3913 * commands.
3914 */
2c3dfe3f 3915 /* NPIV - scan physical port only */
e315cd28 3916 if (!vha->vp_idx) {
2c3dfe3f
SJ		 3917 spin_lock_irqsave(&ha->hardware_lock,
3918 cpu_flags);
73208dfd 3919 req = ha->req_q_map[0];
2c3dfe3f
SJ		 3920 for (index = 1;
3921 index < MAX_OUTSTANDING_COMMANDS;
3922 index++) {
3923 fc_port_t *sfcp;
3924
e315cd28 3925 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 3926 if (!sp)
3927 continue;
9ba56b95 3928 if (sp->type != SRB_SCSI_CMD)
cf53b069 3929 continue;
2c3dfe3f 3930 sfcp = sp->fcport;
f08b7251 3931 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 3932 continue;
bdf79621 3933
8f7daead
GM		 3934 if (IS_QLA82XX(ha))
3935 set_bit(FCOE_CTX_RESET_NEEDED,
3936 &vha->dpc_flags);
3937 else
3938 set_bit(ISP_ABORT_NEEDED,
e315cd28 3939 &vha->dpc_flags);
2c3dfe3f
SJ		 3940 break;
3941 }
3942 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 3943 cpu_flags);
1da177e4 3944 }
1da177e4
LT		 3945 start_dpc++;
3946 }
3947
3948 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 3949 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 3950 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 3951 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 3952 "Loop down - aborting ISP.\n");
3953
8f7daead
GM		 3954 if (IS_QLA82XX(ha))
3955 set_bit(FCOE_CTX_RESET_NEEDED,
3956 &vha->dpc_flags);
3957 else
3958 set_bit(ISP_ABORT_NEEDED,
3959 &vha->dpc_flags);
1da177e4
LT		 3960 }
3961 }
7c3df132
SK		 3962 ql_dbg(ql_dbg_timer, vha, 0x600a,
3963 "Loop down - seconds remaining %d.\n",
3964 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 3965 }
3966
cefcaba6
SK		 3967 /* Check if beacon LED needs to be blinked for physical host only */
3968 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 3969 /* There is no beacon_blink function for ISP82xx */
3970 if (!IS_QLA82XX(ha)) {
3971 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
3972 start_dpc++;
3973 }
f6df144c
AV		 3974 }
3975
550bf57d 3976 /* Process any deferred work. */
e315cd28 3977 if (!list_empty(&vha->work_list))
550bf57d
AV		 3978 start_dpc++;
3979
1da177e4 3980 /* Schedule the DPC routine if needed */
e315cd28
AC		 3981 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3982 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3983 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 3984 start_dpc ||
e315cd28
AC		 3985 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3986 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 3987 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3988 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 3989 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 3990 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3991 ql_dbg(ql_dbg_timer, vha, 0x600b,
3992 "isp_abort_needed=%d loop_resync_needed=%d "
3993 "fcport_update_needed=%d start_dpc=%d "
3994 "reset_marker_needed=%d",
3995 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3996 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3997 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3998 start_dpc,
3999 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
4000 ql_dbg(ql_dbg_timer, vha, 0x600c,
4001 "beacon_blink_needed=%d isp_unrecoverable=%d "
4002 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
4003 "relogin_needed=%d.\n",
4004 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
4005 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
4006 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
4007 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
4008 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 4009 qla2xxx_wake_dpc(vha);
7c3df132 4010 }
1da177e4 4011
e315cd28 4012 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 4013}
4014
5433383e
AV		 4015/* Firmware interface routines. */
4016
6246b8a1 4017#define FW_BLOBS 10
5433383e
AV		 4018#define FW_ISP21XX 0
4019#define FW_ISP22XX 1
4020#define FW_ISP2300 2
4021#define FW_ISP2322 3
48c02fde 4022#define FW_ISP24XX 4
c3a2f0df 4023#define FW_ISP25XX 5
3a03eb79 4024#define FW_ISP81XX 6
a9083016 4025#define FW_ISP82XX 7
6246b8a1
GM		 4026#define FW_ISP2031 8
4027#define FW_ISP8031 9
5433383e 4028
bb8ee499
AV		 4029#define FW_FILE_ISP21XX "ql2100_fw.bin"
4030#define FW_FILE_ISP22XX "ql2200_fw.bin"
4031#define FW_FILE_ISP2300 "ql2300_fw.bin"
4032#define FW_FILE_ISP2322 "ql2322_fw.bin"
4033#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 4034#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 4035#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 4036#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 4037#define FW_FILE_ISP2031 "ql2600_fw.bin"
4038#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 4039
e1e82b6f 4040static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 4041
4042static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 4043 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
4044 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
4045 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
4046 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
4047 { .name = FW_FILE_ISP24XX, },
c3a2f0df 4048 { .name = FW_FILE_ISP25XX, },
3a03eb79 4049 { .name = FW_FILE_ISP81XX, },
a9083016 4050 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 4051 { .name = FW_FILE_ISP2031, },
4052 { .name = FW_FILE_ISP8031, },
5433383e
AV		 4053};
4054
4055struct fw_blob *
e315cd28 4056qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 4057{
e315cd28 4058 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 4059 struct fw_blob *blob;
4060
5433383e
AV		 4061 if (IS_QLA2100(ha)) {
4062 blob = &qla_fw_blobs[FW_ISP21XX];
4063 } else if (IS_QLA2200(ha)) {
4064 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 4065 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 4066 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 4067 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 4068 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 4069 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 4070 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 4071 } else if (IS_QLA25XX(ha)) {
4072 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 4073 } else if (IS_QLA81XX(ha)) {
4074 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 4075 } else if (IS_QLA82XX(ha)) {
4076 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 4077 } else if (IS_QLA2031(ha)) {
4078 blob = &qla_fw_blobs[FW_ISP2031];
4079 } else if (IS_QLA8031(ha)) {
4080 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 4081 } else {
4082 return NULL;
5433383e
AV		 4083 }
4084
e1e82b6f 4085 mutex_lock(&qla_fw_lock);
5433383e
AV		 4086 if (blob->fw)
4087 goto out;
4088
4089 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4090 ql_log(ql_log_warn, vha, 0x0063,
4091 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4092 blob->fw = NULL;
4093 blob = NULL;
4094 goto out;
4095 }
4096
4097out:
e1e82b6f 4098 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4099 return blob;
4100}
4101
4102static void
4103qla2x00_release_firmware(void)
4104{
4105 int idx;
4106
e1e82b6f 4107 mutex_lock(&qla_fw_lock);
5433383e
AV		 4108 for (idx = 0; idx < FW_BLOBS; idx++)
4109 if (qla_fw_blobs[idx].fw)
4110 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4111 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4112}
4113
14e660e6
SJ		 4114static pci_ers_result_t
4115qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4116{
85880801
AV		 4117 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4118 struct qla_hw_data *ha = vha->hw;
4119
7c3df132
SK		 4120 ql_dbg(ql_dbg_aer, vha, 0x9000,
4121 "PCI error detected, state %x.\n", state);
b9b12f73 4122
14e660e6
SJ		 4123 switch (state) {
4124 case pci_channel_io_normal:
85880801 4125 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4126 return PCI_ERS_RESULT_CAN_RECOVER;
4127 case pci_channel_io_frozen:
85880801 4128 ha->flags.eeh_busy = 1;
a5b36321
LC		 4129 /* For ISP82XX complete any pending mailbox cmd */
4130 if (IS_QLA82XX(ha)) {
7190575f 4131 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 4132 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
4133 qla82xx_clear_pending_mbx(vha);
a5b36321 4134 }
90a86fc0 4135 qla2x00_free_irqs(vha);
14e660e6 4136 pci_disable_device(pdev);
bddd2d65
LC		 4137 /* Return back all IOs */
4138 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4139 return PCI_ERS_RESULT_NEED_RESET;
4140 case pci_channel_io_perm_failure:
85880801
AV		 4141 ha->flags.pci_channel_io_perm_failure = 1;
4142 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4143 return PCI_ERS_RESULT_DISCONNECT;
4144 }
4145 return PCI_ERS_RESULT_NEED_RESET;
4146}
4147
4148static pci_ers_result_t
4149qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4150{
4151 int risc_paused = 0;
4152 uint32_t stat;
4153 unsigned long flags;
e315cd28
AC		 4154 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4155 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4156 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4157 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4158
bcc5b6d3
SK		 4159 if (IS_QLA82XX(ha))
4160 return PCI_ERS_RESULT_RECOVERED;
4161
14e660e6
SJ		 4162 spin_lock_irqsave(&ha->hardware_lock, flags);
4163 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4164 stat = RD_REG_DWORD(&reg->hccr);
4165 if (stat & HCCR_RISC_PAUSE)
4166 risc_paused = 1;
4167 } else if (IS_QLA23XX(ha)) {
4168 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4169 if (stat & HSR_RISC_PAUSED)
4170 risc_paused = 1;
4171 } else if (IS_FWI2_CAPABLE(ha)) {
4172 stat = RD_REG_DWORD(&reg24->host_status);
4173 if (stat & HSRX_RISC_PAUSED)
4174 risc_paused = 1;
4175 }
4176 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4177
4178 if (risc_paused) {
7c3df132
SK		 4179 ql_log(ql_log_info, base_vha, 0x9003,
4180 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4181 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4182
4183 return PCI_ERS_RESULT_NEED_RESET;
4184 } else
4185 return PCI_ERS_RESULT_RECOVERED;
4186}
4187
a5b36321
LC		 4188uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4189{
4190 uint32_t rval = QLA_FUNCTION_FAILED;
4191 uint32_t drv_active = 0;
4192 struct qla_hw_data *ha = base_vha->hw;
4193 int fn;
4194 struct pci_dev *other_pdev = NULL;
4195
7c3df132
SK		 4196 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4197 "Entered %s.\n", __func__);
a5b36321
LC		 4198
4199 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4200
4201 if (base_vha->flags.online) {
4202 /* Abort all outstanding commands,
4203 * so as to be requeued later */
4204 qla2x00_abort_isp_cleanup(base_vha);
4205 }
4206
4207
4208 fn = PCI_FUNC(ha->pdev->devfn);
4209 while (fn > 0) {
4210 fn--;
7c3df132
SK		 4211 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4212 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 4213 other_pdev =
4214 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4215 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4216 fn));
4217
4218 if (!other_pdev)
4219 continue;
4220 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 4221 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4222 "Found PCI func available and enable at 0x%x.\n",
4223 fn);
a5b36321
LC		 4224 pci_dev_put(other_pdev);
4225 break;
4226 }
4227 pci_dev_put(other_pdev);
4228 }
4229
4230 if (!fn) {
4231 /* Reset owner */
7c3df132
SK		 4232 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4233 "This devfn is reset owner = 0x%x.\n",
4234 ha->pdev->devfn);
a5b36321
LC		 4235 qla82xx_idc_lock(ha);
4236
4237 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4238 QLA82XX_DEV_INITIALIZING);
4239
4240 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4241 QLA82XX_IDC_VERSION);
4242
4243 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 4244 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4245 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 4246
4247 qla82xx_idc_unlock(ha);
4248 /* Reset if device is not already reset
4249 * drv_active would be 0 if a reset has already been done
4250 */
4251 if (drv_active)
4252 rval = qla82xx_start_firmware(base_vha);
4253 else
4254 rval = QLA_SUCCESS;
4255 qla82xx_idc_lock(ha);
4256
4257 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4258 ql_log(ql_log_info, base_vha, 0x900b,
4259 "HW State: FAILED.\n");
a5b36321
LC		 4260 qla82xx_clear_drv_active(ha);
4261 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4262 QLA82XX_DEV_FAILED);
4263 } else {
7c3df132
SK		 4264 ql_log(ql_log_info, base_vha, 0x900c,
4265 "HW State: READY.\n");
a5b36321
LC		 4266 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4267 QLA82XX_DEV_READY);
4268 qla82xx_idc_unlock(ha);
7190575f 4269 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4270 rval = qla82xx_restart_isp(base_vha);
4271 qla82xx_idc_lock(ha);
4272 /* Clear driver state register */
4273 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4274 qla82xx_set_drv_active(base_vha);
4275 }
4276 qla82xx_idc_unlock(ha);
4277 } else {
7c3df132
SK		 4278 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4279 "This devfn is not reset owner = 0x%x.\n",
4280 ha->pdev->devfn);
a5b36321
LC		 4281 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4282 QLA82XX_DEV_READY)) {
7190575f 4283 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4284 rval = qla82xx_restart_isp(base_vha);
4285 qla82xx_idc_lock(ha);
4286 qla82xx_set_drv_active(base_vha);
4287 qla82xx_idc_unlock(ha);
4288 }
4289 }
4290 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4291
4292 return rval;
4293}
4294
14e660e6
SJ		 4295static pci_ers_result_t
4296qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4297{
4298 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 4299 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4300 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 4301 struct rsp_que *rsp;
4302 int rc, retries = 10;
09483916 4303
7c3df132
SK		 4304 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4305 "Slot Reset.\n");
85880801 4306
90a86fc0
JC		 4307 /* Workaround: qla2xxx driver which access hardware earlier
4308 * needs error state to be pci_channel_io_online.
4309 * Otherwise mailbox command timesout.
4310 */
4311 pdev->error_state = pci_channel_io_normal;
4312
4313 pci_restore_state(pdev);
4314
8c1496bd
RL		 4315 /* pci_restore_state() clears the saved_state flag of the device
4316 * save restored state which resets saved_state flag
4317 */
4318 pci_save_state(pdev);
4319
09483916
BH		 4320 if (ha->mem_only)
4321 rc = pci_enable_device_mem(pdev);
4322 else
4323 rc = pci_enable_device(pdev);
14e660e6 4324
09483916 4325 if (rc) {
7c3df132 4326 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 4327 "Can't re-enable PCI device after reset.\n");
a5b36321 4328 goto exit_slot_reset;
14e660e6 4329 }
14e660e6 4330
90a86fc0
JC		 4331 rsp = ha->rsp_q_map[0];
4332 if (qla2x00_request_irqs(ha, rsp))
a5b36321 4333 goto exit_slot_reset;
90a86fc0 4334
e315cd28 4335 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 4336 goto exit_slot_reset;
4337
4338 if (IS_QLA82XX(ha)) {
4339 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4340 ret = PCI_ERS_RESULT_RECOVERED;
4341 goto exit_slot_reset;
4342 } else
4343 goto exit_slot_reset;
4344 }
14e660e6 4345
90a86fc0
JC		 4346 while (ha->flags.mbox_busy && retries--)
4347 msleep(1000);
85880801 4348
e315cd28 4349 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 4350 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 4351 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 4352 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 4353
90a86fc0 4354
a5b36321 4355exit_slot_reset:
7c3df132
SK		 4356 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4357 "slot_reset return %x.\n", ret);
85880801 4358
14e660e6
SJ		 4359 return ret;
4360}
4361
4362static void
4363qla2xxx_pci_resume(struct pci_dev *pdev)
4364{
e315cd28
AC		 4365 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4366 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4367 int ret;
4368
7c3df132
SK		 4369 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4370 "pci_resume.\n");
85880801 4371
e315cd28 4372 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 4373 if (ret != QLA_SUCCESS) {
7c3df132
SK		 4374 ql_log(ql_log_fatal, base_vha, 0x9002,
4375 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 4376 }
85880801 4377
3e46f031
LC		 4378 pci_cleanup_aer_uncorrect_error_status(pdev);
4379
85880801 4380 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4381}
4382
4383static struct pci_error_handlers qla2xxx_err_handler = {
4384 .error_detected = qla2xxx_pci_error_detected,
4385 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4386 .slot_reset = qla2xxx_pci_slot_reset,
4387 .resume = qla2xxx_pci_resume,
4388};
4389
5433383e 4390static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 4391 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4392 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4393 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4394 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4395 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4396 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4397 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4398 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4399 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 4400 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 4401 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4402 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 4403 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 4404 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 4405 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 4406 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5433383e
AV		 4407 { 0 },
4408};
4409MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4410
fca29703 4411static struct pci_driver qla2xxx_pci_driver = {
cb63067a 4412 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 4413 .driver = {
4414 .owner = THIS_MODULE,
4415 },
fca29703 4416 .id_table = qla2xxx_pci_tbl,
7ee61397 4417 .probe = qla2x00_probe_one,
4c993f76 4418 .remove = qla2x00_remove_one,
e30d1756 4419 .shutdown = qla2x00_shutdown,
14e660e6 4420 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 4421};
4422
6a03b4cd
HZ		 4423static struct file_operations apidev_fops = {
4424 .owner = THIS_MODULE,
6038f373 4425 .llseek = noop_llseek,
6a03b4cd
HZ		 4426};
4427
1da177e4
LT		 4428/**
4429 * qla2x00_module_init - Module initialization.
4430 **/
4431static int __init
4432qla2x00_module_init(void)
4433{
fca29703
AV		 4434 int ret = 0;
4435
1da177e4 4436 /* Allocate cache for SRBs. */
354d6b21 4437 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 4438 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 4439 if (srb_cachep == NULL) {
7c3df132
SK		 4440 ql_log(ql_log_fatal, NULL, 0x0001,
4441 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 4442 return -ENOMEM;
4443 }
4444
4445 /* Derive version string. */
4446 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 4447 if (ql2xextended_error_logging)
0181944f
AV		 4448 strcat(qla2x00_version_str, "-debug");
4449
1c97a12a
AV		 4450 qla2xxx_transport_template =
4451 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 4452 if (!qla2xxx_transport_template) {
4453 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 4454 ql_log(ql_log_fatal, NULL, 0x0002,
4455 "fc_attach_transport failed...Failing load!.\n");
1da177e4 4456 return -ENODEV;
2c3dfe3f 4457 }
6a03b4cd
HZ		 4458
4459 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4460 if (apidev_major < 0) {
7c3df132
SK		 4461 ql_log(ql_log_fatal, NULL, 0x0003,
4462 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 4463 }
4464
2c3dfe3f
SJ		 4465 qla2xxx_transport_vport_template =
4466 fc_attach_transport(&qla2xxx_transport_vport_functions);
4467 if (!qla2xxx_transport_vport_template) {
4468 kmem_cache_destroy(srb_cachep);
4469 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 4470 ql_log(ql_log_fatal, NULL, 0x0004,
4471 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 4472 return -ENODEV;
2c3dfe3f 4473 }
7c3df132
SK		 4474 ql_log(ql_log_info, NULL, 0x0005,
4475 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 4476 qla2x00_version_str);
7ee61397 4477 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 4478 if (ret) {
4479 kmem_cache_destroy(srb_cachep);
4480 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4481 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 4482 ql_log(ql_log_fatal, NULL, 0x0006,
4483 "pci_register_driver failed...ret=%d Failing load!.\n",
4484 ret);
fca29703
AV		 4485 }
4486 return ret;
1da177e4
LT		 4487}
4488
4489/**
4490 * qla2x00_module_exit - Module cleanup.
4491 **/
4492static void __exit
4493qla2x00_module_exit(void)
4494{
6a03b4cd 4495 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 4496 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 4497 qla2x00_release_firmware();
354d6b21 4498 kmem_cache_destroy(srb_cachep);
a9083016
GM		 4499 if (ctx_cachep)
4500 kmem_cache_destroy(ctx_cachep);
1da177e4 4501 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4502 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 4503}
4504
4505module_init(qla2x00_module_init);
4506module_exit(qla2x00_module_exit);
4507
4508MODULE_AUTHOR("QLogic Corporation");
4509MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4510MODULE_LICENSE("GPL");
4511MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 4512MODULE_FIRMWARE(FW_FILE_ISP21XX);
4513MODULE_FIRMWARE(FW_FILE_ISP22XX);
4514MODULE_FIRMWARE(FW_FILE_ISP2300);
4515MODULE_FIRMWARE(FW_FILE_ISP2322);
4516MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 4517MODULE_FIRMWARE(FW_FILE_ISP25XX);
kernel source for telekom puls (alcatel/mediatek)