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[SCSI] zfcp: support for hardware data router
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22/*
23 * Driver version
24 */
25char qla2x00_version_str[40];
26
6a03b4cd
HZ		 27static int apidev_major;
28
1da177e4
LT		 29/*
30 * SRB allocation cache
31 */
e18b890b 32static struct kmem_cache *srb_cachep;
1da177e4 33
a9083016
GM		 34/*
35 * CT6 CTX allocation cache
36 */
37static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 38/*
39 * error level for logging
40 */
41int ql_errlev = ql_log_all;
a9083016 42
1da177e4 43int ql2xlogintimeout = 20;
f2019cb1 44module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
a7b61842 48int qlport_down_retry;
f2019cb1 49module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 50MODULE_PARM_DESC(qlport_down_retry,
900d9f98 51 "Maximum number of command retries to a port that returns "
1da177e4
LT		 52 "a PORT-DOWN status.");
53
1da177e4
LT		 54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
900d9f98 58 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
1da177e4 61int ql2xloginretrycount = 0;
f2019cb1 62module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
a7a167bf 66int ql2xallocfwdump = 1;
f2019cb1 67module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
11010fec 73int ql2xextended_error_logging;
27d94035 74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 75MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
86 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 87
a9083016 88int ql2xshiftctondsd = 6;
f2019cb1 89module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 90MODULE_PARM_DESC(ql2xshiftctondsd,
91 "Set to control shifting of command type processing "
92 "based on total number of SG elements.");
93
1da177e4
LT		 94static void qla2x00_free_device(scsi_qla_host_t *);
95
7e47e5ca 96int ql2xfdmienable=1;
f2019cb1 97module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 98MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 99 "Enables FDMI registrations. "
100 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 101
df7baa50
AV		 102#define MAX_Q_DEPTH 32
103static int ql2xmaxqdepth = MAX_Q_DEPTH;
104module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
105MODULE_PARM_DESC(ql2xmaxqdepth,
106 "Maximum queue depth to report for target devices.");
107
bad75002 108/* Do not change the value of this after module load */
8cb2049c 109int ql2xenabledif = 0;
bad75002
AE		 110module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
111MODULE_PARM_DESC(ql2xenabledif,
112 " Enable T10-CRC-DIF "
8cb2049c
AE		 113 " Default is 0 - No DIF Support. 1 - Enable it"
114 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 115
8cb2049c 116int ql2xenablehba_err_chk = 2;
bad75002
AE		 117module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
118MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 119 " Enable T10-CRC-DIF Error isolation by HBA:\n"
120 " Default is 1.\n"
121 " 0 -- Error isolation disabled\n"
122 " 1 -- Error isolation enabled only for DIX Type 0\n"
123 " 2 -- Error isolation enabled for all Types\n");
bad75002 124
e5896bd5 125int ql2xiidmaenable=1;
f2019cb1 126module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 127MODULE_PARM_DESC(ql2xiidmaenable,
128 "Enables iIDMA settings "
129 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
130
73208dfd 131int ql2xmaxqueues = 1;
f2019cb1 132module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 133MODULE_PARM_DESC(ql2xmaxqueues,
134 "Enables MQ settings "
ae68230c
JP		 135 "Default is 1 for single queue. Set it to number "
136 "of queues in MQ mode.");
68ca949c
AC		 137
138int ql2xmultique_tag;
f2019cb1 139module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 140MODULE_PARM_DESC(ql2xmultique_tag,
141 "Enables CPU affinity settings for the driver "
142 "Default is 0 for no affinity of request and response IO. "
143 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 144
145int ql2xfwloadbin;
f2019cb1 146module_param(ql2xfwloadbin, int, S_IRUGO);
e337d907 147MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 148 "Option to specify location from which to load ISP firmware:.\n"
149 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 150 " interface.\n"
151 " 1 -- load firmware from flash.\n"
152 " 0 -- use default semantics.\n");
153
ae97c91e 154int ql2xetsenable;
f2019cb1 155module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 156MODULE_PARM_DESC(ql2xetsenable,
157 "Enables firmware ETS burst."
158 "Default is 0 - skip ETS enablement.");
159
6907869d 160int ql2xdbwr = 1;
f2019cb1 161module_param(ql2xdbwr, int, S_IRUGO);
a9083016 162MODULE_PARM_DESC(ql2xdbwr,
7c3df132 163 "Option to specify scheme for request queue posting.\n"
a9083016
GM		 164 " 0 -- Regular doorbell.\n"
165 " 1 -- CAMRAM doorbell (faster).\n");
166
f4c496c1 167int ql2xtargetreset = 1;
f2019cb1 168module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 169MODULE_PARM_DESC(ql2xtargetreset,
170 "Enable target reset."
171 "Default is 1 - use hw defaults.");
172
4da26e16 173int ql2xgffidenable;
f2019cb1 174module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 175MODULE_PARM_DESC(ql2xgffidenable,
176 "Enables GFF_ID checks of port type. "
177 "Default is 0 - Do not use GFF_ID information.");
a9083016 178
3822263e 179int ql2xasynctmfenable;
f2019cb1 180module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 181MODULE_PARM_DESC(ql2xasynctmfenable,
182 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
183 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 184
185int ql2xdontresethba;
186module_param(ql2xdontresethba, int, S_IRUGO);
187MODULE_PARM_DESC(ql2xdontresethba,
7c3df132 188 "Option to specify reset behaviour.\n"
ed0de87c
GM		 189 " 0 (Default) -- Reset on failure.\n"
190 " 1 -- Do not reset on failure.\n");
191
82515920
AV		 192uint ql2xmaxlun = MAX_LUNS;
193module_param(ql2xmaxlun, uint, S_IRUGO);
194MODULE_PARM_DESC(ql2xmaxlun,
195 "Defines the maximum LU number to register with the SCSI "
196 "midlayer. Default is 65535.");
197
1da177e4 198/*
fa2a1ce5 199 * SCSI host template entry points
1da177e4
LT		 200 */
201static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 202static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 203static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
204static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 205static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 206static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 207static int qla2xxx_eh_abort(struct scsi_cmnd *);
208static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 209static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 210static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
211static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 212
e881a172 213static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 214static int qla2x00_change_queue_type(struct scsi_device *, int);
215
a5326f86 216struct scsi_host_template qla2xxx_driver_template = {
1da177e4 217 .module = THIS_MODULE,
cb63067a 218 .name = QLA2XXX_DRIVER_NAME,
a5326f86 219 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 220
221 .eh_abort_handler = qla2xxx_eh_abort,
222 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 223 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 224 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
225 .eh_host_reset_handler = qla2xxx_eh_host_reset,
226
227 .slave_configure = qla2xxx_slave_configure,
228
229 .slave_alloc = qla2xxx_slave_alloc,
230 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 231 .scan_finished = qla2xxx_scan_finished,
232 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 233 .change_queue_depth = qla2x00_change_queue_depth,
234 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 235 .this_id = -1,
236 .cmd_per_lun = 3,
237 .use_clustering = ENABLE_CLUSTERING,
238 .sg_tablesize = SG_ALL,
239
240 .max_sectors = 0xFFFF,
afb046e2 241 .shost_attrs = qla2x00_host_attrs,
fca29703
AV		 242};
243
1da177e4 244static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 245struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 246
1da177e4
LT		 247/* TODO Convert to inlines
248 *
249 * Timer routines
250 */
1da177e4 251
2c3dfe3f 252__inline__ void
e315cd28 253qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 254{
e315cd28
AC		 255 init_timer(&vha->timer);
256 vha->timer.expires = jiffies + interval * HZ;
257 vha->timer.data = (unsigned long)vha;
258 vha->timer.function = (void (*)(unsigned long))func;
259 add_timer(&vha->timer);
260 vha->timer_active = 1;
1da177e4
LT		 261}
262
263static inline void
e315cd28 264qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 265{
a9083016 266 /* Currently used for 82XX only. */
7c3df132
SK		 267 if (vha->device_flags & DFLG_DEV_FAILED) {
268 ql_dbg(ql_dbg_timer, vha, 0x600d,
269 "Device in a failed state, returning.\n");
a9083016 270 return;
7c3df132 271 }
a9083016 272
e315cd28 273 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 274}
275
a824ebb3 276static __inline__ void
e315cd28 277qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 278{
e315cd28
AC		 279 del_timer_sync(&vha->timer);
280 vha->timer_active = 0;
1da177e4
LT		 281}
282
1da177e4
LT		 283static int qla2x00_do_dpc(void *data);
284
285static void qla2x00_rst_aen(scsi_qla_host_t *);
286
73208dfd
AC		 287static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
288 struct req_que **, struct rsp_que **);
e30d1756 289static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28
AC		 290static void qla2x00_mem_free(struct qla_hw_data *);
291static void qla2x00_sp_free_dma(srb_t *);
1da177e4 292
1da177e4 293/* -------------------------------------------------------------------------- */
73208dfd
AC		 294static int qla2x00_alloc_queues(struct qla_hw_data *ha)
295{
7c3df132 296 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 297 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 298 GFP_KERNEL);
299 if (!ha->req_q_map) {
7c3df132
SK		 300 ql_log(ql_log_fatal, vha, 0x003b,
301 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 302 goto fail_req_map;
303 }
304
2afa19a9 305 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 306 GFP_KERNEL);
307 if (!ha->rsp_q_map) {
7c3df132
SK		 308 ql_log(ql_log_fatal, vha, 0x003c,
309 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 310 goto fail_rsp_map;
311 }
312 set_bit(0, ha->rsp_qid_map);
313 set_bit(0, ha->req_qid_map);
314 return 1;
315
316fail_rsp_map:
317 kfree(ha->req_q_map);
318 ha->req_q_map = NULL;
319fail_req_map:
320 return -ENOMEM;
321}
322
2afa19a9 323static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 324{
73208dfd
AC		 325 if (req && req->ring)
326 dma_free_coherent(&ha->pdev->dev,
327 (req->length + 1) * sizeof(request_t),
328 req->ring, req->dma);
329
330 kfree(req);
331 req = NULL;
332}
333
2afa19a9
AC		 334static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
335{
336 if (rsp && rsp->ring)
337 dma_free_coherent(&ha->pdev->dev,
338 (rsp->length + 1) * sizeof(response_t),
339 rsp->ring, rsp->dma);
340
341 kfree(rsp);
342 rsp = NULL;
343}
344
73208dfd
AC		 345static void qla2x00_free_queues(struct qla_hw_data *ha)
346{
347 struct req_que *req;
348 struct rsp_que *rsp;
349 int cnt;
350
2afa19a9 351 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 352 req = ha->req_q_map[cnt];
2afa19a9 353 qla2x00_free_req_que(ha, req);
73208dfd 354 }
73208dfd
AC		 355 kfree(ha->req_q_map);
356 ha->req_q_map = NULL;
2afa19a9
AC		 357
358 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
359 rsp = ha->rsp_q_map[cnt];
360 qla2x00_free_rsp_que(ha, rsp);
361 }
362 kfree(ha->rsp_q_map);
363 ha->rsp_q_map = NULL;
73208dfd
AC		 364}
365
68ca949c
AC		 366static int qla25xx_setup_mode(struct scsi_qla_host *vha)
367{
368 uint16_t options = 0;
369 int ques, req, ret;
370 struct qla_hw_data *ha = vha->hw;
371
7163ea81 372 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 373 ql_log(ql_log_warn, vha, 0x00d8,
374 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 375 goto fail;
376 }
68ca949c 377 if (ql2xmultique_tag) {
68ca949c
AC		 378 /* create a request queue for IO */
379 options |= BIT_7;
380 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
381 QLA_DEFAULT_QUE_QOS);
382 if (!req) {
7c3df132
SK		 383 ql_log(ql_log_warn, vha, 0x00e0,
384 "Failed to create request queue.\n");
68ca949c
AC		 385 goto fail;
386 }
278274d5 387 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 388 vha->req = ha->req_q_map[req];
389 options |= BIT_1;
390 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
391 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
392 if (!ret) {
7c3df132
SK		 393 ql_log(ql_log_warn, vha, 0x00e8,
394 "Failed to create response queue.\n");
68ca949c
AC		 395 goto fail2;
396 }
397 }
7163ea81 398 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 399 ql_dbg(ql_dbg_multiq, vha, 0xc007,
400 "CPU affinity mode enalbed, "
401 "no. of response queues:%d no. of request queues:%d.\n",
402 ha->max_rsp_queues, ha->max_req_queues);
403 ql_dbg(ql_dbg_init, vha, 0x00e9,
404 "CPU affinity mode enalbed, "
405 "no. of response queues:%d no. of request queues:%d.\n",
406 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 407 }
408 return 0;
409fail2:
410 qla25xx_delete_queues(vha);
7163ea81
AC		 411 destroy_workqueue(ha->wq);
412 ha->wq = NULL;
68ca949c
AC		 413fail:
414 ha->mqenable = 0;
7163ea81
AC		 415 kfree(ha->req_q_map);
416 kfree(ha->rsp_q_map);
417 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 418 return 1;
419}
420
1da177e4 421static char *
e315cd28 422qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 423{
e315cd28 424 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 425 static char *pci_bus_modes[] = {
426 "33", "66", "100", "133",
427 };
428 uint16_t pci_bus;
429
430 strcpy(str, "PCI");
431 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
432 if (pci_bus) {
433 strcat(str, "-X (");
434 strcat(str, pci_bus_modes[pci_bus]);
435 } else {
436 pci_bus = (ha->pci_attr & BIT_8) >> 8;
437 strcat(str, " (");
438 strcat(str, pci_bus_modes[pci_bus]);
439 }
440 strcat(str, " MHz)");
441
442 return (str);
443}
444
fca29703 445static char *
e315cd28 446qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 447{
448 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 449 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 450 uint32_t pci_bus;
451 int pcie_reg;
452
453 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
454 if (pcie_reg) {
455 char lwstr[6];
456 uint16_t pcie_lstat, lspeed, lwidth;
457
458 pcie_reg += 0x12;
459 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
460 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
461 lwidth = (pcie_lstat &
462 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
463
464 strcpy(str, "PCIe (");
465 if (lspeed == 1)
c87a0d8c 466 strcat(str, "2.5GT/s ");
c3a2f0df 467 else if (lspeed == 2)
c87a0d8c 468 strcat(str, "5.0GT/s ");
fca29703
AV		 469 else
470 strcat(str, "<unknown> ");
471 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
472 strcat(str, lwstr);
473
474 return str;
475 }
476
477 strcpy(str, "PCI");
478 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
479 if (pci_bus == 0 || pci_bus == 8) {
480 strcat(str, " (");
481 strcat(str, pci_bus_modes[pci_bus >> 3]);
482 } else {
483 strcat(str, "-X ");
484 if (pci_bus & BIT_2)
485 strcat(str, "Mode 2");
486 else
487 strcat(str, "Mode 1");
488 strcat(str, " (");
489 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
490 }
491 strcat(str, " MHz)");
492
493 return str;
494}
495
e5f82ab8 496static char *
e315cd28 497qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 498{
499 char un_str[10];
e315cd28 500 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 501
1da177e4
LT		 502 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
503 ha->fw_minor_version,
504 ha->fw_subminor_version);
505
506 if (ha->fw_attributes & BIT_9) {
507 strcat(str, "FLX");
508 return (str);
509 }
510
511 switch (ha->fw_attributes & 0xFF) {
512 case 0x7:
513 strcat(str, "EF");
514 break;
515 case 0x17:
516 strcat(str, "TP");
517 break;
518 case 0x37:
519 strcat(str, "IP");
520 break;
521 case 0x77:
522 strcat(str, "VI");
523 break;
524 default:
525 sprintf(un_str, "(%x)", ha->fw_attributes);
526 strcat(str, un_str);
527 break;
528 }
529 if (ha->fw_attributes & 0x100)
530 strcat(str, "X");
531
532 return (str);
533}
534
e5f82ab8 535static char *
e315cd28 536qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 537{
e315cd28 538 struct qla_hw_data *ha = vha->hw;
f0883ac6 539
3a03eb79
AV		 540 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
541 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 542 return str;
fca29703
AV		 543}
544
545static inline srb_t *
e315cd28 546qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
f5e3e40b 547 struct scsi_cmnd *cmd)
fca29703
AV		 548{
549 srb_t *sp;
e315cd28 550 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 551
552 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
7c3df132
SK		 553 if (!sp) {
554 ql_log(ql_log_warn, vha, 0x3006,
555 "Memory allocation failed for sp.\n");
fca29703 556 return sp;
7c3df132 557 }
fca29703 558
083a469d 559 atomic_set(&sp->ref_count, 1);
fca29703
AV		 560 sp->fcport = fcport;
561 sp->cmd = cmd;
562 sp->flags = 0;
563 CMD_SP(cmd) = (void *)sp;
cf53b069 564 sp->ctx = NULL;
fca29703
AV		 565
566 return sp;
567}
568
1da177e4 569static int
f5e3e40b 570qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 571{
134ae078 572 scsi_qla_host_t *vha = shost_priv(host);
fca29703 573 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 574 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 575 struct qla_hw_data *ha = vha->hw;
576 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 577 srb_t *sp;
578 int rval;
579
85880801 580 if (ha->flags.eeh_busy) {
7c3df132
SK		 581 if (ha->flags.pci_channel_io_perm_failure) {
582 ql_dbg(ql_dbg_io, vha, 0x3001,
583 "PCI Channel IO permanent failure, exiting "
584 "cmd=%p.\n", cmd);
b9b12f73 585 cmd->result = DID_NO_CONNECT << 16;
7c3df132
SK		 586 } else {
587 ql_dbg(ql_dbg_io, vha, 0x3002,
588 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 589 cmd->result = DID_REQUEUE << 16;
7c3df132 590 }
14e660e6
SJ		 591 goto qc24_fail_command;
592 }
593
19a7b4ae
JSEC		 594 rval = fc_remote_port_chkready(rport);
595 if (rval) {
596 cmd->result = rval;
7c3df132
SK		 597 ql_dbg(ql_dbg_io, vha, 0x3003,
598 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
599 cmd, rval);
fca29703
AV		 600 goto qc24_fail_command;
601 }
602
bad75002
AE		 603 if (!vha->flags.difdix_supported &&
604 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 605 ql_dbg(ql_dbg_io, vha, 0x3004,
606 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
607 cmd);
bad75002
AE		 608 cmd->result = DID_NO_CONNECT << 16;
609 goto qc24_fail_command;
610 }
fca29703
AV		 611 if (atomic_read(&fcport->state) != FCS_ONLINE) {
612 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 613 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 614 ql_dbg(ql_dbg_io, vha, 0x3005,
615 "Returning DNC, fcport_state=%d loop_state=%d.\n",
616 atomic_read(&fcport->state),
617 atomic_read(&base_vha->loop_state));
fca29703
AV		 618 cmd->result = DID_NO_CONNECT << 16;
619 goto qc24_fail_command;
620 }
7b594131 621 goto qc24_target_busy;
fca29703
AV		 622 }
623
f5e3e40b 624 sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
fca29703 625 if (!sp)
f5e3e40b 626 goto qc24_host_busy;
fca29703 627
e315cd28 628 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 629 if (rval != QLA_SUCCESS) {
630 ql_dbg(ql_dbg_io, vha, 0x3013,
631 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 632 goto qc24_host_busy_free_sp;
7c3df132 633 }
fca29703 634
fca29703
AV		 635 return 0;
636
637qc24_host_busy_free_sp:
e315cd28
AC		 638 qla2x00_sp_free_dma(sp);
639 mempool_free(sp, ha->srb_mempool);
fca29703 640
f5e3e40b 641qc24_host_busy:
fca29703
AV		 642 return SCSI_MLQUEUE_HOST_BUSY;
643
7b594131
MC		 644qc24_target_busy:
645 return SCSI_MLQUEUE_TARGET_BUSY;
646
fca29703 647qc24_fail_command:
f5e3e40b 648 cmd->scsi_done(cmd);
fca29703
AV		 649
650 return 0;
651}
652
1da177e4
LT		 653/*
654 * qla2x00_eh_wait_on_command
655 * Waits for the command to be returned by the Firmware for some
656 * max time.
657 *
658 * Input:
1da177e4 659 * cmd = Scsi Command to wait on.
1da177e4
LT		 660 *
661 * Return:
662 * Not Found : 0
663 * Found : 1
664 */
665static int
e315cd28 666qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 667{
fe74c71f
AV		 668#define ABORT_POLLING_PERIOD 1000
669#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 670 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 671 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
672 struct qla_hw_data *ha = vha->hw;
f4f051eb 673 int ret = QLA_SUCCESS;
1da177e4 674
85880801 675 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 676 ql_dbg(ql_dbg_taskm, vha, 0x8005,
677 "Return:eh_wait.\n");
85880801
AV		 678 return ret;
679 }
680
d970432c 681 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 682 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 683 }
684 if (CMD_SP(cmd))
685 ret = QLA_FUNCTION_FAILED;
1da177e4 686
f4f051eb 687 return ret;
1da177e4
LT		 688}
689
690/*
691 * qla2x00_wait_for_hba_online
fa2a1ce5 692 * Wait till the HBA is online after going through
1da177e4
LT		 693 * <= MAX_RETRIES_OF_ISP_ABORT or
694 * finally HBA is disabled ie marked offline
695 *
696 * Input:
697 * ha - pointer to host adapter structure
fa2a1ce5
AV		 698 *
699 * Note:
1da177e4
LT		 700 * Does context switching-Release SPIN_LOCK
701 * (if any) before calling this routine.
702 *
703 * Return:
704 * Success (Adapter is online) : 0
705 * Failed (Adapter is offline/disabled) : 1
706 */
854165f4 707int
e315cd28 708qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 709{
fca29703
AV		 710 int return_status;
711 unsigned long wait_online;
e315cd28
AC		 712 struct qla_hw_data *ha = vha->hw;
713 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 714
fa2a1ce5 715 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 716 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
717 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
718 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
719 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 720
721 msleep(1000);
722 }
e315cd28 723 if (base_vha->flags.online)
fa2a1ce5 724 return_status = QLA_SUCCESS;
1da177e4
LT		 725 else
726 return_status = QLA_FUNCTION_FAILED;
727
1da177e4
LT		 728 return (return_status);
729}
730
86fbee86
LC		 731/*
732 * qla2x00_wait_for_reset_ready
733 * Wait till the HBA is online after going through
734 * <= MAX_RETRIES_OF_ISP_ABORT or
735 * finally HBA is disabled ie marked offline or flash
736 * operations are in progress.
737 *
738 * Input:
739 * ha - pointer to host adapter structure
740 *
741 * Note:
742 * Does context switching-Release SPIN_LOCK
743 * (if any) before calling this routine.
744 *
745 * Return:
746 * Success (Adapter is online/no flash ops) : 0
747 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
748 */
3dbe756a 749static int
86fbee86
LC		 750qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
751{
752 int return_status;
753 unsigned long wait_online;
754 struct qla_hw_data *ha = vha->hw;
755 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
756
757 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
758 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
759 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
760 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
761 ha->optrom_state != QLA_SWAITING ||
762 ha->dpc_active) && time_before(jiffies, wait_online))
763 msleep(1000);
764
765 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
766 return_status = QLA_SUCCESS;
767 else
768 return_status = QLA_FUNCTION_FAILED;
769
7c3df132
SK		 770 ql_dbg(ql_dbg_taskm, vha, 0x8019,
771 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 772
773 return return_status;
774}
775
2533cf67
LC		 776int
777qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
778{
779 int return_status;
780 unsigned long wait_reset;
781 struct qla_hw_data *ha = vha->hw;
782 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
783
784 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
785 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
786 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
787 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
788 ha->dpc_active) && time_before(jiffies, wait_reset)) {
789
790 msleep(1000);
791
792 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
793 ha->flags.chip_reset_done)
794 break;
795 }
796 if (ha->flags.chip_reset_done)
797 return_status = QLA_SUCCESS;
798 else
799 return_status = QLA_FUNCTION_FAILED;
800
801 return return_status;
802}
803
1da177e4
LT		 804/*
805 * qla2x00_wait_for_loop_ready
806 * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
fa2a1ce5 807 * to be in LOOP_READY state.
1da177e4
LT		 808 * Input:
809 * ha - pointer to host adapter structure
fa2a1ce5
AV		 810 *
811 * Note:
1da177e4
LT		 812 * Does context switching-Release SPIN_LOCK
813 * (if any) before calling this routine.
fa2a1ce5 814 *
1da177e4
LT		 815 *
816 * Return:
817 * Success (LOOP_READY) : 0
818 * Failed (LOOP_NOT_READY) : 1
819 */
fa2a1ce5 820static inline int
e315cd28 821qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
1da177e4
LT		 822{
823 int return_status = QLA_SUCCESS;
824 unsigned long loop_timeout ;
e315cd28
AC		 825 struct qla_hw_data *ha = vha->hw;
826 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 827
828 /* wait for 5 min at the max for loop to be ready */
fa2a1ce5 829 loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1da177e4 830
e315cd28
AC		 831 while ((!atomic_read(&base_vha->loop_down_timer) &&
832 atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
833 atomic_read(&base_vha->loop_state) != LOOP_READY) {
834 if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
57680080
RA		 835 return_status = QLA_FUNCTION_FAILED;
836 break;
837 }
1da177e4
LT		 838 msleep(1000);
839 if (time_after_eq(jiffies, loop_timeout)) {
840 return_status = QLA_FUNCTION_FAILED;
841 break;
842 }
843 }
fa2a1ce5 844 return (return_status);
1da177e4
LT		 845}
846
083a469d
GM		 847static void
848sp_get(struct srb *sp)
849{
850 atomic_inc(&sp->ref_count);
851}
852
1da177e4
LT		 853/**************************************************************************
854* qla2xxx_eh_abort
855*
856* Description:
857* The abort function will abort the specified command.
858*
859* Input:
860* cmd = Linux SCSI command packet to be aborted.
861*
862* Returns:
863* Either SUCCESS or FAILED.
864*
865* Note:
2ea00202 866* Only return FAILED if command not returned by firmware.
1da177e4 867**************************************************************************/
e5f82ab8 868static int
1da177e4
LT		 869qla2xxx_eh_abort(struct scsi_cmnd *cmd)
870{
e315cd28 871 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 872 srb_t *sp;
4e98d3b8 873 int ret;
f4f051eb 874 unsigned int id, lun;
18e144d3 875 unsigned long flags;
2ea00202 876 int wait = 0;
e315cd28 877 struct qla_hw_data *ha = vha->hw;
1da177e4 878
7c3df132
SK		 879 ql_dbg(ql_dbg_taskm, vha, 0x8000,
880 "Entered %s for cmd=%p.\n", __func__, cmd);
f4f051eb 881 if (!CMD_SP(cmd))
2ea00202 882 return SUCCESS;
1da177e4 883
4e98d3b8 884 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 885 ql_dbg(ql_dbg_taskm, vha, 0x8001,
886 "Return value of fc_block_scsi_eh=%d.\n", ret);
4e98d3b8
AV		 887 if (ret != 0)
888 return ret;
889 ret = SUCCESS;
890
f4f051eb
AV		 891 id = cmd->device->id;
892 lun = cmd->device->lun;
1da177e4 893
e315cd28 894 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 895 sp = (srb_t *) CMD_SP(cmd);
896 if (!sp) {
897 spin_unlock_irqrestore(&ha->hardware_lock, flags);
898 return SUCCESS;
899 }
1da177e4 900
7c3df132
SK		 901 ql_dbg(ql_dbg_taskm, vha, 0x8002,
902 "Aborting sp=%p cmd=%p from RISC ", sp, cmd);
17d98630 903
170babc3
MC		 904 /* Get a reference to the sp and drop the lock.*/
905 sp_get(sp);
083a469d 906
e315cd28 907 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 908 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 909 ql_dbg(ql_dbg_taskm, vha, 0x8003,
910 "Abort command mbx failed for cmd=%p.\n", cmd);
170babc3 911 } else {
7c3df132
SK		 912 ql_dbg(ql_dbg_taskm, vha, 0x8004,
913 "Abort command mbx success.\n");
170babc3
MC		 914 wait = 1;
915 }
75942064
SK		 916
917 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3 918 qla2x00_sp_compl(ha, sp);
75942064 919 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 920
bc91ade9
CD		 921 /* Did the command return during mailbox execution? */
922 if (ret == FAILED && !CMD_SP(cmd))
923 ret = SUCCESS;
924
f4f051eb 925 /* Wait for the command to be returned. */
2ea00202 926 if (wait) {
e315cd28 927 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132
SK		 928 ql_log(ql_log_warn, vha, 0x8006,
929 "Abort handler timed out for cmd=%p.\n", cmd);
2ea00202 930 ret = FAILED;
f4f051eb 931 }
1da177e4 932 }
1da177e4 933
7c3df132
SK		 934 ql_log(ql_log_info, vha, 0x801c,
935 "Abort command issued -- %d %x.\n", wait, ret);
1da177e4 936
f4f051eb
AV		 937 return ret;
938}
1da177e4 939
4d78c973 940int
e315cd28 941qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 942 unsigned int l, enum nexus_wait_type type)
f4f051eb 943{
17d98630 944 int cnt, match, status;
18e144d3 945 unsigned long flags;
e315cd28 946 struct qla_hw_data *ha = vha->hw;
73208dfd 947 struct req_que *req;
4d78c973 948 srb_t *sp;
1da177e4 949
523ec773 950 status = QLA_SUCCESS;
17d98630 951
e315cd28 952 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 953 req = vha->req;
17d98630
AC		 954 for (cnt = 1; status == QLA_SUCCESS &&
955 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
956 sp = req->outstanding_cmds[cnt];
957 if (!sp)
523ec773 958 continue;
bad75002 959 if ((sp->ctx) && !IS_PROT_IO(sp))
cf53b069 960 continue;
17d98630
AC		 961 if (vha->vp_idx != sp->fcport->vha->vp_idx)
962 continue;
963 match = 0;
964 switch (type) {
965 case WAIT_HOST:
966 match = 1;
967 break;
968 case WAIT_TARGET:
969 match = sp->cmd->device->id == t;
970 break;
971 case WAIT_LUN:
972 match = (sp->cmd->device->id == t &&
973 sp->cmd->device->lun == l);
974 break;
73208dfd 975 }
17d98630
AC		 976 if (!match)
977 continue;
978
979 spin_unlock_irqrestore(&ha->hardware_lock, flags);
980 status = qla2x00_eh_wait_on_command(sp->cmd);
981 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 982 }
e315cd28 983 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 984
985 return status;
1da177e4
LT		 986}
987
523ec773
AV		 988static char *reset_errors[] = {
989 "HBA not online",
990 "HBA not ready",
991 "Task management failed",
992 "Waiting for command completions",
993};
1da177e4 994
e5f82ab8 995static int
523ec773 996__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 997 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 998{
e315cd28 999 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1000 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1001 int err;
1da177e4 1002
7c3df132
SK		 1003 if (!fcport) {
1004 ql_log(ql_log_warn, vha, 0x8007,
1005 "fcport is NULL.\n");
523ec773 1006 return FAILED;
7c3df132 1007 }
1da177e4 1008
4e98d3b8 1009 err = fc_block_scsi_eh(cmd);
7c3df132
SK		 1010 ql_dbg(ql_dbg_taskm, vha, 0x8008,
1011 "fc_block_scsi_eh ret=%d.\n", err);
4e98d3b8
AV		 1012 if (err != 0)
1013 return err;
1014
7c3df132
SK		 1015 ql_log(ql_log_info, vha, 0x8009,
1016 "%s RESET ISSUED for id %d lun %d cmd=%p.\n", name,
1017 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1018
523ec773 1019 err = 0;
7c3df132
SK		 1020 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1021 ql_log(ql_log_warn, vha, 0x800a,
1022 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1023 goto eh_reset_failed;
7c3df132 1024 }
523ec773 1025 err = 1;
7c3df132
SK		 1026 if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS) {
1027 ql_log(ql_log_warn, vha, 0x800b,
1028 "Wait for loop ready failed for cmd=%p.\n", cmd);
523ec773 1029 goto eh_reset_failed;
7c3df132 1030 }
523ec773 1031 err = 2;
2afa19a9 1032 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1033 != QLA_SUCCESS) {
1034 ql_log(ql_log_warn, vha, 0x800c,
1035 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1036 goto eh_reset_failed;
7c3df132 1037 }
523ec773 1038 err = 3;
e315cd28 1039 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1040 cmd->device->lun, type) != QLA_SUCCESS) {
1041 ql_log(ql_log_warn, vha, 0x800d,
1042 "wait for peding cmds failed for cmd=%p.\n", cmd);
523ec773 1043 goto eh_reset_failed;
7c3df132 1044 }
523ec773 1045
7c3df132
SK		 1046 ql_log(ql_log_info, vha, 0x800e,
1047 "%s RESET SUCCEEDED for id %d lun %d cmd=%p.\n", name,
1048 cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1049
1050 return SUCCESS;
1051
4d78c973 1052eh_reset_failed:
7c3df132
SK		 1053 ql_log(ql_log_info, vha, 0x800f,
1054 "%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
1055 reset_errors[err], cmd->device->id, cmd->device->lun);
523ec773
AV		 1056 return FAILED;
1057}
1da177e4 1058
523ec773
AV		 1059static int
1060qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1061{
e315cd28
AC		 1062 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1063 struct qla_hw_data *ha = vha->hw;
1da177e4 1064
523ec773
AV		 1065 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1066 ha->isp_ops->lun_reset);
1da177e4
LT		 1067}
1068
1da177e4 1069static int
523ec773 1070qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1071{
e315cd28
AC		 1072 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1073 struct qla_hw_data *ha = vha->hw;
1da177e4 1074
523ec773
AV		 1075 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1076 ha->isp_ops->target_reset);
1da177e4
LT		 1077}
1078
1da177e4
LT		 1079/**************************************************************************
1080* qla2xxx_eh_bus_reset
1081*
1082* Description:
1083* The bus reset function will reset the bus and abort any executing
1084* commands.
1085*
1086* Input:
1087* cmd = Linux SCSI command packet of the command that cause the
1088* bus reset.
1089*
1090* Returns:
1091* SUCCESS/FAILURE (defined as macro in scsi.h).
1092*
1093**************************************************************************/
e5f82ab8 1094static int
1da177e4
LT		 1095qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1096{
e315cd28 1097 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1098 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1099 int ret = FAILED;
f4f051eb 1100 unsigned int id, lun;
f4f051eb 1101
f4f051eb
AV		 1102 id = cmd->device->id;
1103 lun = cmd->device->lun;
1da177e4 1104
7c3df132
SK		 1105 if (!fcport) {
1106 ql_log(ql_log_warn, vha, 0x8010,
1107 "fcport is NULL.\n");
f4f051eb 1108 return ret;
7c3df132 1109 }
1da177e4 1110
4e98d3b8 1111 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1112 ql_dbg(ql_dbg_taskm, vha, 0x8011,
1113 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1114 if (ret != 0)
1115 return ret;
1116 ret = FAILED;
1117
7c3df132
SK		 1118 ql_log(ql_log_info, vha, 0x8012,
1119 "BUS RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1120
e315cd28 1121 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1122 ql_log(ql_log_fatal, vha, 0x8013,
1123 "Wait for hba online failed board disabled.\n");
f4f051eb 1124 goto eh_bus_reset_done;
1da177e4
LT		 1125 }
1126
e315cd28
AC		 1127 if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
1128 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
f4f051eb 1129 ret = SUCCESS;
1da177e4 1130 }
f4f051eb
AV		 1131 if (ret == FAILED)
1132 goto eh_bus_reset_done;
1da177e4 1133
9a41a62b 1134 /* Flush outstanding commands. */
4d78c973 1135 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1136 QLA_SUCCESS) {
1137 ql_log(ql_log_warn, vha, 0x8014,
1138 "Wait for pending commands failed.\n");
9a41a62b 1139 ret = FAILED;
7c3df132 1140 }
1da177e4 1141
f4f051eb 1142eh_bus_reset_done:
7c3df132
SK		 1143 ql_log(ql_log_warn, vha, 0x802b,
1144 "BUS RESET %s.\n", (ret == FAILED) ? "FAILED" : "SUCCEDED");
1da177e4 1145
f4f051eb 1146 return ret;
1da177e4
LT		 1147}
1148
1149/**************************************************************************
1150* qla2xxx_eh_host_reset
1151*
1152* Description:
1153* The reset function will reset the Adapter.
1154*
1155* Input:
1156* cmd = Linux SCSI command packet of the command that cause the
1157* adapter reset.
1158*
1159* Returns:
1160* Either SUCCESS or FAILED.
1161*
1162* Note:
1163**************************************************************************/
e5f82ab8 1164static int
1da177e4
LT		 1165qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1166{
e315cd28 1167 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1168 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
e315cd28 1169 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1170 int ret = FAILED;
f4f051eb 1171 unsigned int id, lun;
e315cd28 1172 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1173
f4f051eb
AV		 1174 id = cmd->device->id;
1175 lun = cmd->device->lun;
f4f051eb 1176
7c3df132
SK		 1177 if (!fcport) {
1178 ql_log(ql_log_warn, vha, 0x8016,
1179 "fcport is NULL.\n");
f4f051eb 1180 return ret;
7c3df132 1181 }
1da177e4 1182
4e98d3b8 1183 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1184 ql_dbg(ql_dbg_taskm, vha, 0x8017,
1185 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1186 if (ret != 0)
1187 return ret;
1188 ret = FAILED;
1189
7c3df132
SK		 1190 ql_log(ql_log_info, vha, 0x8018,
1191 "ADAPTER RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1192
86fbee86 1193 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1194 goto eh_host_reset_lock;
1da177e4
LT		 1195
1196 /*
1197 * Fixme-may be dpc thread is active and processing
fa2a1ce5 1198 * loop_resync,so wait a while for it to
1da177e4
LT		 1199 * be completed and then issue big hammer.Otherwise
1200 * it may cause I/O failure as big hammer marks the
1201 * devices as lost kicking of the port_down_timer
1202 * while dpc is stuck for the mailbox to complete.
1203 */
e315cd28
AC		 1204 qla2x00_wait_for_loop_ready(vha);
1205 if (vha != base_vha) {
1206 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1207 goto eh_host_reset_lock;
e315cd28 1208 } else {
a9083016
GM		 1209 if (IS_QLA82XX(vha->hw)) {
1210 if (!qla82xx_fcoe_ctx_reset(vha)) {
1211 /* Ctx reset success */
1212 ret = SUCCESS;
1213 goto eh_host_reset_lock;
1214 }
1215 /* fall thru if ctx reset failed */
1216 }
68ca949c
AC		 1217 if (ha->wq)
1218 flush_workqueue(ha->wq);
1219
e315cd28 1220 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1221 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1222 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1223 /* failed. schedule dpc to try */
1224 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1225
7c3df132
SK		 1226 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1227 ql_log(ql_log_warn, vha, 0x802a,
1228 "wait for hba online failed.\n");
e315cd28 1229 goto eh_host_reset_lock;
7c3df132 1230 }
e315cd28
AC		 1231 }
1232 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1233 }
1da177e4 1234
e315cd28 1235 /* Waiting for command to be returned to OS.*/
4d78c973 1236 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1237 QLA_SUCCESS)
f4f051eb 1238 ret = SUCCESS;
1da177e4 1239
f4f051eb 1240eh_host_reset_lock:
7c3df132 1241 qla_printk(KERN_INFO, ha, "%s: reset %s.\n", __func__,
25985edc 1242 (ret == FAILED) ? "failed" : "succeeded");
1da177e4 1243
f4f051eb
AV		 1244 return ret;
1245}
1da177e4
LT		 1246
1247/*
1248* qla2x00_loop_reset
1249* Issue loop reset.
1250*
1251* Input:
1252* ha = adapter block pointer.
1253*
1254* Returns:
1255* 0 = success
1256*/
a4722cf2 1257int
e315cd28 1258qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1259{
0c8c39af 1260 int ret;
bdf79621 1261 struct fc_port *fcport;
e315cd28 1262 struct qla_hw_data *ha = vha->hw;
1da177e4 1263
f4c496c1 1264 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1265 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1266 if (fcport->port_type != FCT_TARGET)
1267 continue;
1268
1269 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1270 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1271 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1272 "Bus Reset failed: Target Reset=%d "
1273 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1274 }
1275 }
1276 }
1277
a9083016 1278 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
e315cd28 1279 ret = qla2x00_full_login_lip(vha);
0c8c39af 1280 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1281 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1282 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1283 }
1284 atomic_set(&vha->loop_state, LOOP_DOWN);
1285 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1286 qla2x00_mark_all_devices_lost(vha, 0);
1287 qla2x00_wait_for_loop_ready(vha);
0c8c39af
AV		 1288 }
1289
0d6e61bc 1290 if (ha->flags.enable_lip_reset) {
e315cd28 1291 ret = qla2x00_lip_reset(vha);
0c8c39af 1292 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1293 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1294 "lip_reset failed (%d).\n", ret);
e315cd28
AC		 1295 } else
1296 qla2x00_wait_for_loop_ready(vha);
1da177e4
LT		 1297 }
1298
1da177e4 1299 /* Issue marker command only when we are going to start the I/O */
e315cd28 1300 vha->marker_needed = 1;
1da177e4 1301
0c8c39af 1302 return QLA_SUCCESS;
1da177e4
LT		 1303}
1304
df4bf0bb 1305void
e315cd28 1306qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1307{
73208dfd 1308 int que, cnt;
df4bf0bb
AV		 1309 unsigned long flags;
1310 srb_t *sp;
ac280b67 1311 struct srb_ctx *ctx;
e315cd28 1312 struct qla_hw_data *ha = vha->hw;
73208dfd 1313 struct req_que *req;
df4bf0bb
AV		 1314
1315 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1316 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1317 req = ha->req_q_map[que];
73208dfd
AC		 1318 if (!req)
1319 continue;
1320 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1321 sp = req->outstanding_cmds[cnt];
e612d465 1322 if (sp) {
73208dfd 1323 req->outstanding_cmds[cnt] = NULL;
a9083016 1324 if (!sp->ctx ||
bad75002
AE		 1325 (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
1326 IS_PROT_IO(sp)) {
ac280b67
AV		 1327 sp->cmd->result = res;
1328 qla2x00_sp_compl(ha, sp);
1329 } else {
1330 ctx = sp->ctx;
6c452a45
AV		 1331 if (ctx->type == SRB_LOGIN_CMD ||
1332 ctx->type == SRB_LOGOUT_CMD) {
4916392b 1333 ctx->u.iocb_cmd->free(sp);
db3ad7f8 1334 } else {
6c452a45 1335 struct fc_bsg_job *bsg_job =
4916392b 1336 ctx->u.bsg_job;
6c452a45
AV		 1337 if (bsg_job->request->msgcode
1338 == FC_BSG_HST_CT)
db3ad7f8 1339 kfree(sp->fcport);
6c452a45
AV		 1340 bsg_job->req->errors = 0;
1341 bsg_job->reply->result = res;
4916392b 1342 bsg_job->job_done(bsg_job);
db3ad7f8 1343 kfree(sp->ctx);
6c452a45 1344 mempool_free(sp,
4916392b 1345 ha->srb_mempool);
db3ad7f8 1346 }
ac280b67 1347 }
73208dfd 1348 }
df4bf0bb
AV		 1349 }
1350 }
1351 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1352}
1353
f4f051eb
AV		 1354static int
1355qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1356{
bdf79621 1357 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1358
19a7b4ae 1359 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1360 return -ENXIO;
bdf79621 1361
19a7b4ae 1362 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1363
f4f051eb
AV		 1364 return 0;
1365}
1da177e4 1366
f4f051eb
AV		 1367static int
1368qla2xxx_slave_configure(struct scsi_device *sdev)
1369{
e315cd28 1370 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1371 struct req_que *req = vha->req;
8482e118 1372
f4f051eb 1373 if (sdev->tagged_supported)
73208dfd 1374 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1375 else
73208dfd 1376 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1377 return 0;
1378}
1da177e4 1379
f4f051eb
AV		 1380static void
1381qla2xxx_slave_destroy(struct scsi_device *sdev)
1382{
1383 sdev->hostdata = NULL;
1da177e4
LT		 1384}
1385
c45dd305
GM		 1386static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1387{
1388 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1389
1390 if (!scsi_track_queue_full(sdev, qdepth))
1391 return;
1392
7c3df132
SK		 1393 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1394 "Queue depth adjusted-down "
1395 "to %d for scsi(%ld:%d:%d:%d).\n",
1396 sdev->queue_depth, fcport->vha->host_no,
1397 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1398}
1399
1400static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1401{
1402 fc_port_t *fcport = sdev->hostdata;
1403 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1404 struct req_que *req = NULL;
1405
1406 req = vha->req;
1407 if (!req)
1408 return;
1409
1410 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1411 return;
1412
1413 if (sdev->ordered_tags)
1414 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1415 else
1416 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1417
7c3df132
SK		 1418 ql_dbg(ql_dbg_io, vha, 0x302a,
1419 "Queue depth adjusted-up to %d for "
1420 "scsi(%ld:%d:%d:%d).\n",
1421 sdev->queue_depth, fcport->vha->host_no,
1422 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1423}
1424
ce7e4af7 1425static int
e881a172 1426qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1427{
c45dd305
GM		 1428 switch (reason) {
1429 case SCSI_QDEPTH_DEFAULT:
1430 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1431 break;
1432 case SCSI_QDEPTH_QFULL:
1433 qla2x00_handle_queue_full(sdev, qdepth);
1434 break;
1435 case SCSI_QDEPTH_RAMP_UP:
1436 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1437 break;
1438 default:
08002af2 1439 return -EOPNOTSUPP;
c45dd305 1440 }
e881a172 1441
ce7e4af7
AV		 1442 return sdev->queue_depth;
1443}
1444
1445static int
1446qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1447{
1448 if (sdev->tagged_supported) {
1449 scsi_set_tag_type(sdev, tag_type);
1450 if (tag_type)
1451 scsi_activate_tcq(sdev, sdev->queue_depth);
1452 else
1453 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1454 } else
1455 tag_type = 0;
1456
1457 return tag_type;
1458}
1459
1da177e4
LT		 1460/**
1461 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1462 * @ha: HA context
1463 *
1464 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1465 * supported addressing method.
1466 */
1467static void
53303c42 1468qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1469{
7524f9b9 1470 /* Assume a 32bit DMA mask. */
1da177e4 1471 ha->flags.enable_64bit_addressing = 0;
1da177e4 1472
6a35528a 1473 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1474 /* Any upper-dword bits set? */
1475 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1476 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1477 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1478 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1479 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1480 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1481 return;
1da177e4 1482 }
1da177e4 1483 }
7524f9b9 1484
284901a9
YH		 1485 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1486 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1487}
1488
fd34f556 1489static void
e315cd28 1490qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1491{
1492 unsigned long flags = 0;
1493 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1494
1495 spin_lock_irqsave(&ha->hardware_lock, flags);
1496 ha->interrupts_on = 1;
1497 /* enable risc and host interrupts */
1498 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1499 RD_REG_WORD(&reg->ictrl);
1500 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1501
1502}
1503
1504static void
e315cd28 1505qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1506{
1507 unsigned long flags = 0;
1508 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1509
1510 spin_lock_irqsave(&ha->hardware_lock, flags);
1511 ha->interrupts_on = 0;
1512 /* disable risc and host interrupts */
1513 WRT_REG_WORD(&reg->ictrl, 0);
1514 RD_REG_WORD(&reg->ictrl);
1515 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1516}
1517
1518static void
e315cd28 1519qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1520{
1521 unsigned long flags = 0;
1522 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1523
1524 spin_lock_irqsave(&ha->hardware_lock, flags);
1525 ha->interrupts_on = 1;
1526 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1527 RD_REG_DWORD(&reg->ictrl);
1528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1529}
1530
1531static void
e315cd28 1532qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1533{
1534 unsigned long flags = 0;
1535 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1536
124f85e6
AV		 1537 if (IS_NOPOLLING_TYPE(ha))
1538 return;
fd34f556
AV		 1539 spin_lock_irqsave(&ha->hardware_lock, flags);
1540 ha->interrupts_on = 0;
1541 WRT_REG_DWORD(&reg->ictrl, 0);
1542 RD_REG_DWORD(&reg->ictrl);
1543 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1544}
1545
1546static struct isp_operations qla2100_isp_ops = {
1547 .pci_config = qla2100_pci_config,
1548 .reset_chip = qla2x00_reset_chip,
1549 .chip_diag = qla2x00_chip_diag,
1550 .config_rings = qla2x00_config_rings,
1551 .reset_adapter = qla2x00_reset_adapter,
1552 .nvram_config = qla2x00_nvram_config,
1553 .update_fw_options = qla2x00_update_fw_options,
1554 .load_risc = qla2x00_load_risc,
1555 .pci_info_str = qla2x00_pci_info_str,
1556 .fw_version_str = qla2x00_fw_version_str,
1557 .intr_handler = qla2100_intr_handler,
1558 .enable_intrs = qla2x00_enable_intrs,
1559 .disable_intrs = qla2x00_disable_intrs,
1560 .abort_command = qla2x00_abort_command,
523ec773
AV		 1561 .target_reset = qla2x00_abort_target,
1562 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1563 .fabric_login = qla2x00_login_fabric,
1564 .fabric_logout = qla2x00_fabric_logout,
1565 .calc_req_entries = qla2x00_calc_iocbs_32,
1566 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1567 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1568 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1569 .read_nvram = qla2x00_read_nvram_data,
1570 .write_nvram = qla2x00_write_nvram_data,
1571 .fw_dump = qla2100_fw_dump,
1572 .beacon_on = NULL,
1573 .beacon_off = NULL,
1574 .beacon_blink = NULL,
1575 .read_optrom = qla2x00_read_optrom_data,
1576 .write_optrom = qla2x00_write_optrom_data,
1577 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1578 .start_scsi = qla2x00_start_scsi,
a9083016 1579 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1580};
1581
1582static struct isp_operations qla2300_isp_ops = {
1583 .pci_config = qla2300_pci_config,
1584 .reset_chip = qla2x00_reset_chip,
1585 .chip_diag = qla2x00_chip_diag,
1586 .config_rings = qla2x00_config_rings,
1587 .reset_adapter = qla2x00_reset_adapter,
1588 .nvram_config = qla2x00_nvram_config,
1589 .update_fw_options = qla2x00_update_fw_options,
1590 .load_risc = qla2x00_load_risc,
1591 .pci_info_str = qla2x00_pci_info_str,
1592 .fw_version_str = qla2x00_fw_version_str,
1593 .intr_handler = qla2300_intr_handler,
1594 .enable_intrs = qla2x00_enable_intrs,
1595 .disable_intrs = qla2x00_disable_intrs,
1596 .abort_command = qla2x00_abort_command,
523ec773
AV		 1597 .target_reset = qla2x00_abort_target,
1598 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1599 .fabric_login = qla2x00_login_fabric,
1600 .fabric_logout = qla2x00_fabric_logout,
1601 .calc_req_entries = qla2x00_calc_iocbs_32,
1602 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1603 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1604 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1605 .read_nvram = qla2x00_read_nvram_data,
1606 .write_nvram = qla2x00_write_nvram_data,
1607 .fw_dump = qla2300_fw_dump,
1608 .beacon_on = qla2x00_beacon_on,
1609 .beacon_off = qla2x00_beacon_off,
1610 .beacon_blink = qla2x00_beacon_blink,
1611 .read_optrom = qla2x00_read_optrom_data,
1612 .write_optrom = qla2x00_write_optrom_data,
1613 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1614 .start_scsi = qla2x00_start_scsi,
a9083016 1615 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1616};
1617
1618static struct isp_operations qla24xx_isp_ops = {
1619 .pci_config = qla24xx_pci_config,
1620 .reset_chip = qla24xx_reset_chip,
1621 .chip_diag = qla24xx_chip_diag,
1622 .config_rings = qla24xx_config_rings,
1623 .reset_adapter = qla24xx_reset_adapter,
1624 .nvram_config = qla24xx_nvram_config,
1625 .update_fw_options = qla24xx_update_fw_options,
1626 .load_risc = qla24xx_load_risc,
1627 .pci_info_str = qla24xx_pci_info_str,
1628 .fw_version_str = qla24xx_fw_version_str,
1629 .intr_handler = qla24xx_intr_handler,
1630 .enable_intrs = qla24xx_enable_intrs,
1631 .disable_intrs = qla24xx_disable_intrs,
1632 .abort_command = qla24xx_abort_command,
523ec773
AV		 1633 .target_reset = qla24xx_abort_target,
1634 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1635 .fabric_login = qla24xx_login_fabric,
1636 .fabric_logout = qla24xx_fabric_logout,
1637 .calc_req_entries = NULL,
1638 .build_iocbs = NULL,
1639 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1640 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1641 .read_nvram = qla24xx_read_nvram_data,
1642 .write_nvram = qla24xx_write_nvram_data,
1643 .fw_dump = qla24xx_fw_dump,
1644 .beacon_on = qla24xx_beacon_on,
1645 .beacon_off = qla24xx_beacon_off,
1646 .beacon_blink = qla24xx_beacon_blink,
1647 .read_optrom = qla24xx_read_optrom_data,
1648 .write_optrom = qla24xx_write_optrom_data,
1649 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1650 .start_scsi = qla24xx_start_scsi,
a9083016 1651 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1652};
1653
c3a2f0df
AV		 1654static struct isp_operations qla25xx_isp_ops = {
1655 .pci_config = qla25xx_pci_config,
1656 .reset_chip = qla24xx_reset_chip,
1657 .chip_diag = qla24xx_chip_diag,
1658 .config_rings = qla24xx_config_rings,
1659 .reset_adapter = qla24xx_reset_adapter,
1660 .nvram_config = qla24xx_nvram_config,
1661 .update_fw_options = qla24xx_update_fw_options,
1662 .load_risc = qla24xx_load_risc,
1663 .pci_info_str = qla24xx_pci_info_str,
1664 .fw_version_str = qla24xx_fw_version_str,
1665 .intr_handler = qla24xx_intr_handler,
1666 .enable_intrs = qla24xx_enable_intrs,
1667 .disable_intrs = qla24xx_disable_intrs,
1668 .abort_command = qla24xx_abort_command,
523ec773
AV		 1669 .target_reset = qla24xx_abort_target,
1670 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1671 .fabric_login = qla24xx_login_fabric,
1672 .fabric_logout = qla24xx_fabric_logout,
1673 .calc_req_entries = NULL,
1674 .build_iocbs = NULL,
1675 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1676 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1677 .read_nvram = qla25xx_read_nvram_data,
1678 .write_nvram = qla25xx_write_nvram_data,
1679 .fw_dump = qla25xx_fw_dump,
1680 .beacon_on = qla24xx_beacon_on,
1681 .beacon_off = qla24xx_beacon_off,
1682 .beacon_blink = qla24xx_beacon_blink,
338c9161 1683 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1684 .write_optrom = qla24xx_write_optrom_data,
1685 .get_flash_version = qla24xx_get_flash_version,
bad75002 1686 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1687 .abort_isp = qla2x00_abort_isp,
c3a2f0df
AV		 1688};
1689
3a03eb79
AV		 1690static struct isp_operations qla81xx_isp_ops = {
1691 .pci_config = qla25xx_pci_config,
1692 .reset_chip = qla24xx_reset_chip,
1693 .chip_diag = qla24xx_chip_diag,
1694 .config_rings = qla24xx_config_rings,
1695 .reset_adapter = qla24xx_reset_adapter,
1696 .nvram_config = qla81xx_nvram_config,
1697 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1698 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1699 .pci_info_str = qla24xx_pci_info_str,
1700 .fw_version_str = qla24xx_fw_version_str,
1701 .intr_handler = qla24xx_intr_handler,
1702 .enable_intrs = qla24xx_enable_intrs,
1703 .disable_intrs = qla24xx_disable_intrs,
1704 .abort_command = qla24xx_abort_command,
1705 .target_reset = qla24xx_abort_target,
1706 .lun_reset = qla24xx_lun_reset,
1707 .fabric_login = qla24xx_login_fabric,
1708 .fabric_logout = qla24xx_fabric_logout,
1709 .calc_req_entries = NULL,
1710 .build_iocbs = NULL,
1711 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1712 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1713 .read_nvram = NULL,
1714 .write_nvram = NULL,
3a03eb79
AV		 1715 .fw_dump = qla81xx_fw_dump,
1716 .beacon_on = qla24xx_beacon_on,
1717 .beacon_off = qla24xx_beacon_off,
1718 .beacon_blink = qla24xx_beacon_blink,
1719 .read_optrom = qla25xx_read_optrom_data,
1720 .write_optrom = qla24xx_write_optrom_data,
1721 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1722 .start_scsi = qla24xx_dif_start_scsi,
a9083016
GM		 1723 .abort_isp = qla2x00_abort_isp,
1724};
1725
1726static struct isp_operations qla82xx_isp_ops = {
1727 .pci_config = qla82xx_pci_config,
1728 .reset_chip = qla82xx_reset_chip,
1729 .chip_diag = qla24xx_chip_diag,
1730 .config_rings = qla82xx_config_rings,
1731 .reset_adapter = qla24xx_reset_adapter,
1732 .nvram_config = qla81xx_nvram_config,
1733 .update_fw_options = qla24xx_update_fw_options,
1734 .load_risc = qla82xx_load_risc,
1735 .pci_info_str = qla82xx_pci_info_str,
1736 .fw_version_str = qla24xx_fw_version_str,
1737 .intr_handler = qla82xx_intr_handler,
1738 .enable_intrs = qla82xx_enable_intrs,
1739 .disable_intrs = qla82xx_disable_intrs,
1740 .abort_command = qla24xx_abort_command,
1741 .target_reset = qla24xx_abort_target,
1742 .lun_reset = qla24xx_lun_reset,
1743 .fabric_login = qla24xx_login_fabric,
1744 .fabric_logout = qla24xx_fabric_logout,
1745 .calc_req_entries = NULL,
1746 .build_iocbs = NULL,
1747 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1748 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1749 .read_nvram = qla24xx_read_nvram_data,
1750 .write_nvram = qla24xx_write_nvram_data,
1751 .fw_dump = qla24xx_fw_dump,
1752 .beacon_on = qla24xx_beacon_on,
1753 .beacon_off = qla24xx_beacon_off,
1754 .beacon_blink = qla24xx_beacon_blink,
1755 .read_optrom = qla82xx_read_optrom_data,
1756 .write_optrom = qla82xx_write_optrom_data,
1757 .get_flash_version = qla24xx_get_flash_version,
1758 .start_scsi = qla82xx_start_scsi,
1759 .abort_isp = qla82xx_abort_isp,
3a03eb79
AV		 1760};
1761
ea5b6382 1762static inline void
e315cd28 1763qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 1764{
1765 ha->device_type = DT_EXTENDED_IDS;
1766 switch (ha->pdev->device) {
1767 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1768 ha->device_type |= DT_ISP2100;
1769 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1770 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 1771 break;
1772 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1773 ha->device_type |= DT_ISP2200;
1774 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1775 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 1776 break;
1777 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1778 ha->device_type |= DT_ISP2300;
4a59f71d 1779 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1780 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1781 break;
1782 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1783 ha->device_type |= DT_ISP2312;
4a59f71d 1784 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1785 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1786 break;
1787 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1788 ha->device_type |= DT_ISP2322;
4a59f71d 1789 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 1790 if (ha->pdev->subsystem_vendor == 0x1028 &&
1791 ha->pdev->subsystem_device == 0x0170)
1792 ha->device_type |= DT_OEM_001;
441d1072 1793 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1794 break;
1795 case PCI_DEVICE_ID_QLOGIC_ISP6312:
1796 ha->device_type |= DT_ISP6312;
441d1072 1797 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1798 break;
1799 case PCI_DEVICE_ID_QLOGIC_ISP6322:
1800 ha->device_type |= DT_ISP6322;
441d1072 1801 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1802 break;
1803 case PCI_DEVICE_ID_QLOGIC_ISP2422:
1804 ha->device_type |= DT_ISP2422;
4a59f71d 1805 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1806 ha->device_type |= DT_FWI2;
c76f2c01 1807 ha->device_type |= DT_IIDMA;
441d1072 1808 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 1809 break;
1810 case PCI_DEVICE_ID_QLOGIC_ISP2432:
1811 ha->device_type |= DT_ISP2432;
4a59f71d 1812 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1813 ha->device_type |= DT_FWI2;
c76f2c01 1814 ha->device_type |= DT_IIDMA;
441d1072 1815 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1816 break;
4d4df193
HK		 1817 case PCI_DEVICE_ID_QLOGIC_ISP8432:
1818 ha->device_type |= DT_ISP8432;
1819 ha->device_type |= DT_ZIO_SUPPORTED;
1820 ha->device_type |= DT_FWI2;
1821 ha->device_type |= DT_IIDMA;
1822 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1823 break;
044cc6c8
AV		 1824 case PCI_DEVICE_ID_QLOGIC_ISP5422:
1825 ha->device_type |= DT_ISP5422;
e428924c 1826 ha->device_type |= DT_FWI2;
441d1072 1827 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1828 break;
044cc6c8
AV		 1829 case PCI_DEVICE_ID_QLOGIC_ISP5432:
1830 ha->device_type |= DT_ISP5432;
e428924c 1831 ha->device_type |= DT_FWI2;
441d1072 1832 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1833 break;
c3a2f0df
AV		 1834 case PCI_DEVICE_ID_QLOGIC_ISP2532:
1835 ha->device_type |= DT_ISP2532;
1836 ha->device_type |= DT_ZIO_SUPPORTED;
1837 ha->device_type |= DT_FWI2;
1838 ha->device_type |= DT_IIDMA;
441d1072 1839 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1840 break;
3a03eb79
AV		 1841 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1842 ha->device_type |= DT_ISP8001;
1843 ha->device_type |= DT_ZIO_SUPPORTED;
1844 ha->device_type |= DT_FWI2;
1845 ha->device_type |= DT_IIDMA;
1846 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1847 break;
a9083016
GM		 1848 case PCI_DEVICE_ID_QLOGIC_ISP8021:
1849 ha->device_type |= DT_ISP8021;
1850 ha->device_type |= DT_ZIO_SUPPORTED;
1851 ha->device_type |= DT_FWI2;
1852 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1853 /* Initialize 82XX ISP flags */
1854 qla82xx_init_flags(ha);
1855 break;
ea5b6382 1856 }
e5b68a61 1857
a9083016
GM		 1858 if (IS_QLA82XX(ha))
1859 ha->port_no = !(ha->portnum & 1);
1860 else
1861 /* Get adapter physical port no from interrupt pin register. */
1862 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
1863
e5b68a61
AC		 1864 if (ha->port_no & 1)
1865 ha->flags.port0 = 1;
1866 else
1867 ha->flags.port0 = 0;
7c3df132
SK		 1868 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
1869 "device_type=0x%x port=%d fw_srisc_address=%p.\n",
1870 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 1871}
1872
1da177e4 1873static int
e315cd28 1874qla2x00_iospace_config(struct qla_hw_data *ha)
1da177e4 1875{
3776541d 1876 resource_size_t pio;
73208dfd 1877 uint16_t msix;
68ca949c 1878 int cpus;
1da177e4 1879
a9083016
GM		 1880 if (IS_QLA82XX(ha))
1881 return qla82xx_iospace_config(ha);
1882
285d0321
AV		 1883 if (pci_request_selected_regions(ha->pdev, ha->bars,
1884 QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1885 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1886 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
285d0321 1887 pci_name(ha->pdev));
285d0321
AV		 1888 goto iospace_error_exit;
1889 }
1890 if (!(ha->bars & 1))
1891 goto skip_pio;
1892
1da177e4
LT		 1893 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1894 pio = pci_resource_start(ha->pdev, 0);
3776541d
AV		 1895 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1896 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
7c3df132
SK		 1897 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1898 "Invalid pci I/O region size (%s).\n",
1899 pci_name(ha->pdev));
1da177e4
LT		 1900 pio = 0;
1901 }
1902 } else {
7c3df132
SK		 1903 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1904 "Region #0 no a PIO resource (%s).\n",
1da177e4
LT		 1905 pci_name(ha->pdev));
1906 pio = 0;
1907 }
285d0321 1908 ha->pio_address = pio;
7c3df132
SK		 1909 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1910 "PIO address=%p.\n",
1911 ha->pio_address);
1da177e4 1912
285d0321 1913skip_pio:
1da177e4 1914 /* Use MMIO operations for all accesses. */
3776541d 1915 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
7c3df132
SK		 1916 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1917 "Region #1 not an MMIO resource (%s), aborting.\n",
1da177e4
LT		 1918 pci_name(ha->pdev));
1919 goto iospace_error_exit;
1920 }
3776541d 1921 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
7c3df132
SK		 1922 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1923 "Invalid PCI mem region size (%s), aborting.\n",
1924 pci_name(ha->pdev));
1da177e4
LT		 1925 goto iospace_error_exit;
1926 }
1927
3776541d 1928 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1da177e4 1929 if (!ha->iobase) {
7c3df132
SK		 1930 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1931 "Cannot remap MMIO (%s), aborting.\n",
1932 pci_name(ha->pdev));
1da177e4
LT		 1933 goto iospace_error_exit;
1934 }
1935
73208dfd 1936 /* Determine queue resources */
2afa19a9 1937 ha->max_req_queues = ha->max_rsp_queues = 1;
d84a47c2
MH		 1938 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1939 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
2afa19a9 1940 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
17d98630 1941 goto mqiobase_exit;
d84a47c2 1942
17d98630
AC		 1943 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1944 pci_resource_len(ha->pdev, 3));
1945 if (ha->mqiobase) {
7c3df132
SK		 1946 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1947 "MQIO Base=%p.\n", ha->mqiobase);
17d98630
AC		 1948 /* Read MSIX vector size of the board */
1949 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1950 ha->msix_count = msix;
68ca949c
AC		 1951 /* Max queues are bounded by available msix vectors */
1952 /* queue 0 uses two msix vectors */
1953 if (ql2xmultique_tag) {
1954 cpus = num_online_cpus();
27dc9c5a 1955 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
68ca949c
AC		 1956 (cpus + 1) : (ha->msix_count - 1);
1957 ha->max_req_queues = 2;
1958 } else if (ql2xmaxqueues > 1) {
2afa19a9 1959 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
7c3df132
SK		 1960 QLA_MQ_SIZE : ql2xmaxqueues;
1961 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1962 "QoS mode set, max no of request queues:%d.\n",
1963 ha->max_req_queues);
1964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1965 "QoS mode set, max no of request queues:%d.\n",
1966 ha->max_req_queues);
2afa19a9 1967 }
7c3df132
SK		 1968 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1969 "MSI-X vector count: %d.\n", msix);
2afa19a9 1970 } else
7c3df132
SK		 1971 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1972 "BAR 3 not enabled.\n");
17d98630
AC		 1973
1974mqiobase_exit:
2afa19a9 1975 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1976 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1977 "MSIX Count:%d.\n", ha->msix_count);
1da177e4
LT		 1978 return (0);
1979
1980iospace_error_exit:
1981 return (-ENOMEM);
1982}
1983
1e99e33a
AV		 1984static void
1985qla2xxx_scan_start(struct Scsi_Host *shost)
1986{
e315cd28 1987 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 1988
cbc8eb67
AV		 1989 if (vha->hw->flags.running_gold_fw)
1990 return;
1991
e315cd28
AC		 1992 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1993 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1994 set_bit(RSCN_UPDATE, &vha->dpc_flags);
1995 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 1996}
1997
1998static int
1999qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2000{
e315cd28 2001 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2002
e315cd28 2003 if (!vha->host)
1e99e33a 2004 return 1;
e315cd28 2005 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2006 return 1;
2007
e315cd28 2008 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2009}
2010
1da177e4
LT		 2011/*
2012 * PCI driver interface
2013 */
7ee61397
AV		 2014static int __devinit
2015qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2016{
a1541d5a 2017 int ret = -ENODEV;
1da177e4 2018 struct Scsi_Host *host;
e315cd28
AC		 2019 scsi_qla_host_t *base_vha = NULL;
2020 struct qla_hw_data *ha;
29856e28 2021 char pci_info[30];
1da177e4 2022 char fw_str[30];
5433383e 2023 struct scsi_host_template *sht;
c51da4ec 2024 int bars, max_id, mem_only = 0;
e315cd28 2025 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2026 struct req_que *req = NULL;
2027 struct rsp_que *rsp = NULL;
1da177e4 2028
285d0321 2029 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2030 sht = &qla2xxx_driver_template;
5433383e 2031 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2032 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2033 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2034 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2035 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2036 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016
GM		 2037 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2038 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
285d0321 2039 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2040 mem_only = 1;
7c3df132
SK		 2041 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2042 "Mem only adapter.\n");
285d0321 2043 }
7c3df132
SK		 2044 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2045 "Bars=%d.\n", bars);
285d0321 2046
09483916
BH		 2047 if (mem_only) {
2048 if (pci_enable_device_mem(pdev))
2049 goto probe_out;
2050 } else {
2051 if (pci_enable_device(pdev))
2052 goto probe_out;
2053 }
285d0321 2054
0927678f
JB		 2055 /* This may fail but that's ok */
2056 pci_enable_pcie_error_reporting(pdev);
285d0321 2057
e315cd28
AC		 2058 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2059 if (!ha) {
7c3df132
SK		 2060 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2061 "Unable to allocate memory for ha.\n");
e315cd28 2062 goto probe_out;
1da177e4 2063 }
7c3df132
SK		 2064 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2065 "Memory allocated for ha=%p.\n", ha);
e315cd28 2066 ha->pdev = pdev;
1da177e4
LT		 2067
2068 /* Clear our data area */
285d0321 2069 ha->bars = bars;
09483916 2070 ha->mem_only = mem_only;
df4bf0bb 2071 spin_lock_init(&ha->hardware_lock);
339aa70e 2072 spin_lock_init(&ha->vport_slock);
1da177e4 2073
ea5b6382
AV		 2074 /* Set ISP-type information. */
2075 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2076
2077 /* Set EEH reset type to fundamental if required by hba */
2078 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
2079 pdev->needs_freset = 1;
ca79cf66
DG		 2080 }
2081
1da177e4
LT		 2082 /* Configure PCI I/O space */
2083 ret = qla2x00_iospace_config(ha);
a1541d5a 2084 if (ret)
e315cd28 2085 goto probe_hw_failed;
1da177e4 2086
7c3df132
SK		 2087 ql_log_pci(ql_log_info, pdev, 0x001d,
2088 "Found an ISP%04X irq %d iobase 0x%p.\n",
2089 pdev->device, pdev->irq, ha->iobase);
1da177e4 2090 ha->prev_topology = 0;
fca29703 2091 ha->init_cb_size = sizeof(init_cb_t);
d8b45213 2092 ha->link_data_rate = PORT_SPEED_UNKNOWN;
854165f4 2093 ha->optrom_size = OPTROM_SIZE_2300;
1da177e4 2094
abbd8870 2095 /* Assign ISP specific operations. */
e315cd28 2096 max_id = MAX_TARGETS_2200;
1da177e4 2097 if (IS_QLA2100(ha)) {
e315cd28 2098 max_id = MAX_TARGETS_2100;
1da177e4 2099 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2100 req_length = REQUEST_ENTRY_CNT_2100;
2101 rsp_length = RESPONSE_ENTRY_CNT_2100;
2102 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2103 ha->gid_list_info_size = 4;
3a03eb79
AV		 2104 ha->flash_conf_off = ~0;
2105 ha->flash_data_off = ~0;
2106 ha->nvram_conf_off = ~0;
2107 ha->nvram_data_off = ~0;
fd34f556 2108 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2109 } else if (IS_QLA2200(ha)) {
1da177e4 2110 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2111 req_length = REQUEST_ENTRY_CNT_2200;
2112 rsp_length = RESPONSE_ENTRY_CNT_2100;
2113 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2114 ha->gid_list_info_size = 4;
3a03eb79
AV		 2115 ha->flash_conf_off = ~0;
2116 ha->flash_data_off = ~0;
2117 ha->nvram_conf_off = ~0;
2118 ha->nvram_data_off = ~0;
fd34f556 2119 ha->isp_ops = &qla2100_isp_ops;
fca29703 2120 } else if (IS_QLA23XX(ha)) {
1da177e4 2121 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2122 req_length = REQUEST_ENTRY_CNT_2200;
2123 rsp_length = RESPONSE_ENTRY_CNT_2300;
2124 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2125 ha->gid_list_info_size = 6;
854165f4
AV		 2126 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2127 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2128 ha->flash_conf_off = ~0;
2129 ha->flash_data_off = ~0;
2130 ha->nvram_conf_off = ~0;
2131 ha->nvram_data_off = ~0;
fd34f556 2132 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2133 } else if (IS_QLA24XX_TYPE(ha)) {
fca29703 2134 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2135 req_length = REQUEST_ENTRY_CNT_24XX;
2136 rsp_length = RESPONSE_ENTRY_CNT_2300;
2137 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2138 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2139 ha->gid_list_info_size = 8;
854165f4 2140 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2141 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2142 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2143 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2144 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2145 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2146 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2147 } else if (IS_QLA25XX(ha)) {
c3a2f0df 2148 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2149 req_length = REQUEST_ENTRY_CNT_24XX;
2150 rsp_length = RESPONSE_ENTRY_CNT_2300;
2151 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2152 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2153 ha->gid_list_info_size = 8;
2154 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2155 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2156 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2157 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2158 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2159 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2160 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2161 } else if (IS_QLA81XX(ha)) {
2162 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2163 req_length = REQUEST_ENTRY_CNT_24XX;
2164 rsp_length = RESPONSE_ENTRY_CNT_2300;
2165 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2166 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2167 ha->gid_list_info_size = 8;
2168 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2169 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2170 ha->isp_ops = &qla81xx_isp_ops;
2171 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2172 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2173 ha->nvram_conf_off = ~0;
2174 ha->nvram_data_off = ~0;
a9083016
GM		 2175 } else if (IS_QLA82XX(ha)) {
2176 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2177 req_length = REQUEST_ENTRY_CNT_82XX;
2178 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2179 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2180 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2181 ha->gid_list_info_size = 8;
2182 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2183 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2184 ha->isp_ops = &qla82xx_isp_ops;
2185 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2186 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2187 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2188 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
1da177e4 2189 }
7c3df132
SK		 2190 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2191 "mbx_count=%d, req_length=%d, "
2192 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2193 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n",
2194 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2195 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2196 ha->nvram_npiv_size);
2197 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2198 "isp_ops=%p, flash_conf_off=%d, "
2199 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2200 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2201 ha->nvram_conf_off, ha->nvram_data_off);
6c2f527c 2202 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2203 init_completion(&ha->mbx_cmd_comp);
2204 complete(&ha->mbx_cmd_comp);
2205 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2206 init_completion(&ha->dcbx_comp);
1da177e4 2207
2c3dfe3f 2208 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2209
53303c42 2210 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2211 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2212 "64 Bit addressing is %s.\n",
2213 ha->flags.enable_64bit_addressing ? "enable" :
2214 "disable");
73208dfd 2215 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2216 if (!ret) {
7c3df132
SK		 2217 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2218 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2219
e315cd28
AC		 2220 goto probe_hw_failed;
2221 }
2222
73208dfd 2223 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2224 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2225 req->max_q_depth = ql2xmaxqdepth;
2226
e315cd28
AC		 2227
2228 base_vha = qla2x00_create_host(sht, ha);
2229 if (!base_vha) {
a1541d5a 2230 ret = -ENOMEM;
6e9f21f3 2231 qla2x00_mem_free(ha);
2afa19a9
AC		 2232 qla2x00_free_req_que(ha, req);
2233 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2234 goto probe_hw_failed;
1da177e4
LT		 2235 }
2236
e315cd28
AC		 2237 pci_set_drvdata(pdev, base_vha);
2238
e315cd28 2239 host = base_vha->host;
2afa19a9 2240 base_vha->req = req;
73208dfd
AC		 2241 host->can_queue = req->length + 128;
2242 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2243 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2244 else
e315cd28
AC		 2245 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2246 base_vha->vp_idx;
58548cb5
GM		 2247
2248 /* Set the SG table size based on ISP type */
2249 if (!IS_FWI2_CAPABLE(ha)) {
2250 if (IS_QLA2100(ha))
2251 host->sg_tablesize = 32;
2252 } else {
2253 if (!IS_QLA82XX(ha))
2254 host->sg_tablesize = QLA_SG_ALL;
2255 }
7c3df132
SK		 2256 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2257 "can_queue=%d, req=%p, "
2258 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2259 host->can_queue, base_vha->req,
2260 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
e315cd28
AC		 2261 host->max_id = max_id;
2262 host->this_id = 255;
2263 host->cmd_per_lun = 3;
2264 host->unique_id = host->host_no;
e02587d7 2265 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2266 host->max_cmd_len = 32;
2267 else
2268 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2269 host->max_channel = MAX_BUSES - 1;
82515920 2270 host->max_lun = ql2xmaxlun;
e315cd28 2271 host->transportt = qla2xxx_transport_template;
9a069e19 2272 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2273
7c3df132
SK		 2274 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2275 "max_id=%d this_id=%d "
2276 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2277 "max_lun=%d transportt=%p, vendor_id=%d.\n", host->max_id,
2278 host->this_id, host->cmd_per_lun, host->unique_id,
2279 host->max_cmd_len, host->max_channel, host->max_lun,
2280 host->transportt, sht->vendor_id);
2281
73208dfd
AC		 2282 /* Set up the irqs */
2283 ret = qla2x00_request_irqs(ha, rsp);
2284 if (ret)
6e9f21f3 2285 goto probe_init_failed;
90a86fc0
JC		 2286
2287 pci_save_state(pdev);
2288
73208dfd 2289 /* Alloc arrays of request and response ring ptrs */
7163ea81 2290que_init:
73208dfd 2291 if (!qla2x00_alloc_queues(ha)) {
7c3df132
SK		 2292 ql_log(ql_log_fatal, base_vha, 0x003d,
2293 "Failed to allocate memory for queue pointers.. aborting.\n");
6e9f21f3 2294 goto probe_init_failed;
73208dfd 2295 }
a9083016 2296
73208dfd
AC		 2297 ha->rsp_q_map[0] = rsp;
2298 ha->req_q_map[0] = req;
2afa19a9
AC		 2299 rsp->req = req;
2300 req->rsp = rsp;
2301 set_bit(0, ha->req_qid_map);
2302 set_bit(0, ha->rsp_qid_map);
08029990
AV		 2303 /* FWI2-capable only. */
2304 req->req_q_in = &ha->iobase->isp24.req_q_in;
2305 req->req_q_out = &ha->iobase->isp24.req_q_out;
2306 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2307 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
17d98630 2308 if (ha->mqenable) {
08029990
AV		 2309 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2310 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2311 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2312 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2313 }
2314
a9083016
GM		 2315 if (IS_QLA82XX(ha)) {
2316 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2317 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2318 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2319 }
2320
7c3df132
SK		 2321 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2322 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2323 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2324 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2325 "req->req_q_in=%p req->req_q_out=%p "
2326 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2327 req->req_q_in, req->req_q_out,
2328 rsp->rsp_q_in, rsp->rsp_q_out);
2329 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2330 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2331 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2332 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2333 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2334 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2335
7c3df132
SK		 2336 if (qla2x00_initialize_adapter(base_vha)) {
2337 ql_log(ql_log_fatal, base_vha, 0x00d6,
2338 "Failed to initialize adapter - Adapter flags %x.\n",
2339 base_vha->device_flags);
1da177e4 2340
a9083016
GM		 2341 if (IS_QLA82XX(ha)) {
2342 qla82xx_idc_lock(ha);
2343 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2344 QLA82XX_DEV_FAILED);
2345 qla82xx_idc_unlock(ha);
7c3df132
SK		 2346 ql_log(ql_log_fatal, base_vha, 0x00d7,
2347 "HW State: FAILED.\n");
a9083016
GM		 2348 }
2349
a1541d5a 2350 ret = -ENODEV;
1da177e4
LT		 2351 goto probe_failed;
2352 }
2353
7163ea81
AC		 2354 if (ha->mqenable) {
2355 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2356 ql_log(ql_log_warn, base_vha, 0x00ec,
2357 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2358 goto que_init;
2359 }
2360 }
68ca949c 2361
cbc8eb67
AV		 2362 if (ha->flags.running_gold_fw)
2363 goto skip_dpc;
2364
1da177e4
LT		 2365 /*
2366 * Startup the kernel thread for this host adapter
2367 */
39a11240 2368 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2369 "%s_dpc", base_vha->host_str);
39a11240 2370 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2371 ql_log(ql_log_fatal, base_vha, 0x00ed,
2372 "Failed to start DPC thread.\n");
39a11240 2373 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2374 goto probe_failed;
2375 }
7c3df132
SK		 2376 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2377 "DPC thread started successfully.\n");
1da177e4 2378
cbc8eb67 2379skip_dpc:
e315cd28
AC		 2380 list_add_tail(&base_vha->list, &ha->vp_list);
2381 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2382
2383 /* Initialized the timer */
e315cd28 2384 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2385 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2386 "Started qla2x00_timer with "
2387 "interval=%d.\n", WATCH_INTERVAL);
2388 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2389 "Detected hba at address=%p.\n",
2390 ha);
d19044c3 2391
e02587d7 2392 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2393 if (ha->fw_attributes & BIT_4) {
8cb2049c 2394 int prot = 0;
bad75002 2395 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2396 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2397 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2398 if (ql2xenabledif == 1)
2399 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2400 scsi_host_set_prot(host,
8cb2049c 2401 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2402 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2403 | SHOST_DIF_TYPE3_PROTECTION
2404 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2405 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2406 | SHOST_DIX_TYPE3_PROTECTION);
2407 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2408 } else
2409 base_vha->flags.difdix_supported = 0;
2410 }
2411
a9083016
GM		 2412 ha->isp_ops->enable_intrs(ha);
2413
a1541d5a
AV		 2414 ret = scsi_add_host(host, &pdev->dev);
2415 if (ret)
2416 goto probe_failed;
2417
1486400f
MR		 2418 base_vha->flags.init_done = 1;
2419 base_vha->flags.online = 1;
2420
7c3df132
SK		 2421 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2422 "Init done and hba is online.\n");
2423
1e99e33a
AV		 2424 scsi_scan_host(host);
2425
e315cd28 2426 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2427
e315cd28 2428 qla2x00_init_host_attr(base_vha);
a1541d5a 2429
e315cd28 2430 qla2x00_dfs_setup(base_vha);
df613b96 2431
7c3df132
SK		 2432 ql_log(ql_log_info, base_vha, 0x00fa,
2433 "QLogic Fibre Channed HBA Driver: %s.\n",
2434 qla2x00_version_str);
2435 ql_log(ql_log_info, base_vha, 0x00fb,
2436 "QLogic %s - %s.\n",
2437 ha->model_number, ha->model_desc ? ha->model_desc : "");
2438 ql_log(ql_log_info, base_vha, 0x00fc,
2439 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2440 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2441 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2442 base_vha->host_no,
e315cd28 2443 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2444
1da177e4
LT		 2445 return 0;
2446
6e9f21f3 2447probe_init_failed:
2afa19a9
AC		 2448 qla2x00_free_req_que(ha, req);
2449 qla2x00_free_rsp_que(ha, rsp);
2450 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2451
1da177e4 2452probe_failed:
b9978769
AV		 2453 if (base_vha->timer_active)
2454 qla2x00_stop_timer(base_vha);
2455 base_vha->flags.online = 0;
2456 if (ha->dpc_thread) {
2457 struct task_struct *t = ha->dpc_thread;
2458
2459 ha->dpc_thread = NULL;
2460 kthread_stop(t);
2461 }
2462
e315cd28 2463 qla2x00_free_device(base_vha);
1da177e4 2464
e315cd28 2465 scsi_host_put(base_vha->host);
1da177e4 2466
e315cd28 2467probe_hw_failed:
a9083016
GM		 2468 if (IS_QLA82XX(ha)) {
2469 qla82xx_idc_lock(ha);
2470 qla82xx_clear_drv_active(ha);
2471 qla82xx_idc_unlock(ha);
2472 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2473 if (!ql2xdbwr)
2474 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2475 } else {
2476 if (ha->iobase)
2477 iounmap(ha->iobase);
2478 }
e315cd28
AC		 2479 pci_release_selected_regions(ha->pdev, ha->bars);
2480 kfree(ha);
2481 ha = NULL;
1da177e4 2482
a1541d5a 2483probe_out:
e315cd28 2484 pci_disable_device(pdev);
a1541d5a 2485 return ret;
1da177e4 2486}
1da177e4 2487
e30d1756
MI		 2488static void
2489qla2x00_shutdown(struct pci_dev *pdev)
2490{
2491 scsi_qla_host_t *vha;
2492 struct qla_hw_data *ha;
2493
2494 vha = pci_get_drvdata(pdev);
2495 ha = vha->hw;
2496
2497 /* Turn-off FCE trace */
2498 if (ha->flags.fce_enabled) {
2499 qla2x00_disable_fce_trace(vha, NULL, NULL);
2500 ha->flags.fce_enabled = 0;
2501 }
2502
2503 /* Turn-off EFT trace */
2504 if (ha->eft)
2505 qla2x00_disable_eft_trace(vha);
2506
2507 /* Stop currently executing firmware. */
2508 qla2x00_try_to_stop_firmware(vha);
2509
2510 /* Turn adapter off line */
2511 vha->flags.online = 0;
2512
2513 /* turn-off interrupts on the card */
2514 if (ha->interrupts_on) {
2515 vha->flags.init_done = 0;
2516 ha->isp_ops->disable_intrs(ha);
2517 }
2518
2519 qla2x00_free_irqs(vha);
2520
2521 qla2x00_free_fw_dump(ha);
2522}
2523
4c993f76 2524static void
7ee61397 2525qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2526{
feafb7b1 2527 scsi_qla_host_t *base_vha, *vha;
e315cd28 2528 struct qla_hw_data *ha;
feafb7b1 2529 unsigned long flags;
e315cd28
AC		 2530
2531 base_vha = pci_get_drvdata(pdev);
2532 ha = base_vha->hw;
2533
43ebf16d
AE		 2534 mutex_lock(&ha->vport_lock);
2535 while (ha->cur_vport_count) {
2536 struct Scsi_Host *scsi_host;
feafb7b1 2537
43ebf16d 2538 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2539
43ebf16d
AE		 2540 BUG_ON(base_vha->list.next == &ha->vp_list);
2541 /* This assumes first entry in ha->vp_list is always base vha */
2542 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2543 scsi_host = scsi_host_get(vha->host);
feafb7b1 2544
43ebf16d
AE		 2545 spin_unlock_irqrestore(&ha->vport_slock, flags);
2546 mutex_unlock(&ha->vport_lock);
2547
2548 fc_vport_terminate(vha->fc_vport);
2549 scsi_host_put(vha->host);
feafb7b1 2550
43ebf16d 2551 mutex_lock(&ha->vport_lock);
e315cd28 2552 }
43ebf16d 2553 mutex_unlock(&ha->vport_lock);
1da177e4 2554
e315cd28 2555 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2556
b9978769
AV		 2557 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2558
e315cd28 2559 qla2x00_dfs_remove(base_vha);
c795c1e4 2560
e315cd28 2561 qla84xx_put_chip(base_vha);
c795c1e4 2562
b9978769
AV		 2563 /* Disable timer */
2564 if (base_vha->timer_active)
2565 qla2x00_stop_timer(base_vha);
2566
2567 base_vha->flags.online = 0;
2568
68ca949c
AC		 2569 /* Flush the work queue and remove it */
2570 if (ha->wq) {
2571 flush_workqueue(ha->wq);
2572 destroy_workqueue(ha->wq);
2573 ha->wq = NULL;
2574 }
2575
b9978769
AV		 2576 /* Kill the kernel thread for this host */
2577 if (ha->dpc_thread) {
2578 struct task_struct *t = ha->dpc_thread;
2579
2580 /*
2581 * qla2xxx_wake_dpc checks for ->dpc_thread
2582 * so we need to zero it out.
2583 */
2584 ha->dpc_thread = NULL;
2585 kthread_stop(t);
2586 }
2587
e315cd28 2588 qla2x00_free_sysfs_attr(base_vha);
df613b96 2589
e315cd28 2590 fc_remove_host(base_vha->host);
4d4df193 2591
e315cd28 2592 scsi_remove_host(base_vha->host);
1da177e4 2593
e315cd28 2594 qla2x00_free_device(base_vha);
bdf79621 2595
e315cd28 2596 scsi_host_put(base_vha->host);
1da177e4 2597
a9083016 2598 if (IS_QLA82XX(ha)) {
b963752f
GM		 2599 qla82xx_idc_lock(ha);
2600 qla82xx_clear_drv_active(ha);
2601 qla82xx_idc_unlock(ha);
2602
a9083016
GM		 2603 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2604 if (!ql2xdbwr)
2605 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2606 } else {
2607 if (ha->iobase)
2608 iounmap(ha->iobase);
1da177e4 2609
a9083016
GM		 2610 if (ha->mqiobase)
2611 iounmap(ha->mqiobase);
2612 }
73208dfd 2613
e315cd28
AC		 2614 pci_release_selected_regions(ha->pdev, ha->bars);
2615 kfree(ha);
2616 ha = NULL;
1da177e4 2617
90a86fc0
JC		 2618 pci_disable_pcie_error_reporting(pdev);
2619
665db93b 2620 pci_disable_device(pdev);
1da177e4
LT		 2621 pci_set_drvdata(pdev, NULL);
2622}
1da177e4
LT		 2623
2624static void
e315cd28 2625qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2626{
e315cd28 2627 struct qla_hw_data *ha = vha->hw;
1da177e4 2628
85880801
AV		 2629 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2630
2631 /* Disable timer */
2632 if (vha->timer_active)
2633 qla2x00_stop_timer(vha);
2634
2635 /* Kill the kernel thread for this host */
2636 if (ha->dpc_thread) {
2637 struct task_struct *t = ha->dpc_thread;
2638
2639 /*
2640 * qla2xxx_wake_dpc checks for ->dpc_thread
2641 * so we need to zero it out.
2642 */
2643 ha->dpc_thread = NULL;
2644 kthread_stop(t);
2645 }
2646
2afa19a9
AC		 2647 qla25xx_delete_queues(vha);
2648
df613b96 2649 if (ha->flags.fce_enabled)
e315cd28 2650 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2651
a7a167bf 2652 if (ha->eft)
e315cd28 2653 qla2x00_disable_eft_trace(vha);
a7a167bf 2654
f6ef3b18 2655 /* Stop currently executing firmware. */
e315cd28 2656 qla2x00_try_to_stop_firmware(vha);
1da177e4 2657
85880801
AV		 2658 vha->flags.online = 0;
2659
f6ef3b18 2660 /* turn-off interrupts on the card */
a9083016
GM		 2661 if (ha->interrupts_on) {
2662 vha->flags.init_done = 0;
fd34f556 2663 ha->isp_ops->disable_intrs(ha);
a9083016 2664 }
f6ef3b18 2665
e315cd28 2666 qla2x00_free_irqs(vha);
1da177e4 2667
8867048b
CD		 2668 qla2x00_free_fcports(vha);
2669
e315cd28 2670 qla2x00_mem_free(ha);
73208dfd
AC		 2671
2672 qla2x00_free_queues(ha);
1da177e4
LT		 2673}
2674
8867048b
CD		 2675void qla2x00_free_fcports(struct scsi_qla_host *vha)
2676{
2677 fc_port_t *fcport, *tfcport;
2678
2679 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2680 list_del(&fcport->list);
2681 kfree(fcport);
2682 fcport = NULL;
2683 }
2684}
2685
d97994dc 2686static inline void
e315cd28 2687qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 2688 int defer)
2689{
d97994dc 2690 struct fc_rport *rport;
67becc00 2691 scsi_qla_host_t *base_vha;
044d78e1 2692 unsigned long flags;
d97994dc
AV		 2693
2694 if (!fcport->rport)
2695 return;
2696
2697 rport = fcport->rport;
2698 if (defer) {
67becc00 2699 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2700 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2701 fcport->drport = rport;
044d78e1 2702 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2703 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2704 qla2xxx_wake_dpc(base_vha);
5f3a9a20 2705 } else
d97994dc 2706 fc_remote_port_delete(rport);
d97994dc
AV		 2707}
2708
1da177e4
LT		 2709/*
2710 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2711 *
2712 * Input: ha = adapter block pointer. fcport = port structure pointer.
2713 *
2714 * Return: None.
2715 *
2716 * Context:
2717 */
e315cd28 2718void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2719 int do_login, int defer)
1da177e4 2720{
2c3dfe3f 2721 if (atomic_read(&fcport->state) == FCS_ONLINE &&
e315cd28 2722 vha->vp_idx == fcport->vp_idx) {
ec426e10 2723 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2724 qla2x00_schedule_rport_del(vha, fcport, defer);
2725 }
fa2a1ce5 2726 /*
1da177e4
LT		 2727 * We may need to retry the login, so don't change the state of the
2728 * port but do the retries.
2729 */
2730 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2731 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2732
2733 if (!do_login)
2734 return;
2735
2736 if (fcport->login_retry == 0) {
e315cd28
AC		 2737 fcport->login_retry = vha->hw->login_retry_count;
2738 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2739
7c3df132
SK		 2740 ql_dbg(ql_dbg_disc, vha, 0x2067,
2741 "Port login retry "
1da177e4 2742 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2743 "id = 0x%04x retry cnt=%d.\n",
2744 fcport->port_name[0], fcport->port_name[1],
2745 fcport->port_name[2], fcport->port_name[3],
2746 fcport->port_name[4], fcport->port_name[5],
2747 fcport->port_name[6], fcport->port_name[7],
2748 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2749 }
2750}
2751
2752/*
2753 * qla2x00_mark_all_devices_lost
2754 * Updates fcport state when device goes offline.
2755 *
2756 * Input:
2757 * ha = adapter block pointer.
2758 * fcport = port structure pointer.
2759 *
2760 * Return:
2761 * None.
2762 *
2763 * Context:
2764 */
2765void
e315cd28 2766qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 2767{
2768 fc_port_t *fcport;
2769
e315cd28 2770 list_for_each_entry(fcport, &vha->vp_fcports, list) {
0d6e61bc 2771 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
1da177e4 2772 continue;
0d6e61bc 2773
1da177e4
LT		 2774 /*
2775 * No point in marking the device as lost, if the device is
2776 * already DEAD.
2777 */
2778 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2779 continue;
e315cd28 2780 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 2781 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 2782 if (defer)
2783 qla2x00_schedule_rport_del(vha, fcport, defer);
2784 else if (vha->vp_idx == fcport->vp_idx)
2785 qla2x00_schedule_rport_del(vha, fcport, defer);
2786 }
1da177e4
LT		 2787 }
2788}
2789
2790/*
2791* qla2x00_mem_alloc
2792* Allocates adapter memory.
2793*
2794* Returns:
2795* 0 = success.
e8711085 2796* !0 = failure.
1da177e4 2797*/
e8711085 2798static int
73208dfd
AC		 2799qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2800 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 2801{
2802 char name[16];
1da177e4 2803
e8711085 2804 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 2805 &ha->init_cb_dma, GFP_KERNEL);
e8711085 2806 if (!ha->init_cb)
e315cd28 2807 goto fail;
e8711085 2808
e315cd28
AC		 2809 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
2810 &ha->gid_list_dma, GFP_KERNEL);
2811 if (!ha->gid_list)
e8711085 2812 goto fail_free_init_cb;
1da177e4 2813
e8711085
AV		 2814 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2815 if (!ha->srb_mempool)
e315cd28 2816 goto fail_free_gid_list;
e8711085 2817
a9083016
GM		 2818 if (IS_QLA82XX(ha)) {
2819 /* Allocate cache for CT6 Ctx. */
2820 if (!ctx_cachep) {
2821 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2822 sizeof(struct ct6_dsd), 0,
2823 SLAB_HWCACHE_ALIGN, NULL);
2824 if (!ctx_cachep)
2825 goto fail_free_gid_list;
2826 }
2827 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2828 ctx_cachep);
2829 if (!ha->ctx_mempool)
2830 goto fail_free_srb_mempool;
7c3df132
SK		 2831 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2832 "ctx_cachep=%p ctx_mempool=%p.\n",
2833 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 2834 }
2835
e8711085
AV		 2836 /* Get memory for cached NVRAM */
2837 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2838 if (!ha->nvram)
a9083016 2839 goto fail_free_ctx_mempool;
e8711085 2840
e315cd28
AC		 2841 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2842 ha->pdev->device);
2843 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2844 DMA_POOL_SIZE, 8, 0);
2845 if (!ha->s_dma_pool)
2846 goto fail_free_nvram;
2847
7c3df132
SK		 2848 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2849 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2850 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2851
bad75002 2852 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2853 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2854 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2855 if (!ha->dl_dma_pool) {
7c3df132
SK		 2856 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2857 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 2858 goto fail_s_dma_pool;
2859 }
2860
2861 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2862 FCP_CMND_DMA_POOL_SIZE, 8, 0);
2863 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 2864 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
2865 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 2866 goto fail_dl_dma_pool;
2867 }
7c3df132
SK		 2868 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
2869 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
2870 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 2871 }
2872
e8711085
AV		 2873 /* Allocate memory for SNS commands */
2874 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 2875 /* Get consistent memory allocated for SNS commands */
e8711085 2876 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2877 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 2878 if (!ha->sns_cmd)
e315cd28 2879 goto fail_dma_pool;
7c3df132
SK		 2880 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
2881 "sns_cmd.\n", ha->sns_cmd);
e8711085 2882 } else {
e315cd28 2883 /* Get consistent memory allocated for MS IOCB */
e8711085 2884 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 2885 &ha->ms_iocb_dma);
e8711085 2886 if (!ha->ms_iocb)
e315cd28
AC		 2887 goto fail_dma_pool;
2888 /* Get consistent memory allocated for CT SNS commands */
e8711085 2889 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2890 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 2891 if (!ha->ct_sns)
2892 goto fail_free_ms_iocb;
7c3df132
SK		 2893 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
2894 "ms_iocb=%p ct_sns=%p.\n",
2895 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 2896 }
2897
e315cd28 2898 /* Allocate memory for request ring */
73208dfd
AC		 2899 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
2900 if (!*req) {
7c3df132
SK		 2901 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
2902 "Failed to allocate memory for req.\n");
e315cd28
AC		 2903 goto fail_req;
2904 }
73208dfd
AC		 2905 (*req)->length = req_len;
2906 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
2907 ((*req)->length + 1) * sizeof(request_t),
2908 &(*req)->dma, GFP_KERNEL);
2909 if (!(*req)->ring) {
7c3df132
SK		 2910 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
2911 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 2912 goto fail_req_ring;
2913 }
2914 /* Allocate memory for response ring */
73208dfd
AC		 2915 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
2916 if (!*rsp) {
7c3df132
SK		 2917 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
2918 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 2919 goto fail_rsp;
2920 }
73208dfd
AC		 2921 (*rsp)->hw = ha;
2922 (*rsp)->length = rsp_len;
2923 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
2924 ((*rsp)->length + 1) * sizeof(response_t),
2925 &(*rsp)->dma, GFP_KERNEL);
2926 if (!(*rsp)->ring) {
7c3df132
SK		 2927 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
2928 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 2929 goto fail_rsp_ring;
2930 }
73208dfd
AC		 2931 (*req)->rsp = *rsp;
2932 (*rsp)->req = *req;
7c3df132
SK		 2933 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
2934 "req=%p req->length=%d req->ring=%p rsp=%p "
2935 "rsp->length=%d rsp->ring=%p.\n",
2936 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
2937 (*rsp)->ring);
73208dfd
AC		 2938 /* Allocate memory for NVRAM data for vports */
2939 if (ha->nvram_npiv_size) {
2940 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 2941 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 2942 if (!ha->npiv_info) {
7c3df132
SK		 2943 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
2944 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 2945 goto fail_npiv_info;
2946 }
2947 } else
2948 ha->npiv_info = NULL;
e8711085 2949
b64b0e8f 2950 /* Get consistent memory allocated for EX-INIT-CB. */
a9083016 2951 if (IS_QLA8XXX_TYPE(ha)) {
b64b0e8f
AV		 2952 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2953 &ha->ex_init_cb_dma);
2954 if (!ha->ex_init_cb)
2955 goto fail_ex_init_cb;
7c3df132
SK		 2956 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
2957 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 2958 }
2959
a9083016
GM		 2960 INIT_LIST_HEAD(&ha->gbl_dsd_list);
2961
5ff1d584
AV		 2962 /* Get consistent memory allocated for Async Port-Database. */
2963 if (!IS_FWI2_CAPABLE(ha)) {
2964 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2965 &ha->async_pd_dma);
2966 if (!ha->async_pd)
2967 goto fail_async_pd;
7c3df132
SK		 2968 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
2969 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 2970 }
2971
e315cd28
AC		 2972 INIT_LIST_HEAD(&ha->vp_list);
2973 return 1;
2974
5ff1d584
AV		 2975fail_async_pd:
2976 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 2977fail_ex_init_cb:
2978 kfree(ha->npiv_info);
73208dfd
AC		 2979fail_npiv_info:
2980 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
2981 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
2982 (*rsp)->ring = NULL;
2983 (*rsp)->dma = 0;
e315cd28 2984fail_rsp_ring:
73208dfd 2985 kfree(*rsp);
e315cd28 2986fail_rsp:
73208dfd
AC		 2987 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
2988 sizeof(request_t), (*req)->ring, (*req)->dma);
2989 (*req)->ring = NULL;
2990 (*req)->dma = 0;
e315cd28 2991fail_req_ring:
73208dfd 2992 kfree(*req);
e315cd28
AC		 2993fail_req:
2994 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
2995 ha->ct_sns, ha->ct_sns_dma);
2996 ha->ct_sns = NULL;
2997 ha->ct_sns_dma = 0;
e8711085
AV		 2998fail_free_ms_iocb:
2999 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3000 ha->ms_iocb = NULL;
3001 ha->ms_iocb_dma = 0;
e315cd28 3002fail_dma_pool:
bad75002 3003 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3004 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3005 ha->fcp_cmnd_dma_pool = NULL;
3006 }
3007fail_dl_dma_pool:
bad75002 3008 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3009 dma_pool_destroy(ha->dl_dma_pool);
3010 ha->dl_dma_pool = NULL;
3011 }
3012fail_s_dma_pool:
e315cd28
AC		 3013 dma_pool_destroy(ha->s_dma_pool);
3014 ha->s_dma_pool = NULL;
e8711085
AV		 3015fail_free_nvram:
3016 kfree(ha->nvram);
3017 ha->nvram = NULL;
a9083016
GM		 3018fail_free_ctx_mempool:
3019 mempool_destroy(ha->ctx_mempool);
3020 ha->ctx_mempool = NULL;
e8711085
AV		 3021fail_free_srb_mempool:
3022 mempool_destroy(ha->srb_mempool);
3023 ha->srb_mempool = NULL;
e8711085
AV		 3024fail_free_gid_list:
3025 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3026 ha->gid_list_dma);
e8711085
AV		 3027 ha->gid_list = NULL;
3028 ha->gid_list_dma = 0;
e315cd28
AC		 3029fail_free_init_cb:
3030 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3031 ha->init_cb_dma);
3032 ha->init_cb = NULL;
3033 ha->init_cb_dma = 0;
e8711085 3034fail:
7c3df132
SK		 3035 ql_log(ql_log_fatal, NULL, 0x0030,
3036 "Memory allocation failure.\n");
e8711085 3037 return -ENOMEM;
1da177e4
LT		 3038}
3039
3040/*
e30d1756
MI		 3041* qla2x00_free_fw_dump
3042* Frees fw dump stuff.
1da177e4
LT		 3043*
3044* Input:
e30d1756 3045* ha = adapter block pointer.
1da177e4 3046*/
a824ebb3 3047static void
e30d1756 3048qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3049{
df613b96
AV		 3050 if (ha->fce)
3051 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3052 ha->fce_dma);
df613b96 3053
a7a167bf
AV		 3054 if (ha->fw_dump) {
3055 if (ha->eft)
3056 dma_free_coherent(&ha->pdev->dev,
e30d1756 3057 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3058 vfree(ha->fw_dump);
3059 }
e30d1756
MI		 3060 ha->fce = NULL;
3061 ha->fce_dma = 0;
3062 ha->eft = NULL;
3063 ha->eft_dma = 0;
3064 ha->fw_dump = NULL;
3065 ha->fw_dumped = 0;
3066 ha->fw_dump_reading = 0;
3067}
3068
3069/*
3070* qla2x00_mem_free
3071* Frees all adapter allocated memory.
3072*
3073* Input:
3074* ha = adapter block pointer.
3075*/
3076static void
3077qla2x00_mem_free(struct qla_hw_data *ha)
3078{
3079 qla2x00_free_fw_dump(ha);
3080
3081 if (ha->srb_mempool)
3082 mempool_destroy(ha->srb_mempool);
a7a167bf 3083
11bbc1d8
AV		 3084 if (ha->dcbx_tlv)
3085 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3086 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3087
ce0423f4
AV		 3088 if (ha->xgmac_data)
3089 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3090 ha->xgmac_data, ha->xgmac_data_dma);
3091
1da177e4
LT		 3092 if (ha->sns_cmd)
3093 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3094 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3095
3096 if (ha->ct_sns)
3097 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3098 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3099
88729e53
AV		 3100 if (ha->sfp_data)
3101 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3102
ad0ecd61
JC		 3103 if (ha->edc_data)
3104 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
3105
1da177e4
LT		 3106 if (ha->ms_iocb)
3107 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3108
b64b0e8f 3109 if (ha->ex_init_cb)
a9083016
GM		 3110 dma_pool_free(ha->s_dma_pool,
3111 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3112
5ff1d584
AV		 3113 if (ha->async_pd)
3114 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3115
1da177e4
LT		 3116 if (ha->s_dma_pool)
3117 dma_pool_destroy(ha->s_dma_pool);
3118
1da177e4
LT		 3119 if (ha->gid_list)
3120 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3121 ha->gid_list_dma);
1da177e4 3122
a9083016
GM		 3123 if (IS_QLA82XX(ha)) {
3124 if (!list_empty(&ha->gbl_dsd_list)) {
3125 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3126
3127 /* clean up allocated prev pool */
3128 list_for_each_entry_safe(dsd_ptr,
3129 tdsd_ptr, &ha->gbl_dsd_list, list) {
3130 dma_pool_free(ha->dl_dma_pool,
3131 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3132 list_del(&dsd_ptr->list);
3133 kfree(dsd_ptr);
3134 }
3135 }
3136 }
3137
3138 if (ha->dl_dma_pool)
3139 dma_pool_destroy(ha->dl_dma_pool);
3140
3141 if (ha->fcp_cmnd_dma_pool)
3142 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3143
3144 if (ha->ctx_mempool)
3145 mempool_destroy(ha->ctx_mempool);
3146
e315cd28
AC		 3147 if (ha->init_cb)
3148 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3149 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3150 vfree(ha->optrom_buffer);
3151 kfree(ha->nvram);
73208dfd 3152 kfree(ha->npiv_info);
1da177e4 3153
e8711085 3154 ha->srb_mempool = NULL;
a9083016 3155 ha->ctx_mempool = NULL;
1da177e4
LT		 3156 ha->sns_cmd = NULL;
3157 ha->sns_cmd_dma = 0;
3158 ha->ct_sns = NULL;
3159 ha->ct_sns_dma = 0;
3160 ha->ms_iocb = NULL;
3161 ha->ms_iocb_dma = 0;
1da177e4
LT		 3162 ha->init_cb = NULL;
3163 ha->init_cb_dma = 0;
b64b0e8f
AV		 3164 ha->ex_init_cb = NULL;
3165 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3166 ha->async_pd = NULL;
3167 ha->async_pd_dma = 0;
1da177e4
LT		 3168
3169 ha->s_dma_pool = NULL;
a9083016
GM		 3170 ha->dl_dma_pool = NULL;
3171 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3172
1da177e4
LT		 3173 ha->gid_list = NULL;
3174 ha->gid_list_dma = 0;
e315cd28 3175}
1da177e4 3176
e315cd28
AC		 3177struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3178 struct qla_hw_data *ha)
3179{
3180 struct Scsi_Host *host;
3181 struct scsi_qla_host *vha = NULL;
854165f4 3182
e315cd28
AC		 3183 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3184 if (host == NULL) {
7c3df132
SK		 3185 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3186 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3187 goto fail;
3188 }
3189
3190 /* Clear our data area */
3191 vha = shost_priv(host);
3192 memset(vha, 0, sizeof(scsi_qla_host_t));
3193
3194 vha->host = host;
3195 vha->host_no = host->host_no;
3196 vha->hw = ha;
3197
3198 INIT_LIST_HEAD(&vha->vp_fcports);
3199 INIT_LIST_HEAD(&vha->work_list);
3200 INIT_LIST_HEAD(&vha->list);
3201
f999f4c1
AV		 3202 spin_lock_init(&vha->work_lock);
3203
e315cd28 3204 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3205 ql_dbg(ql_dbg_init, vha, 0x0041,
3206 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3207 vha->host, vha->hw, vha,
3208 dev_name(&(ha->pdev->dev)));
3209
e315cd28
AC		 3210 return vha;
3211
3212fail:
3213 return vha;
1da177e4
LT		 3214}
3215
01ef66bb 3216static struct qla_work_evt *
f999f4c1 3217qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3218{
3219 struct qla_work_evt *e;
feafb7b1
AE		 3220 uint8_t bail;
3221
3222 QLA_VHA_MARK_BUSY(vha, bail);
3223 if (bail)
3224 return NULL;
0971de7f 3225
f999f4c1 3226 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3227 if (!e) {
3228 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3229 return NULL;
feafb7b1 3230 }
0971de7f
AV		 3231
3232 INIT_LIST_HEAD(&e->list);
3233 e->type = type;
3234 e->flags = QLA_EVT_FLAG_FREE;
3235 return e;
3236}
3237
01ef66bb 3238static int
f999f4c1 3239qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3240{
f999f4c1 3241 unsigned long flags;
0971de7f 3242
f999f4c1 3243 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3244 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3245 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3246 qla2xxx_wake_dpc(vha);
f999f4c1 3247
0971de7f
AV		 3248 return QLA_SUCCESS;
3249}
3250
3251int
e315cd28 3252qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3253 u32 data)
3254{
3255 struct qla_work_evt *e;
3256
f999f4c1 3257 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3258 if (!e)
3259 return QLA_FUNCTION_FAILED;
3260
3261 e->u.aen.code = code;
3262 e->u.aen.data = data;
f999f4c1 3263 return qla2x00_post_work(vha, e);
0971de7f
AV		 3264}
3265
8a659571
AV		 3266int
3267qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3268{
3269 struct qla_work_evt *e;
3270
f999f4c1 3271 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3272 if (!e)
3273 return QLA_FUNCTION_FAILED;
3274
3275 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3276 return qla2x00_post_work(vha, e);
8a659571
AV		 3277}
3278
ac280b67
AV		 3279#define qla2x00_post_async_work(name, type) \
3280int qla2x00_post_async_##name##_work( \
3281 struct scsi_qla_host *vha, \
3282 fc_port_t *fcport, uint16_t *data) \
3283{ \
3284 struct qla_work_evt *e; \
3285 \
3286 e = qla2x00_alloc_work(vha, type); \
3287 if (!e) \
3288 return QLA_FUNCTION_FAILED; \
3289 \
3290 e->u.logio.fcport = fcport; \
3291 if (data) { \
3292 e->u.logio.data[0] = data[0]; \
3293 e->u.logio.data[1] = data[1]; \
3294 } \
3295 return qla2x00_post_work(vha, e); \
3296}
3297
3298qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3299qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3300qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3301qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3302qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3303qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3304
3420d36c
AV		 3305int
3306qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3307{
3308 struct qla_work_evt *e;
3309
3310 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3311 if (!e)
3312 return QLA_FUNCTION_FAILED;
3313
3314 e->u.uevent.code = code;
3315 return qla2x00_post_work(vha, e);
3316}
3317
3318static void
3319qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3320{
3321 char event_string[40];
3322 char *envp[] = { event_string, NULL };
3323
3324 switch (code) {
3325 case QLA_UEVENT_CODE_FW_DUMP:
3326 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3327 vha->host_no);
3328 break;
3329 default:
3330 /* do nothing */
3331 break;
3332 }
3333 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3334}
3335
ac280b67 3336void
e315cd28 3337qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3338{
f999f4c1
AV		 3339 struct qla_work_evt *e, *tmp;
3340 unsigned long flags;
3341 LIST_HEAD(work);
0971de7f 3342
f999f4c1
AV		 3343 spin_lock_irqsave(&vha->work_lock, flags);
3344 list_splice_init(&vha->work_list, &work);
3345 spin_unlock_irqrestore(&vha->work_lock, flags);
3346
3347 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3348 list_del_init(&e->list);
0971de7f
AV		 3349
3350 switch (e->type) {
3351 case QLA_EVT_AEN:
e315cd28 3352 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3353 e->u.aen.code, e->u.aen.data);
3354 break;
8a659571
AV		 3355 case QLA_EVT_IDC_ACK:
3356 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3357 break;
ac280b67
AV		 3358 case QLA_EVT_ASYNC_LOGIN:
3359 qla2x00_async_login(vha, e->u.logio.fcport,
3360 e->u.logio.data);
3361 break;
3362 case QLA_EVT_ASYNC_LOGIN_DONE:
3363 qla2x00_async_login_done(vha, e->u.logio.fcport,
3364 e->u.logio.data);
3365 break;
3366 case QLA_EVT_ASYNC_LOGOUT:
3367 qla2x00_async_logout(vha, e->u.logio.fcport);
3368 break;
3369 case QLA_EVT_ASYNC_LOGOUT_DONE:
3370 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3371 e->u.logio.data);
3372 break;
5ff1d584
AV		 3373 case QLA_EVT_ASYNC_ADISC:
3374 qla2x00_async_adisc(vha, e->u.logio.fcport,
3375 e->u.logio.data);
3376 break;
3377 case QLA_EVT_ASYNC_ADISC_DONE:
3378 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3379 e->u.logio.data);
3380 break;
3420d36c
AV		 3381 case QLA_EVT_UEVENT:
3382 qla2x00_uevent_emit(vha, e->u.uevent.code);
3383 break;
0971de7f
AV		 3384 }
3385 if (e->flags & QLA_EVT_FLAG_FREE)
3386 kfree(e);
feafb7b1
AE		 3387
3388 /* For each work completed decrement vha ref count */
3389 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3390 }
e315cd28 3391}
f999f4c1 3392
e315cd28
AC		 3393/* Relogins all the fcports of a vport
3394 * Context: dpc thread
3395 */
3396void qla2x00_relogin(struct scsi_qla_host *vha)
3397{
3398 fc_port_t *fcport;
c6b2fca8 3399 int status;
e315cd28
AC		 3400 uint16_t next_loopid = 0;
3401 struct qla_hw_data *ha = vha->hw;
ac280b67 3402 uint16_t data[2];
e315cd28
AC		 3403
3404 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3405 /*
3406 * If the port is not ONLINE then try to login
3407 * to it if we haven't run out of retries.
3408 */
5ff1d584
AV		 3409 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3410 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3411 fcport->login_retry--;
e315cd28 3412 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3413 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3414 ha->isp_ops->fabric_logout(vha,
3415 fcport->loop_id,
3416 fcport->d_id.b.domain,
3417 fcport->d_id.b.area,
3418 fcport->d_id.b.al_pa);
3419
03bcfb57
JC		 3420 if (fcport->loop_id == FC_NO_LOOP_ID) {
3421 fcport->loop_id = next_loopid =
3422 ha->min_external_loopid;
3423 status = qla2x00_find_new_loop_id(
3424 vha, fcport);
3425 if (status != QLA_SUCCESS) {
3426 /* Ran out of IDs to use */
3427 break;
3428 }
3429 }
3430
ac280b67 3431 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3432 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3433 data[0] = 0;
3434 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3435 status = qla2x00_post_async_login_work(
3436 vha, fcport, data);
3437 if (status == QLA_SUCCESS)
3438 continue;
3439 /* Attempt a retry. */
3440 status = 1;
3441 } else
3442 status = qla2x00_fabric_login(vha,
3443 fcport, &next_loopid);
e315cd28
AC		 3444 } else
3445 status = qla2x00_local_device_login(vha,
3446 fcport);
3447
e315cd28
AC		 3448 if (status == QLA_SUCCESS) {
3449 fcport->old_loop_id = fcport->loop_id;
3450
7c3df132
SK		 3451 ql_dbg(ql_dbg_disc, vha, 0x2003,
3452 "Port login OK: logged in ID 0x%x.\n",
3453 fcport->loop_id);
e315cd28
AC		 3454
3455 qla2x00_update_fcport(vha, fcport);
3456
3457 } else if (status == 1) {
3458 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3459 /* retry the login again */
7c3df132
SK		 3460 ql_dbg(ql_dbg_disc, vha, 0x2007,
3461 "Retrying %d login again loop_id 0x%x.\n",
3462 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3463 } else {
3464 fcport->login_retry = 0;
3465 }
3466
3467 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3468 fcport->loop_id = FC_NO_LOOP_ID;
3469 }
3470 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3471 break;
0971de7f 3472 }
0971de7f
AV		 3473}
3474
1da177e4
LT		 3475/**************************************************************************
3476* qla2x00_do_dpc
3477* This kernel thread is a task that is schedule by the interrupt handler
3478* to perform the background processing for interrupts.
3479*
3480* Notes:
3481* This task always run in the context of a kernel thread. It
3482* is kick-off by the driver's detect code and starts up
3483* up one per adapter. It immediately goes to sleep and waits for
3484* some fibre event. When either the interrupt handler or
3485* the timer routine detects a event it will one of the task
3486* bits then wake us up.
3487**************************************************************************/
3488static int
3489qla2x00_do_dpc(void *data)
3490{
2c3dfe3f 3491 int rval;
e315cd28
AC		 3492 scsi_qla_host_t *base_vha;
3493 struct qla_hw_data *ha;
1da177e4 3494
e315cd28
AC		 3495 ha = (struct qla_hw_data *)data;
3496 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 3497
1da177e4
LT		 3498 set_user_nice(current, -20);
3499
563585ec 3500 set_current_state(TASK_INTERRUPTIBLE);
39a11240 3501 while (!kthread_should_stop()) {
7c3df132
SK		 3502 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3503 "DPC handler sleeping.\n");
1da177e4 3504
39a11240
CH		 3505 schedule();
3506 __set_current_state(TASK_RUNNING);
1da177e4 3507
7c3df132
SK		 3508 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3509 "DPC handler waking up.\n");
3510 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3511 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
1da177e4
LT		 3512
3513 /* Initialization not yet finished. Don't do anything yet. */
e315cd28 3514 if (!base_vha->flags.init_done)
1da177e4
LT		 3515 continue;
3516
85880801 3517 if (ha->flags.eeh_busy) {
7c3df132
SK		 3518 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3519 "eeh_busy=%d.\n", ha->flags.eeh_busy);
85880801
AV		 3520 continue;
3521 }
3522
1da177e4
LT		 3523 ha->dpc_active = 1;
3524
1da177e4 3525 if (ha->flags.mbox_busy) {
1da177e4
LT		 3526 ha->dpc_active = 0;
3527 continue;
3528 }
3529
e315cd28 3530 qla2x00_do_work(base_vha);
0971de7f 3531
a9083016
GM		 3532 if (IS_QLA82XX(ha)) {
3533 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3534 &base_vha->dpc_flags)) {
3535 qla82xx_idc_lock(ha);
3536 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3537 QLA82XX_DEV_FAILED);
3538 qla82xx_idc_unlock(ha);
7c3df132
SK		 3539 ql_log(ql_log_info, base_vha, 0x4004,
3540 "HW State: FAILED.\n");
a9083016
GM		 3541 qla82xx_device_state_handler(base_vha);
3542 continue;
3543 }
3544
3545 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3546 &base_vha->dpc_flags)) {
3547
7c3df132
SK		 3548 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3549 "FCoE context reset scheduled.\n");
a9083016
GM		 3550 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3551 &base_vha->dpc_flags))) {
3552 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3553 /* FCoE-ctx reset failed.
3554 * Escalate to chip-reset
3555 */
3556 set_bit(ISP_ABORT_NEEDED,
3557 &base_vha->dpc_flags);
3558 }
3559 clear_bit(ABORT_ISP_ACTIVE,
3560 &base_vha->dpc_flags);
3561 }
3562
7c3df132
SK		 3563 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3564 "FCoE context reset end.\n");
a9083016
GM		 3565 }
3566 }
3567
e315cd28
AC		 3568 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3569 &base_vha->dpc_flags)) {
1da177e4 3570
7c3df132
SK		 3571 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3572 "ISP abort scheduled.\n");
1da177e4 3573 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 3574 &base_vha->dpc_flags))) {
1da177e4 3575
a9083016 3576 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 3577 /* failed. retry later */
3578 set_bit(ISP_ABORT_NEEDED,
e315cd28 3579 &base_vha->dpc_flags);
99363ef8 3580 }
e315cd28
AC		 3581 clear_bit(ABORT_ISP_ACTIVE,
3582 &base_vha->dpc_flags);
99363ef8
SJ		 3583 }
3584
7c3df132
SK		 3585 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3586 "ISP abort end.\n");
1da177e4
LT		 3587 }
3588
e315cd28
AC		 3589 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3590 qla2x00_update_fcports(base_vha);
3591 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 3592 }
d97994dc 3593
579d12b5 3594 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 3595 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3596 "Quiescence mode scheduled.\n");
579d12b5
SK		 3597 qla82xx_device_state_handler(base_vha);
3598 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3599 if (!ha->flags.quiesce_owner) {
3600 qla2x00_perform_loop_resync(base_vha);
3601
3602 qla82xx_idc_lock(ha);
3603 qla82xx_clear_qsnt_ready(base_vha);
3604 qla82xx_idc_unlock(ha);
3605 }
7c3df132
SK		 3606 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3607 "Quiescence mode end.\n");
579d12b5
SK		 3608 }
3609
e315cd28
AC		 3610 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3611 &base_vha->dpc_flags) &&
3612 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 3613
7c3df132
SK		 3614 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3615 "Reset marker scheduled.\n");
e315cd28
AC		 3616 qla2x00_rst_aen(base_vha);
3617 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 3618 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3619 "Reset marker end.\n");
1da177e4
LT		 3620 }
3621
3622 /* Retry each device up to login retry count */
e315cd28
AC		 3623 if ((test_and_clear_bit(RELOGIN_NEEDED,
3624 &base_vha->dpc_flags)) &&
3625 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3626 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 3627
7c3df132
SK		 3628 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3629 "Relogin scheduled.\n");
e315cd28 3630 qla2x00_relogin(base_vha);
7c3df132
SK		 3631 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3632 "Relogin end.\n");
1da177e4
LT		 3633 }
3634
e315cd28
AC		 3635 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3636 &base_vha->dpc_flags)) {
1da177e4 3637
7c3df132
SK		 3638 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3639 "Loop resync scheduled.\n");
1da177e4
LT		 3640
3641 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 3642 &base_vha->dpc_flags))) {
1da177e4 3643
e315cd28 3644 rval = qla2x00_loop_resync(base_vha);
1da177e4 3645
e315cd28
AC		 3646 clear_bit(LOOP_RESYNC_ACTIVE,
3647 &base_vha->dpc_flags);
1da177e4
LT		 3648 }
3649
7c3df132
SK		 3650 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3651 "Loop resync end.\n");
1da177e4
LT		 3652 }
3653
e315cd28
AC		 3654 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3655 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3656 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3657 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 3658 }
3659
1da177e4 3660 if (!ha->interrupts_on)
fd34f556 3661 ha->isp_ops->enable_intrs(ha);
1da177e4 3662
e315cd28
AC		 3663 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3664 &base_vha->dpc_flags))
3665 ha->isp_ops->beacon_blink(base_vha);
f6df144c 3666
e315cd28 3667 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 3668
1da177e4 3669 ha->dpc_active = 0;
563585ec 3670 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 3671 } /* End of while(1) */
563585ec 3672 __set_current_state(TASK_RUNNING);
1da177e4 3673
7c3df132
SK		 3674 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3675 "DPC handler exiting.\n");
1da177e4
LT		 3676
3677 /*
3678 * Make sure that nobody tries to wake us up again.
3679 */
1da177e4
LT		 3680 ha->dpc_active = 0;
3681
ac280b67
AV		 3682 /* Cleanup any residual CTX SRBs. */
3683 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3684
39a11240
CH		 3685 return 0;
3686}
3687
3688void
e315cd28 3689qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 3690{
e315cd28 3691 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 3692 struct task_struct *t = ha->dpc_thread;
3693
e315cd28 3694 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 3695 wake_up_process(t);
1da177e4
LT		 3696}
3697
1da177e4
LT		 3698/*
3699* qla2x00_rst_aen
3700* Processes asynchronous reset.
3701*
3702* Input:
3703* ha = adapter block pointer.
3704*/
3705static void
e315cd28 3706qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 3707{
e315cd28
AC		 3708 if (vha->flags.online && !vha->flags.reset_active &&
3709 !atomic_read(&vha->loop_down_timer) &&
3710 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 3711 do {
e315cd28 3712 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3713
3714 /*
3715 * Issue marker command only when we are going to start
3716 * the I/O.
3717 */
e315cd28
AC		 3718 vha->marker_needed = 1;
3719 } while (!atomic_read(&vha->loop_down_timer) &&
3720 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 3721 }
3722}
3723
f4f051eb 3724static void
e315cd28 3725qla2x00_sp_free_dma(srb_t *sp)
f4f051eb
AV		 3726{
3727 struct scsi_cmnd *cmd = sp->cmd;
bad75002 3728 struct qla_hw_data *ha = sp->fcport->vha->hw;
f4f051eb
AV		 3729
3730 if (sp->flags & SRB_DMA_VALID) {
385d70b4 3731 scsi_dma_unmap(cmd);
f4f051eb
AV		 3732 sp->flags &= ~SRB_DMA_VALID;
3733 }
bad75002
AE		 3734
3735 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
3736 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
3737 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
3738 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
3739 }
3740
3741 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
3742 /* List assured to be having elements */
3743 qla2x00_clean_dsd_pool(ha, sp);
3744 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
3745 }
3746
3747 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
3748 dma_pool_free(ha->dl_dma_pool, sp->ctx,
3749 ((struct crc_context *)sp->ctx)->crc_ctx_dma);
3750 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
3751 }
3752
fca29703 3753 CMD_SP(cmd) = NULL;
f4f051eb
AV		 3754}
3755
3dbe756a 3756static void
083a469d 3757qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
f4f051eb
AV		 3758{
3759 struct scsi_cmnd *cmd = sp->cmd;
3760
e315cd28 3761 qla2x00_sp_free_dma(sp);
f4f051eb 3762
a9083016
GM		 3763 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
3764 struct ct6_dsd *ctx = sp->ctx;
3765 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
3766 ctx->fcp_cmnd_dma);
3767 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
3768 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
3769 ha->gbl_dsd_avail += ctx->dsd_use_cnt;
3770 mempool_free(sp->ctx, ha->ctx_mempool);
3771 sp->ctx = NULL;
3772 }
f4f051eb 3773
a9083016 3774 mempool_free(sp, ha->srb_mempool);
f4f051eb
AV		 3775 cmd->scsi_done(cmd);
3776}
bdf79621 3777
083a469d
GM		 3778void
3779qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
3780{
3781 if (atomic_read(&sp->ref_count) == 0) {
7c3df132
SK		 3782 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
3783 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
3784 sp, sp->cmd);
3785 if (ql2xextended_error_logging & ql_dbg_io)
3786 BUG();
083a469d
GM		 3787 return;
3788 }
3789 if (!atomic_dec_and_test(&sp->ref_count))
3790 return;
3791 qla2x00_sp_final_compl(ha, sp);
3792}
3793
1da177e4
LT		 3794/**************************************************************************
3795* qla2x00_timer
3796*
3797* Description:
3798* One second timer
3799*
3800* Context: Interrupt
3801***************************************************************************/
2c3dfe3f 3802void
e315cd28 3803qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 3804{
1da177e4 3805 unsigned long cpu_flags = 0;
1da177e4
LT		 3806 int start_dpc = 0;
3807 int index;
3808 srb_t *sp;
85880801 3809 uint16_t w;
e315cd28 3810 struct qla_hw_data *ha = vha->hw;
73208dfd 3811 struct req_que *req;
85880801 3812
a5b36321 3813 if (ha->flags.eeh_busy) {
7c3df132
SK		 3814 ql_dbg(ql_dbg_timer, vha, 0x6000,
3815 "EEH = %d, restarting timer.\n",
3816 ha->flags.eeh_busy);
a5b36321
LC		 3817 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3818 return;
3819 }
3820
85880801
AV		 3821 /* Hardware read to raise pending EEH errors during mailbox waits. */
3822 if (!pci_channel_offline(ha->pdev))
3823 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 3824
cefcaba6
SK		 3825 /* Make sure qla82xx_watchdog is run only for physical port */
3826 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 3827 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3828 start_dpc++;
3829 qla82xx_watchdog(vha);
3830 }
3831
1da177e4 3832 /* Loop down handler. */
e315cd28 3833 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 3834 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3835 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 3836 && vha->flags.online) {
1da177e4 3837
e315cd28
AC		 3838 if (atomic_read(&vha->loop_down_timer) ==
3839 vha->loop_down_abort_time) {
1da177e4 3840
7c3df132
SK		 3841 ql_log(ql_log_info, vha, 0x6008,
3842 "Loop down - aborting the queues before time expires.\n");
1da177e4 3843
e315cd28
AC		 3844 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3845 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 3846
f08b7251
AV		 3847 /*
3848 * Schedule an ISP abort to return any FCP2-device
3849 * commands.
3850 */
2c3dfe3f 3851 /* NPIV - scan physical port only */
e315cd28 3852 if (!vha->vp_idx) {
2c3dfe3f
SJ		 3853 spin_lock_irqsave(&ha->hardware_lock,
3854 cpu_flags);
73208dfd 3855 req = ha->req_q_map[0];
2c3dfe3f
SJ		 3856 for (index = 1;
3857 index < MAX_OUTSTANDING_COMMANDS;
3858 index++) {
3859 fc_port_t *sfcp;
3860
e315cd28 3861 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 3862 if (!sp)
3863 continue;
bad75002 3864 if (sp->ctx && !IS_PROT_IO(sp))
cf53b069 3865 continue;
2c3dfe3f 3866 sfcp = sp->fcport;
f08b7251 3867 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 3868 continue;
bdf79621 3869
8f7daead
GM		 3870 if (IS_QLA82XX(ha))
3871 set_bit(FCOE_CTX_RESET_NEEDED,
3872 &vha->dpc_flags);
3873 else
3874 set_bit(ISP_ABORT_NEEDED,
e315cd28 3875 &vha->dpc_flags);
2c3dfe3f
SJ		 3876 break;
3877 }
3878 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 3879 cpu_flags);
1da177e4 3880 }
1da177e4
LT		 3881 start_dpc++;
3882 }
3883
3884 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 3885 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 3886 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 3887 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 3888 "Loop down - aborting ISP.\n");
3889
8f7daead
GM		 3890 if (IS_QLA82XX(ha))
3891 set_bit(FCOE_CTX_RESET_NEEDED,
3892 &vha->dpc_flags);
3893 else
3894 set_bit(ISP_ABORT_NEEDED,
3895 &vha->dpc_flags);
1da177e4
LT		 3896 }
3897 }
7c3df132
SK		 3898 ql_dbg(ql_dbg_timer, vha, 0x600a,
3899 "Loop down - seconds remaining %d.\n",
3900 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 3901 }
3902
cefcaba6
SK		 3903 /* Check if beacon LED needs to be blinked for physical host only */
3904 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
e315cd28 3905 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
f6df144c
AV		 3906 start_dpc++;
3907 }
3908
550bf57d 3909 /* Process any deferred work. */
e315cd28 3910 if (!list_empty(&vha->work_list))
550bf57d
AV		 3911 start_dpc++;
3912
1da177e4 3913 /* Schedule the DPC routine if needed */
e315cd28
AC		 3914 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3915 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3916 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 3917 start_dpc ||
e315cd28
AC		 3918 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3919 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 3920 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3921 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 3922 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 3923 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3924 ql_dbg(ql_dbg_timer, vha, 0x600b,
3925 "isp_abort_needed=%d loop_resync_needed=%d "
3926 "fcport_update_needed=%d start_dpc=%d "
3927 "reset_marker_needed=%d",
3928 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3929 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3930 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3931 start_dpc,
3932 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
3933 ql_dbg(ql_dbg_timer, vha, 0x600c,
3934 "beacon_blink_needed=%d isp_unrecoverable=%d "
3935 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3936 "relogin_needed=%d.\n",
3937 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
3938 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
3939 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
3940 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3941 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 3942 qla2xxx_wake_dpc(vha);
7c3df132 3943 }
1da177e4 3944
e315cd28 3945 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 3946}
3947
5433383e
AV		 3948/* Firmware interface routines. */
3949
a9083016 3950#define FW_BLOBS 8
5433383e
AV		 3951#define FW_ISP21XX 0
3952#define FW_ISP22XX 1
3953#define FW_ISP2300 2
3954#define FW_ISP2322 3
48c02fde 3955#define FW_ISP24XX 4
c3a2f0df 3956#define FW_ISP25XX 5
3a03eb79 3957#define FW_ISP81XX 6
a9083016 3958#define FW_ISP82XX 7
5433383e 3959
bb8ee499
AV		 3960#define FW_FILE_ISP21XX "ql2100_fw.bin"
3961#define FW_FILE_ISP22XX "ql2200_fw.bin"
3962#define FW_FILE_ISP2300 "ql2300_fw.bin"
3963#define FW_FILE_ISP2322 "ql2322_fw.bin"
3964#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 3965#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 3966#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 3967#define FW_FILE_ISP82XX "ql8200_fw.bin"
bb8ee499 3968
e1e82b6f 3969static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 3970
3971static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 3972 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
3973 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
3974 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
3975 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
3976 { .name = FW_FILE_ISP24XX, },
c3a2f0df 3977 { .name = FW_FILE_ISP25XX, },
3a03eb79 3978 { .name = FW_FILE_ISP81XX, },
a9083016 3979 { .name = FW_FILE_ISP82XX, },
5433383e
AV		 3980};
3981
3982struct fw_blob *
e315cd28 3983qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 3984{
e315cd28 3985 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 3986 struct fw_blob *blob;
3987
3988 blob = NULL;
3989 if (IS_QLA2100(ha)) {
3990 blob = &qla_fw_blobs[FW_ISP21XX];
3991 } else if (IS_QLA2200(ha)) {
3992 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 3993 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 3994 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 3995 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 3996 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 3997 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 3998 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 3999 } else if (IS_QLA25XX(ha)) {
4000 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 4001 } else if (IS_QLA81XX(ha)) {
4002 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 4003 } else if (IS_QLA82XX(ha)) {
4004 blob = &qla_fw_blobs[FW_ISP82XX];
5433383e
AV		 4005 }
4006
e1e82b6f 4007 mutex_lock(&qla_fw_lock);
5433383e
AV		 4008 if (blob->fw)
4009 goto out;
4010
4011 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4012 ql_log(ql_log_warn, vha, 0x0063,
4013 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4014 blob->fw = NULL;
4015 blob = NULL;
4016 goto out;
4017 }
4018
4019out:
e1e82b6f 4020 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4021 return blob;
4022}
4023
4024static void
4025qla2x00_release_firmware(void)
4026{
4027 int idx;
4028
e1e82b6f 4029 mutex_lock(&qla_fw_lock);
5433383e
AV		 4030 for (idx = 0; idx < FW_BLOBS; idx++)
4031 if (qla_fw_blobs[idx].fw)
4032 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4033 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4034}
4035
14e660e6
SJ		 4036static pci_ers_result_t
4037qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4038{
85880801
AV		 4039 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4040 struct qla_hw_data *ha = vha->hw;
4041
7c3df132
SK		 4042 ql_dbg(ql_dbg_aer, vha, 0x9000,
4043 "PCI error detected, state %x.\n", state);
b9b12f73 4044
14e660e6
SJ		 4045 switch (state) {
4046 case pci_channel_io_normal:
85880801 4047 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4048 return PCI_ERS_RESULT_CAN_RECOVER;
4049 case pci_channel_io_frozen:
85880801 4050 ha->flags.eeh_busy = 1;
a5b36321
LC		 4051 /* For ISP82XX complete any pending mailbox cmd */
4052 if (IS_QLA82XX(ha)) {
7190575f 4053 ha->flags.isp82xx_fw_hung = 1;
a5b36321
LC		 4054 if (ha->flags.mbox_busy) {
4055 ha->flags.mbox_int = 1;
7c3df132
SK		 4056 ql_dbg(ql_dbg_aer, vha, 0x9001,
4057 "Due to pci channel io frozen, doing premature "
4058 "completion of mbx command.\n");
a5b36321
LC		 4059 complete(&ha->mbx_intr_comp);
4060 }
4061 }
90a86fc0 4062 qla2x00_free_irqs(vha);
14e660e6 4063 pci_disable_device(pdev);
bddd2d65
LC		 4064 /* Return back all IOs */
4065 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4066 return PCI_ERS_RESULT_NEED_RESET;
4067 case pci_channel_io_perm_failure:
85880801
AV		 4068 ha->flags.pci_channel_io_perm_failure = 1;
4069 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4070 return PCI_ERS_RESULT_DISCONNECT;
4071 }
4072 return PCI_ERS_RESULT_NEED_RESET;
4073}
4074
4075static pci_ers_result_t
4076qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4077{
4078 int risc_paused = 0;
4079 uint32_t stat;
4080 unsigned long flags;
e315cd28
AC		 4081 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4082 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4083 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4084 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4085
bcc5b6d3
SK		 4086 if (IS_QLA82XX(ha))
4087 return PCI_ERS_RESULT_RECOVERED;
4088
14e660e6
SJ		 4089 spin_lock_irqsave(&ha->hardware_lock, flags);
4090 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4091 stat = RD_REG_DWORD(&reg->hccr);
4092 if (stat & HCCR_RISC_PAUSE)
4093 risc_paused = 1;
4094 } else if (IS_QLA23XX(ha)) {
4095 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4096 if (stat & HSR_RISC_PAUSED)
4097 risc_paused = 1;
4098 } else if (IS_FWI2_CAPABLE(ha)) {
4099 stat = RD_REG_DWORD(&reg24->host_status);
4100 if (stat & HSRX_RISC_PAUSED)
4101 risc_paused = 1;
4102 }
4103 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4104
4105 if (risc_paused) {
7c3df132
SK		 4106 ql_log(ql_log_info, base_vha, 0x9003,
4107 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4108 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4109
4110 return PCI_ERS_RESULT_NEED_RESET;
4111 } else
4112 return PCI_ERS_RESULT_RECOVERED;
4113}
4114
a5b36321
LC		 4115uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4116{
4117 uint32_t rval = QLA_FUNCTION_FAILED;
4118 uint32_t drv_active = 0;
4119 struct qla_hw_data *ha = base_vha->hw;
4120 int fn;
4121 struct pci_dev *other_pdev = NULL;
4122
7c3df132
SK		 4123 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4124 "Entered %s.\n", __func__);
a5b36321
LC		 4125
4126 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4127
4128 if (base_vha->flags.online) {
4129 /* Abort all outstanding commands,
4130 * so as to be requeued later */
4131 qla2x00_abort_isp_cleanup(base_vha);
4132 }
4133
4134
4135 fn = PCI_FUNC(ha->pdev->devfn);
4136 while (fn > 0) {
4137 fn--;
7c3df132
SK		 4138 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4139 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 4140 other_pdev =
4141 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4142 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4143 fn));
4144
4145 if (!other_pdev)
4146 continue;
4147 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 4148 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4149 "Found PCI func available and enable at 0x%x.\n",
4150 fn);
a5b36321
LC		 4151 pci_dev_put(other_pdev);
4152 break;
4153 }
4154 pci_dev_put(other_pdev);
4155 }
4156
4157 if (!fn) {
4158 /* Reset owner */
7c3df132
SK		 4159 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4160 "This devfn is reset owner = 0x%x.\n",
4161 ha->pdev->devfn);
a5b36321
LC		 4162 qla82xx_idc_lock(ha);
4163
4164 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4165 QLA82XX_DEV_INITIALIZING);
4166
4167 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4168 QLA82XX_IDC_VERSION);
4169
4170 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 4171 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4172 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 4173
4174 qla82xx_idc_unlock(ha);
4175 /* Reset if device is not already reset
4176 * drv_active would be 0 if a reset has already been done
4177 */
4178 if (drv_active)
4179 rval = qla82xx_start_firmware(base_vha);
4180 else
4181 rval = QLA_SUCCESS;
4182 qla82xx_idc_lock(ha);
4183
4184 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4185 ql_log(ql_log_info, base_vha, 0x900b,
4186 "HW State: FAILED.\n");
a5b36321
LC		 4187 qla82xx_clear_drv_active(ha);
4188 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4189 QLA82XX_DEV_FAILED);
4190 } else {
7c3df132
SK		 4191 ql_log(ql_log_info, base_vha, 0x900c,
4192 "HW State: READY.\n");
a5b36321
LC		 4193 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4194 QLA82XX_DEV_READY);
4195 qla82xx_idc_unlock(ha);
7190575f 4196 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4197 rval = qla82xx_restart_isp(base_vha);
4198 qla82xx_idc_lock(ha);
4199 /* Clear driver state register */
4200 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4201 qla82xx_set_drv_active(base_vha);
4202 }
4203 qla82xx_idc_unlock(ha);
4204 } else {
7c3df132
SK		 4205 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4206 "This devfn is not reset owner = 0x%x.\n",
4207 ha->pdev->devfn);
a5b36321
LC		 4208 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4209 QLA82XX_DEV_READY)) {
7190575f 4210 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4211 rval = qla82xx_restart_isp(base_vha);
4212 qla82xx_idc_lock(ha);
4213 qla82xx_set_drv_active(base_vha);
4214 qla82xx_idc_unlock(ha);
4215 }
4216 }
4217 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4218
4219 return rval;
4220}
4221
14e660e6
SJ		 4222static pci_ers_result_t
4223qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4224{
4225 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 4226 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4227 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 4228 struct rsp_que *rsp;
4229 int rc, retries = 10;
09483916 4230
7c3df132
SK		 4231 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4232 "Slot Reset.\n");
85880801 4233
90a86fc0
JC		 4234 /* Workaround: qla2xxx driver which access hardware earlier
4235 * needs error state to be pci_channel_io_online.
4236 * Otherwise mailbox command timesout.
4237 */
4238 pdev->error_state = pci_channel_io_normal;
4239
4240 pci_restore_state(pdev);
4241
8c1496bd
RL		 4242 /* pci_restore_state() clears the saved_state flag of the device
4243 * save restored state which resets saved_state flag
4244 */
4245 pci_save_state(pdev);
4246
09483916
BH		 4247 if (ha->mem_only)
4248 rc = pci_enable_device_mem(pdev);
4249 else
4250 rc = pci_enable_device(pdev);
14e660e6 4251
09483916 4252 if (rc) {
7c3df132 4253 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 4254 "Can't re-enable PCI device after reset.\n");
a5b36321 4255 goto exit_slot_reset;
14e660e6 4256 }
14e660e6 4257
90a86fc0
JC		 4258 rsp = ha->rsp_q_map[0];
4259 if (qla2x00_request_irqs(ha, rsp))
a5b36321 4260 goto exit_slot_reset;
90a86fc0 4261
e315cd28 4262 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 4263 goto exit_slot_reset;
4264
4265 if (IS_QLA82XX(ha)) {
4266 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4267 ret = PCI_ERS_RESULT_RECOVERED;
4268 goto exit_slot_reset;
4269 } else
4270 goto exit_slot_reset;
4271 }
14e660e6 4272
90a86fc0
JC		 4273 while (ha->flags.mbox_busy && retries--)
4274 msleep(1000);
85880801 4275
e315cd28 4276 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 4277 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 4278 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 4279 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 4280
90a86fc0 4281
a5b36321 4282exit_slot_reset:
7c3df132
SK		 4283 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4284 "slot_reset return %x.\n", ret);
85880801 4285
14e660e6
SJ		 4286 return ret;
4287}
4288
4289static void
4290qla2xxx_pci_resume(struct pci_dev *pdev)
4291{
e315cd28
AC		 4292 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4293 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4294 int ret;
4295
7c3df132
SK		 4296 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4297 "pci_resume.\n");
85880801 4298
e315cd28 4299 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 4300 if (ret != QLA_SUCCESS) {
7c3df132
SK		 4301 ql_log(ql_log_fatal, base_vha, 0x9002,
4302 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 4303 }
85880801 4304
3e46f031
LC		 4305 pci_cleanup_aer_uncorrect_error_status(pdev);
4306
85880801 4307 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4308}
4309
4310static struct pci_error_handlers qla2xxx_err_handler = {
4311 .error_detected = qla2xxx_pci_error_detected,
4312 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4313 .slot_reset = qla2xxx_pci_slot_reset,
4314 .resume = qla2xxx_pci_resume,
4315};
4316
5433383e 4317static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 4318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 4327 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 4328 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4329 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 4330 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
3a03eb79 4331 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 4332 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5433383e
AV		 4333 { 0 },
4334};
4335MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4336
fca29703 4337static struct pci_driver qla2xxx_pci_driver = {
cb63067a 4338 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 4339 .driver = {
4340 .owner = THIS_MODULE,
4341 },
fca29703 4342 .id_table = qla2xxx_pci_tbl,
7ee61397 4343 .probe = qla2x00_probe_one,
4c993f76 4344 .remove = qla2x00_remove_one,
e30d1756 4345 .shutdown = qla2x00_shutdown,
14e660e6 4346 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 4347};
4348
6a03b4cd
HZ		 4349static struct file_operations apidev_fops = {
4350 .owner = THIS_MODULE,
6038f373 4351 .llseek = noop_llseek,
6a03b4cd
HZ		 4352};
4353
1da177e4
LT		 4354/**
4355 * qla2x00_module_init - Module initialization.
4356 **/
4357static int __init
4358qla2x00_module_init(void)
4359{
fca29703
AV		 4360 int ret = 0;
4361
1da177e4 4362 /* Allocate cache for SRBs. */
354d6b21 4363 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 4364 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 4365 if (srb_cachep == NULL) {
7c3df132
SK		 4366 ql_log(ql_log_fatal, NULL, 0x0001,
4367 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 4368 return -ENOMEM;
4369 }
4370
4371 /* Derive version string. */
4372 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 4373 if (ql2xextended_error_logging)
0181944f
AV		 4374 strcat(qla2x00_version_str, "-debug");
4375
1c97a12a
AV		 4376 qla2xxx_transport_template =
4377 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 4378 if (!qla2xxx_transport_template) {
4379 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 4380 ql_log(ql_log_fatal, NULL, 0x0002,
4381 "fc_attach_transport failed...Failing load!.\n");
1da177e4 4382 return -ENODEV;
2c3dfe3f 4383 }
6a03b4cd
HZ		 4384
4385 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4386 if (apidev_major < 0) {
7c3df132
SK		 4387 ql_log(ql_log_fatal, NULL, 0x0003,
4388 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 4389 }
4390
2c3dfe3f
SJ		 4391 qla2xxx_transport_vport_template =
4392 fc_attach_transport(&qla2xxx_transport_vport_functions);
4393 if (!qla2xxx_transport_vport_template) {
4394 kmem_cache_destroy(srb_cachep);
4395 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 4396 ql_log(ql_log_fatal, NULL, 0x0004,
4397 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 4398 return -ENODEV;
2c3dfe3f 4399 }
7c3df132
SK		 4400 ql_log(ql_log_info, NULL, 0x0005,
4401 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 4402 qla2x00_version_str);
7ee61397 4403 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 4404 if (ret) {
4405 kmem_cache_destroy(srb_cachep);
4406 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4407 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 4408 ql_log(ql_log_fatal, NULL, 0x0006,
4409 "pci_register_driver failed...ret=%d Failing load!.\n",
4410 ret);
fca29703
AV		 4411 }
4412 return ret;
1da177e4
LT		 4413}
4414
4415/**
4416 * qla2x00_module_exit - Module cleanup.
4417 **/
4418static void __exit
4419qla2x00_module_exit(void)
4420{
6a03b4cd 4421 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 4422 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 4423 qla2x00_release_firmware();
354d6b21 4424 kmem_cache_destroy(srb_cachep);
a9083016
GM		 4425 if (ctx_cachep)
4426 kmem_cache_destroy(ctx_cachep);
1da177e4 4427 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4428 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 4429}
4430
4431module_init(qla2x00_module_init);
4432module_exit(qla2x00_module_exit);
4433
4434MODULE_AUTHOR("QLogic Corporation");
4435MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4436MODULE_LICENSE("GPL");
4437MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 4438MODULE_FIRMWARE(FW_FILE_ISP21XX);
4439MODULE_FIRMWARE(FW_FILE_ISP22XX);
4440MODULE_FIRMWARE(FW_FILE_ISP2300);
4441MODULE_FIRMWARE(FW_FILE_ISP2322);
4442MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 4443MODULE_FIRMWARE(FW_FILE_ISP25XX);
kernel source for telekom puls (alcatel/mediatek)