| 1 | /* |
| 2 | * QLogic Fibre Channel HBA Driver |
| 3 | * Copyright (c) 2003-2012 QLogic Corporation |
| 4 | * |
| 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
| 6 | */ |
| 7 | #include "qla_def.h" |
| 8 | |
| 9 | #include <linux/moduleparam.h> |
| 10 | #include <linux/vmalloc.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/kthread.h> |
| 13 | #include <linux/mutex.h> |
| 14 | #include <linux/kobject.h> |
| 15 | #include <linux/slab.h> |
| 16 | #include <scsi/scsi_tcq.h> |
| 17 | #include <scsi/scsicam.h> |
| 18 | #include <scsi/scsi_transport.h> |
| 19 | #include <scsi/scsi_transport_fc.h> |
| 20 | |
| 21 | #include "qla_target.h" |
| 22 | |
| 23 | /* |
| 24 | * Driver version |
| 25 | */ |
| 26 | char qla2x00_version_str[40]; |
| 27 | |
| 28 | static int apidev_major; |
| 29 | |
| 30 | /* |
| 31 | * SRB allocation cache |
| 32 | */ |
| 33 | static struct kmem_cache *srb_cachep; |
| 34 | |
| 35 | /* |
| 36 | * CT6 CTX allocation cache |
| 37 | */ |
| 38 | static struct kmem_cache *ctx_cachep; |
| 39 | /* |
| 40 | * error level for logging |
| 41 | */ |
| 42 | int ql_errlev = ql_log_all; |
| 43 | |
| 44 | int ql2xenableclass2; |
| 45 | module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); |
| 46 | MODULE_PARM_DESC(ql2xenableclass2, |
| 47 | "Specify if Class 2 operations are supported from the very " |
| 48 | "beginning. Default is 0 - class 2 not supported."); |
| 49 | |
| 50 | int ql2xlogintimeout = 20; |
| 51 | module_param(ql2xlogintimeout, int, S_IRUGO); |
| 52 | MODULE_PARM_DESC(ql2xlogintimeout, |
| 53 | "Login timeout value in seconds."); |
| 54 | |
| 55 | int qlport_down_retry; |
| 56 | module_param(qlport_down_retry, int, S_IRUGO); |
| 57 | MODULE_PARM_DESC(qlport_down_retry, |
| 58 | "Maximum number of command retries to a port that returns " |
| 59 | "a PORT-DOWN status."); |
| 60 | |
| 61 | int ql2xplogiabsentdevice; |
| 62 | module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); |
| 63 | MODULE_PARM_DESC(ql2xplogiabsentdevice, |
| 64 | "Option to enable PLOGI to devices that are not present after " |
| 65 | "a Fabric scan. This is needed for several broken switches. " |
| 66 | "Default is 0 - no PLOGI. 1 - perfom PLOGI."); |
| 67 | |
| 68 | int ql2xloginretrycount = 0; |
| 69 | module_param(ql2xloginretrycount, int, S_IRUGO); |
| 70 | MODULE_PARM_DESC(ql2xloginretrycount, |
| 71 | "Specify an alternate value for the NVRAM login retry count."); |
| 72 | |
| 73 | int ql2xallocfwdump = 1; |
| 74 | module_param(ql2xallocfwdump, int, S_IRUGO); |
| 75 | MODULE_PARM_DESC(ql2xallocfwdump, |
| 76 | "Option to enable allocation of memory for a firmware dump " |
| 77 | "during HBA initialization. Memory allocation requirements " |
| 78 | "vary by ISP type. Default is 1 - allocate memory."); |
| 79 | |
| 80 | int ql2xextended_error_logging; |
| 81 | module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); |
| 82 | MODULE_PARM_DESC(ql2xextended_error_logging, |
| 83 | "Option to enable extended error logging,\n" |
| 84 | "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" |
| 85 | "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" |
| 86 | "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" |
| 87 | "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" |
| 88 | "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" |
| 89 | "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" |
| 90 | "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" |
| 91 | "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" |
| 92 | "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" |
| 93 | "\t\t0x1e400000 - Preferred value for capturing essential " |
| 94 | "debug information (equivalent to old " |
| 95 | "ql2xextended_error_logging=1).\n" |
| 96 | "\t\tDo LOGICAL OR of the value to enable more than one level"); |
| 97 | |
| 98 | int ql2xshiftctondsd = 6; |
| 99 | module_param(ql2xshiftctondsd, int, S_IRUGO); |
| 100 | MODULE_PARM_DESC(ql2xshiftctondsd, |
| 101 | "Set to control shifting of command type processing " |
| 102 | "based on total number of SG elements."); |
| 103 | |
| 104 | static void qla2x00_free_device(scsi_qla_host_t *); |
| 105 | |
| 106 | int ql2xfdmienable=1; |
| 107 | module_param(ql2xfdmienable, int, S_IRUGO); |
| 108 | MODULE_PARM_DESC(ql2xfdmienable, |
| 109 | "Enables FDMI registrations. " |
| 110 | "0 - no FDMI. Default is 1 - perform FDMI."); |
| 111 | |
| 112 | #define MAX_Q_DEPTH 32 |
| 113 | static int ql2xmaxqdepth = MAX_Q_DEPTH; |
| 114 | module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); |
| 115 | MODULE_PARM_DESC(ql2xmaxqdepth, |
| 116 | "Maximum queue depth to report for target devices."); |
| 117 | |
| 118 | /* Do not change the value of this after module load */ |
| 119 | int ql2xenabledif = 0; |
| 120 | module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR); |
| 121 | MODULE_PARM_DESC(ql2xenabledif, |
| 122 | " Enable T10-CRC-DIF " |
| 123 | " Default is 0 - No DIF Support. 1 - Enable it" |
| 124 | ", 2 - Enable DIF for all types, except Type 0."); |
| 125 | |
| 126 | int ql2xenablehba_err_chk = 2; |
| 127 | module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); |
| 128 | MODULE_PARM_DESC(ql2xenablehba_err_chk, |
| 129 | " Enable T10-CRC-DIF Error isolation by HBA:\n" |
| 130 | " Default is 1.\n" |
| 131 | " 0 -- Error isolation disabled\n" |
| 132 | " 1 -- Error isolation enabled only for DIX Type 0\n" |
| 133 | " 2 -- Error isolation enabled for all Types\n"); |
| 134 | |
| 135 | int ql2xiidmaenable=1; |
| 136 | module_param(ql2xiidmaenable, int, S_IRUGO); |
| 137 | MODULE_PARM_DESC(ql2xiidmaenable, |
| 138 | "Enables iIDMA settings " |
| 139 | "Default is 1 - perform iIDMA. 0 - no iIDMA."); |
| 140 | |
| 141 | int ql2xmaxqueues = 1; |
| 142 | module_param(ql2xmaxqueues, int, S_IRUGO); |
| 143 | MODULE_PARM_DESC(ql2xmaxqueues, |
| 144 | "Enables MQ settings " |
| 145 | "Default is 1 for single queue. Set it to number " |
| 146 | "of queues in MQ mode."); |
| 147 | |
| 148 | int ql2xmultique_tag; |
| 149 | module_param(ql2xmultique_tag, int, S_IRUGO); |
| 150 | MODULE_PARM_DESC(ql2xmultique_tag, |
| 151 | "Enables CPU affinity settings for the driver " |
| 152 | "Default is 0 for no affinity of request and response IO. " |
| 153 | "Set it to 1 to turn on the cpu affinity."); |
| 154 | |
| 155 | int ql2xfwloadbin; |
| 156 | module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); |
| 157 | MODULE_PARM_DESC(ql2xfwloadbin, |
| 158 | "Option to specify location from which to load ISP firmware:.\n" |
| 159 | " 2 -- load firmware via the request_firmware() (hotplug).\n" |
| 160 | " interface.\n" |
| 161 | " 1 -- load firmware from flash.\n" |
| 162 | " 0 -- use default semantics.\n"); |
| 163 | |
| 164 | int ql2xetsenable; |
| 165 | module_param(ql2xetsenable, int, S_IRUGO); |
| 166 | MODULE_PARM_DESC(ql2xetsenable, |
| 167 | "Enables firmware ETS burst." |
| 168 | "Default is 0 - skip ETS enablement."); |
| 169 | |
| 170 | int ql2xdbwr = 1; |
| 171 | module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); |
| 172 | MODULE_PARM_DESC(ql2xdbwr, |
| 173 | "Option to specify scheme for request queue posting.\n" |
| 174 | " 0 -- Regular doorbell.\n" |
| 175 | " 1 -- CAMRAM doorbell (faster).\n"); |
| 176 | |
| 177 | int ql2xtargetreset = 1; |
| 178 | module_param(ql2xtargetreset, int, S_IRUGO); |
| 179 | MODULE_PARM_DESC(ql2xtargetreset, |
| 180 | "Enable target reset." |
| 181 | "Default is 1 - use hw defaults."); |
| 182 | |
| 183 | int ql2xgffidenable; |
| 184 | module_param(ql2xgffidenable, int, S_IRUGO); |
| 185 | MODULE_PARM_DESC(ql2xgffidenable, |
| 186 | "Enables GFF_ID checks of port type. " |
| 187 | "Default is 0 - Do not use GFF_ID information."); |
| 188 | |
| 189 | int ql2xasynctmfenable; |
| 190 | module_param(ql2xasynctmfenable, int, S_IRUGO); |
| 191 | MODULE_PARM_DESC(ql2xasynctmfenable, |
| 192 | "Enables issue of TM IOCBs asynchronously via IOCB mechanism" |
| 193 | "Default is 0 - Issue TM IOCBs via mailbox mechanism."); |
| 194 | |
| 195 | int ql2xdontresethba; |
| 196 | module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); |
| 197 | MODULE_PARM_DESC(ql2xdontresethba, |
| 198 | "Option to specify reset behaviour.\n" |
| 199 | " 0 (Default) -- Reset on failure.\n" |
| 200 | " 1 -- Do not reset on failure.\n"); |
| 201 | |
| 202 | uint ql2xmaxlun = MAX_LUNS; |
| 203 | module_param(ql2xmaxlun, uint, S_IRUGO); |
| 204 | MODULE_PARM_DESC(ql2xmaxlun, |
| 205 | "Defines the maximum LU number to register with the SCSI " |
| 206 | "midlayer. Default is 65535."); |
| 207 | |
| 208 | int ql2xmdcapmask = 0x1F; |
| 209 | module_param(ql2xmdcapmask, int, S_IRUGO); |
| 210 | MODULE_PARM_DESC(ql2xmdcapmask, |
| 211 | "Set the Minidump driver capture mask level. " |
| 212 | "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); |
| 213 | |
| 214 | int ql2xmdenable = 1; |
| 215 | module_param(ql2xmdenable, int, S_IRUGO); |
| 216 | MODULE_PARM_DESC(ql2xmdenable, |
| 217 | "Enable/disable MiniDump. " |
| 218 | "0 - MiniDump disabled. " |
| 219 | "1 (Default) - MiniDump enabled."); |
| 220 | |
| 221 | /* |
| 222 | * SCSI host template entry points |
| 223 | */ |
| 224 | static int qla2xxx_slave_configure(struct scsi_device * device); |
| 225 | static int qla2xxx_slave_alloc(struct scsi_device *); |
| 226 | static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); |
| 227 | static void qla2xxx_scan_start(struct Scsi_Host *); |
| 228 | static void qla2xxx_slave_destroy(struct scsi_device *); |
| 229 | static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
| 230 | static int qla2xxx_eh_abort(struct scsi_cmnd *); |
| 231 | static int qla2xxx_eh_device_reset(struct scsi_cmnd *); |
| 232 | static int qla2xxx_eh_target_reset(struct scsi_cmnd *); |
| 233 | static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); |
| 234 | static int qla2xxx_eh_host_reset(struct scsi_cmnd *); |
| 235 | |
| 236 | static int qla2x00_change_queue_depth(struct scsi_device *, int, int); |
| 237 | static int qla2x00_change_queue_type(struct scsi_device *, int); |
| 238 | |
| 239 | struct scsi_host_template qla2xxx_driver_template = { |
| 240 | .module = THIS_MODULE, |
| 241 | .name = QLA2XXX_DRIVER_NAME, |
| 242 | .queuecommand = qla2xxx_queuecommand, |
| 243 | |
| 244 | .eh_abort_handler = qla2xxx_eh_abort, |
| 245 | .eh_device_reset_handler = qla2xxx_eh_device_reset, |
| 246 | .eh_target_reset_handler = qla2xxx_eh_target_reset, |
| 247 | .eh_bus_reset_handler = qla2xxx_eh_bus_reset, |
| 248 | .eh_host_reset_handler = qla2xxx_eh_host_reset, |
| 249 | |
| 250 | .slave_configure = qla2xxx_slave_configure, |
| 251 | |
| 252 | .slave_alloc = qla2xxx_slave_alloc, |
| 253 | .slave_destroy = qla2xxx_slave_destroy, |
| 254 | .scan_finished = qla2xxx_scan_finished, |
| 255 | .scan_start = qla2xxx_scan_start, |
| 256 | .change_queue_depth = qla2x00_change_queue_depth, |
| 257 | .change_queue_type = qla2x00_change_queue_type, |
| 258 | .this_id = -1, |
| 259 | .cmd_per_lun = 3, |
| 260 | .use_clustering = ENABLE_CLUSTERING, |
| 261 | .sg_tablesize = SG_ALL, |
| 262 | |
| 263 | .max_sectors = 0xFFFF, |
| 264 | .shost_attrs = qla2x00_host_attrs, |
| 265 | |
| 266 | .supported_mode = MODE_INITIATOR, |
| 267 | }; |
| 268 | |
| 269 | static struct scsi_transport_template *qla2xxx_transport_template = NULL; |
| 270 | struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; |
| 271 | |
| 272 | /* TODO Convert to inlines |
| 273 | * |
| 274 | * Timer routines |
| 275 | */ |
| 276 | |
| 277 | __inline__ void |
| 278 | qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) |
| 279 | { |
| 280 | init_timer(&vha->timer); |
| 281 | vha->timer.expires = jiffies + interval * HZ; |
| 282 | vha->timer.data = (unsigned long)vha; |
| 283 | vha->timer.function = (void (*)(unsigned long))func; |
| 284 | add_timer(&vha->timer); |
| 285 | vha->timer_active = 1; |
| 286 | } |
| 287 | |
| 288 | static inline void |
| 289 | qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) |
| 290 | { |
| 291 | /* Currently used for 82XX only. */ |
| 292 | if (vha->device_flags & DFLG_DEV_FAILED) { |
| 293 | ql_dbg(ql_dbg_timer, vha, 0x600d, |
| 294 | "Device in a failed state, returning.\n"); |
| 295 | return; |
| 296 | } |
| 297 | |
| 298 | mod_timer(&vha->timer, jiffies + interval * HZ); |
| 299 | } |
| 300 | |
| 301 | static __inline__ void |
| 302 | qla2x00_stop_timer(scsi_qla_host_t *vha) |
| 303 | { |
| 304 | del_timer_sync(&vha->timer); |
| 305 | vha->timer_active = 0; |
| 306 | } |
| 307 | |
| 308 | static int qla2x00_do_dpc(void *data); |
| 309 | |
| 310 | static void qla2x00_rst_aen(scsi_qla_host_t *); |
| 311 | |
| 312 | static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, |
| 313 | struct req_que **, struct rsp_que **); |
| 314 | static void qla2x00_free_fw_dump(struct qla_hw_data *); |
| 315 | static void qla2x00_mem_free(struct qla_hw_data *); |
| 316 | |
| 317 | /* -------------------------------------------------------------------------- */ |
| 318 | static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, |
| 319 | struct rsp_que *rsp) |
| 320 | { |
| 321 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
| 322 | ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, |
| 323 | GFP_KERNEL); |
| 324 | if (!ha->req_q_map) { |
| 325 | ql_log(ql_log_fatal, vha, 0x003b, |
| 326 | "Unable to allocate memory for request queue ptrs.\n"); |
| 327 | goto fail_req_map; |
| 328 | } |
| 329 | |
| 330 | ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, |
| 331 | GFP_KERNEL); |
| 332 | if (!ha->rsp_q_map) { |
| 333 | ql_log(ql_log_fatal, vha, 0x003c, |
| 334 | "Unable to allocate memory for response queue ptrs.\n"); |
| 335 | goto fail_rsp_map; |
| 336 | } |
| 337 | /* |
| 338 | * Make sure we record at least the request and response queue zero in |
| 339 | * case we need to free them if part of the probe fails. |
| 340 | */ |
| 341 | ha->rsp_q_map[0] = rsp; |
| 342 | ha->req_q_map[0] = req; |
| 343 | set_bit(0, ha->rsp_qid_map); |
| 344 | set_bit(0, ha->req_qid_map); |
| 345 | return 1; |
| 346 | |
| 347 | fail_rsp_map: |
| 348 | kfree(ha->req_q_map); |
| 349 | ha->req_q_map = NULL; |
| 350 | fail_req_map: |
| 351 | return -ENOMEM; |
| 352 | } |
| 353 | |
| 354 | static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) |
| 355 | { |
| 356 | if (req && req->ring) |
| 357 | dma_free_coherent(&ha->pdev->dev, |
| 358 | (req->length + 1) * sizeof(request_t), |
| 359 | req->ring, req->dma); |
| 360 | |
| 361 | kfree(req); |
| 362 | req = NULL; |
| 363 | } |
| 364 | |
| 365 | static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) |
| 366 | { |
| 367 | if (rsp && rsp->ring) |
| 368 | dma_free_coherent(&ha->pdev->dev, |
| 369 | (rsp->length + 1) * sizeof(response_t), |
| 370 | rsp->ring, rsp->dma); |
| 371 | |
| 372 | kfree(rsp); |
| 373 | rsp = NULL; |
| 374 | } |
| 375 | |
| 376 | static void qla2x00_free_queues(struct qla_hw_data *ha) |
| 377 | { |
| 378 | struct req_que *req; |
| 379 | struct rsp_que *rsp; |
| 380 | int cnt; |
| 381 | |
| 382 | for (cnt = 0; cnt < ha->max_req_queues; cnt++) { |
| 383 | req = ha->req_q_map[cnt]; |
| 384 | qla2x00_free_req_que(ha, req); |
| 385 | } |
| 386 | kfree(ha->req_q_map); |
| 387 | ha->req_q_map = NULL; |
| 388 | |
| 389 | for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { |
| 390 | rsp = ha->rsp_q_map[cnt]; |
| 391 | qla2x00_free_rsp_que(ha, rsp); |
| 392 | } |
| 393 | kfree(ha->rsp_q_map); |
| 394 | ha->rsp_q_map = NULL; |
| 395 | } |
| 396 | |
| 397 | static int qla25xx_setup_mode(struct scsi_qla_host *vha) |
| 398 | { |
| 399 | uint16_t options = 0; |
| 400 | int ques, req, ret; |
| 401 | struct qla_hw_data *ha = vha->hw; |
| 402 | |
| 403 | if (!(ha->fw_attributes & BIT_6)) { |
| 404 | ql_log(ql_log_warn, vha, 0x00d8, |
| 405 | "Firmware is not multi-queue capable.\n"); |
| 406 | goto fail; |
| 407 | } |
| 408 | if (ql2xmultique_tag) { |
| 409 | /* create a request queue for IO */ |
| 410 | options |= BIT_7; |
| 411 | req = qla25xx_create_req_que(ha, options, 0, 0, -1, |
| 412 | QLA_DEFAULT_QUE_QOS); |
| 413 | if (!req) { |
| 414 | ql_log(ql_log_warn, vha, 0x00e0, |
| 415 | "Failed to create request queue.\n"); |
| 416 | goto fail; |
| 417 | } |
| 418 | ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); |
| 419 | vha->req = ha->req_q_map[req]; |
| 420 | options |= BIT_1; |
| 421 | for (ques = 1; ques < ha->max_rsp_queues; ques++) { |
| 422 | ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); |
| 423 | if (!ret) { |
| 424 | ql_log(ql_log_warn, vha, 0x00e8, |
| 425 | "Failed to create response queue.\n"); |
| 426 | goto fail2; |
| 427 | } |
| 428 | } |
| 429 | ha->flags.cpu_affinity_enabled = 1; |
| 430 | ql_dbg(ql_dbg_multiq, vha, 0xc007, |
| 431 | "CPU affinity mode enalbed, " |
| 432 | "no. of response queues:%d no. of request queues:%d.\n", |
| 433 | ha->max_rsp_queues, ha->max_req_queues); |
| 434 | ql_dbg(ql_dbg_init, vha, 0x00e9, |
| 435 | "CPU affinity mode enalbed, " |
| 436 | "no. of response queues:%d no. of request queues:%d.\n", |
| 437 | ha->max_rsp_queues, ha->max_req_queues); |
| 438 | } |
| 439 | return 0; |
| 440 | fail2: |
| 441 | qla25xx_delete_queues(vha); |
| 442 | destroy_workqueue(ha->wq); |
| 443 | ha->wq = NULL; |
| 444 | vha->req = ha->req_q_map[0]; |
| 445 | fail: |
| 446 | ha->mqenable = 0; |
| 447 | kfree(ha->req_q_map); |
| 448 | kfree(ha->rsp_q_map); |
| 449 | ha->max_req_queues = ha->max_rsp_queues = 1; |
| 450 | return 1; |
| 451 | } |
| 452 | |
| 453 | static char * |
| 454 | qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) |
| 455 | { |
| 456 | struct qla_hw_data *ha = vha->hw; |
| 457 | static char *pci_bus_modes[] = { |
| 458 | "33", "66", "100", "133", |
| 459 | }; |
| 460 | uint16_t pci_bus; |
| 461 | |
| 462 | strcpy(str, "PCI"); |
| 463 | pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; |
| 464 | if (pci_bus) { |
| 465 | strcat(str, "-X ("); |
| 466 | strcat(str, pci_bus_modes[pci_bus]); |
| 467 | } else { |
| 468 | pci_bus = (ha->pci_attr & BIT_8) >> 8; |
| 469 | strcat(str, " ("); |
| 470 | strcat(str, pci_bus_modes[pci_bus]); |
| 471 | } |
| 472 | strcat(str, " MHz)"); |
| 473 | |
| 474 | return (str); |
| 475 | } |
| 476 | |
| 477 | static char * |
| 478 | qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) |
| 479 | { |
| 480 | static char *pci_bus_modes[] = { "33", "66", "100", "133", }; |
| 481 | struct qla_hw_data *ha = vha->hw; |
| 482 | uint32_t pci_bus; |
| 483 | int pcie_reg; |
| 484 | |
| 485 | pcie_reg = pci_pcie_cap(ha->pdev); |
| 486 | if (pcie_reg) { |
| 487 | char lwstr[6]; |
| 488 | uint16_t pcie_lstat, lspeed, lwidth; |
| 489 | |
| 490 | pcie_reg += PCI_EXP_LNKCAP; |
| 491 | pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat); |
| 492 | lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); |
| 493 | lwidth = (pcie_lstat & |
| 494 | (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; |
| 495 | |
| 496 | strcpy(str, "PCIe ("); |
| 497 | if (lspeed == 1) |
| 498 | strcat(str, "2.5GT/s "); |
| 499 | else if (lspeed == 2) |
| 500 | strcat(str, "5.0GT/s "); |
| 501 | else |
| 502 | strcat(str, "<unknown> "); |
| 503 | snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); |
| 504 | strcat(str, lwstr); |
| 505 | |
| 506 | return str; |
| 507 | } |
| 508 | |
| 509 | strcpy(str, "PCI"); |
| 510 | pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; |
| 511 | if (pci_bus == 0 || pci_bus == 8) { |
| 512 | strcat(str, " ("); |
| 513 | strcat(str, pci_bus_modes[pci_bus >> 3]); |
| 514 | } else { |
| 515 | strcat(str, "-X "); |
| 516 | if (pci_bus & BIT_2) |
| 517 | strcat(str, "Mode 2"); |
| 518 | else |
| 519 | strcat(str, "Mode 1"); |
| 520 | strcat(str, " ("); |
| 521 | strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); |
| 522 | } |
| 523 | strcat(str, " MHz)"); |
| 524 | |
| 525 | return str; |
| 526 | } |
| 527 | |
| 528 | static char * |
| 529 | qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) |
| 530 | { |
| 531 | char un_str[10]; |
| 532 | struct qla_hw_data *ha = vha->hw; |
| 533 | |
| 534 | sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, |
| 535 | ha->fw_minor_version, |
| 536 | ha->fw_subminor_version); |
| 537 | |
| 538 | if (ha->fw_attributes & BIT_9) { |
| 539 | strcat(str, "FLX"); |
| 540 | return (str); |
| 541 | } |
| 542 | |
| 543 | switch (ha->fw_attributes & 0xFF) { |
| 544 | case 0x7: |
| 545 | strcat(str, "EF"); |
| 546 | break; |
| 547 | case 0x17: |
| 548 | strcat(str, "TP"); |
| 549 | break; |
| 550 | case 0x37: |
| 551 | strcat(str, "IP"); |
| 552 | break; |
| 553 | case 0x77: |
| 554 | strcat(str, "VI"); |
| 555 | break; |
| 556 | default: |
| 557 | sprintf(un_str, "(%x)", ha->fw_attributes); |
| 558 | strcat(str, un_str); |
| 559 | break; |
| 560 | } |
| 561 | if (ha->fw_attributes & 0x100) |
| 562 | strcat(str, "X"); |
| 563 | |
| 564 | return (str); |
| 565 | } |
| 566 | |
| 567 | static char * |
| 568 | qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) |
| 569 | { |
| 570 | struct qla_hw_data *ha = vha->hw; |
| 571 | |
| 572 | sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, |
| 573 | ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); |
| 574 | return str; |
| 575 | } |
| 576 | |
| 577 | void |
| 578 | qla2x00_sp_free_dma(void *vha, void *ptr) |
| 579 | { |
| 580 | srb_t *sp = (srb_t *)ptr; |
| 581 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); |
| 582 | struct qla_hw_data *ha = sp->fcport->vha->hw; |
| 583 | void *ctx = GET_CMD_CTX_SP(sp); |
| 584 | |
| 585 | if (sp->flags & SRB_DMA_VALID) { |
| 586 | scsi_dma_unmap(cmd); |
| 587 | sp->flags &= ~SRB_DMA_VALID; |
| 588 | } |
| 589 | |
| 590 | if (sp->flags & SRB_CRC_PROT_DMA_VALID) { |
| 591 | dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), |
| 592 | scsi_prot_sg_count(cmd), cmd->sc_data_direction); |
| 593 | sp->flags &= ~SRB_CRC_PROT_DMA_VALID; |
| 594 | } |
| 595 | |
| 596 | if (sp->flags & SRB_CRC_CTX_DSD_VALID) { |
| 597 | /* List assured to be having elements */ |
| 598 | qla2x00_clean_dsd_pool(ha, sp); |
| 599 | sp->flags &= ~SRB_CRC_CTX_DSD_VALID; |
| 600 | } |
| 601 | |
| 602 | if (sp->flags & SRB_CRC_CTX_DMA_VALID) { |
| 603 | dma_pool_free(ha->dl_dma_pool, ctx, |
| 604 | ((struct crc_context *)ctx)->crc_ctx_dma); |
| 605 | sp->flags &= ~SRB_CRC_CTX_DMA_VALID; |
| 606 | } |
| 607 | |
| 608 | if (sp->flags & SRB_FCP_CMND_DMA_VALID) { |
| 609 | struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; |
| 610 | |
| 611 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, |
| 612 | ctx1->fcp_cmnd_dma); |
| 613 | list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); |
| 614 | ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; |
| 615 | ha->gbl_dsd_avail += ctx1->dsd_use_cnt; |
| 616 | mempool_free(ctx1, ha->ctx_mempool); |
| 617 | ctx1 = NULL; |
| 618 | } |
| 619 | |
| 620 | CMD_SP(cmd) = NULL; |
| 621 | mempool_free(sp, ha->srb_mempool); |
| 622 | } |
| 623 | |
| 624 | static void |
| 625 | qla2x00_sp_compl(void *data, void *ptr, int res) |
| 626 | { |
| 627 | struct qla_hw_data *ha = (struct qla_hw_data *)data; |
| 628 | srb_t *sp = (srb_t *)ptr; |
| 629 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); |
| 630 | |
| 631 | cmd->result = res; |
| 632 | |
| 633 | if (atomic_read(&sp->ref_count) == 0) { |
| 634 | ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, |
| 635 | "SP reference-count to ZERO -- sp=%p cmd=%p.\n", |
| 636 | sp, GET_CMD_SP(sp)); |
| 637 | if (ql2xextended_error_logging & ql_dbg_io) |
| 638 | BUG(); |
| 639 | return; |
| 640 | } |
| 641 | if (!atomic_dec_and_test(&sp->ref_count)) |
| 642 | return; |
| 643 | |
| 644 | qla2x00_sp_free_dma(ha, sp); |
| 645 | cmd->scsi_done(cmd); |
| 646 | } |
| 647 | |
| 648 | static int |
| 649 | qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) |
| 650 | { |
| 651 | scsi_qla_host_t *vha = shost_priv(host); |
| 652 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
| 653 | struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); |
| 654 | struct qla_hw_data *ha = vha->hw; |
| 655 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 656 | srb_t *sp; |
| 657 | int rval; |
| 658 | |
| 659 | if (ha->flags.eeh_busy) { |
| 660 | if (ha->flags.pci_channel_io_perm_failure) { |
| 661 | ql_dbg(ql_dbg_aer, vha, 0x9010, |
| 662 | "PCI Channel IO permanent failure, exiting " |
| 663 | "cmd=%p.\n", cmd); |
| 664 | cmd->result = DID_NO_CONNECT << 16; |
| 665 | } else { |
| 666 | ql_dbg(ql_dbg_aer, vha, 0x9011, |
| 667 | "EEH_Busy, Requeuing the cmd=%p.\n", cmd); |
| 668 | cmd->result = DID_REQUEUE << 16; |
| 669 | } |
| 670 | goto qc24_fail_command; |
| 671 | } |
| 672 | |
| 673 | rval = fc_remote_port_chkready(rport); |
| 674 | if (rval) { |
| 675 | cmd->result = rval; |
| 676 | ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, |
| 677 | "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", |
| 678 | cmd, rval); |
| 679 | goto qc24_fail_command; |
| 680 | } |
| 681 | |
| 682 | if (!vha->flags.difdix_supported && |
| 683 | scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { |
| 684 | ql_dbg(ql_dbg_io, vha, 0x3004, |
| 685 | "DIF Cap not reg, fail DIF capable cmd's:%p.\n", |
| 686 | cmd); |
| 687 | cmd->result = DID_NO_CONNECT << 16; |
| 688 | goto qc24_fail_command; |
| 689 | } |
| 690 | |
| 691 | if (!fcport) { |
| 692 | cmd->result = DID_NO_CONNECT << 16; |
| 693 | goto qc24_fail_command; |
| 694 | } |
| 695 | |
| 696 | if (atomic_read(&fcport->state) != FCS_ONLINE) { |
| 697 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || |
| 698 | atomic_read(&base_vha->loop_state) == LOOP_DEAD) { |
| 699 | ql_dbg(ql_dbg_io, vha, 0x3005, |
| 700 | "Returning DNC, fcport_state=%d loop_state=%d.\n", |
| 701 | atomic_read(&fcport->state), |
| 702 | atomic_read(&base_vha->loop_state)); |
| 703 | cmd->result = DID_NO_CONNECT << 16; |
| 704 | goto qc24_fail_command; |
| 705 | } |
| 706 | goto qc24_target_busy; |
| 707 | } |
| 708 | |
| 709 | sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC); |
| 710 | if (!sp) |
| 711 | goto qc24_host_busy; |
| 712 | |
| 713 | sp->u.scmd.cmd = cmd; |
| 714 | sp->type = SRB_SCSI_CMD; |
| 715 | atomic_set(&sp->ref_count, 1); |
| 716 | CMD_SP(cmd) = (void *)sp; |
| 717 | sp->free = qla2x00_sp_free_dma; |
| 718 | sp->done = qla2x00_sp_compl; |
| 719 | |
| 720 | rval = ha->isp_ops->start_scsi(sp); |
| 721 | if (rval != QLA_SUCCESS) { |
| 722 | ql_dbg(ql_dbg_io, vha, 0x3013, |
| 723 | "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); |
| 724 | goto qc24_host_busy_free_sp; |
| 725 | } |
| 726 | |
| 727 | return 0; |
| 728 | |
| 729 | qc24_host_busy_free_sp: |
| 730 | qla2x00_sp_free_dma(ha, sp); |
| 731 | |
| 732 | qc24_host_busy: |
| 733 | return SCSI_MLQUEUE_HOST_BUSY; |
| 734 | |
| 735 | qc24_target_busy: |
| 736 | return SCSI_MLQUEUE_TARGET_BUSY; |
| 737 | |
| 738 | qc24_fail_command: |
| 739 | cmd->scsi_done(cmd); |
| 740 | |
| 741 | return 0; |
| 742 | } |
| 743 | |
| 744 | /* |
| 745 | * qla2x00_eh_wait_on_command |
| 746 | * Waits for the command to be returned by the Firmware for some |
| 747 | * max time. |
| 748 | * |
| 749 | * Input: |
| 750 | * cmd = Scsi Command to wait on. |
| 751 | * |
| 752 | * Return: |
| 753 | * Not Found : 0 |
| 754 | * Found : 1 |
| 755 | */ |
| 756 | static int |
| 757 | qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) |
| 758 | { |
| 759 | #define ABORT_POLLING_PERIOD 1000 |
| 760 | #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) |
| 761 | unsigned long wait_iter = ABORT_WAIT_ITER; |
| 762 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
| 763 | struct qla_hw_data *ha = vha->hw; |
| 764 | int ret = QLA_SUCCESS; |
| 765 | |
| 766 | if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { |
| 767 | ql_dbg(ql_dbg_taskm, vha, 0x8005, |
| 768 | "Return:eh_wait.\n"); |
| 769 | return ret; |
| 770 | } |
| 771 | |
| 772 | while (CMD_SP(cmd) && wait_iter--) { |
| 773 | msleep(ABORT_POLLING_PERIOD); |
| 774 | } |
| 775 | if (CMD_SP(cmd)) |
| 776 | ret = QLA_FUNCTION_FAILED; |
| 777 | |
| 778 | return ret; |
| 779 | } |
| 780 | |
| 781 | /* |
| 782 | * qla2x00_wait_for_hba_online |
| 783 | * Wait till the HBA is online after going through |
| 784 | * <= MAX_RETRIES_OF_ISP_ABORT or |
| 785 | * finally HBA is disabled ie marked offline |
| 786 | * |
| 787 | * Input: |
| 788 | * ha - pointer to host adapter structure |
| 789 | * |
| 790 | * Note: |
| 791 | * Does context switching-Release SPIN_LOCK |
| 792 | * (if any) before calling this routine. |
| 793 | * |
| 794 | * Return: |
| 795 | * Success (Adapter is online) : 0 |
| 796 | * Failed (Adapter is offline/disabled) : 1 |
| 797 | */ |
| 798 | int |
| 799 | qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) |
| 800 | { |
| 801 | int return_status; |
| 802 | unsigned long wait_online; |
| 803 | struct qla_hw_data *ha = vha->hw; |
| 804 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
| 805 | |
| 806 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); |
| 807 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || |
| 808 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || |
| 809 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || |
| 810 | ha->dpc_active) && time_before(jiffies, wait_online)) { |
| 811 | |
| 812 | msleep(1000); |
| 813 | } |
| 814 | if (base_vha->flags.online) |
| 815 | return_status = QLA_SUCCESS; |
| 816 | else |
| 817 | return_status = QLA_FUNCTION_FAILED; |
| 818 | |
| 819 | return (return_status); |
| 820 | } |
| 821 | |
| 822 | /* |
| 823 | * qla2x00_wait_for_reset_ready |
| 824 | * Wait till the HBA is online after going through |
| 825 | * <= MAX_RETRIES_OF_ISP_ABORT or |
| 826 | * finally HBA is disabled ie marked offline or flash |
| 827 | * operations are in progress. |
| 828 | * |
| 829 | * Input: |
| 830 | * ha - pointer to host adapter structure |
| 831 | * |
| 832 | * Note: |
| 833 | * Does context switching-Release SPIN_LOCK |
| 834 | * (if any) before calling this routine. |
| 835 | * |
| 836 | * Return: |
| 837 | * Success (Adapter is online/no flash ops) : 0 |
| 838 | * Failed (Adapter is offline/disabled/flash ops in progress) : 1 |
| 839 | */ |
| 840 | static int |
| 841 | qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) |
| 842 | { |
| 843 | int return_status; |
| 844 | unsigned long wait_online; |
| 845 | struct qla_hw_data *ha = vha->hw; |
| 846 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
| 847 | |
| 848 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); |
| 849 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || |
| 850 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || |
| 851 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || |
| 852 | ha->optrom_state != QLA_SWAITING || |
| 853 | ha->dpc_active) && time_before(jiffies, wait_online)) |
| 854 | msleep(1000); |
| 855 | |
| 856 | if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) |
| 857 | return_status = QLA_SUCCESS; |
| 858 | else |
| 859 | return_status = QLA_FUNCTION_FAILED; |
| 860 | |
| 861 | ql_dbg(ql_dbg_taskm, vha, 0x8019, |
| 862 | "%s return status=%d.\n", __func__, return_status); |
| 863 | |
| 864 | return return_status; |
| 865 | } |
| 866 | |
| 867 | int |
| 868 | qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) |
| 869 | { |
| 870 | int return_status; |
| 871 | unsigned long wait_reset; |
| 872 | struct qla_hw_data *ha = vha->hw; |
| 873 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
| 874 | |
| 875 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); |
| 876 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || |
| 877 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || |
| 878 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || |
| 879 | ha->dpc_active) && time_before(jiffies, wait_reset)) { |
| 880 | |
| 881 | msleep(1000); |
| 882 | |
| 883 | if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && |
| 884 | ha->flags.chip_reset_done) |
| 885 | break; |
| 886 | } |
| 887 | if (ha->flags.chip_reset_done) |
| 888 | return_status = QLA_SUCCESS; |
| 889 | else |
| 890 | return_status = QLA_FUNCTION_FAILED; |
| 891 | |
| 892 | return return_status; |
| 893 | } |
| 894 | |
| 895 | static void |
| 896 | sp_get(struct srb *sp) |
| 897 | { |
| 898 | atomic_inc(&sp->ref_count); |
| 899 | } |
| 900 | |
| 901 | /************************************************************************** |
| 902 | * qla2xxx_eh_abort |
| 903 | * |
| 904 | * Description: |
| 905 | * The abort function will abort the specified command. |
| 906 | * |
| 907 | * Input: |
| 908 | * cmd = Linux SCSI command packet to be aborted. |
| 909 | * |
| 910 | * Returns: |
| 911 | * Either SUCCESS or FAILED. |
| 912 | * |
| 913 | * Note: |
| 914 | * Only return FAILED if command not returned by firmware. |
| 915 | **************************************************************************/ |
| 916 | static int |
| 917 | qla2xxx_eh_abort(struct scsi_cmnd *cmd) |
| 918 | { |
| 919 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
| 920 | srb_t *sp; |
| 921 | int ret; |
| 922 | unsigned int id, lun; |
| 923 | unsigned long flags; |
| 924 | int wait = 0; |
| 925 | struct qla_hw_data *ha = vha->hw; |
| 926 | |
| 927 | if (!CMD_SP(cmd)) |
| 928 | return SUCCESS; |
| 929 | |
| 930 | ret = fc_block_scsi_eh(cmd); |
| 931 | if (ret != 0) |
| 932 | return ret; |
| 933 | ret = SUCCESS; |
| 934 | |
| 935 | id = cmd->device->id; |
| 936 | lun = cmd->device->lun; |
| 937 | |
| 938 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 939 | sp = (srb_t *) CMD_SP(cmd); |
| 940 | if (!sp) { |
| 941 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 942 | return SUCCESS; |
| 943 | } |
| 944 | |
| 945 | ql_dbg(ql_dbg_taskm, vha, 0x8002, |
| 946 | "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n", |
| 947 | vha->host_no, id, lun, sp, cmd); |
| 948 | |
| 949 | /* Get a reference to the sp and drop the lock.*/ |
| 950 | sp_get(sp); |
| 951 | |
| 952 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 953 | if (ha->isp_ops->abort_command(sp)) { |
| 954 | ret = FAILED; |
| 955 | ql_dbg(ql_dbg_taskm, vha, 0x8003, |
| 956 | "Abort command mbx failed cmd=%p.\n", cmd); |
| 957 | } else { |
| 958 | ql_dbg(ql_dbg_taskm, vha, 0x8004, |
| 959 | "Abort command mbx success cmd=%p.\n", cmd); |
| 960 | wait = 1; |
| 961 | } |
| 962 | |
| 963 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 964 | sp->done(ha, sp, 0); |
| 965 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 966 | |
| 967 | /* Did the command return during mailbox execution? */ |
| 968 | if (ret == FAILED && !CMD_SP(cmd)) |
| 969 | ret = SUCCESS; |
| 970 | |
| 971 | /* Wait for the command to be returned. */ |
| 972 | if (wait) { |
| 973 | if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { |
| 974 | ql_log(ql_log_warn, vha, 0x8006, |
| 975 | "Abort handler timed out cmd=%p.\n", cmd); |
| 976 | ret = FAILED; |
| 977 | } |
| 978 | } |
| 979 | |
| 980 | ql_log(ql_log_info, vha, 0x801c, |
| 981 | "Abort command issued nexus=%ld:%d:%d -- %d %x.\n", |
| 982 | vha->host_no, id, lun, wait, ret); |
| 983 | |
| 984 | return ret; |
| 985 | } |
| 986 | |
| 987 | int |
| 988 | qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, |
| 989 | unsigned int l, enum nexus_wait_type type) |
| 990 | { |
| 991 | int cnt, match, status; |
| 992 | unsigned long flags; |
| 993 | struct qla_hw_data *ha = vha->hw; |
| 994 | struct req_que *req; |
| 995 | srb_t *sp; |
| 996 | struct scsi_cmnd *cmd; |
| 997 | |
| 998 | status = QLA_SUCCESS; |
| 999 | |
| 1000 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 1001 | req = vha->req; |
| 1002 | for (cnt = 1; status == QLA_SUCCESS && |
| 1003 | cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { |
| 1004 | sp = req->outstanding_cmds[cnt]; |
| 1005 | if (!sp) |
| 1006 | continue; |
| 1007 | if (sp->type != SRB_SCSI_CMD) |
| 1008 | continue; |
| 1009 | if (vha->vp_idx != sp->fcport->vha->vp_idx) |
| 1010 | continue; |
| 1011 | match = 0; |
| 1012 | cmd = GET_CMD_SP(sp); |
| 1013 | switch (type) { |
| 1014 | case WAIT_HOST: |
| 1015 | match = 1; |
| 1016 | break; |
| 1017 | case WAIT_TARGET: |
| 1018 | match = cmd->device->id == t; |
| 1019 | break; |
| 1020 | case WAIT_LUN: |
| 1021 | match = (cmd->device->id == t && |
| 1022 | cmd->device->lun == l); |
| 1023 | break; |
| 1024 | } |
| 1025 | if (!match) |
| 1026 | continue; |
| 1027 | |
| 1028 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 1029 | status = qla2x00_eh_wait_on_command(cmd); |
| 1030 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 1031 | } |
| 1032 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 1033 | |
| 1034 | return status; |
| 1035 | } |
| 1036 | |
| 1037 | static char *reset_errors[] = { |
| 1038 | "HBA not online", |
| 1039 | "HBA not ready", |
| 1040 | "Task management failed", |
| 1041 | "Waiting for command completions", |
| 1042 | }; |
| 1043 | |
| 1044 | static int |
| 1045 | __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, |
| 1046 | struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) |
| 1047 | { |
| 1048 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
| 1049 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
| 1050 | int err; |
| 1051 | |
| 1052 | if (!fcport) { |
| 1053 | return FAILED; |
| 1054 | } |
| 1055 | |
| 1056 | err = fc_block_scsi_eh(cmd); |
| 1057 | if (err != 0) |
| 1058 | return err; |
| 1059 | |
| 1060 | ql_log(ql_log_info, vha, 0x8009, |
| 1061 | "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no, |
| 1062 | cmd->device->id, cmd->device->lun, cmd); |
| 1063 | |
| 1064 | err = 0; |
| 1065 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
| 1066 | ql_log(ql_log_warn, vha, 0x800a, |
| 1067 | "Wait for hba online failed for cmd=%p.\n", cmd); |
| 1068 | goto eh_reset_failed; |
| 1069 | } |
| 1070 | err = 2; |
| 1071 | if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) |
| 1072 | != QLA_SUCCESS) { |
| 1073 | ql_log(ql_log_warn, vha, 0x800c, |
| 1074 | "do_reset failed for cmd=%p.\n", cmd); |
| 1075 | goto eh_reset_failed; |
| 1076 | } |
| 1077 | err = 3; |
| 1078 | if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, |
| 1079 | cmd->device->lun, type) != QLA_SUCCESS) { |
| 1080 | ql_log(ql_log_warn, vha, 0x800d, |
| 1081 | "wait for pending cmds failed for cmd=%p.\n", cmd); |
| 1082 | goto eh_reset_failed; |
| 1083 | } |
| 1084 | |
| 1085 | ql_log(ql_log_info, vha, 0x800e, |
| 1086 | "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name, |
| 1087 | vha->host_no, cmd->device->id, cmd->device->lun, cmd); |
| 1088 | |
| 1089 | return SUCCESS; |
| 1090 | |
| 1091 | eh_reset_failed: |
| 1092 | ql_log(ql_log_info, vha, 0x800f, |
| 1093 | "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name, |
| 1094 | reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, |
| 1095 | cmd); |
| 1096 | return FAILED; |
| 1097 | } |
| 1098 | |
| 1099 | static int |
| 1100 | qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) |
| 1101 | { |
| 1102 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
| 1103 | struct qla_hw_data *ha = vha->hw; |
| 1104 | |
| 1105 | return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, |
| 1106 | ha->isp_ops->lun_reset); |
| 1107 | } |
| 1108 | |
| 1109 | static int |
| 1110 | qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) |
| 1111 | { |
| 1112 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
| 1113 | struct qla_hw_data *ha = vha->hw; |
| 1114 | |
| 1115 | return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, |
| 1116 | ha->isp_ops->target_reset); |
| 1117 | } |
| 1118 | |
| 1119 | /************************************************************************** |
| 1120 | * qla2xxx_eh_bus_reset |
| 1121 | * |
| 1122 | * Description: |
| 1123 | * The bus reset function will reset the bus and abort any executing |
| 1124 | * commands. |
| 1125 | * |
| 1126 | * Input: |
| 1127 | * cmd = Linux SCSI command packet of the command that cause the |
| 1128 | * bus reset. |
| 1129 | * |
| 1130 | * Returns: |
| 1131 | * SUCCESS/FAILURE (defined as macro in scsi.h). |
| 1132 | * |
| 1133 | **************************************************************************/ |
| 1134 | static int |
| 1135 | qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) |
| 1136 | { |
| 1137 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
| 1138 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
| 1139 | int ret = FAILED; |
| 1140 | unsigned int id, lun; |
| 1141 | |
| 1142 | id = cmd->device->id; |
| 1143 | lun = cmd->device->lun; |
| 1144 | |
| 1145 | if (!fcport) { |
| 1146 | return ret; |
| 1147 | } |
| 1148 | |
| 1149 | ret = fc_block_scsi_eh(cmd); |
| 1150 | if (ret != 0) |
| 1151 | return ret; |
| 1152 | ret = FAILED; |
| 1153 | |
| 1154 | ql_log(ql_log_info, vha, 0x8012, |
| 1155 | "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); |
| 1156 | |
| 1157 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
| 1158 | ql_log(ql_log_fatal, vha, 0x8013, |
| 1159 | "Wait for hba online failed board disabled.\n"); |
| 1160 | goto eh_bus_reset_done; |
| 1161 | } |
| 1162 | |
| 1163 | if (qla2x00_loop_reset(vha) == QLA_SUCCESS) |
| 1164 | ret = SUCCESS; |
| 1165 | |
| 1166 | if (ret == FAILED) |
| 1167 | goto eh_bus_reset_done; |
| 1168 | |
| 1169 | /* Flush outstanding commands. */ |
| 1170 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != |
| 1171 | QLA_SUCCESS) { |
| 1172 | ql_log(ql_log_warn, vha, 0x8014, |
| 1173 | "Wait for pending commands failed.\n"); |
| 1174 | ret = FAILED; |
| 1175 | } |
| 1176 | |
| 1177 | eh_bus_reset_done: |
| 1178 | ql_log(ql_log_warn, vha, 0x802b, |
| 1179 | "BUS RESET %s nexus=%ld:%d:%d.\n", |
| 1180 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); |
| 1181 | |
| 1182 | return ret; |
| 1183 | } |
| 1184 | |
| 1185 | /************************************************************************** |
| 1186 | * qla2xxx_eh_host_reset |
| 1187 | * |
| 1188 | * Description: |
| 1189 | * The reset function will reset the Adapter. |
| 1190 | * |
| 1191 | * Input: |
| 1192 | * cmd = Linux SCSI command packet of the command that cause the |
| 1193 | * adapter reset. |
| 1194 | * |
| 1195 | * Returns: |
| 1196 | * Either SUCCESS or FAILED. |
| 1197 | * |
| 1198 | * Note: |
| 1199 | **************************************************************************/ |
| 1200 | static int |
| 1201 | qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) |
| 1202 | { |
| 1203 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
| 1204 | struct qla_hw_data *ha = vha->hw; |
| 1205 | int ret = FAILED; |
| 1206 | unsigned int id, lun; |
| 1207 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
| 1208 | |
| 1209 | id = cmd->device->id; |
| 1210 | lun = cmd->device->lun; |
| 1211 | |
| 1212 | ql_log(ql_log_info, vha, 0x8018, |
| 1213 | "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); |
| 1214 | |
| 1215 | if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) |
| 1216 | goto eh_host_reset_lock; |
| 1217 | |
| 1218 | if (vha != base_vha) { |
| 1219 | if (qla2x00_vp_abort_isp(vha)) |
| 1220 | goto eh_host_reset_lock; |
| 1221 | } else { |
| 1222 | if (IS_QLA82XX(vha->hw)) { |
| 1223 | if (!qla82xx_fcoe_ctx_reset(vha)) { |
| 1224 | /* Ctx reset success */ |
| 1225 | ret = SUCCESS; |
| 1226 | goto eh_host_reset_lock; |
| 1227 | } |
| 1228 | /* fall thru if ctx reset failed */ |
| 1229 | } |
| 1230 | if (ha->wq) |
| 1231 | flush_workqueue(ha->wq); |
| 1232 | |
| 1233 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
| 1234 | if (ha->isp_ops->abort_isp(base_vha)) { |
| 1235 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
| 1236 | /* failed. schedule dpc to try */ |
| 1237 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); |
| 1238 | |
| 1239 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
| 1240 | ql_log(ql_log_warn, vha, 0x802a, |
| 1241 | "wait for hba online failed.\n"); |
| 1242 | goto eh_host_reset_lock; |
| 1243 | } |
| 1244 | } |
| 1245 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
| 1246 | } |
| 1247 | |
| 1248 | /* Waiting for command to be returned to OS.*/ |
| 1249 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == |
| 1250 | QLA_SUCCESS) |
| 1251 | ret = SUCCESS; |
| 1252 | |
| 1253 | eh_host_reset_lock: |
| 1254 | ql_log(ql_log_info, vha, 0x8017, |
| 1255 | "ADAPTER RESET %s nexus=%ld:%d:%d.\n", |
| 1256 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); |
| 1257 | |
| 1258 | return ret; |
| 1259 | } |
| 1260 | |
| 1261 | /* |
| 1262 | * qla2x00_loop_reset |
| 1263 | * Issue loop reset. |
| 1264 | * |
| 1265 | * Input: |
| 1266 | * ha = adapter block pointer. |
| 1267 | * |
| 1268 | * Returns: |
| 1269 | * 0 = success |
| 1270 | */ |
| 1271 | int |
| 1272 | qla2x00_loop_reset(scsi_qla_host_t *vha) |
| 1273 | { |
| 1274 | int ret; |
| 1275 | struct fc_port *fcport; |
| 1276 | struct qla_hw_data *ha = vha->hw; |
| 1277 | |
| 1278 | if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { |
| 1279 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
| 1280 | if (fcport->port_type != FCT_TARGET) |
| 1281 | continue; |
| 1282 | |
| 1283 | ret = ha->isp_ops->target_reset(fcport, 0, 0); |
| 1284 | if (ret != QLA_SUCCESS) { |
| 1285 | ql_dbg(ql_dbg_taskm, vha, 0x802c, |
| 1286 | "Bus Reset failed: Target Reset=%d " |
| 1287 | "d_id=%x.\n", ret, fcport->d_id.b24); |
| 1288 | } |
| 1289 | } |
| 1290 | } |
| 1291 | |
| 1292 | if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { |
| 1293 | ret = qla2x00_full_login_lip(vha); |
| 1294 | if (ret != QLA_SUCCESS) { |
| 1295 | ql_dbg(ql_dbg_taskm, vha, 0x802d, |
| 1296 | "full_login_lip=%d.\n", ret); |
| 1297 | } |
| 1298 | atomic_set(&vha->loop_state, LOOP_DOWN); |
| 1299 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); |
| 1300 | qla2x00_mark_all_devices_lost(vha, 0); |
| 1301 | } |
| 1302 | |
| 1303 | if (ha->flags.enable_lip_reset) { |
| 1304 | ret = qla2x00_lip_reset(vha); |
| 1305 | if (ret != QLA_SUCCESS) |
| 1306 | ql_dbg(ql_dbg_taskm, vha, 0x802e, |
| 1307 | "lip_reset failed (%d).\n", ret); |
| 1308 | } |
| 1309 | |
| 1310 | /* Issue marker command only when we are going to start the I/O */ |
| 1311 | vha->marker_needed = 1; |
| 1312 | |
| 1313 | return QLA_SUCCESS; |
| 1314 | } |
| 1315 | |
| 1316 | void |
| 1317 | qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) |
| 1318 | { |
| 1319 | int que, cnt; |
| 1320 | unsigned long flags; |
| 1321 | srb_t *sp; |
| 1322 | struct qla_hw_data *ha = vha->hw; |
| 1323 | struct req_que *req; |
| 1324 | |
| 1325 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 1326 | for (que = 0; que < ha->max_req_queues; que++) { |
| 1327 | req = ha->req_q_map[que]; |
| 1328 | if (!req) |
| 1329 | continue; |
| 1330 | for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { |
| 1331 | sp = req->outstanding_cmds[cnt]; |
| 1332 | if (sp) { |
| 1333 | req->outstanding_cmds[cnt] = NULL; |
| 1334 | sp->done(vha, sp, res); |
| 1335 | } |
| 1336 | } |
| 1337 | } |
| 1338 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 1339 | } |
| 1340 | |
| 1341 | static int |
| 1342 | qla2xxx_slave_alloc(struct scsi_device *sdev) |
| 1343 | { |
| 1344 | struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); |
| 1345 | |
| 1346 | if (!rport || fc_remote_port_chkready(rport)) |
| 1347 | return -ENXIO; |
| 1348 | |
| 1349 | sdev->hostdata = *(fc_port_t **)rport->dd_data; |
| 1350 | |
| 1351 | return 0; |
| 1352 | } |
| 1353 | |
| 1354 | static int |
| 1355 | qla2xxx_slave_configure(struct scsi_device *sdev) |
| 1356 | { |
| 1357 | scsi_qla_host_t *vha = shost_priv(sdev->host); |
| 1358 | struct req_que *req = vha->req; |
| 1359 | |
| 1360 | if (sdev->tagged_supported) |
| 1361 | scsi_activate_tcq(sdev, req->max_q_depth); |
| 1362 | else |
| 1363 | scsi_deactivate_tcq(sdev, req->max_q_depth); |
| 1364 | return 0; |
| 1365 | } |
| 1366 | |
| 1367 | static void |
| 1368 | qla2xxx_slave_destroy(struct scsi_device *sdev) |
| 1369 | { |
| 1370 | sdev->hostdata = NULL; |
| 1371 | } |
| 1372 | |
| 1373 | static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) |
| 1374 | { |
| 1375 | fc_port_t *fcport = (struct fc_port *) sdev->hostdata; |
| 1376 | |
| 1377 | if (!scsi_track_queue_full(sdev, qdepth)) |
| 1378 | return; |
| 1379 | |
| 1380 | ql_dbg(ql_dbg_io, fcport->vha, 0x3029, |
| 1381 | "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n", |
| 1382 | sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); |
| 1383 | } |
| 1384 | |
| 1385 | static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) |
| 1386 | { |
| 1387 | fc_port_t *fcport = sdev->hostdata; |
| 1388 | struct scsi_qla_host *vha = fcport->vha; |
| 1389 | struct req_que *req = NULL; |
| 1390 | |
| 1391 | req = vha->req; |
| 1392 | if (!req) |
| 1393 | return; |
| 1394 | |
| 1395 | if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) |
| 1396 | return; |
| 1397 | |
| 1398 | if (sdev->ordered_tags) |
| 1399 | scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); |
| 1400 | else |
| 1401 | scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); |
| 1402 | |
| 1403 | ql_dbg(ql_dbg_io, vha, 0x302a, |
| 1404 | "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n", |
| 1405 | sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); |
| 1406 | } |
| 1407 | |
| 1408 | static int |
| 1409 | qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) |
| 1410 | { |
| 1411 | switch (reason) { |
| 1412 | case SCSI_QDEPTH_DEFAULT: |
| 1413 | scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); |
| 1414 | break; |
| 1415 | case SCSI_QDEPTH_QFULL: |
| 1416 | qla2x00_handle_queue_full(sdev, qdepth); |
| 1417 | break; |
| 1418 | case SCSI_QDEPTH_RAMP_UP: |
| 1419 | qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); |
| 1420 | break; |
| 1421 | default: |
| 1422 | return -EOPNOTSUPP; |
| 1423 | } |
| 1424 | |
| 1425 | return sdev->queue_depth; |
| 1426 | } |
| 1427 | |
| 1428 | static int |
| 1429 | qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) |
| 1430 | { |
| 1431 | if (sdev->tagged_supported) { |
| 1432 | scsi_set_tag_type(sdev, tag_type); |
| 1433 | if (tag_type) |
| 1434 | scsi_activate_tcq(sdev, sdev->queue_depth); |
| 1435 | else |
| 1436 | scsi_deactivate_tcq(sdev, sdev->queue_depth); |
| 1437 | } else |
| 1438 | tag_type = 0; |
| 1439 | |
| 1440 | return tag_type; |
| 1441 | } |
| 1442 | |
| 1443 | /** |
| 1444 | * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. |
| 1445 | * @ha: HA context |
| 1446 | * |
| 1447 | * At exit, the @ha's flags.enable_64bit_addressing set to indicated |
| 1448 | * supported addressing method. |
| 1449 | */ |
| 1450 | static void |
| 1451 | qla2x00_config_dma_addressing(struct qla_hw_data *ha) |
| 1452 | { |
| 1453 | /* Assume a 32bit DMA mask. */ |
| 1454 | ha->flags.enable_64bit_addressing = 0; |
| 1455 | |
| 1456 | if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { |
| 1457 | /* Any upper-dword bits set? */ |
| 1458 | if (MSD(dma_get_required_mask(&ha->pdev->dev)) && |
| 1459 | !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { |
| 1460 | /* Ok, a 64bit DMA mask is applicable. */ |
| 1461 | ha->flags.enable_64bit_addressing = 1; |
| 1462 | ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; |
| 1463 | ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; |
| 1464 | return; |
| 1465 | } |
| 1466 | } |
| 1467 | |
| 1468 | dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); |
| 1469 | pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); |
| 1470 | } |
| 1471 | |
| 1472 | static void |
| 1473 | qla2x00_enable_intrs(struct qla_hw_data *ha) |
| 1474 | { |
| 1475 | unsigned long flags = 0; |
| 1476 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 1477 | |
| 1478 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 1479 | ha->interrupts_on = 1; |
| 1480 | /* enable risc and host interrupts */ |
| 1481 | WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); |
| 1482 | RD_REG_WORD(®->ictrl); |
| 1483 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 1484 | |
| 1485 | } |
| 1486 | |
| 1487 | static void |
| 1488 | qla2x00_disable_intrs(struct qla_hw_data *ha) |
| 1489 | { |
| 1490 | unsigned long flags = 0; |
| 1491 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 1492 | |
| 1493 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 1494 | ha->interrupts_on = 0; |
| 1495 | /* disable risc and host interrupts */ |
| 1496 | WRT_REG_WORD(®->ictrl, 0); |
| 1497 | RD_REG_WORD(®->ictrl); |
| 1498 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 1499 | } |
| 1500 | |
| 1501 | static void |
| 1502 | qla24xx_enable_intrs(struct qla_hw_data *ha) |
| 1503 | { |
| 1504 | unsigned long flags = 0; |
| 1505 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 1506 | |
| 1507 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 1508 | ha->interrupts_on = 1; |
| 1509 | WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); |
| 1510 | RD_REG_DWORD(®->ictrl); |
| 1511 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 1512 | } |
| 1513 | |
| 1514 | static void |
| 1515 | qla24xx_disable_intrs(struct qla_hw_data *ha) |
| 1516 | { |
| 1517 | unsigned long flags = 0; |
| 1518 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 1519 | |
| 1520 | if (IS_NOPOLLING_TYPE(ha)) |
| 1521 | return; |
| 1522 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 1523 | ha->interrupts_on = 0; |
| 1524 | WRT_REG_DWORD(®->ictrl, 0); |
| 1525 | RD_REG_DWORD(®->ictrl); |
| 1526 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 1527 | } |
| 1528 | |
| 1529 | static int |
| 1530 | qla2x00_iospace_config(struct qla_hw_data *ha) |
| 1531 | { |
| 1532 | resource_size_t pio; |
| 1533 | uint16_t msix; |
| 1534 | int cpus; |
| 1535 | |
| 1536 | if (pci_request_selected_regions(ha->pdev, ha->bars, |
| 1537 | QLA2XXX_DRIVER_NAME)) { |
| 1538 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, |
| 1539 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", |
| 1540 | pci_name(ha->pdev)); |
| 1541 | goto iospace_error_exit; |
| 1542 | } |
| 1543 | if (!(ha->bars & 1)) |
| 1544 | goto skip_pio; |
| 1545 | |
| 1546 | /* We only need PIO for Flash operations on ISP2312 v2 chips. */ |
| 1547 | pio = pci_resource_start(ha->pdev, 0); |
| 1548 | if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { |
| 1549 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { |
| 1550 | ql_log_pci(ql_log_warn, ha->pdev, 0x0012, |
| 1551 | "Invalid pci I/O region size (%s).\n", |
| 1552 | pci_name(ha->pdev)); |
| 1553 | pio = 0; |
| 1554 | } |
| 1555 | } else { |
| 1556 | ql_log_pci(ql_log_warn, ha->pdev, 0x0013, |
| 1557 | "Region #0 no a PIO resource (%s).\n", |
| 1558 | pci_name(ha->pdev)); |
| 1559 | pio = 0; |
| 1560 | } |
| 1561 | ha->pio_address = pio; |
| 1562 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, |
| 1563 | "PIO address=%llu.\n", |
| 1564 | (unsigned long long)ha->pio_address); |
| 1565 | |
| 1566 | skip_pio: |
| 1567 | /* Use MMIO operations for all accesses. */ |
| 1568 | if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { |
| 1569 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, |
| 1570 | "Region #1 not an MMIO resource (%s), aborting.\n", |
| 1571 | pci_name(ha->pdev)); |
| 1572 | goto iospace_error_exit; |
| 1573 | } |
| 1574 | if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { |
| 1575 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, |
| 1576 | "Invalid PCI mem region size (%s), aborting.\n", |
| 1577 | pci_name(ha->pdev)); |
| 1578 | goto iospace_error_exit; |
| 1579 | } |
| 1580 | |
| 1581 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); |
| 1582 | if (!ha->iobase) { |
| 1583 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, |
| 1584 | "Cannot remap MMIO (%s), aborting.\n", |
| 1585 | pci_name(ha->pdev)); |
| 1586 | goto iospace_error_exit; |
| 1587 | } |
| 1588 | |
| 1589 | /* Determine queue resources */ |
| 1590 | ha->max_req_queues = ha->max_rsp_queues = 1; |
| 1591 | if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || |
| 1592 | (ql2xmaxqueues > 1 && ql2xmultique_tag) || |
| 1593 | (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) |
| 1594 | goto mqiobase_exit; |
| 1595 | |
| 1596 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), |
| 1597 | pci_resource_len(ha->pdev, 3)); |
| 1598 | if (ha->mqiobase) { |
| 1599 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, |
| 1600 | "MQIO Base=%p.\n", ha->mqiobase); |
| 1601 | /* Read MSIX vector size of the board */ |
| 1602 | pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); |
| 1603 | ha->msix_count = msix; |
| 1604 | /* Max queues are bounded by available msix vectors */ |
| 1605 | /* queue 0 uses two msix vectors */ |
| 1606 | if (ql2xmultique_tag) { |
| 1607 | cpus = num_online_cpus(); |
| 1608 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? |
| 1609 | (cpus + 1) : (ha->msix_count - 1); |
| 1610 | ha->max_req_queues = 2; |
| 1611 | } else if (ql2xmaxqueues > 1) { |
| 1612 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? |
| 1613 | QLA_MQ_SIZE : ql2xmaxqueues; |
| 1614 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, |
| 1615 | "QoS mode set, max no of request queues:%d.\n", |
| 1616 | ha->max_req_queues); |
| 1617 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, |
| 1618 | "QoS mode set, max no of request queues:%d.\n", |
| 1619 | ha->max_req_queues); |
| 1620 | } |
| 1621 | ql_log_pci(ql_log_info, ha->pdev, 0x001a, |
| 1622 | "MSI-X vector count: %d.\n", msix); |
| 1623 | } else |
| 1624 | ql_log_pci(ql_log_info, ha->pdev, 0x001b, |
| 1625 | "BAR 3 not enabled.\n"); |
| 1626 | |
| 1627 | mqiobase_exit: |
| 1628 | ha->msix_count = ha->max_rsp_queues + 1; |
| 1629 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, |
| 1630 | "MSIX Count:%d.\n", ha->msix_count); |
| 1631 | return (0); |
| 1632 | |
| 1633 | iospace_error_exit: |
| 1634 | return (-ENOMEM); |
| 1635 | } |
| 1636 | |
| 1637 | |
| 1638 | static int |
| 1639 | qla83xx_iospace_config(struct qla_hw_data *ha) |
| 1640 | { |
| 1641 | uint16_t msix; |
| 1642 | int cpus; |
| 1643 | |
| 1644 | if (pci_request_selected_regions(ha->pdev, ha->bars, |
| 1645 | QLA2XXX_DRIVER_NAME)) { |
| 1646 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, |
| 1647 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", |
| 1648 | pci_name(ha->pdev)); |
| 1649 | |
| 1650 | goto iospace_error_exit; |
| 1651 | } |
| 1652 | |
| 1653 | /* Use MMIO operations for all accesses. */ |
| 1654 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { |
| 1655 | ql_log_pci(ql_log_warn, ha->pdev, 0x0118, |
| 1656 | "Invalid pci I/O region size (%s).\n", |
| 1657 | pci_name(ha->pdev)); |
| 1658 | goto iospace_error_exit; |
| 1659 | } |
| 1660 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { |
| 1661 | ql_log_pci(ql_log_warn, ha->pdev, 0x0119, |
| 1662 | "Invalid PCI mem region size (%s), aborting\n", |
| 1663 | pci_name(ha->pdev)); |
| 1664 | goto iospace_error_exit; |
| 1665 | } |
| 1666 | |
| 1667 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); |
| 1668 | if (!ha->iobase) { |
| 1669 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, |
| 1670 | "Cannot remap MMIO (%s), aborting.\n", |
| 1671 | pci_name(ha->pdev)); |
| 1672 | goto iospace_error_exit; |
| 1673 | } |
| 1674 | |
| 1675 | /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ |
| 1676 | /* 83XX 26XX always use MQ type access for queues |
| 1677 | * - mbar 2, a.k.a region 4 */ |
| 1678 | ha->max_req_queues = ha->max_rsp_queues = 1; |
| 1679 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), |
| 1680 | pci_resource_len(ha->pdev, 4)); |
| 1681 | |
| 1682 | if (!ha->mqiobase) { |
| 1683 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, |
| 1684 | "BAR2/region4 not enabled\n"); |
| 1685 | goto mqiobase_exit; |
| 1686 | } |
| 1687 | |
| 1688 | ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), |
| 1689 | pci_resource_len(ha->pdev, 2)); |
| 1690 | if (ha->msixbase) { |
| 1691 | /* Read MSIX vector size of the board */ |
| 1692 | pci_read_config_word(ha->pdev, |
| 1693 | QLA_83XX_PCI_MSIX_CONTROL, &msix); |
| 1694 | ha->msix_count = msix; |
| 1695 | /* Max queues are bounded by available msix vectors */ |
| 1696 | /* queue 0 uses two msix vectors */ |
| 1697 | if (ql2xmultique_tag) { |
| 1698 | cpus = num_online_cpus(); |
| 1699 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? |
| 1700 | (cpus + 1) : (ha->msix_count - 1); |
| 1701 | ha->max_req_queues = 2; |
| 1702 | } else if (ql2xmaxqueues > 1) { |
| 1703 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? |
| 1704 | QLA_MQ_SIZE : ql2xmaxqueues; |
| 1705 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, |
| 1706 | "QoS mode set, max no of request queues:%d.\n", |
| 1707 | ha->max_req_queues); |
| 1708 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, |
| 1709 | "QoS mode set, max no of request queues:%d.\n", |
| 1710 | ha->max_req_queues); |
| 1711 | } |
| 1712 | ql_log_pci(ql_log_info, ha->pdev, 0x011c, |
| 1713 | "MSI-X vector count: %d.\n", msix); |
| 1714 | } else |
| 1715 | ql_log_pci(ql_log_info, ha->pdev, 0x011e, |
| 1716 | "BAR 1 not enabled.\n"); |
| 1717 | |
| 1718 | mqiobase_exit: |
| 1719 | ha->msix_count = ha->max_rsp_queues + 1; |
| 1720 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, |
| 1721 | "MSIX Count:%d.\n", ha->msix_count); |
| 1722 | return 0; |
| 1723 | |
| 1724 | iospace_error_exit: |
| 1725 | return -ENOMEM; |
| 1726 | } |
| 1727 | |
| 1728 | static struct isp_operations qla2100_isp_ops = { |
| 1729 | .pci_config = qla2100_pci_config, |
| 1730 | .reset_chip = qla2x00_reset_chip, |
| 1731 | .chip_diag = qla2x00_chip_diag, |
| 1732 | .config_rings = qla2x00_config_rings, |
| 1733 | .reset_adapter = qla2x00_reset_adapter, |
| 1734 | .nvram_config = qla2x00_nvram_config, |
| 1735 | .update_fw_options = qla2x00_update_fw_options, |
| 1736 | .load_risc = qla2x00_load_risc, |
| 1737 | .pci_info_str = qla2x00_pci_info_str, |
| 1738 | .fw_version_str = qla2x00_fw_version_str, |
| 1739 | .intr_handler = qla2100_intr_handler, |
| 1740 | .enable_intrs = qla2x00_enable_intrs, |
| 1741 | .disable_intrs = qla2x00_disable_intrs, |
| 1742 | .abort_command = qla2x00_abort_command, |
| 1743 | .target_reset = qla2x00_abort_target, |
| 1744 | .lun_reset = qla2x00_lun_reset, |
| 1745 | .fabric_login = qla2x00_login_fabric, |
| 1746 | .fabric_logout = qla2x00_fabric_logout, |
| 1747 | .calc_req_entries = qla2x00_calc_iocbs_32, |
| 1748 | .build_iocbs = qla2x00_build_scsi_iocbs_32, |
| 1749 | .prep_ms_iocb = qla2x00_prep_ms_iocb, |
| 1750 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, |
| 1751 | .read_nvram = qla2x00_read_nvram_data, |
| 1752 | .write_nvram = qla2x00_write_nvram_data, |
| 1753 | .fw_dump = qla2100_fw_dump, |
| 1754 | .beacon_on = NULL, |
| 1755 | .beacon_off = NULL, |
| 1756 | .beacon_blink = NULL, |
| 1757 | .read_optrom = qla2x00_read_optrom_data, |
| 1758 | .write_optrom = qla2x00_write_optrom_data, |
| 1759 | .get_flash_version = qla2x00_get_flash_version, |
| 1760 | .start_scsi = qla2x00_start_scsi, |
| 1761 | .abort_isp = qla2x00_abort_isp, |
| 1762 | .iospace_config = qla2x00_iospace_config, |
| 1763 | }; |
| 1764 | |
| 1765 | static struct isp_operations qla2300_isp_ops = { |
| 1766 | .pci_config = qla2300_pci_config, |
| 1767 | .reset_chip = qla2x00_reset_chip, |
| 1768 | .chip_diag = qla2x00_chip_diag, |
| 1769 | .config_rings = qla2x00_config_rings, |
| 1770 | .reset_adapter = qla2x00_reset_adapter, |
| 1771 | .nvram_config = qla2x00_nvram_config, |
| 1772 | .update_fw_options = qla2x00_update_fw_options, |
| 1773 | .load_risc = qla2x00_load_risc, |
| 1774 | .pci_info_str = qla2x00_pci_info_str, |
| 1775 | .fw_version_str = qla2x00_fw_version_str, |
| 1776 | .intr_handler = qla2300_intr_handler, |
| 1777 | .enable_intrs = qla2x00_enable_intrs, |
| 1778 | .disable_intrs = qla2x00_disable_intrs, |
| 1779 | .abort_command = qla2x00_abort_command, |
| 1780 | .target_reset = qla2x00_abort_target, |
| 1781 | .lun_reset = qla2x00_lun_reset, |
| 1782 | .fabric_login = qla2x00_login_fabric, |
| 1783 | .fabric_logout = qla2x00_fabric_logout, |
| 1784 | .calc_req_entries = qla2x00_calc_iocbs_32, |
| 1785 | .build_iocbs = qla2x00_build_scsi_iocbs_32, |
| 1786 | .prep_ms_iocb = qla2x00_prep_ms_iocb, |
| 1787 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, |
| 1788 | .read_nvram = qla2x00_read_nvram_data, |
| 1789 | .write_nvram = qla2x00_write_nvram_data, |
| 1790 | .fw_dump = qla2300_fw_dump, |
| 1791 | .beacon_on = qla2x00_beacon_on, |
| 1792 | .beacon_off = qla2x00_beacon_off, |
| 1793 | .beacon_blink = qla2x00_beacon_blink, |
| 1794 | .read_optrom = qla2x00_read_optrom_data, |
| 1795 | .write_optrom = qla2x00_write_optrom_data, |
| 1796 | .get_flash_version = qla2x00_get_flash_version, |
| 1797 | .start_scsi = qla2x00_start_scsi, |
| 1798 | .abort_isp = qla2x00_abort_isp, |
| 1799 | .iospace_config = qla2x00_iospace_config, |
| 1800 | }; |
| 1801 | |
| 1802 | static struct isp_operations qla24xx_isp_ops = { |
| 1803 | .pci_config = qla24xx_pci_config, |
| 1804 | .reset_chip = qla24xx_reset_chip, |
| 1805 | .chip_diag = qla24xx_chip_diag, |
| 1806 | .config_rings = qla24xx_config_rings, |
| 1807 | .reset_adapter = qla24xx_reset_adapter, |
| 1808 | .nvram_config = qla24xx_nvram_config, |
| 1809 | .update_fw_options = qla24xx_update_fw_options, |
| 1810 | .load_risc = qla24xx_load_risc, |
| 1811 | .pci_info_str = qla24xx_pci_info_str, |
| 1812 | .fw_version_str = qla24xx_fw_version_str, |
| 1813 | .intr_handler = qla24xx_intr_handler, |
| 1814 | .enable_intrs = qla24xx_enable_intrs, |
| 1815 | .disable_intrs = qla24xx_disable_intrs, |
| 1816 | .abort_command = qla24xx_abort_command, |
| 1817 | .target_reset = qla24xx_abort_target, |
| 1818 | .lun_reset = qla24xx_lun_reset, |
| 1819 | .fabric_login = qla24xx_login_fabric, |
| 1820 | .fabric_logout = qla24xx_fabric_logout, |
| 1821 | .calc_req_entries = NULL, |
| 1822 | .build_iocbs = NULL, |
| 1823 | .prep_ms_iocb = qla24xx_prep_ms_iocb, |
| 1824 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, |
| 1825 | .read_nvram = qla24xx_read_nvram_data, |
| 1826 | .write_nvram = qla24xx_write_nvram_data, |
| 1827 | .fw_dump = qla24xx_fw_dump, |
| 1828 | .beacon_on = qla24xx_beacon_on, |
| 1829 | .beacon_off = qla24xx_beacon_off, |
| 1830 | .beacon_blink = qla24xx_beacon_blink, |
| 1831 | .read_optrom = qla24xx_read_optrom_data, |
| 1832 | .write_optrom = qla24xx_write_optrom_data, |
| 1833 | .get_flash_version = qla24xx_get_flash_version, |
| 1834 | .start_scsi = qla24xx_start_scsi, |
| 1835 | .abort_isp = qla2x00_abort_isp, |
| 1836 | .iospace_config = qla2x00_iospace_config, |
| 1837 | }; |
| 1838 | |
| 1839 | static struct isp_operations qla25xx_isp_ops = { |
| 1840 | .pci_config = qla25xx_pci_config, |
| 1841 | .reset_chip = qla24xx_reset_chip, |
| 1842 | .chip_diag = qla24xx_chip_diag, |
| 1843 | .config_rings = qla24xx_config_rings, |
| 1844 | .reset_adapter = qla24xx_reset_adapter, |
| 1845 | .nvram_config = qla24xx_nvram_config, |
| 1846 | .update_fw_options = qla24xx_update_fw_options, |
| 1847 | .load_risc = qla24xx_load_risc, |
| 1848 | .pci_info_str = qla24xx_pci_info_str, |
| 1849 | .fw_version_str = qla24xx_fw_version_str, |
| 1850 | .intr_handler = qla24xx_intr_handler, |
| 1851 | .enable_intrs = qla24xx_enable_intrs, |
| 1852 | .disable_intrs = qla24xx_disable_intrs, |
| 1853 | .abort_command = qla24xx_abort_command, |
| 1854 | .target_reset = qla24xx_abort_target, |
| 1855 | .lun_reset = qla24xx_lun_reset, |
| 1856 | .fabric_login = qla24xx_login_fabric, |
| 1857 | .fabric_logout = qla24xx_fabric_logout, |
| 1858 | .calc_req_entries = NULL, |
| 1859 | .build_iocbs = NULL, |
| 1860 | .prep_ms_iocb = qla24xx_prep_ms_iocb, |
| 1861 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, |
| 1862 | .read_nvram = qla25xx_read_nvram_data, |
| 1863 | .write_nvram = qla25xx_write_nvram_data, |
| 1864 | .fw_dump = qla25xx_fw_dump, |
| 1865 | .beacon_on = qla24xx_beacon_on, |
| 1866 | .beacon_off = qla24xx_beacon_off, |
| 1867 | .beacon_blink = qla24xx_beacon_blink, |
| 1868 | .read_optrom = qla25xx_read_optrom_data, |
| 1869 | .write_optrom = qla24xx_write_optrom_data, |
| 1870 | .get_flash_version = qla24xx_get_flash_version, |
| 1871 | .start_scsi = qla24xx_dif_start_scsi, |
| 1872 | .abort_isp = qla2x00_abort_isp, |
| 1873 | .iospace_config = qla2x00_iospace_config, |
| 1874 | }; |
| 1875 | |
| 1876 | static struct isp_operations qla81xx_isp_ops = { |
| 1877 | .pci_config = qla25xx_pci_config, |
| 1878 | .reset_chip = qla24xx_reset_chip, |
| 1879 | .chip_diag = qla24xx_chip_diag, |
| 1880 | .config_rings = qla24xx_config_rings, |
| 1881 | .reset_adapter = qla24xx_reset_adapter, |
| 1882 | .nvram_config = qla81xx_nvram_config, |
| 1883 | .update_fw_options = qla81xx_update_fw_options, |
| 1884 | .load_risc = qla81xx_load_risc, |
| 1885 | .pci_info_str = qla24xx_pci_info_str, |
| 1886 | .fw_version_str = qla24xx_fw_version_str, |
| 1887 | .intr_handler = qla24xx_intr_handler, |
| 1888 | .enable_intrs = qla24xx_enable_intrs, |
| 1889 | .disable_intrs = qla24xx_disable_intrs, |
| 1890 | .abort_command = qla24xx_abort_command, |
| 1891 | .target_reset = qla24xx_abort_target, |
| 1892 | .lun_reset = qla24xx_lun_reset, |
| 1893 | .fabric_login = qla24xx_login_fabric, |
| 1894 | .fabric_logout = qla24xx_fabric_logout, |
| 1895 | .calc_req_entries = NULL, |
| 1896 | .build_iocbs = NULL, |
| 1897 | .prep_ms_iocb = qla24xx_prep_ms_iocb, |
| 1898 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, |
| 1899 | .read_nvram = NULL, |
| 1900 | .write_nvram = NULL, |
| 1901 | .fw_dump = qla81xx_fw_dump, |
| 1902 | .beacon_on = qla24xx_beacon_on, |
| 1903 | .beacon_off = qla24xx_beacon_off, |
| 1904 | .beacon_blink = qla83xx_beacon_blink, |
| 1905 | .read_optrom = qla25xx_read_optrom_data, |
| 1906 | .write_optrom = qla24xx_write_optrom_data, |
| 1907 | .get_flash_version = qla24xx_get_flash_version, |
| 1908 | .start_scsi = qla24xx_dif_start_scsi, |
| 1909 | .abort_isp = qla2x00_abort_isp, |
| 1910 | .iospace_config = qla2x00_iospace_config, |
| 1911 | }; |
| 1912 | |
| 1913 | static struct isp_operations qla82xx_isp_ops = { |
| 1914 | .pci_config = qla82xx_pci_config, |
| 1915 | .reset_chip = qla82xx_reset_chip, |
| 1916 | .chip_diag = qla24xx_chip_diag, |
| 1917 | .config_rings = qla82xx_config_rings, |
| 1918 | .reset_adapter = qla24xx_reset_adapter, |
| 1919 | .nvram_config = qla81xx_nvram_config, |
| 1920 | .update_fw_options = qla24xx_update_fw_options, |
| 1921 | .load_risc = qla82xx_load_risc, |
| 1922 | .pci_info_str = qla24xx_pci_info_str, |
| 1923 | .fw_version_str = qla24xx_fw_version_str, |
| 1924 | .intr_handler = qla82xx_intr_handler, |
| 1925 | .enable_intrs = qla82xx_enable_intrs, |
| 1926 | .disable_intrs = qla82xx_disable_intrs, |
| 1927 | .abort_command = qla24xx_abort_command, |
| 1928 | .target_reset = qla24xx_abort_target, |
| 1929 | .lun_reset = qla24xx_lun_reset, |
| 1930 | .fabric_login = qla24xx_login_fabric, |
| 1931 | .fabric_logout = qla24xx_fabric_logout, |
| 1932 | .calc_req_entries = NULL, |
| 1933 | .build_iocbs = NULL, |
| 1934 | .prep_ms_iocb = qla24xx_prep_ms_iocb, |
| 1935 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, |
| 1936 | .read_nvram = qla24xx_read_nvram_data, |
| 1937 | .write_nvram = qla24xx_write_nvram_data, |
| 1938 | .fw_dump = qla24xx_fw_dump, |
| 1939 | .beacon_on = qla82xx_beacon_on, |
| 1940 | .beacon_off = qla82xx_beacon_off, |
| 1941 | .beacon_blink = NULL, |
| 1942 | .read_optrom = qla82xx_read_optrom_data, |
| 1943 | .write_optrom = qla82xx_write_optrom_data, |
| 1944 | .get_flash_version = qla24xx_get_flash_version, |
| 1945 | .start_scsi = qla82xx_start_scsi, |
| 1946 | .abort_isp = qla82xx_abort_isp, |
| 1947 | .iospace_config = qla82xx_iospace_config, |
| 1948 | }; |
| 1949 | |
| 1950 | static struct isp_operations qla83xx_isp_ops = { |
| 1951 | .pci_config = qla25xx_pci_config, |
| 1952 | .reset_chip = qla24xx_reset_chip, |
| 1953 | .chip_diag = qla24xx_chip_diag, |
| 1954 | .config_rings = qla24xx_config_rings, |
| 1955 | .reset_adapter = qla24xx_reset_adapter, |
| 1956 | .nvram_config = qla81xx_nvram_config, |
| 1957 | .update_fw_options = qla81xx_update_fw_options, |
| 1958 | .load_risc = qla81xx_load_risc, |
| 1959 | .pci_info_str = qla24xx_pci_info_str, |
| 1960 | .fw_version_str = qla24xx_fw_version_str, |
| 1961 | .intr_handler = qla24xx_intr_handler, |
| 1962 | .enable_intrs = qla24xx_enable_intrs, |
| 1963 | .disable_intrs = qla24xx_disable_intrs, |
| 1964 | .abort_command = qla24xx_abort_command, |
| 1965 | .target_reset = qla24xx_abort_target, |
| 1966 | .lun_reset = qla24xx_lun_reset, |
| 1967 | .fabric_login = qla24xx_login_fabric, |
| 1968 | .fabric_logout = qla24xx_fabric_logout, |
| 1969 | .calc_req_entries = NULL, |
| 1970 | .build_iocbs = NULL, |
| 1971 | .prep_ms_iocb = qla24xx_prep_ms_iocb, |
| 1972 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, |
| 1973 | .read_nvram = NULL, |
| 1974 | .write_nvram = NULL, |
| 1975 | .fw_dump = qla83xx_fw_dump, |
| 1976 | .beacon_on = qla24xx_beacon_on, |
| 1977 | .beacon_off = qla24xx_beacon_off, |
| 1978 | .beacon_blink = qla83xx_beacon_blink, |
| 1979 | .read_optrom = qla25xx_read_optrom_data, |
| 1980 | .write_optrom = qla24xx_write_optrom_data, |
| 1981 | .get_flash_version = qla24xx_get_flash_version, |
| 1982 | .start_scsi = qla24xx_dif_start_scsi, |
| 1983 | .abort_isp = qla2x00_abort_isp, |
| 1984 | .iospace_config = qla83xx_iospace_config, |
| 1985 | }; |
| 1986 | |
| 1987 | static inline void |
| 1988 | qla2x00_set_isp_flags(struct qla_hw_data *ha) |
| 1989 | { |
| 1990 | ha->device_type = DT_EXTENDED_IDS; |
| 1991 | switch (ha->pdev->device) { |
| 1992 | case PCI_DEVICE_ID_QLOGIC_ISP2100: |
| 1993 | ha->device_type |= DT_ISP2100; |
| 1994 | ha->device_type &= ~DT_EXTENDED_IDS; |
| 1995 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
| 1996 | break; |
| 1997 | case PCI_DEVICE_ID_QLOGIC_ISP2200: |
| 1998 | ha->device_type |= DT_ISP2200; |
| 1999 | ha->device_type &= ~DT_EXTENDED_IDS; |
| 2000 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
| 2001 | break; |
| 2002 | case PCI_DEVICE_ID_QLOGIC_ISP2300: |
| 2003 | ha->device_type |= DT_ISP2300; |
| 2004 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2005 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
| 2006 | break; |
| 2007 | case PCI_DEVICE_ID_QLOGIC_ISP2312: |
| 2008 | ha->device_type |= DT_ISP2312; |
| 2009 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2010 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
| 2011 | break; |
| 2012 | case PCI_DEVICE_ID_QLOGIC_ISP2322: |
| 2013 | ha->device_type |= DT_ISP2322; |
| 2014 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2015 | if (ha->pdev->subsystem_vendor == 0x1028 && |
| 2016 | ha->pdev->subsystem_device == 0x0170) |
| 2017 | ha->device_type |= DT_OEM_001; |
| 2018 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
| 2019 | break; |
| 2020 | case PCI_DEVICE_ID_QLOGIC_ISP6312: |
| 2021 | ha->device_type |= DT_ISP6312; |
| 2022 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
| 2023 | break; |
| 2024 | case PCI_DEVICE_ID_QLOGIC_ISP6322: |
| 2025 | ha->device_type |= DT_ISP6322; |
| 2026 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
| 2027 | break; |
| 2028 | case PCI_DEVICE_ID_QLOGIC_ISP2422: |
| 2029 | ha->device_type |= DT_ISP2422; |
| 2030 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2031 | ha->device_type |= DT_FWI2; |
| 2032 | ha->device_type |= DT_IIDMA; |
| 2033 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2034 | break; |
| 2035 | case PCI_DEVICE_ID_QLOGIC_ISP2432: |
| 2036 | ha->device_type |= DT_ISP2432; |
| 2037 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2038 | ha->device_type |= DT_FWI2; |
| 2039 | ha->device_type |= DT_IIDMA; |
| 2040 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2041 | break; |
| 2042 | case PCI_DEVICE_ID_QLOGIC_ISP8432: |
| 2043 | ha->device_type |= DT_ISP8432; |
| 2044 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2045 | ha->device_type |= DT_FWI2; |
| 2046 | ha->device_type |= DT_IIDMA; |
| 2047 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2048 | break; |
| 2049 | case PCI_DEVICE_ID_QLOGIC_ISP5422: |
| 2050 | ha->device_type |= DT_ISP5422; |
| 2051 | ha->device_type |= DT_FWI2; |
| 2052 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2053 | break; |
| 2054 | case PCI_DEVICE_ID_QLOGIC_ISP5432: |
| 2055 | ha->device_type |= DT_ISP5432; |
| 2056 | ha->device_type |= DT_FWI2; |
| 2057 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2058 | break; |
| 2059 | case PCI_DEVICE_ID_QLOGIC_ISP2532: |
| 2060 | ha->device_type |= DT_ISP2532; |
| 2061 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2062 | ha->device_type |= DT_FWI2; |
| 2063 | ha->device_type |= DT_IIDMA; |
| 2064 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2065 | break; |
| 2066 | case PCI_DEVICE_ID_QLOGIC_ISP8001: |
| 2067 | ha->device_type |= DT_ISP8001; |
| 2068 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2069 | ha->device_type |= DT_FWI2; |
| 2070 | ha->device_type |= DT_IIDMA; |
| 2071 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2072 | break; |
| 2073 | case PCI_DEVICE_ID_QLOGIC_ISP8021: |
| 2074 | ha->device_type |= DT_ISP8021; |
| 2075 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2076 | ha->device_type |= DT_FWI2; |
| 2077 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2078 | /* Initialize 82XX ISP flags */ |
| 2079 | qla82xx_init_flags(ha); |
| 2080 | break; |
| 2081 | case PCI_DEVICE_ID_QLOGIC_ISP2031: |
| 2082 | ha->device_type |= DT_ISP2031; |
| 2083 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2084 | ha->device_type |= DT_FWI2; |
| 2085 | ha->device_type |= DT_IIDMA; |
| 2086 | ha->device_type |= DT_T10_PI; |
| 2087 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2088 | break; |
| 2089 | case PCI_DEVICE_ID_QLOGIC_ISP8031: |
| 2090 | ha->device_type |= DT_ISP8031; |
| 2091 | ha->device_type |= DT_ZIO_SUPPORTED; |
| 2092 | ha->device_type |= DT_FWI2; |
| 2093 | ha->device_type |= DT_IIDMA; |
| 2094 | ha->device_type |= DT_T10_PI; |
| 2095 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
| 2096 | break; |
| 2097 | } |
| 2098 | |
| 2099 | if (IS_QLA82XX(ha)) |
| 2100 | ha->port_no = !(ha->portnum & 1); |
| 2101 | else |
| 2102 | /* Get adapter physical port no from interrupt pin register. */ |
| 2103 | pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); |
| 2104 | |
| 2105 | if (ha->port_no & 1) |
| 2106 | ha->flags.port0 = 1; |
| 2107 | else |
| 2108 | ha->flags.port0 = 0; |
| 2109 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, |
| 2110 | "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", |
| 2111 | ha->device_type, ha->flags.port0, ha->fw_srisc_address); |
| 2112 | } |
| 2113 | |
| 2114 | static void |
| 2115 | qla2xxx_scan_start(struct Scsi_Host *shost) |
| 2116 | { |
| 2117 | scsi_qla_host_t *vha = shost_priv(shost); |
| 2118 | |
| 2119 | if (vha->hw->flags.running_gold_fw) |
| 2120 | return; |
| 2121 | |
| 2122 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
| 2123 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); |
| 2124 | set_bit(RSCN_UPDATE, &vha->dpc_flags); |
| 2125 | set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); |
| 2126 | } |
| 2127 | |
| 2128 | static int |
| 2129 | qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) |
| 2130 | { |
| 2131 | scsi_qla_host_t *vha = shost_priv(shost); |
| 2132 | |
| 2133 | if (!vha->host) |
| 2134 | return 1; |
| 2135 | if (time > vha->hw->loop_reset_delay * HZ) |
| 2136 | return 1; |
| 2137 | |
| 2138 | return atomic_read(&vha->loop_state) == LOOP_READY; |
| 2139 | } |
| 2140 | |
| 2141 | /* |
| 2142 | * PCI driver interface |
| 2143 | */ |
| 2144 | static int __devinit |
| 2145 | qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) |
| 2146 | { |
| 2147 | int ret = -ENODEV; |
| 2148 | struct Scsi_Host *host; |
| 2149 | scsi_qla_host_t *base_vha = NULL; |
| 2150 | struct qla_hw_data *ha; |
| 2151 | char pci_info[30]; |
| 2152 | char fw_str[30], wq_name[30]; |
| 2153 | struct scsi_host_template *sht; |
| 2154 | int bars, mem_only = 0; |
| 2155 | uint16_t req_length = 0, rsp_length = 0; |
| 2156 | struct req_que *req = NULL; |
| 2157 | struct rsp_que *rsp = NULL; |
| 2158 | |
| 2159 | bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); |
| 2160 | sht = &qla2xxx_driver_template; |
| 2161 | if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || |
| 2162 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || |
| 2163 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || |
| 2164 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || |
| 2165 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || |
| 2166 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || |
| 2167 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || |
| 2168 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || |
| 2169 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || |
| 2170 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) { |
| 2171 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
| 2172 | mem_only = 1; |
| 2173 | ql_dbg_pci(ql_dbg_init, pdev, 0x0007, |
| 2174 | "Mem only adapter.\n"); |
| 2175 | } |
| 2176 | ql_dbg_pci(ql_dbg_init, pdev, 0x0008, |
| 2177 | "Bars=%d.\n", bars); |
| 2178 | |
| 2179 | if (mem_only) { |
| 2180 | if (pci_enable_device_mem(pdev)) |
| 2181 | goto probe_out; |
| 2182 | } else { |
| 2183 | if (pci_enable_device(pdev)) |
| 2184 | goto probe_out; |
| 2185 | } |
| 2186 | |
| 2187 | /* This may fail but that's ok */ |
| 2188 | pci_enable_pcie_error_reporting(pdev); |
| 2189 | |
| 2190 | ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); |
| 2191 | if (!ha) { |
| 2192 | ql_log_pci(ql_log_fatal, pdev, 0x0009, |
| 2193 | "Unable to allocate memory for ha.\n"); |
| 2194 | goto probe_out; |
| 2195 | } |
| 2196 | ql_dbg_pci(ql_dbg_init, pdev, 0x000a, |
| 2197 | "Memory allocated for ha=%p.\n", ha); |
| 2198 | ha->pdev = pdev; |
| 2199 | ha->tgt.enable_class_2 = ql2xenableclass2; |
| 2200 | |
| 2201 | /* Clear our data area */ |
| 2202 | ha->bars = bars; |
| 2203 | ha->mem_only = mem_only; |
| 2204 | spin_lock_init(&ha->hardware_lock); |
| 2205 | spin_lock_init(&ha->vport_slock); |
| 2206 | mutex_init(&ha->selflogin_lock); |
| 2207 | |
| 2208 | /* Set ISP-type information. */ |
| 2209 | qla2x00_set_isp_flags(ha); |
| 2210 | |
| 2211 | /* Set EEH reset type to fundamental if required by hba */ |
| 2212 | if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) |
| 2213 | pdev->needs_freset = 1; |
| 2214 | |
| 2215 | ha->prev_topology = 0; |
| 2216 | ha->init_cb_size = sizeof(init_cb_t); |
| 2217 | ha->link_data_rate = PORT_SPEED_UNKNOWN; |
| 2218 | ha->optrom_size = OPTROM_SIZE_2300; |
| 2219 | |
| 2220 | /* Assign ISP specific operations. */ |
| 2221 | if (IS_QLA2100(ha)) { |
| 2222 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
| 2223 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; |
| 2224 | req_length = REQUEST_ENTRY_CNT_2100; |
| 2225 | rsp_length = RESPONSE_ENTRY_CNT_2100; |
| 2226 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; |
| 2227 | ha->gid_list_info_size = 4; |
| 2228 | ha->flash_conf_off = ~0; |
| 2229 | ha->flash_data_off = ~0; |
| 2230 | ha->nvram_conf_off = ~0; |
| 2231 | ha->nvram_data_off = ~0; |
| 2232 | ha->isp_ops = &qla2100_isp_ops; |
| 2233 | } else if (IS_QLA2200(ha)) { |
| 2234 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
| 2235 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; |
| 2236 | req_length = REQUEST_ENTRY_CNT_2200; |
| 2237 | rsp_length = RESPONSE_ENTRY_CNT_2100; |
| 2238 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; |
| 2239 | ha->gid_list_info_size = 4; |
| 2240 | ha->flash_conf_off = ~0; |
| 2241 | ha->flash_data_off = ~0; |
| 2242 | ha->nvram_conf_off = ~0; |
| 2243 | ha->nvram_data_off = ~0; |
| 2244 | ha->isp_ops = &qla2100_isp_ops; |
| 2245 | } else if (IS_QLA23XX(ha)) { |
| 2246 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
| 2247 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
| 2248 | req_length = REQUEST_ENTRY_CNT_2200; |
| 2249 | rsp_length = RESPONSE_ENTRY_CNT_2300; |
| 2250 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
| 2251 | ha->gid_list_info_size = 6; |
| 2252 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) |
| 2253 | ha->optrom_size = OPTROM_SIZE_2322; |
| 2254 | ha->flash_conf_off = ~0; |
| 2255 | ha->flash_data_off = ~0; |
| 2256 | ha->nvram_conf_off = ~0; |
| 2257 | ha->nvram_data_off = ~0; |
| 2258 | ha->isp_ops = &qla2300_isp_ops; |
| 2259 | } else if (IS_QLA24XX_TYPE(ha)) { |
| 2260 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
| 2261 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
| 2262 | req_length = REQUEST_ENTRY_CNT_24XX; |
| 2263 | rsp_length = RESPONSE_ENTRY_CNT_2300; |
| 2264 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
| 2265 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
| 2266 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
| 2267 | ha->gid_list_info_size = 8; |
| 2268 | ha->optrom_size = OPTROM_SIZE_24XX; |
| 2269 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; |
| 2270 | ha->isp_ops = &qla24xx_isp_ops; |
| 2271 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
| 2272 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; |
| 2273 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; |
| 2274 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; |
| 2275 | } else if (IS_QLA25XX(ha)) { |
| 2276 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
| 2277 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
| 2278 | req_length = REQUEST_ENTRY_CNT_24XX; |
| 2279 | rsp_length = RESPONSE_ENTRY_CNT_2300; |
| 2280 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
| 2281 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
| 2282 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
| 2283 | ha->gid_list_info_size = 8; |
| 2284 | ha->optrom_size = OPTROM_SIZE_25XX; |
| 2285 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
| 2286 | ha->isp_ops = &qla25xx_isp_ops; |
| 2287 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
| 2288 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; |
| 2289 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; |
| 2290 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; |
| 2291 | } else if (IS_QLA81XX(ha)) { |
| 2292 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
| 2293 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
| 2294 | req_length = REQUEST_ENTRY_CNT_24XX; |
| 2295 | rsp_length = RESPONSE_ENTRY_CNT_2300; |
| 2296 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
| 2297 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); |
| 2298 | ha->gid_list_info_size = 8; |
| 2299 | ha->optrom_size = OPTROM_SIZE_81XX; |
| 2300 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
| 2301 | ha->isp_ops = &qla81xx_isp_ops; |
| 2302 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; |
| 2303 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; |
| 2304 | ha->nvram_conf_off = ~0; |
| 2305 | ha->nvram_data_off = ~0; |
| 2306 | } else if (IS_QLA82XX(ha)) { |
| 2307 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
| 2308 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
| 2309 | req_length = REQUEST_ENTRY_CNT_82XX; |
| 2310 | rsp_length = RESPONSE_ENTRY_CNT_82XX; |
| 2311 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
| 2312 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); |
| 2313 | ha->gid_list_info_size = 8; |
| 2314 | ha->optrom_size = OPTROM_SIZE_82XX; |
| 2315 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
| 2316 | ha->isp_ops = &qla82xx_isp_ops; |
| 2317 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
| 2318 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; |
| 2319 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; |
| 2320 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; |
| 2321 | } else if (IS_QLA83XX(ha)) { |
| 2322 | ha->portnum = PCI_FUNC(ha->pdev->devfn); |
| 2323 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
| 2324 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
| 2325 | req_length = REQUEST_ENTRY_CNT_24XX; |
| 2326 | rsp_length = RESPONSE_ENTRY_CNT_2300; |
| 2327 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
| 2328 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); |
| 2329 | ha->gid_list_info_size = 8; |
| 2330 | ha->optrom_size = OPTROM_SIZE_83XX; |
| 2331 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
| 2332 | ha->isp_ops = &qla83xx_isp_ops; |
| 2333 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; |
| 2334 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; |
| 2335 | ha->nvram_conf_off = ~0; |
| 2336 | ha->nvram_data_off = ~0; |
| 2337 | } |
| 2338 | |
| 2339 | ql_dbg_pci(ql_dbg_init, pdev, 0x001e, |
| 2340 | "mbx_count=%d, req_length=%d, " |
| 2341 | "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " |
| 2342 | "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " |
| 2343 | "max_fibre_devices=%d.\n", |
| 2344 | ha->mbx_count, req_length, rsp_length, ha->max_loop_id, |
| 2345 | ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, |
| 2346 | ha->nvram_npiv_size, ha->max_fibre_devices); |
| 2347 | ql_dbg_pci(ql_dbg_init, pdev, 0x001f, |
| 2348 | "isp_ops=%p, flash_conf_off=%d, " |
| 2349 | "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", |
| 2350 | ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, |
| 2351 | ha->nvram_conf_off, ha->nvram_data_off); |
| 2352 | |
| 2353 | /* Configure PCI I/O space */ |
| 2354 | ret = ha->isp_ops->iospace_config(ha); |
| 2355 | if (ret) |
| 2356 | goto probe_hw_failed; |
| 2357 | |
| 2358 | ql_log_pci(ql_log_info, pdev, 0x001d, |
| 2359 | "Found an ISP%04X irq %d iobase 0x%p.\n", |
| 2360 | pdev->device, pdev->irq, ha->iobase); |
| 2361 | mutex_init(&ha->vport_lock); |
| 2362 | init_completion(&ha->mbx_cmd_comp); |
| 2363 | complete(&ha->mbx_cmd_comp); |
| 2364 | init_completion(&ha->mbx_intr_comp); |
| 2365 | init_completion(&ha->dcbx_comp); |
| 2366 | |
| 2367 | set_bit(0, (unsigned long *) ha->vp_idx_map); |
| 2368 | |
| 2369 | qla2x00_config_dma_addressing(ha); |
| 2370 | ql_dbg_pci(ql_dbg_init, pdev, 0x0020, |
| 2371 | "64 Bit addressing is %s.\n", |
| 2372 | ha->flags.enable_64bit_addressing ? "enable" : |
| 2373 | "disable"); |
| 2374 | ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); |
| 2375 | if (!ret) { |
| 2376 | ql_log_pci(ql_log_fatal, pdev, 0x0031, |
| 2377 | "Failed to allocate memory for adapter, aborting.\n"); |
| 2378 | |
| 2379 | goto probe_hw_failed; |
| 2380 | } |
| 2381 | |
| 2382 | req->max_q_depth = MAX_Q_DEPTH; |
| 2383 | if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) |
| 2384 | req->max_q_depth = ql2xmaxqdepth; |
| 2385 | |
| 2386 | |
| 2387 | base_vha = qla2x00_create_host(sht, ha); |
| 2388 | if (!base_vha) { |
| 2389 | ret = -ENOMEM; |
| 2390 | qla2x00_mem_free(ha); |
| 2391 | qla2x00_free_req_que(ha, req); |
| 2392 | qla2x00_free_rsp_que(ha, rsp); |
| 2393 | goto probe_hw_failed; |
| 2394 | } |
| 2395 | |
| 2396 | pci_set_drvdata(pdev, base_vha); |
| 2397 | |
| 2398 | host = base_vha->host; |
| 2399 | base_vha->req = req; |
| 2400 | host->can_queue = req->length + 128; |
| 2401 | if (IS_QLA2XXX_MIDTYPE(ha)) |
| 2402 | base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; |
| 2403 | else |
| 2404 | base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + |
| 2405 | base_vha->vp_idx; |
| 2406 | |
| 2407 | /* Set the SG table size based on ISP type */ |
| 2408 | if (!IS_FWI2_CAPABLE(ha)) { |
| 2409 | if (IS_QLA2100(ha)) |
| 2410 | host->sg_tablesize = 32; |
| 2411 | } else { |
| 2412 | if (!IS_QLA82XX(ha)) |
| 2413 | host->sg_tablesize = QLA_SG_ALL; |
| 2414 | } |
| 2415 | ql_dbg(ql_dbg_init, base_vha, 0x0032, |
| 2416 | "can_queue=%d, req=%p, " |
| 2417 | "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", |
| 2418 | host->can_queue, base_vha->req, |
| 2419 | base_vha->mgmt_svr_loop_id, host->sg_tablesize); |
| 2420 | host->max_id = ha->max_fibre_devices; |
| 2421 | host->cmd_per_lun = 3; |
| 2422 | host->unique_id = host->host_no; |
| 2423 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) |
| 2424 | host->max_cmd_len = 32; |
| 2425 | else |
| 2426 | host->max_cmd_len = MAX_CMDSZ; |
| 2427 | host->max_channel = MAX_BUSES - 1; |
| 2428 | host->max_lun = ql2xmaxlun; |
| 2429 | host->transportt = qla2xxx_transport_template; |
| 2430 | sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); |
| 2431 | |
| 2432 | ql_dbg(ql_dbg_init, base_vha, 0x0033, |
| 2433 | "max_id=%d this_id=%d " |
| 2434 | "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " |
| 2435 | "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id, |
| 2436 | host->this_id, host->cmd_per_lun, host->unique_id, |
| 2437 | host->max_cmd_len, host->max_channel, host->max_lun, |
| 2438 | host->transportt, sht->vendor_id); |
| 2439 | |
| 2440 | que_init: |
| 2441 | /* Alloc arrays of request and response ring ptrs */ |
| 2442 | if (!qla2x00_alloc_queues(ha, req, rsp)) { |
| 2443 | ql_log(ql_log_fatal, base_vha, 0x003d, |
| 2444 | "Failed to allocate memory for queue pointers..." |
| 2445 | "aborting.\n"); |
| 2446 | goto probe_init_failed; |
| 2447 | } |
| 2448 | |
| 2449 | qlt_probe_one_stage1(base_vha, ha); |
| 2450 | |
| 2451 | /* Set up the irqs */ |
| 2452 | ret = qla2x00_request_irqs(ha, rsp); |
| 2453 | if (ret) |
| 2454 | goto probe_init_failed; |
| 2455 | |
| 2456 | pci_save_state(pdev); |
| 2457 | |
| 2458 | /* Assign back pointers */ |
| 2459 | rsp->req = req; |
| 2460 | req->rsp = rsp; |
| 2461 | |
| 2462 | /* FWI2-capable only. */ |
| 2463 | req->req_q_in = &ha->iobase->isp24.req_q_in; |
| 2464 | req->req_q_out = &ha->iobase->isp24.req_q_out; |
| 2465 | rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; |
| 2466 | rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; |
| 2467 | if (ha->mqenable || IS_QLA83XX(ha)) { |
| 2468 | req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; |
| 2469 | req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; |
| 2470 | rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; |
| 2471 | rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; |
| 2472 | } |
| 2473 | |
| 2474 | if (IS_QLA82XX(ha)) { |
| 2475 | req->req_q_out = &ha->iobase->isp82.req_q_out[0]; |
| 2476 | rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; |
| 2477 | rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; |
| 2478 | } |
| 2479 | |
| 2480 | ql_dbg(ql_dbg_multiq, base_vha, 0xc009, |
| 2481 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", |
| 2482 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); |
| 2483 | ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, |
| 2484 | "req->req_q_in=%p req->req_q_out=%p " |
| 2485 | "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", |
| 2486 | req->req_q_in, req->req_q_out, |
| 2487 | rsp->rsp_q_in, rsp->rsp_q_out); |
| 2488 | ql_dbg(ql_dbg_init, base_vha, 0x003e, |
| 2489 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", |
| 2490 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); |
| 2491 | ql_dbg(ql_dbg_init, base_vha, 0x003f, |
| 2492 | "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", |
| 2493 | req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); |
| 2494 | |
| 2495 | if (qla2x00_initialize_adapter(base_vha)) { |
| 2496 | ql_log(ql_log_fatal, base_vha, 0x00d6, |
| 2497 | "Failed to initialize adapter - Adapter flags %x.\n", |
| 2498 | base_vha->device_flags); |
| 2499 | |
| 2500 | if (IS_QLA82XX(ha)) { |
| 2501 | qla82xx_idc_lock(ha); |
| 2502 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
| 2503 | QLA8XXX_DEV_FAILED); |
| 2504 | qla82xx_idc_unlock(ha); |
| 2505 | ql_log(ql_log_fatal, base_vha, 0x00d7, |
| 2506 | "HW State: FAILED.\n"); |
| 2507 | } |
| 2508 | |
| 2509 | ret = -ENODEV; |
| 2510 | goto probe_failed; |
| 2511 | } |
| 2512 | |
| 2513 | if (ha->mqenable) { |
| 2514 | if (qla25xx_setup_mode(base_vha)) { |
| 2515 | ql_log(ql_log_warn, base_vha, 0x00ec, |
| 2516 | "Failed to create queues, falling back to single queue mode.\n"); |
| 2517 | goto que_init; |
| 2518 | } |
| 2519 | } |
| 2520 | |
| 2521 | if (ha->flags.running_gold_fw) |
| 2522 | goto skip_dpc; |
| 2523 | |
| 2524 | /* |
| 2525 | * Startup the kernel thread for this host adapter |
| 2526 | */ |
| 2527 | ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, |
| 2528 | "%s_dpc", base_vha->host_str); |
| 2529 | if (IS_ERR(ha->dpc_thread)) { |
| 2530 | ql_log(ql_log_fatal, base_vha, 0x00ed, |
| 2531 | "Failed to start DPC thread.\n"); |
| 2532 | ret = PTR_ERR(ha->dpc_thread); |
| 2533 | goto probe_failed; |
| 2534 | } |
| 2535 | ql_dbg(ql_dbg_init, base_vha, 0x00ee, |
| 2536 | "DPC thread started successfully.\n"); |
| 2537 | |
| 2538 | /* |
| 2539 | * If we're not coming up in initiator mode, we might sit for |
| 2540 | * a while without waking up the dpc thread, which leads to a |
| 2541 | * stuck process warning. So just kick the dpc once here and |
| 2542 | * let the kthread start (and go back to sleep in qla2x00_do_dpc). |
| 2543 | */ |
| 2544 | qla2xxx_wake_dpc(base_vha); |
| 2545 | |
| 2546 | if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { |
| 2547 | sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); |
| 2548 | ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); |
| 2549 | INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); |
| 2550 | |
| 2551 | sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); |
| 2552 | ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); |
| 2553 | INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); |
| 2554 | INIT_WORK(&ha->idc_state_handler, |
| 2555 | qla83xx_idc_state_handler_work); |
| 2556 | INIT_WORK(&ha->nic_core_unrecoverable, |
| 2557 | qla83xx_nic_core_unrecoverable_work); |
| 2558 | } |
| 2559 | |
| 2560 | skip_dpc: |
| 2561 | list_add_tail(&base_vha->list, &ha->vp_list); |
| 2562 | base_vha->host->irq = ha->pdev->irq; |
| 2563 | |
| 2564 | /* Initialized the timer */ |
| 2565 | qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); |
| 2566 | ql_dbg(ql_dbg_init, base_vha, 0x00ef, |
| 2567 | "Started qla2x00_timer with " |
| 2568 | "interval=%d.\n", WATCH_INTERVAL); |
| 2569 | ql_dbg(ql_dbg_init, base_vha, 0x00f0, |
| 2570 | "Detected hba at address=%p.\n", |
| 2571 | ha); |
| 2572 | |
| 2573 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { |
| 2574 | if (ha->fw_attributes & BIT_4) { |
| 2575 | int prot = 0; |
| 2576 | base_vha->flags.difdix_supported = 1; |
| 2577 | ql_dbg(ql_dbg_init, base_vha, 0x00f1, |
| 2578 | "Registering for DIF/DIX type 1 and 3 protection.\n"); |
| 2579 | if (ql2xenabledif == 1) |
| 2580 | prot = SHOST_DIX_TYPE0_PROTECTION; |
| 2581 | scsi_host_set_prot(host, |
| 2582 | prot | SHOST_DIF_TYPE1_PROTECTION |
| 2583 | | SHOST_DIF_TYPE2_PROTECTION |
| 2584 | | SHOST_DIF_TYPE3_PROTECTION |
| 2585 | | SHOST_DIX_TYPE1_PROTECTION |
| 2586 | | SHOST_DIX_TYPE2_PROTECTION |
| 2587 | | SHOST_DIX_TYPE3_PROTECTION); |
| 2588 | scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC); |
| 2589 | } else |
| 2590 | base_vha->flags.difdix_supported = 0; |
| 2591 | } |
| 2592 | |
| 2593 | ha->isp_ops->enable_intrs(ha); |
| 2594 | |
| 2595 | ret = scsi_add_host(host, &pdev->dev); |
| 2596 | if (ret) |
| 2597 | goto probe_failed; |
| 2598 | |
| 2599 | base_vha->flags.init_done = 1; |
| 2600 | base_vha->flags.online = 1; |
| 2601 | |
| 2602 | ql_dbg(ql_dbg_init, base_vha, 0x00f2, |
| 2603 | "Init done and hba is online.\n"); |
| 2604 | |
| 2605 | if (qla_ini_mode_enabled(base_vha)) |
| 2606 | scsi_scan_host(host); |
| 2607 | else |
| 2608 | ql_dbg(ql_dbg_init, base_vha, 0x0122, |
| 2609 | "skipping scsi_scan_host() for non-initiator port\n"); |
| 2610 | |
| 2611 | qla2x00_alloc_sysfs_attr(base_vha); |
| 2612 | |
| 2613 | qla2x00_init_host_attr(base_vha); |
| 2614 | |
| 2615 | qla2x00_dfs_setup(base_vha); |
| 2616 | |
| 2617 | ql_log(ql_log_info, base_vha, 0x00fb, |
| 2618 | "QLogic %s - %s.\n", |
| 2619 | ha->model_number, ha->model_desc ? ha->model_desc : ""); |
| 2620 | ql_log(ql_log_info, base_vha, 0x00fc, |
| 2621 | "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", |
| 2622 | pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), |
| 2623 | pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', |
| 2624 | base_vha->host_no, |
| 2625 | ha->isp_ops->fw_version_str(base_vha, fw_str)); |
| 2626 | |
| 2627 | qlt_add_target(ha, base_vha); |
| 2628 | |
| 2629 | return 0; |
| 2630 | |
| 2631 | probe_init_failed: |
| 2632 | qla2x00_free_req_que(ha, req); |
| 2633 | ha->req_q_map[0] = NULL; |
| 2634 | clear_bit(0, ha->req_qid_map); |
| 2635 | qla2x00_free_rsp_que(ha, rsp); |
| 2636 | ha->rsp_q_map[0] = NULL; |
| 2637 | clear_bit(0, ha->rsp_qid_map); |
| 2638 | ha->max_req_queues = ha->max_rsp_queues = 0; |
| 2639 | |
| 2640 | probe_failed: |
| 2641 | if (base_vha->timer_active) |
| 2642 | qla2x00_stop_timer(base_vha); |
| 2643 | base_vha->flags.online = 0; |
| 2644 | if (ha->dpc_thread) { |
| 2645 | struct task_struct *t = ha->dpc_thread; |
| 2646 | |
| 2647 | ha->dpc_thread = NULL; |
| 2648 | kthread_stop(t); |
| 2649 | } |
| 2650 | |
| 2651 | qla2x00_free_device(base_vha); |
| 2652 | |
| 2653 | scsi_host_put(base_vha->host); |
| 2654 | |
| 2655 | probe_hw_failed: |
| 2656 | if (IS_QLA82XX(ha)) { |
| 2657 | qla82xx_idc_lock(ha); |
| 2658 | qla82xx_clear_drv_active(ha); |
| 2659 | qla82xx_idc_unlock(ha); |
| 2660 | iounmap((device_reg_t __iomem *)ha->nx_pcibase); |
| 2661 | if (!ql2xdbwr) |
| 2662 | iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); |
| 2663 | } else { |
| 2664 | if (ha->iobase) |
| 2665 | iounmap(ha->iobase); |
| 2666 | } |
| 2667 | pci_release_selected_regions(ha->pdev, ha->bars); |
| 2668 | kfree(ha); |
| 2669 | ha = NULL; |
| 2670 | |
| 2671 | probe_out: |
| 2672 | pci_disable_device(pdev); |
| 2673 | return ret; |
| 2674 | } |
| 2675 | |
| 2676 | static void |
| 2677 | qla2x00_stop_dpc_thread(scsi_qla_host_t *vha) |
| 2678 | { |
| 2679 | struct qla_hw_data *ha = vha->hw; |
| 2680 | struct task_struct *t = ha->dpc_thread; |
| 2681 | |
| 2682 | if (ha->dpc_thread == NULL) |
| 2683 | return; |
| 2684 | /* |
| 2685 | * qla2xxx_wake_dpc checks for ->dpc_thread |
| 2686 | * so we need to zero it out. |
| 2687 | */ |
| 2688 | ha->dpc_thread = NULL; |
| 2689 | kthread_stop(t); |
| 2690 | } |
| 2691 | |
| 2692 | static void |
| 2693 | qla2x00_shutdown(struct pci_dev *pdev) |
| 2694 | { |
| 2695 | scsi_qla_host_t *vha; |
| 2696 | struct qla_hw_data *ha; |
| 2697 | |
| 2698 | vha = pci_get_drvdata(pdev); |
| 2699 | ha = vha->hw; |
| 2700 | |
| 2701 | /* Turn-off FCE trace */ |
| 2702 | if (ha->flags.fce_enabled) { |
| 2703 | qla2x00_disable_fce_trace(vha, NULL, NULL); |
| 2704 | ha->flags.fce_enabled = 0; |
| 2705 | } |
| 2706 | |
| 2707 | /* Turn-off EFT trace */ |
| 2708 | if (ha->eft) |
| 2709 | qla2x00_disable_eft_trace(vha); |
| 2710 | |
| 2711 | /* Stop currently executing firmware. */ |
| 2712 | qla2x00_try_to_stop_firmware(vha); |
| 2713 | |
| 2714 | /* Turn adapter off line */ |
| 2715 | vha->flags.online = 0; |
| 2716 | |
| 2717 | /* turn-off interrupts on the card */ |
| 2718 | if (ha->interrupts_on) { |
| 2719 | vha->flags.init_done = 0; |
| 2720 | ha->isp_ops->disable_intrs(ha); |
| 2721 | } |
| 2722 | |
| 2723 | qla2x00_free_irqs(vha); |
| 2724 | |
| 2725 | qla2x00_free_fw_dump(ha); |
| 2726 | } |
| 2727 | |
| 2728 | static void |
| 2729 | qla2x00_remove_one(struct pci_dev *pdev) |
| 2730 | { |
| 2731 | scsi_qla_host_t *base_vha, *vha; |
| 2732 | struct qla_hw_data *ha; |
| 2733 | unsigned long flags; |
| 2734 | |
| 2735 | /* |
| 2736 | * If the PCI device is disabled that means that probe failed and any |
| 2737 | * resources should be have cleaned up on probe exit. |
| 2738 | */ |
| 2739 | if (!atomic_read(&pdev->enable_cnt)) |
| 2740 | return; |
| 2741 | |
| 2742 | base_vha = pci_get_drvdata(pdev); |
| 2743 | ha = base_vha->hw; |
| 2744 | |
| 2745 | ha->flags.host_shutting_down = 1; |
| 2746 | |
| 2747 | mutex_lock(&ha->vport_lock); |
| 2748 | while (ha->cur_vport_count) { |
| 2749 | struct Scsi_Host *scsi_host; |
| 2750 | |
| 2751 | spin_lock_irqsave(&ha->vport_slock, flags); |
| 2752 | |
| 2753 | BUG_ON(base_vha->list.next == &ha->vp_list); |
| 2754 | /* This assumes first entry in ha->vp_list is always base vha */ |
| 2755 | vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); |
| 2756 | scsi_host = scsi_host_get(vha->host); |
| 2757 | |
| 2758 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
| 2759 | mutex_unlock(&ha->vport_lock); |
| 2760 | |
| 2761 | fc_vport_terminate(vha->fc_vport); |
| 2762 | scsi_host_put(vha->host); |
| 2763 | |
| 2764 | mutex_lock(&ha->vport_lock); |
| 2765 | } |
| 2766 | mutex_unlock(&ha->vport_lock); |
| 2767 | |
| 2768 | if (IS_QLA8031(ha)) { |
| 2769 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, |
| 2770 | "Clearing fcoe driver presence.\n"); |
| 2771 | if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) |
| 2772 | ql_dbg(ql_dbg_p3p, base_vha, 0xb079, |
| 2773 | "Error while clearing DRV-Presence.\n"); |
| 2774 | } |
| 2775 | |
| 2776 | set_bit(UNLOADING, &base_vha->dpc_flags); |
| 2777 | |
| 2778 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); |
| 2779 | |
| 2780 | qla2x00_dfs_remove(base_vha); |
| 2781 | |
| 2782 | qla84xx_put_chip(base_vha); |
| 2783 | |
| 2784 | /* Disable timer */ |
| 2785 | if (base_vha->timer_active) |
| 2786 | qla2x00_stop_timer(base_vha); |
| 2787 | |
| 2788 | base_vha->flags.online = 0; |
| 2789 | |
| 2790 | /* Flush the work queue and remove it */ |
| 2791 | if (ha->wq) { |
| 2792 | flush_workqueue(ha->wq); |
| 2793 | destroy_workqueue(ha->wq); |
| 2794 | ha->wq = NULL; |
| 2795 | } |
| 2796 | |
| 2797 | /* Cancel all work and destroy DPC workqueues */ |
| 2798 | if (ha->dpc_lp_wq) { |
| 2799 | cancel_work_sync(&ha->idc_aen); |
| 2800 | destroy_workqueue(ha->dpc_lp_wq); |
| 2801 | ha->dpc_lp_wq = NULL; |
| 2802 | } |
| 2803 | |
| 2804 | if (ha->dpc_hp_wq) { |
| 2805 | cancel_work_sync(&ha->nic_core_reset); |
| 2806 | cancel_work_sync(&ha->idc_state_handler); |
| 2807 | cancel_work_sync(&ha->nic_core_unrecoverable); |
| 2808 | destroy_workqueue(ha->dpc_hp_wq); |
| 2809 | ha->dpc_hp_wq = NULL; |
| 2810 | } |
| 2811 | |
| 2812 | /* Kill the kernel thread for this host */ |
| 2813 | if (ha->dpc_thread) { |
| 2814 | struct task_struct *t = ha->dpc_thread; |
| 2815 | |
| 2816 | /* |
| 2817 | * qla2xxx_wake_dpc checks for ->dpc_thread |
| 2818 | * so we need to zero it out. |
| 2819 | */ |
| 2820 | ha->dpc_thread = NULL; |
| 2821 | kthread_stop(t); |
| 2822 | } |
| 2823 | qlt_remove_target(ha, base_vha); |
| 2824 | |
| 2825 | qla2x00_free_sysfs_attr(base_vha); |
| 2826 | |
| 2827 | fc_remove_host(base_vha->host); |
| 2828 | |
| 2829 | scsi_remove_host(base_vha->host); |
| 2830 | |
| 2831 | qla2x00_free_device(base_vha); |
| 2832 | |
| 2833 | scsi_host_put(base_vha->host); |
| 2834 | |
| 2835 | if (IS_QLA82XX(ha)) { |
| 2836 | qla82xx_idc_lock(ha); |
| 2837 | qla82xx_clear_drv_active(ha); |
| 2838 | qla82xx_idc_unlock(ha); |
| 2839 | |
| 2840 | iounmap((device_reg_t __iomem *)ha->nx_pcibase); |
| 2841 | if (!ql2xdbwr) |
| 2842 | iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); |
| 2843 | } else { |
| 2844 | if (ha->iobase) |
| 2845 | iounmap(ha->iobase); |
| 2846 | |
| 2847 | if (ha->mqiobase) |
| 2848 | iounmap(ha->mqiobase); |
| 2849 | |
| 2850 | if (IS_QLA83XX(ha) && ha->msixbase) |
| 2851 | iounmap(ha->msixbase); |
| 2852 | } |
| 2853 | |
| 2854 | pci_release_selected_regions(ha->pdev, ha->bars); |
| 2855 | kfree(ha); |
| 2856 | ha = NULL; |
| 2857 | |
| 2858 | pci_disable_pcie_error_reporting(pdev); |
| 2859 | |
| 2860 | pci_disable_device(pdev); |
| 2861 | pci_set_drvdata(pdev, NULL); |
| 2862 | } |
| 2863 | |
| 2864 | static void |
| 2865 | qla2x00_free_device(scsi_qla_host_t *vha) |
| 2866 | { |
| 2867 | struct qla_hw_data *ha = vha->hw; |
| 2868 | |
| 2869 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); |
| 2870 | |
| 2871 | /* Disable timer */ |
| 2872 | if (vha->timer_active) |
| 2873 | qla2x00_stop_timer(vha); |
| 2874 | |
| 2875 | qla2x00_stop_dpc_thread(vha); |
| 2876 | |
| 2877 | qla25xx_delete_queues(vha); |
| 2878 | if (ha->flags.fce_enabled) |
| 2879 | qla2x00_disable_fce_trace(vha, NULL, NULL); |
| 2880 | |
| 2881 | if (ha->eft) |
| 2882 | qla2x00_disable_eft_trace(vha); |
| 2883 | |
| 2884 | /* Stop currently executing firmware. */ |
| 2885 | qla2x00_try_to_stop_firmware(vha); |
| 2886 | |
| 2887 | vha->flags.online = 0; |
| 2888 | |
| 2889 | /* turn-off interrupts on the card */ |
| 2890 | if (ha->interrupts_on) { |
| 2891 | vha->flags.init_done = 0; |
| 2892 | ha->isp_ops->disable_intrs(ha); |
| 2893 | } |
| 2894 | |
| 2895 | qla2x00_free_irqs(vha); |
| 2896 | |
| 2897 | qla2x00_free_fcports(vha); |
| 2898 | |
| 2899 | qla2x00_mem_free(ha); |
| 2900 | |
| 2901 | qla82xx_md_free(vha); |
| 2902 | |
| 2903 | qla2x00_free_queues(ha); |
| 2904 | } |
| 2905 | |
| 2906 | void qla2x00_free_fcports(struct scsi_qla_host *vha) |
| 2907 | { |
| 2908 | fc_port_t *fcport, *tfcport; |
| 2909 | |
| 2910 | list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { |
| 2911 | list_del(&fcport->list); |
| 2912 | qla2x00_clear_loop_id(fcport); |
| 2913 | kfree(fcport); |
| 2914 | fcport = NULL; |
| 2915 | } |
| 2916 | } |
| 2917 | |
| 2918 | static inline void |
| 2919 | qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, |
| 2920 | int defer) |
| 2921 | { |
| 2922 | struct fc_rport *rport; |
| 2923 | scsi_qla_host_t *base_vha; |
| 2924 | unsigned long flags; |
| 2925 | |
| 2926 | if (!fcport->rport) |
| 2927 | return; |
| 2928 | |
| 2929 | rport = fcport->rport; |
| 2930 | if (defer) { |
| 2931 | base_vha = pci_get_drvdata(vha->hw->pdev); |
| 2932 | spin_lock_irqsave(vha->host->host_lock, flags); |
| 2933 | fcport->drport = rport; |
| 2934 | spin_unlock_irqrestore(vha->host->host_lock, flags); |
| 2935 | set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); |
| 2936 | qla2xxx_wake_dpc(base_vha); |
| 2937 | } else { |
| 2938 | fc_remote_port_delete(rport); |
| 2939 | qlt_fc_port_deleted(vha, fcport); |
| 2940 | } |
| 2941 | } |
| 2942 | |
| 2943 | /* |
| 2944 | * qla2x00_mark_device_lost Updates fcport state when device goes offline. |
| 2945 | * |
| 2946 | * Input: ha = adapter block pointer. fcport = port structure pointer. |
| 2947 | * |
| 2948 | * Return: None. |
| 2949 | * |
| 2950 | * Context: |
| 2951 | */ |
| 2952 | void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, |
| 2953 | int do_login, int defer) |
| 2954 | { |
| 2955 | if (atomic_read(&fcport->state) == FCS_ONLINE && |
| 2956 | vha->vp_idx == fcport->vha->vp_idx) { |
| 2957 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
| 2958 | qla2x00_schedule_rport_del(vha, fcport, defer); |
| 2959 | } |
| 2960 | /* |
| 2961 | * We may need to retry the login, so don't change the state of the |
| 2962 | * port but do the retries. |
| 2963 | */ |
| 2964 | if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) |
| 2965 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
| 2966 | |
| 2967 | if (!do_login) |
| 2968 | return; |
| 2969 | |
| 2970 | if (fcport->login_retry == 0) { |
| 2971 | fcport->login_retry = vha->hw->login_retry_count; |
| 2972 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); |
| 2973 | |
| 2974 | ql_dbg(ql_dbg_disc, vha, 0x2067, |
| 2975 | "Port login retry " |
| 2976 | "%02x%02x%02x%02x%02x%02x%02x%02x, " |
| 2977 | "id = 0x%04x retry cnt=%d.\n", |
| 2978 | fcport->port_name[0], fcport->port_name[1], |
| 2979 | fcport->port_name[2], fcport->port_name[3], |
| 2980 | fcport->port_name[4], fcport->port_name[5], |
| 2981 | fcport->port_name[6], fcport->port_name[7], |
| 2982 | fcport->loop_id, fcport->login_retry); |
| 2983 | } |
| 2984 | } |
| 2985 | |
| 2986 | /* |
| 2987 | * qla2x00_mark_all_devices_lost |
| 2988 | * Updates fcport state when device goes offline. |
| 2989 | * |
| 2990 | * Input: |
| 2991 | * ha = adapter block pointer. |
| 2992 | * fcport = port structure pointer. |
| 2993 | * |
| 2994 | * Return: |
| 2995 | * None. |
| 2996 | * |
| 2997 | * Context: |
| 2998 | */ |
| 2999 | void |
| 3000 | qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) |
| 3001 | { |
| 3002 | fc_port_t *fcport; |
| 3003 | |
| 3004 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
| 3005 | if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) |
| 3006 | continue; |
| 3007 | |
| 3008 | /* |
| 3009 | * No point in marking the device as lost, if the device is |
| 3010 | * already DEAD. |
| 3011 | */ |
| 3012 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) |
| 3013 | continue; |
| 3014 | if (atomic_read(&fcport->state) == FCS_ONLINE) { |
| 3015 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
| 3016 | if (defer) |
| 3017 | qla2x00_schedule_rport_del(vha, fcport, defer); |
| 3018 | else if (vha->vp_idx == fcport->vha->vp_idx) |
| 3019 | qla2x00_schedule_rport_del(vha, fcport, defer); |
| 3020 | } |
| 3021 | } |
| 3022 | } |
| 3023 | |
| 3024 | /* |
| 3025 | * qla2x00_mem_alloc |
| 3026 | * Allocates adapter memory. |
| 3027 | * |
| 3028 | * Returns: |
| 3029 | * 0 = success. |
| 3030 | * !0 = failure. |
| 3031 | */ |
| 3032 | static int |
| 3033 | qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, |
| 3034 | struct req_que **req, struct rsp_que **rsp) |
| 3035 | { |
| 3036 | char name[16]; |
| 3037 | |
| 3038 | ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, |
| 3039 | &ha->init_cb_dma, GFP_KERNEL); |
| 3040 | if (!ha->init_cb) |
| 3041 | goto fail; |
| 3042 | |
| 3043 | if (qlt_mem_alloc(ha) < 0) |
| 3044 | goto fail_free_init_cb; |
| 3045 | |
| 3046 | ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, |
| 3047 | qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); |
| 3048 | if (!ha->gid_list) |
| 3049 | goto fail_free_tgt_mem; |
| 3050 | |
| 3051 | ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); |
| 3052 | if (!ha->srb_mempool) |
| 3053 | goto fail_free_gid_list; |
| 3054 | |
| 3055 | if (IS_QLA82XX(ha)) { |
| 3056 | /* Allocate cache for CT6 Ctx. */ |
| 3057 | if (!ctx_cachep) { |
| 3058 | ctx_cachep = kmem_cache_create("qla2xxx_ctx", |
| 3059 | sizeof(struct ct6_dsd), 0, |
| 3060 | SLAB_HWCACHE_ALIGN, NULL); |
| 3061 | if (!ctx_cachep) |
| 3062 | goto fail_free_gid_list; |
| 3063 | } |
| 3064 | ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, |
| 3065 | ctx_cachep); |
| 3066 | if (!ha->ctx_mempool) |
| 3067 | goto fail_free_srb_mempool; |
| 3068 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, |
| 3069 | "ctx_cachep=%p ctx_mempool=%p.\n", |
| 3070 | ctx_cachep, ha->ctx_mempool); |
| 3071 | } |
| 3072 | |
| 3073 | /* Get memory for cached NVRAM */ |
| 3074 | ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); |
| 3075 | if (!ha->nvram) |
| 3076 | goto fail_free_ctx_mempool; |
| 3077 | |
| 3078 | snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, |
| 3079 | ha->pdev->device); |
| 3080 | ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, |
| 3081 | DMA_POOL_SIZE, 8, 0); |
| 3082 | if (!ha->s_dma_pool) |
| 3083 | goto fail_free_nvram; |
| 3084 | |
| 3085 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, |
| 3086 | "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", |
| 3087 | ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); |
| 3088 | |
| 3089 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
| 3090 | ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, |
| 3091 | DSD_LIST_DMA_POOL_SIZE, 8, 0); |
| 3092 | if (!ha->dl_dma_pool) { |
| 3093 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, |
| 3094 | "Failed to allocate memory for dl_dma_pool.\n"); |
| 3095 | goto fail_s_dma_pool; |
| 3096 | } |
| 3097 | |
| 3098 | ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, |
| 3099 | FCP_CMND_DMA_POOL_SIZE, 8, 0); |
| 3100 | if (!ha->fcp_cmnd_dma_pool) { |
| 3101 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, |
| 3102 | "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); |
| 3103 | goto fail_dl_dma_pool; |
| 3104 | } |
| 3105 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, |
| 3106 | "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", |
| 3107 | ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); |
| 3108 | } |
| 3109 | |
| 3110 | /* Allocate memory for SNS commands */ |
| 3111 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { |
| 3112 | /* Get consistent memory allocated for SNS commands */ |
| 3113 | ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, |
| 3114 | sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); |
| 3115 | if (!ha->sns_cmd) |
| 3116 | goto fail_dma_pool; |
| 3117 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, |
| 3118 | "sns_cmd: %p.\n", ha->sns_cmd); |
| 3119 | } else { |
| 3120 | /* Get consistent memory allocated for MS IOCB */ |
| 3121 | ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
| 3122 | &ha->ms_iocb_dma); |
| 3123 | if (!ha->ms_iocb) |
| 3124 | goto fail_dma_pool; |
| 3125 | /* Get consistent memory allocated for CT SNS commands */ |
| 3126 | ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, |
| 3127 | sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); |
| 3128 | if (!ha->ct_sns) |
| 3129 | goto fail_free_ms_iocb; |
| 3130 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, |
| 3131 | "ms_iocb=%p ct_sns=%p.\n", |
| 3132 | ha->ms_iocb, ha->ct_sns); |
| 3133 | } |
| 3134 | |
| 3135 | /* Allocate memory for request ring */ |
| 3136 | *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); |
| 3137 | if (!*req) { |
| 3138 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, |
| 3139 | "Failed to allocate memory for req.\n"); |
| 3140 | goto fail_req; |
| 3141 | } |
| 3142 | (*req)->length = req_len; |
| 3143 | (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, |
| 3144 | ((*req)->length + 1) * sizeof(request_t), |
| 3145 | &(*req)->dma, GFP_KERNEL); |
| 3146 | if (!(*req)->ring) { |
| 3147 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, |
| 3148 | "Failed to allocate memory for req_ring.\n"); |
| 3149 | goto fail_req_ring; |
| 3150 | } |
| 3151 | /* Allocate memory for response ring */ |
| 3152 | *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); |
| 3153 | if (!*rsp) { |
| 3154 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, |
| 3155 | "Failed to allocate memory for rsp.\n"); |
| 3156 | goto fail_rsp; |
| 3157 | } |
| 3158 | (*rsp)->hw = ha; |
| 3159 | (*rsp)->length = rsp_len; |
| 3160 | (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, |
| 3161 | ((*rsp)->length + 1) * sizeof(response_t), |
| 3162 | &(*rsp)->dma, GFP_KERNEL); |
| 3163 | if (!(*rsp)->ring) { |
| 3164 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, |
| 3165 | "Failed to allocate memory for rsp_ring.\n"); |
| 3166 | goto fail_rsp_ring; |
| 3167 | } |
| 3168 | (*req)->rsp = *rsp; |
| 3169 | (*rsp)->req = *req; |
| 3170 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, |
| 3171 | "req=%p req->length=%d req->ring=%p rsp=%p " |
| 3172 | "rsp->length=%d rsp->ring=%p.\n", |
| 3173 | *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, |
| 3174 | (*rsp)->ring); |
| 3175 | /* Allocate memory for NVRAM data for vports */ |
| 3176 | if (ha->nvram_npiv_size) { |
| 3177 | ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * |
| 3178 | ha->nvram_npiv_size, GFP_KERNEL); |
| 3179 | if (!ha->npiv_info) { |
| 3180 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, |
| 3181 | "Failed to allocate memory for npiv_info.\n"); |
| 3182 | goto fail_npiv_info; |
| 3183 | } |
| 3184 | } else |
| 3185 | ha->npiv_info = NULL; |
| 3186 | |
| 3187 | /* Get consistent memory allocated for EX-INIT-CB. */ |
| 3188 | if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) { |
| 3189 | ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
| 3190 | &ha->ex_init_cb_dma); |
| 3191 | if (!ha->ex_init_cb) |
| 3192 | goto fail_ex_init_cb; |
| 3193 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, |
| 3194 | "ex_init_cb=%p.\n", ha->ex_init_cb); |
| 3195 | } |
| 3196 | |
| 3197 | INIT_LIST_HEAD(&ha->gbl_dsd_list); |
| 3198 | |
| 3199 | /* Get consistent memory allocated for Async Port-Database. */ |
| 3200 | if (!IS_FWI2_CAPABLE(ha)) { |
| 3201 | ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
| 3202 | &ha->async_pd_dma); |
| 3203 | if (!ha->async_pd) |
| 3204 | goto fail_async_pd; |
| 3205 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, |
| 3206 | "async_pd=%p.\n", ha->async_pd); |
| 3207 | } |
| 3208 | |
| 3209 | INIT_LIST_HEAD(&ha->vp_list); |
| 3210 | |
| 3211 | /* Allocate memory for our loop_id bitmap */ |
| 3212 | ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), |
| 3213 | GFP_KERNEL); |
| 3214 | if (!ha->loop_id_map) |
| 3215 | goto fail_async_pd; |
| 3216 | else { |
| 3217 | qla2x00_set_reserved_loop_ids(ha); |
| 3218 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, |
| 3219 | "loop_id_map=%p. \n", ha->loop_id_map); |
| 3220 | } |
| 3221 | |
| 3222 | return 1; |
| 3223 | |
| 3224 | fail_async_pd: |
| 3225 | dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); |
| 3226 | fail_ex_init_cb: |
| 3227 | kfree(ha->npiv_info); |
| 3228 | fail_npiv_info: |
| 3229 | dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * |
| 3230 | sizeof(response_t), (*rsp)->ring, (*rsp)->dma); |
| 3231 | (*rsp)->ring = NULL; |
| 3232 | (*rsp)->dma = 0; |
| 3233 | fail_rsp_ring: |
| 3234 | kfree(*rsp); |
| 3235 | fail_rsp: |
| 3236 | dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * |
| 3237 | sizeof(request_t), (*req)->ring, (*req)->dma); |
| 3238 | (*req)->ring = NULL; |
| 3239 | (*req)->dma = 0; |
| 3240 | fail_req_ring: |
| 3241 | kfree(*req); |
| 3242 | fail_req: |
| 3243 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), |
| 3244 | ha->ct_sns, ha->ct_sns_dma); |
| 3245 | ha->ct_sns = NULL; |
| 3246 | ha->ct_sns_dma = 0; |
| 3247 | fail_free_ms_iocb: |
| 3248 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); |
| 3249 | ha->ms_iocb = NULL; |
| 3250 | ha->ms_iocb_dma = 0; |
| 3251 | fail_dma_pool: |
| 3252 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
| 3253 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); |
| 3254 | ha->fcp_cmnd_dma_pool = NULL; |
| 3255 | } |
| 3256 | fail_dl_dma_pool: |
| 3257 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
| 3258 | dma_pool_destroy(ha->dl_dma_pool); |
| 3259 | ha->dl_dma_pool = NULL; |
| 3260 | } |
| 3261 | fail_s_dma_pool: |
| 3262 | dma_pool_destroy(ha->s_dma_pool); |
| 3263 | ha->s_dma_pool = NULL; |
| 3264 | fail_free_nvram: |
| 3265 | kfree(ha->nvram); |
| 3266 | ha->nvram = NULL; |
| 3267 | fail_free_ctx_mempool: |
| 3268 | mempool_destroy(ha->ctx_mempool); |
| 3269 | ha->ctx_mempool = NULL; |
| 3270 | fail_free_srb_mempool: |
| 3271 | mempool_destroy(ha->srb_mempool); |
| 3272 | ha->srb_mempool = NULL; |
| 3273 | fail_free_gid_list: |
| 3274 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), |
| 3275 | ha->gid_list, |
| 3276 | ha->gid_list_dma); |
| 3277 | ha->gid_list = NULL; |
| 3278 | ha->gid_list_dma = 0; |
| 3279 | fail_free_tgt_mem: |
| 3280 | qlt_mem_free(ha); |
| 3281 | fail_free_init_cb: |
| 3282 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, |
| 3283 | ha->init_cb_dma); |
| 3284 | ha->init_cb = NULL; |
| 3285 | ha->init_cb_dma = 0; |
| 3286 | fail: |
| 3287 | ql_log(ql_log_fatal, NULL, 0x0030, |
| 3288 | "Memory allocation failure.\n"); |
| 3289 | return -ENOMEM; |
| 3290 | } |
| 3291 | |
| 3292 | /* |
| 3293 | * qla2x00_free_fw_dump |
| 3294 | * Frees fw dump stuff. |
| 3295 | * |
| 3296 | * Input: |
| 3297 | * ha = adapter block pointer. |
| 3298 | */ |
| 3299 | static void |
| 3300 | qla2x00_free_fw_dump(struct qla_hw_data *ha) |
| 3301 | { |
| 3302 | if (ha->fce) |
| 3303 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, |
| 3304 | ha->fce_dma); |
| 3305 | |
| 3306 | if (ha->fw_dump) { |
| 3307 | if (ha->eft) |
| 3308 | dma_free_coherent(&ha->pdev->dev, |
| 3309 | ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma); |
| 3310 | vfree(ha->fw_dump); |
| 3311 | } |
| 3312 | ha->fce = NULL; |
| 3313 | ha->fce_dma = 0; |
| 3314 | ha->eft = NULL; |
| 3315 | ha->eft_dma = 0; |
| 3316 | ha->fw_dump = NULL; |
| 3317 | ha->fw_dumped = 0; |
| 3318 | ha->fw_dump_reading = 0; |
| 3319 | } |
| 3320 | |
| 3321 | /* |
| 3322 | * qla2x00_mem_free |
| 3323 | * Frees all adapter allocated memory. |
| 3324 | * |
| 3325 | * Input: |
| 3326 | * ha = adapter block pointer. |
| 3327 | */ |
| 3328 | static void |
| 3329 | qla2x00_mem_free(struct qla_hw_data *ha) |
| 3330 | { |
| 3331 | qla2x00_free_fw_dump(ha); |
| 3332 | |
| 3333 | if (ha->mctp_dump) |
| 3334 | dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, |
| 3335 | ha->mctp_dump_dma); |
| 3336 | |
| 3337 | if (ha->srb_mempool) |
| 3338 | mempool_destroy(ha->srb_mempool); |
| 3339 | |
| 3340 | if (ha->dcbx_tlv) |
| 3341 | dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, |
| 3342 | ha->dcbx_tlv, ha->dcbx_tlv_dma); |
| 3343 | |
| 3344 | if (ha->xgmac_data) |
| 3345 | dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, |
| 3346 | ha->xgmac_data, ha->xgmac_data_dma); |
| 3347 | |
| 3348 | if (ha->sns_cmd) |
| 3349 | dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), |
| 3350 | ha->sns_cmd, ha->sns_cmd_dma); |
| 3351 | |
| 3352 | if (ha->ct_sns) |
| 3353 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), |
| 3354 | ha->ct_sns, ha->ct_sns_dma); |
| 3355 | |
| 3356 | if (ha->sfp_data) |
| 3357 | dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); |
| 3358 | |
| 3359 | if (ha->ms_iocb) |
| 3360 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); |
| 3361 | |
| 3362 | if (ha->ex_init_cb) |
| 3363 | dma_pool_free(ha->s_dma_pool, |
| 3364 | ha->ex_init_cb, ha->ex_init_cb_dma); |
| 3365 | |
| 3366 | if (ha->async_pd) |
| 3367 | dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); |
| 3368 | |
| 3369 | if (ha->s_dma_pool) |
| 3370 | dma_pool_destroy(ha->s_dma_pool); |
| 3371 | |
| 3372 | if (ha->gid_list) |
| 3373 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), |
| 3374 | ha->gid_list, ha->gid_list_dma); |
| 3375 | |
| 3376 | if (IS_QLA82XX(ha)) { |
| 3377 | if (!list_empty(&ha->gbl_dsd_list)) { |
| 3378 | struct dsd_dma *dsd_ptr, *tdsd_ptr; |
| 3379 | |
| 3380 | /* clean up allocated prev pool */ |
| 3381 | list_for_each_entry_safe(dsd_ptr, |
| 3382 | tdsd_ptr, &ha->gbl_dsd_list, list) { |
| 3383 | dma_pool_free(ha->dl_dma_pool, |
| 3384 | dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); |
| 3385 | list_del(&dsd_ptr->list); |
| 3386 | kfree(dsd_ptr); |
| 3387 | } |
| 3388 | } |
| 3389 | } |
| 3390 | |
| 3391 | if (ha->dl_dma_pool) |
| 3392 | dma_pool_destroy(ha->dl_dma_pool); |
| 3393 | |
| 3394 | if (ha->fcp_cmnd_dma_pool) |
| 3395 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); |
| 3396 | |
| 3397 | if (ha->ctx_mempool) |
| 3398 | mempool_destroy(ha->ctx_mempool); |
| 3399 | |
| 3400 | qlt_mem_free(ha); |
| 3401 | |
| 3402 | if (ha->init_cb) |
| 3403 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, |
| 3404 | ha->init_cb, ha->init_cb_dma); |
| 3405 | vfree(ha->optrom_buffer); |
| 3406 | kfree(ha->nvram); |
| 3407 | kfree(ha->npiv_info); |
| 3408 | kfree(ha->swl); |
| 3409 | kfree(ha->loop_id_map); |
| 3410 | |
| 3411 | ha->srb_mempool = NULL; |
| 3412 | ha->ctx_mempool = NULL; |
| 3413 | ha->sns_cmd = NULL; |
| 3414 | ha->sns_cmd_dma = 0; |
| 3415 | ha->ct_sns = NULL; |
| 3416 | ha->ct_sns_dma = 0; |
| 3417 | ha->ms_iocb = NULL; |
| 3418 | ha->ms_iocb_dma = 0; |
| 3419 | ha->init_cb = NULL; |
| 3420 | ha->init_cb_dma = 0; |
| 3421 | ha->ex_init_cb = NULL; |
| 3422 | ha->ex_init_cb_dma = 0; |
| 3423 | ha->async_pd = NULL; |
| 3424 | ha->async_pd_dma = 0; |
| 3425 | |
| 3426 | ha->s_dma_pool = NULL; |
| 3427 | ha->dl_dma_pool = NULL; |
| 3428 | ha->fcp_cmnd_dma_pool = NULL; |
| 3429 | |
| 3430 | ha->gid_list = NULL; |
| 3431 | ha->gid_list_dma = 0; |
| 3432 | |
| 3433 | ha->tgt.atio_ring = NULL; |
| 3434 | ha->tgt.atio_dma = 0; |
| 3435 | ha->tgt.tgt_vp_map = NULL; |
| 3436 | } |
| 3437 | |
| 3438 | struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, |
| 3439 | struct qla_hw_data *ha) |
| 3440 | { |
| 3441 | struct Scsi_Host *host; |
| 3442 | struct scsi_qla_host *vha = NULL; |
| 3443 | |
| 3444 | host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); |
| 3445 | if (host == NULL) { |
| 3446 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, |
| 3447 | "Failed to allocate host from the scsi layer, aborting.\n"); |
| 3448 | goto fail; |
| 3449 | } |
| 3450 | |
| 3451 | /* Clear our data area */ |
| 3452 | vha = shost_priv(host); |
| 3453 | memset(vha, 0, sizeof(scsi_qla_host_t)); |
| 3454 | |
| 3455 | vha->host = host; |
| 3456 | vha->host_no = host->host_no; |
| 3457 | vha->hw = ha; |
| 3458 | |
| 3459 | INIT_LIST_HEAD(&vha->vp_fcports); |
| 3460 | INIT_LIST_HEAD(&vha->work_list); |
| 3461 | INIT_LIST_HEAD(&vha->list); |
| 3462 | |
| 3463 | spin_lock_init(&vha->work_lock); |
| 3464 | |
| 3465 | sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); |
| 3466 | ql_dbg(ql_dbg_init, vha, 0x0041, |
| 3467 | "Allocated the host=%p hw=%p vha=%p dev_name=%s", |
| 3468 | vha->host, vha->hw, vha, |
| 3469 | dev_name(&(ha->pdev->dev))); |
| 3470 | |
| 3471 | return vha; |
| 3472 | |
| 3473 | fail: |
| 3474 | return vha; |
| 3475 | } |
| 3476 | |
| 3477 | static struct qla_work_evt * |
| 3478 | qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) |
| 3479 | { |
| 3480 | struct qla_work_evt *e; |
| 3481 | uint8_t bail; |
| 3482 | |
| 3483 | QLA_VHA_MARK_BUSY(vha, bail); |
| 3484 | if (bail) |
| 3485 | return NULL; |
| 3486 | |
| 3487 | e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); |
| 3488 | if (!e) { |
| 3489 | QLA_VHA_MARK_NOT_BUSY(vha); |
| 3490 | return NULL; |
| 3491 | } |
| 3492 | |
| 3493 | INIT_LIST_HEAD(&e->list); |
| 3494 | e->type = type; |
| 3495 | e->flags = QLA_EVT_FLAG_FREE; |
| 3496 | return e; |
| 3497 | } |
| 3498 | |
| 3499 | static int |
| 3500 | qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) |
| 3501 | { |
| 3502 | unsigned long flags; |
| 3503 | |
| 3504 | spin_lock_irqsave(&vha->work_lock, flags); |
| 3505 | list_add_tail(&e->list, &vha->work_list); |
| 3506 | spin_unlock_irqrestore(&vha->work_lock, flags); |
| 3507 | qla2xxx_wake_dpc(vha); |
| 3508 | |
| 3509 | return QLA_SUCCESS; |
| 3510 | } |
| 3511 | |
| 3512 | int |
| 3513 | qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, |
| 3514 | u32 data) |
| 3515 | { |
| 3516 | struct qla_work_evt *e; |
| 3517 | |
| 3518 | e = qla2x00_alloc_work(vha, QLA_EVT_AEN); |
| 3519 | if (!e) |
| 3520 | return QLA_FUNCTION_FAILED; |
| 3521 | |
| 3522 | e->u.aen.code = code; |
| 3523 | e->u.aen.data = data; |
| 3524 | return qla2x00_post_work(vha, e); |
| 3525 | } |
| 3526 | |
| 3527 | int |
| 3528 | qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) |
| 3529 | { |
| 3530 | struct qla_work_evt *e; |
| 3531 | |
| 3532 | e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); |
| 3533 | if (!e) |
| 3534 | return QLA_FUNCTION_FAILED; |
| 3535 | |
| 3536 | memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); |
| 3537 | return qla2x00_post_work(vha, e); |
| 3538 | } |
| 3539 | |
| 3540 | #define qla2x00_post_async_work(name, type) \ |
| 3541 | int qla2x00_post_async_##name##_work( \ |
| 3542 | struct scsi_qla_host *vha, \ |
| 3543 | fc_port_t *fcport, uint16_t *data) \ |
| 3544 | { \ |
| 3545 | struct qla_work_evt *e; \ |
| 3546 | \ |
| 3547 | e = qla2x00_alloc_work(vha, type); \ |
| 3548 | if (!e) \ |
| 3549 | return QLA_FUNCTION_FAILED; \ |
| 3550 | \ |
| 3551 | e->u.logio.fcport = fcport; \ |
| 3552 | if (data) { \ |
| 3553 | e->u.logio.data[0] = data[0]; \ |
| 3554 | e->u.logio.data[1] = data[1]; \ |
| 3555 | } \ |
| 3556 | return qla2x00_post_work(vha, e); \ |
| 3557 | } |
| 3558 | |
| 3559 | qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); |
| 3560 | qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); |
| 3561 | qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); |
| 3562 | qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); |
| 3563 | qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); |
| 3564 | qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); |
| 3565 | |
| 3566 | int |
| 3567 | qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) |
| 3568 | { |
| 3569 | struct qla_work_evt *e; |
| 3570 | |
| 3571 | e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); |
| 3572 | if (!e) |
| 3573 | return QLA_FUNCTION_FAILED; |
| 3574 | |
| 3575 | e->u.uevent.code = code; |
| 3576 | return qla2x00_post_work(vha, e); |
| 3577 | } |
| 3578 | |
| 3579 | static void |
| 3580 | qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) |
| 3581 | { |
| 3582 | char event_string[40]; |
| 3583 | char *envp[] = { event_string, NULL }; |
| 3584 | |
| 3585 | switch (code) { |
| 3586 | case QLA_UEVENT_CODE_FW_DUMP: |
| 3587 | snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", |
| 3588 | vha->host_no); |
| 3589 | break; |
| 3590 | default: |
| 3591 | /* do nothing */ |
| 3592 | break; |
| 3593 | } |
| 3594 | kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); |
| 3595 | } |
| 3596 | |
| 3597 | void |
| 3598 | qla2x00_do_work(struct scsi_qla_host *vha) |
| 3599 | { |
| 3600 | struct qla_work_evt *e, *tmp; |
| 3601 | unsigned long flags; |
| 3602 | LIST_HEAD(work); |
| 3603 | |
| 3604 | spin_lock_irqsave(&vha->work_lock, flags); |
| 3605 | list_splice_init(&vha->work_list, &work); |
| 3606 | spin_unlock_irqrestore(&vha->work_lock, flags); |
| 3607 | |
| 3608 | list_for_each_entry_safe(e, tmp, &work, list) { |
| 3609 | list_del_init(&e->list); |
| 3610 | |
| 3611 | switch (e->type) { |
| 3612 | case QLA_EVT_AEN: |
| 3613 | fc_host_post_event(vha->host, fc_get_event_number(), |
| 3614 | e->u.aen.code, e->u.aen.data); |
| 3615 | break; |
| 3616 | case QLA_EVT_IDC_ACK: |
| 3617 | qla81xx_idc_ack(vha, e->u.idc_ack.mb); |
| 3618 | break; |
| 3619 | case QLA_EVT_ASYNC_LOGIN: |
| 3620 | qla2x00_async_login(vha, e->u.logio.fcport, |
| 3621 | e->u.logio.data); |
| 3622 | break; |
| 3623 | case QLA_EVT_ASYNC_LOGIN_DONE: |
| 3624 | qla2x00_async_login_done(vha, e->u.logio.fcport, |
| 3625 | e->u.logio.data); |
| 3626 | break; |
| 3627 | case QLA_EVT_ASYNC_LOGOUT: |
| 3628 | qla2x00_async_logout(vha, e->u.logio.fcport); |
| 3629 | break; |
| 3630 | case QLA_EVT_ASYNC_LOGOUT_DONE: |
| 3631 | qla2x00_async_logout_done(vha, e->u.logio.fcport, |
| 3632 | e->u.logio.data); |
| 3633 | break; |
| 3634 | case QLA_EVT_ASYNC_ADISC: |
| 3635 | qla2x00_async_adisc(vha, e->u.logio.fcport, |
| 3636 | e->u.logio.data); |
| 3637 | break; |
| 3638 | case QLA_EVT_ASYNC_ADISC_DONE: |
| 3639 | qla2x00_async_adisc_done(vha, e->u.logio.fcport, |
| 3640 | e->u.logio.data); |
| 3641 | break; |
| 3642 | case QLA_EVT_UEVENT: |
| 3643 | qla2x00_uevent_emit(vha, e->u.uevent.code); |
| 3644 | break; |
| 3645 | } |
| 3646 | if (e->flags & QLA_EVT_FLAG_FREE) |
| 3647 | kfree(e); |
| 3648 | |
| 3649 | /* For each work completed decrement vha ref count */ |
| 3650 | QLA_VHA_MARK_NOT_BUSY(vha); |
| 3651 | } |
| 3652 | } |
| 3653 | |
| 3654 | /* Relogins all the fcports of a vport |
| 3655 | * Context: dpc thread |
| 3656 | */ |
| 3657 | void qla2x00_relogin(struct scsi_qla_host *vha) |
| 3658 | { |
| 3659 | fc_port_t *fcport; |
| 3660 | int status; |
| 3661 | uint16_t next_loopid = 0; |
| 3662 | struct qla_hw_data *ha = vha->hw; |
| 3663 | uint16_t data[2]; |
| 3664 | |
| 3665 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
| 3666 | /* |
| 3667 | * If the port is not ONLINE then try to login |
| 3668 | * to it if we haven't run out of retries. |
| 3669 | */ |
| 3670 | if (atomic_read(&fcport->state) != FCS_ONLINE && |
| 3671 | fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { |
| 3672 | fcport->login_retry--; |
| 3673 | if (fcport->flags & FCF_FABRIC_DEVICE) { |
| 3674 | if (fcport->flags & FCF_FCP2_DEVICE) |
| 3675 | ha->isp_ops->fabric_logout(vha, |
| 3676 | fcport->loop_id, |
| 3677 | fcport->d_id.b.domain, |
| 3678 | fcport->d_id.b.area, |
| 3679 | fcport->d_id.b.al_pa); |
| 3680 | |
| 3681 | if (fcport->loop_id == FC_NO_LOOP_ID) { |
| 3682 | fcport->loop_id = next_loopid = |
| 3683 | ha->min_external_loopid; |
| 3684 | status = qla2x00_find_new_loop_id( |
| 3685 | vha, fcport); |
| 3686 | if (status != QLA_SUCCESS) { |
| 3687 | /* Ran out of IDs to use */ |
| 3688 | break; |
| 3689 | } |
| 3690 | } |
| 3691 | |
| 3692 | if (IS_ALOGIO_CAPABLE(ha)) { |
| 3693 | fcport->flags |= FCF_ASYNC_SENT; |
| 3694 | data[0] = 0; |
| 3695 | data[1] = QLA_LOGIO_LOGIN_RETRIED; |
| 3696 | status = qla2x00_post_async_login_work( |
| 3697 | vha, fcport, data); |
| 3698 | if (status == QLA_SUCCESS) |
| 3699 | continue; |
| 3700 | /* Attempt a retry. */ |
| 3701 | status = 1; |
| 3702 | } else { |
| 3703 | status = qla2x00_fabric_login(vha, |
| 3704 | fcport, &next_loopid); |
| 3705 | if (status == QLA_SUCCESS) { |
| 3706 | int status2; |
| 3707 | uint8_t opts; |
| 3708 | |
| 3709 | opts = 0; |
| 3710 | if (fcport->flags & |
| 3711 | FCF_FCP2_DEVICE) |
| 3712 | opts |= BIT_1; |
| 3713 | status2 = |
| 3714 | qla2x00_get_port_database( |
| 3715 | vha, fcport, |
| 3716 | opts); |
| 3717 | if (status2 != QLA_SUCCESS) |
| 3718 | status = 1; |
| 3719 | } |
| 3720 | } |
| 3721 | } else |
| 3722 | status = qla2x00_local_device_login(vha, |
| 3723 | fcport); |
| 3724 | |
| 3725 | if (status == QLA_SUCCESS) { |
| 3726 | fcport->old_loop_id = fcport->loop_id; |
| 3727 | |
| 3728 | ql_dbg(ql_dbg_disc, vha, 0x2003, |
| 3729 | "Port login OK: logged in ID 0x%x.\n", |
| 3730 | fcport->loop_id); |
| 3731 | |
| 3732 | qla2x00_update_fcport(vha, fcport); |
| 3733 | |
| 3734 | } else if (status == 1) { |
| 3735 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); |
| 3736 | /* retry the login again */ |
| 3737 | ql_dbg(ql_dbg_disc, vha, 0x2007, |
| 3738 | "Retrying %d login again loop_id 0x%x.\n", |
| 3739 | fcport->login_retry, fcport->loop_id); |
| 3740 | } else { |
| 3741 | fcport->login_retry = 0; |
| 3742 | } |
| 3743 | |
| 3744 | if (fcport->login_retry == 0 && status != QLA_SUCCESS) |
| 3745 | qla2x00_clear_loop_id(fcport); |
| 3746 | } |
| 3747 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) |
| 3748 | break; |
| 3749 | } |
| 3750 | } |
| 3751 | |
| 3752 | /* Schedule work on any of the dpc-workqueues */ |
| 3753 | void |
| 3754 | qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) |
| 3755 | { |
| 3756 | struct qla_hw_data *ha = base_vha->hw; |
| 3757 | |
| 3758 | switch (work_code) { |
| 3759 | case MBA_IDC_AEN: /* 0x8200 */ |
| 3760 | if (ha->dpc_lp_wq) |
| 3761 | queue_work(ha->dpc_lp_wq, &ha->idc_aen); |
| 3762 | break; |
| 3763 | |
| 3764 | case QLA83XX_NIC_CORE_RESET: /* 0x1 */ |
| 3765 | if (!ha->flags.nic_core_reset_hdlr_active) { |
| 3766 | if (ha->dpc_hp_wq) |
| 3767 | queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); |
| 3768 | } else |
| 3769 | ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, |
| 3770 | "NIC Core reset is already active. Skip " |
| 3771 | "scheduling it again.\n"); |
| 3772 | break; |
| 3773 | case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ |
| 3774 | if (ha->dpc_hp_wq) |
| 3775 | queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); |
| 3776 | break; |
| 3777 | case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ |
| 3778 | if (ha->dpc_hp_wq) |
| 3779 | queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); |
| 3780 | break; |
| 3781 | default: |
| 3782 | ql_log(ql_log_warn, base_vha, 0xb05f, |
| 3783 | "Unknow work-code=0x%x.\n", work_code); |
| 3784 | } |
| 3785 | |
| 3786 | return; |
| 3787 | } |
| 3788 | |
| 3789 | /* Work: Perform NIC Core Unrecoverable state handling */ |
| 3790 | void |
| 3791 | qla83xx_nic_core_unrecoverable_work(struct work_struct *work) |
| 3792 | { |
| 3793 | struct qla_hw_data *ha = |
| 3794 | container_of(work, struct qla_hw_data, nic_core_reset); |
| 3795 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
| 3796 | uint32_t dev_state = 0; |
| 3797 | |
| 3798 | qla83xx_idc_lock(base_vha, 0); |
| 3799 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); |
| 3800 | qla83xx_reset_ownership(base_vha); |
| 3801 | if (ha->flags.nic_core_reset_owner) { |
| 3802 | ha->flags.nic_core_reset_owner = 0; |
| 3803 | qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, |
| 3804 | QLA8XXX_DEV_FAILED); |
| 3805 | ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); |
| 3806 | qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); |
| 3807 | } |
| 3808 | qla83xx_idc_unlock(base_vha, 0); |
| 3809 | } |
| 3810 | |
| 3811 | /* Work: Execute IDC state handler */ |
| 3812 | void |
| 3813 | qla83xx_idc_state_handler_work(struct work_struct *work) |
| 3814 | { |
| 3815 | struct qla_hw_data *ha = |
| 3816 | container_of(work, struct qla_hw_data, nic_core_reset); |
| 3817 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
| 3818 | uint32_t dev_state = 0; |
| 3819 | |
| 3820 | qla83xx_idc_lock(base_vha, 0); |
| 3821 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); |
| 3822 | if (dev_state == QLA8XXX_DEV_FAILED || |
| 3823 | dev_state == QLA8XXX_DEV_NEED_QUIESCENT) |
| 3824 | qla83xx_idc_state_handler(base_vha); |
| 3825 | qla83xx_idc_unlock(base_vha, 0); |
| 3826 | } |
| 3827 | |
| 3828 | int |
| 3829 | qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) |
| 3830 | { |
| 3831 | int rval = QLA_SUCCESS; |
| 3832 | unsigned long heart_beat_wait = jiffies + (1 * HZ); |
| 3833 | uint32_t heart_beat_counter1, heart_beat_counter2; |
| 3834 | |
| 3835 | do { |
| 3836 | if (time_after(jiffies, heart_beat_wait)) { |
| 3837 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, |
| 3838 | "Nic Core f/w is not alive.\n"); |
| 3839 | rval = QLA_FUNCTION_FAILED; |
| 3840 | break; |
| 3841 | } |
| 3842 | |
| 3843 | qla83xx_idc_lock(base_vha, 0); |
| 3844 | qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, |
| 3845 | &heart_beat_counter1); |
| 3846 | qla83xx_idc_unlock(base_vha, 0); |
| 3847 | msleep(100); |
| 3848 | qla83xx_idc_lock(base_vha, 0); |
| 3849 | qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, |
| 3850 | &heart_beat_counter2); |
| 3851 | qla83xx_idc_unlock(base_vha, 0); |
| 3852 | } while (heart_beat_counter1 == heart_beat_counter2); |
| 3853 | |
| 3854 | return rval; |
| 3855 | } |
| 3856 | |
| 3857 | /* Work: Perform NIC Core Reset handling */ |
| 3858 | void |
| 3859 | qla83xx_nic_core_reset_work(struct work_struct *work) |
| 3860 | { |
| 3861 | struct qla_hw_data *ha = |
| 3862 | container_of(work, struct qla_hw_data, nic_core_reset); |
| 3863 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
| 3864 | uint32_t dev_state = 0; |
| 3865 | |
| 3866 | if (IS_QLA2031(ha)) { |
| 3867 | if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) |
| 3868 | ql_log(ql_log_warn, base_vha, 0xb081, |
| 3869 | "Failed to dump mctp\n"); |
| 3870 | return; |
| 3871 | } |
| 3872 | |
| 3873 | if (!ha->flags.nic_core_reset_hdlr_active) { |
| 3874 | if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { |
| 3875 | qla83xx_idc_lock(base_vha, 0); |
| 3876 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, |
| 3877 | &dev_state); |
| 3878 | qla83xx_idc_unlock(base_vha, 0); |
| 3879 | if (dev_state != QLA8XXX_DEV_NEED_RESET) { |
| 3880 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, |
| 3881 | "Nic Core f/w is alive.\n"); |
| 3882 | return; |
| 3883 | } |
| 3884 | } |
| 3885 | |
| 3886 | ha->flags.nic_core_reset_hdlr_active = 1; |
| 3887 | if (qla83xx_nic_core_reset(base_vha)) { |
| 3888 | /* NIC Core reset failed. */ |
| 3889 | ql_dbg(ql_dbg_p3p, base_vha, 0xb061, |
| 3890 | "NIC Core reset failed.\n"); |
| 3891 | } |
| 3892 | ha->flags.nic_core_reset_hdlr_active = 0; |
| 3893 | } |
| 3894 | } |
| 3895 | |
| 3896 | /* Work: Handle 8200 IDC aens */ |
| 3897 | void |
| 3898 | qla83xx_service_idc_aen(struct work_struct *work) |
| 3899 | { |
| 3900 | struct qla_hw_data *ha = |
| 3901 | container_of(work, struct qla_hw_data, idc_aen); |
| 3902 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
| 3903 | uint32_t dev_state, idc_control; |
| 3904 | |
| 3905 | qla83xx_idc_lock(base_vha, 0); |
| 3906 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); |
| 3907 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); |
| 3908 | qla83xx_idc_unlock(base_vha, 0); |
| 3909 | if (dev_state == QLA8XXX_DEV_NEED_RESET) { |
| 3910 | if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { |
| 3911 | ql_dbg(ql_dbg_p3p, base_vha, 0xb062, |
| 3912 | "Application requested NIC Core Reset.\n"); |
| 3913 | qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); |
| 3914 | } else if (qla83xx_check_nic_core_fw_alive(base_vha) == |
| 3915 | QLA_SUCCESS) { |
| 3916 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, |
| 3917 | "Other protocol driver requested NIC Core Reset.\n"); |
| 3918 | qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); |
| 3919 | } |
| 3920 | } else if (dev_state == QLA8XXX_DEV_FAILED || |
| 3921 | dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { |
| 3922 | qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); |
| 3923 | } |
| 3924 | } |
| 3925 | |
| 3926 | static void |
| 3927 | qla83xx_wait_logic(void) |
| 3928 | { |
| 3929 | int i; |
| 3930 | |
| 3931 | /* Yield CPU */ |
| 3932 | if (!in_interrupt()) { |
| 3933 | /* |
| 3934 | * Wait about 200ms before retrying again. |
| 3935 | * This controls the number of retries for single |
| 3936 | * lock operation. |
| 3937 | */ |
| 3938 | msleep(100); |
| 3939 | schedule(); |
| 3940 | } else { |
| 3941 | for (i = 0; i < 20; i++) |
| 3942 | cpu_relax(); /* This a nop instr on i386 */ |
| 3943 | } |
| 3944 | } |
| 3945 | |
| 3946 | int |
| 3947 | qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) |
| 3948 | { |
| 3949 | int rval; |
| 3950 | uint32_t data; |
| 3951 | uint32_t idc_lck_rcvry_stage_mask = 0x3; |
| 3952 | uint32_t idc_lck_rcvry_owner_mask = 0x3c; |
| 3953 | struct qla_hw_data *ha = base_vha->hw; |
| 3954 | |
| 3955 | rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); |
| 3956 | if (rval) |
| 3957 | return rval; |
| 3958 | |
| 3959 | if ((data & idc_lck_rcvry_stage_mask) > 0) { |
| 3960 | return QLA_SUCCESS; |
| 3961 | } else { |
| 3962 | data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); |
| 3963 | rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, |
| 3964 | data); |
| 3965 | if (rval) |
| 3966 | return rval; |
| 3967 | |
| 3968 | msleep(200); |
| 3969 | |
| 3970 | rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, |
| 3971 | &data); |
| 3972 | if (rval) |
| 3973 | return rval; |
| 3974 | |
| 3975 | if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { |
| 3976 | data &= (IDC_LOCK_RECOVERY_STAGE2 | |
| 3977 | ~(idc_lck_rcvry_stage_mask)); |
| 3978 | rval = qla83xx_wr_reg(base_vha, |
| 3979 | QLA83XX_IDC_LOCK_RECOVERY, data); |
| 3980 | if (rval) |
| 3981 | return rval; |
| 3982 | |
| 3983 | /* Forcefully perform IDC UnLock */ |
| 3984 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, |
| 3985 | &data); |
| 3986 | if (rval) |
| 3987 | return rval; |
| 3988 | /* Clear lock-id by setting 0xff */ |
| 3989 | rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, |
| 3990 | 0xff); |
| 3991 | if (rval) |
| 3992 | return rval; |
| 3993 | /* Clear lock-recovery by setting 0x0 */ |
| 3994 | rval = qla83xx_wr_reg(base_vha, |
| 3995 | QLA83XX_IDC_LOCK_RECOVERY, 0x0); |
| 3996 | if (rval) |
| 3997 | return rval; |
| 3998 | } else |
| 3999 | return QLA_SUCCESS; |
| 4000 | } |
| 4001 | |
| 4002 | return rval; |
| 4003 | } |
| 4004 | |
| 4005 | int |
| 4006 | qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) |
| 4007 | { |
| 4008 | int rval = QLA_SUCCESS; |
| 4009 | uint32_t o_drv_lockid, n_drv_lockid; |
| 4010 | unsigned long lock_recovery_timeout; |
| 4011 | |
| 4012 | lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; |
| 4013 | retry_lockid: |
| 4014 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); |
| 4015 | if (rval) |
| 4016 | goto exit; |
| 4017 | |
| 4018 | /* MAX wait time before forcing IDC Lock recovery = 2 secs */ |
| 4019 | if (time_after_eq(jiffies, lock_recovery_timeout)) { |
| 4020 | if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) |
| 4021 | return QLA_SUCCESS; |
| 4022 | else |
| 4023 | return QLA_FUNCTION_FAILED; |
| 4024 | } |
| 4025 | |
| 4026 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); |
| 4027 | if (rval) |
| 4028 | goto exit; |
| 4029 | |
| 4030 | if (o_drv_lockid == n_drv_lockid) { |
| 4031 | qla83xx_wait_logic(); |
| 4032 | goto retry_lockid; |
| 4033 | } else |
| 4034 | return QLA_SUCCESS; |
| 4035 | |
| 4036 | exit: |
| 4037 | return rval; |
| 4038 | } |
| 4039 | |
| 4040 | void |
| 4041 | qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) |
| 4042 | { |
| 4043 | uint16_t options = (requester_id << 15) | BIT_6; |
| 4044 | uint32_t data; |
| 4045 | struct qla_hw_data *ha = base_vha->hw; |
| 4046 | |
| 4047 | /* IDC-lock implementation using driver-lock/lock-id remote registers */ |
| 4048 | retry_lock: |
| 4049 | if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) |
| 4050 | == QLA_SUCCESS) { |
| 4051 | if (data) { |
| 4052 | /* Setting lock-id to our function-number */ |
| 4053 | qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, |
| 4054 | ha->portnum); |
| 4055 | } else { |
| 4056 | ql_dbg(ql_dbg_p3p, base_vha, 0xb063, |
| 4057 | "Failed to acquire IDC lock. retrying...\n"); |
| 4058 | |
| 4059 | /* Retry/Perform IDC-Lock recovery */ |
| 4060 | if (qla83xx_idc_lock_recovery(base_vha) |
| 4061 | == QLA_SUCCESS) { |
| 4062 | qla83xx_wait_logic(); |
| 4063 | goto retry_lock; |
| 4064 | } else |
| 4065 | ql_log(ql_log_warn, base_vha, 0xb075, |
| 4066 | "IDC Lock recovery FAILED.\n"); |
| 4067 | } |
| 4068 | |
| 4069 | } |
| 4070 | |
| 4071 | return; |
| 4072 | |
| 4073 | /* XXX: IDC-lock implementation using access-control mbx */ |
| 4074 | retry_lock2: |
| 4075 | if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { |
| 4076 | ql_dbg(ql_dbg_p3p, base_vha, 0xb072, |
| 4077 | "Failed to acquire IDC lock. retrying...\n"); |
| 4078 | /* Retry/Perform IDC-Lock recovery */ |
| 4079 | if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { |
| 4080 | qla83xx_wait_logic(); |
| 4081 | goto retry_lock2; |
| 4082 | } else |
| 4083 | ql_log(ql_log_warn, base_vha, 0xb076, |
| 4084 | "IDC Lock recovery FAILED.\n"); |
| 4085 | } |
| 4086 | |
| 4087 | return; |
| 4088 | } |
| 4089 | |
| 4090 | void |
| 4091 | qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) |
| 4092 | { |
| 4093 | uint16_t options = (requester_id << 15) | BIT_7, retry; |
| 4094 | uint32_t data; |
| 4095 | struct qla_hw_data *ha = base_vha->hw; |
| 4096 | |
| 4097 | /* IDC-unlock implementation using driver-unlock/lock-id |
| 4098 | * remote registers |
| 4099 | */ |
| 4100 | retry = 0; |
| 4101 | retry_unlock: |
| 4102 | if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) |
| 4103 | == QLA_SUCCESS) { |
| 4104 | if (data == ha->portnum) { |
| 4105 | qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); |
| 4106 | /* Clearing lock-id by setting 0xff */ |
| 4107 | qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); |
| 4108 | } else if (retry < 10) { |
| 4109 | /* SV: XXX: IDC unlock retrying needed here? */ |
| 4110 | |
| 4111 | /* Retry for IDC-unlock */ |
| 4112 | qla83xx_wait_logic(); |
| 4113 | retry++; |
| 4114 | ql_dbg(ql_dbg_p3p, base_vha, 0xb064, |
| 4115 | "Failed to release IDC lock, retyring=%d\n", retry); |
| 4116 | goto retry_unlock; |
| 4117 | } |
| 4118 | } else if (retry < 10) { |
| 4119 | /* Retry for IDC-unlock */ |
| 4120 | qla83xx_wait_logic(); |
| 4121 | retry++; |
| 4122 | ql_dbg(ql_dbg_p3p, base_vha, 0xb065, |
| 4123 | "Failed to read drv-lockid, retyring=%d\n", retry); |
| 4124 | goto retry_unlock; |
| 4125 | } |
| 4126 | |
| 4127 | return; |
| 4128 | |
| 4129 | /* XXX: IDC-unlock implementation using access-control mbx */ |
| 4130 | retry = 0; |
| 4131 | retry_unlock2: |
| 4132 | if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { |
| 4133 | if (retry < 10) { |
| 4134 | /* Retry for IDC-unlock */ |
| 4135 | qla83xx_wait_logic(); |
| 4136 | retry++; |
| 4137 | ql_dbg(ql_dbg_p3p, base_vha, 0xb066, |
| 4138 | "Failed to release IDC lock, retyring=%d\n", retry); |
| 4139 | goto retry_unlock2; |
| 4140 | } |
| 4141 | } |
| 4142 | |
| 4143 | return; |
| 4144 | } |
| 4145 | |
| 4146 | int |
| 4147 | __qla83xx_set_drv_presence(scsi_qla_host_t *vha) |
| 4148 | { |
| 4149 | int rval = QLA_SUCCESS; |
| 4150 | struct qla_hw_data *ha = vha->hw; |
| 4151 | uint32_t drv_presence; |
| 4152 | |
| 4153 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); |
| 4154 | if (rval == QLA_SUCCESS) { |
| 4155 | drv_presence |= (1 << ha->portnum); |
| 4156 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, |
| 4157 | drv_presence); |
| 4158 | } |
| 4159 | |
| 4160 | return rval; |
| 4161 | } |
| 4162 | |
| 4163 | int |
| 4164 | qla83xx_set_drv_presence(scsi_qla_host_t *vha) |
| 4165 | { |
| 4166 | int rval = QLA_SUCCESS; |
| 4167 | |
| 4168 | qla83xx_idc_lock(vha, 0); |
| 4169 | rval = __qla83xx_set_drv_presence(vha); |
| 4170 | qla83xx_idc_unlock(vha, 0); |
| 4171 | |
| 4172 | return rval; |
| 4173 | } |
| 4174 | |
| 4175 | int |
| 4176 | __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) |
| 4177 | { |
| 4178 | int rval = QLA_SUCCESS; |
| 4179 | struct qla_hw_data *ha = vha->hw; |
| 4180 | uint32_t drv_presence; |
| 4181 | |
| 4182 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); |
| 4183 | if (rval == QLA_SUCCESS) { |
| 4184 | drv_presence &= ~(1 << ha->portnum); |
| 4185 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, |
| 4186 | drv_presence); |
| 4187 | } |
| 4188 | |
| 4189 | return rval; |
| 4190 | } |
| 4191 | |
| 4192 | int |
| 4193 | qla83xx_clear_drv_presence(scsi_qla_host_t *vha) |
| 4194 | { |
| 4195 | int rval = QLA_SUCCESS; |
| 4196 | |
| 4197 | qla83xx_idc_lock(vha, 0); |
| 4198 | rval = __qla83xx_clear_drv_presence(vha); |
| 4199 | qla83xx_idc_unlock(vha, 0); |
| 4200 | |
| 4201 | return rval; |
| 4202 | } |
| 4203 | |
| 4204 | void |
| 4205 | qla83xx_need_reset_handler(scsi_qla_host_t *vha) |
| 4206 | { |
| 4207 | struct qla_hw_data *ha = vha->hw; |
| 4208 | uint32_t drv_ack, drv_presence; |
| 4209 | unsigned long ack_timeout; |
| 4210 | |
| 4211 | /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ |
| 4212 | ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); |
| 4213 | while (1) { |
| 4214 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); |
| 4215 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); |
| 4216 | if (drv_ack == drv_presence) |
| 4217 | break; |
| 4218 | |
| 4219 | if (time_after_eq(jiffies, ack_timeout)) { |
| 4220 | ql_log(ql_log_warn, vha, 0xb067, |
| 4221 | "RESET ACK TIMEOUT! drv_presence=0x%x " |
| 4222 | "drv_ack=0x%x\n", drv_presence, drv_ack); |
| 4223 | /* |
| 4224 | * The function(s) which did not ack in time are forced |
| 4225 | * to withdraw any further participation in the IDC |
| 4226 | * reset. |
| 4227 | */ |
| 4228 | if (drv_ack != drv_presence) |
| 4229 | qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, |
| 4230 | drv_ack); |
| 4231 | break; |
| 4232 | } |
| 4233 | |
| 4234 | qla83xx_idc_unlock(vha, 0); |
| 4235 | msleep(1000); |
| 4236 | qla83xx_idc_lock(vha, 0); |
| 4237 | } |
| 4238 | |
| 4239 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); |
| 4240 | ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); |
| 4241 | } |
| 4242 | |
| 4243 | int |
| 4244 | qla83xx_device_bootstrap(scsi_qla_host_t *vha) |
| 4245 | { |
| 4246 | int rval = QLA_SUCCESS; |
| 4247 | uint32_t idc_control; |
| 4248 | |
| 4249 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); |
| 4250 | ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); |
| 4251 | |
| 4252 | /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ |
| 4253 | __qla83xx_get_idc_control(vha, &idc_control); |
| 4254 | idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; |
| 4255 | __qla83xx_set_idc_control(vha, 0); |
| 4256 | |
| 4257 | qla83xx_idc_unlock(vha, 0); |
| 4258 | rval = qla83xx_restart_nic_firmware(vha); |
| 4259 | qla83xx_idc_lock(vha, 0); |
| 4260 | |
| 4261 | if (rval != QLA_SUCCESS) { |
| 4262 | ql_log(ql_log_fatal, vha, 0xb06a, |
| 4263 | "Failed to restart NIC f/w.\n"); |
| 4264 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); |
| 4265 | ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); |
| 4266 | } else { |
| 4267 | ql_dbg(ql_dbg_p3p, vha, 0xb06c, |
| 4268 | "Success in restarting nic f/w.\n"); |
| 4269 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); |
| 4270 | ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); |
| 4271 | } |
| 4272 | |
| 4273 | return rval; |
| 4274 | } |
| 4275 | |
| 4276 | /* Assumes idc_lock always held on entry */ |
| 4277 | int |
| 4278 | qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) |
| 4279 | { |
| 4280 | struct qla_hw_data *ha = base_vha->hw; |
| 4281 | int rval = QLA_SUCCESS; |
| 4282 | unsigned long dev_init_timeout; |
| 4283 | uint32_t dev_state; |
| 4284 | |
| 4285 | /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ |
| 4286 | dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); |
| 4287 | |
| 4288 | while (1) { |
| 4289 | |
| 4290 | if (time_after_eq(jiffies, dev_init_timeout)) { |
| 4291 | ql_log(ql_log_warn, base_vha, 0xb06e, |
| 4292 | "Initialization TIMEOUT!\n"); |
| 4293 | /* Init timeout. Disable further NIC Core |
| 4294 | * communication. |
| 4295 | */ |
| 4296 | qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, |
| 4297 | QLA8XXX_DEV_FAILED); |
| 4298 | ql_log(ql_log_info, base_vha, 0xb06f, |
| 4299 | "HW State: FAILED.\n"); |
| 4300 | } |
| 4301 | |
| 4302 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); |
| 4303 | switch (dev_state) { |
| 4304 | case QLA8XXX_DEV_READY: |
| 4305 | if (ha->flags.nic_core_reset_owner) |
| 4306 | qla83xx_idc_audit(base_vha, |
| 4307 | IDC_AUDIT_COMPLETION); |
| 4308 | ha->flags.nic_core_reset_owner = 0; |
| 4309 | ql_dbg(ql_dbg_p3p, base_vha, 0xb070, |
| 4310 | "Reset_owner reset by 0x%x.\n", |
| 4311 | ha->portnum); |
| 4312 | goto exit; |
| 4313 | case QLA8XXX_DEV_COLD: |
| 4314 | if (ha->flags.nic_core_reset_owner) |
| 4315 | rval = qla83xx_device_bootstrap(base_vha); |
| 4316 | else { |
| 4317 | /* Wait for AEN to change device-state */ |
| 4318 | qla83xx_idc_unlock(base_vha, 0); |
| 4319 | msleep(1000); |
| 4320 | qla83xx_idc_lock(base_vha, 0); |
| 4321 | } |
| 4322 | break; |
| 4323 | case QLA8XXX_DEV_INITIALIZING: |
| 4324 | /* Wait for AEN to change device-state */ |
| 4325 | qla83xx_idc_unlock(base_vha, 0); |
| 4326 | msleep(1000); |
| 4327 | qla83xx_idc_lock(base_vha, 0); |
| 4328 | break; |
| 4329 | case QLA8XXX_DEV_NEED_RESET: |
| 4330 | if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) |
| 4331 | qla83xx_need_reset_handler(base_vha); |
| 4332 | else { |
| 4333 | /* Wait for AEN to change device-state */ |
| 4334 | qla83xx_idc_unlock(base_vha, 0); |
| 4335 | msleep(1000); |
| 4336 | qla83xx_idc_lock(base_vha, 0); |
| 4337 | } |
| 4338 | /* reset timeout value after need reset handler */ |
| 4339 | dev_init_timeout = jiffies + |
| 4340 | (ha->fcoe_dev_init_timeout * HZ); |
| 4341 | break; |
| 4342 | case QLA8XXX_DEV_NEED_QUIESCENT: |
| 4343 | /* XXX: DEBUG for now */ |
| 4344 | qla83xx_idc_unlock(base_vha, 0); |
| 4345 | msleep(1000); |
| 4346 | qla83xx_idc_lock(base_vha, 0); |
| 4347 | break; |
| 4348 | case QLA8XXX_DEV_QUIESCENT: |
| 4349 | /* XXX: DEBUG for now */ |
| 4350 | if (ha->flags.quiesce_owner) |
| 4351 | goto exit; |
| 4352 | |
| 4353 | qla83xx_idc_unlock(base_vha, 0); |
| 4354 | msleep(1000); |
| 4355 | qla83xx_idc_lock(base_vha, 0); |
| 4356 | dev_init_timeout = jiffies + |
| 4357 | (ha->fcoe_dev_init_timeout * HZ); |
| 4358 | break; |
| 4359 | case QLA8XXX_DEV_FAILED: |
| 4360 | if (ha->flags.nic_core_reset_owner) |
| 4361 | qla83xx_idc_audit(base_vha, |
| 4362 | IDC_AUDIT_COMPLETION); |
| 4363 | ha->flags.nic_core_reset_owner = 0; |
| 4364 | __qla83xx_clear_drv_presence(base_vha); |
| 4365 | qla83xx_idc_unlock(base_vha, 0); |
| 4366 | qla8xxx_dev_failed_handler(base_vha); |
| 4367 | rval = QLA_FUNCTION_FAILED; |
| 4368 | qla83xx_idc_lock(base_vha, 0); |
| 4369 | goto exit; |
| 4370 | case QLA8XXX_BAD_VALUE: |
| 4371 | qla83xx_idc_unlock(base_vha, 0); |
| 4372 | msleep(1000); |
| 4373 | qla83xx_idc_lock(base_vha, 0); |
| 4374 | break; |
| 4375 | default: |
| 4376 | ql_log(ql_log_warn, base_vha, 0xb071, |
| 4377 | "Unknow Device State: %x.\n", dev_state); |
| 4378 | qla83xx_idc_unlock(base_vha, 0); |
| 4379 | qla8xxx_dev_failed_handler(base_vha); |
| 4380 | rval = QLA_FUNCTION_FAILED; |
| 4381 | qla83xx_idc_lock(base_vha, 0); |
| 4382 | goto exit; |
| 4383 | } |
| 4384 | } |
| 4385 | |
| 4386 | exit: |
| 4387 | return rval; |
| 4388 | } |
| 4389 | |
| 4390 | /************************************************************************** |
| 4391 | * qla2x00_do_dpc |
| 4392 | * This kernel thread is a task that is schedule by the interrupt handler |
| 4393 | * to perform the background processing for interrupts. |
| 4394 | * |
| 4395 | * Notes: |
| 4396 | * This task always run in the context of a kernel thread. It |
| 4397 | * is kick-off by the driver's detect code and starts up |
| 4398 | * up one per adapter. It immediately goes to sleep and waits for |
| 4399 | * some fibre event. When either the interrupt handler or |
| 4400 | * the timer routine detects a event it will one of the task |
| 4401 | * bits then wake us up. |
| 4402 | **************************************************************************/ |
| 4403 | static int |
| 4404 | qla2x00_do_dpc(void *data) |
| 4405 | { |
| 4406 | int rval; |
| 4407 | scsi_qla_host_t *base_vha; |
| 4408 | struct qla_hw_data *ha; |
| 4409 | |
| 4410 | ha = (struct qla_hw_data *)data; |
| 4411 | base_vha = pci_get_drvdata(ha->pdev); |
| 4412 | |
| 4413 | set_user_nice(current, -20); |
| 4414 | |
| 4415 | set_current_state(TASK_INTERRUPTIBLE); |
| 4416 | while (!kthread_should_stop()) { |
| 4417 | ql_dbg(ql_dbg_dpc, base_vha, 0x4000, |
| 4418 | "DPC handler sleeping.\n"); |
| 4419 | |
| 4420 | schedule(); |
| 4421 | __set_current_state(TASK_RUNNING); |
| 4422 | |
| 4423 | if (!base_vha->flags.init_done || ha->flags.mbox_busy) |
| 4424 | goto end_loop; |
| 4425 | |
| 4426 | if (ha->flags.eeh_busy) { |
| 4427 | ql_dbg(ql_dbg_dpc, base_vha, 0x4003, |
| 4428 | "eeh_busy=%d.\n", ha->flags.eeh_busy); |
| 4429 | goto end_loop; |
| 4430 | } |
| 4431 | |
| 4432 | ha->dpc_active = 1; |
| 4433 | |
| 4434 | ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, |
| 4435 | "DPC handler waking up, dpc_flags=0x%lx.\n", |
| 4436 | base_vha->dpc_flags); |
| 4437 | |
| 4438 | qla2x00_do_work(base_vha); |
| 4439 | |
| 4440 | if (IS_QLA82XX(ha)) { |
| 4441 | if (test_and_clear_bit(ISP_UNRECOVERABLE, |
| 4442 | &base_vha->dpc_flags)) { |
| 4443 | qla82xx_idc_lock(ha); |
| 4444 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
| 4445 | QLA8XXX_DEV_FAILED); |
| 4446 | qla82xx_idc_unlock(ha); |
| 4447 | ql_log(ql_log_info, base_vha, 0x4004, |
| 4448 | "HW State: FAILED.\n"); |
| 4449 | qla82xx_device_state_handler(base_vha); |
| 4450 | continue; |
| 4451 | } |
| 4452 | |
| 4453 | if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, |
| 4454 | &base_vha->dpc_flags)) { |
| 4455 | |
| 4456 | ql_dbg(ql_dbg_dpc, base_vha, 0x4005, |
| 4457 | "FCoE context reset scheduled.\n"); |
| 4458 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
| 4459 | &base_vha->dpc_flags))) { |
| 4460 | if (qla82xx_fcoe_ctx_reset(base_vha)) { |
| 4461 | /* FCoE-ctx reset failed. |
| 4462 | * Escalate to chip-reset |
| 4463 | */ |
| 4464 | set_bit(ISP_ABORT_NEEDED, |
| 4465 | &base_vha->dpc_flags); |
| 4466 | } |
| 4467 | clear_bit(ABORT_ISP_ACTIVE, |
| 4468 | &base_vha->dpc_flags); |
| 4469 | } |
| 4470 | |
| 4471 | ql_dbg(ql_dbg_dpc, base_vha, 0x4006, |
| 4472 | "FCoE context reset end.\n"); |
| 4473 | } |
| 4474 | } |
| 4475 | |
| 4476 | if (test_and_clear_bit(ISP_ABORT_NEEDED, |
| 4477 | &base_vha->dpc_flags)) { |
| 4478 | |
| 4479 | ql_dbg(ql_dbg_dpc, base_vha, 0x4007, |
| 4480 | "ISP abort scheduled.\n"); |
| 4481 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
| 4482 | &base_vha->dpc_flags))) { |
| 4483 | |
| 4484 | if (ha->isp_ops->abort_isp(base_vha)) { |
| 4485 | /* failed. retry later */ |
| 4486 | set_bit(ISP_ABORT_NEEDED, |
| 4487 | &base_vha->dpc_flags); |
| 4488 | } |
| 4489 | clear_bit(ABORT_ISP_ACTIVE, |
| 4490 | &base_vha->dpc_flags); |
| 4491 | } |
| 4492 | |
| 4493 | ql_dbg(ql_dbg_dpc, base_vha, 0x4008, |
| 4494 | "ISP abort end.\n"); |
| 4495 | } |
| 4496 | |
| 4497 | if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) { |
| 4498 | qla2x00_update_fcports(base_vha); |
| 4499 | clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); |
| 4500 | } |
| 4501 | |
| 4502 | if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { |
| 4503 | int ret; |
| 4504 | ret = qla2x00_send_change_request(base_vha, 0x3, 0); |
| 4505 | if (ret != QLA_SUCCESS) |
| 4506 | ql_log(ql_log_warn, base_vha, 0x121, |
| 4507 | "Failed to enable receiving of RSCN " |
| 4508 | "requests: 0x%x.\n", ret); |
| 4509 | clear_bit(SCR_PENDING, &base_vha->dpc_flags); |
| 4510 | } |
| 4511 | |
| 4512 | if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { |
| 4513 | ql_dbg(ql_dbg_dpc, base_vha, 0x4009, |
| 4514 | "Quiescence mode scheduled.\n"); |
| 4515 | if (IS_QLA82XX(ha)) { |
| 4516 | qla82xx_device_state_handler(base_vha); |
| 4517 | clear_bit(ISP_QUIESCE_NEEDED, |
| 4518 | &base_vha->dpc_flags); |
| 4519 | if (!ha->flags.quiesce_owner) { |
| 4520 | qla2x00_perform_loop_resync(base_vha); |
| 4521 | |
| 4522 | qla82xx_idc_lock(ha); |
| 4523 | qla82xx_clear_qsnt_ready(base_vha); |
| 4524 | qla82xx_idc_unlock(ha); |
| 4525 | } |
| 4526 | } else { |
| 4527 | clear_bit(ISP_QUIESCE_NEEDED, |
| 4528 | &base_vha->dpc_flags); |
| 4529 | qla2x00_quiesce_io(base_vha); |
| 4530 | } |
| 4531 | ql_dbg(ql_dbg_dpc, base_vha, 0x400a, |
| 4532 | "Quiescence mode end.\n"); |
| 4533 | } |
| 4534 | |
| 4535 | if (test_and_clear_bit(RESET_MARKER_NEEDED, |
| 4536 | &base_vha->dpc_flags) && |
| 4537 | (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { |
| 4538 | |
| 4539 | ql_dbg(ql_dbg_dpc, base_vha, 0x400b, |
| 4540 | "Reset marker scheduled.\n"); |
| 4541 | qla2x00_rst_aen(base_vha); |
| 4542 | clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); |
| 4543 | ql_dbg(ql_dbg_dpc, base_vha, 0x400c, |
| 4544 | "Reset marker end.\n"); |
| 4545 | } |
| 4546 | |
| 4547 | /* Retry each device up to login retry count */ |
| 4548 | if ((test_and_clear_bit(RELOGIN_NEEDED, |
| 4549 | &base_vha->dpc_flags)) && |
| 4550 | !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && |
| 4551 | atomic_read(&base_vha->loop_state) != LOOP_DOWN) { |
| 4552 | |
| 4553 | ql_dbg(ql_dbg_dpc, base_vha, 0x400d, |
| 4554 | "Relogin scheduled.\n"); |
| 4555 | qla2x00_relogin(base_vha); |
| 4556 | ql_dbg(ql_dbg_dpc, base_vha, 0x400e, |
| 4557 | "Relogin end.\n"); |
| 4558 | } |
| 4559 | |
| 4560 | if (test_and_clear_bit(LOOP_RESYNC_NEEDED, |
| 4561 | &base_vha->dpc_flags)) { |
| 4562 | |
| 4563 | ql_dbg(ql_dbg_dpc, base_vha, 0x400f, |
| 4564 | "Loop resync scheduled.\n"); |
| 4565 | |
| 4566 | if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, |
| 4567 | &base_vha->dpc_flags))) { |
| 4568 | |
| 4569 | rval = qla2x00_loop_resync(base_vha); |
| 4570 | |
| 4571 | clear_bit(LOOP_RESYNC_ACTIVE, |
| 4572 | &base_vha->dpc_flags); |
| 4573 | } |
| 4574 | |
| 4575 | ql_dbg(ql_dbg_dpc, base_vha, 0x4010, |
| 4576 | "Loop resync end.\n"); |
| 4577 | } |
| 4578 | |
| 4579 | if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && |
| 4580 | atomic_read(&base_vha->loop_state) == LOOP_READY) { |
| 4581 | clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); |
| 4582 | qla2xxx_flash_npiv_conf(base_vha); |
| 4583 | } |
| 4584 | |
| 4585 | if (!ha->interrupts_on) |
| 4586 | ha->isp_ops->enable_intrs(ha); |
| 4587 | |
| 4588 | if (test_and_clear_bit(BEACON_BLINK_NEEDED, |
| 4589 | &base_vha->dpc_flags)) |
| 4590 | ha->isp_ops->beacon_blink(base_vha); |
| 4591 | |
| 4592 | qla2x00_do_dpc_all_vps(base_vha); |
| 4593 | |
| 4594 | ha->dpc_active = 0; |
| 4595 | end_loop: |
| 4596 | set_current_state(TASK_INTERRUPTIBLE); |
| 4597 | } /* End of while(1) */ |
| 4598 | __set_current_state(TASK_RUNNING); |
| 4599 | |
| 4600 | ql_dbg(ql_dbg_dpc, base_vha, 0x4011, |
| 4601 | "DPC handler exiting.\n"); |
| 4602 | |
| 4603 | /* |
| 4604 | * Make sure that nobody tries to wake us up again. |
| 4605 | */ |
| 4606 | ha->dpc_active = 0; |
| 4607 | |
| 4608 | /* Cleanup any residual CTX SRBs. */ |
| 4609 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); |
| 4610 | |
| 4611 | return 0; |
| 4612 | } |
| 4613 | |
| 4614 | void |
| 4615 | qla2xxx_wake_dpc(struct scsi_qla_host *vha) |
| 4616 | { |
| 4617 | struct qla_hw_data *ha = vha->hw; |
| 4618 | struct task_struct *t = ha->dpc_thread; |
| 4619 | |
| 4620 | if (!test_bit(UNLOADING, &vha->dpc_flags) && t) |
| 4621 | wake_up_process(t); |
| 4622 | } |
| 4623 | |
| 4624 | /* |
| 4625 | * qla2x00_rst_aen |
| 4626 | * Processes asynchronous reset. |
| 4627 | * |
| 4628 | * Input: |
| 4629 | * ha = adapter block pointer. |
| 4630 | */ |
| 4631 | static void |
| 4632 | qla2x00_rst_aen(scsi_qla_host_t *vha) |
| 4633 | { |
| 4634 | if (vha->flags.online && !vha->flags.reset_active && |
| 4635 | !atomic_read(&vha->loop_down_timer) && |
| 4636 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { |
| 4637 | do { |
| 4638 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); |
| 4639 | |
| 4640 | /* |
| 4641 | * Issue marker command only when we are going to start |
| 4642 | * the I/O. |
| 4643 | */ |
| 4644 | vha->marker_needed = 1; |
| 4645 | } while (!atomic_read(&vha->loop_down_timer) && |
| 4646 | (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); |
| 4647 | } |
| 4648 | } |
| 4649 | |
| 4650 | /************************************************************************** |
| 4651 | * qla2x00_timer |
| 4652 | * |
| 4653 | * Description: |
| 4654 | * One second timer |
| 4655 | * |
| 4656 | * Context: Interrupt |
| 4657 | ***************************************************************************/ |
| 4658 | void |
| 4659 | qla2x00_timer(scsi_qla_host_t *vha) |
| 4660 | { |
| 4661 | unsigned long cpu_flags = 0; |
| 4662 | int start_dpc = 0; |
| 4663 | int index; |
| 4664 | srb_t *sp; |
| 4665 | uint16_t w; |
| 4666 | struct qla_hw_data *ha = vha->hw; |
| 4667 | struct req_que *req; |
| 4668 | |
| 4669 | if (ha->flags.eeh_busy) { |
| 4670 | ql_dbg(ql_dbg_timer, vha, 0x6000, |
| 4671 | "EEH = %d, restarting timer.\n", |
| 4672 | ha->flags.eeh_busy); |
| 4673 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
| 4674 | return; |
| 4675 | } |
| 4676 | |
| 4677 | /* Hardware read to raise pending EEH errors during mailbox waits. */ |
| 4678 | if (!pci_channel_offline(ha->pdev)) |
| 4679 | pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); |
| 4680 | |
| 4681 | /* Make sure qla82xx_watchdog is run only for physical port */ |
| 4682 | if (!vha->vp_idx && IS_QLA82XX(ha)) { |
| 4683 | if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) |
| 4684 | start_dpc++; |
| 4685 | qla82xx_watchdog(vha); |
| 4686 | } |
| 4687 | |
| 4688 | /* Loop down handler. */ |
| 4689 | if (atomic_read(&vha->loop_down_timer) > 0 && |
| 4690 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && |
| 4691 | !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) |
| 4692 | && vha->flags.online) { |
| 4693 | |
| 4694 | if (atomic_read(&vha->loop_down_timer) == |
| 4695 | vha->loop_down_abort_time) { |
| 4696 | |
| 4697 | ql_log(ql_log_info, vha, 0x6008, |
| 4698 | "Loop down - aborting the queues before time expires.\n"); |
| 4699 | |
| 4700 | if (!IS_QLA2100(ha) && vha->link_down_timeout) |
| 4701 | atomic_set(&vha->loop_state, LOOP_DEAD); |
| 4702 | |
| 4703 | /* |
| 4704 | * Schedule an ISP abort to return any FCP2-device |
| 4705 | * commands. |
| 4706 | */ |
| 4707 | /* NPIV - scan physical port only */ |
| 4708 | if (!vha->vp_idx) { |
| 4709 | spin_lock_irqsave(&ha->hardware_lock, |
| 4710 | cpu_flags); |
| 4711 | req = ha->req_q_map[0]; |
| 4712 | for (index = 1; |
| 4713 | index < MAX_OUTSTANDING_COMMANDS; |
| 4714 | index++) { |
| 4715 | fc_port_t *sfcp; |
| 4716 | |
| 4717 | sp = req->outstanding_cmds[index]; |
| 4718 | if (!sp) |
| 4719 | continue; |
| 4720 | if (sp->type != SRB_SCSI_CMD) |
| 4721 | continue; |
| 4722 | sfcp = sp->fcport; |
| 4723 | if (!(sfcp->flags & FCF_FCP2_DEVICE)) |
| 4724 | continue; |
| 4725 | |
| 4726 | if (IS_QLA82XX(ha)) |
| 4727 | set_bit(FCOE_CTX_RESET_NEEDED, |
| 4728 | &vha->dpc_flags); |
| 4729 | else |
| 4730 | set_bit(ISP_ABORT_NEEDED, |
| 4731 | &vha->dpc_flags); |
| 4732 | break; |
| 4733 | } |
| 4734 | spin_unlock_irqrestore(&ha->hardware_lock, |
| 4735 | cpu_flags); |
| 4736 | } |
| 4737 | start_dpc++; |
| 4738 | } |
| 4739 | |
| 4740 | /* if the loop has been down for 4 minutes, reinit adapter */ |
| 4741 | if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { |
| 4742 | if (!(vha->device_flags & DFLG_NO_CABLE)) { |
| 4743 | ql_log(ql_log_warn, vha, 0x6009, |
| 4744 | "Loop down - aborting ISP.\n"); |
| 4745 | |
| 4746 | if (IS_QLA82XX(ha)) |
| 4747 | set_bit(FCOE_CTX_RESET_NEEDED, |
| 4748 | &vha->dpc_flags); |
| 4749 | else |
| 4750 | set_bit(ISP_ABORT_NEEDED, |
| 4751 | &vha->dpc_flags); |
| 4752 | } |
| 4753 | } |
| 4754 | ql_dbg(ql_dbg_timer, vha, 0x600a, |
| 4755 | "Loop down - seconds remaining %d.\n", |
| 4756 | atomic_read(&vha->loop_down_timer)); |
| 4757 | } |
| 4758 | |
| 4759 | /* Check if beacon LED needs to be blinked for physical host only */ |
| 4760 | if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { |
| 4761 | /* There is no beacon_blink function for ISP82xx */ |
| 4762 | if (!IS_QLA82XX(ha)) { |
| 4763 | set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); |
| 4764 | start_dpc++; |
| 4765 | } |
| 4766 | } |
| 4767 | |
| 4768 | /* Process any deferred work. */ |
| 4769 | if (!list_empty(&vha->work_list)) |
| 4770 | start_dpc++; |
| 4771 | |
| 4772 | /* Schedule the DPC routine if needed */ |
| 4773 | if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || |
| 4774 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || |
| 4775 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || |
| 4776 | start_dpc || |
| 4777 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || |
| 4778 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || |
| 4779 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || |
| 4780 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || |
| 4781 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || |
| 4782 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { |
| 4783 | ql_dbg(ql_dbg_timer, vha, 0x600b, |
| 4784 | "isp_abort_needed=%d loop_resync_needed=%d " |
| 4785 | "fcport_update_needed=%d start_dpc=%d " |
| 4786 | "reset_marker_needed=%d", |
| 4787 | test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), |
| 4788 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), |
| 4789 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), |
| 4790 | start_dpc, |
| 4791 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); |
| 4792 | ql_dbg(ql_dbg_timer, vha, 0x600c, |
| 4793 | "beacon_blink_needed=%d isp_unrecoverable=%d " |
| 4794 | "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " |
| 4795 | "relogin_needed=%d.\n", |
| 4796 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), |
| 4797 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), |
| 4798 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), |
| 4799 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags), |
| 4800 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); |
| 4801 | qla2xxx_wake_dpc(vha); |
| 4802 | } |
| 4803 | |
| 4804 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
| 4805 | } |
| 4806 | |
| 4807 | /* Firmware interface routines. */ |
| 4808 | |
| 4809 | #define FW_BLOBS 10 |
| 4810 | #define FW_ISP21XX 0 |
| 4811 | #define FW_ISP22XX 1 |
| 4812 | #define FW_ISP2300 2 |
| 4813 | #define FW_ISP2322 3 |
| 4814 | #define FW_ISP24XX 4 |
| 4815 | #define FW_ISP25XX 5 |
| 4816 | #define FW_ISP81XX 6 |
| 4817 | #define FW_ISP82XX 7 |
| 4818 | #define FW_ISP2031 8 |
| 4819 | #define FW_ISP8031 9 |
| 4820 | |
| 4821 | #define FW_FILE_ISP21XX "ql2100_fw.bin" |
| 4822 | #define FW_FILE_ISP22XX "ql2200_fw.bin" |
| 4823 | #define FW_FILE_ISP2300 "ql2300_fw.bin" |
| 4824 | #define FW_FILE_ISP2322 "ql2322_fw.bin" |
| 4825 | #define FW_FILE_ISP24XX "ql2400_fw.bin" |
| 4826 | #define FW_FILE_ISP25XX "ql2500_fw.bin" |
| 4827 | #define FW_FILE_ISP81XX "ql8100_fw.bin" |
| 4828 | #define FW_FILE_ISP82XX "ql8200_fw.bin" |
| 4829 | #define FW_FILE_ISP2031 "ql2600_fw.bin" |
| 4830 | #define FW_FILE_ISP8031 "ql8300_fw.bin" |
| 4831 | |
| 4832 | static DEFINE_MUTEX(qla_fw_lock); |
| 4833 | |
| 4834 | static struct fw_blob qla_fw_blobs[FW_BLOBS] = { |
| 4835 | { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, |
| 4836 | { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, |
| 4837 | { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, |
| 4838 | { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, |
| 4839 | { .name = FW_FILE_ISP24XX, }, |
| 4840 | { .name = FW_FILE_ISP25XX, }, |
| 4841 | { .name = FW_FILE_ISP81XX, }, |
| 4842 | { .name = FW_FILE_ISP82XX, }, |
| 4843 | { .name = FW_FILE_ISP2031, }, |
| 4844 | { .name = FW_FILE_ISP8031, }, |
| 4845 | }; |
| 4846 | |
| 4847 | struct fw_blob * |
| 4848 | qla2x00_request_firmware(scsi_qla_host_t *vha) |
| 4849 | { |
| 4850 | struct qla_hw_data *ha = vha->hw; |
| 4851 | struct fw_blob *blob; |
| 4852 | |
| 4853 | if (IS_QLA2100(ha)) { |
| 4854 | blob = &qla_fw_blobs[FW_ISP21XX]; |
| 4855 | } else if (IS_QLA2200(ha)) { |
| 4856 | blob = &qla_fw_blobs[FW_ISP22XX]; |
| 4857 | } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { |
| 4858 | blob = &qla_fw_blobs[FW_ISP2300]; |
| 4859 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { |
| 4860 | blob = &qla_fw_blobs[FW_ISP2322]; |
| 4861 | } else if (IS_QLA24XX_TYPE(ha)) { |
| 4862 | blob = &qla_fw_blobs[FW_ISP24XX]; |
| 4863 | } else if (IS_QLA25XX(ha)) { |
| 4864 | blob = &qla_fw_blobs[FW_ISP25XX]; |
| 4865 | } else if (IS_QLA81XX(ha)) { |
| 4866 | blob = &qla_fw_blobs[FW_ISP81XX]; |
| 4867 | } else if (IS_QLA82XX(ha)) { |
| 4868 | blob = &qla_fw_blobs[FW_ISP82XX]; |
| 4869 | } else if (IS_QLA2031(ha)) { |
| 4870 | blob = &qla_fw_blobs[FW_ISP2031]; |
| 4871 | } else if (IS_QLA8031(ha)) { |
| 4872 | blob = &qla_fw_blobs[FW_ISP8031]; |
| 4873 | } else { |
| 4874 | return NULL; |
| 4875 | } |
| 4876 | |
| 4877 | mutex_lock(&qla_fw_lock); |
| 4878 | if (blob->fw) |
| 4879 | goto out; |
| 4880 | |
| 4881 | if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { |
| 4882 | ql_log(ql_log_warn, vha, 0x0063, |
| 4883 | "Failed to load firmware image (%s).\n", blob->name); |
| 4884 | blob->fw = NULL; |
| 4885 | blob = NULL; |
| 4886 | goto out; |
| 4887 | } |
| 4888 | |
| 4889 | out: |
| 4890 | mutex_unlock(&qla_fw_lock); |
| 4891 | return blob; |
| 4892 | } |
| 4893 | |
| 4894 | static void |
| 4895 | qla2x00_release_firmware(void) |
| 4896 | { |
| 4897 | int idx; |
| 4898 | |
| 4899 | mutex_lock(&qla_fw_lock); |
| 4900 | for (idx = 0; idx < FW_BLOBS; idx++) |
| 4901 | release_firmware(qla_fw_blobs[idx].fw); |
| 4902 | mutex_unlock(&qla_fw_lock); |
| 4903 | } |
| 4904 | |
| 4905 | static pci_ers_result_t |
| 4906 | qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) |
| 4907 | { |
| 4908 | scsi_qla_host_t *vha = pci_get_drvdata(pdev); |
| 4909 | struct qla_hw_data *ha = vha->hw; |
| 4910 | |
| 4911 | ql_dbg(ql_dbg_aer, vha, 0x9000, |
| 4912 | "PCI error detected, state %x.\n", state); |
| 4913 | |
| 4914 | switch (state) { |
| 4915 | case pci_channel_io_normal: |
| 4916 | ha->flags.eeh_busy = 0; |
| 4917 | return PCI_ERS_RESULT_CAN_RECOVER; |
| 4918 | case pci_channel_io_frozen: |
| 4919 | ha->flags.eeh_busy = 1; |
| 4920 | /* For ISP82XX complete any pending mailbox cmd */ |
| 4921 | if (IS_QLA82XX(ha)) { |
| 4922 | ha->flags.isp82xx_fw_hung = 1; |
| 4923 | ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); |
| 4924 | qla82xx_clear_pending_mbx(vha); |
| 4925 | } |
| 4926 | qla2x00_free_irqs(vha); |
| 4927 | pci_disable_device(pdev); |
| 4928 | /* Return back all IOs */ |
| 4929 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); |
| 4930 | return PCI_ERS_RESULT_NEED_RESET; |
| 4931 | case pci_channel_io_perm_failure: |
| 4932 | ha->flags.pci_channel_io_perm_failure = 1; |
| 4933 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); |
| 4934 | return PCI_ERS_RESULT_DISCONNECT; |
| 4935 | } |
| 4936 | return PCI_ERS_RESULT_NEED_RESET; |
| 4937 | } |
| 4938 | |
| 4939 | static pci_ers_result_t |
| 4940 | qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) |
| 4941 | { |
| 4942 | int risc_paused = 0; |
| 4943 | uint32_t stat; |
| 4944 | unsigned long flags; |
| 4945 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
| 4946 | struct qla_hw_data *ha = base_vha->hw; |
| 4947 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 4948 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; |
| 4949 | |
| 4950 | if (IS_QLA82XX(ha)) |
| 4951 | return PCI_ERS_RESULT_RECOVERED; |
| 4952 | |
| 4953 | spin_lock_irqsave(&ha->hardware_lock, flags); |
| 4954 | if (IS_QLA2100(ha) || IS_QLA2200(ha)){ |
| 4955 | stat = RD_REG_DWORD(®->hccr); |
| 4956 | if (stat & HCCR_RISC_PAUSE) |
| 4957 | risc_paused = 1; |
| 4958 | } else if (IS_QLA23XX(ha)) { |
| 4959 | stat = RD_REG_DWORD(®->u.isp2300.host_status); |
| 4960 | if (stat & HSR_RISC_PAUSED) |
| 4961 | risc_paused = 1; |
| 4962 | } else if (IS_FWI2_CAPABLE(ha)) { |
| 4963 | stat = RD_REG_DWORD(®24->host_status); |
| 4964 | if (stat & HSRX_RISC_PAUSED) |
| 4965 | risc_paused = 1; |
| 4966 | } |
| 4967 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
| 4968 | |
| 4969 | if (risc_paused) { |
| 4970 | ql_log(ql_log_info, base_vha, 0x9003, |
| 4971 | "RISC paused -- mmio_enabled, Dumping firmware.\n"); |
| 4972 | ha->isp_ops->fw_dump(base_vha, 0); |
| 4973 | |
| 4974 | return PCI_ERS_RESULT_NEED_RESET; |
| 4975 | } else |
| 4976 | return PCI_ERS_RESULT_RECOVERED; |
| 4977 | } |
| 4978 | |
| 4979 | uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha) |
| 4980 | { |
| 4981 | uint32_t rval = QLA_FUNCTION_FAILED; |
| 4982 | uint32_t drv_active = 0; |
| 4983 | struct qla_hw_data *ha = base_vha->hw; |
| 4984 | int fn; |
| 4985 | struct pci_dev *other_pdev = NULL; |
| 4986 | |
| 4987 | ql_dbg(ql_dbg_aer, base_vha, 0x9006, |
| 4988 | "Entered %s.\n", __func__); |
| 4989 | |
| 4990 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
| 4991 | |
| 4992 | if (base_vha->flags.online) { |
| 4993 | /* Abort all outstanding commands, |
| 4994 | * so as to be requeued later */ |
| 4995 | qla2x00_abort_isp_cleanup(base_vha); |
| 4996 | } |
| 4997 | |
| 4998 | |
| 4999 | fn = PCI_FUNC(ha->pdev->devfn); |
| 5000 | while (fn > 0) { |
| 5001 | fn--; |
| 5002 | ql_dbg(ql_dbg_aer, base_vha, 0x9007, |
| 5003 | "Finding pci device at function = 0x%x.\n", fn); |
| 5004 | other_pdev = |
| 5005 | pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), |
| 5006 | ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), |
| 5007 | fn)); |
| 5008 | |
| 5009 | if (!other_pdev) |
| 5010 | continue; |
| 5011 | if (atomic_read(&other_pdev->enable_cnt)) { |
| 5012 | ql_dbg(ql_dbg_aer, base_vha, 0x9008, |
| 5013 | "Found PCI func available and enable at 0x%x.\n", |
| 5014 | fn); |
| 5015 | pci_dev_put(other_pdev); |
| 5016 | break; |
| 5017 | } |
| 5018 | pci_dev_put(other_pdev); |
| 5019 | } |
| 5020 | |
| 5021 | if (!fn) { |
| 5022 | /* Reset owner */ |
| 5023 | ql_dbg(ql_dbg_aer, base_vha, 0x9009, |
| 5024 | "This devfn is reset owner = 0x%x.\n", |
| 5025 | ha->pdev->devfn); |
| 5026 | qla82xx_idc_lock(ha); |
| 5027 | |
| 5028 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
| 5029 | QLA8XXX_DEV_INITIALIZING); |
| 5030 | |
| 5031 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, |
| 5032 | QLA82XX_IDC_VERSION); |
| 5033 | |
| 5034 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); |
| 5035 | ql_dbg(ql_dbg_aer, base_vha, 0x900a, |
| 5036 | "drv_active = 0x%x.\n", drv_active); |
| 5037 | |
| 5038 | qla82xx_idc_unlock(ha); |
| 5039 | /* Reset if device is not already reset |
| 5040 | * drv_active would be 0 if a reset has already been done |
| 5041 | */ |
| 5042 | if (drv_active) |
| 5043 | rval = qla82xx_start_firmware(base_vha); |
| 5044 | else |
| 5045 | rval = QLA_SUCCESS; |
| 5046 | qla82xx_idc_lock(ha); |
| 5047 | |
| 5048 | if (rval != QLA_SUCCESS) { |
| 5049 | ql_log(ql_log_info, base_vha, 0x900b, |
| 5050 | "HW State: FAILED.\n"); |
| 5051 | qla82xx_clear_drv_active(ha); |
| 5052 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
| 5053 | QLA8XXX_DEV_FAILED); |
| 5054 | } else { |
| 5055 | ql_log(ql_log_info, base_vha, 0x900c, |
| 5056 | "HW State: READY.\n"); |
| 5057 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
| 5058 | QLA8XXX_DEV_READY); |
| 5059 | qla82xx_idc_unlock(ha); |
| 5060 | ha->flags.isp82xx_fw_hung = 0; |
| 5061 | rval = qla82xx_restart_isp(base_vha); |
| 5062 | qla82xx_idc_lock(ha); |
| 5063 | /* Clear driver state register */ |
| 5064 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); |
| 5065 | qla82xx_set_drv_active(base_vha); |
| 5066 | } |
| 5067 | qla82xx_idc_unlock(ha); |
| 5068 | } else { |
| 5069 | ql_dbg(ql_dbg_aer, base_vha, 0x900d, |
| 5070 | "This devfn is not reset owner = 0x%x.\n", |
| 5071 | ha->pdev->devfn); |
| 5072 | if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == |
| 5073 | QLA8XXX_DEV_READY)) { |
| 5074 | ha->flags.isp82xx_fw_hung = 0; |
| 5075 | rval = qla82xx_restart_isp(base_vha); |
| 5076 | qla82xx_idc_lock(ha); |
| 5077 | qla82xx_set_drv_active(base_vha); |
| 5078 | qla82xx_idc_unlock(ha); |
| 5079 | } |
| 5080 | } |
| 5081 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
| 5082 | |
| 5083 | return rval; |
| 5084 | } |
| 5085 | |
| 5086 | static pci_ers_result_t |
| 5087 | qla2xxx_pci_slot_reset(struct pci_dev *pdev) |
| 5088 | { |
| 5089 | pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; |
| 5090 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
| 5091 | struct qla_hw_data *ha = base_vha->hw; |
| 5092 | struct rsp_que *rsp; |
| 5093 | int rc, retries = 10; |
| 5094 | |
| 5095 | ql_dbg(ql_dbg_aer, base_vha, 0x9004, |
| 5096 | "Slot Reset.\n"); |
| 5097 | |
| 5098 | /* Workaround: qla2xxx driver which access hardware earlier |
| 5099 | * needs error state to be pci_channel_io_online. |
| 5100 | * Otherwise mailbox command timesout. |
| 5101 | */ |
| 5102 | pdev->error_state = pci_channel_io_normal; |
| 5103 | |
| 5104 | pci_restore_state(pdev); |
| 5105 | |
| 5106 | /* pci_restore_state() clears the saved_state flag of the device |
| 5107 | * save restored state which resets saved_state flag |
| 5108 | */ |
| 5109 | pci_save_state(pdev); |
| 5110 | |
| 5111 | if (ha->mem_only) |
| 5112 | rc = pci_enable_device_mem(pdev); |
| 5113 | else |
| 5114 | rc = pci_enable_device(pdev); |
| 5115 | |
| 5116 | if (rc) { |
| 5117 | ql_log(ql_log_warn, base_vha, 0x9005, |
| 5118 | "Can't re-enable PCI device after reset.\n"); |
| 5119 | goto exit_slot_reset; |
| 5120 | } |
| 5121 | |
| 5122 | rsp = ha->rsp_q_map[0]; |
| 5123 | if (qla2x00_request_irqs(ha, rsp)) |
| 5124 | goto exit_slot_reset; |
| 5125 | |
| 5126 | if (ha->isp_ops->pci_config(base_vha)) |
| 5127 | goto exit_slot_reset; |
| 5128 | |
| 5129 | if (IS_QLA82XX(ha)) { |
| 5130 | if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { |
| 5131 | ret = PCI_ERS_RESULT_RECOVERED; |
| 5132 | goto exit_slot_reset; |
| 5133 | } else |
| 5134 | goto exit_slot_reset; |
| 5135 | } |
| 5136 | |
| 5137 | while (ha->flags.mbox_busy && retries--) |
| 5138 | msleep(1000); |
| 5139 | |
| 5140 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
| 5141 | if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) |
| 5142 | ret = PCI_ERS_RESULT_RECOVERED; |
| 5143 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
| 5144 | |
| 5145 | |
| 5146 | exit_slot_reset: |
| 5147 | ql_dbg(ql_dbg_aer, base_vha, 0x900e, |
| 5148 | "slot_reset return %x.\n", ret); |
| 5149 | |
| 5150 | return ret; |
| 5151 | } |
| 5152 | |
| 5153 | static void |
| 5154 | qla2xxx_pci_resume(struct pci_dev *pdev) |
| 5155 | { |
| 5156 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
| 5157 | struct qla_hw_data *ha = base_vha->hw; |
| 5158 | int ret; |
| 5159 | |
| 5160 | ql_dbg(ql_dbg_aer, base_vha, 0x900f, |
| 5161 | "pci_resume.\n"); |
| 5162 | |
| 5163 | ret = qla2x00_wait_for_hba_online(base_vha); |
| 5164 | if (ret != QLA_SUCCESS) { |
| 5165 | ql_log(ql_log_fatal, base_vha, 0x9002, |
| 5166 | "The device failed to resume I/O from slot/link_reset.\n"); |
| 5167 | } |
| 5168 | |
| 5169 | pci_cleanup_aer_uncorrect_error_status(pdev); |
| 5170 | |
| 5171 | ha->flags.eeh_busy = 0; |
| 5172 | } |
| 5173 | |
| 5174 | static struct pci_error_handlers qla2xxx_err_handler = { |
| 5175 | .error_detected = qla2xxx_pci_error_detected, |
| 5176 | .mmio_enabled = qla2xxx_pci_mmio_enabled, |
| 5177 | .slot_reset = qla2xxx_pci_slot_reset, |
| 5178 | .resume = qla2xxx_pci_resume, |
| 5179 | }; |
| 5180 | |
| 5181 | static struct pci_device_id qla2xxx_pci_tbl[] = { |
| 5182 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, |
| 5183 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, |
| 5184 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, |
| 5185 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, |
| 5186 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, |
| 5187 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, |
| 5188 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, |
| 5189 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, |
| 5190 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, |
| 5191 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, |
| 5192 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, |
| 5193 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, |
| 5194 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, |
| 5195 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, |
| 5196 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, |
| 5197 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, |
| 5198 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, |
| 5199 | { 0 }, |
| 5200 | }; |
| 5201 | MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); |
| 5202 | |
| 5203 | static struct pci_driver qla2xxx_pci_driver = { |
| 5204 | .name = QLA2XXX_DRIVER_NAME, |
| 5205 | .driver = { |
| 5206 | .owner = THIS_MODULE, |
| 5207 | }, |
| 5208 | .id_table = qla2xxx_pci_tbl, |
| 5209 | .probe = qla2x00_probe_one, |
| 5210 | .remove = qla2x00_remove_one, |
| 5211 | .shutdown = qla2x00_shutdown, |
| 5212 | .err_handler = &qla2xxx_err_handler, |
| 5213 | }; |
| 5214 | |
| 5215 | static struct file_operations apidev_fops = { |
| 5216 | .owner = THIS_MODULE, |
| 5217 | .llseek = noop_llseek, |
| 5218 | }; |
| 5219 | |
| 5220 | /** |
| 5221 | * qla2x00_module_init - Module initialization. |
| 5222 | **/ |
| 5223 | static int __init |
| 5224 | qla2x00_module_init(void) |
| 5225 | { |
| 5226 | int ret = 0; |
| 5227 | |
| 5228 | /* Allocate cache for SRBs. */ |
| 5229 | srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, |
| 5230 | SLAB_HWCACHE_ALIGN, NULL); |
| 5231 | if (srb_cachep == NULL) { |
| 5232 | ql_log(ql_log_fatal, NULL, 0x0001, |
| 5233 | "Unable to allocate SRB cache...Failing load!.\n"); |
| 5234 | return -ENOMEM; |
| 5235 | } |
| 5236 | |
| 5237 | /* Initialize target kmem_cache and mem_pools */ |
| 5238 | ret = qlt_init(); |
| 5239 | if (ret < 0) { |
| 5240 | kmem_cache_destroy(srb_cachep); |
| 5241 | return ret; |
| 5242 | } else if (ret > 0) { |
| 5243 | /* |
| 5244 | * If initiator mode is explictly disabled by qlt_init(), |
| 5245 | * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from |
| 5246 | * performing scsi_scan_target() during LOOP UP event. |
| 5247 | */ |
| 5248 | qla2xxx_transport_functions.disable_target_scan = 1; |
| 5249 | qla2xxx_transport_vport_functions.disable_target_scan = 1; |
| 5250 | } |
| 5251 | |
| 5252 | /* Derive version string. */ |
| 5253 | strcpy(qla2x00_version_str, QLA2XXX_VERSION); |
| 5254 | if (ql2xextended_error_logging) |
| 5255 | strcat(qla2x00_version_str, "-debug"); |
| 5256 | |
| 5257 | qla2xxx_transport_template = |
| 5258 | fc_attach_transport(&qla2xxx_transport_functions); |
| 5259 | if (!qla2xxx_transport_template) { |
| 5260 | kmem_cache_destroy(srb_cachep); |
| 5261 | ql_log(ql_log_fatal, NULL, 0x0002, |
| 5262 | "fc_attach_transport failed...Failing load!.\n"); |
| 5263 | qlt_exit(); |
| 5264 | return -ENODEV; |
| 5265 | } |
| 5266 | |
| 5267 | apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); |
| 5268 | if (apidev_major < 0) { |
| 5269 | ql_log(ql_log_fatal, NULL, 0x0003, |
| 5270 | "Unable to register char device %s.\n", QLA2XXX_APIDEV); |
| 5271 | } |
| 5272 | |
| 5273 | qla2xxx_transport_vport_template = |
| 5274 | fc_attach_transport(&qla2xxx_transport_vport_functions); |
| 5275 | if (!qla2xxx_transport_vport_template) { |
| 5276 | kmem_cache_destroy(srb_cachep); |
| 5277 | qlt_exit(); |
| 5278 | fc_release_transport(qla2xxx_transport_template); |
| 5279 | ql_log(ql_log_fatal, NULL, 0x0004, |
| 5280 | "fc_attach_transport vport failed...Failing load!.\n"); |
| 5281 | return -ENODEV; |
| 5282 | } |
| 5283 | ql_log(ql_log_info, NULL, 0x0005, |
| 5284 | "QLogic Fibre Channel HBA Driver: %s.\n", |
| 5285 | qla2x00_version_str); |
| 5286 | ret = pci_register_driver(&qla2xxx_pci_driver); |
| 5287 | if (ret) { |
| 5288 | kmem_cache_destroy(srb_cachep); |
| 5289 | qlt_exit(); |
| 5290 | fc_release_transport(qla2xxx_transport_template); |
| 5291 | fc_release_transport(qla2xxx_transport_vport_template); |
| 5292 | ql_log(ql_log_fatal, NULL, 0x0006, |
| 5293 | "pci_register_driver failed...ret=%d Failing load!.\n", |
| 5294 | ret); |
| 5295 | } |
| 5296 | return ret; |
| 5297 | } |
| 5298 | |
| 5299 | /** |
| 5300 | * qla2x00_module_exit - Module cleanup. |
| 5301 | **/ |
| 5302 | static void __exit |
| 5303 | qla2x00_module_exit(void) |
| 5304 | { |
| 5305 | unregister_chrdev(apidev_major, QLA2XXX_APIDEV); |
| 5306 | pci_unregister_driver(&qla2xxx_pci_driver); |
| 5307 | qla2x00_release_firmware(); |
| 5308 | kmem_cache_destroy(srb_cachep); |
| 5309 | qlt_exit(); |
| 5310 | if (ctx_cachep) |
| 5311 | kmem_cache_destroy(ctx_cachep); |
| 5312 | fc_release_transport(qla2xxx_transport_template); |
| 5313 | fc_release_transport(qla2xxx_transport_vport_template); |
| 5314 | } |
| 5315 | |
| 5316 | module_init(qla2x00_module_init); |
| 5317 | module_exit(qla2x00_module_exit); |
| 5318 | |
| 5319 | MODULE_AUTHOR("QLogic Corporation"); |
| 5320 | MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); |
| 5321 | MODULE_LICENSE("GPL"); |
| 5322 | MODULE_VERSION(QLA2XXX_VERSION); |
| 5323 | MODULE_FIRMWARE(FW_FILE_ISP21XX); |
| 5324 | MODULE_FIRMWARE(FW_FILE_ISP22XX); |
| 5325 | MODULE_FIRMWARE(FW_FILE_ISP2300); |
| 5326 | MODULE_FIRMWARE(FW_FILE_ISP2322); |
| 5327 | MODULE_FIRMWARE(FW_FILE_ISP24XX); |
| 5328 | MODULE_FIRMWARE(FW_FILE_ISP25XX); |