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pch_gbe: Move the OKI Semiconductor driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
a6b7a407 35#include <linux/interrupt.h>
cd28ab6a 36#include <linux/ip.h>
5a0e3ad6 37#include <linux/slab.h>
c9bdd4b5 38#include <net/ip.h>
cd28ab6a
SH		 39#include <linux/tcp.h>
40#include <linux/in.h>
41#include <linux/delay.h>
91c86df5 42#include <linux/workqueue.h>
d1f13708 43#include <linux/if_vlan.h>
d70cd51a 44#include <linux/prefetch.h>
3cf26753 45#include <linux/debugfs.h>
ef743d33 46#include <linux/mii.h>
cd28ab6a
SH		 47
48#include <asm/irq.h>
49
50#include "sky2.h"
51
52#define DRV_NAME "sky2"
4ec8f0ca 53#define DRV_VERSION "1.29"
cd28ab6a
SH		 54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 65
ee5f68fe 66/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 69#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
efe91932 70#define TX_MAX_PENDING 1024
ee5f68fe 71#define TX_DEF_PENDING 127
cd28ab6a 72
cd28ab6a
SH		 73#define TX_WATCHDOG (5 * HZ)
74#define NAPI_WEIGHT 64
75#define PHY_RETRIES 1000
76
f4331a6d
SH		 77#define SKY2_EEPROM_MAGIC 0x9955aabb
78
060b946c 79#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
cb5d9547 80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e6cac9ba 98static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
060b946c 172 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33
SH		 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
4b7c47aa 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 249
5f8ae5c5 250 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
251
8f70920f
SH		 252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 256
257 sky2_read32(hw, B2_GP_IO);
5afa0a9c 258 }
10547ae2
SH		 259
260 /* Turn on "driver loaded" LED */
261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 262}
5afa0a9c 263
ae306cca
SH		 264static void sky2_power_aux(struct sky2_hw *hw)
265{
4b7c47aa 266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
268 else
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
274
c23ddf8f
SH		 275 /* switch power to VAUX if supported and PME from D3cold */
276 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
277 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 278 sky2_write8(hw, B0_POWER_CTRL,
279 (PC_VAUX_ENA | PC_VCC_ENA |
280 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 281
282 /* turn off "driver loaded LED" */
283 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 284}
285
d3bcfbeb 286static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 287{
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 292
cd28ab6a
SH		 293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301}
302
16ad91e1
SH		 303/* flow control to advertise bits */
304static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309};
310
311/* flow control to advertise bits when using 1000BaseX */
312static const u16 fiber_fc_adv[] = {
df3fe1f3 313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 317};
318
319/* flow control to GMA disable bits */
320static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325};
326
327
cd28ab6a
SH		 328static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329{
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 332
0ea065e5 333 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 338 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
53419c68 341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 342 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 343 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
53419c68
SH		 346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 353 if (sky2_is_copper(hw)) {
05745c4a 354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
cd28ab6a 367 } else {
4fb99cd6 368 if (hw->chip_id >= CHIP_ID_YUKON_OPT) {
369 u16 ctrl2 = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL_2);
370
371 /* enable PHY Reverse Auto-Negotiation */
372 ctrl2 |= 1u << 13;
373
374 /* Write PHY changes (SW-reset must follow) */
375 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL_2, ctrl2);
376 }
377
378
cd28ab6a
SH		 379 /* disable energy detect */
380 ctrl &= ~PHY_M_PC_EN_DET_MSK;
381
382 /* enable automatic crossover */
383 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
384
53419c68 385 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 386 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
387 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 388 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 389 ctrl &= ~PHY_M_PC_DSC_MSK;
390 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
391 }
392 }
cd28ab6a
SH		 393 } else {
394 /* workaround for deviation #4.88 (CRC errors) */
395 /* disable Automatic Crossover */
396
397 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 398 }
cd28ab6a 399
b89165f2
SH		 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 /* special setup for PHY 88E1112 Fiber */
ea76e635 403 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 404 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 405
b89165f2
SH		 406 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
407 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl &= ~PHY_M_MAC_MD_MSK;
410 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412
413 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 414 /* select page 1 to access Fiber registers */
415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 416
417 /* for SFP-module set SIGDET polarity to low */
418 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
419 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 420 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 421 }
b89165f2
SH		 422
423 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 424 }
425
7800fddc 426 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 427 ct1000 = 0;
428 adv = PHY_AN_CSMA;
2eaba1a2 429 reg = 0;
cd28ab6a 430
0ea065e5 431 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 432 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 433 if (sky2->advertising & ADVERTISED_1000baseT_Full)
434 ct1000 |= PHY_M_1000C_AFD;
435 if (sky2->advertising & ADVERTISED_1000baseT_Half)
436 ct1000 |= PHY_M_1000C_AHD;
437 if (sky2->advertising & ADVERTISED_100baseT_Full)
438 adv |= PHY_M_AN_100_FD;
439 if (sky2->advertising & ADVERTISED_100baseT_Half)
440 adv |= PHY_M_AN_100_HD;
441 if (sky2->advertising & ADVERTISED_10baseT_Full)
442 adv |= PHY_M_AN_10_FD;
443 if (sky2->advertising & ADVERTISED_10baseT_Half)
444 adv |= PHY_M_AN_10_HD;
709c6e7b 445
b89165f2
SH		 446 } else { /* special defines for FIBER (88E1040S only) */
447 if (sky2->advertising & ADVERTISED_1000baseT_Full)
448 adv |= PHY_M_AN_1000X_AFD;
449 if (sky2->advertising & ADVERTISED_1000baseT_Half)
450 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 451 }
cd28ab6a
SH		 452
453 /* Restart Auto-negotiation */
454 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
455 } else {
456 /* forced speed/duplex settings */
457 ct1000 = PHY_M_1000C_MSE;
458
0ea065e5
SH		 459 /* Disable auto update for duplex flow control and duplex */
460 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 461
462 switch (sky2->speed) {
463 case SPEED_1000:
464 ctrl |= PHY_CT_SP1000;
2eaba1a2 465 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 466 break;
467 case SPEED_100:
468 ctrl |= PHY_CT_SP100;
2eaba1a2 469 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 470 break;
471 }
472
2eaba1a2
SH		 473 if (sky2->duplex == DUPLEX_FULL) {
474 reg |= GM_GPCR_DUP_FULL;
475 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 476 } else if (sky2->speed < SPEED_1000)
477 sky2->flow_mode = FC_NONE;
0ea065e5 478 }
2eaba1a2 479
0ea065e5
SH		 480 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
481 if (sky2_is_copper(hw))
482 adv |= copper_fc_adv[sky2->flow_mode];
483 else
484 adv |= fiber_fc_adv[sky2->flow_mode];
485 } else {
486 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 487 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 488
489 /* Forward pause packets to GMAC? */
16ad91e1 490 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 491 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
492 else
493 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 494 }
495
2eaba1a2
SH		 496 gma_write16(hw, port, GM_GP_CTRL, reg);
497
05745c4a 498 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 499 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
500
501 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
502 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
503
504 /* Setup Phy LED's */
505 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
506 ledover = 0;
507
508 switch (hw->chip_id) {
509 case CHIP_ID_YUKON_FE:
510 /* on 88E3082 these bits are at 11..9 (shifted left) */
511 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
512
513 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
514
515 /* delete ACT LED control bits */
516 ctrl &= ~PHY_M_FELP_LED1_MSK;
517 /* change ACT LED control to blink mode */
518 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
519 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
520 break;
521
05745c4a
SH		 522 case CHIP_ID_YUKON_FE_P:
523 /* Enable Link Partner Next Page */
524 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
525 ctrl |= PHY_M_PC_ENA_LIP_NP;
526
527 /* disable Energy Detect and enable scrambler */
528 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
529 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
530
531 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
532 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
533 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
534 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
535
536 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
537 break;
538
cd28ab6a 539 case CHIP_ID_YUKON_XL:
793b883e 540 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 541
542 /* select page 3 to access LED control register */
543 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
544
545 /* set LED Function Control register */
ed6d32c7
SH		 546 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
547 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
548 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
549 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
550 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 551
552 /* set Polarity Control register */
553 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 554 (PHY_M_POLC_LS1_P_MIX(4) |
555 PHY_M_POLC_IS0_P_MIX(4) |
556 PHY_M_POLC_LOS_CTRL(2) |
557 PHY_M_POLC_INIT_CTRL(2) |
558 PHY_M_POLC_STA1_CTRL(2) |
559 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 560
561 /* restore page register */
793b883e 562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 563 break;
93745494 564
ed6d32c7 565 case CHIP_ID_YUKON_EC_U:
93745494 566 case CHIP_ID_YUKON_EX:
ed4d4161 567 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 568 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
569
570 /* select page 3 to access LED control register */
571 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
572
573 /* set LED Function Control register */
574 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
575 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
576 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
577 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
578 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
579
580 /* set Blink Rate in LED Timer Control Register */
581 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
582 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
583 /* restore page register */
584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
585 break;
cd28ab6a
SH		 586
587 default:
588 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
589 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 590
cd28ab6a 591 /* turn off the Rx LED (LED_RX) */
a84d0a3d 592 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 593 }
594
0ce8b98d 595 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 596 /* apply fixes in PHY AFE */
ed6d32c7
SH		 597 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
598
977bdf06 599 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 600 gm_phy_write(hw, port, 0x18, 0xaa99);
601 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 602
0ce8b98d
SH		 603 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
604 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
605 gm_phy_write(hw, port, 0x18, 0xa204);
606 gm_phy_write(hw, port, 0x17, 0x2002);
607 }
977bdf06
SH		 608
609 /* set page register to 0 */
9467a8fc 610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 611 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
612 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
613 /* apply workaround for integrated resistors calibration */
614 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
615 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 616 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
617 /* apply fixes in PHY AFE */
618 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
619
620 /* apply RDAC termination workaround */
621 gm_phy_write(hw, port, 24, 0x2800);
622 gm_phy_write(hw, port, 23, 0x2001);
623
624 /* set page register back to 0 */
625 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 626 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
627 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 628 /* no effect on Yukon-XL */
977bdf06 629 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 630
8e95a202
JP		 631 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
632 sky2->speed == SPEED_100) {
977bdf06 633 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 634 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 635 }
cd28ab6a 636
977bdf06
SH		 637 if (ledover)
638 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
639
4fb99cd6 640 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
641 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
642 int i;
643 /* This a phy register setup workaround copied from vendor driver. */
644 static const struct {
645 u16 reg, val;
646 } eee_afe[] = {
647 { 0x156, 0x58ce },
648 { 0x153, 0x99eb },
649 { 0x141, 0x8064 },
650 /* { 0x155, 0x130b },*/
651 { 0x000, 0x0000 },
652 { 0x151, 0x8433 },
653 { 0x14b, 0x8c44 },
654 { 0x14c, 0x0f90 },
655 { 0x14f, 0x39aa },
656 /* { 0x154, 0x2f39 },*/
657 { 0x14d, 0xba33 },
658 { 0x144, 0x0048 },
659 { 0x152, 0x2010 },
660 /* { 0x158, 0x1223 },*/
661 { 0x140, 0x4444 },
662 { 0x154, 0x2f3b },
663 { 0x158, 0xb203 },
664 { 0x157, 0x2029 },
665 };
666
667 /* Start Workaround for OptimaEEE Rev.Z0 */
668 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
669
670 gm_phy_write(hw, port, 1, 0x4099);
671 gm_phy_write(hw, port, 3, 0x1120);
672 gm_phy_write(hw, port, 11, 0x113c);
673 gm_phy_write(hw, port, 14, 0x8100);
674 gm_phy_write(hw, port, 15, 0x112a);
675 gm_phy_write(hw, port, 17, 0x1008);
676
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
678 gm_phy_write(hw, port, 1, 0x20b0);
679
680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
681
682 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
683 /* apply AFE settings */
684 gm_phy_write(hw, port, 17, eee_afe[i].val);
685 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
686 }
687
688 /* End Workaround for OptimaEEE */
689 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
690
691 /* Enable 10Base-Te (EEE) */
692 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
693 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
694 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
695 reg | PHY_M_10B_TE_ENABLE);
696 }
977bdf06 697 }
2eaba1a2 698
d571b694 699 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 700 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 701 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
702 else
703 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
704}
705
b96936da
SH		 706static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
707static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
708
709static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 710{
711 u32 reg1;
d3bcfbeb 712
a40ccc68 713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 714 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 715 reg1 &= ~phy_power[port];
d3bcfbeb 716
4b7c47aa 717 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 718 reg1 |= coma_mode[port];
719
b32f40c4 720 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 721 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 722 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 723
724 if (hw->chip_id == CHIP_ID_YUKON_FE)
725 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
726 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
727 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 728}
167f53d0 729
b96936da
SH		 730static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
731{
732 u32 reg1;
db99b988
SH		 733 u16 ctrl;
734
735 /* release GPHY Control reset */
736 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
737
738 /* release GMAC reset */
739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
740
741 if (hw->flags & SKY2_HW_NEWER_PHY) {
742 /* select page 2 to access MAC control register */
743 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
744
745 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
746 /* allow GMII Power Down */
747 ctrl &= ~PHY_M_MAC_GMIF_PUP;
748 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
749
750 /* set page register back to 0 */
751 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
752 }
753
754 /* setup General Purpose Control Register */
755 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 756 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
757 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
758 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 759
760 if (hw->chip_id != CHIP_ID_YUKON_EC) {
761 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 762 /* select page 2 to access MAC control register */
763 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 764
e484d5f5 765 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 766 /* enable Power Down */
767 ctrl |= PHY_M_PC_POW_D_ENA;
768 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 769
770 /* set page register back to 0 */
771 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 772 }
773
774 /* set IEEE compatible Power Down Mode (dev. #4.99) */
775 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
776 }
b96936da 777
a40ccc68 778 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 779 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 780 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 781 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 782 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 783}
784
8e11680f 785/* configure IPG according to used link speed */
786static void sky2_set_ipg(struct sky2_port *sky2)
787{
788 u16 reg;
789
790 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
791 reg &= ~GM_SMOD_IPG_MSK;
792 if (sky2->speed > SPEED_100)
793 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
794 else
795 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
796 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
797}
798
38000a94
BP		 799/* Enable Rx/Tx */
800static void sky2_enable_rx_tx(struct sky2_port *sky2)
801{
802 struct sky2_hw *hw = sky2->hw;
803 unsigned port = sky2->port;
804 u16 reg;
805
806 reg = gma_read16(hw, port, GM_GP_CTRL);
807 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
808 gma_write16(hw, port, GM_GP_CTRL, reg);
809}
810
1b537565
SH		 811/* Force a renegotiation */
812static void sky2_phy_reinit(struct sky2_port *sky2)
813{
e07b1aa8 814 spin_lock_bh(&sky2->phy_lock);
1b537565 815 sky2_phy_init(sky2->hw, sky2->port);
38000a94 816 sky2_enable_rx_tx(sky2);
e07b1aa8 817 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 818}
819
e3173832
SH		 820/* Put device in state to listen for Wake On Lan */
821static void sky2_wol_init(struct sky2_port *sky2)
822{
823 struct sky2_hw *hw = sky2->hw;
824 unsigned port = sky2->port;
825 enum flow_control save_mode;
826 u16 ctrl;
e3173832
SH		 827
828 /* Bring hardware out of reset */
829 sky2_write16(hw, B0_CTST, CS_RST_CLR);
830 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
831
832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
833 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
834
835 /* Force to 10/100
836 * sky2_reset will re-enable on resume
837 */
838 save_mode = sky2->flow_mode;
839 ctrl = sky2->advertising;
840
841 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
842 sky2->flow_mode = FC_NONE;
b96936da
SH		 843
844 spin_lock_bh(&sky2->phy_lock);
845 sky2_phy_power_up(hw, port);
846 sky2_phy_init(hw, port);
847 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 848
849 sky2->flow_mode = save_mode;
850 sky2->advertising = ctrl;
851
852 /* Set GMAC to no flow control and auto update for speed/duplex */
853 gma_write16(hw, port, GM_GP_CTRL,
854 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
855 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
856
857 /* Set WOL address */
858 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
859 sky2->netdev->dev_addr, ETH_ALEN);
860
861 /* Turn on appropriate WOL control bits */
862 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
863 ctrl = 0;
864 if (sky2->wol & WAKE_PHY)
865 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
866 else
867 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
868
869 if (sky2->wol & WAKE_MAGIC)
870 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
871 else
a419aef8 872 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 873
874 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
875 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
876
5f8ae5c5 877 /* Disable PiG firmware */
878 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
879
e3173832
SH		 880 /* block receiver */
881 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 882}
883
69161611
SH		 884static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
885{
05745c4a
SH		 886 struct net_device *dev = hw->dev[port];
887
ed4d4161
SH		 888 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
889 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 890 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 891 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 892 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
893 } else if (dev->mtu > ETH_DATA_LEN) {
894 /* set Tx GMAC FIFO Almost Empty Threshold */
895 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
896 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 897
44dde56d 898 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
899 } else
900 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 901}
902
cd28ab6a
SH		 903static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
904{
905 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
906 u16 reg;
25cccecc 907 u32 rx_reg;
cd28ab6a
SH		 908 int i;
909 const u8 *addr = hw->dev[port]->dev_addr;
910
f350339c
SH		 911 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
912 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 913
914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
915
4b7c47aa 916 if (hw->chip_id == CHIP_ID_YUKON_XL &&
917 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
918 port == 1) {
cd28ab6a
SH		 919 /* WA DEV_472 -- looks like crossed wires on port 2 */
920 /* clear GMAC 1 Control reset */
921 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
922 do {
923 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
924 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
925 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
926 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
927 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
928 }
929
793b883e 930 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 931
2eaba1a2
SH		 932 /* Enable Transmit FIFO Underrun */
933 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
934
e07b1aa8 935 spin_lock_bh(&sky2->phy_lock);
b96936da 936 sky2_phy_power_up(hw, port);
cd28ab6a 937 sky2_phy_init(hw, port);
e07b1aa8 938 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 939
940 /* MIB clear */
941 reg = gma_read16(hw, port, GM_PHY_ADDR);
942 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
943
43f2f104
SH		 944 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
945 gma_read16(hw, port, i);
cd28ab6a
SH		 946 gma_write16(hw, port, GM_PHY_ADDR, reg);
947
948 /* transmit control */
949 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
950
951 /* receive control reg: unicast + multicast + no FCS */
952 gma_write16(hw, port, GM_RX_CTRL,
793b883e 953 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 954
955 /* transmit flow control */
956 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
957
958 /* transmit parameter */
959 gma_write16(hw, port, GM_TX_PARAM,
960 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
961 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
962 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
963 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
964
965 /* serial mode register */
966 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
8e11680f 967 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
cd28ab6a 968
6b1a3aef 969 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 970 reg |= GM_SMOD_JUMBO_ENA;
971
c1cd0a85 972 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
973 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
974 reg |= GM_NEW_FLOW_CTRL;
975
cd28ab6a
SH		 976 gma_write16(hw, port, GM_SERIAL_MODE, reg);
977
cd28ab6a
SH		 978 /* virtual address for data */
979 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
980
793b883e
SH		 981 /* physical address: used for pause frames */
982 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
983
984 /* ignore counter overflows */
cd28ab6a
SH		 985 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
986 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
987 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
988
989 /* Configure Rx MAC FIFO */
990 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 991 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 992 if (hw->chip_id == CHIP_ID_YUKON_EX ||
993 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 994 rx_reg |= GMF_RX_OVER_ON;
69161611 995
25cccecc 996 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 997
798fdd07
SH		 998 if (hw->chip_id == CHIP_ID_YUKON_XL) {
999 /* Hardware errata - clear flush mask */
1000 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1001 } else {
1002 /* Flush Rx MAC FIFO on any flow control or error */
1003 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1004 }
cd28ab6a 1005
8df9a876 1006 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 1007 reg = RX_GMF_FL_THR_DEF + 1;
1008 /* Another magic mystery workaround from sk98lin */
1009 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1010 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1011 reg = 0x178;
1012 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 1013
1014 /* Configure Tx MAC FIFO */
1015 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1016 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 1017
25985edc 1018 /* On chips without ram buffer, pause is controlled by MAC level */
39dbd958 1019 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 1020 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 1021 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1022 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 1023 reg = 1568 / 8;
1024 else
1025 reg = 1024 / 8;
1026 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1027 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 1028
69161611 1029 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 1030 }
1031
e970d1f8
SH		 1032 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1033 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1034 /* disable dynamic watermark */
1035 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1036 reg &= ~TX_DYN_WM_ENA;
1037 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1038 }
cd28ab6a
SH		 1039}
1040
67712901
SH		 1041/* Assign Ram Buffer allocation to queue */
1042static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 1043{
67712901
SH		 1044 u32 end;
1045
1046 /* convert from K bytes to qwords used for hw register */
1047 start *= 1024/8;
1048 space *= 1024/8;
1049 end = start + space - 1;
793b883e 1050
cd28ab6a
SH		 1051 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1052 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1053 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1054 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1055 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1056
1057 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 1058 u32 tp = space - space/4;
793b883e 1059
1c28f6ba
SH		 1060 /* On receive queue's set the thresholds
1061 * give receiver priority when > 3/4 full
1062 * send pause when down to 2K
1063 */
1064 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1065 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 1066
1c28f6ba
SH		 1067 tp = space - 2048/8;
1068 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1069 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 1070 } else {
1071 /* Enable store & forward on Tx queue's because
1072 * Tx FIFO is only 1K on Yukon
1073 */
1074 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1075 }
1076
1077 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 1078 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 1079}
1080
cd28ab6a 1081/* Setup Bus Memory Interface */
af4ed7e6 1082static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1083{
1084 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1085 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1086 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1087 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1088}
1089
cd28ab6a
SH		 1090/* Setup prefetch unit registers. This is the interface between
1091 * hardware and driver list elements
1092 */
8cc048e3 1093static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1094 dma_addr_t addr, u32 last)
cd28ab6a 1095{
cd28ab6a
SH		 1096 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1097 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1098 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1099 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1100 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1102
1103 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1104}
1105
9b289c33 1106static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1107{
9b289c33 1108 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1109
ee5f68fe 1110 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1111 le->ctrl = 0;
793b883e
SH		 1112 return le;
1113}
cd28ab6a 1114
88f5f0ca
SH		 1115static void tx_init(struct sky2_port *sky2)
1116{
1117 struct sky2_tx_le *le;
1118
1119 sky2->tx_prod = sky2->tx_cons = 0;
1120 sky2->tx_tcpsum = 0;
1121 sky2->tx_last_mss = 0;
1122
9b289c33 1123 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1124 le->addr = 0;
1125 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1126 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1127}
1128
290d4de5
SH		 1129/* Update chip's next pointer */
1130static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1131{
50432cb5 1132 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1133 wmb();
50432cb5
SH		 1134 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1135
1136 /* Synchronize I/O on since next processor may write to tail */
1137 mmiowb();
cd28ab6a
SH		 1138}
1139
793b883e 1140
cd28ab6a
SH		 1141static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1142{
1143 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1144 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1145 le->ctrl = 0;
cd28ab6a
SH		 1146 return le;
1147}
1148
060b946c 1149static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
39ef110b
MM		 1150{
1151 unsigned size;
1152
1153 /* Space needed for frame data + headers rounded up */
1154 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1155
1156 /* Stopping point for hardware truncation */
1157 return (size - 8) / sizeof(u32);
1158}
1159
060b946c 1160static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
39ef110b
MM		 1161{
1162 struct rx_ring_info *re;
1163 unsigned size;
1164
1165 /* Space needed for frame data + headers rounded up */
1166 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1167
1168 sky2->rx_nfrags = size >> PAGE_SHIFT;
1169 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1170
1171 /* Compute residue after pages */
1172 size -= sky2->rx_nfrags << PAGE_SHIFT;
1173
1174 /* Optimize to handle small packets and headers */
1175 if (size < copybreak)
1176 size = copybreak;
1177 if (size < ETH_HLEN)
1178 size = ETH_HLEN;
1179
1180 return size;
1181}
1182
14d0263f 1183/* Build description to hardware for one receive segment */
060b946c 1184static void sky2_rx_add(struct sky2_port *sky2, u8 op,
14d0263f 1185 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1186{
1187 struct sky2_rx_le *le;
1188
86c6887e 1189 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1190 le = sky2_next_rx(sky2);
86c6887e 1191 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1192 le->opcode = OP_ADDR64 | HW_OWNER;
1193 }
793b883e 1194
cd28ab6a 1195 le = sky2_next_rx(sky2);
d6e74b6b 1196 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1197 le->length = cpu_to_le16(len);
14d0263f 1198 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1199}
1200
14d0263f
SH		 1201/* Build description to hardware for one possibly fragmented skb */
1202static void sky2_rx_submit(struct sky2_port *sky2,
1203 const struct rx_ring_info *re)
1204{
1205 int i;
1206
1207 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1208
1209 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1210 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1211}
1212
1213
454e6cb6 1214static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1215 unsigned size)
1216{
1217 struct sk_buff *skb = re->skb;
1218 int i;
1219
1220 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1221 if (pci_dma_mapping_error(pdev, re->data_addr))
1222 goto mapping_error;
454e6cb6 1223
7cd26ce5 1224 dma_unmap_len_set(re, data_size, size);
14d0263f 1225
3fbd9187 1226 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1227 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1228
1229 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1230 frag->page_offset,
1231 frag->size,
14d0263f 1232 PCI_DMA_FROMDEVICE);
3fbd9187 1233
1234 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1235 goto map_page_error;
1236 }
454e6cb6 1237 return 0;
3fbd9187 1238
1239map_page_error:
1240 while (--i >= 0) {
1241 pci_unmap_page(pdev, re->frag_addr[i],
1242 skb_shinfo(skb)->frags[i].size,
1243 PCI_DMA_FROMDEVICE);
1244 }
1245
7cd26ce5 1246 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
3fbd9187 1247 PCI_DMA_FROMDEVICE);
1248
1249mapping_error:
1250 if (net_ratelimit())
1251 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1252 skb->dev->name);
1253 return -EIO;
14d0263f
SH		 1254}
1255
1256static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1257{
1258 struct sk_buff *skb = re->skb;
1259 int i;
1260
7cd26ce5 1261 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
14d0263f
SH		 1262 PCI_DMA_FROMDEVICE);
1263
1264 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1265 pci_unmap_page(pdev, re->frag_addr[i],
1266 skb_shinfo(skb)->frags[i].size,
1267 PCI_DMA_FROMDEVICE);
1268}
793b883e 1269
cd28ab6a
SH		 1270/* Tell chip where to start receive checksum.
1271 * Actually has two checksums, but set both same to avoid possible byte
1272 * order problems.
1273 */
793b883e 1274static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1275{
ea76e635 1276 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1277
ea76e635
SH		 1278 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1279 le->ctrl = 0;
1280 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1281
ea76e635
SH		 1282 sky2_write32(sky2->hw,
1283 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
f5d64037 1284 (sky2->netdev->features & NETIF_F_RXCSUM)
0ea065e5 1285 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1286}
1287
bf73130d 1288/* Enable/disable receive hash calculation (RSS) */
f5d64037 1289static void rx_set_rss(struct net_device *dev, u32 features)
bf73130d
SH		 1290{
1291 struct sky2_port *sky2 = netdev_priv(dev);
1292 struct sky2_hw *hw = sky2->hw;
1293 int i, nkeys = 4;
1294
1295 /* Supports IPv6 and other modes */
1296 if (hw->flags & SKY2_HW_NEW_LE) {
1297 nkeys = 10;
1298 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1299 }
1300
1301 /* Program RSS initial values */
f5d64037 1302 if (features & NETIF_F_RXHASH) {
bf73130d
SH		 1303 u32 key[nkeys];
1304
1305 get_random_bytes(key, nkeys * sizeof(u32));
1306 for (i = 0; i < nkeys; i++)
1307 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1308 key[i]);
1309
1310 /* Need to turn on (undocumented) flag to make hashing work */
1311 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1312 RX_STFW_ENA);
1313
1314 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1315 BMU_ENA_RX_RSS_HASH);
1316 } else
1317 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1318 BMU_DIS_RX_RSS_HASH);
1319}
1320
6b1a3aef
SH		 1321/*
1322 * The RX Stop command will not work for Yukon-2 if the BMU does not
1323 * reach the end of packet and since we can't make sure that we have
1324 * incoming data, we must reset the BMU while it is not doing a DMA
1325 * transfer. Since it is possible that the RX path is still active,
1326 * the RX RAM buffer will be stopped first, so any possible incoming
1327 * data will not trigger a DMA. After the RAM buffer is stopped, the
1328 * BMU is polled until any DMA in progress is ended and only then it
1329 * will be reset.
1330 */
1331static void sky2_rx_stop(struct sky2_port *sky2)
1332{
1333 struct sky2_hw *hw = sky2->hw;
1334 unsigned rxq = rxqaddr[sky2->port];
1335 int i;
1336
1337 /* disable the RAM Buffer receive queue */
1338 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1339
1340 for (i = 0; i < 0xffff; i++)
1341 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1342 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1343 goto stopped;
1344
ada1db5c 1345 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef
SH		 1346stopped:
1347 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1348
1349 /* reset the Rx prefetch unit */
1350 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1351 mmiowb();
6b1a3aef 1352}
793b883e 1353
d571b694 1354/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1355static void sky2_rx_clean(struct sky2_port *sky2)
1356{
1357 unsigned i;
1358
1359 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1360 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1361 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1362
1363 if (re->skb) {
14d0263f 1364 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1365 kfree_skb(re->skb);
1366 re->skb = NULL;
1367 }
1368 }
1369}
1370
ef743d33
SH		 1371/* Basic MII support */
1372static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1373{
1374 struct mii_ioctl_data *data = if_mii(ifr);
1375 struct sky2_port *sky2 = netdev_priv(dev);
1376 struct sky2_hw *hw = sky2->hw;
1377 int err = -EOPNOTSUPP;
1378
1379 if (!netif_running(dev))
1380 return -ENODEV; /* Phy still in reset */
1381
d89e1343 1382 switch (cmd) {
ef743d33
SH		 1383 case SIOCGMIIPHY:
1384 data->phy_id = PHY_ADDR_MARV;
1385
1386 /* fallthru */
1387 case SIOCGMIIREG: {
1388 u16 val = 0;
91c86df5 1389
e07b1aa8 1390 spin_lock_bh(&sky2->phy_lock);
ef743d33 1391 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1392 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1393
ef743d33
SH		 1394 data->val_out = val;
1395 break;
1396 }
1397
1398 case SIOCSMIIREG:
e07b1aa8 1399 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1400 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1401 data->val_in);
e07b1aa8 1402 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1403 break;
1404 }
1405 return err;
1406}
1407
f5d64037 1408#define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
d494eacd 1409
f5d64037 1410static void sky2_vlan_mode(struct net_device *dev, u32 features)
d494eacd
SH		 1411{
1412 struct sky2_port *sky2 = netdev_priv(dev);
1413 struct sky2_hw *hw = sky2->hw;
1414 u16 port = sky2->port;
1415
f5d64037 1416 if (features & NETIF_F_HW_VLAN_RX)
86aa7785
SH		 1417 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1418 RX_VLAN_STRIP_ON);
1419 else
1420 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1421 RX_VLAN_STRIP_OFF);
d494eacd 1422
f5d64037 1423 if (features & NETIF_F_HW_VLAN_TX) {
86aa7785
SH		 1424 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1425 TX_VLAN_TAG_ON);
f5d64037
MM		 1426
1427 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1428 } else {
86aa7785
SH		 1429 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1430 TX_VLAN_TAG_OFF);
d1f13708 1431
86aa7785 1432 /* Can't do transmit offload of vlan without hw vlan */
f5d64037 1433 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
86aa7785 1434 }
d1f13708 1435}
d1f13708 1436
bd1c6869
SH		 1437/* Amount of required worst case padding in rx buffer */
1438static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1439{
1440 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1441}
1442
82788c7a 1443/*
14d0263f
SH		 1444 * Allocate an skb for receiving. If the MTU is large enough
1445 * make the skb non-linear with a fragment list of pages.
82788c7a 1446 */
68ac3191 1447static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
82788c7a
SH		 1448{
1449 struct sk_buff *skb;
14d0263f 1450 int i;
82788c7a 1451
68ac3191
ED		 1452 skb = __netdev_alloc_skb(sky2->netdev,
1453 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1454 gfp);
bd1c6869
SH		 1455 if (!skb)
1456 goto nomem;
1457
39dbd958 1458 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1459 unsigned char *start;
1460 /*
1461 * Workaround for a bug in FIFO that cause hang
1462 * if the FIFO if the receive buffer is not 64 byte aligned.
1463 * The buffer returned from netdev_alloc_skb is
1464 * aligned except if slab debugging is enabled.
1465 */
f03b8654
SH		 1466 start = PTR_ALIGN(skb->data, 8);
1467 skb_reserve(skb, start - skb->data);
bd1c6869 1468 } else
f03b8654 1469 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1470
1471 for (i = 0; i < sky2->rx_nfrags; i++) {
68ac3191 1472 struct page *page = alloc_page(gfp);
14d0263f
SH		 1473
1474 if (!page)
1475 goto free_partial;
1476 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1477 }
1478
1479 return skb;
14d0263f
SH		 1480free_partial:
1481 kfree_skb(skb);
1482nomem:
1483 return NULL;
82788c7a
SH		 1484}
1485
55c9dd35
SH		 1486static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1487{
1488 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1489}
1490
200ac492
MM		 1491static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1492{
1493 struct sky2_hw *hw = sky2->hw;
1494 unsigned i;
1495
1496 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1497
1498 /* Fill Rx ring */
1499 for (i = 0; i < sky2->rx_pending; i++) {
1500 struct rx_ring_info *re = sky2->rx_ring + i;
1501
68ac3191 1502 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
200ac492
MM		 1503 if (!re->skb)
1504 return -ENOMEM;
1505
1506 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1507 dev_kfree_skb(re->skb);
1508 re->skb = NULL;
1509 return -ENOMEM;
1510 }
1511 }
1512 return 0;
1513}
1514
cd28ab6a 1515/*
200ac492 1516 * Setup receiver buffer pool.
14d0263f
SH		 1517 * Normal case this ends up creating one list element for skb
1518 * in the receive ring. Worst case if using large MTU and each
1519 * allocation falls on a different 64 bit region, that results
1520 * in 6 list elements per ring entry.
1521 * One element is used for checksum enable/disable, and one
1522 * extra to avoid wrap.
cd28ab6a 1523 */
200ac492 1524static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1525{
6b1a3aef 1526 struct sky2_hw *hw = sky2->hw;
14d0263f 1527 struct rx_ring_info *re;
6b1a3aef 1528 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1529 unsigned i, thresh;
cd28ab6a 1530
6b1a3aef 1531 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1532 sky2_qset(hw, rxq);
977bdf06 1533
c3905bc4 1534 /* On PCI express lowering the watermark gives better performance */
1a10ccae 1535 if (pci_is_pcie(hw->pdev))
c3905bc4
SH		 1536 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1537
1538 /* These chips have no ram buffer?
1539 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1540 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1541 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1542 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1543
6b1a3aef
SH		 1544 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1545
ea76e635
SH		 1546 if (!(hw->flags & SKY2_HW_NEW_LE))
1547 rx_set_checksum(sky2);
14d0263f 1548
bf73130d 1549 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
f5d64037 1550 rx_set_rss(sky2->netdev, sky2->netdev->features);
bf73130d 1551
200ac492 1552 /* submit Rx ring */
793b883e 1553 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1554 re = sky2->rx_ring + i;
14d0263f 1555 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1556 }
1557
a1433ac4
SH		 1558 /*
1559 * The receiver hangs if it receives frames larger than the
1560 * packet buffer. As a workaround, truncate oversize frames, but
1561 * the register is limited to 9 bits, so if you do frames > 2052
1562 * you better get the MTU right!
1563 */
39ef110b 1564 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1565 if (thresh > 0x1ff)
1566 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1567 else {
1568 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1569 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1570 }
1571
6b1a3aef 1572 /* Tell chip about available buffers */
55c9dd35 1573 sky2_rx_update(sky2, rxq);
877c8570
SH		 1574
1575 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1576 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1577 /*
1578 * Disable flushing of non ASF packets;
1579 * must be done after initializing the BMUs;
1580 * drivers without ASF support should do this too, otherwise
1581 * it may happen that they cannot run on ASF devices;
1582 * remember that the MAC FIFO isn't reset during initialization.
1583 */
1584 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1585 }
1586
1587 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1588 /* Enable RX Home Address & Routing Header checksum fix */
1589 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1590 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1591
1592 /* Enable TX Home Address & Routing Header checksum fix */
1593 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1594 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1595 }
cd28ab6a
SH		 1596}
1597
90bbebb4
MM		 1598static int sky2_alloc_buffers(struct sky2_port *sky2)
1599{
1600 struct sky2_hw *hw = sky2->hw;
1601
1602 /* must be power of 2 */
1603 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1604 sky2->tx_ring_size *
1605 sizeof(struct sky2_tx_le),
1606 &sky2->tx_le_map);
1607 if (!sky2->tx_le)
1608 goto nomem;
1609
1610 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1611 GFP_KERNEL);
1612 if (!sky2->tx_ring)
1613 goto nomem;
1614
1615 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1616 &sky2->rx_le_map);
1617 if (!sky2->rx_le)
1618 goto nomem;
1619 memset(sky2->rx_le, 0, RX_LE_BYTES);
1620
1621 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1622 GFP_KERNEL);
1623 if (!sky2->rx_ring)
1624 goto nomem;
1625
200ac492 1626 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1627nomem:
1628 return -ENOMEM;
1629}
1630
1631static void sky2_free_buffers(struct sky2_port *sky2)
1632{
1633 struct sky2_hw *hw = sky2->hw;
1634
200ac492
MM		 1635 sky2_rx_clean(sky2);
1636
90bbebb4
MM		 1637 if (sky2->rx_le) {
1638 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1639 sky2->rx_le, sky2->rx_le_map);
1640 sky2->rx_le = NULL;
1641 }
1642 if (sky2->tx_le) {
1643 pci_free_consistent(hw->pdev,
1644 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1645 sky2->tx_le, sky2->tx_le_map);
1646 sky2->tx_le = NULL;
1647 }
1648 kfree(sky2->tx_ring);
1649 kfree(sky2->rx_ring);
1650
1651 sky2->tx_ring = NULL;
1652 sky2->rx_ring = NULL;
1653}
1654
ea0f71e5 1655static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1656{
cd28ab6a
SH		 1657 struct sky2_hw *hw = sky2->hw;
1658 unsigned port = sky2->port;
ea0f71e5
MM		 1659 u32 ramsize;
1660 int cap;
843a46f4 1661 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1662
ea0f71e5
MM		 1663 tx_init(sky2);
1664
ee7abb04
SH		 1665 /*
1666 * On dual port PCI-X card, there is an problem where status
1667 * can be received out of order due to split transactions
843a46f4 1668 */
ee7abb04
SH		 1669 if (otherdev && netif_running(otherdev) &&
1670 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1671 u16 cmd;
1672
b32f40c4 1673 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1674 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1675 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1676 }
cd28ab6a 1677
cd28ab6a
SH		 1678 sky2_mac_init(hw, port);
1679
e0c28116
SH		 1680 /* Register is number of 4K blocks on internal RAM buffer. */
1681 ramsize = sky2_read8(hw, B2_E_0) * 4;
1682 if (ramsize > 0) {
67712901 1683 u32 rxspace;
cd28ab6a 1684
ada1db5c 1685 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1686 if (ramsize < 16)
1687 rxspace = ramsize / 2;
1688 else
1689 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1690
67712901
SH		 1691 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1692 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1693
1694 /* Make sure SyncQ is disabled */
1695 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1696 RB_RST_SET);
1697 }
793b883e 1698
af4ed7e6 1699 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1700
69161611
SH		 1701 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1702 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1703 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1704
977bdf06 1705 /* Set almost empty threshold */
8e95a202
JP		 1706 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1707 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1708 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1709
6b1a3aef 1710 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1711 sky2->tx_ring_size - 1);
cd28ab6a 1712
f5d64037
MM		 1713 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1714 netdev_update_features(sky2->netdev);
d494eacd 1715
200ac492 1716 sky2_rx_start(sky2);
ea0f71e5
MM		 1717}
1718
1719/* Bring up network interface. */
1720static int sky2_up(struct net_device *dev)
1721{
1722 struct sky2_port *sky2 = netdev_priv(dev);
1723 struct sky2_hw *hw = sky2->hw;
1724 unsigned port = sky2->port;
1725 u32 imask;
1726 int err;
1727
1728 netif_carrier_off(dev);
1729
1730 err = sky2_alloc_buffers(sky2);
1731 if (err)
1732 goto err_out;
1733
1734 sky2_hw_up(sky2);
cd28ab6a 1735
cd28ab6a 1736 /* Enable interrupts from phy/mac for port */
e07b1aa8 1737 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1738 imask |= portirq_msk[port];
e07b1aa8 1739 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1740 sky2_read32(hw, B0_IMSK);
e07b1aa8 1741
6c35abae 1742 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1743
cd28ab6a
SH		 1744 return 0;
1745
1746err_out:
90bbebb4 1747 sky2_free_buffers(sky2);
cd28ab6a
SH		 1748 return err;
1749}
1750
793b883e 1751/* Modular subtraction in ring */
ee5f68fe 1752static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1753{
ee5f68fe 1754 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1755}
cd28ab6a 1756
793b883e
SH		 1757/* Number of list elements available for next tx */
1758static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1759{
ee5f68fe 1760 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1761}
1762
793b883e 1763/* Estimate of number of transmit list elements required */
28bd181a 1764static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1765{
793b883e
SH		 1766 unsigned count;
1767
07e31637
SH		 1768 count = (skb_shinfo(skb)->nr_frags + 1)
1769 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1770
89114afd 1771 if (skb_is_gso(skb))
793b883e 1772 ++count;
07e31637
SH		 1773 else if (sizeof(dma_addr_t) == sizeof(u32))
1774 ++count; /* possible vlan */
793b883e 1775
84fa7933 1776 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1777 ++count;
1778
1779 return count;
cd28ab6a
SH		 1780}
1781
f6815077 1782static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1783{
1784 if (re->flags & TX_MAP_SINGLE)
7cd26ce5
FT		 1785 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1786 dma_unmap_len(re, maplen),
6b84daca
SH		 1787 PCI_DMA_TODEVICE);
1788 else if (re->flags & TX_MAP_PAGE)
7cd26ce5
FT		 1789 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1790 dma_unmap_len(re, maplen),
6b84daca 1791 PCI_DMA_TODEVICE);
f6815077 1792 re->flags = 0;
6b84daca
SH		 1793}
1794
793b883e
SH		 1795/*
1796 * Put one packet in ring for transmit.
1797 * A single packet can generate multiple list elements, and
1798 * the number of ring elements will probably be less than the number
1799 * of list elements used.
1800 */
61357325
SH		 1801static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1802 struct net_device *dev)
cd28ab6a
SH		 1803{
1804 struct sky2_port *sky2 = netdev_priv(dev);
1805 struct sky2_hw *hw = sky2->hw;
d1f13708 1806 struct sky2_tx_le *le = NULL;
6cdbbdf3 1807 struct tx_ring_info *re;
9b289c33 1808 unsigned i, len;
cd28ab6a 1809 dma_addr_t mapping;
5dce95e5
SH		 1810 u32 upper;
1811 u16 slot;
cd28ab6a
SH		 1812 u16 mss;
1813 u8 ctrl;
1814
2bb8c262
SH		 1815 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1816 return NETDEV_TX_BUSY;
cd28ab6a 1817
cd28ab6a
SH		 1818 len = skb_headlen(skb);
1819 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1820
454e6cb6
SH		 1821 if (pci_dma_mapping_error(hw->pdev, mapping))
1822 goto mapping_error;
1823
9b289c33 1824 slot = sky2->tx_prod;
6c35abae
JP		 1825 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1826 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1827
86c6887e 1828 /* Send high bits if needed */
5dce95e5
SH		 1829 upper = upper_32_bits(mapping);
1830 if (upper != sky2->tx_last_upper) {
9b289c33 1831 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1832 le->addr = cpu_to_le32(upper);
1833 sky2->tx_last_upper = upper;
793b883e 1834 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1835 }
cd28ab6a
SH		 1836
1837 /* Check for TCP Segmentation Offload */
7967168c 1838 mss = skb_shinfo(skb)->gso_size;
793b883e 1839 if (mss != 0) {
ea76e635
SH		 1840
1841 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1842 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1843
1844 if (mss != sky2->tx_last_mss) {
9b289c33 1845 le = get_tx_le(sky2, &slot);
69161611 1846 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1847
1848 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1849 le->opcode = OP_MSS | HW_OWNER;
1850 else
1851 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1852 sky2->tx_last_mss = mss;
1853 }
cd28ab6a
SH		 1854 }
1855
cd28ab6a 1856 ctrl = 0;
86aa7785 1857
d1f13708 1858 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
eab6d18d 1859 if (vlan_tx_tag_present(skb)) {
d1f13708 1860 if (!le) {
9b289c33 1861 le = get_tx_le(sky2, &slot);
f65b138c 1862 le->addr = 0;
d1f13708 1863 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1864 } else
1865 le->opcode |= OP_VLAN;
1866 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1867 ctrl |= INS_VLAN;
1868 }
d1f13708
SH		 1869
1870 /* Handle TCP checksum offload */
84fa7933 1871 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1872 /* On Yukon EX (some versions) encoding change. */
ea76e635 1873 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1874 ctrl |= CALSUM; /* auto checksum */
1875 else {
1876 const unsigned offset = skb_transport_offset(skb);
1877 u32 tcpsum;
1878
1879 tcpsum = offset << 16; /* sum start */
1880 tcpsum |= offset + skb->csum_offset; /* sum write */
1881
1882 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1883 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1884 ctrl |= UDPTCP;
1885
1886 if (tcpsum != sky2->tx_tcpsum) {
1887 sky2->tx_tcpsum = tcpsum;
1888
9b289c33 1889 le = get_tx_le(sky2, &slot);
69161611
SH		 1890 le->addr = cpu_to_le32(tcpsum);
1891 le->length = 0; /* initial checksum value */
1892 le->ctrl = 1; /* one packet */
1893 le->opcode = OP_TCPLISW | HW_OWNER;
1894 }
1d179332 1895 }
cd28ab6a
SH		 1896 }
1897
6b84daca
SH		 1898 re = sky2->tx_ring + slot;
1899 re->flags = TX_MAP_SINGLE;
7cd26ce5
FT		 1900 dma_unmap_addr_set(re, mapaddr, mapping);
1901 dma_unmap_len_set(re, maplen, len);
6b84daca 1902
9b289c33 1903 le = get_tx_le(sky2, &slot);
d6e74b6b 1904 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1905 le->length = cpu_to_le16(len);
1906 le->ctrl = ctrl;
793b883e 1907 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1908
cd28ab6a
SH		 1909
1910 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1911 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1912
1913 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1914 frag->size, PCI_DMA_TODEVICE);
86c6887e 1915
454e6cb6
SH		 1916 if (pci_dma_mapping_error(hw->pdev, mapping))
1917 goto mapping_unwind;
1918
5dce95e5
SH		 1919 upper = upper_32_bits(mapping);
1920 if (upper != sky2->tx_last_upper) {
9b289c33 1921 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1922 le->addr = cpu_to_le32(upper);
1923 sky2->tx_last_upper = upper;
793b883e 1924 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1925 }
1926
6b84daca
SH		 1927 re = sky2->tx_ring + slot;
1928 re->flags = TX_MAP_PAGE;
7cd26ce5
FT		 1929 dma_unmap_addr_set(re, mapaddr, mapping);
1930 dma_unmap_len_set(re, maplen, frag->size);
6b84daca 1931
9b289c33 1932 le = get_tx_le(sky2, &slot);
d6e74b6b 1933 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1934 le->length = cpu_to_le16(frag->size);
1935 le->ctrl = ctrl;
793b883e 1936 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1937 }
6cdbbdf3 1938
6b84daca 1939 re->skb = skb;
cd28ab6a
SH		 1940 le->ctrl |= EOP;
1941
9b289c33
MM		 1942 sky2->tx_prod = slot;
1943
97bda706
SH		 1944 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1945 netif_stop_queue(dev);
b19666d9 1946
290d4de5 1947 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1948
cd28ab6a 1949 return NETDEV_TX_OK;
454e6cb6
SH		 1950
1951mapping_unwind:
ee5f68fe 1952 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1953 re = sky2->tx_ring + i;
1954
6b84daca 1955 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1956 }
1957
454e6cb6
SH		 1958mapping_error:
1959 if (net_ratelimit())
1960 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1961 dev_kfree_skb(skb);
1962 return NETDEV_TX_OK;
cd28ab6a
SH		 1963}
1964
cd28ab6a 1965/*
793b883e
SH		 1966 * Free ring elements from starting at tx_cons until "done"
1967 *
481cea4a
SH		 1968 * NB:
1969 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1970 * buffers so make sure not to free skb to early.
481cea4a
SH		 1971 * 2. This may run in parallel start_xmit because the it only
1972 * looks at the tail of the queue of FIFO (tx_cons), not
1973 * the head (tx_prod)
cd28ab6a 1974 */
d11c13e7 1975static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1976{
d11c13e7 1977 struct net_device *dev = sky2->netdev;
291ea614 1978 unsigned idx;
cd28ab6a 1979
ee5f68fe 1980 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1981
291ea614 1982 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1983 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1984 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1985 struct sk_buff *skb = re->skb;
291ea614 1986
6b84daca 1987 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1988
6b84daca 1989 if (skb) {
6c35abae
JP		 1990 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1991 "tx done %u\n", idx);
3cf26753 1992
0885a30b 1993 u64_stats_update_begin(&sky2->tx_stats.syncp);
1994 ++sky2->tx_stats.packets;
1995 sky2->tx_stats.bytes += skb->len;
1996 u64_stats_update_end(&sky2->tx_stats.syncp);
bd1c6869 1997
f6815077 1998 re->skb = NULL;
724b6942 1999 dev_kfree_skb_any(skb);
2bf56fe2 2000
ee5f68fe 2001 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 2002 }
793b883e 2003 }
793b883e 2004
291ea614 2005 sky2->tx_cons = idx;
50432cb5 2006 smp_mb();
cd28ab6a
SH		 2007}
2008
264bb4fa 2009static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 2010{
a510996b
MM		 2011 /* Disable Force Sync bit and Enable Alloc bit */
2012 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2013 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2014
2015 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2016 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2017 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2018
2019 /* Reset the PCI FIFO of the async Tx queue */
2020 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2021 BMU_RST_SET | BMU_FIFO_RST);
2022
2023 /* Reset the Tx prefetch units */
2024 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2025 PREF_UNIT_RST_SET);
2026
2027 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2028 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2029}
2030
f2b31cb3 2031static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 2032{
cd28ab6a
SH		 2033 struct sky2_hw *hw = sky2->hw;
2034 unsigned port = sky2->port;
f2b31cb3 2035 u16 ctrl;
cd28ab6a 2036
d104acaf
SH		 2037 /* Force flow control off */
2038 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 2039
cd28ab6a
SH		 2040 /* Stop transmitter */
2041 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2042 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2043
2044 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 2045 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 2046
2047 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 2048 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 2049 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2050
2051 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2052
2053 /* Workaround shared GMAC reset */
8e95a202
JP		 2054 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2055 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 2056 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2057
cd28ab6a 2058 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 2059
6c83504f
SH		 2060 /* Force any delayed status interrrupt and NAPI */
2061 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2062 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2063 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2064 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2065
a947a39d
MM		 2066 sky2_rx_stop(sky2);
2067
0da6d7b3 2068 spin_lock_bh(&sky2->phy_lock);
b96936da 2069 sky2_phy_power_down(hw, port);
0da6d7b3 2070 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 2071
264bb4fa
MM		 2072 sky2_tx_reset(hw, port);
2073
481cea4a
SH		 2074 /* Free any pending frames stuck in HW queue */
2075 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 2076}
2077
2078/* Network shutdown */
2079static int sky2_down(struct net_device *dev)
2080{
2081 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 2082 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 2083
2084 /* Never really got started! */
2085 if (!sky2->tx_le)
2086 return 0;
2087
6c35abae 2088 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 2089
8a0c9228
MM		 2090 /* Disable port IRQ */
2091 sky2_write32(hw, B0_IMSK,
2092 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2093 sky2_read32(hw, B0_IMSK);
2094
2095 synchronize_irq(hw->pdev->irq);
2096 napi_synchronize(&hw->napi);
2097
f2b31cb3 2098 sky2_hw_down(sky2);
481cea4a 2099
90bbebb4 2100 sky2_free_buffers(sky2);
1b537565 2101
cd28ab6a
SH		 2102 return 0;
2103}
2104
2105static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2106{
ea76e635 2107 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 2108 return SPEED_1000;
2109
05745c4a
SH		 2110 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2111 if (aux & PHY_M_PS_SPEED_100)
2112 return SPEED_100;
2113 else
2114 return SPEED_10;
2115 }
cd28ab6a
SH		 2116
2117 switch (aux & PHY_M_PS_SPEED_MSK) {
2118 case PHY_M_PS_SPEED_1000:
2119 return SPEED_1000;
2120 case PHY_M_PS_SPEED_100:
2121 return SPEED_100;
2122 default:
2123 return SPEED_10;
2124 }
2125}
2126
2127static void sky2_link_up(struct sky2_port *sky2)
2128{
2129 struct sky2_hw *hw = sky2->hw;
2130 unsigned port = sky2->port;
16ad91e1
SH		 2131 static const char *fc_name[] = {
2132 [FC_NONE] = "none",
2133 [FC_TX] = "tx",
2134 [FC_RX] = "rx",
2135 [FC_BOTH] = "both",
2136 };
cd28ab6a 2137
8e11680f 2138 sky2_set_ipg(sky2);
2139
38000a94 2140 sky2_enable_rx_tx(sky2);
cd28ab6a
SH		 2141
2142 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2143
2144 netif_carrier_on(sky2->netdev);
cd28ab6a 2145
75e80683 2146 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2147
cd28ab6a 2148 /* Turn on link LED */
793b883e 2149 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2150 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2151
6c35abae
JP		 2152 netif_info(sky2, link, sky2->netdev,
2153 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2154 sky2->speed,
2155 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2156 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2157}
2158
2159static void sky2_link_down(struct sky2_port *sky2)
2160{
2161 struct sky2_hw *hw = sky2->hw;
2162 unsigned port = sky2->port;
2163 u16 reg;
2164
2165 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2166
2167 reg = gma_read16(hw, port, GM_GP_CTRL);
2168 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2169 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2170
cd28ab6a 2171 netif_carrier_off(sky2->netdev);
cd28ab6a 2172
809aaaae 2173 /* Turn off link LED */
cd28ab6a
SH		 2174 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2175
6c35abae 2176 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2177
cd28ab6a
SH		 2178 sky2_phy_init(hw, port);
2179}
2180
16ad91e1
SH		 2181static enum flow_control sky2_flow(int rx, int tx)
2182{
2183 if (rx)
2184 return tx ? FC_BOTH : FC_RX;
2185 else
2186 return tx ? FC_TX : FC_NONE;
2187}
2188
793b883e
SH		 2189static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2190{
2191 struct sky2_hw *hw = sky2->hw;
2192 unsigned port = sky2->port;
da4c1ff4 2193 u16 advert, lpa;
793b883e 2194
da4c1ff4 2195 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2196 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2197 if (lpa & PHY_M_AN_RF) {
ada1db5c 2198 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2199 return -1;
2200 }
2201
793b883e 2202 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2203 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2204 return -1;
2205 }
2206
793b883e 2207 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2208 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2209
da4c1ff4
SH		 2210 /* Since the pause result bits seem to in different positions on
2211 * different chips. look at registers.
2212 */
ea76e635 2213 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2214 /* Shift for bits in fiber PHY */
2215 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2216 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2217
2218 if (advert & ADVERTISE_1000XPAUSE)
2219 advert |= ADVERTISE_PAUSE_CAP;
2220 if (advert & ADVERTISE_1000XPSE_ASYM)
2221 advert |= ADVERTISE_PAUSE_ASYM;
2222 if (lpa & LPA_1000XPAUSE)
2223 lpa |= LPA_PAUSE_CAP;
2224 if (lpa & LPA_1000XPAUSE_ASYM)
2225 lpa |= LPA_PAUSE_ASYM;
2226 }
793b883e 2227
da4c1ff4
SH		 2228 sky2->flow_status = FC_NONE;
2229 if (advert & ADVERTISE_PAUSE_CAP) {
2230 if (lpa & LPA_PAUSE_CAP)
2231 sky2->flow_status = FC_BOTH;
2232 else if (advert & ADVERTISE_PAUSE_ASYM)
2233 sky2->flow_status = FC_RX;
2234 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2235 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2236 sky2->flow_status = FC_TX;
2237 }
793b883e 2238
8e95a202
JP		 2239 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2240 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2241 sky2->flow_status = FC_NONE;
2eaba1a2 2242
da4c1ff4 2243 if (sky2->flow_status & FC_TX)
793b883e
SH		 2244 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2245 else
2246 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2247
2248 return 0;
2249}
cd28ab6a 2250
e07b1aa8
SH		 2251/* Interrupt from PHY */
2252static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2253{
e07b1aa8
SH		 2254 struct net_device *dev = hw->dev[port];
2255 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2256 u16 istatus, phystat;
2257
ebc646f6
SH		 2258 if (!netif_running(dev))
2259 return;
2260
e07b1aa8
SH		 2261 spin_lock(&sky2->phy_lock);
2262 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2263 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2264
6c35abae
JP		 2265 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2266 istatus, phystat);
cd28ab6a 2267
0ea065e5 2268 if (istatus & PHY_M_IS_AN_COMPL) {
9badba25 2269 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2270 !netif_carrier_ok(dev))
793b883e
SH		 2271 sky2_link_up(sky2);
2272 goto out;
2273 }
cd28ab6a 2274
793b883e
SH		 2275 if (istatus & PHY_M_IS_LSP_CHANGE)
2276 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2277
793b883e
SH		 2278 if (istatus & PHY_M_IS_DUP_CHANGE)
2279 sky2->duplex =
2280 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2281
793b883e
SH		 2282 if (istatus & PHY_M_IS_LST_CHANGE) {
2283 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2284 sky2_link_up(sky2);
793b883e
SH		 2285 else
2286 sky2_link_down(sky2);
cd28ab6a 2287 }
793b883e 2288out:
e07b1aa8 2289 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2290}
2291
0f5aac70
SH		 2292/* Special quick link interrupt (Yukon-2 Optima only) */
2293static void sky2_qlink_intr(struct sky2_hw *hw)
2294{
2295 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2296 u32 imask;
2297 u16 phy;
2298
2299 /* disable irq */
2300 imask = sky2_read32(hw, B0_IMSK);
2301 imask &= ~Y2_IS_PHY_QLNK;
2302 sky2_write32(hw, B0_IMSK, imask);
2303
2304 /* reset PHY Link Detect */
2305 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2306 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2307 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2308 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2309
2310 sky2_link_up(sky2);
2311}
2312
62335ab0 2313/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2314 * and tx queue is full (stopped).
2315 */
cd28ab6a
SH		 2316static void sky2_tx_timeout(struct net_device *dev)
2317{
2318 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2319 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2320
6c35abae 2321 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2322
ada1db5c
JP		 2323 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2324 sky2->tx_cons, sky2->tx_prod,
2325 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2326 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2327
81906791
SH		 2328 /* can't restart safely under softirq */
2329 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2330}
2331
2332static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2333{
6b1a3aef
SH		 2334 struct sky2_port *sky2 = netdev_priv(dev);
2335 struct sky2_hw *hw = sky2->hw;
b628ed98 2336 unsigned port = sky2->port;
6b1a3aef
SH		 2337 int err;
2338 u16 ctl, mode;
e07b1aa8 2339 u32 imask;
cd28ab6a 2340
44dde56d 2341 /* MTU size outside the spec */
cd28ab6a
SH		 2342 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2343 return -EINVAL;
2344
44dde56d 2345 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2346 if (new_mtu > ETH_DATA_LEN &&
2347 (hw->chip_id == CHIP_ID_YUKON_FE ||
2348 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2349 return -EINVAL;
2350
6b1a3aef
SH		 2351 if (!netif_running(dev)) {
2352 dev->mtu = new_mtu;
f5d64037 2353 netdev_update_features(dev);
6b1a3aef
SH		 2354 return 0;
2355 }
2356
e07b1aa8 2357 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2358 sky2_write32(hw, B0_IMSK, 0);
2359
018d1c66 2360 dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 2361 napi_disable(&hw->napi);
df01093b 2362 netif_tx_disable(dev);
018d1c66 2363
e07b1aa8
SH		 2364 synchronize_irq(hw->pdev->irq);
2365
39dbd958 2366 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2367 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2368
2369 ctl = gma_read16(hw, port, GM_GP_CTRL);
2370 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2371 sky2_rx_stop(sky2);
2372 sky2_rx_clean(sky2);
cd28ab6a
SH		 2373
2374 dev->mtu = new_mtu;
f5d64037 2375 netdev_update_features(dev);
14d0263f 2376
8e11680f 2377 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2378 if (sky2->speed > SPEED_100)
2379 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2380 else
2381 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
6b1a3aef
SH		 2382
2383 if (dev->mtu > ETH_DATA_LEN)
2384 mode |= GM_SMOD_JUMBO_ENA;
2385
b628ed98 2386 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2387
b628ed98 2388 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2389
200ac492
MM		 2390 err = sky2_alloc_rx_skbs(sky2);
2391 if (!err)
2392 sky2_rx_start(sky2);
2393 else
2394 sky2_rx_clean(sky2);
e07b1aa8 2395 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2396
d1d08d12 2397 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2398 napi_enable(&hw->napi);
2399
1b537565
SH		 2400 if (err)
2401 dev_close(dev);
2402 else {
b628ed98 2403 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2404
1b537565
SH		 2405 netif_wake_queue(dev);
2406 }
2407
cd28ab6a
SH		 2408 return err;
2409}
2410
14d0263f
SH		 2411/* For small just reuse existing skb for next receive */
2412static struct sk_buff *receive_copy(struct sky2_port *sky2,
2413 const struct rx_ring_info *re,
2414 unsigned length)
2415{
2416 struct sk_buff *skb;
2417
89d71a66 2418 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2419 if (likely(skb)) {
14d0263f
SH		 2420 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2421 length, PCI_DMA_FROMDEVICE);
d626f62b 2422 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2423 skb->ip_summed = re->skb->ip_summed;
2424 skb->csum = re->skb->csum;
2425 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2426 length, PCI_DMA_FROMDEVICE);
2427 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2428 skb_put(skb, length);
14d0263f
SH		 2429 }
2430 return skb;
2431}
2432
2433/* Adjust length of skb with fragments to match received data */
2434static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2435 unsigned int length)
2436{
2437 int i, num_frags;
2438 unsigned int size;
2439
2440 /* put header into skb */
2441 size = min(length, hdr_space);
2442 skb->tail += size;
2443 skb->len += size;
2444 length -= size;
2445
2446 num_frags = skb_shinfo(skb)->nr_frags;
2447 for (i = 0; i < num_frags; i++) {
2448 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2449
2450 if (length == 0) {
2451 /* don't need this page */
2452 __free_page(frag->page);
2453 --skb_shinfo(skb)->nr_frags;
2454 } else {
2455 size = min(length, (unsigned) PAGE_SIZE);
2456
2457 frag->size = size;
2458 skb->data_len += size;
2459 skb->truesize += size;
2460 skb->len += size;
2461 length -= size;
2462 }
2463 }
2464}
2465
2466/* Normal packet - take skb from ring element and put in a new one */
2467static struct sk_buff *receive_new(struct sky2_port *sky2,
2468 struct rx_ring_info *re,
2469 unsigned int length)
2470{
3fbd9187 2471 struct sk_buff *skb;
2472 struct rx_ring_info nre;
14d0263f
SH		 2473 unsigned hdr_space = sky2->rx_data_size;
2474
68ac3191 2475 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
3fbd9187 2476 if (unlikely(!nre.skb))
2477 goto nobuf;
2478
2479 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2480 goto nomap;
14d0263f
SH		 2481
2482 skb = re->skb;
2483 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2484 prefetch(skb->data);
3fbd9187 2485 *re = nre;
14d0263f
SH		 2486
2487 if (skb_shinfo(skb)->nr_frags)
2488 skb_put_frags(skb, hdr_space, length);
2489 else
489b10c1 2490 skb_put(skb, length);
14d0263f 2491 return skb;
3fbd9187 2492
2493nomap:
2494 dev_kfree_skb(nre.skb);
2495nobuf:
2496 return NULL;
14d0263f
SH		 2497}
2498
cd28ab6a
SH		 2499/*
2500 * Receive one packet.
d571b694 2501 * For larger packets, get new buffer.
cd28ab6a 2502 */
497d7c86 2503static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2504 u16 length, u32 status)
2505{
497d7c86 2506 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2507 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2508 struct sk_buff *skb = NULL;
d6532232
SH		 2509 u16 count = (status & GMR_FS_LEN) >> 16;
2510
86aa7785
SH		 2511 if (status & GMR_FS_VLAN)
2512 count -= VLAN_HLEN; /* Account for vlan tag */
cd28ab6a 2513
6c35abae
JP		 2514 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2515 "rx slot %u status 0x%x len %d\n",
2516 sky2->rx_next, status, length);
cd28ab6a 2517
793b883e 2518 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2519 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2520
3b12e014
SH		 2521 /* This chip has hardware problems that generates bogus status.
2522 * So do only marginal checking and expect higher level protocols
2523 * to handle crap frames.
2524 */
2525 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2526 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2527 length != count)
2528 goto okay;
2529
42eeea01 2530 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2531 goto error;
2532
42eeea01
SH		 2533 if (!(status & GMR_FS_RX_OK))
2534 goto resubmit;
2535
d6532232
SH		 2536 /* if length reported by DMA does not match PHY, packet was truncated */
2537 if (length != count)
0885a30b 2538 goto error;
71749531 2539
3b12e014 2540okay:
14d0263f
SH		 2541 if (length < copybreak)
2542 skb = receive_copy(sky2, re, length);
2543 else
2544 skb = receive_new(sky2, re, length);
90c30335
SH		 2545
2546 dev->stats.rx_dropped += (skb == NULL);
2547
793b883e 2548resubmit:
14d0263f 2549 sky2_rx_submit(sky2, re);
79e57d32 2550
cd28ab6a
SH		 2551 return skb;
2552
2553error:
7138a0f5 2554 ++dev->stats.rx_errors;
6e15b712 2555
6c35abae
JP		 2556 if (net_ratelimit())
2557 netif_info(sky2, rx_err, dev,
2558 "rx error, status 0x%x length %d\n", status, length);
793b883e 2559
793b883e 2560 goto resubmit;
cd28ab6a
SH		 2561}
2562
e07b1aa8
SH		 2563/* Transmit complete */
2564static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2565{
e07b1aa8 2566 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2567
8a0c9228 2568 if (netif_running(dev)) {
e07b1aa8 2569 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2570
2571 /* Wake unless it's detached, and called e.g. from sky2_down() */
2572 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2573 netif_wake_queue(dev);
2574 }
cd28ab6a
SH		 2575}
2576
37e5a243
SH		 2577static inline void sky2_skb_rx(const struct sky2_port *sky2,
2578 u32 status, struct sk_buff *skb)
2579{
86aa7785
SH		 2580 if (status & GMR_FS_VLAN)
2581 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2582
37e5a243
SH		 2583 if (skb->ip_summed == CHECKSUM_NONE)
2584 netif_receive_skb(skb);
2585 else
2586 napi_gro_receive(&sky2->hw->napi, skb);
2587}
2588
bf15fe99
SH		 2589static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2590 unsigned packets, unsigned bytes)
2591{
0885a30b 2592 struct net_device *dev = hw->dev[port];
2593 struct sky2_port *sky2 = netdev_priv(dev);
bf15fe99 2594
0885a30b 2595 if (packets == 0)
2596 return;
2597
2598 u64_stats_update_begin(&sky2->rx_stats.syncp);
2599 sky2->rx_stats.packets += packets;
2600 sky2->rx_stats.bytes += bytes;
2601 u64_stats_update_end(&sky2->rx_stats.syncp);
2602
2603 dev->last_rx = jiffies;
2604 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
bf15fe99
SH		 2605}
2606
375c5688 2607static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2608{
2609 /* If this happens then driver assuming wrong format for chip type */
2610 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2611
2612 /* Both checksum counters are programmed to start at
2613 * the same offset, so unless there is a problem they
2614 * should match. This failure is an early indication that
2615 * hardware receive checksumming won't work.
2616 */
2617 if (likely((u16)(status >> 16) == (u16)status)) {
2618 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2619 skb->ip_summed = CHECKSUM_COMPLETE;
2620 skb->csum = le16_to_cpu(status);
2621 } else {
2622 dev_notice(&sky2->hw->pdev->dev,
2623 "%s: receive checksum problem (status = %#x)\n",
2624 sky2->netdev->name, status);
2625
f5d64037
MM		 2626 /* Disable checksum offload
2627 * It will be reenabled on next ndo_set_features, but if it's
2628 * really broken, will get disabled again
2629 */
2630 sky2->netdev->features &= ~NETIF_F_RXCSUM;
375c5688 2631 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2632 BMU_DIS_RX_CHKSUM);
2633 }
2634}
2635
bf73130d
SH		 2636static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2637{
2638 struct sk_buff *skb;
2639
2640 skb = sky2->rx_ring[sky2->rx_next].skb;
2641 skb->rxhash = le32_to_cpu(status);
2642}
2643
e07b1aa8 2644/* Process status response ring */
26691830 2645static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2646{
e07b1aa8 2647 int work_done = 0;
bf15fe99
SH		 2648 unsigned int total_bytes[2] = { 0 };
2649 unsigned int total_packets[2] = { 0 };
a8fd6266 2650
af2a58ac 2651 rmb();
26691830 2652 do {
55c9dd35 2653 struct sky2_port *sky2;
13210ce5 2654 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2655 unsigned port;
13210ce5 2656 struct net_device *dev;
cd28ab6a 2657 struct sk_buff *skb;
cd28ab6a
SH		 2658 u32 status;
2659 u16 length;
ab5adecb
SH		 2660 u8 opcode = le->opcode;
2661
2662 if (!(opcode & HW_OWNER))
2663 break;
cd28ab6a 2664
efe91932 2665 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
bea86103 2666
ab5adecb 2667 port = le->css & CSS_LINK_BIT;
69161611 2668 dev = hw->dev[port];
13210ce5 2669 sky2 = netdev_priv(dev);
f65b138c
SH		 2670 length = le16_to_cpu(le->length);
2671 status = le32_to_cpu(le->status);
cd28ab6a 2672
ab5adecb
SH		 2673 le->opcode = 0;
2674 switch (opcode & ~HW_OWNER) {
cd28ab6a 2675 case OP_RXSTAT:
bf15fe99
SH		 2676 total_packets[port]++;
2677 total_bytes[port] += length;
90c30335 2678
497d7c86 2679 skb = sky2_receive(dev, length, status);
90c30335 2680 if (!skb)
55c9dd35 2681 break;
13210ce5 2682
69161611 2683 /* This chip reports checksum status differently */
05745c4a 2684 if (hw->flags & SKY2_HW_NEW_LE) {
f5d64037 2685 if ((dev->features & NETIF_F_RXCSUM) &&
69161611
SH		 2686 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2687 (le->css & CSS_TCPUDPCSOK))
2688 skb->ip_summed = CHECKSUM_UNNECESSARY;
2689 else
2690 skb->ip_summed = CHECKSUM_NONE;
2691 }
2692
13210ce5 2693 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2694
37e5a243 2695 sky2_skb_rx(sky2, status, skb);
13210ce5 2696
22e11703 2697 /* Stop after net poll weight */
13210ce5
SH		 2698 if (++work_done >= to_do)
2699 goto exit_loop;
cd28ab6a
SH		 2700 break;
2701
d1f13708
SH		 2702 case OP_RXVLAN:
2703 sky2->rx_tag = length;
2704 break;
2705
2706 case OP_RXCHKSVLAN:
2707 sky2->rx_tag = length;
2708 /* fall through */
cd28ab6a 2709 case OP_RXCHKS:
f5d64037 2710 if (likely(dev->features & NETIF_F_RXCSUM))
375c5688 2711 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2712 break;
2713
bf73130d
SH		 2714 case OP_RSS_HASH:
2715 sky2_rx_hash(sky2, status);
2716 break;
2717
cd28ab6a 2718 case OP_TXINDEXLE:
13b97b74 2719 /* TX index reports status for both ports */
f55925d7 2720 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2721 if (hw->dev[1])
2722 sky2_tx_done(hw->dev[1],
2723 ((status >> 24) & 0xff)
2724 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2725 break;
2726
cd28ab6a
SH		 2727 default:
2728 if (net_ratelimit())
ada1db5c 2729 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2730 }
26691830 2731 } while (hw->st_idx != idx);
cd28ab6a 2732
fe2a24df
SH		 2733 /* Fully processed status ring so clear irq */
2734 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2735
13210ce5 2736exit_loop:
bf15fe99
SH		 2737 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2738 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2739
e07b1aa8 2740 return work_done;
cd28ab6a
SH		 2741}
2742
2743static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2744{
2745 struct net_device *dev = hw->dev[port];
2746
3be92a70 2747 if (net_ratelimit())
ada1db5c 2748 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2749
2750 if (status & Y2_IS_PAR_RD1) {
3be92a70 2751 if (net_ratelimit())
ada1db5c 2752 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2753 /* Clear IRQ */
2754 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2755 }
2756
2757 if (status & Y2_IS_PAR_WR1) {
3be92a70 2758 if (net_ratelimit())
ada1db5c 2759 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2760
2761 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2762 }
2763
2764 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2765 if (net_ratelimit())
ada1db5c 2766 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2767 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2768 }
2769
2770 if (status & Y2_IS_PAR_RX1) {
3be92a70 2771 if (net_ratelimit())
ada1db5c 2772 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2773 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2774 }
2775
2776 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2777 if (net_ratelimit())
ada1db5c 2778 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2779 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2780 }
2781}
2782
2783static void sky2_hw_intr(struct sky2_hw *hw)
2784{
555382cb 2785 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2786 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2787 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2788
2789 status &= hwmsk;
cd28ab6a 2790
793b883e 2791 if (status & Y2_IS_TIST_OV)
cd28ab6a 2792 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2793
2794 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2795 u16 pci_err;
2796
a40ccc68 2797 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2798 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2799 if (net_ratelimit())
555382cb 2800 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2801 pci_err);
cd28ab6a 2802
b32f40c4 2803 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2804 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2805 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2806 }
2807
2808 if (status & Y2_IS_PCI_EXP) {
d571b694 2809 /* PCI-Express uncorrectable Error occurred */
555382cb 2810 u32 err;
cd28ab6a 2811
a40ccc68 2812 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2813 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2814 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2815 0xfffffffful);
3be92a70 2816 if (net_ratelimit())
555382cb 2817 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2818
7782c8c4 2819 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2820 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2821 }
2822
2823 if (status & Y2_HWE_L1_MASK)
2824 sky2_hw_error(hw, 0, status);
2825 status >>= 8;
2826 if (status & Y2_HWE_L1_MASK)
2827 sky2_hw_error(hw, 1, status);
2828}
2829
2830static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2831{
2832 struct net_device *dev = hw->dev[port];
2833 struct sky2_port *sky2 = netdev_priv(dev);
2834 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2835
6c35abae 2836 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2837
a3caeada
SH		 2838 if (status & GM_IS_RX_CO_OV)
2839 gma_read16(hw, port, GM_RX_IRQ_SRC);
2840
2841 if (status & GM_IS_TX_CO_OV)
2842 gma_read16(hw, port, GM_TX_IRQ_SRC);
2843
cd28ab6a 2844 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2845 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2846 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2847 }
2848
2849 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2850 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2851 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2852 }
cd28ab6a
SH		 2853}
2854
40b01727 2855/* This should never happen it is a bug. */
c119731d 2856static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2857{
2858 struct net_device *dev = hw->dev[port];
c119731d 2859 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2860
ada1db5c 2861 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2862 dev->name, (unsigned) q, (unsigned) idx,
2863 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2864
40b01727 2865 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2866}
cd28ab6a 2867
75e80683
SH		 2868static int sky2_rx_hung(struct net_device *dev)
2869{
2870 struct sky2_port *sky2 = netdev_priv(dev);
2871 struct sky2_hw *hw = sky2->hw;
2872 unsigned port = sky2->port;
2873 unsigned rxq = rxqaddr[port];
2874 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2875 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2876 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2877 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2878
2879 /* If idle and MAC or PCI is stuck */
2880 if (sky2->check.last == dev->last_rx &&
2881 ((mac_rp == sky2->check.mac_rp &&
2882 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2883 /* Check if the PCI RX hang */
2884 (fifo_rp == sky2->check.fifo_rp &&
2885 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2886 netdev_printk(KERN_DEBUG, dev,
2887 "hung mac %d:%d fifo %d (%d:%d)\n",
2888 mac_lev, mac_rp, fifo_lev,
2889 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2890 return 1;
2891 } else {
2892 sky2->check.last = dev->last_rx;
2893 sky2->check.mac_rp = mac_rp;
2894 sky2->check.mac_lev = mac_lev;
2895 sky2->check.fifo_rp = fifo_rp;
2896 sky2->check.fifo_lev = fifo_lev;
2897 return 0;
2898 }
2899}
2900
32c2c300 2901static void sky2_watchdog(unsigned long arg)
d27ed387 2902{
01bd7564 2903 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2904
75e80683 2905 /* Check for lost IRQ once a second */
32c2c300 2906 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2907 napi_schedule(&hw->napi);
75e80683
SH		 2908 } else {
2909 int i, active = 0;
2910
2911 for (i = 0; i < hw->ports; i++) {
bea3348e 2912 struct net_device *dev = hw->dev[i];
75e80683
SH		 2913 if (!netif_running(dev))
2914 continue;
2915 ++active;
2916
2917 /* For chips with Rx FIFO, check if stuck */
39dbd958 2918 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2919 sky2_rx_hung(dev)) {
ada1db5c 2920 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2921 schedule_work(&hw->restart_work);
2922 return;
2923 }
2924 }
2925
2926 if (active == 0)
2927 return;
32c2c300 2928 }
01bd7564 2929
75e80683 2930 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2931}
2932
40b01727
SH		 2933/* Hardware/software error handling */
2934static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2935{
40b01727
SH		 2936 if (net_ratelimit())
2937 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2938
1e5f1283
SH		 2939 if (status & Y2_IS_HW_ERR)
2940 sky2_hw_intr(hw);
d257924e 2941
1e5f1283
SH		 2942 if (status & Y2_IS_IRQ_MAC1)
2943 sky2_mac_intr(hw, 0);
cd28ab6a 2944
1e5f1283
SH		 2945 if (status & Y2_IS_IRQ_MAC2)
2946 sky2_mac_intr(hw, 1);
cd28ab6a 2947
1e5f1283 2948 if (status & Y2_IS_CHK_RX1)
c119731d 2949 sky2_le_error(hw, 0, Q_R1);
d257924e 2950
1e5f1283 2951 if (status & Y2_IS_CHK_RX2)
c119731d 2952 sky2_le_error(hw, 1, Q_R2);
d257924e 2953
1e5f1283 2954 if (status & Y2_IS_CHK_TXA1)
c119731d 2955 sky2_le_error(hw, 0, Q_XA1);
d257924e 2956
1e5f1283 2957 if (status & Y2_IS_CHK_TXA2)
c119731d 2958 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2959}
2960
bea3348e 2961static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2962{
bea3348e 2963 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2964 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2965 int work_done = 0;
26691830 2966 u16 idx;
40b01727
SH		 2967
2968 if (unlikely(status & Y2_IS_ERROR))
2969 sky2_err_intr(hw, status);
2970
2971 if (status & Y2_IS_IRQ_PHY1)
2972 sky2_phy_intr(hw, 0);
2973
2974 if (status & Y2_IS_IRQ_PHY2)
2975 sky2_phy_intr(hw, 1);
cd28ab6a 2976
0f5aac70
SH		 2977 if (status & Y2_IS_PHY_QLNK)
2978 sky2_qlink_intr(hw);
2979
26691830
SH		 2980 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2981 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2982
2983 if (work_done >= work_limit)
26691830
SH		 2984 goto done;
2985 }
6f535763 2986
26691830
SH		 2987 napi_complete(napi);
2988 sky2_read32(hw, B0_Y2_SP_LISR);
2989done:
6f535763 2990
bea3348e 2991 return work_done;
e07b1aa8
SH		 2992}
2993
7d12e780 2994static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2995{
2996 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2997 u32 status;
2998
2999 /* Reading this mask interrupts as side effect */
3000 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3001 if (status == 0 || status == ~0)
3002 return IRQ_NONE;
793b883e 3003
e07b1aa8 3004 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 3005
3006 napi_schedule(&hw->napi);
793b883e 3007
cd28ab6a
SH		 3008 return IRQ_HANDLED;
3009}
3010
3011#ifdef CONFIG_NET_POLL_CONTROLLER
3012static void sky2_netpoll(struct net_device *dev)
3013{
3014 struct sky2_port *sky2 = netdev_priv(dev);
3015
bea3348e 3016 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 3017}
3018#endif
3019
3020/* Chip internal frequency for clock calculations */
05745c4a 3021static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 3022{
793b883e 3023 switch (hw->chip_id) {
cd28ab6a 3024 case CHIP_ID_YUKON_EC:
5a5b1ea0 3025 case CHIP_ID_YUKON_EC_U:
93745494 3026 case CHIP_ID_YUKON_EX:
ed4d4161 3027 case CHIP_ID_YUKON_SUPR:
0ce8b98d 3028 case CHIP_ID_YUKON_UL_2:
0f5aac70 3029 case CHIP_ID_YUKON_OPT:
4fb99cd6 3030 case CHIP_ID_YUKON_PRM:
3031 case CHIP_ID_YUKON_OP_2:
05745c4a
SH		 3032 return 125;
3033
cd28ab6a 3034 case CHIP_ID_YUKON_FE:
05745c4a
SH		 3035 return 100;
3036
3037 case CHIP_ID_YUKON_FE_P:
3038 return 50;
3039
3040 case CHIP_ID_YUKON_XL:
3041 return 156;
3042
3043 default:
3044 BUG();
cd28ab6a
SH		 3045 }
3046}
3047
fb17358f 3048static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 3049{
fb17358f 3050 return sky2_mhz(hw) * us;
cd28ab6a
SH		 3051}
3052
fb17358f 3053static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 3054{
fb17358f 3055 return clk / sky2_mhz(hw);
cd28ab6a
SH		 3056}
3057
fb17358f 3058
e3173832 3059static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 3060{
b89165f2 3061 u8 t8;
cd28ab6a 3062
167f53d0 3063 /* Enable all clocks and check for bad PCI access */
b32f40c4 3064 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 3065
cd28ab6a 3066 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 3067
cd28ab6a 3068 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 3069 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3070
060b946c 3071 switch (hw->chip_id) {
ea76e635 3072 case CHIP_ID_YUKON_XL:
39dbd958 3073 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
bf73130d
SH		 3074 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3075 hw->flags |= SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3076 break;
3077
3078 case CHIP_ID_YUKON_EC_U:
3079 hw->flags = SKY2_HW_GIGABIT
3080 | SKY2_HW_NEWER_PHY
3081 | SKY2_HW_ADV_POWER_CTL;
3082 break;
3083
3084 case CHIP_ID_YUKON_EX:
3085 hw->flags = SKY2_HW_GIGABIT
3086 | SKY2_HW_NEWER_PHY
3087 | SKY2_HW_NEW_LE
aa5ca96c 3088 | SKY2_HW_ADV_POWER_CTL
3089 | SKY2_HW_RSS_CHKSUM;
ea76e635
SH		 3090
3091 /* New transmit checksum */
3092 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3093 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3094 break;
3095
3096 case CHIP_ID_YUKON_EC:
3097 /* This rev is really old, and requires untested workarounds */
3098 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3099 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3100 return -EOPNOTSUPP;
3101 }
bf73130d 3102 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3103 break;
3104
3105 case CHIP_ID_YUKON_FE:
bf73130d 3106 hw->flags = SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3107 break;
3108
05745c4a
SH		 3109 case CHIP_ID_YUKON_FE_P:
3110 hw->flags = SKY2_HW_NEWER_PHY
3111 | SKY2_HW_NEW_LE
3112 | SKY2_HW_AUTO_TX_SUM
3113 | SKY2_HW_ADV_POWER_CTL;
86aa7785
SH		 3114
3115 /* The workaround for status conflicts VLAN tag detection. */
3116 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
aa5ca96c 3117 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
05745c4a 3118 break;
ed4d4161
SH		 3119
3120 case CHIP_ID_YUKON_SUPR:
3121 hw->flags = SKY2_HW_GIGABIT
3122 | SKY2_HW_NEWER_PHY
3123 | SKY2_HW_NEW_LE
3124 | SKY2_HW_AUTO_TX_SUM
3125 | SKY2_HW_ADV_POWER_CTL;
aa5ca96c 3126
3127 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3128 hw->flags |= SKY2_HW_RSS_CHKSUM;
ed4d4161
SH		 3129 break;
3130
0ce8b98d 3131 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3132 hw->flags = SKY2_HW_GIGABIT
3133 | SKY2_HW_ADV_POWER_CTL;
3134 break;
3135
0f5aac70 3136 case CHIP_ID_YUKON_OPT:
4fb99cd6 3137 case CHIP_ID_YUKON_PRM:
3138 case CHIP_ID_YUKON_OP_2:
0ce8b98d 3139 hw->flags = SKY2_HW_GIGABIT
b338682d 3140 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3141 | SKY2_HW_ADV_POWER_CTL;
3142 break;
3143
ea76e635 3144 default:
b02a9258
SH		 3145 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3146 hw->chip_id);
cd28ab6a
SH		 3147 return -EOPNOTSUPP;
3148 }
3149
ea76e635
SH		 3150 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3151 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3152 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3153
e3173832
SH		 3154 hw->ports = 1;
3155 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3156 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3157 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3158 ++hw->ports;
3159 }
3160
74a61ebf
MM		 3161 if (sky2_read8(hw, B2_E_0))
3162 hw->flags |= SKY2_HW_RAM_BUFFER;
3163
e3173832
SH		 3164 return 0;
3165}
3166
3167static void sky2_reset(struct sky2_hw *hw)
3168{
555382cb 3169 struct pci_dev *pdev = hw->pdev;
e3173832 3170 u16 status;
1a10ccae 3171 int i;
555382cb 3172 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3173
cd28ab6a 3174 /* disable ASF */
acd12dde 3175 if (hw->chip_id == CHIP_ID_YUKON_EX
3176 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3177 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3178 status = sky2_read16(hw, HCU_CCSR);
3179 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3180 HCU_CCSR_UC_STATE_MSK);
acd12dde 3181 /*
3182 * CPU clock divider shouldn't be used because
3183 * - ASF firmware may malfunction
3184 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3185 */
3186 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3187 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3188 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3189 } else
3190 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3191 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3192
3193 /* do a SW reset */
3194 sky2_write8(hw, B0_CTST, CS_RST_SET);
3195 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3196
ac93a394
SH		 3197 /* allow writes to PCI config */
3198 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3199
cd28ab6a 3200 /* clear PCI errors, if any */
b32f40c4 3201 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3202 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3203 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3204
3205 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3206
1a10ccae 3207 if (pci_is_pcie(pdev)) {
7782c8c4
SH		 3208 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3209 0xfffffffful);
555382cb
SH		 3210
3211 /* If error bit is stuck on ignore it */
3212 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3213 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3214 else
555382cb
SH		 3215 hwe_mask |= Y2_IS_PCI_EXP;
3216 }
cd28ab6a 3217
ae306cca 3218 sky2_power_on(hw);
a40ccc68 3219 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3220
3221 for (i = 0; i < hw->ports; i++) {
3222 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3223 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3224
ed4d4161
SH		 3225 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3226 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3227 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3228 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3229 | GMC_BYP_RETR_ON);
877c8570
SH		 3230
3231 }
3232
3233 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3234 /* enable MACSec clock gating */
3235 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3236 }
3237
4fb99cd6 3238 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3239 hw->chip_id == CHIP_ID_YUKON_PRM ||
3240 hw->chip_id == CHIP_ID_YUKON_OP_2) {
0f5aac70
SH		 3241 u16 reg;
3242 u32 msk;
3243
4fb99cd6 3244 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
0f5aac70
SH		 3245 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3246 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3247
3248 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3249 reg = 10;
4fb99cd6 3250
3251 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3252 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
0f5aac70
SH		 3253 } else {
3254 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3255 reg = 3;
3256 }
3257
3258 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
4fb99cd6 3259 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
0f5aac70
SH		 3260
3261 /* reset PHY Link Detect */
a40ccc68 3262 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3263 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3264
0f5aac70
SH		 3265 /* enable PHY Quick Link */
3266 msk = sky2_read32(hw, B0_IMSK);
3267 msk |= Y2_IS_PHY_QLNK;
3268 sky2_write32(hw, B0_IMSK, msk);
3269
3270 /* check if PSMv2 was running before */
3271 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
1a10ccae 3272 if (reg & PCI_EXP_LNKCTL_ASPMC)
0f5aac70 3273 /* restore the PCIe Link Control register */
1a10ccae
JM		 3274 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3275 reg);
3276
a40ccc68 3277 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3278
3279 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3280 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3281 }
3282
793b883e
SH		 3283 /* Clear I2C IRQ noise */
3284 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3285
3286 /* turn off hardware timer (unused) */
3287 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3288 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3289
69634ee7
SH		 3290 /* Turn off descriptor polling */
3291 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3292
3293 /* Turn off receive timestamp */
3294 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3295 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3296
3297 /* enable the Tx Arbiters */
3298 for (i = 0; i < hw->ports; i++)
3299 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3300
3301 /* Initialize ram interface */
3302 for (i = 0; i < hw->ports; i++) {
793b883e 3303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3304
3305 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3306 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3307 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3308 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3309 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3310 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3311 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3312 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3313 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3314 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3315 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3316 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3317 }
3318
555382cb 3319 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3320
cd28ab6a 3321 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3322 sky2_gmac_reset(hw, i);
cd28ab6a 3323
efe91932 3324 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
cd28ab6a
SH		 3325 hw->st_idx = 0;
3326
3327 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3328 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3329
3330 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3331 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3332
3333 /* Set the list last index */
efe91932 3334 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
cd28ab6a 3335
290d4de5
SH		 3336 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3337 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3338
290d4de5
SH		 3339 /* set Status-FIFO ISR watermark */
3340 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3341 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3342 else
3343 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3344
290d4de5 3345 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3346 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3347 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3348
793b883e 3349 /* enable status unit */
cd28ab6a
SH		 3350 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3351
3352 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3353 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3354 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3355}
3356
af18d8b8
SH		 3357/* Take device down (offline).
3358 * Equivalent to doing dev_stop() but this does not
25985edc 3359 * inform upper layers of the transition.
af18d8b8
SH		 3360 */
3361static void sky2_detach(struct net_device *dev)
3362{
3363 if (netif_running(dev)) {
c36531b9 3364 netif_tx_lock(dev);
af18d8b8 3365 netif_device_detach(dev); /* stop txq */
c36531b9 3366 netif_tx_unlock(dev);
af18d8b8
SH		 3367 sky2_down(dev);
3368 }
3369}
3370
3371/* Bring device back after doing sky2_detach */
3372static int sky2_reattach(struct net_device *dev)
3373{
3374 int err = 0;
3375
3376 if (netif_running(dev)) {
3377 err = sky2_up(dev);
3378 if (err) {
ada1db5c 3379 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3380 dev_close(dev);
3381 } else {
3382 netif_device_attach(dev);
3383 sky2_set_multicast(dev);
3384 }
3385 }
3386
3387 return err;
3388}
3389
d72ff8fa 3390static void sky2_all_down(struct sky2_hw *hw)
81906791 3391{
af18d8b8 3392 int i;
81906791 3393
d72ff8fa 3394 sky2_read32(hw, B0_IMSK);
8cfcbe99 3395 sky2_write32(hw, B0_IMSK, 0);
93135a3b
MM		 3396 synchronize_irq(hw->pdev->irq);
3397 napi_disable(&hw->napi);
8a0c9228
MM		 3398
3399 for (i = 0; i < hw->ports; i++) {
3400 struct net_device *dev = hw->dev[i];
3401 struct sky2_port *sky2 = netdev_priv(dev);
3402
3403 if (!netif_running(dev))
3404 continue;
3405
3406 netif_carrier_off(dev);
3407 netif_tx_disable(dev);
3408 sky2_hw_down(sky2);
3409 }
d72ff8fa 3410}
8a0c9228 3411
d72ff8fa
MM		 3412static void sky2_all_up(struct sky2_hw *hw)
3413{
3414 u32 imask = Y2_IS_BASE;
3415 int i;
81906791 3416
8a0c9228
MM		 3417 for (i = 0; i < hw->ports; i++) {
3418 struct net_device *dev = hw->dev[i];
3419 struct sky2_port *sky2 = netdev_priv(dev);
3420
3421 if (!netif_running(dev))
3422 continue;
3423
3424 sky2_hw_up(sky2);
37652522 3425 sky2_set_multicast(dev);
d72ff8fa 3426 imask |= portirq_msk[i];
8a0c9228
MM		 3427 netif_wake_queue(dev);
3428 }
3429
3430 sky2_write32(hw, B0_IMSK, imask);
3431 sky2_read32(hw, B0_IMSK);
3432
3433 sky2_read32(hw, B0_Y2_SP_LISR);
3434 napi_enable(&hw->napi);
d72ff8fa
MM		 3435}
3436
3437static void sky2_restart(struct work_struct *work)
3438{
3439 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3440
3441 rtnl_lock();
3442
3443 sky2_all_down(hw);
3444 sky2_reset(hw);
3445 sky2_all_up(hw);
81906791 3446
81906791
SH		 3447 rtnl_unlock();
3448}
3449
e3173832
SH		 3450static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3451{
3452 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3453}
3454
3455static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3456{
3457 const struct sky2_port *sky2 = netdev_priv(dev);
3458
3459 wol->supported = sky2_wol_supported(sky2->hw);
3460 wol->wolopts = sky2->wol;
3461}
3462
3463static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3464{
3465 struct sky2_port *sky2 = netdev_priv(dev);
3466 struct sky2_hw *hw = sky2->hw;
0f333d10
RW		 3467 bool enable_wakeup = false;
3468 int i;
cd28ab6a 3469
8e95a202
JP		 3470 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3471 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3472 return -EOPNOTSUPP;
3473
3474 sky2->wol = wol->wolopts;
0f333d10
RW		 3475
3476 for (i = 0; i < hw->ports; i++) {
3477 struct net_device *dev = hw->dev[i];
3478 struct sky2_port *sky2 = netdev_priv(dev);
3479
3480 if (sky2->wol)
3481 enable_wakeup = true;
3482 }
3483 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3484
cd28ab6a
SH		 3485 return 0;
3486}
3487
28bd181a 3488static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3489{
b89165f2
SH		 3490 if (sky2_is_copper(hw)) {
3491 u32 modes = SUPPORTED_10baseT_Half
3492 | SUPPORTED_10baseT_Full
3493 | SUPPORTED_100baseT_Half
2aca31e7 3494 | SUPPORTED_100baseT_Full;
cd28ab6a 3495
ea76e635 3496 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3497 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3498 | SUPPORTED_1000baseT_Full;
3499 return modes;
cd28ab6a 3500 } else
2aca31e7
SH		 3501 return SUPPORTED_1000baseT_Half
3502 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 3503}
3504
793b883e 3505static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3506{
3507 struct sky2_port *sky2 = netdev_priv(dev);
3508 struct sky2_hw *hw = sky2->hw;
3509
3510 ecmd->transceiver = XCVR_INTERNAL;
3511 ecmd->supported = sky2_supported_modes(hw);
3512 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3513 if (sky2_is_copper(hw)) {
cd28ab6a 3514 ecmd->port = PORT_TP;
70739497 3515 ethtool_cmd_speed_set(ecmd, sky2->speed);
2aca31e7 3516 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
b89165f2 3517 } else {
70739497 3518 ethtool_cmd_speed_set(ecmd, SPEED_1000);
cd28ab6a 3519 ecmd->port = PORT_FIBRE;
2aca31e7 3520 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
b89165f2 3521 }
cd28ab6a
SH		 3522
3523 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3524 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3525 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3526 ecmd->duplex = sky2->duplex;
3527 return 0;
3528}
3529
3530static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3531{
3532 struct sky2_port *sky2 = netdev_priv(dev);
3533 const struct sky2_hw *hw = sky2->hw;
3534 u32 supported = sky2_supported_modes(hw);
3535
3536 if (ecmd->autoneg == AUTONEG_ENABLE) {
2aca31e7
SH		 3537 if (ecmd->advertising & ~supported)
3538 return -EINVAL;
3539
3540 if (sky2_is_copper(hw))
3541 sky2->advertising = ecmd->advertising |
3542 ADVERTISED_TP |
3543 ADVERTISED_Autoneg;
3544 else
3545 sky2->advertising = ecmd->advertising |
3546 ADVERTISED_FIBRE |
3547 ADVERTISED_Autoneg;
3548
0ea065e5 3549 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3550 sky2->duplex = -1;
3551 sky2->speed = -1;
3552 } else {
3553 u32 setting;
25db0338 3554 u32 speed = ethtool_cmd_speed(ecmd);
cd28ab6a 3555
25db0338 3556 switch (speed) {
cd28ab6a
SH		 3557 case SPEED_1000:
3558 if (ecmd->duplex == DUPLEX_FULL)
3559 setting = SUPPORTED_1000baseT_Full;
3560 else if (ecmd->duplex == DUPLEX_HALF)
3561 setting = SUPPORTED_1000baseT_Half;
3562 else
3563 return -EINVAL;
3564 break;
3565 case SPEED_100:
3566 if (ecmd->duplex == DUPLEX_FULL)
3567 setting = SUPPORTED_100baseT_Full;
3568 else if (ecmd->duplex == DUPLEX_HALF)
3569 setting = SUPPORTED_100baseT_Half;
3570 else
3571 return -EINVAL;
3572 break;
3573
3574 case SPEED_10:
3575 if (ecmd->duplex == DUPLEX_FULL)
3576 setting = SUPPORTED_10baseT_Full;
3577 else if (ecmd->duplex == DUPLEX_HALF)
3578 setting = SUPPORTED_10baseT_Half;
3579 else
3580 return -EINVAL;
3581 break;
3582 default:
3583 return -EINVAL;
3584 }
3585
3586 if ((setting & supported) == 0)
3587 return -EINVAL;
3588
25db0338 3589 sky2->speed = speed;
cd28ab6a 3590 sky2->duplex = ecmd->duplex;
0ea065e5 3591 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3592 }
3593
d1b139c0 3594 if (netif_running(dev)) {
1b537565 3595 sky2_phy_reinit(sky2);
d1b139c0
SH		 3596 sky2_set_multicast(dev);
3597 }
cd28ab6a
SH		 3598
3599 return 0;
3600}
3601
3602static void sky2_get_drvinfo(struct net_device *dev,
3603 struct ethtool_drvinfo *info)
3604{
3605 struct sky2_port *sky2 = netdev_priv(dev);
3606
3607 strcpy(info->driver, DRV_NAME);
3608 strcpy(info->version, DRV_VERSION);
3609 strcpy(info->fw_version, "N/A");
3610 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3611}
3612
3613static const struct sky2_stat {
793b883e
SH		 3614 char name[ETH_GSTRING_LEN];
3615 u16 offset;
cd28ab6a
SH		 3616} sky2_stats[] = {
3617 { "tx_bytes", GM_TXO_OK_HI },
3618 { "rx_bytes", GM_RXO_OK_HI },
3619 { "tx_broadcast", GM_TXF_BC_OK },
3620 { "rx_broadcast", GM_RXF_BC_OK },
3621 { "tx_multicast", GM_TXF_MC_OK },
3622 { "rx_multicast", GM_RXF_MC_OK },
3623 { "tx_unicast", GM_TXF_UC_OK },
3624 { "rx_unicast", GM_RXF_UC_OK },
3625 { "tx_mac_pause", GM_TXF_MPAUSE },
3626 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3627 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3628 { "late_collision",GM_TXF_LAT_COL },
3629 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3630 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3631 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3632
d2604540 3633 { "rx_short", GM_RXF_SHT },
cd28ab6a 3634 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3635 { "rx_64_byte_packets", GM_RXF_64B },
3636 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3637 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3638 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3639 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3640 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3641 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3642 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3643 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3644 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3645 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3646
3647 { "tx_64_byte_packets", GM_TXF_64B },
3648 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3649 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3650 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3651 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3652 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3653 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3654 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3655};
3656
cd28ab6a
SH		 3657static u32 sky2_get_msglevel(struct net_device *netdev)
3658{
3659 struct sky2_port *sky2 = netdev_priv(netdev);
3660 return sky2->msg_enable;
3661}
3662
9a7ae0a9
SH		 3663static int sky2_nway_reset(struct net_device *dev)
3664{
3665 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3666
0ea065e5 3667 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3668 return -EINVAL;
3669
1b537565 3670 sky2_phy_reinit(sky2);
d1b139c0 3671 sky2_set_multicast(dev);
9a7ae0a9
SH		 3672
3673 return 0;
3674}
3675
793b883e 3676static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3677{
3678 struct sky2_hw *hw = sky2->hw;
3679 unsigned port = sky2->port;
3680 int i;
3681
0885a30b 3682 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3683 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
cd28ab6a 3684
793b883e 3685 for (i = 2; i < count; i++)
0885a30b 3686 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
cd28ab6a
SH		 3687}
3688
cd28ab6a
SH		 3689static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3690{
3691 struct sky2_port *sky2 = netdev_priv(netdev);
3692 sky2->msg_enable = value;
3693}
3694
b9f2c044 3695static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3696{
b9f2c044
JG		 3697 switch (sset) {
3698 case ETH_SS_STATS:
3699 return ARRAY_SIZE(sky2_stats);
3700 default:
3701 return -EOPNOTSUPP;
3702 }
cd28ab6a
SH		 3703}
3704
3705static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3706 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3707{
3708 struct sky2_port *sky2 = netdev_priv(dev);
3709
793b883e 3710 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3711}
3712
793b883e 3713static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3714{
3715 int i;
3716
3717 switch (stringset) {
3718 case ETH_SS_STATS:
3719 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3720 memcpy(data + i * ETH_GSTRING_LEN,
3721 sky2_stats[i].name, ETH_GSTRING_LEN);
3722 break;
3723 }
3724}
3725
cd28ab6a
SH		 3726static int sky2_set_mac_address(struct net_device *dev, void *p)
3727{
3728 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3729 struct sky2_hw *hw = sky2->hw;
3730 unsigned port = sky2->port;
3731 const struct sockaddr *addr = p;
cd28ab6a
SH		 3732
3733 if (!is_valid_ether_addr(addr->sa_data))
3734 return -EADDRNOTAVAIL;
3735
cd28ab6a 3736 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3737 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3738 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3739 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3740 dev->dev_addr, ETH_ALEN);
1b537565 3741
a8ab1ec0
SH		 3742 /* virtual address for data */
3743 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3744
3745 /* physical address: used for pause frames */
3746 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3747
3748 return 0;
cd28ab6a
SH		 3749}
3750
060b946c 3751static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
a052b52f
SH		 3752{
3753 u32 bit;
3754
3755 bit = ether_crc(ETH_ALEN, addr) & 63;
3756 filter[bit >> 3] |= 1 << (bit & 7);
3757}
3758
cd28ab6a
SH		 3759static void sky2_set_multicast(struct net_device *dev)
3760{
3761 struct sky2_port *sky2 = netdev_priv(dev);
3762 struct sky2_hw *hw = sky2->hw;
3763 unsigned port = sky2->port;
22bedad3 3764 struct netdev_hw_addr *ha;
cd28ab6a
SH		 3765 u16 reg;
3766 u8 filter[8];
a052b52f
SH		 3767 int rx_pause;
3768 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3769
a052b52f 3770 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3771 memset(filter, 0, sizeof(filter));
3772
3773 reg = gma_read16(hw, port, GM_RX_CTRL);
3774 reg |= GM_RXCR_UCF_ENA;
3775
d571b694 3776 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3777 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3778 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3779 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3780 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3781 reg &= ~GM_RXCR_MCF_ENA;
3782 else {
cd28ab6a
SH		 3783 reg |= GM_RXCR_MCF_ENA;
3784
a052b52f
SH		 3785 if (rx_pause)
3786 sky2_add_filter(filter, pause_mc_addr);
3787
22bedad3
JP		 3788 netdev_for_each_mc_addr(ha, dev)
3789 sky2_add_filter(filter, ha->addr);
cd28ab6a
SH		 3790 }
3791
cd28ab6a 3792 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3793 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3794 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3795 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3796 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3797 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3798 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3799 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3800
3801 gma_write16(hw, port, GM_RX_CTRL, reg);
3802}
3803
0885a30b 3804static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3805 struct rtnl_link_stats64 *stats)
3806{
3807 struct sky2_port *sky2 = netdev_priv(dev);
3808 struct sky2_hw *hw = sky2->hw;
3809 unsigned port = sky2->port;
3810 unsigned int start;
3811 u64 _bytes, _packets;
3812
3813 do {
3814 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3815 _bytes = sky2->rx_stats.bytes;
3816 _packets = sky2->rx_stats.packets;
3817 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3818
3819 stats->rx_packets = _packets;
3820 stats->rx_bytes = _bytes;
3821
3822 do {
3823 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3824 _bytes = sky2->tx_stats.bytes;
3825 _packets = sky2->tx_stats.packets;
3826 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3827
3828 stats->tx_packets = _packets;
3829 stats->tx_bytes = _bytes;
3830
3831 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3832 + get_stats32(hw, port, GM_RXF_BC_OK);
3833
3834 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3835
3836 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3837 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3838 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3839 + get_stats32(hw, port, GM_RXE_FRAG);
3840 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3841
3842 stats->rx_dropped = dev->stats.rx_dropped;
3843 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3844 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3845
3846 return stats;
3847}
3848
cd28ab6a
SH		 3849/* Can have one global because blinking is controlled by
3850 * ethtool and that is always under RTNL mutex
3851 */
a84d0a3d 3852static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3853{
a84d0a3d
SH		 3854 struct sky2_hw *hw = sky2->hw;
3855 unsigned port = sky2->port;
793b883e 3856
a84d0a3d
SH		 3857 spin_lock_bh(&sky2->phy_lock);
3858 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3859 hw->chip_id == CHIP_ID_YUKON_EX ||
3860 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3861 u16 pg;
793b883e
SH		 3862 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3863 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3864
a84d0a3d
SH		 3865 switch (mode) {
3866 case MO_LED_OFF:
3867 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3868 PHY_M_LEDC_LOS_CTRL(8) |
3869 PHY_M_LEDC_INIT_CTRL(8) |
3870 PHY_M_LEDC_STA1_CTRL(8) |
3871 PHY_M_LEDC_STA0_CTRL(8));
3872 break;
3873 case MO_LED_ON:
3874 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3875 PHY_M_LEDC_LOS_CTRL(9) |
3876 PHY_M_LEDC_INIT_CTRL(9) |
3877 PHY_M_LEDC_STA1_CTRL(9) |
3878 PHY_M_LEDC_STA0_CTRL(9));
3879 break;
3880 case MO_LED_BLINK:
3881 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3882 PHY_M_LEDC_LOS_CTRL(0xa) |
3883 PHY_M_LEDC_INIT_CTRL(0xa) |
3884 PHY_M_LEDC_STA1_CTRL(0xa) |
3885 PHY_M_LEDC_STA0_CTRL(0xa));
3886 break;
3887 case MO_LED_NORM:
3888 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3889 PHY_M_LEDC_LOS_CTRL(1) |
3890 PHY_M_LEDC_INIT_CTRL(8) |
3891 PHY_M_LEDC_STA1_CTRL(7) |
3892 PHY_M_LEDC_STA0_CTRL(7));
3893 }
793b883e 3894
a84d0a3d
SH		 3895 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3896 } else
7d2e3cb7 3897 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3898 PHY_M_LED_MO_DUP(mode) |
3899 PHY_M_LED_MO_10(mode) |
3900 PHY_M_LED_MO_100(mode) |
3901 PHY_M_LED_MO_1000(mode) |
3902 PHY_M_LED_MO_RX(mode) |
3903 PHY_M_LED_MO_TX(mode));
3904
3905 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3906}
3907
3908/* blink LED's for finding board */
74e532ff 3909static int sky2_set_phys_id(struct net_device *dev,
3910 enum ethtool_phys_id_state state)
cd28ab6a
SH		 3911{
3912 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3913
74e532ff 3914 switch (state) {
3915 case ETHTOOL_ID_ACTIVE:
fce55922 3916 return 1; /* cycle on/off once per second */
74e532ff 3917 case ETHTOOL_ID_INACTIVE:
3918 sky2_led(sky2, MO_LED_NORM);
3919 break;
3920 case ETHTOOL_ID_ON:
a84d0a3d 3921 sky2_led(sky2, MO_LED_ON);
74e532ff 3922 break;
3923 case ETHTOOL_ID_OFF:
a84d0a3d 3924 sky2_led(sky2, MO_LED_OFF);
74e532ff 3925 break;
793b883e 3926 }
cd28ab6a
SH		 3927
3928 return 0;
3929}
3930
3931static void sky2_get_pauseparam(struct net_device *dev,
3932 struct ethtool_pauseparam *ecmd)
3933{
3934 struct sky2_port *sky2 = netdev_priv(dev);
3935
16ad91e1
SH		 3936 switch (sky2->flow_mode) {
3937 case FC_NONE:
3938 ecmd->tx_pause = ecmd->rx_pause = 0;
3939 break;
3940 case FC_TX:
3941 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3942 break;
3943 case FC_RX:
3944 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3945 break;
3946 case FC_BOTH:
3947 ecmd->tx_pause = ecmd->rx_pause = 1;
3948 }
3949
0ea065e5
SH		 3950 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3951 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3952}
3953
3954static int sky2_set_pauseparam(struct net_device *dev,
3955 struct ethtool_pauseparam *ecmd)
3956{
3957 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3958
0ea065e5
SH		 3959 if (ecmd->autoneg == AUTONEG_ENABLE)
3960 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3961 else
3962 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3963
16ad91e1 3964 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3965
16ad91e1
SH		 3966 if (netif_running(dev))
3967 sky2_phy_reinit(sky2);
cd28ab6a 3968
2eaba1a2 3969 return 0;
cd28ab6a
SH		 3970}
3971
fb17358f
SH		 3972static int sky2_get_coalesce(struct net_device *dev,
3973 struct ethtool_coalesce *ecmd)
3974{
3975 struct sky2_port *sky2 = netdev_priv(dev);
3976 struct sky2_hw *hw = sky2->hw;
3977
3978 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3979 ecmd->tx_coalesce_usecs = 0;
3980 else {
3981 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3982 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3983 }
3984 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3985
3986 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3987 ecmd->rx_coalesce_usecs = 0;
3988 else {
3989 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3990 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3991 }
3992 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3993
3994 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3995 ecmd->rx_coalesce_usecs_irq = 0;
3996 else {
3997 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3998 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3999 }
4000
4001 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4002
4003 return 0;
4004}
4005
4006/* Note: this affect both ports */
4007static int sky2_set_coalesce(struct net_device *dev,
4008 struct ethtool_coalesce *ecmd)
4009{
4010 struct sky2_port *sky2 = netdev_priv(dev);
4011 struct sky2_hw *hw = sky2->hw;
77b3d6a2 4012 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 4013
77b3d6a2
SH		 4014 if (ecmd->tx_coalesce_usecs > tmax ||
4015 ecmd->rx_coalesce_usecs > tmax ||
4016 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 4017 return -EINVAL;
4018
ee5f68fe 4019 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 4020 return -EINVAL;
ff81fbbe 4021 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 4022 return -EINVAL;
060b946c 4023 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
fb17358f
SH		 4024 return -EINVAL;
4025
4026 if (ecmd->tx_coalesce_usecs == 0)
4027 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4028 else {
4029 sky2_write32(hw, STAT_TX_TIMER_INI,
4030 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4031 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4032 }
4033 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4034
4035 if (ecmd->rx_coalesce_usecs == 0)
4036 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4037 else {
4038 sky2_write32(hw, STAT_LEV_TIMER_INI,
4039 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4040 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4041 }
4042 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4043
4044 if (ecmd->rx_coalesce_usecs_irq == 0)
4045 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4046 else {
d28d4870 4047 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 4048 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4049 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4050 }
4051 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4052 return 0;
4053}
4054
793b883e
SH		 4055static void sky2_get_ringparam(struct net_device *dev,
4056 struct ethtool_ringparam *ering)
4057{
4058 struct sky2_port *sky2 = netdev_priv(dev);
4059
4060 ering->rx_max_pending = RX_MAX_PENDING;
4061 ering->rx_mini_max_pending = 0;
4062 ering->rx_jumbo_max_pending = 0;
ee5f68fe 4063 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 4064
4065 ering->rx_pending = sky2->rx_pending;
4066 ering->rx_mini_pending = 0;
4067 ering->rx_jumbo_pending = 0;
4068 ering->tx_pending = sky2->tx_pending;
4069}
4070
4071static int sky2_set_ringparam(struct net_device *dev,
4072 struct ethtool_ringparam *ering)
4073{
4074 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 4075
4076 if (ering->rx_pending > RX_MAX_PENDING ||
4077 ering->rx_pending < 8 ||
ee5f68fe
SH		 4078 ering->tx_pending < TX_MIN_PENDING ||
4079 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 4080 return -EINVAL;
4081
af18d8b8 4082 sky2_detach(dev);
793b883e
SH		 4083
4084 sky2->rx_pending = ering->rx_pending;
4085 sky2->tx_pending = ering->tx_pending;
ee5f68fe 4086 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 4087
af18d8b8 4088 return sky2_reattach(dev);
793b883e
SH		 4089}
4090
793b883e
SH		 4091static int sky2_get_regs_len(struct net_device *dev)
4092{
6e4cbb34 4093 return 0x4000;
793b883e
SH		 4094}
4095
c32bbff8
MM		 4096static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4097{
4098 /* This complicated switch statement is to make sure and
4099 * only access regions that are unreserved.
4100 * Some blocks are only valid on dual port cards.
4101 */
4102 switch (b) {
4103 /* second port */
4104 case 5: /* Tx Arbiter 2 */
4105 case 9: /* RX2 */
4106 case 14 ... 15: /* TX2 */
4107 case 17: case 19: /* Ram Buffer 2 */
4108 case 22 ... 23: /* Tx Ram Buffer 2 */
4109 case 25: /* Rx MAC Fifo 1 */
4110 case 27: /* Tx MAC Fifo 2 */
4111 case 31: /* GPHY 2 */
4112 case 40 ... 47: /* Pattern Ram 2 */
4113 case 52: case 54: /* TCP Segmentation 2 */
4114 case 112 ... 116: /* GMAC 2 */
4115 return hw->ports > 1;
4116
4117 case 0: /* Control */
4118 case 2: /* Mac address */
4119 case 4: /* Tx Arbiter 1 */
4120 case 7: /* PCI express reg */
4121 case 8: /* RX1 */
4122 case 12 ... 13: /* TX1 */
4123 case 16: case 18:/* Rx Ram Buffer 1 */
4124 case 20 ... 21: /* Tx Ram Buffer 1 */
4125 case 24: /* Rx MAC Fifo 1 */
4126 case 26: /* Tx MAC Fifo 1 */
4127 case 28 ... 29: /* Descriptor and status unit */
4128 case 30: /* GPHY 1*/
4129 case 32 ... 39: /* Pattern Ram 1 */
4130 case 48: case 50: /* TCP Segmentation 1 */
4131 case 56 ... 60: /* PCI space */
4132 case 80 ... 84: /* GMAC 1 */
4133 return 1;
4134
4135 default:
4136 return 0;
4137 }
4138}
4139
793b883e
SH		 4140/*
4141 * Returns copy of control register region
3ead5db7 4142 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 4143 */
4144static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4145 void *p)
4146{
4147 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 4148 const void __iomem *io = sky2->hw->regs;
295b54c4 4149 unsigned int b;
793b883e
SH		 4150
4151 regs->version = 1;
793b883e 4152
295b54c4 4153 for (b = 0; b < 128; b++) {
c32bbff8
MM		 4154 /* skip poisonous diagnostic ram region in block 3 */
4155 if (b == 3)
295b54c4 4156 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 4157 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 4158 memcpy_fromio(p, io, 128);
c32bbff8 4159 else
295b54c4 4160 memset(p, 0, 128);
3ead5db7 4161
295b54c4
SH		 4162 p += 128;
4163 io += 128;
4164 }
793b883e 4165}
cd28ab6a 4166
f4331a6d
SH		 4167static int sky2_get_eeprom_len(struct net_device *dev)
4168{
4169 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4170 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4171 u16 reg2;
4172
b32f40c4 4173 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4174 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4175}
4176
1413235c 4177static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4178{
1413235c 4179 unsigned long start = jiffies;
f4331a6d 4180
1413235c
SH		 4181 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4182 /* Can take up to 10.6 ms for write */
4183 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4184 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4185 return -ETIMEDOUT;
4186 }
4187 mdelay(1);
4188 }
167f53d0 4189
1413235c
SH		 4190 return 0;
4191}
167f53d0 4192
1413235c
SH		 4193static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4194 u16 offset, size_t length)
4195{
4196 int rc = 0;
4197
4198 while (length > 0) {
4199 u32 val;
4200
4201 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4202 rc = sky2_vpd_wait(hw, cap, 0);
4203 if (rc)
4204 break;
4205
4206 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4207
4208 memcpy(data, &val, min(sizeof(val), length));
4209 offset += sizeof(u32);
4210 data += sizeof(u32);
4211 length -= sizeof(u32);
4212 }
4213
4214 return rc;
f4331a6d
SH		 4215}
4216
1413235c
SH		 4217static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4218 u16 offset, unsigned int length)
f4331a6d 4219{
1413235c
SH		 4220 unsigned int i;
4221 int rc = 0;
4222
4223 for (i = 0; i < length; i += sizeof(u32)) {
4224 u32 val = *(u32 *)(data + i);
4225
4226 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4227 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4228
4229 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4230 if (rc)
4231 break;
4232 }
4233 return rc;
f4331a6d
SH		 4234}
4235
4236static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4237 u8 *data)
4238{
4239 struct sky2_port *sky2 = netdev_priv(dev);
4240 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4241
4242 if (!cap)
4243 return -EINVAL;
4244
4245 eeprom->magic = SKY2_EEPROM_MAGIC;
4246
1413235c 4247 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4248}
4249
4250static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4251 u8 *data)
4252{
4253 struct sky2_port *sky2 = netdev_priv(dev);
4254 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4255
4256 if (!cap)
4257 return -EINVAL;
4258
4259 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4260 return -EINVAL;
4261
1413235c
SH		 4262 /* Partial writes not supported */
4263 if ((eeprom->offset & 3) || (eeprom->len & 3))
4264 return -EINVAL;
f4331a6d 4265
1413235c 4266 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4267}
4268
f5d64037 4269static u32 sky2_fix_features(struct net_device *dev, u32 features)
bf73130d 4270{
f5d64037
MM		 4271 const struct sky2_port *sky2 = netdev_priv(dev);
4272 const struct sky2_hw *hw = sky2->hw;
bf73130d 4273
f5d64037
MM		 4274 /* In order to do Jumbo packets on these chips, need to turn off the
4275 * transmit store/forward. Therefore checksum offload won't work.
4276 */
aa5ca96c 4277 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4278 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
f5d64037 4279 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
aa5ca96c 4280 }
4281
4282 /* Some hardware requires receive checksum for RSS to work. */
4283 if ( (features & NETIF_F_RXHASH) &&
4284 !(features & NETIF_F_RXCSUM) &&
4285 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4286 netdev_info(dev, "receive hashing forces receive checksum\n");
4287 features |= NETIF_F_RXCSUM;
4288 }
86aa7785 4289
f5d64037
MM		 4290 return features;
4291}
86aa7785 4292
f5d64037
MM		 4293static int sky2_set_features(struct net_device *dev, u32 features)
4294{
4295 struct sky2_port *sky2 = netdev_priv(dev);
4296 u32 changed = dev->features ^ features;
86aa7785 4297
f5d64037
MM		 4298 if (changed & NETIF_F_RXCSUM) {
4299 u32 on = features & NETIF_F_RXCSUM;
4300 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4301 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4302 }
bf73130d 4303
f5d64037
MM		 4304 if (changed & NETIF_F_RXHASH)
4305 rx_set_rss(dev, features);
86aa7785 4306
f5d64037
MM		 4307 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4308 sky2_vlan_mode(dev, features);
bf73130d
SH		 4309
4310 return 0;
4311}
f4331a6d 4312
7282d491 4313static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4314 .get_settings = sky2_get_settings,
4315 .set_settings = sky2_set_settings,
4316 .get_drvinfo = sky2_get_drvinfo,
4317 .get_wol = sky2_get_wol,
4318 .set_wol = sky2_set_wol,
4319 .get_msglevel = sky2_get_msglevel,
4320 .set_msglevel = sky2_set_msglevel,
4321 .nway_reset = sky2_nway_reset,
4322 .get_regs_len = sky2_get_regs_len,
4323 .get_regs = sky2_get_regs,
4324 .get_link = ethtool_op_get_link,
4325 .get_eeprom_len = sky2_get_eeprom_len,
4326 .get_eeprom = sky2_get_eeprom,
4327 .set_eeprom = sky2_set_eeprom,
f4331a6d
SH		 4328 .get_strings = sky2_get_strings,
4329 .get_coalesce = sky2_get_coalesce,
4330 .set_coalesce = sky2_set_coalesce,
4331 .get_ringparam = sky2_get_ringparam,
4332 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4333 .get_pauseparam = sky2_get_pauseparam,
4334 .set_pauseparam = sky2_set_pauseparam,
74e532ff 4335 .set_phys_id = sky2_set_phys_id,
b9f2c044 4336 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4337 .get_ethtool_stats = sky2_get_ethtool_stats,
4338};
4339
3cf26753
SH		 4340#ifdef CONFIG_SKY2_DEBUG
4341
4342static struct dentry *sky2_debug;
4343
e4c2abe2
SH		 4344
4345/*
4346 * Read and parse the first part of Vital Product Data
4347 */
4348#define VPD_SIZE 128
4349#define VPD_MAGIC 0x82
4350
4351static const struct vpd_tag {
4352 char tag[2];
4353 char *label;
4354} vpd_tags[] = {
4355 { "PN", "Part Number" },
4356 { "EC", "Engineering Level" },
4357 { "MN", "Manufacturer" },
4358 { "SN", "Serial Number" },
4359 { "YA", "Asset Tag" },
4360 { "VL", "First Error Log Message" },
4361 { "VF", "Second Error Log Message" },
4362 { "VB", "Boot Agent ROM Configuration" },
4363 { "VE", "EFI UNDI Configuration" },
4364};
4365
4366static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4367{
4368 size_t vpd_size;
4369 loff_t offs;
4370 u8 len;
4371 unsigned char *buf;
4372 u16 reg2;
4373
4374 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4375 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4376
4377 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4378 buf = kmalloc(vpd_size, GFP_KERNEL);
4379 if (!buf) {
4380 seq_puts(seq, "no memory!\n");
4381 return;
4382 }
4383
4384 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4385 seq_puts(seq, "VPD read failed\n");
4386 goto out;
4387 }
4388
4389 if (buf[0] != VPD_MAGIC) {
4390 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4391 goto out;
4392 }
4393 len = buf[1];
4394 if (len == 0 || len > vpd_size - 4) {
4395 seq_printf(seq, "Invalid id length: %d\n", len);
4396 goto out;
4397 }
4398
4399 seq_printf(seq, "%.*s\n", len, buf + 3);
4400 offs = len + 3;
4401
4402 while (offs < vpd_size - 4) {
4403 int i;
4404
4405 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4406 break;
4407 len = buf[offs + 2];
4408 if (offs + len + 3 >= vpd_size)
4409 break;
4410
4411 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4412 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4413 seq_printf(seq, " %s: %.*s\n",
4414 vpd_tags[i].label, len, buf + offs + 3);
4415 break;
4416 }
4417 }
4418 offs += len + 3;
4419 }
4420out:
4421 kfree(buf);
4422}
4423
3cf26753
SH		 4424static int sky2_debug_show(struct seq_file *seq, void *v)
4425{
4426 struct net_device *dev = seq->private;
4427 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4428 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4429 unsigned port = sky2->port;
4430 unsigned idx, last;
4431 int sop;
4432
e4c2abe2 4433 sky2_show_vpd(seq, hw);
3cf26753 4434
e4c2abe2 4435 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4436 sky2_read32(hw, B0_ISRC),
4437 sky2_read32(hw, B0_IMSK),
4438 sky2_read32(hw, B0_Y2_SP_ICR));
4439
e4c2abe2
SH		 4440 if (!netif_running(dev)) {
4441 seq_printf(seq, "network not running\n");
4442 return 0;
4443 }
4444
bea3348e 4445 napi_disable(&hw->napi);
3cf26753
SH		 4446 last = sky2_read16(hw, STAT_PUT_IDX);
4447
efe91932 4448 seq_printf(seq, "Status ring %u\n", hw->st_size);
3cf26753
SH		 4449 if (hw->st_idx == last)
4450 seq_puts(seq, "Status ring (empty)\n");
4451 else {
4452 seq_puts(seq, "Status ring\n");
efe91932 4453 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4454 idx = RING_NEXT(idx, hw->st_size)) {
3cf26753
SH		 4455 const struct sky2_status_le *le = hw->st_le + idx;
4456 seq_printf(seq, "[%d] %#x %d %#x\n",
4457 idx, le->opcode, le->length, le->status);
4458 }
4459 seq_puts(seq, "\n");
4460 }
4461
4462 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4463 sky2->tx_cons, sky2->tx_prod,
4464 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4465 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4466
4467 /* Dump contents of tx ring */
4468 sop = 1;
ee5f68fe
SH		 4469 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4470 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4471 const struct sky2_tx_le *le = sky2->tx_le + idx;
4472 u32 a = le32_to_cpu(le->addr);
4473
4474 if (sop)
4475 seq_printf(seq, "%u:", idx);
4476 sop = 0;
4477
060b946c 4478 switch (le->opcode & ~HW_OWNER) {
3cf26753
SH		 4479 case OP_ADDR64:
4480 seq_printf(seq, " %#x:", a);
4481 break;
4482 case OP_LRGLEN:
4483 seq_printf(seq, " mtu=%d", a);
4484 break;
4485 case OP_VLAN:
4486 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4487 break;
4488 case OP_TCPLISW:
4489 seq_printf(seq, " csum=%#x", a);
4490 break;
4491 case OP_LARGESEND:
4492 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4493 break;
4494 case OP_PACKET:
4495 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4496 break;
4497 case OP_BUFFER:
4498 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4499 break;
4500 default:
4501 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4502 a, le16_to_cpu(le->length));
4503 }
4504
4505 if (le->ctrl & EOP) {
4506 seq_putc(seq, '\n');
4507 sop = 1;
4508 }
4509 }
4510
4511 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4512 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4513 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4514 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4515
d1d08d12 4516 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4517 napi_enable(&hw->napi);
3cf26753
SH		 4518 return 0;
4519}
4520
4521static int sky2_debug_open(struct inode *inode, struct file *file)
4522{
4523 return single_open(file, sky2_debug_show, inode->i_private);
4524}
4525
4526static const struct file_operations sky2_debug_fops = {
4527 .owner = THIS_MODULE,
4528 .open = sky2_debug_open,
4529 .read = seq_read,
4530 .llseek = seq_lseek,
4531 .release = single_release,
4532};
4533
4534/*
4535 * Use network device events to create/remove/rename
4536 * debugfs file entries
4537 */
4538static int sky2_device_event(struct notifier_block *unused,
4539 unsigned long event, void *ptr)
4540{
4541 struct net_device *dev = ptr;
5b296bc9 4542 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4543
1436b301 4544 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4545 return NOTIFY_DONE;
3cf26753 4546
060b946c 4547 switch (event) {
5b296bc9
SH		 4548 case NETDEV_CHANGENAME:
4549 if (sky2->debugfs) {
4550 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4551 sky2_debug, dev->name);
4552 }
4553 break;
3cf26753 4554
5b296bc9
SH		 4555 case NETDEV_GOING_DOWN:
4556 if (sky2->debugfs) {
ada1db5c 4557 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4558 debugfs_remove(sky2->debugfs);
4559 sky2->debugfs = NULL;
3cf26753 4560 }
5b296bc9
SH		 4561 break;
4562
4563 case NETDEV_UP:
4564 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4565 sky2_debug, dev,
4566 &sky2_debug_fops);
4567 if (IS_ERR(sky2->debugfs))
4568 sky2->debugfs = NULL;
3cf26753
SH		 4569 }
4570
4571 return NOTIFY_DONE;
4572}
4573
4574static struct notifier_block sky2_notifier = {
4575 .notifier_call = sky2_device_event,
4576};
4577
4578
4579static __init void sky2_debug_init(void)
4580{
4581 struct dentry *ent;
4582
4583 ent = debugfs_create_dir("sky2", NULL);
4584 if (!ent || IS_ERR(ent))
4585 return;
4586
4587 sky2_debug = ent;
4588 register_netdevice_notifier(&sky2_notifier);
4589}
4590
4591static __exit void sky2_debug_cleanup(void)
4592{
4593 if (sky2_debug) {
4594 unregister_netdevice_notifier(&sky2_notifier);
4595 debugfs_remove(sky2_debug);
4596 sky2_debug = NULL;
4597 }
4598}
4599
4600#else
4601#define sky2_debug_init()
4602#define sky2_debug_cleanup()
4603#endif
4604
1436b301
SH		 4605/* Two copies of network device operations to handle special case of
4606 not allowing netpoll on second port */
4607static const struct net_device_ops sky2_netdev_ops[2] = {
4608 {
4609 .ndo_open = sky2_up,
4610 .ndo_stop = sky2_down,
00829823 4611 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4612 .ndo_do_ioctl = sky2_ioctl,
4613 .ndo_validate_addr = eth_validate_addr,
4614 .ndo_set_mac_address = sky2_set_mac_address,
4615 .ndo_set_multicast_list = sky2_set_multicast,
4616 .ndo_change_mtu = sky2_change_mtu,
f5d64037
MM		 4617 .ndo_fix_features = sky2_fix_features,
4618 .ndo_set_features = sky2_set_features,
1436b301 4619 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4620 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4621#ifdef CONFIG_NET_POLL_CONTROLLER
4622 .ndo_poll_controller = sky2_netpoll,
4623#endif
4624 },
4625 {
4626 .ndo_open = sky2_up,
4627 .ndo_stop = sky2_down,
00829823 4628 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4629 .ndo_do_ioctl = sky2_ioctl,
4630 .ndo_validate_addr = eth_validate_addr,
4631 .ndo_set_mac_address = sky2_set_mac_address,
4632 .ndo_set_multicast_list = sky2_set_multicast,
4633 .ndo_change_mtu = sky2_change_mtu,
f5d64037
MM		 4634 .ndo_fix_features = sky2_fix_features,
4635 .ndo_set_features = sky2_set_features,
1436b301 4636 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4637 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4638 },
4639};
3cf26753 4640
cd28ab6a
SH		 4641/* Initialize network device */
4642static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4643 unsigned port,
be63a21c 4644 int highmem, int wol)
cd28ab6a
SH		 4645{
4646 struct sky2_port *sky2;
4647 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4648
4649 if (!dev) {
898eb71c 4650 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4651 return NULL;
4652 }
4653
cd28ab6a 4654 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4655 dev->irq = hw->pdev->irq;
cd28ab6a 4656 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4657 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4658 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4659
4660 sky2 = netdev_priv(dev);
4661 sky2->netdev = dev;
4662 sky2->hw = hw;
4663 sky2->msg_enable = netif_msg_init(debug, default_msg);
4664
cd28ab6a 4665 /* Auto speed and flow control */
0ea065e5
SH		 4666 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4667 if (hw->chip_id != CHIP_ID_YUKON_XL)
f5d64037 4668 dev->hw_features |= NETIF_F_RXCSUM;
0ea065e5 4669
16ad91e1
SH		 4670 sky2->flow_mode = FC_BOTH;
4671
cd28ab6a
SH		 4672 sky2->duplex = -1;
4673 sky2->speed = -1;
4674 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4675 sky2->wol = wol;
75d070c5 4676
e07b1aa8 4677 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4678
793b883e 4679 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4680 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4681 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4682
4683 hw->dev[port] = dev;
4684
4685 sky2->port = port;
4686
f5d64037 4687 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
86aa7785 4688
cd28ab6a
SH		 4689 if (highmem)
4690 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4691
bf73130d
SH		 4692 /* Enable receive hashing unless hardware is known broken */
4693 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
f5d64037
MM		 4694 dev->hw_features |= NETIF_F_RXHASH;
4695
4696 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4697 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4698 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4699 }
bf73130d 4700
f5d64037 4701 dev->features |= dev->hw_features;
d1f13708 4702
cd28ab6a 4703 /* read the mac address */
793b883e 4704 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4705 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4706
cd28ab6a
SH		 4707 return dev;
4708}
4709
28bd181a 4710static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4711{
4712 const struct sky2_port *sky2 = netdev_priv(dev);
4713
6c35abae 4714 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4715}
4716
fb2690a9 4717/* Handle software interrupt used during MSI test */
7d12e780 4718static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4719{
4720 struct sky2_hw *hw = dev_id;
4721 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4722
4723 if (status == 0)
4724 return IRQ_NONE;
4725
4726 if (status & Y2_IS_IRQ_SW) {
ea76e635 4727 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4728 wake_up(&hw->msi_wait);
4729 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4730 }
4731 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4732
4733 return IRQ_HANDLED;
4734}
4735
4736/* Test interrupt path by forcing a a software IRQ */
4737static int __devinit sky2_test_msi(struct sky2_hw *hw)
4738{
4739 struct pci_dev *pdev = hw->pdev;
4740 int err;
4741
060b946c 4742 init_waitqueue_head(&hw->msi_wait);
bb507fe1 4743
fb2690a9
SH		 4744 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4745
b0a20ded 4746 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4747 if (err) {
b02a9258 4748 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4749 return err;
4750 }
4751
fb2690a9 4752 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4753 sky2_read8(hw, B0_CTST);
fb2690a9 4754
ea76e635 4755 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4756
ea76e635 4757 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4758 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4759 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4760 "switching to INTx mode.\n");
fb2690a9
SH		 4761
4762 err = -EOPNOTSUPP;
4763 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4764 }
4765
4766 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4767 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4768
4769 free_irq(pdev->irq, hw);
4770
4771 return err;
4772}
4773
c7127a34
SH		 4774/* This driver supports yukon2 chipset only */
4775static const char *sky2_name(u8 chipid, char *buf, int sz)
4776{
4777 const char *name[] = {
4778 "XL", /* 0xb3 */
4779 "EC Ultra", /* 0xb4 */
4780 "Extreme", /* 0xb5 */
4781 "EC", /* 0xb6 */
4782 "FE", /* 0xb7 */
4783 "FE+", /* 0xb8 */
4784 "Supreme", /* 0xb9 */
0ce8b98d 4785 "UL 2", /* 0xba */
0f5aac70
SH		 4786 "Unknown", /* 0xbb */
4787 "Optima", /* 0xbc */
4fb99cd6 4788 "Optima Prime", /* 0xbd */
4789 "Optima 2", /* 0xbe */
c7127a34
SH		 4790 };
4791
4fb99cd6 4792 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
c7127a34
SH		 4793 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4794 else
4795 snprintf(buf, sz, "(chip %#x)", chipid);
4796 return buf;
4797}
4798
cd28ab6a
SH		 4799static int __devinit sky2_probe(struct pci_dev *pdev,
4800 const struct pci_device_id *ent)
4801{
7f60c64b 4802 struct net_device *dev;
cd28ab6a 4803 struct sky2_hw *hw;
be63a21c 4804 int err, using_dac = 0, wol_default;
3834507d 4805 u32 reg;
c7127a34 4806 char buf1[16];
cd28ab6a 4807
793b883e
SH		 4808 err = pci_enable_device(pdev);
4809 if (err) {
b02a9258 4810 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4811 goto err_out;
4812 }
4813
6cc90a5a
SH		 4814 /* Get configuration information
4815 * Note: only regular PCI config access once to test for HW issues
4816 * other PCI access through shared memory for speed and to
4817 * avoid MMCONFIG problems.
4818 */
4819 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4820 if (err) {
4821 dev_err(&pdev->dev, "PCI read config failed\n");
4822 goto err_out;
4823 }
4824
4825 if (~reg == 0) {
4826 dev_err(&pdev->dev, "PCI configuration read error\n");
4827 goto err_out;
4828 }
4829
793b883e
SH		 4830 err = pci_request_regions(pdev, DRV_NAME);
4831 if (err) {
b02a9258 4832 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4833 goto err_out_disable;
cd28ab6a
SH		 4834 }
4835
4836 pci_set_master(pdev);
4837
d1f3d4dd 4838 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4839 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4840 using_dac = 1;
6a35528a 4841 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4842 if (err < 0) {
b02a9258
SH		 4843 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4844 "for consistent allocations\n");
d1f3d4dd
SH		 4845 goto err_out_free_regions;
4846 }
d1f3d4dd 4847 } else {
284901a9 4848 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4849 if (err) {
b02a9258 4850 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4851 goto err_out_free_regions;
4852 }
4853 }
d1f3d4dd 4854
3834507d
SH		 4855
4856#ifdef __BIG_ENDIAN
4857 /* The sk98lin vendor driver uses hardware byte swapping but
4858 * this driver uses software swapping.
4859 */
4860 reg &= ~PCI_REV_DESC;
060b946c 4861 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3834507d
SH		 4862 if (err) {
4863 dev_err(&pdev->dev, "PCI write config failed\n");
4864 goto err_out_free_regions;
4865 }
4866#endif
4867
9d731d77 4868 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4869
cd28ab6a 4870 err = -ENOMEM;
66466797
SH		 4871
4872 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4873 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4874 if (!hw) {
b02a9258 4875 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4876 goto err_out_free_regions;
4877 }
4878
cd28ab6a 4879 hw->pdev = pdev;
66466797 4880 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4881
4882 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4883 if (!hw->regs) {
b02a9258 4884 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4885 goto err_out_free_hw;
4886 }
4887
e3173832 4888 err = sky2_init(hw);
cd28ab6a 4889 if (err)
793b883e 4890 goto err_out_iounmap;
cd28ab6a 4891
efe91932 4892 /* ring for status responses */
bf73130d 4893 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
efe91932 4894 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4895 &hw->st_dma);
4896 if (!hw->st_le)
4897 goto err_out_reset;
4898
c844d483
SH		 4899 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4900 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4901
e3173832
SH		 4902 sky2_reset(hw);
4903
be63a21c 4904 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4905 if (!dev) {
4906 err = -ENOMEM;
cd28ab6a 4907 goto err_out_free_pci;
7f60c64b 4908 }
cd28ab6a 4909
9fa1b1f3
SH		 4910 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4911 err = sky2_test_msi(hw);
4912 if (err == -EOPNOTSUPP)
4913 pci_disable_msi(pdev);
4914 else if (err)
4915 goto err_out_free_netdev;
4916 }
4917
793b883e
SH		 4918 err = register_netdev(dev);
4919 if (err) {
b02a9258 4920 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4921 goto err_out_free_netdev;
4922 }
4923
33cb7d33
BP		 4924 netif_carrier_off(dev);
4925
6de16237
SH		 4926 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4927
ea76e635
SH		 4928 err = request_irq(pdev->irq, sky2_intr,
4929 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4930 hw->irq_name, hw);
9fa1b1f3 4931 if (err) {
b02a9258 4932 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4933 goto err_out_unregister;
4934 }
4935 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4936 napi_enable(&hw->napi);
9fa1b1f3 4937
cd28ab6a
SH		 4938 sky2_show_addr(dev);
4939
7f60c64b 4940 if (hw->ports > 1) {
4941 struct net_device *dev1;
4942
ca519274 4943 err = -ENOMEM;
be63a21c 4944 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4945 if (dev1 && (err = register_netdev(dev1)) == 0)
4946 sky2_show_addr(dev1);
4947 else {
b02a9258
SH		 4948 dev_warn(&pdev->dev,
4949 "register of second port failed (%d)\n", err);
cd28ab6a 4950 hw->dev[1] = NULL;
ca519274
SH		 4951 hw->ports = 1;
4952 if (dev1)
4953 free_netdev(dev1);
4954 }
cd28ab6a
SH		 4955 }
4956
32c2c300 4957 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4958 INIT_WORK(&hw->restart_work, sky2_restart);
4959
793b883e 4960 pci_set_drvdata(pdev, hw);
1ae861e6 4961 pdev->d3_delay = 150;
793b883e 4962
cd28ab6a
SH		 4963 return 0;
4964
793b883e 4965err_out_unregister:
ea76e635 4966 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4967 pci_disable_msi(pdev);
793b883e 4968 unregister_netdev(dev);
cd28ab6a
SH		 4969err_out_free_netdev:
4970 free_netdev(dev);
cd28ab6a 4971err_out_free_pci:
efe91932 4972 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4973 hw->st_le, hw->st_dma);
4974err_out_reset:
793b883e 4975 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4976err_out_iounmap:
4977 iounmap(hw->regs);
4978err_out_free_hw:
4979 kfree(hw);
4980err_out_free_regions:
4981 pci_release_regions(pdev);
44a1d2e5 4982err_out_disable:
cd28ab6a 4983 pci_disable_device(pdev);
cd28ab6a 4984err_out:
549a68c3 4985 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4986 return err;
4987}
4988
4989static void __devexit sky2_remove(struct pci_dev *pdev)
4990{
793b883e 4991 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4992 int i;
cd28ab6a 4993
793b883e 4994 if (!hw)
cd28ab6a
SH		 4995 return;
4996
32c2c300 4997 del_timer_sync(&hw->watchdog_timer);
6de16237 4998 cancel_work_sync(&hw->restart_work);
d27ed387 4999
b877fe28 5000 for (i = hw->ports-1; i >= 0; --i)
6de16237 5001 unregister_netdev(hw->dev[i]);
81906791 5002
d27ed387 5003 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 5004
ae306cca
SH		 5005 sky2_power_aux(hw);
5006
793b883e 5007 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 5008 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 5009
5010 free_irq(pdev->irq, hw);
ea76e635 5011 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 5012 pci_disable_msi(pdev);
efe91932 5013 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5014 hw->st_le, hw->st_dma);
cd28ab6a
SH		 5015 pci_release_regions(pdev);
5016 pci_disable_device(pdev);
793b883e 5017
b877fe28 5018 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 5019 free_netdev(hw->dev[i]);
5020
cd28ab6a
SH		 5021 iounmap(hw->regs);
5022 kfree(hw);
5afa0a9c 5023
cd28ab6a
SH		 5024 pci_set_drvdata(pdev, NULL);
5025}
5026
0f333d10 5027static int sky2_suspend(struct device *dev)
cd28ab6a 5028{
0f333d10 5029 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 5030 struct sky2_hw *hw = pci_get_drvdata(pdev);
0f333d10 5031 int i;
cd28ab6a 5032
549a68c3
SH		 5033 if (!hw)
5034 return 0;
5035
063a0b38
SH		 5036 del_timer_sync(&hw->watchdog_timer);
5037 cancel_work_sync(&hw->restart_work);
5038
19720737 5039 rtnl_lock();
3403aca2
MM		 5040
5041 sky2_all_down(hw);
f05267e7 5042 for (i = 0; i < hw->ports; i++) {
cd28ab6a 5043 struct net_device *dev = hw->dev[i];
e3173832 5044 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 5045
e3173832
SH		 5046 if (sky2->wol)
5047 sky2_wol_init(sky2);
cd28ab6a
SH		 5048 }
5049
ae306cca 5050 sky2_power_aux(hw);
19720737 5051 rtnl_unlock();
e3173832 5052
2ccc99b7 5053 return 0;
cd28ab6a
SH		 5054}
5055
94252763 5056#ifdef CONFIG_PM_SLEEP
0f333d10 5057static int sky2_resume(struct device *dev)
cd28ab6a 5058{
0f333d10 5059 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 5060 struct sky2_hw *hw = pci_get_drvdata(pdev);
3403aca2 5061 int err;
cd28ab6a 5062
549a68c3
SH		 5063 if (!hw)
5064 return 0;
5065
1ad5b4a5 5066 /* Re-enable all clocks */
a0db28b8 5067 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5068 if (err) {
5069 dev_err(&pdev->dev, "PCI write config failed\n");
5070 goto out;
5071 }
1ad5b4a5 5072
3403aca2 5073 rtnl_lock();
e3173832 5074 sky2_reset(hw);
3403aca2 5075 sky2_all_up(hw);
af18d8b8 5076 rtnl_unlock();
eb35cf60 5077
ae306cca 5078 return 0;
08c06d8a 5079out:
af18d8b8 5080
b02a9258 5081 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 5082 pci_disable_device(pdev);
08c06d8a 5083 return err;
cd28ab6a 5084}
0f333d10
RW		 5085
5086static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5087#define SKY2_PM_OPS (&sky2_pm_ops)
5088
5089#else
5090
5091#define SKY2_PM_OPS NULL
cd28ab6a
SH		 5092#endif
5093
e3173832
SH		 5094static void sky2_shutdown(struct pci_dev *pdev)
5095{
0f333d10
RW		 5096 sky2_suspend(&pdev->dev);
5097 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5098 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 5099}
5100
cd28ab6a 5101static struct pci_driver sky2_driver = {
793b883e
SH		 5102 .name = DRV_NAME,
5103 .id_table = sky2_id_table,
5104 .probe = sky2_probe,
5105 .remove = __devexit_p(sky2_remove),
e3173832 5106 .shutdown = sky2_shutdown,
0f333d10 5107 .driver.pm = SKY2_PM_OPS,
cd28ab6a
SH		 5108};
5109
5110static int __init sky2_init_module(void)
5111{
ada1db5c 5112 pr_info("driver version " DRV_VERSION "\n");
c844d483 5113
3cf26753 5114 sky2_debug_init();
50241c4c 5115 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 5116}
5117
5118static void __exit sky2_cleanup_module(void)
5119{
5120 pci_unregister_driver(&sky2_driver);
3cf26753 5121 sky2_debug_cleanup();
cd28ab6a
SH		 5122}
5123
5124module_init(sky2_init_module);
5125module_exit(sky2_cleanup_module);
5126
5127MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 5128MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 5129MODULE_LICENSE("GPL");
5f4f9dc1 5130MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)