projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sky2: FE+ vlan workaround
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
faf60e72 54#define DRV_VERSION "1.18"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 136 { 0 }
137};
793b883e 138
cd28ab6a
SH		 139MODULE_DEVICE_TABLE(pci, sky2_id_table);
140
141/* Avoid conditionals by using array */
142static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 144static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 145
92f965e8
SH		 146/* This driver supports yukon2 chipset only */
147static const char *yukon2_name[] = {
148 "XL", /* 0xb3 */
149 "EC Ultra", /* 0xb4 */
93745494 150 "Extreme", /* 0xb5 */
92f965e8
SH		 151 "EC", /* 0xb6 */
152 "FE", /* 0xb7 */
05745c4a 153 "FE+", /* 0xb8 */
793b883e
SH		 154};
155
d1b139c0
SH		 156static void sky2_set_multicast(struct net_device *dev);
157
793b883e 158/* Access to external PHY */
ef743d33 159static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 160{
161 int i;
162
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
166
167 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 168 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 169 return 0;
793b883e 170 udelay(1);
cd28ab6a 171 }
ef743d33 172
793b883e 173 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 174 return -ETIMEDOUT;
cd28ab6a
SH		 175}
176
ef743d33 177static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 178{
179 int i;
180
793b883e 181 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 182 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
183
184 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 185 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
186 *val = gma_read16(hw, port, GM_SMI_DATA);
187 return 0;
188 }
189
793b883e 190 udelay(1);
cd28ab6a
SH		 191 }
192
ef743d33
SH		 193 return -ETIMEDOUT;
194}
195
196static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
197{
198 u16 v;
199
200 if (__gm_phy_read(hw, port, reg, &v) != 0)
201 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
202 return v;
cd28ab6a
SH		 203}
204
5afa0a9c 205
ae306cca
SH		 206static void sky2_power_on(struct sky2_hw *hw)
207{
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw, B0_POWER_CTRL,
210 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 211
ae306cca
SH		 212 /* disable Core Clock Division, */
213 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 214
ae306cca
SH		 215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
216 /* enable bits are inverted */
217 sky2_write8(hw, B2_Y2_CLK_GATE,
218 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
219 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
220 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
221 else
222 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 223
ea76e635 224 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 225 u32 reg;
5afa0a9c 226
b2345773
SH		 227 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
228
fc99fe06
SH		 229 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
230 /* set all bits to 0 except bits 15..12 and 8 */
231 reg &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
233
234 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
235 /* set all bits to 0 except bits 28 & 27 */
236 reg &= P_CTL_TIM_VMAIN_AV_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
238
239 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 240
241 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
242 reg = sky2_read32(hw, B2_GP_IO);
243 reg |= GLB_GPIO_STAT_RACE_DIS;
244 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 245
246 sky2_read32(hw, B2_GP_IO);
5afa0a9c 247 }
ae306cca 248}
5afa0a9c 249
ae306cca
SH		 250static void sky2_power_aux(struct sky2_hw *hw)
251{
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
254 else
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
260
261 /* switch power to VAUX */
262 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
16ad91e1
SH		 287/* flow control to advertise bits */
288static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293};
294
295/* flow control to advertise bits when using 1000BaseX */
296static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301};
302
303/* flow control to GMA disable bits */
304static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309};
310
311
cd28ab6a
SH		 312static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
313{
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 316
ea76e635
SH		 317 if (sky2->autoneg == AUTONEG_ENABLE &&
318 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 322 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324
53419c68 325 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 326 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 327 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 328 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
329 else
53419c68
SH		 330 /* set master & slave downshift counter to 1x */
331 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 332
333 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
334 }
335
336 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 337 if (sky2_is_copper(hw)) {
05745c4a 338 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 341
342 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
343 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
344 u16 spec;
345
346 /* Enable Class A driver for FE+ A0 */
347 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
348 spec |= PHY_M_FESC_SEL_CL_A;
349 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
350 }
cd28ab6a
SH		 351 } else {
352 /* disable energy detect */
353 ctrl &= ~PHY_M_PC_EN_DET_MSK;
354
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
357
53419c68 358 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 359 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 360 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 361 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 362 ctrl &= ~PHY_M_PC_DSC_MSK;
363 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
364 }
365 }
cd28ab6a
SH		 366 } else {
367 /* workaround for deviation #4.88 (CRC errors) */
368 /* disable Automatic Crossover */
369
370 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 371 }
cd28ab6a 372
b89165f2
SH		 373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
374
375 /* special setup for PHY 88E1112 Fiber */
ea76e635 376 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 377 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 378
b89165f2
SH		 379 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
381 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
382 ctrl &= ~PHY_M_MAC_MD_MSK;
383 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
384 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
385
386 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 387 /* select page 1 to access Fiber registers */
388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 389
390 /* for SFP-module set SIGDET polarity to low */
391 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
392 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 394 }
b89165f2
SH		 395
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 397 }
398
7800fddc 399 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 400 ct1000 = 0;
401 adv = PHY_AN_CSMA;
2eaba1a2 402 reg = 0;
cd28ab6a
SH		 403
404 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 405 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 ct1000 |= PHY_M_1000C_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 ct1000 |= PHY_M_1000C_AHD;
410 if (sky2->advertising & ADVERTISED_100baseT_Full)
411 adv |= PHY_M_AN_100_FD;
412 if (sky2->advertising & ADVERTISED_100baseT_Half)
413 adv |= PHY_M_AN_100_HD;
414 if (sky2->advertising & ADVERTISED_10baseT_Full)
415 adv |= PHY_M_AN_10_FD;
416 if (sky2->advertising & ADVERTISED_10baseT_Half)
417 adv |= PHY_M_AN_10_HD;
709c6e7b 418
16ad91e1 419 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 420 } else { /* special defines for FIBER (88E1040S only) */
421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 adv |= PHY_M_AN_1000X_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 425
16ad91e1 426 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 427 }
cd28ab6a
SH		 428
429 /* Restart Auto-negotiation */
430 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
431 } else {
432 /* forced speed/duplex settings */
433 ct1000 = PHY_M_1000C_MSE;
434
2eaba1a2
SH		 435 /* Disable auto update for duplex flow control and speed */
436 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 437
438 switch (sky2->speed) {
439 case SPEED_1000:
440 ctrl |= PHY_CT_SP1000;
2eaba1a2 441 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 442 break;
443 case SPEED_100:
444 ctrl |= PHY_CT_SP100;
2eaba1a2 445 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 446 break;
447 }
448
2eaba1a2
SH		 449 if (sky2->duplex == DUPLEX_FULL) {
450 reg |= GM_GPCR_DUP_FULL;
451 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 452 } else if (sky2->speed < SPEED_1000)
453 sky2->flow_mode = FC_NONE;
2eaba1a2 454
2eaba1a2 455
16ad91e1 456 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 457
458 /* Forward pause packets to GMAC? */
16ad91e1 459 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 460 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
461 else
462 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 463 }
464
2eaba1a2
SH		 465 gma_write16(hw, port, GM_GP_CTRL, reg);
466
05745c4a 467 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 468 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
469
470 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
471 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
472
473 /* Setup Phy LED's */
474 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
475 ledover = 0;
476
477 switch (hw->chip_id) {
478 case CHIP_ID_YUKON_FE:
479 /* on 88E3082 these bits are at 11..9 (shifted left) */
480 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
481
482 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
483
484 /* delete ACT LED control bits */
485 ctrl &= ~PHY_M_FELP_LED1_MSK;
486 /* change ACT LED control to blink mode */
487 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
488 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
489 break;
490
05745c4a
SH		 491 case CHIP_ID_YUKON_FE_P:
492 /* Enable Link Partner Next Page */
493 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
494 ctrl |= PHY_M_PC_ENA_LIP_NP;
495
496 /* disable Energy Detect and enable scrambler */
497 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
498 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
499
500 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
501 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
502 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
503 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
504
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
cd28ab6a 508 case CHIP_ID_YUKON_XL:
793b883e 509 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 510
511 /* select page 3 to access LED control register */
512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
513
514 /* set LED Function Control register */
ed6d32c7
SH		 515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
516 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
517 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
518 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
519 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 520
521 /* set Polarity Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 523 (PHY_M_POLC_LS1_P_MIX(4) |
524 PHY_M_POLC_IS0_P_MIX(4) |
525 PHY_M_POLC_LOS_CTRL(2) |
526 PHY_M_POLC_INIT_CTRL(2) |
527 PHY_M_POLC_STA1_CTRL(2) |
528 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 529
530 /* restore page register */
793b883e 531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 532 break;
93745494 533
ed6d32c7 534 case CHIP_ID_YUKON_EC_U:
93745494 535 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 536 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
537
538 /* select page 3 to access LED control register */
539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
540
541 /* set LED Function Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
543 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
544 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
545 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
546 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
547
548 /* set Blink Rate in LED Timer Control Register */
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
550 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
551 /* restore page register */
552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
553 break;
cd28ab6a
SH		 554
555 default:
556 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
557 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
558 /* turn off the Rx LED (LED_RX) */
0efdf262 559 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 560 }
561
9467a8fc
SH		 562 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
563 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 564 /* apply fixes in PHY AFE */
ed6d32c7
SH		 565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
566
977bdf06 567 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 568 gm_phy_write(hw, port, 0x18, 0xaa99);
569 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 570
977bdf06 571 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 572 gm_phy_write(hw, port, 0x18, 0xa204);
573 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 574
575 /* set page register to 0 */
9467a8fc 576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 577 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
578 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
579 /* apply workaround for integrated resistors calibration */
580 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
581 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 582 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 583 /* no effect on Yukon-XL */
977bdf06 584 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 585
977bdf06
SH		 586 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
587 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 588 ledover |= PHY_M_LED_MO_100;
977bdf06 589 }
cd28ab6a 590
977bdf06
SH		 591 if (ledover)
592 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
593
594 }
2eaba1a2 595
d571b694 596 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 597 if (sky2->autoneg == AUTONEG_ENABLE)
598 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
599 else
600 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
601}
602
d3bcfbeb
SH		 603static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
604{
605 u32 reg1;
606 static const u32 phy_power[]
607 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
608
609 /* looks like this XL is back asswards .. */
610 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
611 onoff = !onoff;
612
aed2cec4 613 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 614 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 615 if (onoff)
616 /* Turn off phy power saving */
617 reg1 &= ~phy_power[port];
618 else
619 reg1 |= phy_power[port];
620
621 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 622 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 623 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 624 udelay(100);
625}
626
1b537565
SH		 627/* Force a renegotiation */
628static void sky2_phy_reinit(struct sky2_port *sky2)
629{
e07b1aa8 630 spin_lock_bh(&sky2->phy_lock);
1b537565 631 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 632 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 633}
634
e3173832
SH		 635/* Put device in state to listen for Wake On Lan */
636static void sky2_wol_init(struct sky2_port *sky2)
637{
638 struct sky2_hw *hw = sky2->hw;
639 unsigned port = sky2->port;
640 enum flow_control save_mode;
641 u16 ctrl;
642 u32 reg1;
643
644 /* Bring hardware out of reset */
645 sky2_write16(hw, B0_CTST, CS_RST_CLR);
646 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
647
648 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
649 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
650
651 /* Force to 10/100
652 * sky2_reset will re-enable on resume
653 */
654 save_mode = sky2->flow_mode;
655 ctrl = sky2->advertising;
656
657 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
658 sky2->flow_mode = FC_NONE;
659 sky2_phy_power(hw, port, 1);
660 sky2_phy_reinit(sky2);
661
662 sky2->flow_mode = save_mode;
663 sky2->advertising = ctrl;
664
665 /* Set GMAC to no flow control and auto update for speed/duplex */
666 gma_write16(hw, port, GM_GP_CTRL,
667 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
668 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
669
670 /* Set WOL address */
671 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
672 sky2->netdev->dev_addr, ETH_ALEN);
673
674 /* Turn on appropriate WOL control bits */
675 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
676 ctrl = 0;
677 if (sky2->wol & WAKE_PHY)
678 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
679 else
680 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
681
682 if (sky2->wol & WAKE_MAGIC)
683 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
684 else
685 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
686
687 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
688 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
689
690 /* Turn on legacy PCI-Express PME mode */
691 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
692 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
693 reg1 |= PCI_Y2_PME_LEGACY;
694 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
695 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
696
697 /* block receiver */
698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
699
700}
701
69161611
SH		 702static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
703{
05745c4a
SH		 704 struct net_device *dev = hw->dev[port];
705
706 if (dev->mtu <= ETH_DATA_LEN)
69161611 707 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 708 TX_JUMBO_DIS | TX_STFW_ENA);
709
710 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
711 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
712 TX_STFW_ENA | TX_JUMBO_ENA);
713 else {
714 /* set Tx GMAC FIFO Almost Empty Threshold */
715 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
716 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 717
05745c4a
SH		 718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
719 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 720
05745c4a
SH		 721 /* Can't do offload because of lack of store/forward */
722 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 723 }
724}
725
cd28ab6a
SH		 726static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
727{
728 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
729 u16 reg;
25cccecc 730 u32 rx_reg;
cd28ab6a
SH		 731 int i;
732 const u8 *addr = hw->dev[port]->dev_addr;
733
f350339c
SH		 734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
735 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 736
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
738
793b883e 739 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 740 /* WA DEV_472 -- looks like crossed wires on port 2 */
741 /* clear GMAC 1 Control reset */
742 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
743 do {
744 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
745 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
746 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
747 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
748 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
749 }
750
793b883e 751 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 752
2eaba1a2
SH		 753 /* Enable Transmit FIFO Underrun */
754 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
755
e07b1aa8 756 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 757 sky2_phy_init(hw, port);
e07b1aa8 758 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 759
760 /* MIB clear */
761 reg = gma_read16(hw, port, GM_PHY_ADDR);
762 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
763
43f2f104
SH		 764 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
765 gma_read16(hw, port, i);
cd28ab6a
SH		 766 gma_write16(hw, port, GM_PHY_ADDR, reg);
767
768 /* transmit control */
769 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
770
771 /* receive control reg: unicast + multicast + no FCS */
772 gma_write16(hw, port, GM_RX_CTRL,
793b883e 773 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 774
775 /* transmit flow control */
776 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
777
778 /* transmit parameter */
779 gma_write16(hw, port, GM_TX_PARAM,
780 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
781 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
782 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
783 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
784
785 /* serial mode register */
786 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 787 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 788
6b1a3aef 789 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 790 reg |= GM_SMOD_JUMBO_ENA;
791
792 gma_write16(hw, port, GM_SERIAL_MODE, reg);
793
cd28ab6a
SH		 794 /* virtual address for data */
795 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
796
793b883e
SH		 797 /* physical address: used for pause frames */
798 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
799
800 /* ignore counter overflows */
cd28ab6a
SH		 801 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
802 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
803 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
804
805 /* Configure Rx MAC FIFO */
806 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 807 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 808 if (hw->chip_id == CHIP_ID_YUKON_EX ||
809 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 810 rx_reg |= GMF_RX_OVER_ON;
69161611 811
25cccecc 812 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 813
d571b694 814 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 815 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 816
8df9a876 817 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 818 reg = RX_GMF_FL_THR_DEF + 1;
819 /* Another magic mystery workaround from sk98lin */
820 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
821 hw->chip_rev == CHIP_REV_YU_FE2_A0)
822 reg = 0x178;
823 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 824
825 /* Configure Tx MAC FIFO */
826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
827 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 828
e0c28116
SH		 829 /* On chips without ram buffer, pause is controled by MAC level */
830 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 831 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 832 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 833
69161611 834 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 835 }
836
cd28ab6a
SH		 837}
838
67712901
SH		 839/* Assign Ram Buffer allocation to queue */
840static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 841{
67712901
SH		 842 u32 end;
843
844 /* convert from K bytes to qwords used for hw register */
845 start *= 1024/8;
846 space *= 1024/8;
847 end = start + space - 1;
793b883e 848
cd28ab6a
SH		 849 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
850 sky2_write32(hw, RB_ADDR(q, RB_START), start);
851 sky2_write32(hw, RB_ADDR(q, RB_END), end);
852 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
853 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
854
855 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 856 u32 tp = space - space/4;
793b883e 857
1c28f6ba
SH		 858 /* On receive queue's set the thresholds
859 * give receiver priority when > 3/4 full
860 * send pause when down to 2K
861 */
862 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
863 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 864
1c28f6ba
SH		 865 tp = space - 2048/8;
866 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
867 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 868 } else {
869 /* Enable store & forward on Tx queue's because
870 * Tx FIFO is only 1K on Yukon
871 */
872 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
873 }
874
875 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 876 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 877}
878
cd28ab6a 879/* Setup Bus Memory Interface */
af4ed7e6 880static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 881{
882 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
883 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
884 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 885 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 886}
887
cd28ab6a
SH		 888/* Setup prefetch unit registers. This is the interface between
889 * hardware and driver list elements
890 */
8cc048e3 891static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 892 u64 addr, u32 last)
893{
cd28ab6a
SH		 894 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
895 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
896 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
897 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
898 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
899 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 900
901 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 902}
903
793b883e
SH		 904static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
905{
906 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
907
cb5d9547 908 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 909 le->ctrl = 0;
793b883e
SH		 910 return le;
911}
cd28ab6a 912
291ea614
SH		 913static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
914 struct sky2_tx_le *le)
915{
916 return sky2->tx_ring + (le - sky2->tx_le);
917}
918
290d4de5
SH		 919/* Update chip's next pointer */
920static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 921{
50432cb5 922 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 923 wmb();
50432cb5
SH		 924 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
925
926 /* Synchronize I/O on since next processor may write to tail */
927 mmiowb();
cd28ab6a
SH		 928}
929
793b883e 930
cd28ab6a
SH		 931static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
932{
933 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 934 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 935 le->ctrl = 0;
cd28ab6a
SH		 936 return le;
937}
938
14d0263f
SH		 939/* Build description to hardware for one receive segment */
940static void sky2_rx_add(struct sky2_port *sky2, u8 op,
941 dma_addr_t map, unsigned len)
cd28ab6a
SH		 942{
943 struct sky2_rx_le *le;
36eb0c71 944 u32 hi = upper_32_bits(map);
cd28ab6a 945
793b883e 946 if (sky2->rx_addr64 != hi) {
cd28ab6a 947 le = sky2_next_rx(sky2);
793b883e 948 le->addr = cpu_to_le32(hi);
cd28ab6a 949 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 950 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 951 }
793b883e 952
cd28ab6a 953 le = sky2_next_rx(sky2);
734d1868
SH		 954 le->addr = cpu_to_le32((u32) map);
955 le->length = cpu_to_le16(len);
14d0263f 956 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 957}
958
14d0263f
SH		 959/* Build description to hardware for one possibly fragmented skb */
960static void sky2_rx_submit(struct sky2_port *sky2,
961 const struct rx_ring_info *re)
962{
963 int i;
964
965 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
966
967 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
968 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
969}
970
971
972static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
973 unsigned size)
974{
975 struct sk_buff *skb = re->skb;
976 int i;
977
978 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
979 pci_unmap_len_set(re, data_size, size);
980
981 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
982 re->frag_addr[i] = pci_map_page(pdev,
983 skb_shinfo(skb)->frags[i].page,
984 skb_shinfo(skb)->frags[i].page_offset,
985 skb_shinfo(skb)->frags[i].size,
986 PCI_DMA_FROMDEVICE);
987}
988
989static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
990{
991 struct sk_buff *skb = re->skb;
992 int i;
993
994 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
995 PCI_DMA_FROMDEVICE);
996
997 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
998 pci_unmap_page(pdev, re->frag_addr[i],
999 skb_shinfo(skb)->frags[i].size,
1000 PCI_DMA_FROMDEVICE);
1001}
793b883e 1002
cd28ab6a
SH		 1003/* Tell chip where to start receive checksum.
1004 * Actually has two checksums, but set both same to avoid possible byte
1005 * order problems.
1006 */
793b883e 1007static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1008{
ea76e635 1009 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1010
ea76e635
SH		 1011 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1012 le->ctrl = 0;
1013 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1014
ea76e635
SH		 1015 sky2_write32(sky2->hw,
1016 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1017 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1018}
1019
6b1a3aef
SH		 1020/*
1021 * The RX Stop command will not work for Yukon-2 if the BMU does not
1022 * reach the end of packet and since we can't make sure that we have
1023 * incoming data, we must reset the BMU while it is not doing a DMA
1024 * transfer. Since it is possible that the RX path is still active,
1025 * the RX RAM buffer will be stopped first, so any possible incoming
1026 * data will not trigger a DMA. After the RAM buffer is stopped, the
1027 * BMU is polled until any DMA in progress is ended and only then it
1028 * will be reset.
1029 */
1030static void sky2_rx_stop(struct sky2_port *sky2)
1031{
1032 struct sky2_hw *hw = sky2->hw;
1033 unsigned rxq = rxqaddr[sky2->port];
1034 int i;
1035
1036 /* disable the RAM Buffer receive queue */
1037 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1038
1039 for (i = 0; i < 0xffff; i++)
1040 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1041 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1042 goto stopped;
1043
1044 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1045 sky2->netdev->name);
1046stopped:
1047 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1048
1049 /* reset the Rx prefetch unit */
1050 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1051 mmiowb();
6b1a3aef 1052}
793b883e 1053
d571b694 1054/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1055static void sky2_rx_clean(struct sky2_port *sky2)
1056{
1057 unsigned i;
1058
1059 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1060 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1061 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1062
1063 if (re->skb) {
14d0263f 1064 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1065 kfree_skb(re->skb);
1066 re->skb = NULL;
1067 }
1068 }
1069}
1070
ef743d33
SH		 1071/* Basic MII support */
1072static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1073{
1074 struct mii_ioctl_data *data = if_mii(ifr);
1075 struct sky2_port *sky2 = netdev_priv(dev);
1076 struct sky2_hw *hw = sky2->hw;
1077 int err = -EOPNOTSUPP;
1078
1079 if (!netif_running(dev))
1080 return -ENODEV; /* Phy still in reset */
1081
d89e1343 1082 switch (cmd) {
ef743d33
SH		 1083 case SIOCGMIIPHY:
1084 data->phy_id = PHY_ADDR_MARV;
1085
1086 /* fallthru */
1087 case SIOCGMIIREG: {
1088 u16 val = 0;
91c86df5 1089
e07b1aa8 1090 spin_lock_bh(&sky2->phy_lock);
ef743d33 1091 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1092 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1093
ef743d33
SH		 1094 data->val_out = val;
1095 break;
1096 }
1097
1098 case SIOCSMIIREG:
1099 if (!capable(CAP_NET_ADMIN))
1100 return -EPERM;
1101
e07b1aa8 1102 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1103 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1104 data->val_in);
e07b1aa8 1105 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1106 break;
1107 }
1108 return err;
1109}
1110
d1f13708
SH		 1111#ifdef SKY2_VLAN_TAG_USED
1112static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1113{
1114 struct sky2_port *sky2 = netdev_priv(dev);
1115 struct sky2_hw *hw = sky2->hw;
1116 u16 port = sky2->port;
d1f13708 1117
2bb8c262 1118 netif_tx_lock_bh(dev);
3d4e66f5 1119 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1120
d1f13708 1121 sky2->vlgrp = grp;
3d4e66f5
SH		 1122 if (grp) {
1123 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1124 RX_VLAN_STRIP_ON);
1125 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1126 TX_VLAN_TAG_ON);
1127 } else {
1128 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1129 RX_VLAN_STRIP_OFF);
1130 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1131 TX_VLAN_TAG_OFF);
1132 }
d1f13708 1133
3d4e66f5 1134 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1135 netif_tx_unlock_bh(dev);
d1f13708
SH		 1136}
1137#endif
1138
82788c7a 1139/*
14d0263f
SH		 1140 * Allocate an skb for receiving. If the MTU is large enough
1141 * make the skb non-linear with a fragment list of pages.
1142 *
82788c7a
SH		 1143 * It appears the hardware has a bug in the FIFO logic that
1144 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1145 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1146 * aligned except if slab debugging is enabled.
82788c7a 1147 */
14d0263f 1148static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1149{
1150 struct sk_buff *skb;
14d0263f
SH		 1151 unsigned long p;
1152 int i;
82788c7a 1153
14d0263f
SH		 1154 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1155 if (!skb)
1156 goto nomem;
1157
1158 p = (unsigned long) skb->data;
1159 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1160
1161 for (i = 0; i < sky2->rx_nfrags; i++) {
1162 struct page *page = alloc_page(GFP_ATOMIC);
1163
1164 if (!page)
1165 goto free_partial;
1166 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1167 }
1168
1169 return skb;
14d0263f
SH		 1170free_partial:
1171 kfree_skb(skb);
1172nomem:
1173 return NULL;
82788c7a
SH		 1174}
1175
55c9dd35
SH		 1176static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1177{
1178 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1179}
1180
cd28ab6a
SH		 1181/*
1182 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1183 * Normal case this ends up creating one list element for skb
1184 * in the receive ring. Worst case if using large MTU and each
1185 * allocation falls on a different 64 bit region, that results
1186 * in 6 list elements per ring entry.
1187 * One element is used for checksum enable/disable, and one
1188 * extra to avoid wrap.
cd28ab6a 1189 */
6b1a3aef 1190static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1191{
6b1a3aef 1192 struct sky2_hw *hw = sky2->hw;
14d0263f 1193 struct rx_ring_info *re;
6b1a3aef 1194 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1195 unsigned i, size, space, thresh;
cd28ab6a 1196
6b1a3aef 1197 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1198 sky2_qset(hw, rxq);
977bdf06 1199
c3905bc4
SH		 1200 /* On PCI express lowering the watermark gives better performance */
1201 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1202 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1203
1204 /* These chips have no ram buffer?
1205 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1206 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1207 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1208 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1209 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1210
6b1a3aef
SH		 1211 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1212
ea76e635
SH		 1213 if (!(hw->flags & SKY2_HW_NEW_LE))
1214 rx_set_checksum(sky2);
14d0263f
SH		 1215
1216 /* Space needed for frame data + headers rounded up */
f957da2a 1217 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1218
1219 /* Stopping point for hardware truncation */
1220 thresh = (size - 8) / sizeof(u32);
1221
1222 /* Account for overhead of skb - to avoid order > 0 allocation */
1223 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1224 + sizeof(struct skb_shared_info);
1225
1226 sky2->rx_nfrags = space >> PAGE_SHIFT;
1227 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1228
1229 if (sky2->rx_nfrags != 0) {
1230 /* Compute residue after pages */
1231 space = sky2->rx_nfrags << PAGE_SHIFT;
1232
1233 if (space < size)
1234 size -= space;
1235 else
1236 size = 0;
1237
1238 /* Optimize to handle small packets and headers */
1239 if (size < copybreak)
1240 size = copybreak;
1241 if (size < ETH_HLEN)
1242 size = ETH_HLEN;
1243 }
1244 sky2->rx_data_size = size;
1245
1246 /* Fill Rx ring */
793b883e 1247 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1248 re = sky2->rx_ring + i;
cd28ab6a 1249
14d0263f 1250 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1251 if (!re->skb)
1252 goto nomem;
1253
14d0263f
SH		 1254 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1255 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1256 }
1257
a1433ac4
SH		 1258 /*
1259 * The receiver hangs if it receives frames larger than the
1260 * packet buffer. As a workaround, truncate oversize frames, but
1261 * the register is limited to 9 bits, so if you do frames > 2052
1262 * you better get the MTU right!
1263 */
a1433ac4
SH		 1264 if (thresh > 0x1ff)
1265 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1266 else {
1267 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1268 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1269 }
1270
6b1a3aef 1271 /* Tell chip about available buffers */
55c9dd35 1272 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1273 return 0;
1274nomem:
1275 sky2_rx_clean(sky2);
1276 return -ENOMEM;
1277}
1278
1279/* Bring up network interface. */
1280static int sky2_up(struct net_device *dev)
1281{
1282 struct sky2_port *sky2 = netdev_priv(dev);
1283 struct sky2_hw *hw = sky2->hw;
1284 unsigned port = sky2->port;
e0c28116 1285 u32 imask, ramsize;
ee7abb04 1286 int cap, err = -ENOMEM;
843a46f4 1287 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1288
ee7abb04
SH		 1289 /*
1290 * On dual port PCI-X card, there is an problem where status
1291 * can be received out of order due to split transactions
843a46f4 1292 */
ee7abb04
SH		 1293 if (otherdev && netif_running(otherdev) &&
1294 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1295 struct sky2_port *osky2 = netdev_priv(otherdev);
1296 u16 cmd;
1297
1298 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1299 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1300 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1301
1302 sky2->rx_csum = 0;
1303 osky2->rx_csum = 0;
1304 }
843a46f4 1305
cd28ab6a
SH		 1306 if (netif_msg_ifup(sky2))
1307 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1308
55d7b4e6
SH		 1309 netif_carrier_off(dev);
1310
cd28ab6a
SH		 1311 /* must be power of 2 */
1312 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1313 TX_RING_SIZE *
1314 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1315 &sky2->tx_le_map);
1316 if (!sky2->tx_le)
1317 goto err_out;
1318
6cdbbdf3 1319 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1320 GFP_KERNEL);
1321 if (!sky2->tx_ring)
1322 goto err_out;
1323 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1324
1325 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1326 &sky2->rx_le_map);
1327 if (!sky2->rx_le)
1328 goto err_out;
1329 memset(sky2->rx_le, 0, RX_LE_BYTES);
1330
291ea614 1331 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1332 GFP_KERNEL);
1333 if (!sky2->rx_ring)
1334 goto err_out;
1335
d3bcfbeb
SH		 1336 sky2_phy_power(hw, port, 1);
1337
cd28ab6a
SH		 1338 sky2_mac_init(hw, port);
1339
e0c28116
SH		 1340 /* Register is number of 4K blocks on internal RAM buffer. */
1341 ramsize = sky2_read8(hw, B2_E_0) * 4;
1342 if (ramsize > 0) {
67712901 1343 u32 rxspace;
cd28ab6a 1344
e0c28116 1345 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1346 if (ramsize < 16)
1347 rxspace = ramsize / 2;
1348 else
1349 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1350
67712901
SH		 1351 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1352 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1353
1354 /* Make sure SyncQ is disabled */
1355 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1356 RB_RST_SET);
1357 }
793b883e 1358
af4ed7e6 1359 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1360
69161611
SH		 1361 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1362 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1363 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1364
977bdf06 1365 /* Set almost empty threshold */
c2716fb4
SH		 1366 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1367 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1368 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1369
6b1a3aef
SH		 1370 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1371 TX_RING_SIZE - 1);
cd28ab6a 1372
6b1a3aef 1373 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1374 if (err)
1375 goto err_out;
1376
cd28ab6a 1377 /* Enable interrupts from phy/mac for port */
e07b1aa8 1378 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1379 imask |= portirq_msk[port];
e07b1aa8
SH		 1380 sky2_write32(hw, B0_IMSK, imask);
1381
cd28ab6a
SH		 1382 return 0;
1383
1384err_out:
1b537565 1385 if (sky2->rx_le) {
cd28ab6a
SH		 1386 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1387 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1388 sky2->rx_le = NULL;
1389 }
1390 if (sky2->tx_le) {
cd28ab6a
SH		 1391 pci_free_consistent(hw->pdev,
1392 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1393 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1394 sky2->tx_le = NULL;
1395 }
1396 kfree(sky2->tx_ring);
1397 kfree(sky2->rx_ring);
cd28ab6a 1398
1b537565
SH		 1399 sky2->tx_ring = NULL;
1400 sky2->rx_ring = NULL;
cd28ab6a
SH		 1401 return err;
1402}
1403
793b883e
SH		 1404/* Modular subtraction in ring */
1405static inline int tx_dist(unsigned tail, unsigned head)
1406{
cb5d9547 1407 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1408}
cd28ab6a 1409
793b883e
SH		 1410/* Number of list elements available for next tx */
1411static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1412{
793b883e 1413 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1414}
1415
793b883e 1416/* Estimate of number of transmit list elements required */
28bd181a 1417static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1418{
793b883e
SH		 1419 unsigned count;
1420
1421 count = sizeof(dma_addr_t) / sizeof(u32);
1422 count += skb_shinfo(skb)->nr_frags * count;
1423
89114afd 1424 if (skb_is_gso(skb))
793b883e
SH		 1425 ++count;
1426
84fa7933 1427 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1428 ++count;
1429
1430 return count;
cd28ab6a
SH		 1431}
1432
793b883e
SH		 1433/*
1434 * Put one packet in ring for transmit.
1435 * A single packet can generate multiple list elements, and
1436 * the number of ring elements will probably be less than the number
1437 * of list elements used.
1438 */
cd28ab6a
SH		 1439static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1440{
1441 struct sky2_port *sky2 = netdev_priv(dev);
1442 struct sky2_hw *hw = sky2->hw;
d1f13708 1443 struct sky2_tx_le *le = NULL;
6cdbbdf3 1444 struct tx_ring_info *re;
cd28ab6a
SH		 1445 unsigned i, len;
1446 dma_addr_t mapping;
1447 u32 addr64;
1448 u16 mss;
1449 u8 ctrl;
1450
2bb8c262
SH		 1451 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1452 return NETDEV_TX_BUSY;
cd28ab6a 1453
793b883e 1454 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1455 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1456 dev->name, sky2->tx_prod, skb->len);
1457
cd28ab6a
SH		 1458 len = skb_headlen(skb);
1459 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1460 addr64 = upper_32_bits(mapping);
793b883e 1461
a018e330 1462 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1463 if (addr64 != sky2->tx_addr64 ||
1464 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1465 le = get_tx_le(sky2);
f65b138c 1466 le->addr = cpu_to_le32(addr64);
793b883e 1467 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1468 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1469 }
cd28ab6a
SH		 1470
1471 /* Check for TCP Segmentation Offload */
7967168c 1472 mss = skb_shinfo(skb)->gso_size;
793b883e 1473 if (mss != 0) {
ea76e635
SH		 1474
1475 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1476 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1477
1478 if (mss != sky2->tx_last_mss) {
1479 le = get_tx_le(sky2);
1480 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1481
1482 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1483 le->opcode = OP_MSS | HW_OWNER;
1484 else
1485 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1486 sky2->tx_last_mss = mss;
1487 }
cd28ab6a
SH		 1488 }
1489
cd28ab6a 1490 ctrl = 0;
d1f13708
SH		 1491#ifdef SKY2_VLAN_TAG_USED
1492 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1493 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1494 if (!le) {
1495 le = get_tx_le(sky2);
f65b138c 1496 le->addr = 0;
d1f13708 1497 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1498 } else
1499 le->opcode |= OP_VLAN;
1500 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1501 ctrl |= INS_VLAN;
1502 }
1503#endif
1504
1505 /* Handle TCP checksum offload */
84fa7933 1506 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1507 /* On Yukon EX (some versions) encoding change. */
ea76e635 1508 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1509 ctrl |= CALSUM; /* auto checksum */
1510 else {
1511 const unsigned offset = skb_transport_offset(skb);
1512 u32 tcpsum;
1513
1514 tcpsum = offset << 16; /* sum start */
1515 tcpsum |= offset + skb->csum_offset; /* sum write */
1516
1517 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1518 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1519 ctrl |= UDPTCP;
1520
1521 if (tcpsum != sky2->tx_tcpsum) {
1522 sky2->tx_tcpsum = tcpsum;
1523
1524 le = get_tx_le(sky2);
1525 le->addr = cpu_to_le32(tcpsum);
1526 le->length = 0; /* initial checksum value */
1527 le->ctrl = 1; /* one packet */
1528 le->opcode = OP_TCPLISW | HW_OWNER;
1529 }
1d179332 1530 }
cd28ab6a
SH		 1531 }
1532
1533 le = get_tx_le(sky2);
f65b138c 1534 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1535 le->length = cpu_to_le16(len);
1536 le->ctrl = ctrl;
793b883e 1537 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1538
291ea614 1539 re = tx_le_re(sky2, le);
cd28ab6a 1540 re->skb = skb;
6cdbbdf3 1541 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1542 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1543
1544 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1545 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1546
1547 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1548 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1549 addr64 = upper_32_bits(mapping);
793b883e
SH		 1550 if (addr64 != sky2->tx_addr64) {
1551 le = get_tx_le(sky2);
f65b138c 1552 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1553 le->ctrl = 0;
1554 le->opcode = OP_ADDR64 | HW_OWNER;
1555 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1556 }
1557
1558 le = get_tx_le(sky2);
f65b138c 1559 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1560 le->length = cpu_to_le16(frag->size);
1561 le->ctrl = ctrl;
793b883e 1562 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1563
291ea614
SH		 1564 re = tx_le_re(sky2, le);
1565 re->skb = skb;
1566 pci_unmap_addr_set(re, mapaddr, mapping);
1567 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1568 }
6cdbbdf3 1569
cd28ab6a
SH		 1570 le->ctrl |= EOP;
1571
97bda706
SH		 1572 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1573 netif_stop_queue(dev);
b19666d9 1574
290d4de5 1575 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1576
cd28ab6a
SH		 1577 dev->trans_start = jiffies;
1578 return NETDEV_TX_OK;
1579}
1580
cd28ab6a 1581/*
793b883e
SH		 1582 * Free ring elements from starting at tx_cons until "done"
1583 *
1584 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1585 * buffers so make sure not to free skb to early.
cd28ab6a 1586 */
d11c13e7 1587static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1588{
d11c13e7 1589 struct net_device *dev = sky2->netdev;
af2a58ac 1590 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1591 unsigned idx;
cd28ab6a 1592
0e3ff6aa 1593 BUG_ON(done >= TX_RING_SIZE);
2224795d 1594
291ea614
SH		 1595 for (idx = sky2->tx_cons; idx != done;
1596 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1597 struct sky2_tx_le *le = sky2->tx_le + idx;
1598 struct tx_ring_info *re = sky2->tx_ring + idx;
1599
1600 switch(le->opcode & ~HW_OWNER) {
1601 case OP_LARGESEND:
1602 case OP_PACKET:
1603 pci_unmap_single(pdev,
1604 pci_unmap_addr(re, mapaddr),
1605 pci_unmap_len(re, maplen),
1606 PCI_DMA_TODEVICE);
af2a58ac 1607 break;
291ea614
SH		 1608 case OP_BUFFER:
1609 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1610 pci_unmap_len(re, maplen),
734d1868 1611 PCI_DMA_TODEVICE);
291ea614
SH		 1612 break;
1613 }
1614
1615 if (le->ctrl & EOP) {
1616 if (unlikely(netif_msg_tx_done(sky2)))
1617 printk(KERN_DEBUG "%s: tx done %u\n",
1618 dev->name, idx);
3cf26753 1619
2bf56fe2 1620 sky2->net_stats.tx_packets++;
1621 sky2->net_stats.tx_bytes += re->skb->len;
1622
794b2bd2 1623 dev_kfree_skb_any(re->skb);
3cf26753 1624 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1625 }
793b883e 1626 }
793b883e 1627
291ea614 1628 sky2->tx_cons = idx;
50432cb5
SH		 1629 smp_mb();
1630
22e11703 1631 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1632 netif_wake_queue(dev);
cd28ab6a
SH		 1633}
1634
1635/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1636static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1637{
2bb8c262
SH		 1638 struct sky2_port *sky2 = netdev_priv(dev);
1639
1640 netif_tx_lock_bh(dev);
d11c13e7 1641 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1642 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1643}
1644
1645/* Network shutdown */
1646static int sky2_down(struct net_device *dev)
1647{
1648 struct sky2_port *sky2 = netdev_priv(dev);
1649 struct sky2_hw *hw = sky2->hw;
1650 unsigned port = sky2->port;
1651 u16 ctrl;
e07b1aa8 1652 u32 imask;
cd28ab6a 1653
1b537565
SH		 1654 /* Never really got started! */
1655 if (!sky2->tx_le)
1656 return 0;
1657
cd28ab6a
SH		 1658 if (netif_msg_ifdown(sky2))
1659 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1660
018d1c66 1661 /* Stop more packets from being queued */
cd28ab6a
SH		 1662 netif_stop_queue(dev);
1663
ebc646f6
SH		 1664 /* Disable port IRQ */
1665 imask = sky2_read32(hw, B0_IMSK);
1666 imask &= ~portirq_msk[port];
1667 sky2_write32(hw, B0_IMSK, imask);
1668
d3bcfbeb 1669 sky2_gmac_reset(hw, port);
793b883e 1670
cd28ab6a
SH		 1671 /* Stop transmitter */
1672 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1673 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1674
1675 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1676 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1677
1678 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1679 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1680 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1681
1682 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1683
1684 /* Workaround shared GMAC reset */
793b883e
SH		 1685 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1686 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1687 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1688
1689 /* Disable Force Sync bit and Enable Alloc bit */
1690 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1691 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1692
1693 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1694 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1695 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1696
1697 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1698 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1699 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1700
1701 /* Reset the Tx prefetch units */
1702 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1703 PREF_UNIT_RST_SET);
1704
1705 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1706
6b1a3aef 1707 sky2_rx_stop(sky2);
cd28ab6a
SH		 1708
1709 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1710 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1711
d3bcfbeb
SH		 1712 sky2_phy_power(hw, port, 0);
1713
55d7b4e6
SH		 1714 netif_carrier_off(dev);
1715
d571b694 1716 /* turn off LED's */
cd28ab6a
SH		 1717 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1718
018d1c66
SH		 1719 synchronize_irq(hw->pdev->irq);
1720
2bb8c262 1721 sky2_tx_clean(dev);
cd28ab6a
SH		 1722 sky2_rx_clean(sky2);
1723
1724 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1725 sky2->rx_le, sky2->rx_le_map);
1726 kfree(sky2->rx_ring);
1727
1728 pci_free_consistent(hw->pdev,
1729 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1730 sky2->tx_le, sky2->tx_le_map);
1731 kfree(sky2->tx_ring);
1732
1b537565
SH		 1733 sky2->tx_le = NULL;
1734 sky2->rx_le = NULL;
1735
1736 sky2->rx_ring = NULL;
1737 sky2->tx_ring = NULL;
1738
cd28ab6a
SH		 1739 return 0;
1740}
1741
1742static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1743{
ea76e635 1744 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1745 return SPEED_1000;
1746
05745c4a
SH		 1747 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1748 if (aux & PHY_M_PS_SPEED_100)
1749 return SPEED_100;
1750 else
1751 return SPEED_10;
1752 }
cd28ab6a
SH		 1753
1754 switch (aux & PHY_M_PS_SPEED_MSK) {
1755 case PHY_M_PS_SPEED_1000:
1756 return SPEED_1000;
1757 case PHY_M_PS_SPEED_100:
1758 return SPEED_100;
1759 default:
1760 return SPEED_10;
1761 }
1762}
1763
1764static void sky2_link_up(struct sky2_port *sky2)
1765{
1766 struct sky2_hw *hw = sky2->hw;
1767 unsigned port = sky2->port;
1768 u16 reg;
16ad91e1
SH		 1769 static const char *fc_name[] = {
1770 [FC_NONE] = "none",
1771 [FC_TX] = "tx",
1772 [FC_RX] = "rx",
1773 [FC_BOTH] = "both",
1774 };
cd28ab6a 1775
cd28ab6a 1776 /* enable Rx/Tx */
2eaba1a2 1777 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1778 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1779 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1780
1781 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1782
1783 netif_carrier_on(sky2->netdev);
cd28ab6a 1784
75e80683 1785 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1786
cd28ab6a 1787 /* Turn on link LED */
793b883e 1788 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1789 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1790
ea76e635 1791 if (hw->flags & SKY2_HW_NEWER_PHY) {
793b883e 1792 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1793 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1794
1795 switch(sky2->speed) {
1796 case SPEED_10:
1797 led |= PHY_M_LEDC_INIT_CTRL(7);
1798 break;
1799
1800 case SPEED_100:
1801 led |= PHY_M_LEDC_STA1_CTRL(7);
1802 break;
1803
1804 case SPEED_1000:
1805 led |= PHY_M_LEDC_STA0_CTRL(7);
1806 break;
1807 }
793b883e
SH		 1808
1809 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1810 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1811 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1812 }
1813
cd28ab6a
SH		 1814 if (netif_msg_link(sky2))
1815 printk(KERN_INFO PFX
d571b694 1816 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1817 sky2->netdev->name, sky2->speed,
1818 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1819 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1820}
1821
1822static void sky2_link_down(struct sky2_port *sky2)
1823{
1824 struct sky2_hw *hw = sky2->hw;
1825 unsigned port = sky2->port;
1826 u16 reg;
1827
1828 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1829
1830 reg = gma_read16(hw, port, GM_GP_CTRL);
1831 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1832 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1833
cd28ab6a 1834 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1835
1836 /* Turn on link LED */
1837 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1838
1839 if (netif_msg_link(sky2))
1840 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1841
cd28ab6a
SH		 1842 sky2_phy_init(hw, port);
1843}
1844
16ad91e1
SH		 1845static enum flow_control sky2_flow(int rx, int tx)
1846{
1847 if (rx)
1848 return tx ? FC_BOTH : FC_RX;
1849 else
1850 return tx ? FC_TX : FC_NONE;
1851}
1852
793b883e
SH		 1853static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1854{
1855 struct sky2_hw *hw = sky2->hw;
1856 unsigned port = sky2->port;
da4c1ff4 1857 u16 advert, lpa;
793b883e 1858
da4c1ff4 1859 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1860 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1861 if (lpa & PHY_M_AN_RF) {
1862 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1863 return -1;
1864 }
1865
793b883e
SH		 1866 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1867 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1868 sky2->netdev->name);
1869 return -1;
1870 }
1871
793b883e 1872 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1873 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1874
da4c1ff4
SH		 1875 /* Since the pause result bits seem to in different positions on
1876 * different chips. look at registers.
1877 */
ea76e635 1878 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1879 /* Shift for bits in fiber PHY */
1880 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1881 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1882
1883 if (advert & ADVERTISE_1000XPAUSE)
1884 advert |= ADVERTISE_PAUSE_CAP;
1885 if (advert & ADVERTISE_1000XPSE_ASYM)
1886 advert |= ADVERTISE_PAUSE_ASYM;
1887 if (lpa & LPA_1000XPAUSE)
1888 lpa |= LPA_PAUSE_CAP;
1889 if (lpa & LPA_1000XPAUSE_ASYM)
1890 lpa |= LPA_PAUSE_ASYM;
1891 }
793b883e 1892
da4c1ff4
SH		 1893 sky2->flow_status = FC_NONE;
1894 if (advert & ADVERTISE_PAUSE_CAP) {
1895 if (lpa & LPA_PAUSE_CAP)
1896 sky2->flow_status = FC_BOTH;
1897 else if (advert & ADVERTISE_PAUSE_ASYM)
1898 sky2->flow_status = FC_RX;
1899 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1900 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1901 sky2->flow_status = FC_TX;
1902 }
793b883e 1903
16ad91e1 1904 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1905 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1906 sky2->flow_status = FC_NONE;
2eaba1a2 1907
da4c1ff4 1908 if (sky2->flow_status & FC_TX)
793b883e
SH		 1909 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1910 else
1911 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1912
1913 return 0;
1914}
cd28ab6a 1915
e07b1aa8
SH		 1916/* Interrupt from PHY */
1917static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1918{
e07b1aa8
SH		 1919 struct net_device *dev = hw->dev[port];
1920 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1921 u16 istatus, phystat;
1922
ebc646f6
SH		 1923 if (!netif_running(dev))
1924 return;
1925
e07b1aa8
SH		 1926 spin_lock(&sky2->phy_lock);
1927 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1928 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1929
cd28ab6a
SH		 1930 if (netif_msg_intr(sky2))
1931 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1932 sky2->netdev->name, istatus, phystat);
1933
2eaba1a2 1934 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1935 if (sky2_autoneg_done(sky2, phystat) == 0)
1936 sky2_link_up(sky2);
1937 goto out;
1938 }
cd28ab6a 1939
793b883e
SH		 1940 if (istatus & PHY_M_IS_LSP_CHANGE)
1941 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1942
793b883e
SH		 1943 if (istatus & PHY_M_IS_DUP_CHANGE)
1944 sky2->duplex =
1945 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1946
793b883e
SH		 1947 if (istatus & PHY_M_IS_LST_CHANGE) {
1948 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1949 sky2_link_up(sky2);
793b883e
SH		 1950 else
1951 sky2_link_down(sky2);
cd28ab6a 1952 }
793b883e 1953out:
e07b1aa8 1954 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1955}
1956
62335ab0 1957/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1958 * and tx queue is full (stopped).
1959 */
cd28ab6a
SH		 1960static void sky2_tx_timeout(struct net_device *dev)
1961{
1962 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1963 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1964
1965 if (netif_msg_timer(sky2))
1966 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1967
8f24664d 1968 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1969 dev->name, sky2->tx_cons, sky2->tx_prod,
1970 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1971 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1972
81906791
SH		 1973 /* can't restart safely under softirq */
1974 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1975}
1976
1977static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1978{
6b1a3aef
SH		 1979 struct sky2_port *sky2 = netdev_priv(dev);
1980 struct sky2_hw *hw = sky2->hw;
b628ed98 1981 unsigned port = sky2->port;
6b1a3aef
SH		 1982 int err;
1983 u16 ctl, mode;
e07b1aa8 1984 u32 imask;
cd28ab6a
SH		 1985
1986 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1987 return -EINVAL;
1988
05745c4a
SH		 1989 if (new_mtu > ETH_DATA_LEN &&
1990 (hw->chip_id == CHIP_ID_YUKON_FE ||
1991 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 1992 return -EINVAL;
1993
6b1a3aef
SH		 1994 if (!netif_running(dev)) {
1995 dev->mtu = new_mtu;
1996 return 0;
1997 }
1998
e07b1aa8 1999 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2000 sky2_write32(hw, B0_IMSK, 0);
2001
018d1c66
SH		 2002 dev->trans_start = jiffies; /* prevent tx timeout */
2003 netif_stop_queue(dev);
2004 netif_poll_disable(hw->dev[0]);
2005
e07b1aa8
SH		 2006 synchronize_irq(hw->pdev->irq);
2007
e0c28116 2008 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2009 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2010
2011 ctl = gma_read16(hw, port, GM_GP_CTRL);
2012 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2013 sky2_rx_stop(sky2);
2014 sky2_rx_clean(sky2);
cd28ab6a
SH		 2015
2016 dev->mtu = new_mtu;
14d0263f 2017
6b1a3aef
SH		 2018 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2019 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2020
2021 if (dev->mtu > ETH_DATA_LEN)
2022 mode |= GM_SMOD_JUMBO_ENA;
2023
b628ed98 2024 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2025
b628ed98 2026 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2027
6b1a3aef 2028 err = sky2_rx_start(sky2);
e07b1aa8 2029 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2030
1b537565
SH		 2031 if (err)
2032 dev_close(dev);
2033 else {
b628ed98 2034 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 2035
2036 netif_poll_enable(hw->dev[0]);
2037 netif_wake_queue(dev);
2038 }
2039
cd28ab6a
SH		 2040 return err;
2041}
2042
14d0263f
SH		 2043/* For small just reuse existing skb for next receive */
2044static struct sk_buff *receive_copy(struct sky2_port *sky2,
2045 const struct rx_ring_info *re,
2046 unsigned length)
2047{
2048 struct sk_buff *skb;
2049
2050 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2051 if (likely(skb)) {
2052 skb_reserve(skb, 2);
2053 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2054 length, PCI_DMA_FROMDEVICE);
d626f62b 2055 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2056 skb->ip_summed = re->skb->ip_summed;
2057 skb->csum = re->skb->csum;
2058 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2059 length, PCI_DMA_FROMDEVICE);
2060 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2061 skb_put(skb, length);
14d0263f
SH		 2062 }
2063 return skb;
2064}
2065
2066/* Adjust length of skb with fragments to match received data */
2067static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2068 unsigned int length)
2069{
2070 int i, num_frags;
2071 unsigned int size;
2072
2073 /* put header into skb */
2074 size = min(length, hdr_space);
2075 skb->tail += size;
2076 skb->len += size;
2077 length -= size;
2078
2079 num_frags = skb_shinfo(skb)->nr_frags;
2080 for (i = 0; i < num_frags; i++) {
2081 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2082
2083 if (length == 0) {
2084 /* don't need this page */
2085 __free_page(frag->page);
2086 --skb_shinfo(skb)->nr_frags;
2087 } else {
2088 size = min(length, (unsigned) PAGE_SIZE);
2089
2090 frag->size = size;
2091 skb->data_len += size;
2092 skb->truesize += size;
2093 skb->len += size;
2094 length -= size;
2095 }
2096 }
2097}
2098
2099/* Normal packet - take skb from ring element and put in a new one */
2100static struct sk_buff *receive_new(struct sky2_port *sky2,
2101 struct rx_ring_info *re,
2102 unsigned int length)
2103{
2104 struct sk_buff *skb, *nskb;
2105 unsigned hdr_space = sky2->rx_data_size;
2106
14d0263f
SH		 2107 /* Don't be tricky about reusing pages (yet) */
2108 nskb = sky2_rx_alloc(sky2);
2109 if (unlikely(!nskb))
2110 return NULL;
2111
2112 skb = re->skb;
2113 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2114
2115 prefetch(skb->data);
2116 re->skb = nskb;
2117 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2118
2119 if (skb_shinfo(skb)->nr_frags)
2120 skb_put_frags(skb, hdr_space, length);
2121 else
489b10c1 2122 skb_put(skb, length);
14d0263f
SH		 2123 return skb;
2124}
2125
cd28ab6a
SH		 2126/*
2127 * Receive one packet.
d571b694 2128 * For larger packets, get new buffer.
cd28ab6a 2129 */
497d7c86 2130static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2131 u16 length, u32 status)
2132{
497d7c86 2133 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2134 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2135 struct sk_buff *skb = NULL;
d6532232
SH		 2136 u16 count = (status & GMR_FS_LEN) >> 16;
2137
2138#ifdef SKY2_VLAN_TAG_USED
2139 /* Account for vlan tag */
2140 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2141 count -= VLAN_HLEN;
2142#endif
cd28ab6a
SH		 2143
2144 if (unlikely(netif_msg_rx_status(sky2)))
2145 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2146 dev->name, sky2->rx_next, status, length);
cd28ab6a 2147
793b883e 2148 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2149 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2150
3b12e014
SH		 2151 if (length < ETH_ZLEN || length > sky2->rx_data_size)
2152 goto len_error;
2153
2154 /* This chip has hardware problems that generates bogus status.
2155 * So do only marginal checking and expect higher level protocols
2156 * to handle crap frames.
2157 */
2158 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2159 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2160 length != count)
2161 goto okay;
2162
42eeea01 2163 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2164 goto error;
2165
42eeea01
SH		 2166 if (!(status & GMR_FS_RX_OK))
2167 goto resubmit;
2168
d6532232
SH		 2169 /* if length reported by DMA does not match PHY, packet was truncated */
2170 if (length != count)
3b12e014 2171 goto len_error;
71749531 2172
3b12e014 2173okay:
14d0263f
SH		 2174 if (length < copybreak)
2175 skb = receive_copy(sky2, re, length);
2176 else
2177 skb = receive_new(sky2, re, length);
793b883e 2178resubmit:
14d0263f 2179 sky2_rx_submit(sky2, re);
79e57d32 2180
cd28ab6a
SH		 2181 return skb;
2182
3b12e014 2183len_error:
71749531
SH		 2184 /* Truncation of overlength packets
2185 causes PHY length to not match MAC length */
2186 ++sky2->net_stats.rx_length_errors;
d6532232 2187 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2188 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2189 dev->name, status, length);
d6532232 2190 goto resubmit;
71749531 2191
cd28ab6a 2192error:
6e15b712 2193 ++sky2->net_stats.rx_errors;
b6d77734 2194 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2195 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2196 goto resubmit;
2197 }
6e15b712 2198
3be92a70 2199 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2200 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2201 dev->name, status, length);
793b883e
SH		 2202
2203 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2204 sky2->net_stats.rx_length_errors++;
2205 if (status & GMR_FS_FRAGMENT)
2206 sky2->net_stats.rx_frame_errors++;
2207 if (status & GMR_FS_CRC_ERR)
2208 sky2->net_stats.rx_crc_errors++;
79e57d32 2209
793b883e 2210 goto resubmit;
cd28ab6a
SH		 2211}
2212
e07b1aa8
SH		 2213/* Transmit complete */
2214static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2215{
e07b1aa8 2216 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2217
e07b1aa8 2218 if (netif_running(dev)) {
2bb8c262 2219 netif_tx_lock(dev);
e07b1aa8 2220 sky2_tx_complete(sky2, last);
2bb8c262 2221 netif_tx_unlock(dev);
2224795d 2222 }
cd28ab6a
SH		 2223}
2224
e07b1aa8
SH		 2225/* Process status response ring */
2226static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2227{
e07b1aa8 2228 int work_done = 0;
55c9dd35 2229 unsigned rx[2] = { 0, 0 };
e71ebd73 2230 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2231
af2a58ac 2232 rmb();
bea86103 2233
e71ebd73 2234 while (hw->st_idx != hwidx) {
55c9dd35 2235 struct sky2_port *sky2;
13210ce5 2236 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2237 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2238 struct net_device *dev;
cd28ab6a 2239 struct sk_buff *skb;
cd28ab6a
SH		 2240 u32 status;
2241 u16 length;
2242
cb5d9547 2243 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2244
69161611 2245 dev = hw->dev[port];
13210ce5 2246 sky2 = netdev_priv(dev);
f65b138c
SH		 2247 length = le16_to_cpu(le->length);
2248 status = le32_to_cpu(le->status);
cd28ab6a 2249
e71ebd73 2250 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2251 case OP_RXSTAT:
55c9dd35 2252 ++rx[port];
497d7c86 2253 skb = sky2_receive(dev, length, status);
3225b919
SH		 2254 if (unlikely(!skb)) {
2255 sky2->net_stats.rx_dropped++;
55c9dd35 2256 break;
3225b919 2257 }
13210ce5 2258
69161611 2259 /* This chip reports checksum status differently */
05745c4a 2260 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2261 if (sky2->rx_csum &&
2262 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2263 (le->css & CSS_TCPUDPCSOK))
2264 skb->ip_summed = CHECKSUM_UNNECESSARY;
2265 else
2266 skb->ip_summed = CHECKSUM_NONE;
2267 }
2268
13210ce5 2269 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2270 sky2->net_stats.rx_packets++;
2271 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2272 dev->last_rx = jiffies;
2273
d1f13708
SH		 2274#ifdef SKY2_VLAN_TAG_USED
2275 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2276 vlan_hwaccel_receive_skb(skb,
2277 sky2->vlgrp,
2278 be16_to_cpu(sky2->rx_tag));
2279 } else
2280#endif
cd28ab6a 2281 netif_receive_skb(skb);
13210ce5 2282
22e11703 2283 /* Stop after net poll weight */
13210ce5
SH		 2284 if (++work_done >= to_do)
2285 goto exit_loop;
cd28ab6a
SH		 2286 break;
2287
d1f13708
SH		 2288#ifdef SKY2_VLAN_TAG_USED
2289 case OP_RXVLAN:
2290 sky2->rx_tag = length;
2291 break;
2292
2293 case OP_RXCHKSVLAN:
2294 sky2->rx_tag = length;
2295 /* fall through */
2296#endif
cd28ab6a 2297 case OP_RXCHKS:
87418307
SH		 2298 if (!sky2->rx_csum)
2299 break;
2300
05745c4a
SH		 2301 /* If this happens then driver assuming wrong format */
2302 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2303 if (net_ratelimit())
2304 printk(KERN_NOTICE "%s: unexpected"
2305 " checksum status\n",
2306 dev->name);
69161611 2307 break;
05745c4a 2308 }
69161611 2309
87418307
SH		 2310 /* Both checksum counters are programmed to start at
2311 * the same offset, so unless there is a problem they
2312 * should match. This failure is an early indication that
2313 * hardware receive checksumming won't work.
2314 */
2315 if (likely(status >> 16 == (status & 0xffff))) {
2316 skb = sky2->rx_ring[sky2->rx_next].skb;
2317 skb->ip_summed = CHECKSUM_COMPLETE;
2318 skb->csum = status & 0xffff;
2319 } else {
2320 printk(KERN_NOTICE PFX "%s: hardware receive "
2321 "checksum problem (status = %#x)\n",
2322 dev->name, status);
2323 sky2->rx_csum = 0;
2324 sky2_write32(sky2->hw,
69161611 2325 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2326 BMU_DIS_RX_CHKSUM);
2327 }
cd28ab6a
SH		 2328 break;
2329
2330 case OP_TXINDEXLE:
13b97b74 2331 /* TX index reports status for both ports */
f55925d7
SH		 2332 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2333 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2334 if (hw->dev[1])
2335 sky2_tx_done(hw->dev[1],
2336 ((status >> 24) & 0xff)
2337 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2338 break;
2339
cd28ab6a
SH		 2340 default:
2341 if (net_ratelimit())
793b883e 2342 printk(KERN_WARNING PFX
e71ebd73 2343 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2344 }
13210ce5 2345 }
cd28ab6a 2346
fe2a24df
SH		 2347 /* Fully processed status ring so clear irq */
2348 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2349
13210ce5 2350exit_loop:
55c9dd35
SH		 2351 if (rx[0])
2352 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2353
55c9dd35
SH		 2354 if (rx[1])
2355 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2356
e07b1aa8 2357 return work_done;
cd28ab6a
SH		 2358}
2359
2360static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2361{
2362 struct net_device *dev = hw->dev[port];
2363
3be92a70
SH		 2364 if (net_ratelimit())
2365 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2366 dev->name, status);
cd28ab6a
SH		 2367
2368 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2369 if (net_ratelimit())
2370 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2371 dev->name);
cd28ab6a
SH		 2372 /* Clear IRQ */
2373 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2374 }
2375
2376 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2377 if (net_ratelimit())
2378 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2379 dev->name);
cd28ab6a
SH		 2380
2381 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2382 }
2383
2384 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2385 if (net_ratelimit())
2386 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2387 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2388 }
2389
2390 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2391 if (net_ratelimit())
2392 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2393 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2394 }
2395
2396 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2397 if (net_ratelimit())
2398 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2399 dev->name);
cd28ab6a
SH		 2400 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2401 }
2402}
2403
2404static void sky2_hw_intr(struct sky2_hw *hw)
2405{
2406 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2407
793b883e 2408 if (status & Y2_IS_TIST_OV)
cd28ab6a 2409 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2410
2411 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2412 u16 pci_err;
2413
56a645cc 2414 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2415 if (net_ratelimit())
b02a9258
SH		 2416 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2417 pci_err);
cd28ab6a
SH		 2418
2419 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2420 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2421 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2422 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2423 }
2424
2425 if (status & Y2_IS_PCI_EXP) {
d571b694 2426 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2427 u32 pex_err;
2428
7bd656d1 2429 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2430
3be92a70 2431 if (net_ratelimit())
b02a9258
SH		 2432 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2433 pex_err);
cd28ab6a
SH		 2434
2435 /* clear the interrupt */
2436 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2437 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2438 0xffffffffUL);
cd28ab6a
SH		 2439 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2440
7bd656d1 2441 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2442 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2443 hwmsk &= ~Y2_IS_PCI_EXP;
2444 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2445 }
2446 }
2447
2448 if (status & Y2_HWE_L1_MASK)
2449 sky2_hw_error(hw, 0, status);
2450 status >>= 8;
2451 if (status & Y2_HWE_L1_MASK)
2452 sky2_hw_error(hw, 1, status);
2453}
2454
2455static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2456{
2457 struct net_device *dev = hw->dev[port];
2458 struct sky2_port *sky2 = netdev_priv(dev);
2459 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2460
2461 if (netif_msg_intr(sky2))
2462 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2463 dev->name, status);
2464
a3caeada
SH		 2465 if (status & GM_IS_RX_CO_OV)
2466 gma_read16(hw, port, GM_RX_IRQ_SRC);
2467
2468 if (status & GM_IS_TX_CO_OV)
2469 gma_read16(hw, port, GM_TX_IRQ_SRC);
2470
cd28ab6a
SH		 2471 if (status & GM_IS_RX_FF_OR) {
2472 ++sky2->net_stats.rx_fifo_errors;
2473 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2474 }
2475
2476 if (status & GM_IS_TX_FF_UR) {
2477 ++sky2->net_stats.tx_fifo_errors;
2478 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2479 }
cd28ab6a
SH		 2480}
2481
40b01727
SH		 2482/* This should never happen it is a bug. */
2483static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2484 u16 q, unsigned ring_size)
d257924e
SH		 2485{
2486 struct net_device *dev = hw->dev[port];
2487 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2488 unsigned idx;
2489 const u64 *le = (q == Q_R1 || q == Q_R2)
2490 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2491
40b01727
SH		 2492 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2493 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2494 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2495 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2496
40b01727 2497 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2498}
cd28ab6a 2499
75e80683
SH		 2500static int sky2_rx_hung(struct net_device *dev)
2501{
2502 struct sky2_port *sky2 = netdev_priv(dev);
2503 struct sky2_hw *hw = sky2->hw;
2504 unsigned port = sky2->port;
2505 unsigned rxq = rxqaddr[port];
2506 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2507 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2508 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2509 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2510
2511 /* If idle and MAC or PCI is stuck */
2512 if (sky2->check.last == dev->last_rx &&
2513 ((mac_rp == sky2->check.mac_rp &&
2514 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2515 /* Check if the PCI RX hang */
2516 (fifo_rp == sky2->check.fifo_rp &&
2517 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2518 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2519 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2520 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2521 return 1;
2522 } else {
2523 sky2->check.last = dev->last_rx;
2524 sky2->check.mac_rp = mac_rp;
2525 sky2->check.mac_lev = mac_lev;
2526 sky2->check.fifo_rp = fifo_rp;
2527 sky2->check.fifo_lev = fifo_lev;
2528 return 0;
2529 }
2530}
2531
32c2c300 2532static void sky2_watchdog(unsigned long arg)
d27ed387 2533{
01bd7564 2534 struct sky2_hw *hw = (struct sky2_hw *) arg;
75e80683 2535 struct net_device *dev;
d27ed387 2536
75e80683 2537 /* Check for lost IRQ once a second */
32c2c300 2538 if (sky2_read32(hw, B0_ISRC)) {
75e80683 2539 dev = hw->dev[0];
32c2c300
SH		 2540 if (__netif_rx_schedule_prep(dev))
2541 __netif_rx_schedule(dev);
75e80683
SH		 2542 } else {
2543 int i, active = 0;
2544
2545 for (i = 0; i < hw->ports; i++) {
2546 dev = hw->dev[i];
2547 if (!netif_running(dev))
2548 continue;
2549 ++active;
2550
2551 /* For chips with Rx FIFO, check if stuck */
e0c28116 2552 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2553 sky2_rx_hung(dev)) {
2554 pr_info(PFX "%s: receiver hang detected\n",
2555 dev->name);
2556 schedule_work(&hw->restart_work);
2557 return;
2558 }
2559 }
2560
2561 if (active == 0)
2562 return;
32c2c300 2563 }
01bd7564 2564
75e80683 2565 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2566}
2567
40b01727
SH		 2568/* Hardware/software error handling */
2569static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2570{
40b01727
SH		 2571 if (net_ratelimit())
2572 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2573
1e5f1283
SH		 2574 if (status & Y2_IS_HW_ERR)
2575 sky2_hw_intr(hw);
d257924e 2576
1e5f1283
SH		 2577 if (status & Y2_IS_IRQ_MAC1)
2578 sky2_mac_intr(hw, 0);
cd28ab6a 2579
1e5f1283
SH		 2580 if (status & Y2_IS_IRQ_MAC2)
2581 sky2_mac_intr(hw, 1);
cd28ab6a 2582
1e5f1283 2583 if (status & Y2_IS_CHK_RX1)
40b01727 2584 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2585
1e5f1283 2586 if (status & Y2_IS_CHK_RX2)
40b01727 2587 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2588
1e5f1283 2589 if (status & Y2_IS_CHK_TXA1)
40b01727 2590 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2591
1e5f1283 2592 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2593 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2594}
2595
2596static int sky2_poll(struct net_device *dev0, int *budget)
2597{
2598 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2599 int work_done;
40b01727
SH		 2600 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2601
2602 if (unlikely(status & Y2_IS_ERROR))
2603 sky2_err_intr(hw, status);
2604
2605 if (status & Y2_IS_IRQ_PHY1)
2606 sky2_phy_intr(hw, 0);
2607
2608 if (status & Y2_IS_IRQ_PHY2)
2609 sky2_phy_intr(hw, 1);
cd28ab6a 2610
5c11ce70
SH		 2611 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2612 *budget -= work_done;
2613 dev0->quota -= work_done;
86fba634 2614
5c11ce70
SH		 2615 /* More work? */
2616 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2617 return 1;
5c11ce70
SH		 2618
2619 /* Bug/Errata workaround?
2620 * Need to kick the TX irq moderation timer.
2621 */
2622 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2623 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2624 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2625 }
5c11ce70
SH		 2626 netif_rx_complete(dev0);
2627
2628 sky2_read32(hw, B0_Y2_SP_LISR);
2629 return 0;
e07b1aa8
SH		 2630}
2631
7d12e780 2632static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2633{
2634 struct sky2_hw *hw = dev_id;
2635 struct net_device *dev0 = hw->dev[0];
2636 u32 status;
2637
2638 /* Reading this mask interrupts as side effect */
2639 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2640 if (status == 0 || status == ~0)
2641 return IRQ_NONE;
793b883e 2642
e07b1aa8
SH		 2643 prefetch(&hw->st_le[hw->st_idx]);
2644 if (likely(__netif_rx_schedule_prep(dev0)))
2645 __netif_rx_schedule(dev0);
793b883e 2646
cd28ab6a
SH		 2647 return IRQ_HANDLED;
2648}
2649
2650#ifdef CONFIG_NET_POLL_CONTROLLER
2651static void sky2_netpoll(struct net_device *dev)
2652{
2653 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2654 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2655
88d11360
SH		 2656 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2657 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2658}
2659#endif
2660
2661/* Chip internal frequency for clock calculations */
05745c4a 2662static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2663{
793b883e 2664 switch (hw->chip_id) {
cd28ab6a 2665 case CHIP_ID_YUKON_EC:
5a5b1ea0 2666 case CHIP_ID_YUKON_EC_U:
93745494 2667 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2668 return 125;
2669
cd28ab6a 2670 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2671 return 100;
2672
2673 case CHIP_ID_YUKON_FE_P:
2674 return 50;
2675
2676 case CHIP_ID_YUKON_XL:
2677 return 156;
2678
2679 default:
2680 BUG();
cd28ab6a
SH		 2681 }
2682}
2683
fb17358f 2684static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2685{
fb17358f 2686 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2687}
2688
fb17358f 2689static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2690{
fb17358f 2691 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2692}
2693
fb17358f 2694
e3173832 2695static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2696{
b89165f2 2697 u8 t8;
cd28ab6a 2698
451af335
SH		 2699 /* Enable all clocks */
2700 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2701
cd28ab6a 2702 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2703
cd28ab6a 2704 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2705 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2706
2707 switch(hw->chip_id) {
2708 case CHIP_ID_YUKON_XL:
2709 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2710 | SKY2_HW_NEWER_PHY;
2711 if (hw->chip_rev < 3)
2712 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2713
ea76e635
SH		 2714 break;
2715
2716 case CHIP_ID_YUKON_EC_U:
2717 hw->flags = SKY2_HW_GIGABIT
2718 | SKY2_HW_NEWER_PHY
2719 | SKY2_HW_ADV_POWER_CTL;
2720 break;
2721
2722 case CHIP_ID_YUKON_EX:
2723 hw->flags = SKY2_HW_GIGABIT
2724 | SKY2_HW_NEWER_PHY
2725 | SKY2_HW_NEW_LE
2726 | SKY2_HW_ADV_POWER_CTL;
2727
2728 /* New transmit checksum */
2729 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2730 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2731 break;
2732
2733 case CHIP_ID_YUKON_EC:
2734 /* This rev is really old, and requires untested workarounds */
2735 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2736 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2737 return -EOPNOTSUPP;
2738 }
e0c28116 2739 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2740 break;
2741
2742 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2743 break;
2744
05745c4a
SH		 2745 case CHIP_ID_YUKON_FE_P:
2746 hw->flags = SKY2_HW_NEWER_PHY
2747 | SKY2_HW_NEW_LE
2748 | SKY2_HW_AUTO_TX_SUM
2749 | SKY2_HW_ADV_POWER_CTL;
2750 break;
ea76e635 2751 default:
b02a9258
SH		 2752 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2753 hw->chip_id);
cd28ab6a
SH		 2754 return -EOPNOTSUPP;
2755 }
2756
ea76e635
SH		 2757 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2758 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2759 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2760
290d4de5 2761
e3173832
SH		 2762 hw->ports = 1;
2763 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2764 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2765 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2766 ++hw->ports;
2767 }
2768
2769 return 0;
2770}
2771
2772static void sky2_reset(struct sky2_hw *hw)
2773{
2774 u16 status;
2775 int i;
2776
cd28ab6a 2777 /* disable ASF */
4f44d8ba
SH		 2778 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2779 status = sky2_read16(hw, HCU_CCSR);
2780 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2781 HCU_CCSR_UC_STATE_MSK);
2782 sky2_write16(hw, HCU_CCSR, status);
2783 } else
2784 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2785 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2786
2787 /* do a SW reset */
2788 sky2_write8(hw, B0_CTST, CS_RST_SET);
2789 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2790
2791 /* clear PCI errors, if any */
56a645cc 2792 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2793
cd28ab6a 2794 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2795 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2796
cd28ab6a
SH		 2797
2798 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2799
2800 /* clear any PEX errors */
7bd656d1
SH		 2801 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2802 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2803
cd28ab6a 2804
ae306cca 2805 sky2_power_on(hw);
cd28ab6a
SH		 2806
2807 for (i = 0; i < hw->ports; i++) {
2808 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2809 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2810
2811 if (hw->chip_id == CHIP_ID_YUKON_EX)
2812 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2813 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2814 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2815 }
2816
2817 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2818
793b883e
SH		 2819 /* Clear I2C IRQ noise */
2820 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2821
2822 /* turn off hardware timer (unused) */
2823 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2824 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2825
cd28ab6a
SH		 2826 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2827
69634ee7
SH		 2828 /* Turn off descriptor polling */
2829 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2830
2831 /* Turn off receive timestamp */
2832 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2833 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2834
2835 /* enable the Tx Arbiters */
2836 for (i = 0; i < hw->ports; i++)
2837 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2838
2839 /* Initialize ram interface */
2840 for (i = 0; i < hw->ports; i++) {
793b883e 2841 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2842
2843 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2844 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2845 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2846 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2847 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2848 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2849 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2850 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2851 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2852 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2855 }
2856
7bd656d1 2857 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2858
cd28ab6a 2859 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2860 sky2_gmac_reset(hw, i);
cd28ab6a 2861
cd28ab6a
SH		 2862 memset(hw->st_le, 0, STATUS_LE_BYTES);
2863 hw->st_idx = 0;
2864
2865 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2866 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2867
2868 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2869 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2870
2871 /* Set the list last index */
793b883e 2872 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2873
290d4de5
SH		 2874 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2875 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2876
290d4de5
SH		 2877 /* set Status-FIFO ISR watermark */
2878 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2879 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2880 else
2881 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2882
290d4de5 2883 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2884 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2885 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2886
793b883e 2887 /* enable status unit */
cd28ab6a
SH		 2888 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2889
2890 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2891 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2892 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2893}
2894
81906791
SH		 2895static void sky2_restart(struct work_struct *work)
2896{
2897 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2898 struct net_device *dev;
2899 int i, err;
2900
81906791
SH		 2901 rtnl_lock();
2902 sky2_write32(hw, B0_IMSK, 0);
2903 sky2_read32(hw, B0_IMSK);
2904
2905 netif_poll_disable(hw->dev[0]);
2906
2907 for (i = 0; i < hw->ports; i++) {
2908 dev = hw->dev[i];
2909 if (netif_running(dev))
2910 sky2_down(dev);
2911 }
2912
2913 sky2_reset(hw);
2914 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2915 netif_poll_enable(hw->dev[0]);
2916
2917 for (i = 0; i < hw->ports; i++) {
2918 dev = hw->dev[i];
2919 if (netif_running(dev)) {
2920 err = sky2_up(dev);
2921 if (err) {
2922 printk(KERN_INFO PFX "%s: could not restart %d\n",
2923 dev->name, err);
2924 dev_close(dev);
2925 }
2926 }
2927 }
2928
81906791
SH		 2929 rtnl_unlock();
2930}
2931
e3173832
SH		 2932static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2933{
2934 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2935}
2936
2937static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2938{
2939 const struct sky2_port *sky2 = netdev_priv(dev);
2940
2941 wol->supported = sky2_wol_supported(sky2->hw);
2942 wol->wolopts = sky2->wol;
2943}
2944
2945static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2946{
2947 struct sky2_port *sky2 = netdev_priv(dev);
2948 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2949
e3173832
SH		 2950 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2951 return -EOPNOTSUPP;
2952
2953 sky2->wol = wol->wolopts;
2954
05745c4a
SH		 2955 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2956 hw->chip_id == CHIP_ID_YUKON_EX ||
2957 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2958 sky2_write32(hw, B0_CTST, sky2->wol
2959 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2960
2961 if (!netif_running(dev))
2962 sky2_wol_init(sky2);
cd28ab6a
SH		 2963 return 0;
2964}
2965
28bd181a 2966static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2967{
b89165f2
SH		 2968 if (sky2_is_copper(hw)) {
2969 u32 modes = SUPPORTED_10baseT_Half
2970 | SUPPORTED_10baseT_Full
2971 | SUPPORTED_100baseT_Half
2972 | SUPPORTED_100baseT_Full
2973 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2974
ea76e635 2975 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2976 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2977 | SUPPORTED_1000baseT_Full;
2978 return modes;
cd28ab6a 2979 } else
b89165f2
SH		 2980 return SUPPORTED_1000baseT_Half
2981 | SUPPORTED_1000baseT_Full
2982 | SUPPORTED_Autoneg
2983 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2984}
2985
793b883e 2986static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2987{
2988 struct sky2_port *sky2 = netdev_priv(dev);
2989 struct sky2_hw *hw = sky2->hw;
2990
2991 ecmd->transceiver = XCVR_INTERNAL;
2992 ecmd->supported = sky2_supported_modes(hw);
2993 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2994 if (sky2_is_copper(hw)) {
cd28ab6a 2995 ecmd->port = PORT_TP;
b89165f2
SH		 2996 ecmd->speed = sky2->speed;
2997 } else {
2998 ecmd->speed = SPEED_1000;
cd28ab6a 2999 ecmd->port = PORT_FIBRE;
b89165f2 3000 }
cd28ab6a
SH		 3001
3002 ecmd->advertising = sky2->advertising;
3003 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3004 ecmd->duplex = sky2->duplex;
3005 return 0;
3006}
3007
3008static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3009{
3010 struct sky2_port *sky2 = netdev_priv(dev);
3011 const struct sky2_hw *hw = sky2->hw;
3012 u32 supported = sky2_supported_modes(hw);
3013
3014 if (ecmd->autoneg == AUTONEG_ENABLE) {
3015 ecmd->advertising = supported;
3016 sky2->duplex = -1;
3017 sky2->speed = -1;
3018 } else {
3019 u32 setting;
3020
793b883e 3021 switch (ecmd->speed) {
cd28ab6a
SH		 3022 case SPEED_1000:
3023 if (ecmd->duplex == DUPLEX_FULL)
3024 setting = SUPPORTED_1000baseT_Full;
3025 else if (ecmd->duplex == DUPLEX_HALF)
3026 setting = SUPPORTED_1000baseT_Half;
3027 else
3028 return -EINVAL;
3029 break;
3030 case SPEED_100:
3031 if (ecmd->duplex == DUPLEX_FULL)
3032 setting = SUPPORTED_100baseT_Full;
3033 else if (ecmd->duplex == DUPLEX_HALF)
3034 setting = SUPPORTED_100baseT_Half;
3035 else
3036 return -EINVAL;
3037 break;
3038
3039 case SPEED_10:
3040 if (ecmd->duplex == DUPLEX_FULL)
3041 setting = SUPPORTED_10baseT_Full;
3042 else if (ecmd->duplex == DUPLEX_HALF)
3043 setting = SUPPORTED_10baseT_Half;
3044 else
3045 return -EINVAL;
3046 break;
3047 default:
3048 return -EINVAL;
3049 }
3050
3051 if ((setting & supported) == 0)
3052 return -EINVAL;
3053
3054 sky2->speed = ecmd->speed;
3055 sky2->duplex = ecmd->duplex;
3056 }
3057
3058 sky2->autoneg = ecmd->autoneg;
3059 sky2->advertising = ecmd->advertising;
3060
d1b139c0 3061 if (netif_running(dev)) {
1b537565 3062 sky2_phy_reinit(sky2);
d1b139c0
SH		 3063 sky2_set_multicast(dev);
3064 }
cd28ab6a
SH		 3065
3066 return 0;
3067}
3068
3069static void sky2_get_drvinfo(struct net_device *dev,
3070 struct ethtool_drvinfo *info)
3071{
3072 struct sky2_port *sky2 = netdev_priv(dev);
3073
3074 strcpy(info->driver, DRV_NAME);
3075 strcpy(info->version, DRV_VERSION);
3076 strcpy(info->fw_version, "N/A");
3077 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3078}
3079
3080static const struct sky2_stat {
793b883e
SH		 3081 char name[ETH_GSTRING_LEN];
3082 u16 offset;
cd28ab6a
SH		 3083} sky2_stats[] = {
3084 { "tx_bytes", GM_TXO_OK_HI },
3085 { "rx_bytes", GM_RXO_OK_HI },
3086 { "tx_broadcast", GM_TXF_BC_OK },
3087 { "rx_broadcast", GM_RXF_BC_OK },
3088 { "tx_multicast", GM_TXF_MC_OK },
3089 { "rx_multicast", GM_RXF_MC_OK },
3090 { "tx_unicast", GM_TXF_UC_OK },
3091 { "rx_unicast", GM_RXF_UC_OK },
3092 { "tx_mac_pause", GM_TXF_MPAUSE },
3093 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3094 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3095 { "late_collision",GM_TXF_LAT_COL },
3096 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3097 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3098 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3099
d2604540 3100 { "rx_short", GM_RXF_SHT },
cd28ab6a 3101 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3102 { "rx_64_byte_packets", GM_RXF_64B },
3103 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3104 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3105 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3106 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3107 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3108 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3109 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3110 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3111 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3112 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3113
3114 { "tx_64_byte_packets", GM_TXF_64B },
3115 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3116 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3117 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3118 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3119 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3120 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3121 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3122};
3123
cd28ab6a
SH		 3124static u32 sky2_get_rx_csum(struct net_device *dev)
3125{
3126 struct sky2_port *sky2 = netdev_priv(dev);
3127
3128 return sky2->rx_csum;
3129}
3130
3131static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3132{
3133 struct sky2_port *sky2 = netdev_priv(dev);
3134
3135 sky2->rx_csum = data;
793b883e 3136
cd28ab6a
SH		 3137 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3138 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3139
3140 return 0;
3141}
3142
3143static u32 sky2_get_msglevel(struct net_device *netdev)
3144{
3145 struct sky2_port *sky2 = netdev_priv(netdev);
3146 return sky2->msg_enable;
3147}
3148
9a7ae0a9
SH		 3149static int sky2_nway_reset(struct net_device *dev)
3150{
3151 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3152
16ad91e1 3153 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3154 return -EINVAL;
3155
1b537565 3156 sky2_phy_reinit(sky2);
d1b139c0 3157 sky2_set_multicast(dev);
9a7ae0a9
SH		 3158
3159 return 0;
3160}
3161
793b883e 3162static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3163{
3164 struct sky2_hw *hw = sky2->hw;
3165 unsigned port = sky2->port;
3166 int i;
3167
3168 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3169 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3170 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3171 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3172
793b883e 3173 for (i = 2; i < count; i++)
cd28ab6a
SH		 3174 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3175}
3176
cd28ab6a
SH		 3177static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3178{
3179 struct sky2_port *sky2 = netdev_priv(netdev);
3180 sky2->msg_enable = value;
3181}
3182
3183static int sky2_get_stats_count(struct net_device *dev)
3184{
3185 return ARRAY_SIZE(sky2_stats);
3186}
3187
3188static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3189 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3190{
3191 struct sky2_port *sky2 = netdev_priv(dev);
3192
793b883e 3193 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3194}
3195
793b883e 3196static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3197{
3198 int i;
3199
3200 switch (stringset) {
3201 case ETH_SS_STATS:
3202 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3203 memcpy(data + i * ETH_GSTRING_LEN,
3204 sky2_stats[i].name, ETH_GSTRING_LEN);
3205 break;
3206 }
3207}
3208
cd28ab6a
SH		 3209static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3210{
3211 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3212 return &sky2->net_stats;
3213}
3214
3215static int sky2_set_mac_address(struct net_device *dev, void *p)
3216{
3217 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3218 struct sky2_hw *hw = sky2->hw;
3219 unsigned port = sky2->port;
3220 const struct sockaddr *addr = p;
cd28ab6a
SH		 3221
3222 if (!is_valid_ether_addr(addr->sa_data))
3223 return -EADDRNOTAVAIL;
3224
cd28ab6a 3225 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3226 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3227 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3228 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3229 dev->dev_addr, ETH_ALEN);
1b537565 3230
a8ab1ec0
SH		 3231 /* virtual address for data */
3232 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3233
3234 /* physical address: used for pause frames */
3235 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3236
3237 return 0;
cd28ab6a
SH		 3238}
3239
a052b52f
SH		 3240static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3241{
3242 u32 bit;
3243
3244 bit = ether_crc(ETH_ALEN, addr) & 63;
3245 filter[bit >> 3] |= 1 << (bit & 7);
3246}
3247
cd28ab6a
SH		 3248static void sky2_set_multicast(struct net_device *dev)
3249{
3250 struct sky2_port *sky2 = netdev_priv(dev);
3251 struct sky2_hw *hw = sky2->hw;
3252 unsigned port = sky2->port;
3253 struct dev_mc_list *list = dev->mc_list;
3254 u16 reg;
3255 u8 filter[8];
a052b52f
SH		 3256 int rx_pause;
3257 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3258
a052b52f 3259 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3260 memset(filter, 0, sizeof(filter));
3261
3262 reg = gma_read16(hw, port, GM_RX_CTRL);
3263 reg |= GM_RXCR_UCF_ENA;
3264
d571b694 3265 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3266 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3267 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3268 memset(filter, 0xff, sizeof(filter));
a052b52f 3269 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3270 reg &= ~GM_RXCR_MCF_ENA;
3271 else {
3272 int i;
3273 reg |= GM_RXCR_MCF_ENA;
3274
a052b52f
SH		 3275 if (rx_pause)
3276 sky2_add_filter(filter, pause_mc_addr);
3277
3278 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3279 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3280 }
3281
cd28ab6a 3282 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3283 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3284 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3285 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3286 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3287 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3288 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3289 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3290
3291 gma_write16(hw, port, GM_RX_CTRL, reg);
3292}
3293
3294/* Can have one global because blinking is controlled by
3295 * ethtool and that is always under RTNL mutex
3296 */
91c86df5 3297static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3298{
793b883e
SH		 3299 u16 pg;
3300
793b883e
SH		 3301 switch (hw->chip_id) {
3302 case CHIP_ID_YUKON_XL:
3303 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3304 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3305 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3306 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3307 PHY_M_LEDC_INIT_CTRL(7) |
3308 PHY_M_LEDC_STA1_CTRL(7) |
3309 PHY_M_LEDC_STA0_CTRL(7))
3310 : 0);
3311
3312 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3313 break;
3314
3315 default:
3316 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3317 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3318 on ? PHY_M_LED_ALL : 0);
793b883e 3319 }
cd28ab6a
SH		 3320}
3321
3322/* blink LED's for finding board */
3323static int sky2_phys_id(struct net_device *dev, u32 data)
3324{
3325 struct sky2_port *sky2 = netdev_priv(dev);
3326 struct sky2_hw *hw = sky2->hw;
3327 unsigned port = sky2->port;
793b883e 3328 u16 ledctrl, ledover = 0;
cd28ab6a 3329 long ms;
91c86df5 3330 int interrupted;
cd28ab6a
SH		 3331 int onoff = 1;
3332
793b883e 3333 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3334 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3335 else
3336 ms = data * 1000;
3337
3338 /* save initial values */
e07b1aa8 3339 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3340 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3341 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3343 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3344 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3345 } else {
3346 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3347 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3348 }
cd28ab6a 3349
91c86df5
SH		 3350 interrupted = 0;
3351 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3352 sky2_led(hw, port, onoff);
3353 onoff = !onoff;
3354
e07b1aa8 3355 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3356 interrupted = msleep_interruptible(250);
e07b1aa8 3357 spin_lock_bh(&sky2->phy_lock);
91c86df5 3358
cd28ab6a
SH		 3359 ms -= 250;
3360 }
3361
3362 /* resume regularly scheduled programming */
793b883e
SH		 3363 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3364 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3366 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3367 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3368 } else {
3369 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3370 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3371 }
e07b1aa8 3372 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3373
3374 return 0;
3375}
3376
3377static void sky2_get_pauseparam(struct net_device *dev,
3378 struct ethtool_pauseparam *ecmd)
3379{
3380 struct sky2_port *sky2 = netdev_priv(dev);
3381
16ad91e1
SH		 3382 switch (sky2->flow_mode) {
3383 case FC_NONE:
3384 ecmd->tx_pause = ecmd->rx_pause = 0;
3385 break;
3386 case FC_TX:
3387 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3388 break;
3389 case FC_RX:
3390 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3391 break;
3392 case FC_BOTH:
3393 ecmd->tx_pause = ecmd->rx_pause = 1;
3394 }
3395
cd28ab6a
SH		 3396 ecmd->autoneg = sky2->autoneg;
3397}
3398
3399static int sky2_set_pauseparam(struct net_device *dev,
3400 struct ethtool_pauseparam *ecmd)
3401{
3402 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3403
3404 sky2->autoneg = ecmd->autoneg;
16ad91e1 3405 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3406
16ad91e1
SH		 3407 if (netif_running(dev))
3408 sky2_phy_reinit(sky2);
cd28ab6a 3409
2eaba1a2 3410 return 0;
cd28ab6a
SH		 3411}
3412
fb17358f
SH		 3413static int sky2_get_coalesce(struct net_device *dev,
3414 struct ethtool_coalesce *ecmd)
3415{
3416 struct sky2_port *sky2 = netdev_priv(dev);
3417 struct sky2_hw *hw = sky2->hw;
3418
3419 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3420 ecmd->tx_coalesce_usecs = 0;
3421 else {
3422 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3423 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3424 }
3425 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3426
3427 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3428 ecmd->rx_coalesce_usecs = 0;
3429 else {
3430 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3431 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3432 }
3433 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3434
3435 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3436 ecmd->rx_coalesce_usecs_irq = 0;
3437 else {
3438 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3439 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3440 }
3441
3442 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3443
3444 return 0;
3445}
3446
3447/* Note: this affect both ports */
3448static int sky2_set_coalesce(struct net_device *dev,
3449 struct ethtool_coalesce *ecmd)
3450{
3451 struct sky2_port *sky2 = netdev_priv(dev);
3452 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3453 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3454
77b3d6a2
SH		 3455 if (ecmd->tx_coalesce_usecs > tmax ||
3456 ecmd->rx_coalesce_usecs > tmax ||
3457 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3458 return -EINVAL;
3459
ff81fbbe 3460 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3461 return -EINVAL;
ff81fbbe 3462 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3463 return -EINVAL;
ff81fbbe 3464 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3465 return -EINVAL;
3466
3467 if (ecmd->tx_coalesce_usecs == 0)
3468 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3469 else {
3470 sky2_write32(hw, STAT_TX_TIMER_INI,
3471 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3472 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3473 }
3474 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3475
3476 if (ecmd->rx_coalesce_usecs == 0)
3477 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3478 else {
3479 sky2_write32(hw, STAT_LEV_TIMER_INI,
3480 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3481 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3482 }
3483 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3484
3485 if (ecmd->rx_coalesce_usecs_irq == 0)
3486 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3487 else {
d28d4870 3488 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3489 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3490 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3491 }
3492 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3493 return 0;
3494}
3495
793b883e
SH		 3496static void sky2_get_ringparam(struct net_device *dev,
3497 struct ethtool_ringparam *ering)
3498{
3499 struct sky2_port *sky2 = netdev_priv(dev);
3500
3501 ering->rx_max_pending = RX_MAX_PENDING;
3502 ering->rx_mini_max_pending = 0;
3503 ering->rx_jumbo_max_pending = 0;
3504 ering->tx_max_pending = TX_RING_SIZE - 1;
3505
3506 ering->rx_pending = sky2->rx_pending;
3507 ering->rx_mini_pending = 0;
3508 ering->rx_jumbo_pending = 0;
3509 ering->tx_pending = sky2->tx_pending;
3510}
3511
3512static int sky2_set_ringparam(struct net_device *dev,
3513 struct ethtool_ringparam *ering)
3514{
3515 struct sky2_port *sky2 = netdev_priv(dev);
3516 int err = 0;
3517
3518 if (ering->rx_pending > RX_MAX_PENDING ||
3519 ering->rx_pending < 8 ||
3520 ering->tx_pending < MAX_SKB_TX_LE ||
3521 ering->tx_pending > TX_RING_SIZE - 1)
3522 return -EINVAL;
3523
3524 if (netif_running(dev))
3525 sky2_down(dev);
3526
3527 sky2->rx_pending = ering->rx_pending;
3528 sky2->tx_pending = ering->tx_pending;
3529
1b537565 3530 if (netif_running(dev)) {
793b883e 3531 err = sky2_up(dev);
1b537565
SH		 3532 if (err)
3533 dev_close(dev);
6ed995bb
SH		 3534 else
3535 sky2_set_multicast(dev);
1b537565 3536 }
793b883e
SH		 3537
3538 return err;
3539}
3540
793b883e
SH		 3541static int sky2_get_regs_len(struct net_device *dev)
3542{
6e4cbb34 3543 return 0x4000;
793b883e
SH		 3544}
3545
3546/*
3547 * Returns copy of control register region
3ead5db7 3548 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3549 */
3550static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3551 void *p)
3552{
3553 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3554 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3555
3556 regs->version = 1;
6e4cbb34 3557 memset(p, 0, regs->len);
793b883e 3558
6e4cbb34
SH		 3559 memcpy_fromio(p, io, B3_RAM_ADDR);
3560
3ead5db7
SH		 3561 /* skip diagnostic ram region */
3562 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3563
3564 /* copy GMAC registers */
3565 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3566 if (sky2->hw->ports > 1)
3567 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3568
793b883e 3569}
cd28ab6a 3570
b628ed98
SH		 3571/* In order to do Jumbo packets on these chips, need to turn off the
3572 * transmit store/forward. Therefore checksum offload won't work.
3573 */
3574static int no_tx_offload(struct net_device *dev)
3575{
3576 const struct sky2_port *sky2 = netdev_priv(dev);
3577 const struct sky2_hw *hw = sky2->hw;
3578
69161611 3579 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3580}
3581
3582static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3583{
3584 if (data && no_tx_offload(dev))
3585 return -EINVAL;
3586
3587 return ethtool_op_set_tx_csum(dev, data);
3588}
3589
3590
3591static int sky2_set_tso(struct net_device *dev, u32 data)
3592{
3593 if (data && no_tx_offload(dev))
3594 return -EINVAL;
3595
3596 return ethtool_op_set_tso(dev, data);
3597}
3598
f4331a6d
SH		 3599static int sky2_get_eeprom_len(struct net_device *dev)
3600{
3601 struct sky2_port *sky2 = netdev_priv(dev);
3602 u16 reg2;
3603
3604 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3605 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3606}
3607
3608static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3609{
3610 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3611
3612 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3613 cpu_relax();
3614 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3615}
3616
3617static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3618{
3619 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3620 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3621 do {
3622 cpu_relax();
3623 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3624}
3625
3626static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3627 u8 *data)
3628{
3629 struct sky2_port *sky2 = netdev_priv(dev);
3630 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3631 int length = eeprom->len;
3632 u16 offset = eeprom->offset;
3633
3634 if (!cap)
3635 return -EINVAL;
3636
3637 eeprom->magic = SKY2_EEPROM_MAGIC;
3638
3639 while (length > 0) {
3640 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3641 int n = min_t(int, length, sizeof(val));
3642
3643 memcpy(data, &val, n);
3644 length -= n;
3645 data += n;
3646 offset += n;
3647 }
3648 return 0;
3649}
3650
3651static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3652 u8 *data)
3653{
3654 struct sky2_port *sky2 = netdev_priv(dev);
3655 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3656 int length = eeprom->len;
3657 u16 offset = eeprom->offset;
3658
3659 if (!cap)
3660 return -EINVAL;
3661
3662 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3663 return -EINVAL;
3664
3665 while (length > 0) {
3666 u32 val;
3667 int n = min_t(int, length, sizeof(val));
3668
3669 if (n < sizeof(val))
3670 val = sky2_vpd_read(sky2->hw, cap, offset);
3671 memcpy(&val, data, n);
3672
3673 sky2_vpd_write(sky2->hw, cap, offset, val);
3674
3675 length -= n;
3676 data += n;
3677 offset += n;
3678 }
3679 return 0;
3680}
3681
3682
7282d491 3683static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3684 .get_settings = sky2_get_settings,
3685 .set_settings = sky2_set_settings,
3686 .get_drvinfo = sky2_get_drvinfo,
3687 .get_wol = sky2_get_wol,
3688 .set_wol = sky2_set_wol,
3689 .get_msglevel = sky2_get_msglevel,
3690 .set_msglevel = sky2_set_msglevel,
3691 .nway_reset = sky2_nway_reset,
3692 .get_regs_len = sky2_get_regs_len,
3693 .get_regs = sky2_get_regs,
3694 .get_link = ethtool_op_get_link,
3695 .get_eeprom_len = sky2_get_eeprom_len,
3696 .get_eeprom = sky2_get_eeprom,
3697 .set_eeprom = sky2_set_eeprom,
3698 .get_sg = ethtool_op_get_sg,
3699 .set_sg = ethtool_op_set_sg,
3700 .get_tx_csum = ethtool_op_get_tx_csum,
3701 .set_tx_csum = sky2_set_tx_csum,
3702 .get_tso = ethtool_op_get_tso,
3703 .set_tso = sky2_set_tso,
3704 .get_rx_csum = sky2_get_rx_csum,
3705 .set_rx_csum = sky2_set_rx_csum,
3706 .get_strings = sky2_get_strings,
3707 .get_coalesce = sky2_get_coalesce,
3708 .set_coalesce = sky2_set_coalesce,
3709 .get_ringparam = sky2_get_ringparam,
3710 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3711 .get_pauseparam = sky2_get_pauseparam,
3712 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3713 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3714 .get_stats_count = sky2_get_stats_count,
3715 .get_ethtool_stats = sky2_get_ethtool_stats,
3716};
3717
3cf26753
SH		 3718#ifdef CONFIG_SKY2_DEBUG
3719
3720static struct dentry *sky2_debug;
3721
3722static int sky2_debug_show(struct seq_file *seq, void *v)
3723{
3724 struct net_device *dev = seq->private;
3725 const struct sky2_port *sky2 = netdev_priv(dev);
3726 const struct sky2_hw *hw = sky2->hw;
3727 unsigned port = sky2->port;
3728 unsigned idx, last;
3729 int sop;
3730
3731 if (!netif_running(dev))
3732 return -ENETDOWN;
3733
3734 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3735 sky2_read32(hw, B0_ISRC),
3736 sky2_read32(hw, B0_IMSK),
3737 sky2_read32(hw, B0_Y2_SP_ICR));
3738
3739 netif_poll_disable(hw->dev[0]);
3740 last = sky2_read16(hw, STAT_PUT_IDX);
3741
3742 if (hw->st_idx == last)
3743 seq_puts(seq, "Status ring (empty)\n");
3744 else {
3745 seq_puts(seq, "Status ring\n");
3746 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3747 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3748 const struct sky2_status_le *le = hw->st_le + idx;
3749 seq_printf(seq, "[%d] %#x %d %#x\n",
3750 idx, le->opcode, le->length, le->status);
3751 }
3752 seq_puts(seq, "\n");
3753 }
3754
3755 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3756 sky2->tx_cons, sky2->tx_prod,
3757 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3758 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3759
3760 /* Dump contents of tx ring */
3761 sop = 1;
3762 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3763 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3764 const struct sky2_tx_le *le = sky2->tx_le + idx;
3765 u32 a = le32_to_cpu(le->addr);
3766
3767 if (sop)
3768 seq_printf(seq, "%u:", idx);
3769 sop = 0;
3770
3771 switch(le->opcode & ~HW_OWNER) {
3772 case OP_ADDR64:
3773 seq_printf(seq, " %#x:", a);
3774 break;
3775 case OP_LRGLEN:
3776 seq_printf(seq, " mtu=%d", a);
3777 break;
3778 case OP_VLAN:
3779 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3780 break;
3781 case OP_TCPLISW:
3782 seq_printf(seq, " csum=%#x", a);
3783 break;
3784 case OP_LARGESEND:
3785 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3786 break;
3787 case OP_PACKET:
3788 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3789 break;
3790 case OP_BUFFER:
3791 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3792 break;
3793 default:
3794 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3795 a, le16_to_cpu(le->length));
3796 }
3797
3798 if (le->ctrl & EOP) {
3799 seq_putc(seq, '\n');
3800 sop = 1;
3801 }
3802 }
3803
3804 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3805 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3806 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3807 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3808
3809 netif_poll_enable(hw->dev[0]);
3810 return 0;
3811}
3812
3813static int sky2_debug_open(struct inode *inode, struct file *file)
3814{
3815 return single_open(file, sky2_debug_show, inode->i_private);
3816}
3817
3818static const struct file_operations sky2_debug_fops = {
3819 .owner = THIS_MODULE,
3820 .open = sky2_debug_open,
3821 .read = seq_read,
3822 .llseek = seq_lseek,
3823 .release = single_release,
3824};
3825
3826/*
3827 * Use network device events to create/remove/rename
3828 * debugfs file entries
3829 */
3830static int sky2_device_event(struct notifier_block *unused,
3831 unsigned long event, void *ptr)
3832{
3833 struct net_device *dev = ptr;
3834
3835 if (dev->open == sky2_up) {
3836 struct sky2_port *sky2 = netdev_priv(dev);
3837
3838 switch(event) {
3839 case NETDEV_CHANGENAME:
3840 if (!netif_running(dev))
3841 break;
3842 /* fallthrough */
3843 case NETDEV_DOWN:
3844 case NETDEV_GOING_DOWN:
3845 if (sky2->debugfs) {
3846 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3847 dev->name);
3848 debugfs_remove(sky2->debugfs);
3849 sky2->debugfs = NULL;
3850 }
3851
3852 if (event != NETDEV_CHANGENAME)
3853 break;
3854 /* fallthrough for changename */
3855 case NETDEV_UP:
3856 if (sky2_debug) {
3857 struct dentry *d;
3858 d = debugfs_create_file(dev->name, S_IRUGO,
3859 sky2_debug, dev,
3860 &sky2_debug_fops);
3861 if (d == NULL || IS_ERR(d))
3862 printk(KERN_INFO PFX
3863 "%s: debugfs create failed\n",
3864 dev->name);
3865 else
3866 sky2->debugfs = d;
3867 }
3868 break;
3869 }
3870 }
3871
3872 return NOTIFY_DONE;
3873}
3874
3875static struct notifier_block sky2_notifier = {
3876 .notifier_call = sky2_device_event,
3877};
3878
3879
3880static __init void sky2_debug_init(void)
3881{
3882 struct dentry *ent;
3883
3884 ent = debugfs_create_dir("sky2", NULL);
3885 if (!ent || IS_ERR(ent))
3886 return;
3887
3888 sky2_debug = ent;
3889 register_netdevice_notifier(&sky2_notifier);
3890}
3891
3892static __exit void sky2_debug_cleanup(void)
3893{
3894 if (sky2_debug) {
3895 unregister_netdevice_notifier(&sky2_notifier);
3896 debugfs_remove(sky2_debug);
3897 sky2_debug = NULL;
3898 }
3899}
3900
3901#else
3902#define sky2_debug_init()
3903#define sky2_debug_cleanup()
3904#endif
3905
3906
cd28ab6a
SH		 3907/* Initialize network device */
3908static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3909 unsigned port,
3910 int highmem, int wol)
cd28ab6a
SH		 3911{
3912 struct sky2_port *sky2;
3913 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3914
3915 if (!dev) {
b02a9258 3916 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3917 return NULL;
3918 }
3919
3920 SET_MODULE_OWNER(dev);
3921 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3922 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3923 dev->open = sky2_up;
3924 dev->stop = sky2_down;
ef743d33 3925 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3926 dev->hard_start_xmit = sky2_xmit_frame;
3927 dev->get_stats = sky2_get_stats;
3928 dev->set_multicast_list = sky2_set_multicast;
3929 dev->set_mac_address = sky2_set_mac_address;
3930 dev->change_mtu = sky2_change_mtu;
3931 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3932 dev->tx_timeout = sky2_tx_timeout;
3933 dev->watchdog_timeo = TX_WATCHDOG;
3934 if (port == 0)
3935 dev->poll = sky2_poll;
3936 dev->weight = NAPI_WEIGHT;
3937#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3938 /* Network console (only works on port 0)
3939 * because netpoll makes assumptions about NAPI
3940 */
3941 if (port == 0)
3942 dev->poll_controller = sky2_netpoll;
cd28ab6a 3943#endif
cd28ab6a
SH		 3944
3945 sky2 = netdev_priv(dev);
3946 sky2->netdev = dev;
3947 sky2->hw = hw;
3948 sky2->msg_enable = netif_msg_init(debug, default_msg);
3949
cd28ab6a
SH		 3950 /* Auto speed and flow control */
3951 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3952 sky2->flow_mode = FC_BOTH;
3953
cd28ab6a
SH		 3954 sky2->duplex = -1;
3955 sky2->speed = -1;
3956 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3957 sky2->rx_csum = 1;
e3173832 3958 sky2->wol = wol;
75d070c5 3959
e07b1aa8 3960 spin_lock_init(&sky2->phy_lock);
793b883e 3961 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3962 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3963
3964 hw->dev[port] = dev;
3965
3966 sky2->port = port;
3967
4a50a876 3968 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3969 if (highmem)
3970 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3971
d1f13708 3972#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 3973 /* The workaround for FE+ status conflicts with VLAN tag detection. */
3974 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
3975 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
3976 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3977 dev->vlan_rx_register = sky2_vlan_rx_register;
3978 }
d1f13708
SH		 3979#endif
3980
cd28ab6a 3981 /* read the mac address */
793b883e 3982 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3983 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3984
cd28ab6a
SH		 3985 return dev;
3986}
3987
28bd181a 3988static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3989{
3990 const struct sky2_port *sky2 = netdev_priv(dev);
3991
3992 if (netif_msg_probe(sky2))
3993 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3994 dev->name,
3995 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3996 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3997}
3998
fb2690a9 3999/* Handle software interrupt used during MSI test */
7d12e780 4000static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4001{
4002 struct sky2_hw *hw = dev_id;
4003 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4004
4005 if (status == 0)
4006 return IRQ_NONE;
4007
4008 if (status & Y2_IS_IRQ_SW) {
ea76e635 4009 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4010 wake_up(&hw->msi_wait);
4011 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4012 }
4013 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4014
4015 return IRQ_HANDLED;
4016}
4017
4018/* Test interrupt path by forcing a a software IRQ */
4019static int __devinit sky2_test_msi(struct sky2_hw *hw)
4020{
4021 struct pci_dev *pdev = hw->pdev;
4022 int err;
4023
bb507fe1
SH		 4024 init_waitqueue_head (&hw->msi_wait);
4025
fb2690a9
SH		 4026 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4027
b0a20ded 4028 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4029 if (err) {
b02a9258 4030 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4031 return err;
4032 }
4033
fb2690a9 4034 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4035 sky2_read8(hw, B0_CTST);
fb2690a9 4036
ea76e635 4037 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4038
ea76e635 4039 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4040 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4041 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4042 "switching to INTx mode.\n");
fb2690a9
SH		 4043
4044 err = -EOPNOTSUPP;
4045 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4046 }
4047
4048 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4049 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4050
4051 free_irq(pdev->irq, hw);
4052
4053 return err;
4054}
4055
e3173832
SH		 4056static int __devinit pci_wake_enabled(struct pci_dev *dev)
4057{
4058 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4059 u16 value;
4060
4061 if (!pm)
4062 return 0;
4063 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4064 return 0;
4065 return value & PCI_PM_CTRL_PME_ENABLE;
4066}
4067
cd28ab6a
SH		 4068static int __devinit sky2_probe(struct pci_dev *pdev,
4069 const struct pci_device_id *ent)
4070{
7f60c64b 4071 struct net_device *dev;
cd28ab6a 4072 struct sky2_hw *hw;
e3173832 4073 int err, using_dac = 0, wol_default;
cd28ab6a 4074
793b883e
SH		 4075 err = pci_enable_device(pdev);
4076 if (err) {
b02a9258 4077 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4078 goto err_out;
4079 }
4080
793b883e
SH		 4081 err = pci_request_regions(pdev, DRV_NAME);
4082 if (err) {
b02a9258 4083 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4084 goto err_out_disable;
cd28ab6a
SH		 4085 }
4086
4087 pci_set_master(pdev);
4088
d1f3d4dd
SH		 4089 if (sizeof(dma_addr_t) > sizeof(u32) &&
4090 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4091 using_dac = 1;
4092 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4093 if (err < 0) {
b02a9258
SH		 4094 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4095 "for consistent allocations\n");
d1f3d4dd
SH		 4096 goto err_out_free_regions;
4097 }
d1f3d4dd 4098 } else {
cd28ab6a
SH		 4099 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4100 if (err) {
b02a9258 4101 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4102 goto err_out_free_regions;
4103 }
4104 }
d1f3d4dd 4105
e3173832
SH		 4106 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4107
cd28ab6a 4108 err = -ENOMEM;
6aad85d6 4109 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4110 if (!hw) {
b02a9258 4111 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4112 goto err_out_free_regions;
4113 }
4114
cd28ab6a 4115 hw->pdev = pdev;
cd28ab6a
SH		 4116
4117 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4118 if (!hw->regs) {
b02a9258 4119 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4120 goto err_out_free_hw;
4121 }
4122
56a645cc 4123#ifdef __BIG_ENDIAN
f65b138c
SH		 4124 /* The sk98lin vendor driver uses hardware byte swapping but
4125 * this driver uses software swapping.
4126 */
56a645cc
SH		 4127 {
4128 u32 reg;
56a645cc 4129 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4130 reg &= ~PCI_REV_DESC;
56a645cc
SH		 4131 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4132 }
4133#endif
4134
08c06d8a
SH		 4135 /* ring for status responses */
4136 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
4137 &hw->st_dma);
4138 if (!hw->st_le)
4139 goto err_out_iounmap;
4140
e3173832 4141 err = sky2_init(hw);
cd28ab6a 4142 if (err)
793b883e 4143 goto err_out_iounmap;
cd28ab6a 4144
b02a9258 4145 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4146 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4147 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4148 hw->chip_id, hw->chip_rev);
cd28ab6a 4149
e3173832
SH		 4150 sky2_reset(hw);
4151
4152 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4153 if (!dev) {
4154 err = -ENOMEM;
cd28ab6a 4155 goto err_out_free_pci;
7f60c64b 4156 }
cd28ab6a 4157
9fa1b1f3
SH		 4158 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4159 err = sky2_test_msi(hw);
4160 if (err == -EOPNOTSUPP)
4161 pci_disable_msi(pdev);
4162 else if (err)
4163 goto err_out_free_netdev;
4164 }
4165
793b883e
SH		 4166 err = register_netdev(dev);
4167 if (err) {
b02a9258 4168 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4169 goto err_out_free_netdev;
4170 }
4171
ea76e635
SH		 4172 err = request_irq(pdev->irq, sky2_intr,
4173 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4174 dev->name, hw);
9fa1b1f3 4175 if (err) {
b02a9258 4176 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4177 goto err_out_unregister;
4178 }
4179 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4180
cd28ab6a
SH		 4181 sky2_show_addr(dev);
4182
7f60c64b 4183 if (hw->ports > 1) {
4184 struct net_device *dev1;
4185
e3173832 4186 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4187 if (!dev1)
4188 dev_warn(&pdev->dev, "allocation for second device failed\n");
4189 else if ((err = register_netdev(dev1))) {
4190 dev_warn(&pdev->dev,
4191 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4192 hw->dev[1] = NULL;
4193 free_netdev(dev1);
b02a9258
SH		 4194 } else
4195 sky2_show_addr(dev1);
cd28ab6a
SH		 4196 }
4197
32c2c300 4198 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4199 INIT_WORK(&hw->restart_work, sky2_restart);
4200
793b883e
SH		 4201 pci_set_drvdata(pdev, hw);
4202
cd28ab6a
SH		 4203 return 0;
4204
793b883e 4205err_out_unregister:
ea76e635 4206 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4207 pci_disable_msi(pdev);
793b883e 4208 unregister_netdev(dev);
cd28ab6a
SH		 4209err_out_free_netdev:
4210 free_netdev(dev);
cd28ab6a 4211err_out_free_pci:
793b883e 4212 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4213 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4214err_out_iounmap:
4215 iounmap(hw->regs);
4216err_out_free_hw:
4217 kfree(hw);
4218err_out_free_regions:
4219 pci_release_regions(pdev);
44a1d2e5 4220err_out_disable:
cd28ab6a 4221 pci_disable_device(pdev);
cd28ab6a 4222err_out:
549a68c3 4223 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4224 return err;
4225}
4226
4227static void __devexit sky2_remove(struct pci_dev *pdev)
4228{
793b883e 4229 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4230 struct net_device *dev0, *dev1;
4231
793b883e 4232 if (!hw)
cd28ab6a
SH		 4233 return;
4234
32c2c300 4235 del_timer_sync(&hw->watchdog_timer);
d27ed387 4236
81906791
SH		 4237 flush_scheduled_work();
4238
d27ed387 4239 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4240 synchronize_irq(hw->pdev->irq);
4241
cd28ab6a 4242 dev0 = hw->dev[0];
793b883e
SH		 4243 dev1 = hw->dev[1];
4244 if (dev1)
4245 unregister_netdev(dev1);
cd28ab6a
SH		 4246 unregister_netdev(dev0);
4247
ae306cca
SH		 4248 sky2_power_aux(hw);
4249
cd28ab6a 4250 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4251 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4252 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4253
4254 free_irq(pdev->irq, hw);
ea76e635 4255 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4256 pci_disable_msi(pdev);
793b883e 4257 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4258 pci_release_regions(pdev);
4259 pci_disable_device(pdev);
793b883e 4260
cd28ab6a
SH		 4261 if (dev1)
4262 free_netdev(dev1);
4263 free_netdev(dev0);
4264 iounmap(hw->regs);
4265 kfree(hw);
5afa0a9c 4266
cd28ab6a
SH		 4267 pci_set_drvdata(pdev, NULL);
4268}
4269
4270#ifdef CONFIG_PM
4271static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4272{
793b883e 4273 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4274 int i, wol = 0;
cd28ab6a 4275
549a68c3
SH		 4276 if (!hw)
4277 return 0;
4278
6a5706b9 4279 netif_poll_disable(hw->dev[0]);
eb35cf60 4280
f05267e7 4281 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4282 struct net_device *dev = hw->dev[i];
e3173832 4283 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4284
e3173832 4285 if (netif_running(dev))
5afa0a9c 4286 sky2_down(dev);
e3173832
SH		 4287
4288 if (sky2->wol)
4289 sky2_wol_init(sky2);
4290
4291 wol |= sky2->wol;
cd28ab6a
SH		 4292 }
4293
8ab8fca2 4294 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4295 sky2_power_aux(hw);
e3173832 4296
d374c1c1 4297 pci_save_state(pdev);
e3173832 4298 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4299 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4300
2ccc99b7 4301 return 0;
cd28ab6a
SH		 4302}
4303
4304static int sky2_resume(struct pci_dev *pdev)
4305{
793b883e 4306 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4307 int i, err;
cd28ab6a 4308
549a68c3
SH		 4309 if (!hw)
4310 return 0;
4311
ae306cca
SH		 4312 err = pci_set_power_state(pdev, PCI_D0);
4313 if (err)
4314 goto out;
4315
4316 err = pci_restore_state(pdev);
4317 if (err)
4318 goto out;
4319
cd28ab6a 4320 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4321
4322 /* Re-enable all clocks */
05745c4a
SH		 4323 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4324 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4325 hw->chip_id == CHIP_ID_YUKON_FE_P)
1ad5b4a5
SH		 4326 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4327
e3173832 4328 sky2_reset(hw);
cd28ab6a 4329
8ab8fca2
SH		 4330 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4331
f05267e7 4332 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4333 struct net_device *dev = hw->dev[i];
6a5706b9 4334 if (netif_running(dev)) {
08c06d8a
SH		 4335 err = sky2_up(dev);
4336 if (err) {
4337 printk(KERN_ERR PFX "%s: could not up: %d\n",
4338 dev->name, err);
4339 dev_close(dev);
eb35cf60 4340 goto out;
5afa0a9c 4341 }
d1b139c0
SH		 4342
4343 sky2_set_multicast(dev);
cd28ab6a
SH		 4344 }
4345 }
eb35cf60 4346
6a5706b9 4347 netif_poll_enable(hw->dev[0]);
32c2c300 4348
ae306cca 4349 return 0;
08c06d8a 4350out:
b02a9258 4351 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4352 pci_disable_device(pdev);
08c06d8a 4353 return err;
cd28ab6a
SH		 4354}
4355#endif
4356
e3173832
SH		 4357static void sky2_shutdown(struct pci_dev *pdev)
4358{
4359 struct sky2_hw *hw = pci_get_drvdata(pdev);
4360 int i, wol = 0;
4361
549a68c3
SH		 4362 if (!hw)
4363 return;
4364
e3173832
SH		 4365 netif_poll_disable(hw->dev[0]);
4366
4367 for (i = 0; i < hw->ports; i++) {
4368 struct net_device *dev = hw->dev[i];
4369 struct sky2_port *sky2 = netdev_priv(dev);
4370
4371 if (sky2->wol) {
4372 wol = 1;
4373 sky2_wol_init(sky2);
4374 }
4375 }
4376
4377 if (wol)
4378 sky2_power_aux(hw);
4379
4380 pci_enable_wake(pdev, PCI_D3hot, wol);
4381 pci_enable_wake(pdev, PCI_D3cold, wol);
4382
4383 pci_disable_device(pdev);
4384 pci_set_power_state(pdev, PCI_D3hot);
4385
4386}
4387
cd28ab6a 4388static struct pci_driver sky2_driver = {
793b883e
SH		 4389 .name = DRV_NAME,
4390 .id_table = sky2_id_table,
4391 .probe = sky2_probe,
4392 .remove = __devexit_p(sky2_remove),
cd28ab6a 4393#ifdef CONFIG_PM
793b883e
SH		 4394 .suspend = sky2_suspend,
4395 .resume = sky2_resume,
cd28ab6a 4396#endif
e3173832 4397 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4398};
4399
4400static int __init sky2_init_module(void)
4401{
3cf26753 4402 sky2_debug_init();
50241c4c 4403 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4404}
4405
4406static void __exit sky2_cleanup_module(void)
4407{
4408 pci_unregister_driver(&sky2_driver);
3cf26753 4409 sky2_debug_cleanup();
cd28ab6a
SH		 4410}
4411
4412module_init(sky2_init_module);
4413module_exit(sky2_cleanup_module);
4414
4415MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4416MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4417MODULE_LICENSE("GPL");
5f4f9dc1 4418MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)