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[PATCH] sky2: use kzalloc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * TODO
28 * - coalescing setting?
cd28ab6a
SH		 29 *
30 * TOTEST
31 * - speed setting
724bca3c 32 * - suspend/resume
cd28ab6a
SH		 33 */
34
35#include <linux/config.h>
793b883e 36#include <linux/crc32.h>
cd28ab6a
SH		 37#include <linux/kernel.h>
38#include <linux/version.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/pci.h>
44#include <linux/ip.h>
45#include <linux/tcp.h>
46#include <linux/in.h>
47#include <linux/delay.h>
d1f13708 48#include <linux/if_vlan.h>
cd28ab6a
SH		 49
50#include <asm/irq.h>
51
d1f13708
SH		 52#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53#define SKY2_VLAN_TAG_USED 1
54#endif
55
cd28ab6a
SH		 56#include "sky2.h"
57
58#define DRV_NAME "sky2"
724bca3c 59#define DRV_VERSION "0.6"
cd28ab6a
SH		 60#define PFX DRV_NAME " "
61
62/*
63 * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 * that are organized into three (receive, transmit, status) different rings
65 * similar to Tigon3. A transmit can require several elements;
66 * a receive requires one (or two if using 64 bit dma).
67 */
68
69#ifdef CONFIG_SKY2_EC_A1
70#define is_ec_a1(hw) \
71 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
73#else
74#define is_ec_a1(hw) 0
75#endif
76
793b883e 77#define RX_LE_SIZE 256
cd28ab6a 78#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
793b883e
SH		 79#define RX_MAX_PENDING (RX_LE_SIZE/2 - 1)
80#define RX_DEF_PENDING 128
79e57d32 81#define RX_COPY_THRESHOLD 256
793b883e
SH		 82
83#define TX_RING_SIZE 512
84#define TX_DEF_PENDING (TX_RING_SIZE - 1)
85#define TX_MIN_PENDING 64
86#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 87
793b883e 88#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 89#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
90#define ETH_JUMBO_MTU 9000
91#define TX_WATCHDOG (5 * HZ)
92#define NAPI_WEIGHT 64
93#define PHY_RETRIES 1000
94
95static const u32 default_msg =
793b883e
SH		 96 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
97 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
98 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 99
793b883e 100static int debug = -1; /* defaults above */
cd28ab6a
SH		 101module_param(debug, int, 0);
102MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
103
104static const struct pci_device_id sky2_id_table[] = {
793b883e 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { 0 }
123};
793b883e 124
cd28ab6a
SH		 125MODULE_DEVICE_TABLE(pci, sky2_id_table);
126
127/* Avoid conditionals by using array */
128static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
129static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
130
793b883e
SH		 131static const char *yukon_name[] = {
132 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
133 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
134 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
cd28ab6a 135
793b883e
SH		 136 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
137 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
138};
139
140
141/* Access to external PHY */
cd28ab6a
SH		 142static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
143{
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
793b883e
SH		 152 return;
153 udelay(1);
cd28ab6a 154 }
793b883e 155 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
cd28ab6a
SH		 156}
157
158static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
159{
160 int i;
161
793b883e 162 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 163 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
164
165 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a
SH		 166 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
167 goto ready;
793b883e 168 udelay(1);
cd28ab6a
SH		 169 }
170
793b883e
SH		 171 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
172ready:
cd28ab6a
SH		 173 return gma_read16(hw, port, GM_SMI_DATA);
174}
175
5afa0a9c
SH		 176static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
177{
178 u16 power_control;
179 u32 reg1;
180 int vaux;
181 int ret = 0;
182
183 pr_debug("sky2_set_power_state %d\n", state);
184 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
185
186 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
187 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
188 (power_control & PCI_PM_CAP_PME_D3cold);
189
190 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
191
192 power_control |= PCI_PM_CTRL_PME_STATUS;
193 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
194
195 switch (state) {
196 case PCI_D0:
197 /* switch power to VCC (WA for VAUX problem) */
198 sky2_write8(hw, B0_POWER_CTRL,
199 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
200
201 /* disable Core Clock Division, */
202 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
203
204 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
205 /* enable bits are inverted */
206 sky2_write8(hw, B2_Y2_CLK_GATE,
207 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
208 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
209 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
210 else
211 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
212
213 /* Turn off phy power saving */
214 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
215 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
216
217 /* looks like this xl is back asswards .. */
218 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
219 reg1 |= PCI_Y2_PHY1_COMA;
220 if (hw->ports > 1)
221 reg1 |= PCI_Y2_PHY2_COMA;
222 }
223 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
224 break;
225
226 case PCI_D3hot:
227 case PCI_D3cold:
228 /* Turn on phy power saving */
229 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
231 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
232 else
233 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
234 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
235
236 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
237 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
238 else
239 /* enable bits are inverted */
240 sky2_write8(hw, B2_Y2_CLK_GATE,
241 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
242 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
243 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
244
245 /* switch power to VAUX */
246 if (vaux && state != PCI_D3cold)
247 sky2_write8(hw, B0_POWER_CTRL,
248 (PC_VAUX_ENA | PC_VCC_ENA |
249 PC_VAUX_ON | PC_VCC_OFF));
250 break;
251 default:
252 printk(KERN_ERR PFX "Unknown power state %d\n", state);
253 ret = -1;
254 }
255
256 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
257 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
258 return ret;
259}
260
cd28ab6a
SH		 261static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
262{
263 u16 reg;
264
265 /* disable all GMAC IRQ's */
266 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
267 /* disable PHY IRQs */
268 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 269
cd28ab6a
SH		 270 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
271 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
272 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
274
275 reg = gma_read16(hw, port, GM_RX_CTRL);
276 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
277 gma_write16(hw, port, GM_RX_CTRL, reg);
278}
279
280static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
281{
282 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 283 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 284
793b883e 285 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 286 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
287
288 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 289 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 290 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
291
292 if (hw->chip_id == CHIP_ID_YUKON_EC)
293 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
294 else
295 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
296
297 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
298 }
299
300 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
301 if (hw->copper) {
302 if (hw->chip_id == CHIP_ID_YUKON_FE) {
303 /* enable automatic crossover */
304 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
305 } else {
306 /* disable energy detect */
307 ctrl &= ~PHY_M_PC_EN_DET_MSK;
308
309 /* enable automatic crossover */
310 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
311
312 if (sky2->autoneg == AUTONEG_ENABLE &&
313 hw->chip_id == CHIP_ID_YUKON_XL) {
314 ctrl &= ~PHY_M_PC_DSC_MSK;
315 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
316 }
317 }
318 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
319 } else {
320 /* workaround for deviation #4.88 (CRC errors) */
321 /* disable Automatic Crossover */
322
323 ctrl &= ~PHY_M_PC_MDIX_MSK;
324 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
325
326 if (hw->chip_id == CHIP_ID_YUKON_XL) {
327 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
328 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
329 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
330 ctrl &= ~PHY_M_MAC_MD_MSK;
331 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333
334 /* select page 1 to access Fiber registers */
335 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
336 }
cd28ab6a
SH		 337 }
338
339 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
340 if (sky2->autoneg == AUTONEG_DISABLE)
341 ctrl &= ~PHY_CT_ANE;
342 else
343 ctrl |= PHY_CT_ANE;
344
345 ctrl |= PHY_CT_RESET;
346 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
347
348 ctrl = 0;
349 ct1000 = 0;
350 adv = PHY_AN_CSMA;
351
352 if (sky2->autoneg == AUTONEG_ENABLE) {
353 if (hw->copper) {
354 if (sky2->advertising & ADVERTISED_1000baseT_Full)
355 ct1000 |= PHY_M_1000C_AFD;
356 if (sky2->advertising & ADVERTISED_1000baseT_Half)
357 ct1000 |= PHY_M_1000C_AHD;
358 if (sky2->advertising & ADVERTISED_100baseT_Full)
359 adv |= PHY_M_AN_100_FD;
360 if (sky2->advertising & ADVERTISED_100baseT_Half)
361 adv |= PHY_M_AN_100_HD;
362 if (sky2->advertising & ADVERTISED_10baseT_Full)
363 adv |= PHY_M_AN_10_FD;
364 if (sky2->advertising & ADVERTISED_10baseT_Half)
365 adv |= PHY_M_AN_10_HD;
793b883e 366 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 367 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
368
369 /* Set Flow-control capabilities */
370 if (sky2->tx_pause && sky2->rx_pause)
793b883e 371 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 372 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 373 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 374 else if (!sky2->rx_pause && sky2->tx_pause)
375 adv |= PHY_AN_PAUSE_ASYM; /* local */
376
377 /* Restart Auto-negotiation */
378 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
379 } else {
380 /* forced speed/duplex settings */
381 ct1000 = PHY_M_1000C_MSE;
382
383 if (sky2->duplex == DUPLEX_FULL)
384 ctrl |= PHY_CT_DUP_MD;
385
386 switch (sky2->speed) {
387 case SPEED_1000:
388 ctrl |= PHY_CT_SP1000;
389 break;
390 case SPEED_100:
391 ctrl |= PHY_CT_SP100;
392 break;
393 }
394
395 ctrl |= PHY_CT_RESET;
396 }
397
398 if (hw->chip_id != CHIP_ID_YUKON_FE)
399 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
400
401 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
402 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
403
404 /* Setup Phy LED's */
405 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
406 ledover = 0;
407
408 switch (hw->chip_id) {
409 case CHIP_ID_YUKON_FE:
410 /* on 88E3082 these bits are at 11..9 (shifted left) */
411 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
412
413 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
414
415 /* delete ACT LED control bits */
416 ctrl &= ~PHY_M_FELP_LED1_MSK;
417 /* change ACT LED control to blink mode */
418 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
419 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
420 break;
421
422 case CHIP_ID_YUKON_XL:
793b883e 423 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 424
425 /* select page 3 to access LED control register */
426 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
427
428 /* set LED Function Control register */
793b883e
SH		 429 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
430 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
431 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
432 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 433
434 /* set Polarity Control register */
435 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 436 (PHY_M_POLC_LS1_P_MIX(4) |
437 PHY_M_POLC_IS0_P_MIX(4) |
438 PHY_M_POLC_LOS_CTRL(2) |
439 PHY_M_POLC_INIT_CTRL(2) |
440 PHY_M_POLC_STA1_CTRL(2) |
441 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 442
443 /* restore page register */
793b883e 444 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 445 break;
446
447 default:
448 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
449 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
450 /* turn off the Rx LED (LED_RX) */
451 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
452 }
453
454 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
455
456 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
457 /* turn on 100 Mbps LED (LED_LINK100) */
458 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
459 }
460
461 if (ledover)
462 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
463
464 /* Enable phy interrupt on autonegotiation complete (or link up) */
465 if (sky2->autoneg == AUTONEG_ENABLE)
466 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
467 else
468 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
469}
470
471static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
472{
473 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
474 u16 reg;
475 int i;
476 const u8 *addr = hw->dev[port]->dev_addr;
477
478 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
479 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
480
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
482
793b883e 483 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 484 /* WA DEV_472 -- looks like crossed wires on port 2 */
485 /* clear GMAC 1 Control reset */
486 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
487 do {
488 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
489 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
490 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
491 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
492 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
493 }
494
cd28ab6a
SH		 495 if (sky2->autoneg == AUTONEG_DISABLE) {
496 reg = gma_read16(hw, port, GM_GP_CTRL);
497 reg |= GM_GPCR_AU_ALL_DIS;
498 gma_write16(hw, port, GM_GP_CTRL, reg);
499 gma_read16(hw, port, GM_GP_CTRL);
500
cd28ab6a
SH		 501 switch (sky2->speed) {
502 case SPEED_1000:
503 reg |= GM_GPCR_SPEED_1000;
504 /* fallthru */
505 case SPEED_100:
506 reg |= GM_GPCR_SPEED_100;
507 }
508
509 if (sky2->duplex == DUPLEX_FULL)
510 reg |= GM_GPCR_DUP_FULL;
511 } else
512 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
513
514 if (!sky2->tx_pause && !sky2->rx_pause) {
515 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 516 reg |=
517 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
518 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 519 /* disable Rx flow-control */
520 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
521 }
522
523 gma_write16(hw, port, GM_GP_CTRL, reg);
524
793b883e 525 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a
SH		 526
527 spin_lock_bh(&hw->phy_lock);
528 sky2_phy_init(hw, port);
529 spin_unlock_bh(&hw->phy_lock);
530
531 /* MIB clear */
532 reg = gma_read16(hw, port, GM_PHY_ADDR);
533 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
534
535 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 536 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 537 gma_write16(hw, port, GM_PHY_ADDR, reg);
538
539 /* transmit control */
540 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
541
542 /* receive control reg: unicast + multicast + no FCS */
543 gma_write16(hw, port, GM_RX_CTRL,
793b883e 544 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 545
546 /* transmit flow control */
547 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
548
549 /* transmit parameter */
550 gma_write16(hw, port, GM_TX_PARAM,
551 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
552 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
553 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
554 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
555
556 /* serial mode register */
557 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 558 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 559
6b1a3aef 560 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 561 reg |= GM_SMOD_JUMBO_ENA;
562
563 gma_write16(hw, port, GM_SERIAL_MODE, reg);
564
cd28ab6a
SH		 565 /* virtual address for data */
566 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
567
793b883e
SH		 568 /* physical address: used for pause frames */
569 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
570
571 /* ignore counter overflows */
cd28ab6a
SH		 572 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
573 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
574 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
575
576 /* Configure Rx MAC FIFO */
577 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 578 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 579 GMF_RX_CTRL_DEF);
cd28ab6a 580
793b883e
SH		 581 /* Flush Rx MAC FIFO on any flowcontrol or error */
582 reg = GMR_FS_ANY_ERR;
cd28ab6a
SH		 583 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
584 reg = 0; /* WA Dev #4115 */
585
586 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
793b883e
SH		 587 /* Set threshold to 0xa (64 bytes)
588 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 589 */
590 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
591
592 /* Configure Tx MAC FIFO */
593 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
594 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
cd28ab6a
SH		 595}
596
597static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
598{
599 u32 end;
600
601 start /= 8;
602 len /= 8;
603 end = start + len - 1;
793b883e 604
cd28ab6a
SH		 605 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
606 sky2_write32(hw, RB_ADDR(q, RB_START), start);
607 sky2_write32(hw, RB_ADDR(q, RB_END), end);
608 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
609 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
610
611 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 612 u32 rxup, rxlo;
613
614 rxlo = len/2;
615 rxup = rxlo + len/4;
793b883e 616
cd28ab6a 617 /* Set thresholds on receive queue's */
793b883e
SH		 618 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
619 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 620 } else {
621 /* Enable store & forward on Tx queue's because
622 * Tx FIFO is only 1K on Yukon
623 */
624 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
625 }
626
627 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 628 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 629}
630
cd28ab6a
SH		 631/* Setup Bus Memory Interface */
632static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
633{
634 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
635 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
636 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
637 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
638}
639
cd28ab6a
SH		 640/* Setup prefetch unit registers. This is the interface between
641 * hardware and driver list elements
642 */
643static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
644 u64 addr, u32 last)
645{
cd28ab6a
SH		 646 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
647 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
648 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
649 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
650 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
651 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 652
653 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 654}
655
793b883e
SH		 656static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
657{
658 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
659
660 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
661 return le;
662}
cd28ab6a
SH		 663
664/*
665 * This is a workaround code taken from syskonnect sk98lin driver
793b883e 666 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 667 */
668static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
669 u16 idx, u16 *last, u16 size)
cd28ab6a 670{
cd28ab6a
SH		 671 if (is_ec_a1(hw) && idx < *last) {
672 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
673
674 if (hwget == 0) {
675 /* Start prefetching again */
793b883e 676 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 677 goto setnew;
678 }
679
793b883e 680 if (hwget == size - 1) {
cd28ab6a
SH		 681 /* set watermark to one list element */
682 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
683
684 /* set put index to first list element */
685 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 686 } else /* have hardware go to end of list */
687 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
688 size - 1);
cd28ab6a 689 } else {
793b883e 690setnew:
cd28ab6a 691 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 692 }
793b883e 693 *last = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 694}
695
793b883e 696
cd28ab6a
SH		 697static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
698{
699 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
700 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
701 return le;
702}
703
793b883e
SH		 704/* Build description to hardware about buffer */
705static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
cd28ab6a
SH		 706{
707 struct sky2_rx_le *le;
793b883e 708 u32 hi = (re->mapaddr >> 16) >> 16;
cd28ab6a 709
793b883e
SH		 710 re->idx = sky2->rx_put;
711 if (sky2->rx_addr64 != hi) {
cd28ab6a 712 le = sky2_next_rx(sky2);
793b883e 713 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 714 le->ctrl = 0;
715 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 716 sky2->rx_addr64 = hi;
cd28ab6a 717 }
793b883e 718
cd28ab6a 719 le = sky2_next_rx(sky2);
793b883e
SH		 720 le->addr = cpu_to_le32((u32) re->mapaddr);
721 le->length = cpu_to_le16(re->maplen);
cd28ab6a
SH		 722 le->ctrl = 0;
723 le->opcode = OP_PACKET | HW_OWNER;
724}
725
793b883e
SH		 726/* Tell receiver about new buffers. */
727static inline void rx_set_put(struct net_device *dev)
728{
729 struct sky2_port *sky2 = netdev_priv(dev);
730
731 if (sky2->rx_last_put != sky2->rx_put)
732 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
733 &sky2->rx_last_put, RX_LE_SIZE);
734}
735
cd28ab6a
SH		 736/* Tell chip where to start receive checksum.
737 * Actually has two checksums, but set both same to avoid possible byte
738 * order problems.
739 */
793b883e 740static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 741{
742 struct sky2_rx_le *le;
743
cd28ab6a 744 le = sky2_next_rx(sky2);
793b883e 745 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 746 le->ctrl = 0;
747 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 748
793b883e
SH		 749 sky2_write32(sky2->hw,
750 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
751 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 752
753}
754
6b1a3aef
SH		 755/*
756 * The RX Stop command will not work for Yukon-2 if the BMU does not
757 * reach the end of packet and since we can't make sure that we have
758 * incoming data, we must reset the BMU while it is not doing a DMA
759 * transfer. Since it is possible that the RX path is still active,
760 * the RX RAM buffer will be stopped first, so any possible incoming
761 * data will not trigger a DMA. After the RAM buffer is stopped, the
762 * BMU is polled until any DMA in progress is ended and only then it
763 * will be reset.
764 */
765static void sky2_rx_stop(struct sky2_port *sky2)
766{
767 struct sky2_hw *hw = sky2->hw;
768 unsigned rxq = rxqaddr[sky2->port];
769 int i;
770
771 /* disable the RAM Buffer receive queue */
772 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
773
774 for (i = 0; i < 0xffff; i++)
775 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
776 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
777 goto stopped;
778
779 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
780 sky2->netdev->name);
781stopped:
782 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
783
784 /* reset the Rx prefetch unit */
785 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
786}
793b883e 787
cd28ab6a
SH		 788/* Cleanout receive buffer area, assumes receiver hardware stopped */
789static void sky2_rx_clean(struct sky2_port *sky2)
790{
791 unsigned i;
792
793 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 794 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 795 struct ring_info *re = sky2->rx_ring + i;
796
797 if (re->skb) {
793b883e
SH		 798 pci_unmap_single(sky2->hw->pdev,
799 re->mapaddr, re->maplen,
cd28ab6a
SH		 800 PCI_DMA_FROMDEVICE);
801 kfree_skb(re->skb);
802 re->skb = NULL;
803 }
804 }
805}
806
d1f13708
SH		 807#ifdef SKY2_VLAN_TAG_USED
808static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
809{
810 struct sky2_port *sky2 = netdev_priv(dev);
811 struct sky2_hw *hw = sky2->hw;
812 u16 port = sky2->port;
813 unsigned long flags;
814
815 spin_lock_irqsave(&sky2->tx_lock, flags);
816
817 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
818 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
819 sky2->vlgrp = grp;
820
821 spin_unlock_irqrestore(&sky2->tx_lock, flags);
822}
823
824static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
825{
826 struct sky2_port *sky2 = netdev_priv(dev);
827 struct sky2_hw *hw = sky2->hw;
828 u16 port = sky2->port;
829 unsigned long flags;
830
831 spin_lock_irqsave(&sky2->tx_lock, flags);
832
833 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
834 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
835 if (sky2->vlgrp)
836 sky2->vlgrp->vlan_devices[vid] = NULL;
837
838 spin_unlock_irqrestore(&sky2->tx_lock, flags);
839}
840#endif
841
79e57d32 842#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
6b1a3aef 843static inline unsigned rx_size(const struct sky2_port *sky2)
cd28ab6a 844{
79e57d32 845 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
cd28ab6a
SH		 846}
847
848/*
849 * Allocate and setup receiver buffer pool.
850 * In case of 64 bit dma, there are 2X as many list elements
851 * available as ring entries
852 * and need to reserve one list element so we don't wrap around.
79e57d32
SH		 853 *
854 * It appears the hardware has a bug in the FIFO logic that
855 * cause it to hang if the FIFO gets overrun and the receive buffer
856 * is not aligned. This means we can't use skb_reserve to align
857 * the IP header.
cd28ab6a 858 */
6b1a3aef 859static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 860{
6b1a3aef
SH		 861 struct sky2_hw *hw = sky2->hw;
862 unsigned size = rx_size(sky2);
863 unsigned rxq = rxqaddr[sky2->port];
864 int i;
cd28ab6a 865
6b1a3aef
SH		 866 sky2->rx_put = sky2->rx_next = 0;
867 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
868 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
869
870 rx_set_checksum(sky2);
793b883e 871 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 872 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 873
79e57d32 874 re->skb = dev_alloc_skb(size);
cd28ab6a
SH		 875 if (!re->skb)
876 goto nomem;
877
6b1a3aef 878 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
79e57d32
SH		 879 size, PCI_DMA_FROMDEVICE);
880 re->maplen = size;
793b883e 881 sky2_rx_add(sky2, re);
cd28ab6a
SH		 882 }
883
6b1a3aef
SH		 884 /* Tell chip about available buffers */
885 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
886 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 887 return 0;
888nomem:
889 sky2_rx_clean(sky2);
890 return -ENOMEM;
891}
892
893/* Bring up network interface. */
894static int sky2_up(struct net_device *dev)
895{
896 struct sky2_port *sky2 = netdev_priv(dev);
897 struct sky2_hw *hw = sky2->hw;
898 unsigned port = sky2->port;
899 u32 ramsize, rxspace;
900 int err = -ENOMEM;
901
902 if (netif_msg_ifup(sky2))
903 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
904
905 /* must be power of 2 */
906 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 907 TX_RING_SIZE *
908 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 909 &sky2->tx_le_map);
910 if (!sky2->tx_le)
911 goto err_out;
912
b2f5ad4f 913 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
cd28ab6a
SH		 914 GFP_KERNEL);
915 if (!sky2->tx_ring)
916 goto err_out;
917 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 918
919 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
920 &sky2->rx_le_map);
921 if (!sky2->rx_le)
922 goto err_out;
923 memset(sky2->rx_le, 0, RX_LE_BYTES);
924
b2f5ad4f 925 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
cd28ab6a
SH		 926 GFP_KERNEL);
927 if (!sky2->rx_ring)
928 goto err_out;
929
930 sky2_mac_init(hw, port);
931
932 /* Configure RAM buffers */
933 if (hw->chip_id == CHIP_ID_YUKON_FE ||
934 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
935 ramsize = 4096;
936 else {
793b883e
SH		 937 u8 e0 = sky2_read8(hw, B2_E_0);
938 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 939 }
940
941 /* 2/3 for Rx */
942 rxspace = (2 * ramsize) / 3;
943 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
944 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
945
793b883e
SH		 946 /* Make sure SyncQ is disabled */
947 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
948 RB_RST_SET);
949
cd28ab6a 950 sky2_qset(hw, txqaddr[port], 0x600);
6b1a3aef
SH		 951 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
952 TX_RING_SIZE - 1);
cd28ab6a 953
6b1a3aef 954 err = sky2_rx_start(sky2);
cd28ab6a
SH		 955 if (err)
956 goto err_out;
957
cd28ab6a
SH		 958 /* Enable interrupts from phy/mac for port */
959 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
960 sky2_write32(hw, B0_IMSK, hw->intr_mask);
961 return 0;
962
963err_out:
964 if (sky2->rx_le)
965 pci_free_consistent(hw->pdev, RX_LE_BYTES,
966 sky2->rx_le, sky2->rx_le_map);
967 if (sky2->tx_le)
968 pci_free_consistent(hw->pdev,
969 TX_RING_SIZE * sizeof(struct sky2_tx_le),
970 sky2->tx_le, sky2->tx_le_map);
971 if (sky2->tx_ring)
972 kfree(sky2->tx_ring);
973 if (sky2->rx_ring)
974 kfree(sky2->rx_ring);
975
976 return err;
977}
978
793b883e
SH		 979/* Modular subtraction in ring */
980static inline int tx_dist(unsigned tail, unsigned head)
981{
982 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
983}
cd28ab6a 984
793b883e
SH		 985/* Number of list elements available for next tx */
986static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 987{
793b883e 988 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 989}
990
793b883e
SH		 991/* Estimate of number of transmit list elements required */
992static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 993{
793b883e
SH		 994 unsigned count;
995
996 count = sizeof(dma_addr_t) / sizeof(u32);
997 count += skb_shinfo(skb)->nr_frags * count;
998
999 if (skb_shinfo(skb)->tso_size)
1000 ++count;
1001
1002 if (skb->ip_summed)
1003 ++count;
1004
1005 return count;
cd28ab6a
SH		 1006}
1007
793b883e
SH		 1008/*
1009 * Put one packet in ring for transmit.
1010 * A single packet can generate multiple list elements, and
1011 * the number of ring elements will probably be less than the number
1012 * of list elements used.
1013 */
cd28ab6a
SH		 1014static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1015{
1016 struct sky2_port *sky2 = netdev_priv(dev);
1017 struct sky2_hw *hw = sky2->hw;
d1f13708 1018 struct sky2_tx_le *le = NULL;
cd28ab6a 1019 struct ring_info *re;
793b883e 1020 unsigned long flags;
cd28ab6a
SH		 1021 unsigned i, len;
1022 dma_addr_t mapping;
1023 u32 addr64;
1024 u16 mss;
1025 u8 ctrl;
1026
793b883e
SH		 1027 local_irq_save(flags);
1028 if (!spin_trylock(&sky2->tx_lock)) {
1029 local_irq_restore(flags);
cd28ab6a 1030 return NETDEV_TX_LOCKED;
793b883e 1031 }
cd28ab6a 1032
793b883e 1033 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
cd28ab6a 1034 netif_stop_queue(dev);
793b883e 1035 spin_unlock_irqrestore(&sky2->tx_lock, flags);
cd28ab6a
SH		 1036
1037 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1038 dev->name);
1039 return NETDEV_TX_BUSY;
1040 }
1041
793b883e 1042 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1043 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1044 dev->name, sky2->tx_prod, skb->len);
1045
cd28ab6a
SH		 1046 len = skb_headlen(skb);
1047 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e
SH		 1048 addr64 = (mapping >> 16) >> 16;
1049
1050 re = sky2->tx_ring + sky2->tx_prod;
1051
1052 /* Send high bits if changed */
1053 if (addr64 != sky2->tx_addr64) {
1054 le = get_tx_le(sky2);
1055 le->tx.addr = cpu_to_le32(addr64);
1056 le->ctrl = 0;
1057 le->opcode = OP_ADDR64 | HW_OWNER;
1058 sky2->tx_addr64 = addr64;
1059 }
cd28ab6a
SH		 1060
1061 /* Check for TCP Segmentation Offload */
1062 mss = skb_shinfo(skb)->tso_size;
793b883e 1063 if (mss != 0) {
cd28ab6a
SH		 1064 /* just drop the packet if non-linear expansion fails */
1065 if (skb_header_cloned(skb) &&
1066 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1067 dev_kfree_skb_any(skb);
1068 goto out_unlock;
cd28ab6a
SH		 1069 }
1070
1071 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1072 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1073 mss += ETH_HLEN;
793b883e 1074 }
cd28ab6a 1075
793b883e 1076 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1077 le = get_tx_le(sky2);
1078 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1079 le->tx.tso.rsvd = 0;
cd28ab6a 1080 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1081 le->ctrl = 0;
793b883e 1082 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1083 }
1084
cd28ab6a 1085 ctrl = 0;
d1f13708
SH		 1086#ifdef SKY2_VLAN_TAG_USED
1087 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1088 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1089 if (!le) {
1090 le = get_tx_le(sky2);
1091 le->tx.addr = 0;
1092 le->opcode = OP_VLAN|HW_OWNER;
1093 le->ctrl = 0;
1094 } else
1095 le->opcode |= OP_VLAN;
1096 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1097 ctrl |= INS_VLAN;
1098 }
1099#endif
1100
1101 /* Handle TCP checksum offload */
cd28ab6a 1102 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1103 u16 hdr = skb->h.raw - skb->data;
1104 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1105
1106 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1107 if (skb->nh.iph->protocol == IPPROTO_UDP)
1108 ctrl |= UDPTCP;
1109
1110 le = get_tx_le(sky2);
1111 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1112 le->tx.csum.offset = cpu_to_le16(offset);
1113 le->length = 0; /* initial checksum value */
cd28ab6a 1114 le->ctrl = 1; /* one packet */
793b883e 1115 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1116 }
1117
1118 le = get_tx_le(sky2);
1119 le->tx.addr = cpu_to_le32((u32) mapping);
1120 le->length = cpu_to_le16(len);
1121 le->ctrl = ctrl;
793b883e 1122 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1123
793b883e 1124 /* Record the transmit mapping info */
cd28ab6a 1125 re->skb = skb;
793b883e
SH		 1126 re->mapaddr = mapping;
1127 re->maplen = len;
cd28ab6a
SH		 1128
1129 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1130 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
793b883e 1131 struct ring_info *fre;
cd28ab6a
SH		 1132
1133 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1134 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1135 addr64 = (mapping >> 16) >> 16;
1136 if (addr64 != sky2->tx_addr64) {
1137 le = get_tx_le(sky2);
1138 le->tx.addr = cpu_to_le32(addr64);
1139 le->ctrl = 0;
1140 le->opcode = OP_ADDR64 | HW_OWNER;
1141 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1142 }
1143
1144 le = get_tx_le(sky2);
1145 le->tx.addr = cpu_to_le32((u32) mapping);
1146 le->length = cpu_to_le16(frag->size);
1147 le->ctrl = ctrl;
793b883e 1148 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1149
793b883e
SH		 1150 fre = sky2->tx_ring
1151 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1152 fre->skb = NULL;
1153 fre->mapaddr = mapping;
1154 fre->maplen = frag->size;
cd28ab6a 1155 }
793b883e 1156 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1157 le->ctrl |= EOP;
1158
724bca3c 1159 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1160 &sky2->tx_last_put, TX_RING_SIZE);
1161
793b883e 1162 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
cd28ab6a 1163 netif_stop_queue(dev);
793b883e
SH		 1164
1165out_unlock:
1166 mmiowb();
1167 spin_unlock_irqrestore(&sky2->tx_lock, flags);
cd28ab6a
SH		 1168
1169 dev->trans_start = jiffies;
1170 return NETDEV_TX_OK;
1171}
1172
cd28ab6a 1173/*
793b883e
SH		 1174 * Free ring elements from starting at tx_cons until "done"
1175 *
1176 * NB: the hardware will tell us about partial completion of multi-part
1177 * buffers; these are defered until completion.
cd28ab6a 1178 */
d11c13e7 1179static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1180{
d11c13e7 1181 struct net_device *dev = sky2->netdev;
793b883e 1182 unsigned i;
cd28ab6a 1183
d11c13e7
SH		 1184 if (unlikely(netif_msg_tx_done(sky2)))
1185 printk(KERN_DEBUG "%s: tx done, upto %u\n",
1186 dev->name, done);
cd28ab6a
SH		 1187
1188 spin_lock(&sky2->tx_lock);
cd28ab6a 1189
793b883e
SH		 1190 while (sky2->tx_cons != done) {
1191 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1192 struct sk_buff *skb;
cd28ab6a 1193
793b883e
SH		 1194 /* Check for partial status */
1195 if (tx_dist(sky2->tx_cons, done)
1196 < tx_dist(sky2->tx_cons, re->idx))
1197 goto out;
1198
1199 skb = re->skb;
1200 pci_unmap_single(sky2->hw->pdev,
1201 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1202
1203 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1204 struct ring_info *fre;
1205 fre =
1206 sky2->tx_ring + (sky2->tx_cons + i +
1207 1) % TX_RING_SIZE;
1208 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1209 fre->maplen, PCI_DMA_TODEVICE);
cd28ab6a
SH		 1210 }
1211
cd28ab6a 1212 dev_kfree_skb_any(skb);
cd28ab6a 1213
793b883e
SH		 1214 sky2->tx_cons = re->idx;
1215 }
1216out:
1217
1218 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1219 netif_wake_queue(dev);
1220 spin_unlock(&sky2->tx_lock);
1221}
1222
1223/* Cleanup all untransmitted buffers, assume transmitter not running */
1224static inline void sky2_tx_clean(struct sky2_port *sky2)
1225{
d11c13e7 1226 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1227}
1228
1229/* Network shutdown */
1230static int sky2_down(struct net_device *dev)
1231{
1232 struct sky2_port *sky2 = netdev_priv(dev);
1233 struct sky2_hw *hw = sky2->hw;
1234 unsigned port = sky2->port;
1235 u16 ctrl;
cd28ab6a
SH		 1236
1237 if (netif_msg_ifdown(sky2))
1238 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1239
1240 netif_stop_queue(dev);
1241
793b883e
SH		 1242 sky2_phy_reset(hw, port);
1243
cd28ab6a
SH		 1244 /* Stop transmitter */
1245 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1246 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1247
1248 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1249 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1250
1251 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1252 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1253 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1254
1255 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1256
1257 /* Workaround shared GMAC reset */
793b883e
SH		 1258 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1259 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1260 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1261
1262 /* Disable Force Sync bit and Enable Alloc bit */
1263 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1264 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1265
1266 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1267 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1268 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1269
1270 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1271 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1272 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1273
1274 /* Reset the Tx prefetch units */
1275 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1276 PREF_UNIT_RST_SET);
1277
1278 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1279
6b1a3aef 1280 sky2_rx_stop(sky2);
cd28ab6a
SH		 1281
1282 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1283 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1284
1285 /* turn off led's */
1286 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1287
1288 sky2_tx_clean(sky2);
1289 sky2_rx_clean(sky2);
1290
1291 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1292 sky2->rx_le, sky2->rx_le_map);
1293 kfree(sky2->rx_ring);
1294
1295 pci_free_consistent(hw->pdev,
1296 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1297 sky2->tx_le, sky2->tx_le_map);
1298 kfree(sky2->tx_ring);
1299
1300 return 0;
1301}
1302
1303static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1304{
793b883e
SH		 1305 if (!hw->copper)
1306 return SPEED_1000;
1307
cd28ab6a
SH		 1308 if (hw->chip_id == CHIP_ID_YUKON_FE)
1309 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1310
1311 switch (aux & PHY_M_PS_SPEED_MSK) {
1312 case PHY_M_PS_SPEED_1000:
1313 return SPEED_1000;
1314 case PHY_M_PS_SPEED_100:
1315 return SPEED_100;
1316 default:
1317 return SPEED_10;
1318 }
1319}
1320
1321static void sky2_link_up(struct sky2_port *sky2)
1322{
1323 struct sky2_hw *hw = sky2->hw;
1324 unsigned port = sky2->port;
1325 u16 reg;
1326
793b883e
SH		 1327 /* disable Rx GMAC FIFO flush mode */
1328 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1329
cd28ab6a 1330 /* Enable Transmit FIFO Underrun */
793b883e 1331 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1332
1333 reg = gma_read16(hw, port, GM_GP_CTRL);
1334 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1335 reg |= GM_GPCR_DUP_FULL;
1336
cd28ab6a
SH		 1337 /* enable Rx/Tx */
1338 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1339 gma_write16(hw, port, GM_GP_CTRL, reg);
1340 gma_read16(hw, port, GM_GP_CTRL);
1341
1342 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1343
1344 netif_carrier_on(sky2->netdev);
1345 netif_wake_queue(sky2->netdev);
1346
1347 /* Turn on link LED */
793b883e 1348 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1349 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1350
793b883e
SH		 1351 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1352 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1353
1354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1356 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1357 SPEED_10 ? 7 : 0) |
1358 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1359 SPEED_100 ? 7 : 0) |
1360 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1361 SPEED_1000 ? 7 : 0));
1362 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1363 }
1364
cd28ab6a
SH		 1365 if (netif_msg_link(sky2))
1366 printk(KERN_INFO PFX
1367 "%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n",
1368 sky2->netdev->name, sky2->speed,
1369 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1370 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1371 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1372}
1373
1374static void sky2_link_down(struct sky2_port *sky2)
1375{
1376 struct sky2_hw *hw = sky2->hw;
1377 unsigned port = sky2->port;
1378 u16 reg;
1379
1380 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1381
1382 reg = gma_read16(hw, port, GM_GP_CTRL);
1383 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1384 gma_write16(hw, port, GM_GP_CTRL, reg);
1385 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1386
1387 if (sky2->rx_pause && !sky2->tx_pause) {
1388 /* restore Asymmetric Pause bit */
1389 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1390 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1391 | PHY_M_AN_ASP);
cd28ab6a
SH		 1392 }
1393
1394 sky2_phy_reset(hw, port);
1395
1396 netif_carrier_off(sky2->netdev);
1397 netif_stop_queue(sky2->netdev);
1398
1399 /* Turn on link LED */
1400 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1401
1402 if (netif_msg_link(sky2))
1403 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1404 sky2_phy_init(hw, port);
1405}
1406
793b883e
SH		 1407static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1408{
1409 struct sky2_hw *hw = sky2->hw;
1410 unsigned port = sky2->port;
1411 u16 lpa;
1412
1413 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1414
1415 if (lpa & PHY_M_AN_RF) {
1416 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1417 return -1;
1418 }
1419
1420 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1421 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1422 printk(KERN_ERR PFX "%s: master/slave fault",
1423 sky2->netdev->name);
1424 return -1;
1425 }
1426
1427 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1428 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1429 sky2->netdev->name);
1430 return -1;
1431 }
1432
1433 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1434
1435 sky2->speed = sky2_phy_speed(hw, aux);
1436
1437 /* Pause bits are offset (9..8) */
1438 if (hw->chip_id == CHIP_ID_YUKON_XL)
1439 aux >>= 6;
1440
1441 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1442 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1443
1444 if ((sky2->tx_pause || sky2->rx_pause)
1445 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1447 else
1448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1449
1450 return 0;
1451}
cd28ab6a
SH		 1452
1453/*
1454 * Interrrupt from PHY are handled in tasklet (soft irq)
1455 * because accessing phy registers requires spin wait which might
1456 * cause excess interrupt latency.
1457 */
1458static void sky2_phy_task(unsigned long data)
1459{
793b883e 1460 struct sky2_port *sky2 = (struct sky2_port *)data;
cd28ab6a 1461 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1462 u16 istatus, phystat;
1463
793b883e
SH		 1464 spin_lock(&hw->phy_lock);
1465 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1466 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1467
1468 if (netif_msg_intr(sky2))
1469 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1470 sky2->netdev->name, istatus, phystat);
1471
1472 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1473 if (sky2_autoneg_done(sky2, phystat) == 0)
1474 sky2_link_up(sky2);
1475 goto out;
1476 }
cd28ab6a 1477
793b883e
SH		 1478 if (istatus & PHY_M_IS_LSP_CHANGE)
1479 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1480
793b883e
SH		 1481 if (istatus & PHY_M_IS_DUP_CHANGE)
1482 sky2->duplex =
1483 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1484
793b883e
SH		 1485 if (istatus & PHY_M_IS_LST_CHANGE) {
1486 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1487 sky2_link_up(sky2);
793b883e
SH		 1488 else
1489 sky2_link_down(sky2);
cd28ab6a 1490 }
793b883e
SH		 1491out:
1492 spin_unlock(&hw->phy_lock);
cd28ab6a
SH		 1493
1494 local_irq_disable();
793b883e 1495 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1496 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1497 local_irq_enable();
1498}
1499
1500static void sky2_tx_timeout(struct net_device *dev)
1501{
1502 struct sky2_port *sky2 = netdev_priv(dev);
1503
1504 if (netif_msg_timer(sky2))
1505 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1506
1507 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1508 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1509
1510 sky2_tx_clean(sky2);
1511}
1512
1513static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1514{
6b1a3aef
SH		 1515 struct sky2_port *sky2 = netdev_priv(dev);
1516 struct sky2_hw *hw = sky2->hw;
1517 int err;
1518 u16 ctl, mode;
cd28ab6a
SH		 1519
1520 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1521 return -EINVAL;
1522
6b1a3aef
SH		 1523 if (!netif_running(dev)) {
1524 dev->mtu = new_mtu;
1525 return 0;
1526 }
1527
1528 local_irq_disable();
1529 sky2_write32(hw, B0_IMSK, 0);
1530
1531 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1532 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1533 sky2_rx_stop(sky2);
1534 sky2_rx_clean(sky2);
cd28ab6a
SH		 1535
1536 dev->mtu = new_mtu;
6b1a3aef
SH		 1537 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1538 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1539
1540 if (dev->mtu > ETH_DATA_LEN)
1541 mode |= GM_SMOD_JUMBO_ENA;
1542
1543 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1544
6b1a3aef 1545 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1546
6b1a3aef
SH		 1547 err = sky2_rx_start(sky2);
1548 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1549
1550 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1551 sky2_read32(hw, B0_IMSK);
1552 local_irq_enable();
cd28ab6a
SH		 1553 return err;
1554}
1555
1556/*
1557 * Receive one packet.
1558 * For small packets or errors, just reuse existing skb.
1559 * For larger pakects, get new buffer.
1560 */
d11c13e7 1561static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1562 u16 length, u32 status)
1563{
cd28ab6a 1564 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1565 struct sk_buff *skb = NULL;
d11c13e7 1566 struct net_device *dev;
6b1a3aef 1567 const unsigned int bufsize = rx_size(sky2);
cd28ab6a
SH		 1568
1569 if (unlikely(netif_msg_rx_status(sky2)))
1570 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1571 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1572
793b883e 1573 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
cd28ab6a 1574
d1f13708 1575 if (!(status & GMR_FS_RX_OK) || (status & GMR_FS_ANY_ERR))
cd28ab6a
SH		 1576 goto error;
1577
793b883e 1578 if (length < RX_COPY_THRESHOLD) {
79e57d32
SH		 1579 skb = alloc_skb(length + 2, GFP_ATOMIC);
1580 if (!skb)
793b883e
SH		 1581 goto resubmit;
1582
79e57d32 1583 skb_reserve(skb, 2);
793b883e
SH		 1584 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1585 length, PCI_DMA_FROMDEVICE);
79e57d32 1586 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1587 skb->ip_summed = re->skb->ip_summed;
1588 skb->csum = re->skb->csum;
793b883e
SH		 1589 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1590 length, PCI_DMA_FROMDEVICE);
793b883e 1591 } else {
79e57d32
SH		 1592 struct sk_buff *nskb;
1593
1594 nskb = dev_alloc_skb(bufsize);
793b883e
SH		 1595 if (!nskb)
1596 goto resubmit;
cd28ab6a 1597
793b883e 1598 skb = re->skb;
79e57d32 1599 re->skb = nskb;
793b883e
SH		 1600 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1601 re->maplen, PCI_DMA_FROMDEVICE);
1602 prefetch(skb->data);
cd28ab6a 1603
793b883e 1604 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
79e57d32
SH		 1605 bufsize, PCI_DMA_FROMDEVICE);
1606 re->maplen = bufsize;
793b883e 1607 }
cd28ab6a 1608
79e57d32 1609 skb_put(skb, length);
d11c13e7
SH		 1610 dev = sky2->netdev;
1611 skb->dev = dev;
79e57d32
SH		 1612 skb->protocol = eth_type_trans(skb, dev);
1613 dev->last_rx = jiffies;
1614
793b883e 1615resubmit:
d11c13e7 1616 re->skb->ip_summed = CHECKSUM_NONE;
793b883e 1617 sky2_rx_add(sky2, re);
79e57d32 1618
cd28ab6a
SH		 1619 return skb;
1620
1621error:
793b883e
SH		 1622 if (status & GMR_FS_GOOD_FC)
1623 goto resubmit;
1624
cd28ab6a
SH		 1625 if (netif_msg_rx_err(sky2))
1626 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1627 sky2->netdev->name, status, length);
793b883e
SH		 1628
1629 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1630 sky2->net_stats.rx_length_errors++;
1631 if (status & GMR_FS_FRAGMENT)
1632 sky2->net_stats.rx_frame_errors++;
1633 if (status & GMR_FS_CRC_ERR)
1634 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1635 if (status & GMR_FS_RX_FF_OV)
1636 sky2->net_stats.rx_fifo_errors++;
79e57d32 1637
793b883e 1638 goto resubmit;
cd28ab6a
SH		 1639}
1640
793b883e
SH		 1641/* Transmit ring index in reported status block is encoded as:
1642 *
1643 * | TXS2 | TXA2 | TXS1 | TXA1
1644 */
1645static inline u16 tx_index(u8 port, u32 status, u16 len)
cd28ab6a
SH		 1646{
1647 if (port == 0)
1648 return status & 0xfff;
1649 else
1650 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1651}
1652
1653/*
cd28ab6a
SH		 1654 * Both ports share the same status interrupt, therefore there is only
1655 * one poll routine.
cd28ab6a 1656 */
d11c13e7 1657static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1658{
d11c13e7
SH		 1659 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1660 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1661 unsigned int work_done = 0;
793b883e 1662 u16 hwidx;
cd28ab6a 1663
793b883e 1664 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1665 BUG_ON(hwidx >= STATUS_RING_SIZE);
793b883e
SH		 1666 rmb();
1667 while (hw->st_idx != hwidx && work_done < to_do) {
cd28ab6a 1668 struct sky2_status_le *le = hw->st_le + hw->st_idx;
d11c13e7 1669 struct sky2_port *sky2;
cd28ab6a 1670 struct sk_buff *skb;
cd28ab6a
SH		 1671 u32 status;
1672 u16 length;
1673
d11c13e7 1674 BUG_ON(le->link >= hw->ports);
d1f13708
SH		 1675 if (!hw->dev[le->link])
1676 goto skip;
1677
d11c13e7 1678 sky2 = netdev_priv(hw->dev[le->link]);
cd28ab6a
SH		 1679 status = le32_to_cpu(le->status);
1680 length = le16_to_cpu(le->length);
cd28ab6a 1681
793b883e 1682 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1683 case OP_RXSTAT:
d11c13e7 1684 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1685 if (!skb)
1686 break;
1687#ifdef SKY2_VLAN_TAG_USED
1688 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1689 vlan_hwaccel_receive_skb(skb,
1690 sky2->vlgrp,
1691 be16_to_cpu(sky2->rx_tag));
1692 } else
1693#endif
cd28ab6a 1694 netif_receive_skb(skb);
cd28ab6a
SH		 1695 break;
1696
d1f13708
SH		 1697#ifdef SKY2_VLAN_TAG_USED
1698 case OP_RXVLAN:
1699 sky2->rx_tag = length;
1700 break;
1701
1702 case OP_RXCHKSVLAN:
1703 sky2->rx_tag = length;
1704 /* fall through */
1705#endif
cd28ab6a 1706 case OP_RXCHKS:
d11c13e7
SH		 1707 skb = sky2->rx_ring[sky2->rx_next].skb;
1708 skb->ip_summed = CHECKSUM_HW;
1709 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1710 break;
1711
1712 case OP_TXINDEXLE:
d11c13e7
SH		 1713 sky2_tx_complete(sky2,
1714 tx_index(sky2->port, status, length));
cd28ab6a
SH		 1715 break;
1716
cd28ab6a
SH		 1717 default:
1718 if (net_ratelimit())
793b883e
SH		 1719 printk(KERN_WARNING PFX
1720 "unknown status opcode 0x%x\n",
cd28ab6a
SH		 1721 le->opcode);
1722 break;
1723 }
1724
d1f13708 1725 skip:
793b883e
SH		 1726 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1727 if (hw->st_idx == hwidx) {
1728 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1729 rmb();
1730 }
cd28ab6a
SH		 1731 }
1732
793b883e
SH		 1733 mmiowb();
1734
1735 if (hw->dev[0])
1736 rx_set_put(hw->dev[0]);
1737
1738 if (hw->dev[1])
1739 rx_set_put(hw->dev[1]);
1740
cd28ab6a 1741 *budget -= work_done;
d11c13e7 1742 dev0->quota -= work_done;
cd28ab6a
SH		 1743 if (work_done < to_do) {
1744 /*
1745 * Another chip workaround, need to restart TX timer if status
1746 * LE was handled. WA_DEV_43_418
1747 */
1748 if (is_ec_a1(hw)) {
1749 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1750 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1751 }
1752
1753 hw->intr_mask |= Y2_IS_STAT_BMU;
1754 sky2_write32(hw, B0_IMSK, hw->intr_mask);
793b883e 1755 sky2_read32(hw, B0_IMSK);
d11c13e7 1756 netif_rx_complete(dev0);
cd28ab6a
SH		 1757 }
1758
1759 return work_done >= to_do;
1760
1761}
1762
1763static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1764{
1765 struct net_device *dev = hw->dev[port];
1766
1767 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1768 dev->name, status);
1769
1770 if (status & Y2_IS_PAR_RD1) {
1771 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1772 dev->name);
1773 /* Clear IRQ */
1774 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1775 }
1776
1777 if (status & Y2_IS_PAR_WR1) {
1778 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1779 dev->name);
1780
1781 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1782 }
1783
1784 if (status & Y2_IS_PAR_MAC1) {
1785 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1786 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1787 }
1788
1789 if (status & Y2_IS_PAR_RX1) {
1790 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1791 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1792 }
1793
1794 if (status & Y2_IS_TCP_TXA1) {
1795 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1796 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1797 }
1798}
1799
1800static void sky2_hw_intr(struct sky2_hw *hw)
1801{
1802 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1803
793b883e 1804 if (status & Y2_IS_TIST_OV)
cd28ab6a 1805 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1806
1807 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1808 u16 pci_err;
1809
1810 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1811 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1812 pci_name(hw->pdev), pci_err);
1813
1814 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1815 pci_write_config_word(hw->pdev, PCI_STATUS,
1816 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1817 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1818 }
1819
1820 if (status & Y2_IS_PCI_EXP) {
1821 /* PCI-Express uncorrectable Error occured */
793b883e
SH		 1822 u32 pex_err;
1823
1824 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1825
cd28ab6a
SH		 1826 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1827 pci_name(hw->pdev), pex_err);
1828
1829 /* clear the interrupt */
1830 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1831 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1832 0xffffffffUL);
cd28ab6a
SH		 1833 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1834
1835 if (pex_err & PEX_FATAL_ERRORS) {
1836 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1837 hwmsk &= ~Y2_IS_PCI_EXP;
1838 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1839 }
1840 }
1841
1842 if (status & Y2_HWE_L1_MASK)
1843 sky2_hw_error(hw, 0, status);
1844 status >>= 8;
1845 if (status & Y2_HWE_L1_MASK)
1846 sky2_hw_error(hw, 1, status);
1847}
1848
1849static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1850{
1851 struct net_device *dev = hw->dev[port];
1852 struct sky2_port *sky2 = netdev_priv(dev);
1853 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1854
1855 if (netif_msg_intr(sky2))
1856 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1857 dev->name, status);
1858
1859 if (status & GM_IS_RX_FF_OR) {
1860 ++sky2->net_stats.rx_fifo_errors;
1861 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1862 }
1863
1864 if (status & GM_IS_TX_FF_UR) {
1865 ++sky2->net_stats.tx_fifo_errors;
1866 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1867 }
cd28ab6a
SH		 1868}
1869
1870static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1871{
1872 struct net_device *dev = hw->dev[port];
1873 struct sky2_port *sky2 = netdev_priv(dev);
1874
1875 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1876 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1877 tasklet_schedule(&sky2->phy_task);
1878}
1879
1880static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1881{
1882 struct sky2_hw *hw = dev_id;
1883 u32 status;
1884
1885 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 1886 if (status == 0 || status == ~0)
cd28ab6a
SH		 1887 return IRQ_NONE;
1888
1889 if (status & Y2_IS_HW_ERR)
1890 sky2_hw_intr(hw);
1891
793b883e
SH		 1892 /* Do NAPI for Rx and Tx status */
1893 if ((status & Y2_IS_STAT_BMU) && netif_rx_schedule_test(hw->dev[0])) {
1894 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1895
cd28ab6a
SH		 1896 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1897 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1898 __netif_rx_schedule(hw->dev[0]);
1899 }
1900
793b883e 1901 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 1902 sky2_phy_intr(hw, 0);
1903
1904 if (status & Y2_IS_IRQ_PHY2)
1905 sky2_phy_intr(hw, 1);
1906
1907 if (status & Y2_IS_IRQ_MAC1)
1908 sky2_mac_intr(hw, 0);
1909
1910 if (status & Y2_IS_IRQ_MAC2)
1911 sky2_mac_intr(hw, 1);
1912
cd28ab6a 1913 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 1914
1915 sky2_read32(hw, B0_IMSK);
1916
cd28ab6a
SH		 1917 return IRQ_HANDLED;
1918}
1919
1920#ifdef CONFIG_NET_POLL_CONTROLLER
1921static void sky2_netpoll(struct net_device *dev)
1922{
1923 struct sky2_port *sky2 = netdev_priv(dev);
1924
793b883e 1925 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 1926}
1927#endif
1928
1929/* Chip internal frequency for clock calculations */
1930static inline u32 sky2_khz(const struct sky2_hw *hw)
1931{
793b883e 1932 switch (hw->chip_id) {
cd28ab6a
SH		 1933 case CHIP_ID_YUKON_EC:
1934 return 125000; /* 125 Mhz */
1935 case CHIP_ID_YUKON_FE:
1936 return 100000; /* 100 Mhz */
793b883e 1937 default: /* YUKON_XL */
cd28ab6a
SH		 1938 return 156000; /* 156 Mhz */
1939 }
1940}
1941
1942static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1943{
1944 return sky2_khz(hw) * ms;
1945}
1946
1947static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1948{
793b883e 1949 return (sky2_khz(hw) * us) / 1000;
cd28ab6a
SH		 1950}
1951
1952static int sky2_reset(struct sky2_hw *hw)
1953{
5afa0a9c 1954 u32 ctst;
cd28ab6a
SH		 1955 u16 status;
1956 u8 t8, pmd_type;
1957 int i;
1958
1959 ctst = sky2_read32(hw, B0_CTST);
1960
1961 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1962 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1963 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1964 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1965 pci_name(hw->pdev), hw->chip_id);
1966 return -EOPNOTSUPP;
1967 }
1968
793b883e
SH		 1969 /* ring for status responses */
1970 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1971 &hw->st_dma);
1972 if (!hw->st_le)
1973 return -ENOMEM;
1974
cd28ab6a
SH		 1975 /* disable ASF */
1976 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1977 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1978 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1979 }
1980
1981 /* do a SW reset */
1982 sky2_write8(hw, B0_CTST, CS_RST_SET);
1983 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1984
1985 /* clear PCI errors, if any */
793b883e 1986 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 1987 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1988 pci_write_config_word(hw->pdev, PCI_STATUS,
1989 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1990
1991 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1992
1993 /* clear any PEX errors */
1994 if (is_pciex(hw)) {
793b883e
SH		 1995 u16 lstat;
1996 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1997 0xffffffffUL);
1998 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 1999 }
2000
2001 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2002 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2003
2004 hw->ports = 1;
2005 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2006 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2007 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2008 ++hw->ports;
2009 }
2010 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2011
5afa0a9c 2012 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2013
2014 for (i = 0; i < hw->ports; i++) {
2015 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2016 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2017 }
2018
2019 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2020
793b883e
SH		 2021 /* Clear I2C IRQ noise */
2022 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2023
2024 /* turn off hardware timer (unused) */
2025 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2026 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2027
cd28ab6a
SH		 2028 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2029
793b883e 2030 /* Turn on descriptor polling (every 75us) */
cd28ab6a
SH		 2031 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2032 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2033
2034 /* Turn off receive timestamp */
2035 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2036 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2037
2038 /* enable the Tx Arbiters */
2039 for (i = 0; i < hw->ports; i++)
2040 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2041
2042 /* Initialize ram interface */
2043 for (i = 0; i < hw->ports; i++) {
793b883e 2044 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2045
2046 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2047 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2048 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2049 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2050 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2051 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2052 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2053 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2054 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2055 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2056 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2057 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2058 }
2059
cd28ab6a 2060 if (is_pciex(hw)) {
793b883e
SH		 2061 u16 pctrl;
2062
2063 /* change Max. Read Request Size to 2048 bytes */
2064 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2065 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2066 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2067
2068
cd28ab6a 2069 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e 2070 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
cd28ab6a
SH		 2071 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2072 }
2073
2074 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2075
cd28ab6a
SH		 2076 spin_lock_bh(&hw->phy_lock);
2077 for (i = 0; i < hw->ports; i++)
2078 sky2_phy_reset(hw, i);
2079 spin_unlock_bh(&hw->phy_lock);
2080
cd28ab6a
SH		 2081 memset(hw->st_le, 0, STATUS_LE_BYTES);
2082 hw->st_idx = 0;
2083
2084 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2085 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2086
2087 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2088 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2089
2090 /* Set the list last index */
793b883e 2091 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2092
793b883e
SH		 2093 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2094
2095 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2096 if (is_ec_a1(hw)) {
2097 /* WA for dev. #4.3 */
793b883e 2098 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2099
2100 /* set Status-FIFO watermark */
2101 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2102
2103 /* set Status-FIFO ISR watermark */
793b883e 2104 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
cd28ab6a 2105
cd28ab6a 2106 } else {
cd28ab6a
SH		 2107 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2108
2109 /* set Status-FIFO watermark */
2110 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2111
2112 /* set Status-FIFO ISR watermark */
2113 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2114 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2115
793b883e 2116 else /* WA 4109 */
cd28ab6a
SH		 2117 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2118
2119 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2120 }
2121
793b883e 2122 /* enable status unit */
cd28ab6a
SH		 2123 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2124
2125 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2126 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2127 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2128
2129 return 0;
2130}
2131
2132static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2133{
2134 u32 modes;
2135 if (hw->copper) {
793b883e
SH		 2136 modes = SUPPORTED_10baseT_Half
2137 | SUPPORTED_10baseT_Full
2138 | SUPPORTED_100baseT_Half
2139 | SUPPORTED_100baseT_Full
2140 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2141
2142 if (hw->chip_id != CHIP_ID_YUKON_FE)
2143 modes |= SUPPORTED_1000baseT_Half
793b883e 2144 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2145 } else
2146 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2147 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2148 return modes;
2149}
2150
793b883e 2151static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2152{
2153 struct sky2_port *sky2 = netdev_priv(dev);
2154 struct sky2_hw *hw = sky2->hw;
2155
2156 ecmd->transceiver = XCVR_INTERNAL;
2157 ecmd->supported = sky2_supported_modes(hw);
2158 ecmd->phy_address = PHY_ADDR_MARV;
2159 if (hw->copper) {
2160 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2161 | SUPPORTED_10baseT_Full
2162 | SUPPORTED_100baseT_Half
2163 | SUPPORTED_100baseT_Full
2164 | SUPPORTED_1000baseT_Half
2165 | SUPPORTED_1000baseT_Full
2166 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2167 ecmd->port = PORT_TP;
2168 } else
2169 ecmd->port = PORT_FIBRE;
2170
2171 ecmd->advertising = sky2->advertising;
2172 ecmd->autoneg = sky2->autoneg;
2173 ecmd->speed = sky2->speed;
2174 ecmd->duplex = sky2->duplex;
2175 return 0;
2176}
2177
2178static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2179{
2180 struct sky2_port *sky2 = netdev_priv(dev);
2181 const struct sky2_hw *hw = sky2->hw;
2182 u32 supported = sky2_supported_modes(hw);
2183
2184 if (ecmd->autoneg == AUTONEG_ENABLE) {
2185 ecmd->advertising = supported;
2186 sky2->duplex = -1;
2187 sky2->speed = -1;
2188 } else {
2189 u32 setting;
2190
793b883e 2191 switch (ecmd->speed) {
cd28ab6a
SH		 2192 case SPEED_1000:
2193 if (ecmd->duplex == DUPLEX_FULL)
2194 setting = SUPPORTED_1000baseT_Full;
2195 else if (ecmd->duplex == DUPLEX_HALF)
2196 setting = SUPPORTED_1000baseT_Half;
2197 else
2198 return -EINVAL;
2199 break;
2200 case SPEED_100:
2201 if (ecmd->duplex == DUPLEX_FULL)
2202 setting = SUPPORTED_100baseT_Full;
2203 else if (ecmd->duplex == DUPLEX_HALF)
2204 setting = SUPPORTED_100baseT_Half;
2205 else
2206 return -EINVAL;
2207 break;
2208
2209 case SPEED_10:
2210 if (ecmd->duplex == DUPLEX_FULL)
2211 setting = SUPPORTED_10baseT_Full;
2212 else if (ecmd->duplex == DUPLEX_HALF)
2213 setting = SUPPORTED_10baseT_Half;
2214 else
2215 return -EINVAL;
2216 break;
2217 default:
2218 return -EINVAL;
2219 }
2220
2221 if ((setting & supported) == 0)
2222 return -EINVAL;
2223
2224 sky2->speed = ecmd->speed;
2225 sky2->duplex = ecmd->duplex;
2226 }
2227
2228 sky2->autoneg = ecmd->autoneg;
2229 sky2->advertising = ecmd->advertising;
2230
2231 if (netif_running(dev)) {
2232 sky2_down(dev);
2233 sky2_up(dev);
2234 }
2235
2236 return 0;
2237}
2238
2239static void sky2_get_drvinfo(struct net_device *dev,
2240 struct ethtool_drvinfo *info)
2241{
2242 struct sky2_port *sky2 = netdev_priv(dev);
2243
2244 strcpy(info->driver, DRV_NAME);
2245 strcpy(info->version, DRV_VERSION);
2246 strcpy(info->fw_version, "N/A");
2247 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2248}
2249
2250static const struct sky2_stat {
793b883e
SH		 2251 char name[ETH_GSTRING_LEN];
2252 u16 offset;
cd28ab6a
SH		 2253} sky2_stats[] = {
2254 { "tx_bytes", GM_TXO_OK_HI },
2255 { "rx_bytes", GM_RXO_OK_HI },
2256 { "tx_broadcast", GM_TXF_BC_OK },
2257 { "rx_broadcast", GM_RXF_BC_OK },
2258 { "tx_multicast", GM_TXF_MC_OK },
2259 { "rx_multicast", GM_RXF_MC_OK },
2260 { "tx_unicast", GM_TXF_UC_OK },
2261 { "rx_unicast", GM_RXF_UC_OK },
2262 { "tx_mac_pause", GM_TXF_MPAUSE },
2263 { "rx_mac_pause", GM_RXF_MPAUSE },
2264 { "collisions", GM_TXF_SNG_COL },
2265 { "late_collision",GM_TXF_LAT_COL },
2266 { "aborted", GM_TXF_ABO_COL },
2267 { "multi_collisions", GM_TXF_MUL_COL },
2268 { "fifo_underrun", GM_TXE_FIFO_UR },
2269 { "fifo_overflow", GM_RXE_FIFO_OV },
2270 { "rx_toolong", GM_RXF_LNG_ERR },
2271 { "rx_jabber", GM_RXF_JAB_PKT },
2272 { "rx_runt", GM_RXE_FRAG },
2273 { "rx_too_long", GM_RXF_LNG_ERR },
2274 { "rx_fcs_error", GM_RXF_FCS_ERR },
2275};
2276
cd28ab6a
SH		 2277static u32 sky2_get_rx_csum(struct net_device *dev)
2278{
2279 struct sky2_port *sky2 = netdev_priv(dev);
2280
2281 return sky2->rx_csum;
2282}
2283
2284static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2285{
2286 struct sky2_port *sky2 = netdev_priv(dev);
2287
2288 sky2->rx_csum = data;
793b883e 2289
cd28ab6a
SH		 2290 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2291 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2292
2293 return 0;
2294}
2295
2296static u32 sky2_get_msglevel(struct net_device *netdev)
2297{
2298 struct sky2_port *sky2 = netdev_priv(netdev);
2299 return sky2->msg_enable;
2300}
2301
9a7ae0a9
SH		 2302static int sky2_nway_reset(struct net_device *dev)
2303{
2304 struct sky2_port *sky2 = netdev_priv(dev);
2305 struct sky2_hw *hw = sky2->hw;
2306
2307 if (sky2->autoneg != AUTONEG_ENABLE)
2308 return -EINVAL;
2309
2310 netif_stop_queue(dev);
2311
2312 spin_lock_irq(&hw->phy_lock);
2313 sky2_phy_reset(hw, sky2->port);
2314 sky2_phy_init(hw, sky2->port);
2315 spin_unlock_irq(&hw->phy_lock);
2316
2317 return 0;
2318}
2319
793b883e 2320static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2321{
2322 struct sky2_hw *hw = sky2->hw;
2323 unsigned port = sky2->port;
2324 int i;
2325
2326 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2327 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2328 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2329 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2330
793b883e 2331 for (i = 2; i < count; i++)
cd28ab6a
SH		 2332 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2333}
2334
cd28ab6a
SH		 2335static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2336{
2337 struct sky2_port *sky2 = netdev_priv(netdev);
2338 sky2->msg_enable = value;
2339}
2340
2341static int sky2_get_stats_count(struct net_device *dev)
2342{
2343 return ARRAY_SIZE(sky2_stats);
2344}
2345
2346static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2347 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2348{
2349 struct sky2_port *sky2 = netdev_priv(dev);
2350
793b883e 2351 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2352}
2353
793b883e 2354static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2355{
2356 int i;
2357
2358 switch (stringset) {
2359 case ETH_SS_STATS:
2360 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2361 memcpy(data + i * ETH_GSTRING_LEN,
2362 sky2_stats[i].name, ETH_GSTRING_LEN);
2363 break;
2364 }
2365}
2366
2367/* Use hardware MIB variables for critical path statistics and
2368 * transmit feedback not reported at interrupt.
2369 * Other errors are accounted for in interrupt handler.
2370 */
2371static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2372{
2373 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2374 u64 data[13];
cd28ab6a 2375
793b883e 2376 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2377
2378 sky2->net_stats.tx_bytes = data[0];
2379 sky2->net_stats.rx_bytes = data[1];
2380 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2381 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2382 sky2->net_stats.multicast = data[5] + data[7];
2383 sky2->net_stats.collisions = data[10];
2384 sky2->net_stats.tx_aborted_errors = data[12];
2385
2386 return &sky2->net_stats;
2387}
2388
2389static int sky2_set_mac_address(struct net_device *dev, void *p)
2390{
2391 struct sky2_port *sky2 = netdev_priv(dev);
2392 struct sockaddr *addr = p;
2393 int err = 0;
2394
2395 if (!is_valid_ether_addr(addr->sa_data))
2396 return -EADDRNOTAVAIL;
2397
2398 sky2_down(dev);
2399 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2400 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2401 dev->dev_addr, ETH_ALEN);
793b883e 2402 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a
SH		 2403 dev->dev_addr, ETH_ALEN);
2404 if (dev->flags & IFF_UP)
2405 err = sky2_up(dev);
2406 return err;
2407}
2408
2409static void sky2_set_multicast(struct net_device *dev)
2410{
2411 struct sky2_port *sky2 = netdev_priv(dev);
2412 struct sky2_hw *hw = sky2->hw;
2413 unsigned port = sky2->port;
2414 struct dev_mc_list *list = dev->mc_list;
2415 u16 reg;
2416 u8 filter[8];
2417
2418 memset(filter, 0, sizeof(filter));
2419
2420 reg = gma_read16(hw, port, GM_RX_CTRL);
2421 reg |= GM_RXCR_UCF_ENA;
2422
793b883e 2423 if (dev->flags & IFF_PROMISC) /* promiscious */
cd28ab6a 2424 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2425 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2426 memset(filter, 0xff, sizeof(filter));
793b883e 2427 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2428 reg &= ~GM_RXCR_MCF_ENA;
2429 else {
2430 int i;
2431 reg |= GM_RXCR_MCF_ENA;
2432
2433 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2434 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2435 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2436 }
2437 }
2438
cd28ab6a 2439 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2440 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2441 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2442 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2443 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2444 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2445 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2446 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2447
2448 gma_write16(hw, port, GM_RX_CTRL, reg);
2449}
2450
2451/* Can have one global because blinking is controlled by
2452 * ethtool and that is always under RTNL mutex
2453 */
2454static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2455{
793b883e
SH		 2456 u16 pg;
2457
cd28ab6a 2458 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2459 switch (hw->chip_id) {
2460 case CHIP_ID_YUKON_XL:
2461 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2462 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2463 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2464 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2465 PHY_M_LEDC_INIT_CTRL(7) |
2466 PHY_M_LEDC_STA1_CTRL(7) |
2467 PHY_M_LEDC_STA0_CTRL(7))
2468 : 0);
2469
2470 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2471 break;
2472
2473 default:
2474 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2475 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2476 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2477 PHY_M_LED_MO_10(MO_LED_ON) |
2478 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2479 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2480 PHY_M_LED_MO_RX(MO_LED_ON)
2481 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2482 PHY_M_LED_MO_10(MO_LED_OFF) |
2483 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2484 PHY_M_LED_MO_1000(MO_LED_OFF) |
2485 PHY_M_LED_MO_RX(MO_LED_OFF));
2486
793b883e 2487 }
cd28ab6a
SH		 2488 spin_unlock_bh(&hw->phy_lock);
2489}
2490
2491/* blink LED's for finding board */
2492static int sky2_phys_id(struct net_device *dev, u32 data)
2493{
2494 struct sky2_port *sky2 = netdev_priv(dev);
2495 struct sky2_hw *hw = sky2->hw;
2496 unsigned port = sky2->port;
793b883e 2497 u16 ledctrl, ledover = 0;
cd28ab6a
SH		 2498 long ms;
2499 int onoff = 1;
2500
793b883e 2501 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2502 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2503 else
2504 ms = data * 1000;
2505
2506 /* save initial values */
2507 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2508 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2509 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2511 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2513 } else {
2514 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2515 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2516 }
cd28ab6a
SH		 2517 spin_unlock_bh(&hw->phy_lock);
2518
2519 while (ms > 0) {
2520 sky2_led(hw, port, onoff);
2521 onoff = !onoff;
2522
2523 if (msleep_interruptible(250))
2524 break; /* interrupted */
2525 ms -= 250;
2526 }
2527
2528 /* resume regularly scheduled programming */
2529 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2530 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2531 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2533 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2535 } else {
2536 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2537 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2538 }
cd28ab6a
SH		 2539 spin_unlock_bh(&hw->phy_lock);
2540
2541 return 0;
2542}
2543
2544static void sky2_get_pauseparam(struct net_device *dev,
2545 struct ethtool_pauseparam *ecmd)
2546{
2547 struct sky2_port *sky2 = netdev_priv(dev);
2548
2549 ecmd->tx_pause = sky2->tx_pause;
2550 ecmd->rx_pause = sky2->rx_pause;
2551 ecmd->autoneg = sky2->autoneg;
2552}
2553
2554static int sky2_set_pauseparam(struct net_device *dev,
2555 struct ethtool_pauseparam *ecmd)
2556{
2557 struct sky2_port *sky2 = netdev_priv(dev);
2558 int err = 0;
2559
2560 sky2->autoneg = ecmd->autoneg;
2561 sky2->tx_pause = ecmd->tx_pause != 0;
2562 sky2->rx_pause = ecmd->rx_pause != 0;
2563
2564 if (netif_running(dev)) {
2565 sky2_down(dev);
2566 err = sky2_up(dev);
2567 }
2568
2569 return err;
2570}
2571
2572#ifdef CONFIG_PM
2573static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2574{
2575 struct sky2_port *sky2 = netdev_priv(dev);
2576
2577 wol->supported = WAKE_MAGIC;
2578 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2579}
2580
2581static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2582{
2583 struct sky2_port *sky2 = netdev_priv(dev);
2584 struct sky2_hw *hw = sky2->hw;
2585
2586 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2587 return -EOPNOTSUPP;
2588
2589 sky2->wol = wol->wolopts == WAKE_MAGIC;
2590
2591 if (sky2->wol) {
2592 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2593
2594 sky2_write16(hw, WOL_CTRL_STAT,
2595 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2596 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2597 } else
2598 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2599
2600 return 0;
2601}
2602#endif
2603
793b883e
SH		 2604static void sky2_get_ringparam(struct net_device *dev,
2605 struct ethtool_ringparam *ering)
2606{
2607 struct sky2_port *sky2 = netdev_priv(dev);
2608
2609 ering->rx_max_pending = RX_MAX_PENDING;
2610 ering->rx_mini_max_pending = 0;
2611 ering->rx_jumbo_max_pending = 0;
2612 ering->tx_max_pending = TX_RING_SIZE - 1;
2613
2614 ering->rx_pending = sky2->rx_pending;
2615 ering->rx_mini_pending = 0;
2616 ering->rx_jumbo_pending = 0;
2617 ering->tx_pending = sky2->tx_pending;
2618}
2619
2620static int sky2_set_ringparam(struct net_device *dev,
2621 struct ethtool_ringparam *ering)
2622{
2623 struct sky2_port *sky2 = netdev_priv(dev);
2624 int err = 0;
2625
2626 if (ering->rx_pending > RX_MAX_PENDING ||
2627 ering->rx_pending < 8 ||
2628 ering->tx_pending < MAX_SKB_TX_LE ||
2629 ering->tx_pending > TX_RING_SIZE - 1)
2630 return -EINVAL;
2631
2632 if (netif_running(dev))
2633 sky2_down(dev);
2634
2635 sky2->rx_pending = ering->rx_pending;
2636 sky2->tx_pending = ering->tx_pending;
2637
2638 if (netif_running(dev))
2639 err = sky2_up(dev);
2640
2641 return err;
2642}
2643
793b883e
SH		 2644static int sky2_get_regs_len(struct net_device *dev)
2645{
6e4cbb34 2646 return 0x4000;
793b883e
SH		 2647}
2648
2649/*
2650 * Returns copy of control register region
6e4cbb34 2651 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2652 */
2653static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2654 void *p)
2655{
2656 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2657 const void __iomem *io = sky2->hw->regs;
793b883e 2658
6e4cbb34 2659 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2660 regs->version = 1;
6e4cbb34 2661 memset(p, 0, regs->len);
793b883e 2662
6e4cbb34
SH		 2663 memcpy_fromio(p, io, B3_RAM_ADDR);
2664
2665 memcpy_fromio(p + B3_RI_WTO_R1,
2666 io + B3_RI_WTO_R1,
2667 regs->len - B3_RI_WTO_R1);
793b883e 2668}
cd28ab6a
SH		 2669
2670static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2671 .get_settings = sky2_get_settings,
2672 .set_settings = sky2_set_settings,
2673 .get_drvinfo = sky2_get_drvinfo,
2674 .get_msglevel = sky2_get_msglevel,
2675 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2676 .nway_reset = sky2_nway_reset,
793b883e
SH		 2677 .get_regs_len = sky2_get_regs_len,
2678 .get_regs = sky2_get_regs,
2679 .get_link = ethtool_op_get_link,
2680 .get_sg = ethtool_op_get_sg,
2681 .set_sg = ethtool_op_set_sg,
2682 .get_tx_csum = ethtool_op_get_tx_csum,
2683 .set_tx_csum = ethtool_op_set_tx_csum,
2684 .get_tso = ethtool_op_get_tso,
2685 .set_tso = ethtool_op_set_tso,
2686 .get_rx_csum = sky2_get_rx_csum,
2687 .set_rx_csum = sky2_set_rx_csum,
2688 .get_strings = sky2_get_strings,
2689 .get_ringparam = sky2_get_ringparam,
2690 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2691 .get_pauseparam = sky2_get_pauseparam,
2692 .set_pauseparam = sky2_set_pauseparam,
2693#ifdef CONFIG_PM
793b883e
SH		 2694 .get_wol = sky2_get_wol,
2695 .set_wol = sky2_set_wol,
cd28ab6a 2696#endif
793b883e 2697 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2698 .get_stats_count = sky2_get_stats_count,
2699 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2700 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2701};
2702
2703/* Initialize network device */
2704static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2705 unsigned port, int highmem)
2706{
2707 struct sky2_port *sky2;
2708 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2709
2710 if (!dev) {
2711 printk(KERN_ERR "sky2 etherdev alloc failed");
2712 return NULL;
2713 }
2714
2715 SET_MODULE_OWNER(dev);
2716 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2717 dev->open = sky2_up;
2718 dev->stop = sky2_down;
2719 dev->hard_start_xmit = sky2_xmit_frame;
2720 dev->get_stats = sky2_get_stats;
2721 dev->set_multicast_list = sky2_set_multicast;
2722 dev->set_mac_address = sky2_set_mac_address;
2723 dev->change_mtu = sky2_change_mtu;
2724 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2725 dev->tx_timeout = sky2_tx_timeout;
2726 dev->watchdog_timeo = TX_WATCHDOG;
2727 if (port == 0)
2728 dev->poll = sky2_poll;
2729 dev->weight = NAPI_WEIGHT;
2730#ifdef CONFIG_NET_POLL_CONTROLLER
2731 dev->poll_controller = sky2_netpoll;
2732#endif
cd28ab6a
SH		 2733
2734 sky2 = netdev_priv(dev);
2735 sky2->netdev = dev;
2736 sky2->hw = hw;
2737 sky2->msg_enable = netif_msg_init(debug, default_msg);
2738
2739 spin_lock_init(&sky2->tx_lock);
2740 /* Auto speed and flow control */
2741 sky2->autoneg = AUTONEG_ENABLE;
2742 sky2->tx_pause = 0;
2743 sky2->rx_pause = 1;
2744 sky2->duplex = -1;
2745 sky2->speed = -1;
2746 sky2->advertising = sky2_supported_modes(hw);
2747 sky2->rx_csum = 1;
793b883e
SH		 2748 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2749 sky2->tx_pending = TX_DEF_PENDING;
2750 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
cd28ab6a
SH		 2751
2752 hw->dev[port] = dev;
2753
2754 sky2->port = port;
2755
793b883e 2756 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
cd28ab6a
SH		 2757 if (highmem)
2758 dev->features |= NETIF_F_HIGHDMA;
793b883e 2759 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2760
d1f13708
SH		 2761#ifdef SKY2_VLAN_TAG_USED
2762 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2763 dev->vlan_rx_register = sky2_vlan_rx_register;
2764 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2765#endif
2766
cd28ab6a 2767 /* read the mac address */
793b883e 2768 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 2769 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 2770
2771 /* device is off until link detection */
2772 netif_carrier_off(dev);
2773 netif_stop_queue(dev);
2774
2775 return dev;
2776}
2777
2778static inline void sky2_show_addr(struct net_device *dev)
2779{
2780 const struct sky2_port *sky2 = netdev_priv(dev);
2781
2782 if (netif_msg_probe(sky2))
2783 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2784 dev->name,
2785 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2786 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2787}
2788
2789static int __devinit sky2_probe(struct pci_dev *pdev,
2790 const struct pci_device_id *ent)
2791{
793b883e 2792 struct net_device *dev, *dev1 = NULL;
cd28ab6a 2793 struct sky2_hw *hw;
5afa0a9c 2794 int err, pm_cap, using_dac = 0;
cd28ab6a 2795
793b883e
SH		 2796 err = pci_enable_device(pdev);
2797 if (err) {
cd28ab6a
SH		 2798 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2799 pci_name(pdev));
2800 goto err_out;
2801 }
2802
793b883e
SH		 2803 err = pci_request_regions(pdev, DRV_NAME);
2804 if (err) {
cd28ab6a
SH		 2805 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2806 pci_name(pdev));
793b883e 2807 goto err_out;
cd28ab6a
SH		 2808 }
2809
2810 pci_set_master(pdev);
2811
5afa0a9c
SH		 2812 /* Find power-management capability. */
2813 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2814 if (pm_cap == 0) {
2815 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2816 "aborting.\n");
2817 err = -EIO;
2818 goto err_out_free_regions;
2819 }
2820
cd28ab6a
SH		 2821 if (sizeof(dma_addr_t) > sizeof(u32)) {
2822 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2823 if (!err)
2824 using_dac = 1;
2825 }
2826
2827 if (!using_dac) {
2828 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2829 if (err) {
2830 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2831 pci_name(pdev));
2832 goto err_out_free_regions;
2833 }
2834 }
cd28ab6a
SH		 2835#ifdef __BIG_ENDIAN
2836 /* byte swap decriptors in hardware */
2837 {
2838 u32 reg;
2839
2840 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
2841 reg |= PCI_REV_DESC;
2842 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2843 }
2844#endif
2845
2846 err = -ENOMEM;
2847 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2848 if (!hw) {
2849 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2850 pci_name(pdev));
2851 goto err_out_free_regions;
2852 }
2853
2854 memset(hw, 0, sizeof(*hw));
2855 hw->pdev = pdev;
2856 spin_lock_init(&hw->phy_lock);
2857
2858 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2859 if (!hw->regs) {
2860 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2861 pci_name(pdev));
2862 goto err_out_free_hw;
2863 }
5afa0a9c 2864 hw->pm_cap = pm_cap;
cd28ab6a 2865
cd28ab6a
SH		 2866 err = sky2_reset(hw);
2867 if (err)
793b883e 2868 goto err_out_iounmap;
cd28ab6a 2869
793b883e 2870 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
cd28ab6a 2871 pci_resource_start(pdev, 0), pdev->irq,
793b883e
SH		 2872 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2873 hw->chip_id, hw->chip_rev);
cd28ab6a 2874
793b883e
SH		 2875 dev = sky2_init_netdev(hw, 0, using_dac);
2876 if (!dev)
cd28ab6a
SH		 2877 goto err_out_free_pci;
2878
793b883e
SH		 2879 err = register_netdev(dev);
2880 if (err) {
cd28ab6a
SH		 2881 printk(KERN_ERR PFX "%s: cannot register net device\n",
2882 pci_name(pdev));
2883 goto err_out_free_netdev;
2884 }
2885
2886 sky2_show_addr(dev);
2887
2888 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2889 if (register_netdev(dev1) == 0)
2890 sky2_show_addr(dev1);
2891 else {
2892 /* Failure to register second port need not be fatal */
793b883e
SH		 2893 printk(KERN_WARNING PFX
2894 "register of second port failed\n");
cd28ab6a
SH		 2895 hw->dev[1] = NULL;
2896 free_netdev(dev1);
2897 }
2898 }
2899
793b883e
SH		 2900 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2901 if (err) {
2902 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2903 pci_name(pdev), pdev->irq);
2904 goto err_out_unregister;
2905 }
2906
2907 hw->intr_mask = Y2_IS_BASE;
2908 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2909
2910 pci_set_drvdata(pdev, hw);
2911
cd28ab6a
SH		 2912 return 0;
2913
793b883e
SH		 2914err_out_unregister:
2915 if (dev1) {
2916 unregister_netdev(dev1);
2917 free_netdev(dev1);
2918 }
2919 unregister_netdev(dev);
cd28ab6a
SH		 2920err_out_free_netdev:
2921 free_netdev(dev);
cd28ab6a 2922err_out_free_pci:
793b883e 2923 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 2924 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2925err_out_iounmap:
2926 iounmap(hw->regs);
2927err_out_free_hw:
2928 kfree(hw);
2929err_out_free_regions:
2930 pci_release_regions(pdev);
cd28ab6a 2931 pci_disable_device(pdev);
cd28ab6a
SH		 2932err_out:
2933 return err;
2934}
2935
2936static void __devexit sky2_remove(struct pci_dev *pdev)
2937{
793b883e 2938 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 2939 struct net_device *dev0, *dev1;
2940
793b883e 2941 if (!hw)
cd28ab6a
SH		 2942 return;
2943
cd28ab6a 2944 dev0 = hw->dev[0];
793b883e
SH		 2945 dev1 = hw->dev[1];
2946 if (dev1)
2947 unregister_netdev(dev1);
cd28ab6a
SH		 2948 unregister_netdev(dev0);
2949
793b883e 2950 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 2951 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 2952 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 2953 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 2954 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 2955
2956 free_irq(pdev->irq, hw);
793b883e 2957 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 2958 pci_release_regions(pdev);
2959 pci_disable_device(pdev);
793b883e 2960
cd28ab6a
SH		 2961 if (dev1)
2962 free_netdev(dev1);
2963 free_netdev(dev0);
2964 iounmap(hw->regs);
2965 kfree(hw);
5afa0a9c 2966
cd28ab6a
SH		 2967 pci_set_drvdata(pdev, NULL);
2968}
2969
2970#ifdef CONFIG_PM
2971static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2972{
793b883e 2973 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 2974 int i;
cd28ab6a
SH		 2975
2976 for (i = 0; i < 2; i++) {
2977 struct net_device *dev = hw->dev[i];
2978
2979 if (dev) {
5afa0a9c
SH		 2980 if (!netif_running(dev))
2981 continue;
2982
2983 sky2_down(dev);
cd28ab6a 2984 netif_device_detach(dev);
cd28ab6a
SH		 2985 }
2986 }
2987
5afa0a9c 2988 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 2989}
2990
2991static int sky2_resume(struct pci_dev *pdev)
2992{
793b883e 2993 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 2994 int i;
2995
cd28ab6a
SH		 2996 pci_restore_state(pdev);
2997 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 2998 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2999
3000 sky2_reset(hw);
3001
3002 for (i = 0; i < 2; i++) {
3003 struct net_device *dev = hw->dev[i];
3004 if (dev) {
5afa0a9c
SH		 3005 if (netif_running(dev)) {
3006 netif_device_attach(dev);
cd28ab6a 3007 sky2_up(dev);
5afa0a9c 3008 }
cd28ab6a
SH		 3009 }
3010 }
3011 return 0;
3012}
3013#endif
3014
3015static struct pci_driver sky2_driver = {
793b883e
SH		 3016 .name = DRV_NAME,
3017 .id_table = sky2_id_table,
3018 .probe = sky2_probe,
3019 .remove = __devexit_p(sky2_remove),
cd28ab6a 3020#ifdef CONFIG_PM
793b883e
SH		 3021 .suspend = sky2_suspend,
3022 .resume = sky2_resume,
cd28ab6a
SH		 3023#endif
3024};
3025
3026static int __init sky2_init_module(void)
3027{
cd28ab6a
SH		 3028 return pci_module_init(&sky2_driver);
3029}
3030
3031static void __exit sky2_cleanup_module(void)
3032{
3033 pci_unregister_driver(&sky2_driver);
3034}
3035
3036module_init(sky2_init_module);
3037module_exit(sky2_cleanup_module);
3038
3039MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3040MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3041MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)