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sky2: workarounds for Yukon-2 supreme
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
0c3f450b 53#define DRV_VERSION "1.25"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe 67/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 143 { 0 }
144};
793b883e 145
cd28ab6a
SH		 146MODULE_DEVICE_TABLE(pci, sky2_id_table);
147
148/* Avoid conditionals by using array */
149static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
150static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 151static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 152
d1b139c0
SH		 153static void sky2_set_multicast(struct net_device *dev);
154
af043aa5 155/* Access to PHY via serial interconnect */
ef743d33 156static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 157{
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (ctrl == 0xffff)
167 goto io_error;
168
169 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 170 return 0;
af043aa5
SH		 171
172 udelay(10);
cd28ab6a 173 }
ef743d33 174
af043aa5 175 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 176 return -ETIMEDOUT;
af043aa5
SH		 177
178io_error:
179 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 return -EIO;
cd28ab6a
SH		 181}
182
ef743d33 183static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 184{
185 int i;
186
793b883e 187 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 188 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189
190 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 191 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl == 0xffff)
193 goto io_error;
194
195 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 196 *val = gma_read16(hw, port, GM_SMI_DATA);
197 return 0;
198 }
199
af043aa5 200 udelay(10);
cd28ab6a
SH		 201 }
202
af043aa5 203 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 204 return -ETIMEDOUT;
af043aa5
SH		 205io_error:
206 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 return -EIO;
ef743d33
SH		 208}
209
af043aa5 210static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 211{
212 u16 v;
af043aa5 213 __gm_phy_read(hw, port, reg, &v);
ef743d33 214 return v;
cd28ab6a
SH		 215}
216
5afa0a9c 217
ae306cca
SH		 218static void sky2_power_on(struct sky2_hw *hw)
219{
220 /* switch power to VCC (WA for VAUX problem) */
221 sky2_write8(hw, B0_POWER_CTRL,
222 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 223
ae306cca
SH		 224 /* disable Core Clock Division, */
225 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 226
ae306cca
SH		 227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
228 /* enable bits are inverted */
229 sky2_write8(hw, B2_Y2_CLK_GATE,
230 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
231 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
232 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 else
234 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 235
ea76e635 236 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 237 u32 reg;
5afa0a9c 238
b32f40c4 239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 240
b32f40c4 241 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 242 /* set all bits to 0 except bits 15..12 and 8 */
243 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 244 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 245
b32f40c4 246 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 247 /* set all bits to 0 except bits 28 & 27 */
248 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 249 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 250
b32f40c4 251 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 252
253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
254 reg = sky2_read32(hw, B2_GP_IO);
255 reg |= GLB_GPIO_STAT_RACE_DIS;
256 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 257
258 sky2_read32(hw, B2_GP_IO);
5afa0a9c 259 }
10547ae2
SH		 260
261 /* Turn on "driver loaded" LED */
262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 263}
5afa0a9c 264
ae306cca
SH		 265static void sky2_power_aux(struct sky2_hw *hw)
266{
267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
268 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 else
270 /* enable bits are inverted */
271 sky2_write8(hw, B2_Y2_CLK_GATE,
272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275
c23ddf8f
SH		 276 /* switch power to VAUX if supported and PME from D3cold */
277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
278 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 282
283 /* turn off "driver loaded LED" */
284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 285}
286
d3bcfbeb 287static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 288{
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 293
cd28ab6a
SH		 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302}
303
16ad91e1
SH		 304/* flow control to advertise bits */
305static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310};
311
312/* flow control to advertise bits when using 1000BaseX */
313static const u16 fiber_fc_adv[] = {
df3fe1f3 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 318};
319
320/* flow control to GMA disable bits */
321static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326};
327
328
cd28ab6a
SH		 329static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330{
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 333
0ea065e5 334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 339 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
53419c68 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 343 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 344 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
53419c68
SH		 347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 354 if (sky2_is_copper(hw)) {
05745c4a 355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
cd28ab6a
SH		 368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
53419c68 375 /* downshift on PHY 88E1112 and 88E1149 is changed */
0ea065e5 376 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
ea76e635 377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 378 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
cd28ab6a
SH		 383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 388 }
cd28ab6a 389
b89165f2
SH		 390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
ea76e635 393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 395
b89165f2
SH		 396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 411 }
b89165f2
SH		 412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 414 }
415
7800fddc 416 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
2eaba1a2 419 reg = 0;
cd28ab6a 420
0ea065e5 421 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 422 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
709c6e7b 435
b89165f2
SH		 436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 441 }
cd28ab6a
SH		 442
443 /* Restart Auto-negotiation */
444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 } else {
446 /* forced speed/duplex settings */
447 ct1000 = PHY_M_1000C_MSE;
448
0ea065e5
SH		 449 /* Disable auto update for duplex flow control and duplex */
450 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 451
452 switch (sky2->speed) {
453 case SPEED_1000:
454 ctrl |= PHY_CT_SP1000;
2eaba1a2 455 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 456 break;
457 case SPEED_100:
458 ctrl |= PHY_CT_SP100;
2eaba1a2 459 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 460 break;
461 }
462
2eaba1a2
SH		 463 if (sky2->duplex == DUPLEX_FULL) {
464 reg |= GM_GPCR_DUP_FULL;
465 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 466 } else if (sky2->speed < SPEED_1000)
467 sky2->flow_mode = FC_NONE;
0ea065e5 468 }
2eaba1a2 469
0ea065e5
SH		 470 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
471 if (sky2_is_copper(hw))
472 adv |= copper_fc_adv[sky2->flow_mode];
473 else
474 adv |= fiber_fc_adv[sky2->flow_mode];
475 } else {
476 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 477 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 478
479 /* Forward pause packets to GMAC? */
16ad91e1 480 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
482 else
483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 484 }
485
2eaba1a2
SH		 486 gma_write16(hw, port, GM_GP_CTRL, reg);
487
05745c4a 488 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 489 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
490
491 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
493
494 /* Setup Phy LED's */
495 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
496 ledover = 0;
497
498 switch (hw->chip_id) {
499 case CHIP_ID_YUKON_FE:
500 /* on 88E3082 these bits are at 11..9 (shifted left) */
501 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
502
503 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
504
505 /* delete ACT LED control bits */
506 ctrl &= ~PHY_M_FELP_LED1_MSK;
507 /* change ACT LED control to blink mode */
508 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
509 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
510 break;
511
05745c4a
SH		 512 case CHIP_ID_YUKON_FE_P:
513 /* Enable Link Partner Next Page */
514 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
515 ctrl |= PHY_M_PC_ENA_LIP_NP;
516
517 /* disable Energy Detect and enable scrambler */
518 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
519 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
520
521 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
522 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
523 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
524 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
525
526 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
527 break;
528
cd28ab6a 529 case CHIP_ID_YUKON_XL:
793b883e 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 531
532 /* select page 3 to access LED control register */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
534
535 /* set LED Function Control register */
ed6d32c7
SH		 536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
537 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
538 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
539 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
540 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 541
542 /* set Polarity Control register */
543 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 544 (PHY_M_POLC_LS1_P_MIX(4) |
545 PHY_M_POLC_IS0_P_MIX(4) |
546 PHY_M_POLC_LOS_CTRL(2) |
547 PHY_M_POLC_INIT_CTRL(2) |
548 PHY_M_POLC_STA1_CTRL(2) |
549 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 550
551 /* restore page register */
793b883e 552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 553 break;
93745494 554
ed6d32c7 555 case CHIP_ID_YUKON_EC_U:
93745494 556 case CHIP_ID_YUKON_EX:
ed4d4161 557 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 558 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
559
560 /* select page 3 to access LED control register */
561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
562
563 /* set LED Function Control register */
564 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
565 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
566 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
567 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
568 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
569
570 /* set Blink Rate in LED Timer Control Register */
571 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
572 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
573 /* restore page register */
574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
575 break;
cd28ab6a
SH		 576
577 default:
578 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
579 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 580
cd28ab6a 581 /* turn off the Rx LED (LED_RX) */
a84d0a3d 582 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 583 }
584
0ce8b98d 585 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 586 /* apply fixes in PHY AFE */
ed6d32c7
SH		 587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
588
977bdf06 589 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 590 gm_phy_write(hw, port, 0x18, 0xaa99);
591 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 592
0ce8b98d
SH		 593 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
594 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
595 gm_phy_write(hw, port, 0x18, 0xa204);
596 gm_phy_write(hw, port, 0x17, 0x2002);
597 }
977bdf06
SH		 598
599 /* set page register to 0 */
9467a8fc 600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 601 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
602 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
603 /* apply workaround for integrated resistors calibration */
604 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
605 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 606 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
607 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 608 /* no effect on Yukon-XL */
977bdf06 609 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 610
0ea065e5
SH		 611 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
612 || sky2->speed == SPEED_100) {
977bdf06 613 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 614 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 615 }
cd28ab6a 616
977bdf06
SH		 617 if (ledover)
618 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
619
620 }
2eaba1a2 621
d571b694 622 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 623 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 624 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
625 else
626 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
627}
628
b96936da
SH		 629static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
630static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
631
632static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 633{
634 u32 reg1;
d3bcfbeb 635
82637e80 636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 638 reg1 &= ~phy_power[port];
d3bcfbeb 639
b96936da 640 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 641 reg1 |= coma_mode[port];
642
b32f40c4 643 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 644 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
645 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 646
647 if (hw->chip_id == CHIP_ID_YUKON_FE)
648 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
649 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
650 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 651}
167f53d0 652
b96936da
SH		 653static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
654{
655 u32 reg1;
db99b988
SH		 656 u16 ctrl;
657
658 /* release GPHY Control reset */
659 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
660
661 /* release GMAC reset */
662 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
663
664 if (hw->flags & SKY2_HW_NEWER_PHY) {
665 /* select page 2 to access MAC control register */
666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
667
668 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
669 /* allow GMII Power Down */
670 ctrl &= ~PHY_M_MAC_GMIF_PUP;
671 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
672
673 /* set page register back to 0 */
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
675 }
676
677 /* setup General Purpose Control Register */
678 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 679 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
680 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
681 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 682
683 if (hw->chip_id != CHIP_ID_YUKON_EC) {
684 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 685 /* select page 2 to access MAC control register */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 687
e484d5f5 688 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 689 /* enable Power Down */
690 ctrl |= PHY_M_PC_POW_D_ENA;
691 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 692
693 /* set page register back to 0 */
694 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 695 }
696
697 /* set IEEE compatible Power Down Mode (dev. #4.99) */
698 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
699 }
b96936da
SH		 700
701 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
702 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 703 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 704 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
705 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 706}
707
1b537565
SH		 708/* Force a renegotiation */
709static void sky2_phy_reinit(struct sky2_port *sky2)
710{
e07b1aa8 711 spin_lock_bh(&sky2->phy_lock);
1b537565 712 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 713 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 714}
715
e3173832
SH		 716/* Put device in state to listen for Wake On Lan */
717static void sky2_wol_init(struct sky2_port *sky2)
718{
719 struct sky2_hw *hw = sky2->hw;
720 unsigned port = sky2->port;
721 enum flow_control save_mode;
722 u16 ctrl;
723 u32 reg1;
724
725 /* Bring hardware out of reset */
726 sky2_write16(hw, B0_CTST, CS_RST_CLR);
727 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
728
729 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
730 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
731
732 /* Force to 10/100
733 * sky2_reset will re-enable on resume
734 */
735 save_mode = sky2->flow_mode;
736 ctrl = sky2->advertising;
737
738 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
739 sky2->flow_mode = FC_NONE;
b96936da
SH		 740
741 spin_lock_bh(&sky2->phy_lock);
742 sky2_phy_power_up(hw, port);
743 sky2_phy_init(hw, port);
744 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 745
746 sky2->flow_mode = save_mode;
747 sky2->advertising = ctrl;
748
749 /* Set GMAC to no flow control and auto update for speed/duplex */
750 gma_write16(hw, port, GM_GP_CTRL,
751 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
752 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
753
754 /* Set WOL address */
755 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
756 sky2->netdev->dev_addr, ETH_ALEN);
757
758 /* Turn on appropriate WOL control bits */
759 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
760 ctrl = 0;
761 if (sky2->wol & WAKE_PHY)
762 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
763 else
764 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
765
766 if (sky2->wol & WAKE_MAGIC)
767 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
768 else
a419aef8 769 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 770
771 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
772 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
773
774 /* Turn on legacy PCI-Express PME mode */
b32f40c4 775 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 776 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 777 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 778
779 /* block receiver */
780 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
781
782}
783
69161611
SH		 784static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
785{
05745c4a
SH		 786 struct net_device *dev = hw->dev[port];
787
ed4d4161
SH		 788 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
789 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 790 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161
SH		 791 /* Yukon-Extreme B0 and further Extreme devices */
792 /* enable Store & Forward mode for TX */
05745c4a 793
ed4d4161
SH		 794 if (dev->mtu <= ETH_DATA_LEN)
795 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
796 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 797
ed4d4161
SH		 798 else
799 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
800 TX_JUMBO_ENA| TX_STFW_ENA);
801 } else {
802 if (dev->mtu <= ETH_DATA_LEN)
803 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
804 else {
805 /* set Tx GMAC FIFO Almost Empty Threshold */
806 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
807 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 808
ed4d4161
SH		 809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
810
811 /* Can't do offload because of lack of store/forward */
812 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
813 }
69161611
SH		 814 }
815}
816
cd28ab6a
SH		 817static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
818{
819 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
820 u16 reg;
25cccecc 821 u32 rx_reg;
cd28ab6a
SH		 822 int i;
823 const u8 *addr = hw->dev[port]->dev_addr;
824
f350339c
SH		 825 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
826 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 827
828 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
829
793b883e 830 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 831 /* WA DEV_472 -- looks like crossed wires on port 2 */
832 /* clear GMAC 1 Control reset */
833 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
834 do {
835 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
836 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
837 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
838 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
839 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
840 }
841
793b883e 842 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 843
2eaba1a2
SH		 844 /* Enable Transmit FIFO Underrun */
845 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
846
e07b1aa8 847 spin_lock_bh(&sky2->phy_lock);
b96936da 848 sky2_phy_power_up(hw, port);
cd28ab6a 849 sky2_phy_init(hw, port);
e07b1aa8 850 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 851
852 /* MIB clear */
853 reg = gma_read16(hw, port, GM_PHY_ADDR);
854 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
855
43f2f104
SH		 856 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
857 gma_read16(hw, port, i);
cd28ab6a
SH		 858 gma_write16(hw, port, GM_PHY_ADDR, reg);
859
860 /* transmit control */
861 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
862
863 /* receive control reg: unicast + multicast + no FCS */
864 gma_write16(hw, port, GM_RX_CTRL,
793b883e 865 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 866
867 /* transmit flow control */
868 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
869
870 /* transmit parameter */
871 gma_write16(hw, port, GM_TX_PARAM,
872 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
873 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
874 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
875 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
876
877 /* serial mode register */
878 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 879 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 880
6b1a3aef 881 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 882 reg |= GM_SMOD_JUMBO_ENA;
883
884 gma_write16(hw, port, GM_SERIAL_MODE, reg);
885
cd28ab6a
SH		 886 /* virtual address for data */
887 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
888
793b883e
SH		 889 /* physical address: used for pause frames */
890 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
891
892 /* ignore counter overflows */
cd28ab6a
SH		 893 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
895 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
896
897 /* Configure Rx MAC FIFO */
898 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 899 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 900 if (hw->chip_id == CHIP_ID_YUKON_EX ||
901 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 902 rx_reg |= GMF_RX_OVER_ON;
69161611 903
25cccecc 904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 905
798fdd07
SH		 906 if (hw->chip_id == CHIP_ID_YUKON_XL) {
907 /* Hardware errata - clear flush mask */
908 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
909 } else {
910 /* Flush Rx MAC FIFO on any flow control or error */
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
912 }
cd28ab6a 913
8df9a876 914 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 915 reg = RX_GMF_FL_THR_DEF + 1;
916 /* Another magic mystery workaround from sk98lin */
917 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
918 hw->chip_rev == CHIP_REV_YU_FE2_A0)
919 reg = 0x178;
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 921
922 /* Configure Tx MAC FIFO */
923 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
924 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 925
e0c28116 926 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 927 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24
SH		 928 /* Pause threshold is scaled by 8 in bytes */
929 if (hw->chip_id == CHIP_ID_YUKON_FE_P
930 && hw->chip_rev == CHIP_REV_YU_FE2_A0)
931 reg = 1568 / 8;
932 else
933 reg = 1024 / 8;
934 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
935 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 936
69161611 937 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 938 }
939
e970d1f8
SH		 940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
942 /* disable dynamic watermark */
943 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
944 reg &= ~TX_DYN_WM_ENA;
945 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
946 }
cd28ab6a
SH		 947}
948
67712901
SH		 949/* Assign Ram Buffer allocation to queue */
950static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 951{
67712901
SH		 952 u32 end;
953
954 /* convert from K bytes to qwords used for hw register */
955 start *= 1024/8;
956 space *= 1024/8;
957 end = start + space - 1;
793b883e 958
cd28ab6a
SH		 959 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
960 sky2_write32(hw, RB_ADDR(q, RB_START), start);
961 sky2_write32(hw, RB_ADDR(q, RB_END), end);
962 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
963 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
964
965 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 966 u32 tp = space - space/4;
793b883e 967
1c28f6ba
SH		 968 /* On receive queue's set the thresholds
969 * give receiver priority when > 3/4 full
970 * send pause when down to 2K
971 */
972 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
973 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 974
1c28f6ba
SH		 975 tp = space - 2048/8;
976 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
977 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 978 } else {
979 /* Enable store & forward on Tx queue's because
980 * Tx FIFO is only 1K on Yukon
981 */
982 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
983 }
984
985 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 986 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 987}
988
cd28ab6a 989/* Setup Bus Memory Interface */
af4ed7e6 990static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 991{
992 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
993 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
994 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 995 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 996}
997
cd28ab6a
SH		 998/* Setup prefetch unit registers. This is the interface between
999 * hardware and driver list elements
1000 */
8cc048e3 1001static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1002 dma_addr_t addr, u32 last)
cd28ab6a 1003{
cd28ab6a
SH		 1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1005 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1006 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1007 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1008 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1009 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1010
1011 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1012}
1013
9b289c33 1014static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1015{
9b289c33 1016 struct sky2_tx_le *le = sky2->tx_le + *slot;
6b84daca 1017 struct tx_ring_info *re = sky2->tx_ring + *slot;
793b883e 1018
ee5f68fe 1019 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
6b84daca
SH		 1020 re->flags = 0;
1021 re->skb = NULL;
291ea614 1022 le->ctrl = 0;
793b883e
SH		 1023 return le;
1024}
cd28ab6a 1025
88f5f0ca
SH		 1026static void tx_init(struct sky2_port *sky2)
1027{
1028 struct sky2_tx_le *le;
1029
1030 sky2->tx_prod = sky2->tx_cons = 0;
1031 sky2->tx_tcpsum = 0;
1032 sky2->tx_last_mss = 0;
1033
9b289c33 1034 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1035 le->addr = 0;
1036 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1037 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1038}
1039
290d4de5
SH		 1040/* Update chip's next pointer */
1041static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1042{
50432cb5 1043 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1044 wmb();
50432cb5
SH		 1045 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1046
1047 /* Synchronize I/O on since next processor may write to tail */
1048 mmiowb();
cd28ab6a
SH		 1049}
1050
793b883e 1051
cd28ab6a
SH		 1052static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1053{
1054 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1055 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1056 le->ctrl = 0;
cd28ab6a
SH		 1057 return le;
1058}
1059
14d0263f
SH		 1060/* Build description to hardware for one receive segment */
1061static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1062 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1063{
1064 struct sky2_rx_le *le;
1065
86c6887e 1066 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1067 le = sky2_next_rx(sky2);
86c6887e 1068 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1069 le->opcode = OP_ADDR64 | HW_OWNER;
1070 }
793b883e 1071
cd28ab6a 1072 le = sky2_next_rx(sky2);
d6e74b6b 1073 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1074 le->length = cpu_to_le16(len);
14d0263f 1075 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1076}
1077
14d0263f
SH		 1078/* Build description to hardware for one possibly fragmented skb */
1079static void sky2_rx_submit(struct sky2_port *sky2,
1080 const struct rx_ring_info *re)
1081{
1082 int i;
1083
1084 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1085
1086 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1087 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1088}
1089
1090
454e6cb6 1091static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1092 unsigned size)
1093{
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1098 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1099 return -EIO;
1100
14d0263f
SH		 1101 pci_unmap_len_set(re, data_size, size);
1102
1103 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1104 re->frag_addr[i] = pci_map_page(pdev,
1105 skb_shinfo(skb)->frags[i].page,
1106 skb_shinfo(skb)->frags[i].page_offset,
1107 skb_shinfo(skb)->frags[i].size,
1108 PCI_DMA_FROMDEVICE);
454e6cb6 1109 return 0;
14d0263f
SH		 1110}
1111
1112static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1113{
1114 struct sk_buff *skb = re->skb;
1115 int i;
1116
1117 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1118 PCI_DMA_FROMDEVICE);
1119
1120 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1121 pci_unmap_page(pdev, re->frag_addr[i],
1122 skb_shinfo(skb)->frags[i].size,
1123 PCI_DMA_FROMDEVICE);
1124}
793b883e 1125
cd28ab6a
SH		 1126/* Tell chip where to start receive checksum.
1127 * Actually has two checksums, but set both same to avoid possible byte
1128 * order problems.
1129 */
793b883e 1130static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1131{
ea76e635 1132 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1133
ea76e635
SH		 1134 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1135 le->ctrl = 0;
1136 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1137
ea76e635
SH		 1138 sky2_write32(sky2->hw,
1139 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1140 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1141 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1142}
1143
6b1a3aef
SH		 1144/*
1145 * The RX Stop command will not work for Yukon-2 if the BMU does not
1146 * reach the end of packet and since we can't make sure that we have
1147 * incoming data, we must reset the BMU while it is not doing a DMA
1148 * transfer. Since it is possible that the RX path is still active,
1149 * the RX RAM buffer will be stopped first, so any possible incoming
1150 * data will not trigger a DMA. After the RAM buffer is stopped, the
1151 * BMU is polled until any DMA in progress is ended and only then it
1152 * will be reset.
1153 */
1154static void sky2_rx_stop(struct sky2_port *sky2)
1155{
1156 struct sky2_hw *hw = sky2->hw;
1157 unsigned rxq = rxqaddr[sky2->port];
1158 int i;
1159
1160 /* disable the RAM Buffer receive queue */
1161 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1162
1163 for (i = 0; i < 0xffff; i++)
1164 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1165 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1166 goto stopped;
1167
1168 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1169 sky2->netdev->name);
1170stopped:
1171 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1172
1173 /* reset the Rx prefetch unit */
1174 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1175 mmiowb();
6b1a3aef 1176}
793b883e 1177
d571b694 1178/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1179static void sky2_rx_clean(struct sky2_port *sky2)
1180{
1181 unsigned i;
1182
1183 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1184 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1185 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1186
1187 if (re->skb) {
14d0263f 1188 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1189 kfree_skb(re->skb);
1190 re->skb = NULL;
1191 }
1192 }
1193}
1194
ef743d33
SH		 1195/* Basic MII support */
1196static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1197{
1198 struct mii_ioctl_data *data = if_mii(ifr);
1199 struct sky2_port *sky2 = netdev_priv(dev);
1200 struct sky2_hw *hw = sky2->hw;
1201 int err = -EOPNOTSUPP;
1202
1203 if (!netif_running(dev))
1204 return -ENODEV; /* Phy still in reset */
1205
d89e1343 1206 switch (cmd) {
ef743d33
SH		 1207 case SIOCGMIIPHY:
1208 data->phy_id = PHY_ADDR_MARV;
1209
1210 /* fallthru */
1211 case SIOCGMIIREG: {
1212 u16 val = 0;
91c86df5 1213
e07b1aa8 1214 spin_lock_bh(&sky2->phy_lock);
ef743d33 1215 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1216 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1217
ef743d33
SH		 1218 data->val_out = val;
1219 break;
1220 }
1221
1222 case SIOCSMIIREG:
e07b1aa8 1223 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1224 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1225 data->val_in);
e07b1aa8 1226 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1227 break;
1228 }
1229 return err;
1230}
1231
d1f13708 1232#ifdef SKY2_VLAN_TAG_USED
d494eacd 1233static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1234{
d494eacd 1235 if (onoff) {
3d4e66f5
SH		 1236 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1237 RX_VLAN_STRIP_ON);
1238 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1239 TX_VLAN_TAG_ON);
1240 } else {
1241 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1242 RX_VLAN_STRIP_OFF);
1243 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1244 TX_VLAN_TAG_OFF);
1245 }
d494eacd
SH		 1246}
1247
1248static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1249{
1250 struct sky2_port *sky2 = netdev_priv(dev);
1251 struct sky2_hw *hw = sky2->hw;
1252 u16 port = sky2->port;
1253
1254 netif_tx_lock_bh(dev);
1255 napi_disable(&hw->napi);
1256
1257 sky2->vlgrp = grp;
1258 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1259
d1d08d12 1260 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1261 napi_enable(&hw->napi);
2bb8c262 1262 netif_tx_unlock_bh(dev);
d1f13708
SH		 1263}
1264#endif
1265
bd1c6869
SH		 1266/* Amount of required worst case padding in rx buffer */
1267static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1268{
1269 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1270}
1271
82788c7a 1272/*
14d0263f
SH		 1273 * Allocate an skb for receiving. If the MTU is large enough
1274 * make the skb non-linear with a fragment list of pages.
82788c7a 1275 */
14d0263f 1276static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1277{
1278 struct sk_buff *skb;
14d0263f 1279 int i;
82788c7a 1280
724b6942
SH		 1281 skb = netdev_alloc_skb(sky2->netdev,
1282 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1283 if (!skb)
1284 goto nomem;
1285
39dbd958 1286 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1287 unsigned char *start;
1288 /*
1289 * Workaround for a bug in FIFO that cause hang
1290 * if the FIFO if the receive buffer is not 64 byte aligned.
1291 * The buffer returned from netdev_alloc_skb is
1292 * aligned except if slab debugging is enabled.
1293 */
f03b8654
SH		 1294 start = PTR_ALIGN(skb->data, 8);
1295 skb_reserve(skb, start - skb->data);
bd1c6869 1296 } else
f03b8654 1297 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1298
1299 for (i = 0; i < sky2->rx_nfrags; i++) {
1300 struct page *page = alloc_page(GFP_ATOMIC);
1301
1302 if (!page)
1303 goto free_partial;
1304 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1305 }
1306
1307 return skb;
14d0263f
SH		 1308free_partial:
1309 kfree_skb(skb);
1310nomem:
1311 return NULL;
82788c7a
SH		 1312}
1313
55c9dd35
SH		 1314static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1315{
1316 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1317}
1318
cd28ab6a
SH		 1319/*
1320 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1321 * Normal case this ends up creating one list element for skb
1322 * in the receive ring. Worst case if using large MTU and each
1323 * allocation falls on a different 64 bit region, that results
1324 * in 6 list elements per ring entry.
1325 * One element is used for checksum enable/disable, and one
1326 * extra to avoid wrap.
cd28ab6a 1327 */
6b1a3aef 1328static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1329{
6b1a3aef 1330 struct sky2_hw *hw = sky2->hw;
14d0263f 1331 struct rx_ring_info *re;
6b1a3aef 1332 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1333 unsigned i, size, thresh;
cd28ab6a 1334
6b1a3aef 1335 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1336 sky2_qset(hw, rxq);
977bdf06 1337
c3905bc4
SH		 1338 /* On PCI express lowering the watermark gives better performance */
1339 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1340 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1341
1342 /* These chips have no ram buffer?
1343 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1344 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1345 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1346 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1347 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1348
6b1a3aef
SH		 1349 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1350
ea76e635
SH		 1351 if (!(hw->flags & SKY2_HW_NEW_LE))
1352 rx_set_checksum(sky2);
14d0263f
SH		 1353
1354 /* Space needed for frame data + headers rounded up */
f957da2a 1355 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1356
1357 /* Stopping point for hardware truncation */
1358 thresh = (size - 8) / sizeof(u32);
1359
5f06eba4 1360 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1361 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1362
5f06eba4
SH		 1363 /* Compute residue after pages */
1364 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1365
5f06eba4
SH		 1366 /* Optimize to handle small packets and headers */
1367 if (size < copybreak)
1368 size = copybreak;
1369 if (size < ETH_HLEN)
1370 size = ETH_HLEN;
14d0263f 1371
14d0263f
SH		 1372 sky2->rx_data_size = size;
1373
1374 /* Fill Rx ring */
793b883e 1375 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1376 re = sky2->rx_ring + i;
cd28ab6a 1377
14d0263f 1378 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1379 if (!re->skb)
1380 goto nomem;
1381
454e6cb6
SH		 1382 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1383 dev_kfree_skb(re->skb);
1384 re->skb = NULL;
1385 goto nomem;
1386 }
1387
14d0263f 1388 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1389 }
1390
a1433ac4
SH		 1391 /*
1392 * The receiver hangs if it receives frames larger than the
1393 * packet buffer. As a workaround, truncate oversize frames, but
1394 * the register is limited to 9 bits, so if you do frames > 2052
1395 * you better get the MTU right!
1396 */
a1433ac4
SH		 1397 if (thresh > 0x1ff)
1398 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1399 else {
1400 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1401 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1402 }
1403
6b1a3aef 1404 /* Tell chip about available buffers */
55c9dd35 1405 sky2_rx_update(sky2, rxq);
877c8570
SH		 1406
1407 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1408 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1409 /*
1410 * Disable flushing of non ASF packets;
1411 * must be done after initializing the BMUs;
1412 * drivers without ASF support should do this too, otherwise
1413 * it may happen that they cannot run on ASF devices;
1414 * remember that the MAC FIFO isn't reset during initialization.
1415 */
1416 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1417 }
1418
1419 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1420 /* Enable RX Home Address & Routing Header checksum fix */
1421 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1422 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1423
1424 /* Enable TX Home Address & Routing Header checksum fix */
1425 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1426 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1427 }
1428
1429
1430
cd28ab6a
SH		 1431 return 0;
1432nomem:
1433 sky2_rx_clean(sky2);
1434 return -ENOMEM;
1435}
1436
90bbebb4
MM		 1437static int sky2_alloc_buffers(struct sky2_port *sky2)
1438{
1439 struct sky2_hw *hw = sky2->hw;
1440
1441 /* must be power of 2 */
1442 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1443 sky2->tx_ring_size *
1444 sizeof(struct sky2_tx_le),
1445 &sky2->tx_le_map);
1446 if (!sky2->tx_le)
1447 goto nomem;
1448
1449 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1450 GFP_KERNEL);
1451 if (!sky2->tx_ring)
1452 goto nomem;
1453
1454 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1455 &sky2->rx_le_map);
1456 if (!sky2->rx_le)
1457 goto nomem;
1458 memset(sky2->rx_le, 0, RX_LE_BYTES);
1459
1460 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1461 GFP_KERNEL);
1462 if (!sky2->rx_ring)
1463 goto nomem;
1464
1465 return 0;
1466nomem:
1467 return -ENOMEM;
1468}
1469
1470static void sky2_free_buffers(struct sky2_port *sky2)
1471{
1472 struct sky2_hw *hw = sky2->hw;
1473
1474 if (sky2->rx_le) {
1475 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1476 sky2->rx_le, sky2->rx_le_map);
1477 sky2->rx_le = NULL;
1478 }
1479 if (sky2->tx_le) {
1480 pci_free_consistent(hw->pdev,
1481 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1482 sky2->tx_le, sky2->tx_le_map);
1483 sky2->tx_le = NULL;
1484 }
1485 kfree(sky2->tx_ring);
1486 kfree(sky2->rx_ring);
1487
1488 sky2->tx_ring = NULL;
1489 sky2->rx_ring = NULL;
1490}
1491
cd28ab6a
SH		 1492/* Bring up network interface. */
1493static int sky2_up(struct net_device *dev)
1494{
1495 struct sky2_port *sky2 = netdev_priv(dev);
1496 struct sky2_hw *hw = sky2->hw;
1497 unsigned port = sky2->port;
e0c28116 1498 u32 imask, ramsize;
90bbebb4 1499 int cap, err;
843a46f4 1500 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1501
ee7abb04
SH		 1502 /*
1503 * On dual port PCI-X card, there is an problem where status
1504 * can be received out of order due to split transactions
843a46f4 1505 */
ee7abb04
SH		 1506 if (otherdev && netif_running(otherdev) &&
1507 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1508 u16 cmd;
1509
b32f40c4 1510 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1511 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1512 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1513
ee7abb04 1514 }
843a46f4 1515
55d7b4e6
SH		 1516 netif_carrier_off(dev);
1517
90bbebb4
MM		 1518 err = sky2_alloc_buffers(sky2);
1519 if (err)
cd28ab6a 1520 goto err_out;
88f5f0ca
SH		 1521
1522 tx_init(sky2);
cd28ab6a 1523
cd28ab6a
SH		 1524 sky2_mac_init(hw, port);
1525
e0c28116
SH		 1526 /* Register is number of 4K blocks on internal RAM buffer. */
1527 ramsize = sky2_read8(hw, B2_E_0) * 4;
1528 if (ramsize > 0) {
67712901 1529 u32 rxspace;
cd28ab6a 1530
e0c28116 1531 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1532 if (ramsize < 16)
1533 rxspace = ramsize / 2;
1534 else
1535 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1536
67712901
SH		 1537 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1538 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1539
1540 /* Make sure SyncQ is disabled */
1541 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1542 RB_RST_SET);
1543 }
793b883e 1544
af4ed7e6 1545 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1546
69161611
SH		 1547 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1548 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1549 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1550
977bdf06 1551 /* Set almost empty threshold */
c2716fb4
SH		 1552 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1553 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1554 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1555
6b1a3aef 1556 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1557 sky2->tx_ring_size - 1);
cd28ab6a 1558
d494eacd
SH		 1559#ifdef SKY2_VLAN_TAG_USED
1560 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1561#endif
1562
6b1a3aef 1563 err = sky2_rx_start(sky2);
6de16237 1564 if (err)
cd28ab6a
SH		 1565 goto err_out;
1566
cd28ab6a 1567 /* Enable interrupts from phy/mac for port */
e07b1aa8 1568 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1569 imask |= portirq_msk[port];
e07b1aa8 1570 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1571 sky2_read32(hw, B0_IMSK);
e07b1aa8 1572
a11da890
AD		 1573 if (netif_msg_ifup(sky2))
1574 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1575
cd28ab6a
SH		 1576 return 0;
1577
1578err_out:
90bbebb4 1579 sky2_free_buffers(sky2);
cd28ab6a
SH		 1580 return err;
1581}
1582
793b883e 1583/* Modular subtraction in ring */
ee5f68fe 1584static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1585{
ee5f68fe 1586 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1587}
cd28ab6a 1588
793b883e
SH		 1589/* Number of list elements available for next tx */
1590static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1591{
ee5f68fe 1592 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1593}
1594
793b883e 1595/* Estimate of number of transmit list elements required */
28bd181a 1596static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1597{
793b883e
SH		 1598 unsigned count;
1599
07e31637
SH		 1600 count = (skb_shinfo(skb)->nr_frags + 1)
1601 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1602
89114afd 1603 if (skb_is_gso(skb))
793b883e 1604 ++count;
07e31637
SH		 1605 else if (sizeof(dma_addr_t) == sizeof(u32))
1606 ++count; /* possible vlan */
793b883e 1607
84fa7933 1608 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1609 ++count;
1610
1611 return count;
cd28ab6a
SH		 1612}
1613
6b84daca
SH		 1614static void sky2_tx_unmap(struct pci_dev *pdev,
1615 const struct tx_ring_info *re)
1616{
1617 if (re->flags & TX_MAP_SINGLE)
1618 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1619 pci_unmap_len(re, maplen),
1620 PCI_DMA_TODEVICE);
1621 else if (re->flags & TX_MAP_PAGE)
1622 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1623 pci_unmap_len(re, maplen),
1624 PCI_DMA_TODEVICE);
1625}
1626
793b883e
SH		 1627/*
1628 * Put one packet in ring for transmit.
1629 * A single packet can generate multiple list elements, and
1630 * the number of ring elements will probably be less than the number
1631 * of list elements used.
1632 */
61357325
SH		 1633static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1634 struct net_device *dev)
cd28ab6a
SH		 1635{
1636 struct sky2_port *sky2 = netdev_priv(dev);
1637 struct sky2_hw *hw = sky2->hw;
d1f13708 1638 struct sky2_tx_le *le = NULL;
6cdbbdf3 1639 struct tx_ring_info *re;
9b289c33 1640 unsigned i, len;
cd28ab6a 1641 dma_addr_t mapping;
5dce95e5
SH		 1642 u32 upper;
1643 u16 slot;
cd28ab6a
SH		 1644 u16 mss;
1645 u8 ctrl;
1646
2bb8c262
SH		 1647 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1648 return NETDEV_TX_BUSY;
cd28ab6a 1649
cd28ab6a
SH		 1650 len = skb_headlen(skb);
1651 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1652
454e6cb6
SH		 1653 if (pci_dma_mapping_error(hw->pdev, mapping))
1654 goto mapping_error;
1655
9b289c33 1656 slot = sky2->tx_prod;
454e6cb6
SH		 1657 if (unlikely(netif_msg_tx_queued(sky2)))
1658 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1659 dev->name, slot, skb->len);
454e6cb6 1660
86c6887e 1661 /* Send high bits if needed */
5dce95e5
SH		 1662 upper = upper_32_bits(mapping);
1663 if (upper != sky2->tx_last_upper) {
9b289c33 1664 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1665 le->addr = cpu_to_le32(upper);
1666 sky2->tx_last_upper = upper;
793b883e 1667 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1668 }
cd28ab6a
SH		 1669
1670 /* Check for TCP Segmentation Offload */
7967168c 1671 mss = skb_shinfo(skb)->gso_size;
793b883e 1672 if (mss != 0) {
ea76e635
SH		 1673
1674 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1675 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1676
1677 if (mss != sky2->tx_last_mss) {
9b289c33 1678 le = get_tx_le(sky2, &slot);
69161611 1679 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1680
1681 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1682 le->opcode = OP_MSS | HW_OWNER;
1683 else
1684 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1685 sky2->tx_last_mss = mss;
1686 }
cd28ab6a
SH		 1687 }
1688
cd28ab6a 1689 ctrl = 0;
d1f13708
SH		 1690#ifdef SKY2_VLAN_TAG_USED
1691 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1692 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1693 if (!le) {
9b289c33 1694 le = get_tx_le(sky2, &slot);
f65b138c 1695 le->addr = 0;
d1f13708 1696 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1697 } else
1698 le->opcode |= OP_VLAN;
1699 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1700 ctrl |= INS_VLAN;
1701 }
1702#endif
1703
1704 /* Handle TCP checksum offload */
84fa7933 1705 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1706 /* On Yukon EX (some versions) encoding change. */
ea76e635 1707 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1708 ctrl |= CALSUM; /* auto checksum */
1709 else {
1710 const unsigned offset = skb_transport_offset(skb);
1711 u32 tcpsum;
1712
1713 tcpsum = offset << 16; /* sum start */
1714 tcpsum |= offset + skb->csum_offset; /* sum write */
1715
1716 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1717 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1718 ctrl |= UDPTCP;
1719
1720 if (tcpsum != sky2->tx_tcpsum) {
1721 sky2->tx_tcpsum = tcpsum;
1722
9b289c33 1723 le = get_tx_le(sky2, &slot);
69161611
SH		 1724 le->addr = cpu_to_le32(tcpsum);
1725 le->length = 0; /* initial checksum value */
1726 le->ctrl = 1; /* one packet */
1727 le->opcode = OP_TCPLISW | HW_OWNER;
1728 }
1d179332 1729 }
cd28ab6a
SH		 1730 }
1731
6b84daca
SH		 1732 re = sky2->tx_ring + slot;
1733 re->flags = TX_MAP_SINGLE;
1734 pci_unmap_addr_set(re, mapaddr, mapping);
1735 pci_unmap_len_set(re, maplen, len);
1736
9b289c33 1737 le = get_tx_le(sky2, &slot);
d6e74b6b 1738 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1739 le->length = cpu_to_le16(len);
1740 le->ctrl = ctrl;
793b883e 1741 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1742
cd28ab6a
SH		 1743
1744 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1745 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1746
1747 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1748 frag->size, PCI_DMA_TODEVICE);
86c6887e 1749
454e6cb6
SH		 1750 if (pci_dma_mapping_error(hw->pdev, mapping))
1751 goto mapping_unwind;
1752
5dce95e5
SH		 1753 upper = upper_32_bits(mapping);
1754 if (upper != sky2->tx_last_upper) {
9b289c33 1755 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1756 le->addr = cpu_to_le32(upper);
1757 sky2->tx_last_upper = upper;
793b883e 1758 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1759 }
1760
6b84daca
SH		 1761 re = sky2->tx_ring + slot;
1762 re->flags = TX_MAP_PAGE;
1763 pci_unmap_addr_set(re, mapaddr, mapping);
1764 pci_unmap_len_set(re, maplen, frag->size);
1765
9b289c33 1766 le = get_tx_le(sky2, &slot);
d6e74b6b 1767 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1768 le->length = cpu_to_le16(frag->size);
1769 le->ctrl = ctrl;
793b883e 1770 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1771 }
6cdbbdf3 1772
6b84daca 1773 re->skb = skb;
cd28ab6a
SH		 1774 le->ctrl |= EOP;
1775
9b289c33
MM		 1776 sky2->tx_prod = slot;
1777
97bda706
SH		 1778 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1779 netif_stop_queue(dev);
b19666d9 1780
290d4de5 1781 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1782
cd28ab6a 1783 return NETDEV_TX_OK;
454e6cb6
SH		 1784
1785mapping_unwind:
ee5f68fe 1786 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1787 re = sky2->tx_ring + i;
1788
6b84daca 1789 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1790 }
1791
454e6cb6
SH		 1792mapping_error:
1793 if (net_ratelimit())
1794 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1795 dev_kfree_skb(skb);
1796 return NETDEV_TX_OK;
cd28ab6a
SH		 1797}
1798
cd28ab6a 1799/*
793b883e
SH		 1800 * Free ring elements from starting at tx_cons until "done"
1801 *
481cea4a
SH		 1802 * NB:
1803 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1804 * buffers so make sure not to free skb to early.
481cea4a
SH		 1805 * 2. This may run in parallel start_xmit because the it only
1806 * looks at the tail of the queue of FIFO (tx_cons), not
1807 * the head (tx_prod)
cd28ab6a 1808 */
d11c13e7 1809static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1810{
d11c13e7 1811 struct net_device *dev = sky2->netdev;
291ea614 1812 unsigned idx;
cd28ab6a 1813
ee5f68fe 1814 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1815
291ea614 1816 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1817 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1818 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1819 struct sk_buff *skb = re->skb;
291ea614 1820
6b84daca 1821 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1822
6b84daca 1823 if (skb) {
291ea614
SH		 1824 if (unlikely(netif_msg_tx_done(sky2)))
1825 printk(KERN_DEBUG "%s: tx done %u\n",
1826 dev->name, idx);
3cf26753 1827
7138a0f5 1828 dev->stats.tx_packets++;
bd1c6869
SH		 1829 dev->stats.tx_bytes += skb->len;
1830
724b6942 1831 dev_kfree_skb_any(skb);
2bf56fe2 1832
ee5f68fe 1833 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1834 }
793b883e 1835 }
793b883e 1836
291ea614 1837 sky2->tx_cons = idx;
50432cb5
SH		 1838 smp_mb();
1839
22e11703 1840 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1841 netif_wake_queue(dev);
cd28ab6a
SH		 1842}
1843
264bb4fa 1844static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1845{
a510996b
MM		 1846 /* Disable Force Sync bit and Enable Alloc bit */
1847 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1848 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1849
1850 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1851 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1852 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1853
1854 /* Reset the PCI FIFO of the async Tx queue */
1855 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1856 BMU_RST_SET | BMU_FIFO_RST);
1857
1858 /* Reset the Tx prefetch units */
1859 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1860 PREF_UNIT_RST_SET);
1861
1862 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1863 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1864}
1865
cd28ab6a
SH		 1866/* Network shutdown */
1867static int sky2_down(struct net_device *dev)
1868{
1869 struct sky2_port *sky2 = netdev_priv(dev);
1870 struct sky2_hw *hw = sky2->hw;
1871 unsigned port = sky2->port;
1872 u16 ctrl;
e07b1aa8 1873 u32 imask;
cd28ab6a 1874
1b537565
SH		 1875 /* Never really got started! */
1876 if (!sky2->tx_le)
1877 return 0;
1878
cd28ab6a
SH		 1879 if (netif_msg_ifdown(sky2))
1880 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1881
d104acaf
SH		 1882 /* Force flow control off */
1883 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1884
cd28ab6a
SH		 1885 /* Stop transmitter */
1886 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1887 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1888
1889 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1890 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1891
1892 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1893 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1894 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1895
1896 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1897
1898 /* Workaround shared GMAC reset */
793b883e
SH		 1899 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1900 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1901 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1902
cd28ab6a 1903 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1904
6c83504f
SH		 1905 /* Force any delayed status interrrupt and NAPI */
1906 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1907 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1908 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1909 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1910
a947a39d
MM		 1911 sky2_rx_stop(sky2);
1912
1913 /* Disable port IRQ */
1914 imask = sky2_read32(hw, B0_IMSK);
1915 imask &= ~portirq_msk[port];
1916 sky2_write32(hw, B0_IMSK, imask);
1917 sky2_read32(hw, B0_IMSK);
1918
6c83504f
SH		 1919 synchronize_irq(hw->pdev->irq);
1920 napi_synchronize(&hw->napi);
1921
0da6d7b3 1922 spin_lock_bh(&sky2->phy_lock);
b96936da 1923 sky2_phy_power_down(hw, port);
0da6d7b3 1924 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1925
264bb4fa
MM		 1926 sky2_tx_reset(hw, port);
1927
481cea4a
SH		 1928 /* Free any pending frames stuck in HW queue */
1929 sky2_tx_complete(sky2, sky2->tx_prod);
1930
cd28ab6a
SH		 1931 sky2_rx_clean(sky2);
1932
90bbebb4 1933 sky2_free_buffers(sky2);
1b537565 1934
cd28ab6a
SH		 1935 return 0;
1936}
1937
1938static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1939{
ea76e635 1940 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1941 return SPEED_1000;
1942
05745c4a
SH		 1943 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1944 if (aux & PHY_M_PS_SPEED_100)
1945 return SPEED_100;
1946 else
1947 return SPEED_10;
1948 }
cd28ab6a
SH		 1949
1950 switch (aux & PHY_M_PS_SPEED_MSK) {
1951 case PHY_M_PS_SPEED_1000:
1952 return SPEED_1000;
1953 case PHY_M_PS_SPEED_100:
1954 return SPEED_100;
1955 default:
1956 return SPEED_10;
1957 }
1958}
1959
1960static void sky2_link_up(struct sky2_port *sky2)
1961{
1962 struct sky2_hw *hw = sky2->hw;
1963 unsigned port = sky2->port;
1964 u16 reg;
16ad91e1
SH		 1965 static const char *fc_name[] = {
1966 [FC_NONE] = "none",
1967 [FC_TX] = "tx",
1968 [FC_RX] = "rx",
1969 [FC_BOTH] = "both",
1970 };
cd28ab6a 1971
cd28ab6a 1972 /* enable Rx/Tx */
2eaba1a2 1973 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1974 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1975 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1976
1977 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1978
1979 netif_carrier_on(sky2->netdev);
cd28ab6a 1980
75e80683 1981 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1982
cd28ab6a 1983 /* Turn on link LED */
793b883e 1984 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1985 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1986
1987 if (netif_msg_link(sky2))
1988 printk(KERN_INFO PFX
d571b694 1989 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1990 sky2->netdev->name, sky2->speed,
1991 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1992 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1993}
1994
1995static void sky2_link_down(struct sky2_port *sky2)
1996{
1997 struct sky2_hw *hw = sky2->hw;
1998 unsigned port = sky2->port;
1999 u16 reg;
2000
2001 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2002
2003 reg = gma_read16(hw, port, GM_GP_CTRL);
2004 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2005 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2006
cd28ab6a 2007 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 2008
2009 /* Turn on link LED */
2010 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2011
2012 if (netif_msg_link(sky2))
2013 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 2014
cd28ab6a
SH		 2015 sky2_phy_init(hw, port);
2016}
2017
16ad91e1
SH		 2018static enum flow_control sky2_flow(int rx, int tx)
2019{
2020 if (rx)
2021 return tx ? FC_BOTH : FC_RX;
2022 else
2023 return tx ? FC_TX : FC_NONE;
2024}
2025
793b883e
SH		 2026static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2027{
2028 struct sky2_hw *hw = sky2->hw;
2029 unsigned port = sky2->port;
da4c1ff4 2030 u16 advert, lpa;
793b883e 2031
da4c1ff4 2032 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2033 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 2034 if (lpa & PHY_M_AN_RF) {
2035 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2036 return -1;
2037 }
2038
793b883e
SH		 2039 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2040 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2041 sky2->netdev->name);
2042 return -1;
2043 }
2044
793b883e 2045 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2046 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2047
da4c1ff4
SH		 2048 /* Since the pause result bits seem to in different positions on
2049 * different chips. look at registers.
2050 */
ea76e635 2051 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2052 /* Shift for bits in fiber PHY */
2053 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2054 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2055
2056 if (advert & ADVERTISE_1000XPAUSE)
2057 advert |= ADVERTISE_PAUSE_CAP;
2058 if (advert & ADVERTISE_1000XPSE_ASYM)
2059 advert |= ADVERTISE_PAUSE_ASYM;
2060 if (lpa & LPA_1000XPAUSE)
2061 lpa |= LPA_PAUSE_CAP;
2062 if (lpa & LPA_1000XPAUSE_ASYM)
2063 lpa |= LPA_PAUSE_ASYM;
2064 }
793b883e 2065
da4c1ff4
SH		 2066 sky2->flow_status = FC_NONE;
2067 if (advert & ADVERTISE_PAUSE_CAP) {
2068 if (lpa & LPA_PAUSE_CAP)
2069 sky2->flow_status = FC_BOTH;
2070 else if (advert & ADVERTISE_PAUSE_ASYM)
2071 sky2->flow_status = FC_RX;
2072 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2073 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2074 sky2->flow_status = FC_TX;
2075 }
793b883e 2076
16ad91e1 2077 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2078 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2079 sky2->flow_status = FC_NONE;
2eaba1a2 2080
da4c1ff4 2081 if (sky2->flow_status & FC_TX)
793b883e
SH		 2082 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2083 else
2084 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2085
2086 return 0;
2087}
cd28ab6a 2088
e07b1aa8
SH		 2089/* Interrupt from PHY */
2090static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2091{
e07b1aa8
SH		 2092 struct net_device *dev = hw->dev[port];
2093 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2094 u16 istatus, phystat;
2095
ebc646f6
SH		 2096 if (!netif_running(dev))
2097 return;
2098
e07b1aa8
SH		 2099 spin_lock(&sky2->phy_lock);
2100 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2101 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2102
cd28ab6a
SH		 2103 if (netif_msg_intr(sky2))
2104 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2105 sky2->netdev->name, istatus, phystat);
2106
0ea065e5 2107 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2108 if (sky2_autoneg_done(sky2, phystat) == 0)
2109 sky2_link_up(sky2);
2110 goto out;
2111 }
cd28ab6a 2112
793b883e
SH		 2113 if (istatus & PHY_M_IS_LSP_CHANGE)
2114 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2115
793b883e
SH		 2116 if (istatus & PHY_M_IS_DUP_CHANGE)
2117 sky2->duplex =
2118 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2119
793b883e
SH		 2120 if (istatus & PHY_M_IS_LST_CHANGE) {
2121 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2122 sky2_link_up(sky2);
793b883e
SH		 2123 else
2124 sky2_link_down(sky2);
cd28ab6a 2125 }
793b883e 2126out:
e07b1aa8 2127 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2128}
2129
62335ab0 2130/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2131 * and tx queue is full (stopped).
2132 */
cd28ab6a
SH		 2133static void sky2_tx_timeout(struct net_device *dev)
2134{
2135 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2136 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2137
2138 if (netif_msg_timer(sky2))
2139 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2140
8f24664d 2141 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2142 dev->name, sky2->tx_cons, sky2->tx_prod,
2143 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2144 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2145
81906791
SH		 2146 /* can't restart safely under softirq */
2147 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2148}
2149
2150static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2151{
6b1a3aef
SH		 2152 struct sky2_port *sky2 = netdev_priv(dev);
2153 struct sky2_hw *hw = sky2->hw;
b628ed98 2154 unsigned port = sky2->port;
6b1a3aef
SH		 2155 int err;
2156 u16 ctl, mode;
e07b1aa8 2157 u32 imask;
cd28ab6a
SH		 2158
2159 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2160 return -EINVAL;
2161
05745c4a
SH		 2162 if (new_mtu > ETH_DATA_LEN &&
2163 (hw->chip_id == CHIP_ID_YUKON_FE ||
2164 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2165 return -EINVAL;
2166
6b1a3aef
SH		 2167 if (!netif_running(dev)) {
2168 dev->mtu = new_mtu;
2169 return 0;
2170 }
2171
e07b1aa8 2172 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2173 sky2_write32(hw, B0_IMSK, 0);
2174
018d1c66
SH		 2175 dev->trans_start = jiffies; /* prevent tx timeout */
2176 netif_stop_queue(dev);
bea3348e 2177 napi_disable(&hw->napi);
018d1c66 2178
e07b1aa8
SH		 2179 synchronize_irq(hw->pdev->irq);
2180
39dbd958 2181 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2182 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2183
2184 ctl = gma_read16(hw, port, GM_GP_CTRL);
2185 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2186 sky2_rx_stop(sky2);
2187 sky2_rx_clean(sky2);
cd28ab6a
SH		 2188
2189 dev->mtu = new_mtu;
14d0263f 2190
6b1a3aef
SH		 2191 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2192 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2193
2194 if (dev->mtu > ETH_DATA_LEN)
2195 mode |= GM_SMOD_JUMBO_ENA;
2196
b628ed98 2197 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2198
b628ed98 2199 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2200
6b1a3aef 2201 err = sky2_rx_start(sky2);
e07b1aa8 2202 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2203
d1d08d12 2204 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2205 napi_enable(&hw->napi);
2206
1b537565
SH		 2207 if (err)
2208 dev_close(dev);
2209 else {
b628ed98 2210 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2211
1b537565
SH		 2212 netif_wake_queue(dev);
2213 }
2214
cd28ab6a
SH		 2215 return err;
2216}
2217
14d0263f
SH		 2218/* For small just reuse existing skb for next receive */
2219static struct sk_buff *receive_copy(struct sky2_port *sky2,
2220 const struct rx_ring_info *re,
2221 unsigned length)
2222{
2223 struct sk_buff *skb;
2224
89d71a66 2225 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2226 if (likely(skb)) {
14d0263f
SH		 2227 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2228 length, PCI_DMA_FROMDEVICE);
d626f62b 2229 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2230 skb->ip_summed = re->skb->ip_summed;
2231 skb->csum = re->skb->csum;
2232 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2233 length, PCI_DMA_FROMDEVICE);
2234 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2235 skb_put(skb, length);
14d0263f
SH		 2236 }
2237 return skb;
2238}
2239
2240/* Adjust length of skb with fragments to match received data */
2241static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2242 unsigned int length)
2243{
2244 int i, num_frags;
2245 unsigned int size;
2246
2247 /* put header into skb */
2248 size = min(length, hdr_space);
2249 skb->tail += size;
2250 skb->len += size;
2251 length -= size;
2252
2253 num_frags = skb_shinfo(skb)->nr_frags;
2254 for (i = 0; i < num_frags; i++) {
2255 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2256
2257 if (length == 0) {
2258 /* don't need this page */
2259 __free_page(frag->page);
2260 --skb_shinfo(skb)->nr_frags;
2261 } else {
2262 size = min(length, (unsigned) PAGE_SIZE);
2263
2264 frag->size = size;
2265 skb->data_len += size;
2266 skb->truesize += size;
2267 skb->len += size;
2268 length -= size;
2269 }
2270 }
2271}
2272
2273/* Normal packet - take skb from ring element and put in a new one */
2274static struct sk_buff *receive_new(struct sky2_port *sky2,
2275 struct rx_ring_info *re,
2276 unsigned int length)
2277{
2278 struct sk_buff *skb, *nskb;
2279 unsigned hdr_space = sky2->rx_data_size;
2280
14d0263f
SH		 2281 /* Don't be tricky about reusing pages (yet) */
2282 nskb = sky2_rx_alloc(sky2);
2283 if (unlikely(!nskb))
2284 return NULL;
2285
2286 skb = re->skb;
2287 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2288
2289 prefetch(skb->data);
2290 re->skb = nskb;
454e6cb6
SH		 2291 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2292 dev_kfree_skb(nskb);
2293 re->skb = skb;
2294 return NULL;
2295 }
14d0263f
SH		 2296
2297 if (skb_shinfo(skb)->nr_frags)
2298 skb_put_frags(skb, hdr_space, length);
2299 else
489b10c1 2300 skb_put(skb, length);
14d0263f
SH		 2301 return skb;
2302}
2303
cd28ab6a
SH		 2304/*
2305 * Receive one packet.
d571b694 2306 * For larger packets, get new buffer.
cd28ab6a 2307 */
497d7c86 2308static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2309 u16 length, u32 status)
2310{
497d7c86 2311 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2312 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2313 struct sk_buff *skb = NULL;
d6532232
SH		 2314 u16 count = (status & GMR_FS_LEN) >> 16;
2315
2316#ifdef SKY2_VLAN_TAG_USED
2317 /* Account for vlan tag */
2318 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2319 count -= VLAN_HLEN;
2320#endif
cd28ab6a
SH		 2321
2322 if (unlikely(netif_msg_rx_status(sky2)))
2323 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2324 dev->name, sky2->rx_next, status, length);
cd28ab6a 2325
793b883e 2326 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2327 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2328
3b12e014
SH		 2329 /* This chip has hardware problems that generates bogus status.
2330 * So do only marginal checking and expect higher level protocols
2331 * to handle crap frames.
2332 */
2333 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2334 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2335 length != count)
2336 goto okay;
2337
42eeea01 2338 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2339 goto error;
2340
42eeea01
SH		 2341 if (!(status & GMR_FS_RX_OK))
2342 goto resubmit;
2343
d6532232
SH		 2344 /* if length reported by DMA does not match PHY, packet was truncated */
2345 if (length != count)
3b12e014 2346 goto len_error;
71749531 2347
3b12e014 2348okay:
14d0263f
SH		 2349 if (length < copybreak)
2350 skb = receive_copy(sky2, re, length);
2351 else
2352 skb = receive_new(sky2, re, length);
793b883e 2353resubmit:
14d0263f 2354 sky2_rx_submit(sky2, re);
79e57d32 2355
cd28ab6a
SH		 2356 return skb;
2357
3b12e014 2358len_error:
71749531
SH		 2359 /* Truncation of overlength packets
2360 causes PHY length to not match MAC length */
7138a0f5 2361 ++dev->stats.rx_length_errors;
d6532232 2362 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2363 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2364 dev->name, status, length);
d6532232 2365 goto resubmit;
71749531 2366
cd28ab6a 2367error:
7138a0f5 2368 ++dev->stats.rx_errors;
b6d77734 2369 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2370 dev->stats.rx_over_errors++;
b6d77734
SH		 2371 goto resubmit;
2372 }
6e15b712 2373
3be92a70 2374 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2375 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2376 dev->name, status, length);
793b883e
SH		 2377
2378 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2379 dev->stats.rx_length_errors++;
cd28ab6a 2380 if (status & GMR_FS_FRAGMENT)
7138a0f5 2381 dev->stats.rx_frame_errors++;
cd28ab6a 2382 if (status & GMR_FS_CRC_ERR)
7138a0f5 2383 dev->stats.rx_crc_errors++;
79e57d32 2384
793b883e 2385 goto resubmit;
cd28ab6a
SH		 2386}
2387
e07b1aa8
SH		 2388/* Transmit complete */
2389static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2390{
e07b1aa8 2391 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2392
49d4b8ba 2393 if (netif_running(dev))
e07b1aa8 2394 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2395}
2396
37e5a243
SH		 2397static inline void sky2_skb_rx(const struct sky2_port *sky2,
2398 u32 status, struct sk_buff *skb)
2399{
2400#ifdef SKY2_VLAN_TAG_USED
2401 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2402 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2403 if (skb->ip_summed == CHECKSUM_NONE)
2404 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2405 else
2406 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2407 vlan_tag, skb);
2408 return;
2409 }
2410#endif
2411 if (skb->ip_summed == CHECKSUM_NONE)
2412 netif_receive_skb(skb);
2413 else
2414 napi_gro_receive(&sky2->hw->napi, skb);
2415}
2416
bf15fe99
SH		 2417static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2418 unsigned packets, unsigned bytes)
2419{
2420 if (packets) {
2421 struct net_device *dev = hw->dev[port];
2422
2423 dev->stats.rx_packets += packets;
2424 dev->stats.rx_bytes += bytes;
2425 dev->last_rx = jiffies;
2426 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2427 }
2428}
2429
e07b1aa8 2430/* Process status response ring */
26691830 2431static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2432{
e07b1aa8 2433 int work_done = 0;
bf15fe99
SH		 2434 unsigned int total_bytes[2] = { 0 };
2435 unsigned int total_packets[2] = { 0 };
a8fd6266 2436
af2a58ac 2437 rmb();
26691830 2438 do {
55c9dd35 2439 struct sky2_port *sky2;
13210ce5 2440 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2441 unsigned port;
13210ce5 2442 struct net_device *dev;
cd28ab6a 2443 struct sk_buff *skb;
cd28ab6a
SH		 2444 u32 status;
2445 u16 length;
ab5adecb
SH		 2446 u8 opcode = le->opcode;
2447
2448 if (!(opcode & HW_OWNER))
2449 break;
cd28ab6a 2450
cb5d9547 2451 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2452
ab5adecb 2453 port = le->css & CSS_LINK_BIT;
69161611 2454 dev = hw->dev[port];
13210ce5 2455 sky2 = netdev_priv(dev);
f65b138c
SH		 2456 length = le16_to_cpu(le->length);
2457 status = le32_to_cpu(le->status);
cd28ab6a 2458
ab5adecb
SH		 2459 le->opcode = 0;
2460 switch (opcode & ~HW_OWNER) {
cd28ab6a 2461 case OP_RXSTAT:
bf15fe99
SH		 2462 total_packets[port]++;
2463 total_bytes[port] += length;
497d7c86 2464 skb = sky2_receive(dev, length, status);
3225b919 2465 if (unlikely(!skb)) {
7138a0f5 2466 dev->stats.rx_dropped++;
55c9dd35 2467 break;
3225b919 2468 }
13210ce5 2469
69161611 2470 /* This chip reports checksum status differently */
05745c4a 2471 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2472 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2473 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2474 (le->css & CSS_TCPUDPCSOK))
2475 skb->ip_summed = CHECKSUM_UNNECESSARY;
2476 else
2477 skb->ip_summed = CHECKSUM_NONE;
2478 }
2479
13210ce5 2480 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2481
37e5a243 2482 sky2_skb_rx(sky2, status, skb);
13210ce5 2483
22e11703 2484 /* Stop after net poll weight */
13210ce5
SH		 2485 if (++work_done >= to_do)
2486 goto exit_loop;
cd28ab6a
SH		 2487 break;
2488
d1f13708
SH		 2489#ifdef SKY2_VLAN_TAG_USED
2490 case OP_RXVLAN:
2491 sky2->rx_tag = length;
2492 break;
2493
2494 case OP_RXCHKSVLAN:
2495 sky2->rx_tag = length;
2496 /* fall through */
2497#endif
cd28ab6a 2498 case OP_RXCHKS:
0ea065e5 2499 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH		 2500 break;
2501
05745c4a
SH		 2502 /* If this happens then driver assuming wrong format */
2503 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2504 if (net_ratelimit())
2505 printk(KERN_NOTICE "%s: unexpected"
2506 " checksum status\n",
2507 dev->name);
69161611 2508 break;
05745c4a 2509 }
69161611 2510
87418307
SH		 2511 /* Both checksum counters are programmed to start at
2512 * the same offset, so unless there is a problem they
2513 * should match. This failure is an early indication that
2514 * hardware receive checksumming won't work.
2515 */
2516 if (likely(status >> 16 == (status & 0xffff))) {
2517 skb = sky2->rx_ring[sky2->rx_next].skb;
2518 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2519 skb->csum = le16_to_cpu(status);
87418307
SH		 2520 } else {
2521 printk(KERN_NOTICE PFX "%s: hardware receive "
2522 "checksum problem (status = %#x)\n",
2523 dev->name, status);
0ea065e5
SH		 2524 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2525
87418307 2526 sky2_write32(sky2->hw,
69161611 2527 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2528 BMU_DIS_RX_CHKSUM);
2529 }
cd28ab6a
SH		 2530 break;
2531
2532 case OP_TXINDEXLE:
13b97b74 2533 /* TX index reports status for both ports */
f55925d7 2534 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2535 if (hw->dev[1])
2536 sky2_tx_done(hw->dev[1],
2537 ((status >> 24) & 0xff)
2538 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2539 break;
2540
cd28ab6a
SH		 2541 default:
2542 if (net_ratelimit())
793b883e 2543 printk(KERN_WARNING PFX
ab5adecb 2544 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2545 }
26691830 2546 } while (hw->st_idx != idx);
cd28ab6a 2547
fe2a24df
SH		 2548 /* Fully processed status ring so clear irq */
2549 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2550
13210ce5 2551exit_loop:
bf15fe99
SH		 2552 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2553 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2554
e07b1aa8 2555 return work_done;
cd28ab6a
SH		 2556}
2557
2558static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2559{
2560 struct net_device *dev = hw->dev[port];
2561
3be92a70
SH		 2562 if (net_ratelimit())
2563 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2564 dev->name, status);
cd28ab6a
SH		 2565
2566 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2567 if (net_ratelimit())
2568 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2569 dev->name);
cd28ab6a
SH		 2570 /* Clear IRQ */
2571 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2572 }
2573
2574 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2575 if (net_ratelimit())
2576 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2577 dev->name);
cd28ab6a
SH		 2578
2579 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2580 }
2581
2582 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2583 if (net_ratelimit())
2584 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2585 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2586 }
2587
2588 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2589 if (net_ratelimit())
2590 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2591 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2592 }
2593
2594 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2595 if (net_ratelimit())
2596 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2597 dev->name);
cd28ab6a
SH		 2598 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2599 }
2600}
2601
2602static void sky2_hw_intr(struct sky2_hw *hw)
2603{
555382cb 2604 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2605 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2606 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2607
2608 status &= hwmsk;
cd28ab6a 2609
793b883e 2610 if (status & Y2_IS_TIST_OV)
cd28ab6a 2611 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2612
2613 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2614 u16 pci_err;
2615
82637e80 2616 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2617 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2618 if (net_ratelimit())
555382cb 2619 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2620 pci_err);
cd28ab6a 2621
b32f40c4 2622 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2623 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2624 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2625 }
2626
2627 if (status & Y2_IS_PCI_EXP) {
d571b694 2628 /* PCI-Express uncorrectable Error occurred */
555382cb 2629 u32 err;
cd28ab6a 2630
82637e80 2631 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2632 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2633 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2634 0xfffffffful);
3be92a70 2635 if (net_ratelimit())
555382cb 2636 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2637
7782c8c4 2638 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2639 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2640 }
2641
2642 if (status & Y2_HWE_L1_MASK)
2643 sky2_hw_error(hw, 0, status);
2644 status >>= 8;
2645 if (status & Y2_HWE_L1_MASK)
2646 sky2_hw_error(hw, 1, status);
2647}
2648
2649static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2650{
2651 struct net_device *dev = hw->dev[port];
2652 struct sky2_port *sky2 = netdev_priv(dev);
2653 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2654
2655 if (netif_msg_intr(sky2))
2656 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2657 dev->name, status);
2658
a3caeada
SH		 2659 if (status & GM_IS_RX_CO_OV)
2660 gma_read16(hw, port, GM_RX_IRQ_SRC);
2661
2662 if (status & GM_IS_TX_CO_OV)
2663 gma_read16(hw, port, GM_TX_IRQ_SRC);
2664
cd28ab6a 2665 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2666 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2667 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2668 }
2669
2670 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2671 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2672 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2673 }
cd28ab6a
SH		 2674}
2675
40b01727 2676/* This should never happen it is a bug. */
c119731d 2677static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2678{
2679 struct net_device *dev = hw->dev[port];
c119731d 2680 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2681
c119731d
SH		 2682 dev_err(&hw->pdev->dev, PFX
2683 "%s: descriptor error q=%#x get=%u put=%u\n",
2684 dev->name, (unsigned) q, (unsigned) idx,
2685 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2686
40b01727 2687 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2688}
cd28ab6a 2689
75e80683
SH		 2690static int sky2_rx_hung(struct net_device *dev)
2691{
2692 struct sky2_port *sky2 = netdev_priv(dev);
2693 struct sky2_hw *hw = sky2->hw;
2694 unsigned port = sky2->port;
2695 unsigned rxq = rxqaddr[port];
2696 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2697 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2698 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2699 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2700
2701 /* If idle and MAC or PCI is stuck */
2702 if (sky2->check.last == dev->last_rx &&
2703 ((mac_rp == sky2->check.mac_rp &&
2704 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2705 /* Check if the PCI RX hang */
2706 (fifo_rp == sky2->check.fifo_rp &&
2707 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2708 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2709 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2710 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2711 return 1;
2712 } else {
2713 sky2->check.last = dev->last_rx;
2714 sky2->check.mac_rp = mac_rp;
2715 sky2->check.mac_lev = mac_lev;
2716 sky2->check.fifo_rp = fifo_rp;
2717 sky2->check.fifo_lev = fifo_lev;
2718 return 0;
2719 }
2720}
2721
32c2c300 2722static void sky2_watchdog(unsigned long arg)
d27ed387 2723{
01bd7564 2724 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2725
75e80683 2726 /* Check for lost IRQ once a second */
32c2c300 2727 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2728 napi_schedule(&hw->napi);
75e80683
SH		 2729 } else {
2730 int i, active = 0;
2731
2732 for (i = 0; i < hw->ports; i++) {
bea3348e 2733 struct net_device *dev = hw->dev[i];
75e80683
SH		 2734 if (!netif_running(dev))
2735 continue;
2736 ++active;
2737
2738 /* For chips with Rx FIFO, check if stuck */
39dbd958 2739 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2740 sky2_rx_hung(dev)) {
2741 pr_info(PFX "%s: receiver hang detected\n",
2742 dev->name);
2743 schedule_work(&hw->restart_work);
2744 return;
2745 }
2746 }
2747
2748 if (active == 0)
2749 return;
32c2c300 2750 }
01bd7564 2751
75e80683 2752 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2753}
2754
40b01727
SH		 2755/* Hardware/software error handling */
2756static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2757{
40b01727
SH		 2758 if (net_ratelimit())
2759 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2760
1e5f1283
SH		 2761 if (status & Y2_IS_HW_ERR)
2762 sky2_hw_intr(hw);
d257924e 2763
1e5f1283
SH		 2764 if (status & Y2_IS_IRQ_MAC1)
2765 sky2_mac_intr(hw, 0);
cd28ab6a 2766
1e5f1283
SH		 2767 if (status & Y2_IS_IRQ_MAC2)
2768 sky2_mac_intr(hw, 1);
cd28ab6a 2769
1e5f1283 2770 if (status & Y2_IS_CHK_RX1)
c119731d 2771 sky2_le_error(hw, 0, Q_R1);
d257924e 2772
1e5f1283 2773 if (status & Y2_IS_CHK_RX2)
c119731d 2774 sky2_le_error(hw, 1, Q_R2);
d257924e 2775
1e5f1283 2776 if (status & Y2_IS_CHK_TXA1)
c119731d 2777 sky2_le_error(hw, 0, Q_XA1);
d257924e 2778
1e5f1283 2779 if (status & Y2_IS_CHK_TXA2)
c119731d 2780 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2781}
2782
bea3348e 2783static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2784{
bea3348e 2785 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2786 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2787 int work_done = 0;
26691830 2788 u16 idx;
40b01727
SH		 2789
2790 if (unlikely(status & Y2_IS_ERROR))
2791 sky2_err_intr(hw, status);
2792
2793 if (status & Y2_IS_IRQ_PHY1)
2794 sky2_phy_intr(hw, 0);
2795
2796 if (status & Y2_IS_IRQ_PHY2)
2797 sky2_phy_intr(hw, 1);
cd28ab6a 2798
26691830
SH		 2799 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2800 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2801
2802 if (work_done >= work_limit)
26691830
SH		 2803 goto done;
2804 }
6f535763 2805
26691830
SH		 2806 napi_complete(napi);
2807 sky2_read32(hw, B0_Y2_SP_LISR);
2808done:
6f535763 2809
bea3348e 2810 return work_done;
e07b1aa8
SH		 2811}
2812
7d12e780 2813static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2814{
2815 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2816 u32 status;
2817
2818 /* Reading this mask interrupts as side effect */
2819 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2820 if (status == 0 || status == ~0)
2821 return IRQ_NONE;
793b883e 2822
e07b1aa8 2823 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2824
2825 napi_schedule(&hw->napi);
793b883e 2826
cd28ab6a
SH		 2827 return IRQ_HANDLED;
2828}
2829
2830#ifdef CONFIG_NET_POLL_CONTROLLER
2831static void sky2_netpoll(struct net_device *dev)
2832{
2833 struct sky2_port *sky2 = netdev_priv(dev);
2834
bea3348e 2835 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2836}
2837#endif
2838
2839/* Chip internal frequency for clock calculations */
05745c4a 2840static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2841{
793b883e 2842 switch (hw->chip_id) {
cd28ab6a 2843 case CHIP_ID_YUKON_EC:
5a5b1ea0 2844 case CHIP_ID_YUKON_EC_U:
93745494 2845 case CHIP_ID_YUKON_EX:
ed4d4161 2846 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2847 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2848 return 125;
2849
cd28ab6a 2850 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2851 return 100;
2852
2853 case CHIP_ID_YUKON_FE_P:
2854 return 50;
2855
2856 case CHIP_ID_YUKON_XL:
2857 return 156;
2858
2859 default:
2860 BUG();
cd28ab6a
SH		 2861 }
2862}
2863
fb17358f 2864static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2865{
fb17358f 2866 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2867}
2868
fb17358f 2869static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2870{
fb17358f 2871 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2872}
2873
fb17358f 2874
e3173832 2875static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2876{
b89165f2 2877 u8 t8;
cd28ab6a 2878
167f53d0 2879 /* Enable all clocks and check for bad PCI access */
b32f40c4 2880 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2881
cd28ab6a 2882 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2883
cd28ab6a 2884 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2885 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2886
2887 switch(hw->chip_id) {
2888 case CHIP_ID_YUKON_XL:
39dbd958 2889 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2890 break;
2891
2892 case CHIP_ID_YUKON_EC_U:
2893 hw->flags = SKY2_HW_GIGABIT
2894 | SKY2_HW_NEWER_PHY
2895 | SKY2_HW_ADV_POWER_CTL;
2896 break;
2897
2898 case CHIP_ID_YUKON_EX:
2899 hw->flags = SKY2_HW_GIGABIT
2900 | SKY2_HW_NEWER_PHY
2901 | SKY2_HW_NEW_LE
2902 | SKY2_HW_ADV_POWER_CTL;
2903
2904 /* New transmit checksum */
2905 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2906 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2907 break;
2908
2909 case CHIP_ID_YUKON_EC:
2910 /* This rev is really old, and requires untested workarounds */
2911 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2912 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2913 return -EOPNOTSUPP;
2914 }
39dbd958 2915 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2916 break;
2917
2918 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2919 break;
2920
05745c4a
SH		 2921 case CHIP_ID_YUKON_FE_P:
2922 hw->flags = SKY2_HW_NEWER_PHY
2923 | SKY2_HW_NEW_LE
2924 | SKY2_HW_AUTO_TX_SUM
2925 | SKY2_HW_ADV_POWER_CTL;
2926 break;
ed4d4161
SH		 2927
2928 case CHIP_ID_YUKON_SUPR:
2929 hw->flags = SKY2_HW_GIGABIT
2930 | SKY2_HW_NEWER_PHY
2931 | SKY2_HW_NEW_LE
2932 | SKY2_HW_AUTO_TX_SUM
2933 | SKY2_HW_ADV_POWER_CTL;
2934 break;
2935
0ce8b98d
SH		 2936 case CHIP_ID_YUKON_UL_2:
2937 hw->flags = SKY2_HW_GIGABIT
2938 | SKY2_HW_ADV_POWER_CTL;
2939 break;
2940
ea76e635 2941 default:
b02a9258
SH		 2942 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2943 hw->chip_id);
cd28ab6a
SH		 2944 return -EOPNOTSUPP;
2945 }
2946
ea76e635
SH		 2947 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2948 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2949 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2950
e3173832
SH		 2951 hw->ports = 1;
2952 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2953 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2954 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2955 ++hw->ports;
2956 }
2957
74a61ebf
MM		 2958 if (sky2_read8(hw, B2_E_0))
2959 hw->flags |= SKY2_HW_RAM_BUFFER;
2960
e3173832
SH		 2961 return 0;
2962}
2963
2964static void sky2_reset(struct sky2_hw *hw)
2965{
555382cb 2966 struct pci_dev *pdev = hw->pdev;
e3173832 2967 u16 status;
555382cb
SH		 2968 int i, cap;
2969 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2970
cd28ab6a 2971 /* disable ASF */
4f44d8ba
SH		 2972 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2973 status = sky2_read16(hw, HCU_CCSR);
2974 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2975 HCU_CCSR_UC_STATE_MSK);
2976 sky2_write16(hw, HCU_CCSR, status);
2977 } else
2978 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2979 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2980
2981 /* do a SW reset */
2982 sky2_write8(hw, B0_CTST, CS_RST_SET);
2983 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2984
ac93a394
SH		 2985 /* allow writes to PCI config */
2986 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2987
cd28ab6a 2988 /* clear PCI errors, if any */
b32f40c4 2989 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2990 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2991 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2992
2993 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2994
555382cb
SH		 2995 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2996 if (cap) {
7782c8c4
SH		 2997 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2998 0xfffffffful);
555382cb
SH		 2999
3000 /* If error bit is stuck on ignore it */
3001 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3002 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3003 else
555382cb
SH		 3004 hwe_mask |= Y2_IS_PCI_EXP;
3005 }
cd28ab6a 3006
ae306cca 3007 sky2_power_on(hw);
82637e80 3008 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3009
3010 for (i = 0; i < hw->ports; i++) {
3011 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3012 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3013
ed4d4161
SH		 3014 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3015 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3016 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3017 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3018 | GMC_BYP_RETR_ON);
877c8570
SH		 3019
3020 }
3021
3022 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3023 /* enable MACSec clock gating */
3024 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3025 }
3026
793b883e
SH		 3027 /* Clear I2C IRQ noise */
3028 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3029
3030 /* turn off hardware timer (unused) */
3031 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3032 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3033
69634ee7
SH		 3034 /* Turn off descriptor polling */
3035 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3036
3037 /* Turn off receive timestamp */
3038 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3039 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3040
3041 /* enable the Tx Arbiters */
3042 for (i = 0; i < hw->ports; i++)
3043 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3044
3045 /* Initialize ram interface */
3046 for (i = 0; i < hw->ports; i++) {
793b883e 3047 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3048
3049 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3050 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3051 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3052 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3053 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3054 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3055 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3056 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3057 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3058 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3059 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3060 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3061 }
3062
555382cb 3063 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3064
cd28ab6a 3065 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3066 sky2_gmac_reset(hw, i);
cd28ab6a 3067
cd28ab6a
SH		 3068 memset(hw->st_le, 0, STATUS_LE_BYTES);
3069 hw->st_idx = 0;
3070
3071 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3072 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3073
3074 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3075 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3076
3077 /* Set the list last index */
793b883e 3078 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3079
290d4de5
SH		 3080 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3081 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3082
290d4de5
SH		 3083 /* set Status-FIFO ISR watermark */
3084 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3085 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3086 else
3087 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3088
290d4de5 3089 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3090 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3091 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3092
793b883e 3093 /* enable status unit */
cd28ab6a
SH		 3094 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3095
3096 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3097 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3098 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3099}
3100
af18d8b8
SH		 3101/* Take device down (offline).
3102 * Equivalent to doing dev_stop() but this does not
3103 * inform upper layers of the transistion.
3104 */
3105static void sky2_detach(struct net_device *dev)
3106{
3107 if (netif_running(dev)) {
3108 netif_device_detach(dev); /* stop txq */
3109 sky2_down(dev);
3110 }
3111}
3112
3113/* Bring device back after doing sky2_detach */
3114static int sky2_reattach(struct net_device *dev)
3115{
3116 int err = 0;
3117
3118 if (netif_running(dev)) {
3119 err = sky2_up(dev);
3120 if (err) {
3121 printk(KERN_INFO PFX "%s: could not restart %d\n",
3122 dev->name, err);
3123 dev_close(dev);
3124 } else {
3125 netif_device_attach(dev);
3126 sky2_set_multicast(dev);
3127 }
3128 }
3129
3130 return err;
3131}
3132
81906791
SH		 3133static void sky2_restart(struct work_struct *work)
3134{
3135 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3136 int i;
81906791 3137
81906791 3138 rtnl_lock();
af18d8b8
SH		 3139 for (i = 0; i < hw->ports; i++)
3140 sky2_detach(hw->dev[i]);
81906791 3141
8cfcbe99
SH		 3142 napi_disable(&hw->napi);
3143 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3144 sky2_reset(hw);
3145 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3146 napi_enable(&hw->napi);
81906791 3147
af18d8b8
SH		 3148 for (i = 0; i < hw->ports; i++)
3149 sky2_reattach(hw->dev[i]);
81906791 3150
81906791
SH		 3151 rtnl_unlock();
3152}
3153
e3173832
SH		 3154static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3155{
3156 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3157}
3158
3159static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3160{
3161 const struct sky2_port *sky2 = netdev_priv(dev);
3162
3163 wol->supported = sky2_wol_supported(sky2->hw);
3164 wol->wolopts = sky2->wol;
3165}
3166
3167static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3168{
3169 struct sky2_port *sky2 = netdev_priv(dev);
3170 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3171
9d731d77
RW		 3172 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3173 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3174 return -EOPNOTSUPP;
3175
3176 sky2->wol = wol->wolopts;
3177
05745c4a
SH		 3178 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3179 hw->chip_id == CHIP_ID_YUKON_EX ||
3180 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3181 sky2_write32(hw, B0_CTST, sky2->wol
3182 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3183
9d731d77
RW		 3184 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3185
e3173832
SH		 3186 if (!netif_running(dev))
3187 sky2_wol_init(sky2);
cd28ab6a
SH		 3188 return 0;
3189}
3190
28bd181a 3191static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3192{
b89165f2
SH		 3193 if (sky2_is_copper(hw)) {
3194 u32 modes = SUPPORTED_10baseT_Half
3195 | SUPPORTED_10baseT_Full
3196 | SUPPORTED_100baseT_Half
3197 | SUPPORTED_100baseT_Full
3198 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3199
ea76e635 3200 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3201 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3202 | SUPPORTED_1000baseT_Full;
3203 return modes;
cd28ab6a 3204 } else
b89165f2
SH		 3205 return SUPPORTED_1000baseT_Half
3206 | SUPPORTED_1000baseT_Full
3207 | SUPPORTED_Autoneg
3208 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3209}
3210
793b883e 3211static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3212{
3213 struct sky2_port *sky2 = netdev_priv(dev);
3214 struct sky2_hw *hw = sky2->hw;
3215
3216 ecmd->transceiver = XCVR_INTERNAL;
3217 ecmd->supported = sky2_supported_modes(hw);
3218 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3219 if (sky2_is_copper(hw)) {
cd28ab6a 3220 ecmd->port = PORT_TP;
b89165f2
SH		 3221 ecmd->speed = sky2->speed;
3222 } else {
3223 ecmd->speed = SPEED_1000;
cd28ab6a 3224 ecmd->port = PORT_FIBRE;
b89165f2 3225 }
cd28ab6a
SH		 3226
3227 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3228 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3229 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3230 ecmd->duplex = sky2->duplex;
3231 return 0;
3232}
3233
3234static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3235{
3236 struct sky2_port *sky2 = netdev_priv(dev);
3237 const struct sky2_hw *hw = sky2->hw;
3238 u32 supported = sky2_supported_modes(hw);
3239
3240 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3241 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3242 ecmd->advertising = supported;
3243 sky2->duplex = -1;
3244 sky2->speed = -1;
3245 } else {
3246 u32 setting;
3247
793b883e 3248 switch (ecmd->speed) {
cd28ab6a
SH		 3249 case SPEED_1000:
3250 if (ecmd->duplex == DUPLEX_FULL)
3251 setting = SUPPORTED_1000baseT_Full;
3252 else if (ecmd->duplex == DUPLEX_HALF)
3253 setting = SUPPORTED_1000baseT_Half;
3254 else
3255 return -EINVAL;
3256 break;
3257 case SPEED_100:
3258 if (ecmd->duplex == DUPLEX_FULL)
3259 setting = SUPPORTED_100baseT_Full;
3260 else if (ecmd->duplex == DUPLEX_HALF)
3261 setting = SUPPORTED_100baseT_Half;
3262 else
3263 return -EINVAL;
3264 break;
3265
3266 case SPEED_10:
3267 if (ecmd->duplex == DUPLEX_FULL)
3268 setting = SUPPORTED_10baseT_Full;
3269 else if (ecmd->duplex == DUPLEX_HALF)
3270 setting = SUPPORTED_10baseT_Half;
3271 else
3272 return -EINVAL;
3273 break;
3274 default:
3275 return -EINVAL;
3276 }
3277
3278 if ((setting & supported) == 0)
3279 return -EINVAL;
3280
3281 sky2->speed = ecmd->speed;
3282 sky2->duplex = ecmd->duplex;
0ea065e5 3283 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3284 }
3285
cd28ab6a
SH		 3286 sky2->advertising = ecmd->advertising;
3287
d1b139c0 3288 if (netif_running(dev)) {
1b537565 3289 sky2_phy_reinit(sky2);
d1b139c0
SH		 3290 sky2_set_multicast(dev);
3291 }
cd28ab6a
SH		 3292
3293 return 0;
3294}
3295
3296static void sky2_get_drvinfo(struct net_device *dev,
3297 struct ethtool_drvinfo *info)
3298{
3299 struct sky2_port *sky2 = netdev_priv(dev);
3300
3301 strcpy(info->driver, DRV_NAME);
3302 strcpy(info->version, DRV_VERSION);
3303 strcpy(info->fw_version, "N/A");
3304 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3305}
3306
3307static const struct sky2_stat {
793b883e
SH		 3308 char name[ETH_GSTRING_LEN];
3309 u16 offset;
cd28ab6a
SH		 3310} sky2_stats[] = {
3311 { "tx_bytes", GM_TXO_OK_HI },
3312 { "rx_bytes", GM_RXO_OK_HI },
3313 { "tx_broadcast", GM_TXF_BC_OK },
3314 { "rx_broadcast", GM_RXF_BC_OK },
3315 { "tx_multicast", GM_TXF_MC_OK },
3316 { "rx_multicast", GM_RXF_MC_OK },
3317 { "tx_unicast", GM_TXF_UC_OK },
3318 { "rx_unicast", GM_RXF_UC_OK },
3319 { "tx_mac_pause", GM_TXF_MPAUSE },
3320 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3321 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3322 { "late_collision",GM_TXF_LAT_COL },
3323 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3324 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3325 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3326
d2604540 3327 { "rx_short", GM_RXF_SHT },
cd28ab6a 3328 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3329 { "rx_64_byte_packets", GM_RXF_64B },
3330 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3331 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3332 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3333 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3334 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3335 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3336 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3337 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3338 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3339 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3340
3341 { "tx_64_byte_packets", GM_TXF_64B },
3342 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3343 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3344 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3345 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3346 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3347 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3348 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3349};
3350
cd28ab6a
SH		 3351static u32 sky2_get_rx_csum(struct net_device *dev)
3352{
3353 struct sky2_port *sky2 = netdev_priv(dev);
3354
0ea065e5 3355 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3356}
3357
3358static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3359{
3360 struct sky2_port *sky2 = netdev_priv(dev);
3361
0ea065e5
SH		 3362 if (data)
3363 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3364 else
3365 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3366
cd28ab6a
SH		 3367 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3368 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3369
3370 return 0;
3371}
3372
3373static u32 sky2_get_msglevel(struct net_device *netdev)
3374{
3375 struct sky2_port *sky2 = netdev_priv(netdev);
3376 return sky2->msg_enable;
3377}
3378
9a7ae0a9
SH		 3379static int sky2_nway_reset(struct net_device *dev)
3380{
3381 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3382
0ea065e5 3383 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3384 return -EINVAL;
3385
1b537565 3386 sky2_phy_reinit(sky2);
d1b139c0 3387 sky2_set_multicast(dev);
9a7ae0a9
SH		 3388
3389 return 0;
3390}
3391
793b883e 3392static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3393{
3394 struct sky2_hw *hw = sky2->hw;
3395 unsigned port = sky2->port;
3396 int i;
3397
3398 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3399 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3400 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3401 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3402
793b883e 3403 for (i = 2; i < count; i++)
cd28ab6a
SH		 3404 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3405}
3406
cd28ab6a
SH		 3407static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3408{
3409 struct sky2_port *sky2 = netdev_priv(netdev);
3410 sky2->msg_enable = value;
3411}
3412
b9f2c044 3413static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3414{
b9f2c044
JG		 3415 switch (sset) {
3416 case ETH_SS_STATS:
3417 return ARRAY_SIZE(sky2_stats);
3418 default:
3419 return -EOPNOTSUPP;
3420 }
cd28ab6a
SH		 3421}
3422
3423static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3424 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3425{
3426 struct sky2_port *sky2 = netdev_priv(dev);
3427
793b883e 3428 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3429}
3430
793b883e 3431static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3432{
3433 int i;
3434
3435 switch (stringset) {
3436 case ETH_SS_STATS:
3437 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3438 memcpy(data + i * ETH_GSTRING_LEN,
3439 sky2_stats[i].name, ETH_GSTRING_LEN);
3440 break;
3441 }
3442}
3443
cd28ab6a
SH		 3444static int sky2_set_mac_address(struct net_device *dev, void *p)
3445{
3446 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3447 struct sky2_hw *hw = sky2->hw;
3448 unsigned port = sky2->port;
3449 const struct sockaddr *addr = p;
cd28ab6a
SH		 3450
3451 if (!is_valid_ether_addr(addr->sa_data))
3452 return -EADDRNOTAVAIL;
3453
cd28ab6a 3454 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3455 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3456 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3457 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3458 dev->dev_addr, ETH_ALEN);
1b537565 3459
a8ab1ec0
SH		 3460 /* virtual address for data */
3461 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3462
3463 /* physical address: used for pause frames */
3464 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3465
3466 return 0;
cd28ab6a
SH		 3467}
3468
a052b52f
SH		 3469static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3470{
3471 u32 bit;
3472
3473 bit = ether_crc(ETH_ALEN, addr) & 63;
3474 filter[bit >> 3] |= 1 << (bit & 7);
3475}
3476
cd28ab6a
SH		 3477static void sky2_set_multicast(struct net_device *dev)
3478{
3479 struct sky2_port *sky2 = netdev_priv(dev);
3480 struct sky2_hw *hw = sky2->hw;
3481 unsigned port = sky2->port;
3482 struct dev_mc_list *list = dev->mc_list;
3483 u16 reg;
3484 u8 filter[8];
a052b52f
SH		 3485 int rx_pause;
3486 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3487
a052b52f 3488 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3489 memset(filter, 0, sizeof(filter));
3490
3491 reg = gma_read16(hw, port, GM_RX_CTRL);
3492 reg |= GM_RXCR_UCF_ENA;
3493
d571b694 3494 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3495 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3496 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3497 memset(filter, 0xff, sizeof(filter));
a052b52f 3498 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3499 reg &= ~GM_RXCR_MCF_ENA;
3500 else {
3501 int i;
3502 reg |= GM_RXCR_MCF_ENA;
3503
a052b52f
SH		 3504 if (rx_pause)
3505 sky2_add_filter(filter, pause_mc_addr);
3506
3507 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3508 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3509 }
3510
cd28ab6a 3511 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3512 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3513 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3514 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3515 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3516 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3517 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3518 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3519
3520 gma_write16(hw, port, GM_RX_CTRL, reg);
3521}
3522
3523/* Can have one global because blinking is controlled by
3524 * ethtool and that is always under RTNL mutex
3525 */
a84d0a3d 3526static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3527{
a84d0a3d
SH		 3528 struct sky2_hw *hw = sky2->hw;
3529 unsigned port = sky2->port;
793b883e 3530
a84d0a3d
SH		 3531 spin_lock_bh(&sky2->phy_lock);
3532 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3533 hw->chip_id == CHIP_ID_YUKON_EX ||
3534 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3535 u16 pg;
793b883e
SH		 3536 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3538
a84d0a3d
SH		 3539 switch (mode) {
3540 case MO_LED_OFF:
3541 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3542 PHY_M_LEDC_LOS_CTRL(8) |
3543 PHY_M_LEDC_INIT_CTRL(8) |
3544 PHY_M_LEDC_STA1_CTRL(8) |
3545 PHY_M_LEDC_STA0_CTRL(8));
3546 break;
3547 case MO_LED_ON:
3548 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3549 PHY_M_LEDC_LOS_CTRL(9) |
3550 PHY_M_LEDC_INIT_CTRL(9) |
3551 PHY_M_LEDC_STA1_CTRL(9) |
3552 PHY_M_LEDC_STA0_CTRL(9));
3553 break;
3554 case MO_LED_BLINK:
3555 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3556 PHY_M_LEDC_LOS_CTRL(0xa) |
3557 PHY_M_LEDC_INIT_CTRL(0xa) |
3558 PHY_M_LEDC_STA1_CTRL(0xa) |
3559 PHY_M_LEDC_STA0_CTRL(0xa));
3560 break;
3561 case MO_LED_NORM:
3562 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3563 PHY_M_LEDC_LOS_CTRL(1) |
3564 PHY_M_LEDC_INIT_CTRL(8) |
3565 PHY_M_LEDC_STA1_CTRL(7) |
3566 PHY_M_LEDC_STA0_CTRL(7));
3567 }
793b883e 3568
a84d0a3d
SH		 3569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3570 } else
7d2e3cb7 3571 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3572 PHY_M_LED_MO_DUP(mode) |
3573 PHY_M_LED_MO_10(mode) |
3574 PHY_M_LED_MO_100(mode) |
3575 PHY_M_LED_MO_1000(mode) |
3576 PHY_M_LED_MO_RX(mode) |
3577 PHY_M_LED_MO_TX(mode));
3578
3579 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3580}
3581
3582/* blink LED's for finding board */
3583static int sky2_phys_id(struct net_device *dev, u32 data)
3584{
3585 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3586 unsigned int i;
cd28ab6a 3587
a84d0a3d
SH		 3588 if (data == 0)
3589 data = UINT_MAX;
cd28ab6a 3590
a84d0a3d
SH		 3591 for (i = 0; i < data; i++) {
3592 sky2_led(sky2, MO_LED_ON);
3593 if (msleep_interruptible(500))
3594 break;
3595 sky2_led(sky2, MO_LED_OFF);
3596 if (msleep_interruptible(500))
3597 break;
793b883e 3598 }
a84d0a3d 3599 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3600
3601 return 0;
3602}
3603
3604static void sky2_get_pauseparam(struct net_device *dev,
3605 struct ethtool_pauseparam *ecmd)
3606{
3607 struct sky2_port *sky2 = netdev_priv(dev);
3608
16ad91e1
SH		 3609 switch (sky2->flow_mode) {
3610 case FC_NONE:
3611 ecmd->tx_pause = ecmd->rx_pause = 0;
3612 break;
3613 case FC_TX:
3614 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3615 break;
3616 case FC_RX:
3617 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3618 break;
3619 case FC_BOTH:
3620 ecmd->tx_pause = ecmd->rx_pause = 1;
3621 }
3622
0ea065e5
SH		 3623 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3624 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3625}
3626
3627static int sky2_set_pauseparam(struct net_device *dev,
3628 struct ethtool_pauseparam *ecmd)
3629{
3630 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3631
0ea065e5
SH		 3632 if (ecmd->autoneg == AUTONEG_ENABLE)
3633 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3634 else
3635 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3636
16ad91e1 3637 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3638
16ad91e1
SH		 3639 if (netif_running(dev))
3640 sky2_phy_reinit(sky2);
cd28ab6a 3641
2eaba1a2 3642 return 0;
cd28ab6a
SH		 3643}
3644
fb17358f
SH		 3645static int sky2_get_coalesce(struct net_device *dev,
3646 struct ethtool_coalesce *ecmd)
3647{
3648 struct sky2_port *sky2 = netdev_priv(dev);
3649 struct sky2_hw *hw = sky2->hw;
3650
3651 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3652 ecmd->tx_coalesce_usecs = 0;
3653 else {
3654 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3655 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3656 }
3657 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3658
3659 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3660 ecmd->rx_coalesce_usecs = 0;
3661 else {
3662 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3663 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3664 }
3665 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3666
3667 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3668 ecmd->rx_coalesce_usecs_irq = 0;
3669 else {
3670 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3671 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3672 }
3673
3674 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3675
3676 return 0;
3677}
3678
3679/* Note: this affect both ports */
3680static int sky2_set_coalesce(struct net_device *dev,
3681 struct ethtool_coalesce *ecmd)
3682{
3683 struct sky2_port *sky2 = netdev_priv(dev);
3684 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3685 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3686
77b3d6a2
SH		 3687 if (ecmd->tx_coalesce_usecs > tmax ||
3688 ecmd->rx_coalesce_usecs > tmax ||
3689 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3690 return -EINVAL;
3691
ee5f68fe 3692 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3693 return -EINVAL;
ff81fbbe 3694 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3695 return -EINVAL;
ff81fbbe 3696 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3697 return -EINVAL;
3698
3699 if (ecmd->tx_coalesce_usecs == 0)
3700 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3701 else {
3702 sky2_write32(hw, STAT_TX_TIMER_INI,
3703 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3704 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3705 }
3706 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3707
3708 if (ecmd->rx_coalesce_usecs == 0)
3709 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3710 else {
3711 sky2_write32(hw, STAT_LEV_TIMER_INI,
3712 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3713 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3714 }
3715 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3716
3717 if (ecmd->rx_coalesce_usecs_irq == 0)
3718 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3719 else {
d28d4870 3720 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3721 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3722 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3723 }
3724 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3725 return 0;
3726}
3727
793b883e
SH		 3728static void sky2_get_ringparam(struct net_device *dev,
3729 struct ethtool_ringparam *ering)
3730{
3731 struct sky2_port *sky2 = netdev_priv(dev);
3732
3733 ering->rx_max_pending = RX_MAX_PENDING;
3734 ering->rx_mini_max_pending = 0;
3735 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3736 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3737
3738 ering->rx_pending = sky2->rx_pending;
3739 ering->rx_mini_pending = 0;
3740 ering->rx_jumbo_pending = 0;
3741 ering->tx_pending = sky2->tx_pending;
3742}
3743
3744static int sky2_set_ringparam(struct net_device *dev,
3745 struct ethtool_ringparam *ering)
3746{
3747 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3748
3749 if (ering->rx_pending > RX_MAX_PENDING ||
3750 ering->rx_pending < 8 ||
ee5f68fe
SH		 3751 ering->tx_pending < TX_MIN_PENDING ||
3752 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3753 return -EINVAL;
3754
af18d8b8 3755 sky2_detach(dev);
793b883e
SH		 3756
3757 sky2->rx_pending = ering->rx_pending;
3758 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3759 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3760
af18d8b8 3761 return sky2_reattach(dev);
793b883e
SH		 3762}
3763
793b883e
SH		 3764static int sky2_get_regs_len(struct net_device *dev)
3765{
6e4cbb34 3766 return 0x4000;
793b883e
SH		 3767}
3768
3769/*
3770 * Returns copy of control register region
3ead5db7 3771 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3772 */
3773static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3774 void *p)
3775{
3776 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3777 const void __iomem *io = sky2->hw->regs;
295b54c4 3778 unsigned int b;
793b883e
SH		 3779
3780 regs->version = 1;
793b883e 3781
295b54c4
SH		 3782 for (b = 0; b < 128; b++) {
3783 /* This complicated switch statement is to make sure and
3784 * only access regions that are unreserved.
3785 * Some blocks are only valid on dual port cards.
3786 * and block 3 has some special diagnostic registers that
3787 * are poison.
3788 */
3789 switch (b) {
3790 case 3:
3791 /* skip diagnostic ram region */
3792 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3793 break;
3ead5db7 3794
295b54c4
SH		 3795 /* dual port cards only */
3796 case 5: /* Tx Arbiter 2 */
3797 case 9: /* RX2 */
3798 case 14 ... 15: /* TX2 */
3799 case 17: case 19: /* Ram Buffer 2 */
3800 case 22 ... 23: /* Tx Ram Buffer 2 */
3801 case 25: /* Rx MAC Fifo 1 */
3802 case 27: /* Tx MAC Fifo 2 */
3803 case 31: /* GPHY 2 */
3804 case 40 ... 47: /* Pattern Ram 2 */
3805 case 52: case 54: /* TCP Segmentation 2 */
3806 case 112 ... 116: /* GMAC 2 */
3807 if (sky2->hw->ports == 1)
3808 goto reserved;
3809 /* fall through */
3810 case 0: /* Control */
3811 case 2: /* Mac address */
3812 case 4: /* Tx Arbiter 1 */
3813 case 7: /* PCI express reg */
3814 case 8: /* RX1 */
3815 case 12 ... 13: /* TX1 */
3816 case 16: case 18:/* Rx Ram Buffer 1 */
3817 case 20 ... 21: /* Tx Ram Buffer 1 */
3818 case 24: /* Rx MAC Fifo 1 */
3819 case 26: /* Tx MAC Fifo 1 */
3820 case 28 ... 29: /* Descriptor and status unit */
3821 case 30: /* GPHY 1*/
3822 case 32 ... 39: /* Pattern Ram 1 */
3823 case 48: case 50: /* TCP Segmentation 1 */
3824 case 56 ... 60: /* PCI space */
3825 case 80 ... 84: /* GMAC 1 */
3826 memcpy_fromio(p, io, 128);
3827 break;
3828 default:
3829reserved:
3830 memset(p, 0, 128);
3831 }
3ead5db7 3832
295b54c4
SH		 3833 p += 128;
3834 io += 128;
3835 }
793b883e 3836}
cd28ab6a 3837
b628ed98
SH		 3838/* In order to do Jumbo packets on these chips, need to turn off the
3839 * transmit store/forward. Therefore checksum offload won't work.
3840 */
3841static int no_tx_offload(struct net_device *dev)
3842{
3843 const struct sky2_port *sky2 = netdev_priv(dev);
3844 const struct sky2_hw *hw = sky2->hw;
3845
69161611 3846 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3847}
3848
3849static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3850{
3851 if (data && no_tx_offload(dev))
3852 return -EINVAL;
3853
3854 return ethtool_op_set_tx_csum(dev, data);
3855}
3856
3857
3858static int sky2_set_tso(struct net_device *dev, u32 data)
3859{
3860 if (data && no_tx_offload(dev))
3861 return -EINVAL;
3862
3863 return ethtool_op_set_tso(dev, data);
3864}
3865
f4331a6d
SH		 3866static int sky2_get_eeprom_len(struct net_device *dev)
3867{
3868 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3869 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3870 u16 reg2;
3871
b32f40c4 3872 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3873 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3874}
3875
1413235c 3876static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3877{
1413235c 3878 unsigned long start = jiffies;
f4331a6d 3879
1413235c
SH		 3880 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3881 /* Can take up to 10.6 ms for write */
3882 if (time_after(jiffies, start + HZ/4)) {
3883 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3884 return -ETIMEDOUT;
3885 }
3886 mdelay(1);
3887 }
167f53d0 3888
1413235c
SH		 3889 return 0;
3890}
167f53d0 3891
1413235c
SH		 3892static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3893 u16 offset, size_t length)
3894{
3895 int rc = 0;
3896
3897 while (length > 0) {
3898 u32 val;
3899
3900 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3901 rc = sky2_vpd_wait(hw, cap, 0);
3902 if (rc)
3903 break;
3904
3905 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3906
3907 memcpy(data, &val, min(sizeof(val), length));
3908 offset += sizeof(u32);
3909 data += sizeof(u32);
3910 length -= sizeof(u32);
3911 }
3912
3913 return rc;
f4331a6d
SH		 3914}
3915
1413235c
SH		 3916static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3917 u16 offset, unsigned int length)
f4331a6d 3918{
1413235c
SH		 3919 unsigned int i;
3920 int rc = 0;
3921
3922 for (i = 0; i < length; i += sizeof(u32)) {
3923 u32 val = *(u32 *)(data + i);
3924
3925 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3926 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3927
3928 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3929 if (rc)
3930 break;
3931 }
3932 return rc;
f4331a6d
SH		 3933}
3934
3935static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3936 u8 *data)
3937{
3938 struct sky2_port *sky2 = netdev_priv(dev);
3939 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3940
3941 if (!cap)
3942 return -EINVAL;
3943
3944 eeprom->magic = SKY2_EEPROM_MAGIC;
3945
1413235c 3946 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3947}
3948
3949static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3950 u8 *data)
3951{
3952 struct sky2_port *sky2 = netdev_priv(dev);
3953 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3954
3955 if (!cap)
3956 return -EINVAL;
3957
3958 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3959 return -EINVAL;
3960
1413235c
SH		 3961 /* Partial writes not supported */
3962 if ((eeprom->offset & 3) || (eeprom->len & 3))
3963 return -EINVAL;
f4331a6d 3964
1413235c 3965 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3966}
3967
3968
7282d491 3969static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3970 .get_settings = sky2_get_settings,
3971 .set_settings = sky2_set_settings,
3972 .get_drvinfo = sky2_get_drvinfo,
3973 .get_wol = sky2_get_wol,
3974 .set_wol = sky2_set_wol,
3975 .get_msglevel = sky2_get_msglevel,
3976 .set_msglevel = sky2_set_msglevel,
3977 .nway_reset = sky2_nway_reset,
3978 .get_regs_len = sky2_get_regs_len,
3979 .get_regs = sky2_get_regs,
3980 .get_link = ethtool_op_get_link,
3981 .get_eeprom_len = sky2_get_eeprom_len,
3982 .get_eeprom = sky2_get_eeprom,
3983 .set_eeprom = sky2_set_eeprom,
f4331a6d 3984 .set_sg = ethtool_op_set_sg,
f4331a6d 3985 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3986 .set_tso = sky2_set_tso,
3987 .get_rx_csum = sky2_get_rx_csum,
3988 .set_rx_csum = sky2_set_rx_csum,
3989 .get_strings = sky2_get_strings,
3990 .get_coalesce = sky2_get_coalesce,
3991 .set_coalesce = sky2_set_coalesce,
3992 .get_ringparam = sky2_get_ringparam,
3993 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3994 .get_pauseparam = sky2_get_pauseparam,
3995 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3996 .phys_id = sky2_phys_id,
b9f2c044 3997 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3998 .get_ethtool_stats = sky2_get_ethtool_stats,
3999};
4000
3cf26753
SH		 4001#ifdef CONFIG_SKY2_DEBUG
4002
4003static struct dentry *sky2_debug;
4004
e4c2abe2
SH		 4005
4006/*
4007 * Read and parse the first part of Vital Product Data
4008 */
4009#define VPD_SIZE 128
4010#define VPD_MAGIC 0x82
4011
4012static const struct vpd_tag {
4013 char tag[2];
4014 char *label;
4015} vpd_tags[] = {
4016 { "PN", "Part Number" },
4017 { "EC", "Engineering Level" },
4018 { "MN", "Manufacturer" },
4019 { "SN", "Serial Number" },
4020 { "YA", "Asset Tag" },
4021 { "VL", "First Error Log Message" },
4022 { "VF", "Second Error Log Message" },
4023 { "VB", "Boot Agent ROM Configuration" },
4024 { "VE", "EFI UNDI Configuration" },
4025};
4026
4027static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4028{
4029 size_t vpd_size;
4030 loff_t offs;
4031 u8 len;
4032 unsigned char *buf;
4033 u16 reg2;
4034
4035 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4036 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4037
4038 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4039 buf = kmalloc(vpd_size, GFP_KERNEL);
4040 if (!buf) {
4041 seq_puts(seq, "no memory!\n");
4042 return;
4043 }
4044
4045 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4046 seq_puts(seq, "VPD read failed\n");
4047 goto out;
4048 }
4049
4050 if (buf[0] != VPD_MAGIC) {
4051 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4052 goto out;
4053 }
4054 len = buf[1];
4055 if (len == 0 || len > vpd_size - 4) {
4056 seq_printf(seq, "Invalid id length: %d\n", len);
4057 goto out;
4058 }
4059
4060 seq_printf(seq, "%.*s\n", len, buf + 3);
4061 offs = len + 3;
4062
4063 while (offs < vpd_size - 4) {
4064 int i;
4065
4066 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4067 break;
4068 len = buf[offs + 2];
4069 if (offs + len + 3 >= vpd_size)
4070 break;
4071
4072 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4073 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4074 seq_printf(seq, " %s: %.*s\n",
4075 vpd_tags[i].label, len, buf + offs + 3);
4076 break;
4077 }
4078 }
4079 offs += len + 3;
4080 }
4081out:
4082 kfree(buf);
4083}
4084
3cf26753
SH		 4085static int sky2_debug_show(struct seq_file *seq, void *v)
4086{
4087 struct net_device *dev = seq->private;
4088 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4089 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4090 unsigned port = sky2->port;
4091 unsigned idx, last;
4092 int sop;
4093
e4c2abe2 4094 sky2_show_vpd(seq, hw);
3cf26753 4095
e4c2abe2 4096 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4097 sky2_read32(hw, B0_ISRC),
4098 sky2_read32(hw, B0_IMSK),
4099 sky2_read32(hw, B0_Y2_SP_ICR));
4100
e4c2abe2
SH		 4101 if (!netif_running(dev)) {
4102 seq_printf(seq, "network not running\n");
4103 return 0;
4104 }
4105
bea3348e 4106 napi_disable(&hw->napi);
3cf26753
SH		 4107 last = sky2_read16(hw, STAT_PUT_IDX);
4108
4109 if (hw->st_idx == last)
4110 seq_puts(seq, "Status ring (empty)\n");
4111 else {
4112 seq_puts(seq, "Status ring\n");
4113 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4114 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4115 const struct sky2_status_le *le = hw->st_le + idx;
4116 seq_printf(seq, "[%d] %#x %d %#x\n",
4117 idx, le->opcode, le->length, le->status);
4118 }
4119 seq_puts(seq, "\n");
4120 }
4121
4122 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4123 sky2->tx_cons, sky2->tx_prod,
4124 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4125 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4126
4127 /* Dump contents of tx ring */
4128 sop = 1;
ee5f68fe
SH		 4129 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4130 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4131 const struct sky2_tx_le *le = sky2->tx_le + idx;
4132 u32 a = le32_to_cpu(le->addr);
4133
4134 if (sop)
4135 seq_printf(seq, "%u:", idx);
4136 sop = 0;
4137
4138 switch(le->opcode & ~HW_OWNER) {
4139 case OP_ADDR64:
4140 seq_printf(seq, " %#x:", a);
4141 break;
4142 case OP_LRGLEN:
4143 seq_printf(seq, " mtu=%d", a);
4144 break;
4145 case OP_VLAN:
4146 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4147 break;
4148 case OP_TCPLISW:
4149 seq_printf(seq, " csum=%#x", a);
4150 break;
4151 case OP_LARGESEND:
4152 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4153 break;
4154 case OP_PACKET:
4155 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4156 break;
4157 case OP_BUFFER:
4158 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4159 break;
4160 default:
4161 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4162 a, le16_to_cpu(le->length));
4163 }
4164
4165 if (le->ctrl & EOP) {
4166 seq_putc(seq, '\n');
4167 sop = 1;
4168 }
4169 }
4170
4171 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4172 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4173 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4174 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4175
d1d08d12 4176 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4177 napi_enable(&hw->napi);
3cf26753
SH		 4178 return 0;
4179}
4180
4181static int sky2_debug_open(struct inode *inode, struct file *file)
4182{
4183 return single_open(file, sky2_debug_show, inode->i_private);
4184}
4185
4186static const struct file_operations sky2_debug_fops = {
4187 .owner = THIS_MODULE,
4188 .open = sky2_debug_open,
4189 .read = seq_read,
4190 .llseek = seq_lseek,
4191 .release = single_release,
4192};
4193
4194/*
4195 * Use network device events to create/remove/rename
4196 * debugfs file entries
4197 */
4198static int sky2_device_event(struct notifier_block *unused,
4199 unsigned long event, void *ptr)
4200{
4201 struct net_device *dev = ptr;
5b296bc9 4202 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4203
1436b301 4204 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4205 return NOTIFY_DONE;
3cf26753 4206
5b296bc9
SH		 4207 switch(event) {
4208 case NETDEV_CHANGENAME:
4209 if (sky2->debugfs) {
4210 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4211 sky2_debug, dev->name);
4212 }
4213 break;
3cf26753 4214
5b296bc9
SH		 4215 case NETDEV_GOING_DOWN:
4216 if (sky2->debugfs) {
4217 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4218 dev->name);
4219 debugfs_remove(sky2->debugfs);
4220 sky2->debugfs = NULL;
3cf26753 4221 }
5b296bc9
SH		 4222 break;
4223
4224 case NETDEV_UP:
4225 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4226 sky2_debug, dev,
4227 &sky2_debug_fops);
4228 if (IS_ERR(sky2->debugfs))
4229 sky2->debugfs = NULL;
3cf26753
SH		 4230 }
4231
4232 return NOTIFY_DONE;
4233}
4234
4235static struct notifier_block sky2_notifier = {
4236 .notifier_call = sky2_device_event,
4237};
4238
4239
4240static __init void sky2_debug_init(void)
4241{
4242 struct dentry *ent;
4243
4244 ent = debugfs_create_dir("sky2", NULL);
4245 if (!ent || IS_ERR(ent))
4246 return;
4247
4248 sky2_debug = ent;
4249 register_netdevice_notifier(&sky2_notifier);
4250}
4251
4252static __exit void sky2_debug_cleanup(void)
4253{
4254 if (sky2_debug) {
4255 unregister_netdevice_notifier(&sky2_notifier);
4256 debugfs_remove(sky2_debug);
4257 sky2_debug = NULL;
4258 }
4259}
4260
4261#else
4262#define sky2_debug_init()
4263#define sky2_debug_cleanup()
4264#endif
4265
1436b301
SH		 4266/* Two copies of network device operations to handle special case of
4267 not allowing netpoll on second port */
4268static const struct net_device_ops sky2_netdev_ops[2] = {
4269 {
4270 .ndo_open = sky2_up,
4271 .ndo_stop = sky2_down,
00829823 4272 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4273 .ndo_do_ioctl = sky2_ioctl,
4274 .ndo_validate_addr = eth_validate_addr,
4275 .ndo_set_mac_address = sky2_set_mac_address,
4276 .ndo_set_multicast_list = sky2_set_multicast,
4277 .ndo_change_mtu = sky2_change_mtu,
4278 .ndo_tx_timeout = sky2_tx_timeout,
4279#ifdef SKY2_VLAN_TAG_USED
4280 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4281#endif
4282#ifdef CONFIG_NET_POLL_CONTROLLER
4283 .ndo_poll_controller = sky2_netpoll,
4284#endif
4285 },
4286 {
4287 .ndo_open = sky2_up,
4288 .ndo_stop = sky2_down,
00829823 4289 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4290 .ndo_do_ioctl = sky2_ioctl,
4291 .ndo_validate_addr = eth_validate_addr,
4292 .ndo_set_mac_address = sky2_set_mac_address,
4293 .ndo_set_multicast_list = sky2_set_multicast,
4294 .ndo_change_mtu = sky2_change_mtu,
4295 .ndo_tx_timeout = sky2_tx_timeout,
4296#ifdef SKY2_VLAN_TAG_USED
4297 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4298#endif
4299 },
4300};
3cf26753 4301
cd28ab6a
SH		 4302/* Initialize network device */
4303static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4304 unsigned port,
be63a21c 4305 int highmem, int wol)
cd28ab6a
SH		 4306{
4307 struct sky2_port *sky2;
4308 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4309
4310 if (!dev) {
898eb71c 4311 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4312 return NULL;
4313 }
4314
cd28ab6a 4315 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4316 dev->irq = hw->pdev->irq;
cd28ab6a 4317 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4318 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4319 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4320
4321 sky2 = netdev_priv(dev);
4322 sky2->netdev = dev;
4323 sky2->hw = hw;
4324 sky2->msg_enable = netif_msg_init(debug, default_msg);
4325
cd28ab6a 4326 /* Auto speed and flow control */
0ea065e5
SH		 4327 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4328 if (hw->chip_id != CHIP_ID_YUKON_XL)
4329 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4330
16ad91e1
SH		 4331 sky2->flow_mode = FC_BOTH;
4332
cd28ab6a
SH		 4333 sky2->duplex = -1;
4334 sky2->speed = -1;
4335 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4336 sky2->wol = wol;
75d070c5 4337
e07b1aa8 4338 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4339
793b883e 4340 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4341 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4342 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4343
4344 hw->dev[port] = dev;
4345
4346 sky2->port = port;
4347
4a50a876 4348 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4349 if (highmem)
4350 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4351
d1f13708 4352#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4353 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4354 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4355 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4356 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4357 }
d1f13708
SH		 4358#endif
4359
cd28ab6a 4360 /* read the mac address */
793b883e 4361 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4362 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4363
cd28ab6a
SH		 4364 return dev;
4365}
4366
28bd181a 4367static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4368{
4369 const struct sky2_port *sky2 = netdev_priv(dev);
4370
4371 if (netif_msg_probe(sky2))
e174961c
JB		 4372 printk(KERN_INFO PFX "%s: addr %pM\n",
4373 dev->name, dev->dev_addr);
cd28ab6a
SH		 4374}
4375
fb2690a9 4376/* Handle software interrupt used during MSI test */
7d12e780 4377static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4378{
4379 struct sky2_hw *hw = dev_id;
4380 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4381
4382 if (status == 0)
4383 return IRQ_NONE;
4384
4385 if (status & Y2_IS_IRQ_SW) {
ea76e635 4386 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4387 wake_up(&hw->msi_wait);
4388 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4389 }
4390 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4391
4392 return IRQ_HANDLED;
4393}
4394
4395/* Test interrupt path by forcing a a software IRQ */
4396static int __devinit sky2_test_msi(struct sky2_hw *hw)
4397{
4398 struct pci_dev *pdev = hw->pdev;
4399 int err;
4400
bb507fe1
SH		 4401 init_waitqueue_head (&hw->msi_wait);
4402
fb2690a9
SH		 4403 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4404
b0a20ded 4405 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4406 if (err) {
b02a9258 4407 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4408 return err;
4409 }
4410
fb2690a9 4411 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4412 sky2_read8(hw, B0_CTST);
fb2690a9 4413
ea76e635 4414 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4415
ea76e635 4416 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4417 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4418 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4419 "switching to INTx mode.\n");
fb2690a9
SH		 4420
4421 err = -EOPNOTSUPP;
4422 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4423 }
4424
4425 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4426 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4427
4428 free_irq(pdev->irq, hw);
4429
4430 return err;
4431}
4432
c7127a34
SH		 4433/* This driver supports yukon2 chipset only */
4434static const char *sky2_name(u8 chipid, char *buf, int sz)
4435{
4436 const char *name[] = {
4437 "XL", /* 0xb3 */
4438 "EC Ultra", /* 0xb4 */
4439 "Extreme", /* 0xb5 */
4440 "EC", /* 0xb6 */
4441 "FE", /* 0xb7 */
4442 "FE+", /* 0xb8 */
4443 "Supreme", /* 0xb9 */
0ce8b98d 4444 "UL 2", /* 0xba */
c7127a34
SH		 4445 };
4446
0ce8b98d 4447 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4448 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4449 else
4450 snprintf(buf, sz, "(chip %#x)", chipid);
4451 return buf;
4452}
4453
cd28ab6a
SH		 4454static int __devinit sky2_probe(struct pci_dev *pdev,
4455 const struct pci_device_id *ent)
4456{
7f60c64b 4457 struct net_device *dev;
cd28ab6a 4458 struct sky2_hw *hw;
be63a21c 4459 int err, using_dac = 0, wol_default;
3834507d 4460 u32 reg;
c7127a34 4461 char buf1[16];
cd28ab6a 4462
793b883e
SH		 4463 err = pci_enable_device(pdev);
4464 if (err) {
b02a9258 4465 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4466 goto err_out;
4467 }
4468
6cc90a5a
SH		 4469 /* Get configuration information
4470 * Note: only regular PCI config access once to test for HW issues
4471 * other PCI access through shared memory for speed and to
4472 * avoid MMCONFIG problems.
4473 */
4474 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4475 if (err) {
4476 dev_err(&pdev->dev, "PCI read config failed\n");
4477 goto err_out;
4478 }
4479
4480 if (~reg == 0) {
4481 dev_err(&pdev->dev, "PCI configuration read error\n");
4482 goto err_out;
4483 }
4484
793b883e
SH		 4485 err = pci_request_regions(pdev, DRV_NAME);
4486 if (err) {
b02a9258 4487 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4488 goto err_out_disable;
cd28ab6a
SH		 4489 }
4490
4491 pci_set_master(pdev);
4492
d1f3d4dd 4493 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4494 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4495 using_dac = 1;
6a35528a 4496 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4497 if (err < 0) {
b02a9258
SH		 4498 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4499 "for consistent allocations\n");
d1f3d4dd
SH		 4500 goto err_out_free_regions;
4501 }
d1f3d4dd 4502 } else {
284901a9 4503 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4504 if (err) {
b02a9258 4505 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4506 goto err_out_free_regions;
4507 }
4508 }
d1f3d4dd 4509
3834507d
SH		 4510
4511#ifdef __BIG_ENDIAN
4512 /* The sk98lin vendor driver uses hardware byte swapping but
4513 * this driver uses software swapping.
4514 */
4515 reg &= ~PCI_REV_DESC;
4516 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4517 if (err) {
4518 dev_err(&pdev->dev, "PCI write config failed\n");
4519 goto err_out_free_regions;
4520 }
4521#endif
4522
9d731d77 4523 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4524
cd28ab6a 4525 err = -ENOMEM;
66466797
SH		 4526
4527 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4528 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4529 if (!hw) {
b02a9258 4530 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4531 goto err_out_free_regions;
4532 }
4533
cd28ab6a 4534 hw->pdev = pdev;
66466797 4535 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4536
4537 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4538 if (!hw->regs) {
b02a9258 4539 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4540 goto err_out_free_hw;
4541 }
4542
08c06d8a 4543 /* ring for status responses */
167f53d0 4544 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4545 if (!hw->st_le)
4546 goto err_out_iounmap;
4547
e3173832 4548 err = sky2_init(hw);
cd28ab6a 4549 if (err)
793b883e 4550 goto err_out_iounmap;
cd28ab6a 4551
c844d483
SH		 4552 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4553 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4554
e3173832
SH		 4555 sky2_reset(hw);
4556
be63a21c 4557 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4558 if (!dev) {
4559 err = -ENOMEM;
cd28ab6a 4560 goto err_out_free_pci;
7f60c64b 4561 }
cd28ab6a 4562
9fa1b1f3
SH		 4563 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4564 err = sky2_test_msi(hw);
4565 if (err == -EOPNOTSUPP)
4566 pci_disable_msi(pdev);
4567 else if (err)
4568 goto err_out_free_netdev;
4569 }
4570
793b883e
SH		 4571 err = register_netdev(dev);
4572 if (err) {
b02a9258 4573 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4574 goto err_out_free_netdev;
4575 }
4576
6de16237
SH		 4577 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4578
ea76e635
SH		 4579 err = request_irq(pdev->irq, sky2_intr,
4580 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4581 hw->irq_name, hw);
9fa1b1f3 4582 if (err) {
b02a9258 4583 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4584 goto err_out_unregister;
4585 }
4586 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4587 napi_enable(&hw->napi);
9fa1b1f3 4588
cd28ab6a
SH		 4589 sky2_show_addr(dev);
4590
7f60c64b 4591 if (hw->ports > 1) {
4592 struct net_device *dev1;
4593
ca519274 4594 err = -ENOMEM;
be63a21c 4595 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4596 if (dev1 && (err = register_netdev(dev1)) == 0)
4597 sky2_show_addr(dev1);
4598 else {
b02a9258
SH		 4599 dev_warn(&pdev->dev,
4600 "register of second port failed (%d)\n", err);
cd28ab6a 4601 hw->dev[1] = NULL;
ca519274
SH		 4602 hw->ports = 1;
4603 if (dev1)
4604 free_netdev(dev1);
4605 }
cd28ab6a
SH		 4606 }
4607
32c2c300 4608 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4609 INIT_WORK(&hw->restart_work, sky2_restart);
4610
793b883e
SH		 4611 pci_set_drvdata(pdev, hw);
4612
cd28ab6a
SH		 4613 return 0;
4614
793b883e 4615err_out_unregister:
ea76e635 4616 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4617 pci_disable_msi(pdev);
793b883e 4618 unregister_netdev(dev);
cd28ab6a
SH		 4619err_out_free_netdev:
4620 free_netdev(dev);
cd28ab6a 4621err_out_free_pci:
793b883e 4622 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4623 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4624err_out_iounmap:
4625 iounmap(hw->regs);
4626err_out_free_hw:
4627 kfree(hw);
4628err_out_free_regions:
4629 pci_release_regions(pdev);
44a1d2e5 4630err_out_disable:
cd28ab6a 4631 pci_disable_device(pdev);
cd28ab6a 4632err_out:
549a68c3 4633 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4634 return err;
4635}
4636
4637static void __devexit sky2_remove(struct pci_dev *pdev)
4638{
793b883e 4639 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4640 int i;
cd28ab6a 4641
793b883e 4642 if (!hw)
cd28ab6a
SH		 4643 return;
4644
32c2c300 4645 del_timer_sync(&hw->watchdog_timer);
6de16237 4646 cancel_work_sync(&hw->restart_work);
d27ed387 4647
b877fe28 4648 for (i = hw->ports-1; i >= 0; --i)
6de16237 4649 unregister_netdev(hw->dev[i]);
81906791 4650
d27ed387 4651 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4652
ae306cca
SH		 4653 sky2_power_aux(hw);
4654
793b883e 4655 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4656 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4657
4658 free_irq(pdev->irq, hw);
ea76e635 4659 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4660 pci_disable_msi(pdev);
793b883e 4661 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4662 pci_release_regions(pdev);
4663 pci_disable_device(pdev);
793b883e 4664
b877fe28 4665 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4666 free_netdev(hw->dev[i]);
4667
cd28ab6a
SH		 4668 iounmap(hw->regs);
4669 kfree(hw);
5afa0a9c 4670
cd28ab6a
SH		 4671 pci_set_drvdata(pdev, NULL);
4672}
4673
4674#ifdef CONFIG_PM
4675static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4676{
793b883e 4677 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4678 int i, wol = 0;
cd28ab6a 4679
549a68c3
SH		 4680 if (!hw)
4681 return 0;
4682
063a0b38
SH		 4683 del_timer_sync(&hw->watchdog_timer);
4684 cancel_work_sync(&hw->restart_work);
4685
19720737 4686 rtnl_lock();
f05267e7 4687 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4688 struct net_device *dev = hw->dev[i];
e3173832 4689 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4690
af18d8b8 4691 sky2_detach(dev);
e3173832
SH		 4692
4693 if (sky2->wol)
4694 sky2_wol_init(sky2);
4695
4696 wol |= sky2->wol;
cd28ab6a
SH		 4697 }
4698
8ab8fca2 4699 sky2_write32(hw, B0_IMSK, 0);
6de16237 4700 napi_disable(&hw->napi);
ae306cca 4701 sky2_power_aux(hw);
19720737 4702 rtnl_unlock();
e3173832 4703
d374c1c1 4704 pci_save_state(pdev);
e3173832 4705 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4706 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4707
2ccc99b7 4708 return 0;
cd28ab6a
SH		 4709}
4710
4711static int sky2_resume(struct pci_dev *pdev)
4712{
793b883e 4713 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4714 int i, err;
cd28ab6a 4715
549a68c3
SH		 4716 if (!hw)
4717 return 0;
4718
f71eb1a2
SH		 4719 err = pci_set_power_state(pdev, PCI_D0);
4720 if (err)
4721 goto out;
ae306cca
SH		 4722
4723 err = pci_restore_state(pdev);
4724 if (err)
4725 goto out;
4726
cd28ab6a 4727 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4728
4729 /* Re-enable all clocks */
05745c4a
SH		 4730 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4731 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4732 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4733 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4734
e3173832 4735 sky2_reset(hw);
8ab8fca2 4736 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4737 napi_enable(&hw->napi);
8ab8fca2 4738
af18d8b8 4739 rtnl_lock();
f05267e7 4740 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4741 err = sky2_reattach(hw->dev[i]);
4742 if (err)
4743 goto out;
cd28ab6a 4744 }
af18d8b8 4745 rtnl_unlock();
eb35cf60 4746
ae306cca 4747 return 0;
08c06d8a 4748out:
af18d8b8
SH		 4749 rtnl_unlock();
4750
b02a9258 4751 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4752 pci_disable_device(pdev);
08c06d8a 4753 return err;
cd28ab6a
SH		 4754}
4755#endif
4756
e3173832
SH		 4757static void sky2_shutdown(struct pci_dev *pdev)
4758{
4759 struct sky2_hw *hw = pci_get_drvdata(pdev);
4760 int i, wol = 0;
4761
549a68c3
SH		 4762 if (!hw)
4763 return;
4764
19720737 4765 rtnl_lock();
5c0d6b34 4766 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4767
4768 for (i = 0; i < hw->ports; i++) {
4769 struct net_device *dev = hw->dev[i];
4770 struct sky2_port *sky2 = netdev_priv(dev);
4771
4772 if (sky2->wol) {
4773 wol = 1;
4774 sky2_wol_init(sky2);
4775 }
4776 }
4777
4778 if (wol)
4779 sky2_power_aux(hw);
19720737 4780 rtnl_unlock();
e3173832
SH		 4781
4782 pci_enable_wake(pdev, PCI_D3hot, wol);
4783 pci_enable_wake(pdev, PCI_D3cold, wol);
4784
4785 pci_disable_device(pdev);
f71eb1a2 4786 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4787}
4788
cd28ab6a 4789static struct pci_driver sky2_driver = {
793b883e
SH		 4790 .name = DRV_NAME,
4791 .id_table = sky2_id_table,
4792 .probe = sky2_probe,
4793 .remove = __devexit_p(sky2_remove),
cd28ab6a 4794#ifdef CONFIG_PM
793b883e
SH		 4795 .suspend = sky2_suspend,
4796 .resume = sky2_resume,
cd28ab6a 4797#endif
e3173832 4798 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4799};
4800
4801static int __init sky2_init_module(void)
4802{
c844d483
SH		 4803 pr_info(PFX "driver version " DRV_VERSION "\n");
4804
3cf26753 4805 sky2_debug_init();
50241c4c 4806 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4807}
4808
4809static void __exit sky2_cleanup_module(void)
4810{
4811 pci_unregister_driver(&sky2_driver);
3cf26753 4812 sky2_debug_cleanup();
cd28ab6a
SH		 4813}
4814
4815module_init(sky2_init_module);
4816module_exit(sky2_cleanup_module);
4817
4818MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4819MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4820MODULE_LICENSE("GPL");
5f4f9dc1 4821MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)