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net: add skb frag size accessors
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / marvell / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
a6b7a407 35#include <linux/interrupt.h>
cd28ab6a 36#include <linux/ip.h>
5a0e3ad6 37#include <linux/slab.h>
c9bdd4b5 38#include <net/ip.h>
cd28ab6a
SH		 39#include <linux/tcp.h>
40#include <linux/in.h>
41#include <linux/delay.h>
91c86df5 42#include <linux/workqueue.h>
d1f13708 43#include <linux/if_vlan.h>
d70cd51a 44#include <linux/prefetch.h>
3cf26753 45#include <linux/debugfs.h>
ef743d33 46#include <linux/mii.h>
cd28ab6a
SH		 47
48#include <asm/irq.h>
49
50#include "sky2.h"
51
52#define DRV_NAME "sky2"
4ec8f0ca 53#define DRV_VERSION "1.29"
cd28ab6a
SH		 54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 65
ee5f68fe 66/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 69#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
efe91932 70#define TX_MAX_PENDING 1024
ee5f68fe 71#define TX_DEF_PENDING 127
cd28ab6a 72
cd28ab6a
SH		 73#define TX_WATCHDOG (5 * HZ)
74#define NAPI_WEIGHT 64
75#define PHY_RETRIES 1000
76
f4331a6d
SH		 77#define SKY2_EEPROM_MAGIC 0x9955aabb
78
060b946c 79#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
cb5d9547 80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e6cac9ba 98static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0 150static void sky2_set_multicast(struct net_device *dev);
0bdb0bd0 151static irqreturn_t sky2_intr(int irq, void *dev_id);
d1b139c0 152
af043aa5 153/* Access to PHY via serial interconnect */
ef743d33 154static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 155{
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
164 if (ctrl == 0xffff)
165 goto io_error;
166
167 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 168 return 0;
af043aa5
SH		 169
170 udelay(10);
cd28ab6a 171 }
ef743d33 172
060b946c 173 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 174 return -ETIMEDOUT;
af043aa5
SH		 175
176io_error:
177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
178 return -EIO;
cd28ab6a
SH		 179}
180
ef743d33 181static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 182{
183 int i;
184
793b883e 185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187
188 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
190 if (ctrl == 0xffff)
191 goto io_error;
192
193 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 194 *val = gma_read16(hw, port, GM_SMI_DATA);
195 return 0;
196 }
197
af043aa5 198 udelay(10);
cd28ab6a
SH		 199 }
200
af043aa5 201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 202 return -ETIMEDOUT;
af043aa5
SH		 203io_error:
204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
205 return -EIO;
ef743d33
SH		 206}
207
af043aa5 208static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 209{
210 u16 v;
af043aa5 211 __gm_phy_read(hw, port, reg, &v);
ef743d33 212 return v;
cd28ab6a
SH		 213}
214
5afa0a9c 215
ae306cca
SH		 216static void sky2_power_on(struct sky2_hw *hw)
217{
218 /* switch power to VCC (WA for VAUX problem) */
219 sky2_write8(hw, B0_POWER_CTRL,
220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 221
ae306cca
SH		 222 /* disable Core Clock Division, */
223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 224
4b7c47aa 225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 226 /* enable bits are inverted */
227 sky2_write8(hw, B2_Y2_CLK_GATE,
228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 else
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 233
ea76e635 234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 235 u32 reg;
5afa0a9c 236
b32f40c4 237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 238
b32f40c4 239 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 240 /* set all bits to 0 except bits 15..12 and 8 */
241 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 242 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 243
b32f40c4 244 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 245 /* set all bits to 0 except bits 28 & 27 */
246 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 247 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 248
b32f40c4 249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 250
5f8ae5c5 251 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
252
8f70920f
SH		 253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
254 reg = sky2_read32(hw, B2_GP_IO);
255 reg |= GLB_GPIO_STAT_RACE_DIS;
256 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 257
258 sky2_read32(hw, B2_GP_IO);
5afa0a9c 259 }
10547ae2
SH		 260
261 /* Turn on "driver loaded" LED */
262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 263}
5afa0a9c 264
ae306cca
SH		 265static void sky2_power_aux(struct sky2_hw *hw)
266{
4b7c47aa 267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 268 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 else
270 /* enable bits are inverted */
271 sky2_write8(hw, B2_Y2_CLK_GATE,
272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275
c23ddf8f
SH		 276 /* switch power to VAUX if supported and PME from D3cold */
277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
278 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 282
283 /* turn off "driver loaded LED" */
284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 285}
286
d3bcfbeb 287static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 288{
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 293
cd28ab6a
SH		 294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302}
303
16ad91e1
SH		 304/* flow control to advertise bits */
305static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310};
311
312/* flow control to advertise bits when using 1000BaseX */
313static const u16 fiber_fc_adv[] = {
df3fe1f3 314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 318};
319
320/* flow control to GMA disable bits */
321static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326};
327
328
cd28ab6a
SH		 329static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330{
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 333
0ea065e5 334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 339 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
53419c68 342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 343 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 344 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
53419c68
SH		 347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 354 if (sky2_is_copper(hw)) {
05745c4a 355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
cd28ab6a 368 } else {
4fb99cd6 369 if (hw->chip_id >= CHIP_ID_YUKON_OPT) {
370 u16 ctrl2 = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL_2);
371
372 /* enable PHY Reverse Auto-Negotiation */
373 ctrl2 |= 1u << 13;
374
375 /* Write PHY changes (SW-reset must follow) */
376 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL_2, ctrl2);
377 }
378
379
cd28ab6a
SH		 380 /* disable energy detect */
381 ctrl &= ~PHY_M_PC_EN_DET_MSK;
382
383 /* enable automatic crossover */
384 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
385
53419c68 386 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 387 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
388 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 389 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 390 ctrl &= ~PHY_M_PC_DSC_MSK;
391 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
392 }
393 }
cd28ab6a
SH		 394 } else {
395 /* workaround for deviation #4.88 (CRC errors) */
396 /* disable Automatic Crossover */
397
398 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 399 }
cd28ab6a 400
b89165f2
SH		 401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 /* special setup for PHY 88E1112 Fiber */
ea76e635 404 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 405 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 406
b89165f2
SH		 407 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
408 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl &= ~PHY_M_MAC_MD_MSK;
411 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
412 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
413
414 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 415 /* select page 1 to access Fiber registers */
416 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 417
418 /* for SFP-module set SIGDET polarity to low */
419 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
420 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 421 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 422 }
b89165f2
SH		 423
424 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 425 }
426
7800fddc 427 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 428 ct1000 = 0;
429 adv = PHY_AN_CSMA;
2eaba1a2 430 reg = 0;
cd28ab6a 431
0ea065e5 432 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 433 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 434 if (sky2->advertising & ADVERTISED_1000baseT_Full)
435 ct1000 |= PHY_M_1000C_AFD;
436 if (sky2->advertising & ADVERTISED_1000baseT_Half)
437 ct1000 |= PHY_M_1000C_AHD;
438 if (sky2->advertising & ADVERTISED_100baseT_Full)
439 adv |= PHY_M_AN_100_FD;
440 if (sky2->advertising & ADVERTISED_100baseT_Half)
441 adv |= PHY_M_AN_100_HD;
442 if (sky2->advertising & ADVERTISED_10baseT_Full)
443 adv |= PHY_M_AN_10_FD;
444 if (sky2->advertising & ADVERTISED_10baseT_Half)
445 adv |= PHY_M_AN_10_HD;
709c6e7b 446
b89165f2
SH		 447 } else { /* special defines for FIBER (88E1040S only) */
448 if (sky2->advertising & ADVERTISED_1000baseT_Full)
449 adv |= PHY_M_AN_1000X_AFD;
450 if (sky2->advertising & ADVERTISED_1000baseT_Half)
451 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 452 }
cd28ab6a
SH		 453
454 /* Restart Auto-negotiation */
455 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
456 } else {
457 /* forced speed/duplex settings */
458 ct1000 = PHY_M_1000C_MSE;
459
0ea065e5
SH		 460 /* Disable auto update for duplex flow control and duplex */
461 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 462
463 switch (sky2->speed) {
464 case SPEED_1000:
465 ctrl |= PHY_CT_SP1000;
2eaba1a2 466 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 467 break;
468 case SPEED_100:
469 ctrl |= PHY_CT_SP100;
2eaba1a2 470 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 471 break;
472 }
473
2eaba1a2
SH		 474 if (sky2->duplex == DUPLEX_FULL) {
475 reg |= GM_GPCR_DUP_FULL;
476 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 477 } else if (sky2->speed < SPEED_1000)
478 sky2->flow_mode = FC_NONE;
0ea065e5 479 }
2eaba1a2 480
0ea065e5
SH		 481 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
482 if (sky2_is_copper(hw))
483 adv |= copper_fc_adv[sky2->flow_mode];
484 else
485 adv |= fiber_fc_adv[sky2->flow_mode];
486 } else {
487 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 488 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 489
490 /* Forward pause packets to GMAC? */
16ad91e1 491 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 492 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
493 else
494 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 495 }
496
2eaba1a2
SH		 497 gma_write16(hw, port, GM_GP_CTRL, reg);
498
05745c4a 499 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 500 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
501
502 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
503 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
504
505 /* Setup Phy LED's */
506 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
507 ledover = 0;
508
509 switch (hw->chip_id) {
510 case CHIP_ID_YUKON_FE:
511 /* on 88E3082 these bits are at 11..9 (shifted left) */
512 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
513
514 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
515
516 /* delete ACT LED control bits */
517 ctrl &= ~PHY_M_FELP_LED1_MSK;
518 /* change ACT LED control to blink mode */
519 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
520 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
521 break;
522
05745c4a
SH		 523 case CHIP_ID_YUKON_FE_P:
524 /* Enable Link Partner Next Page */
525 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
526 ctrl |= PHY_M_PC_ENA_LIP_NP;
527
528 /* disable Energy Detect and enable scrambler */
529 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
530 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
531
532 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
533 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
534 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
535 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
536
537 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
538 break;
539
cd28ab6a 540 case CHIP_ID_YUKON_XL:
793b883e 541 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 542
543 /* select page 3 to access LED control register */
544 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
545
546 /* set LED Function Control register */
ed6d32c7
SH		 547 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
548 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
549 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
550 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
551 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 552
553 /* set Polarity Control register */
554 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 555 (PHY_M_POLC_LS1_P_MIX(4) |
556 PHY_M_POLC_IS0_P_MIX(4) |
557 PHY_M_POLC_LOS_CTRL(2) |
558 PHY_M_POLC_INIT_CTRL(2) |
559 PHY_M_POLC_STA1_CTRL(2) |
560 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 561
562 /* restore page register */
793b883e 563 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 564 break;
93745494 565
ed6d32c7 566 case CHIP_ID_YUKON_EC_U:
93745494 567 case CHIP_ID_YUKON_EX:
ed4d4161 568 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 569 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
570
571 /* select page 3 to access LED control register */
572 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
573
574 /* set LED Function Control register */
575 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
576 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
577 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
578 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
579 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
580
581 /* set Blink Rate in LED Timer Control Register */
582 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
583 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
584 /* restore page register */
585 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
586 break;
cd28ab6a
SH		 587
588 default:
589 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
590 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 591
cd28ab6a 592 /* turn off the Rx LED (LED_RX) */
a84d0a3d 593 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 594 }
595
0ce8b98d 596 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 597 /* apply fixes in PHY AFE */
ed6d32c7
SH		 598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
599
977bdf06 600 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 601 gm_phy_write(hw, port, 0x18, 0xaa99);
602 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 603
0ce8b98d
SH		 604 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
605 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
606 gm_phy_write(hw, port, 0x18, 0xa204);
607 gm_phy_write(hw, port, 0x17, 0x2002);
608 }
977bdf06
SH		 609
610 /* set page register to 0 */
9467a8fc 611 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 612 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
613 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
614 /* apply workaround for integrated resistors calibration */
615 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
616 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 617 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
618 /* apply fixes in PHY AFE */
619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
620
621 /* apply RDAC termination workaround */
622 gm_phy_write(hw, port, 24, 0x2800);
623 gm_phy_write(hw, port, 23, 0x2001);
624
625 /* set page register back to 0 */
626 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 627 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
628 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 629 /* no effect on Yukon-XL */
977bdf06 630 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 631
8e95a202
JP		 632 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
633 sky2->speed == SPEED_100) {
977bdf06 634 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 635 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 636 }
cd28ab6a 637
977bdf06
SH		 638 if (ledover)
639 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
640
4fb99cd6 641 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
642 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
643 int i;
644 /* This a phy register setup workaround copied from vendor driver. */
645 static const struct {
646 u16 reg, val;
647 } eee_afe[] = {
648 { 0x156, 0x58ce },
649 { 0x153, 0x99eb },
650 { 0x141, 0x8064 },
651 /* { 0x155, 0x130b },*/
652 { 0x000, 0x0000 },
653 { 0x151, 0x8433 },
654 { 0x14b, 0x8c44 },
655 { 0x14c, 0x0f90 },
656 { 0x14f, 0x39aa },
657 /* { 0x154, 0x2f39 },*/
658 { 0x14d, 0xba33 },
659 { 0x144, 0x0048 },
660 { 0x152, 0x2010 },
661 /* { 0x158, 0x1223 },*/
662 { 0x140, 0x4444 },
663 { 0x154, 0x2f3b },
664 { 0x158, 0xb203 },
665 { 0x157, 0x2029 },
666 };
667
668 /* Start Workaround for OptimaEEE Rev.Z0 */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
670
671 gm_phy_write(hw, port, 1, 0x4099);
672 gm_phy_write(hw, port, 3, 0x1120);
673 gm_phy_write(hw, port, 11, 0x113c);
674 gm_phy_write(hw, port, 14, 0x8100);
675 gm_phy_write(hw, port, 15, 0x112a);
676 gm_phy_write(hw, port, 17, 0x1008);
677
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
679 gm_phy_write(hw, port, 1, 0x20b0);
680
681 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
682
683 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
684 /* apply AFE settings */
685 gm_phy_write(hw, port, 17, eee_afe[i].val);
686 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
687 }
688
689 /* End Workaround for OptimaEEE */
690 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
691
692 /* Enable 10Base-Te (EEE) */
693 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
694 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
695 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
696 reg | PHY_M_10B_TE_ENABLE);
697 }
977bdf06 698 }
2eaba1a2 699
d571b694 700 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 701 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 702 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
703 else
704 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
705}
706
b96936da
SH		 707static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
708static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
709
710static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 711{
712 u32 reg1;
d3bcfbeb 713
a40ccc68 714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 715 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 716 reg1 &= ~phy_power[port];
d3bcfbeb 717
4b7c47aa 718 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 719 reg1 |= coma_mode[port];
720
b32f40c4 721 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 722 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 723 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 724
725 if (hw->chip_id == CHIP_ID_YUKON_FE)
726 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
727 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
728 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 729}
167f53d0 730
b96936da
SH		 731static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
732{
733 u32 reg1;
db99b988
SH		 734 u16 ctrl;
735
736 /* release GPHY Control reset */
737 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
738
739 /* release GMAC reset */
740 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
741
742 if (hw->flags & SKY2_HW_NEWER_PHY) {
743 /* select page 2 to access MAC control register */
744 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
745
746 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
747 /* allow GMII Power Down */
748 ctrl &= ~PHY_M_MAC_GMIF_PUP;
749 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
750
751 /* set page register back to 0 */
752 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
753 }
754
755 /* setup General Purpose Control Register */
756 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 757 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
758 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
759 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 760
761 if (hw->chip_id != CHIP_ID_YUKON_EC) {
762 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 763 /* select page 2 to access MAC control register */
764 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 765
e484d5f5 766 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 767 /* enable Power Down */
768 ctrl |= PHY_M_PC_POW_D_ENA;
769 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 770
771 /* set page register back to 0 */
772 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 773 }
774
775 /* set IEEE compatible Power Down Mode (dev. #4.99) */
776 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
777 }
b96936da 778
a40ccc68 779 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 780 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 781 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 782 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 783 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 784}
785
8e11680f 786/* configure IPG according to used link speed */
787static void sky2_set_ipg(struct sky2_port *sky2)
788{
789 u16 reg;
790
791 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
792 reg &= ~GM_SMOD_IPG_MSK;
793 if (sky2->speed > SPEED_100)
794 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
795 else
796 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
797 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
798}
799
38000a94
BP		 800/* Enable Rx/Tx */
801static void sky2_enable_rx_tx(struct sky2_port *sky2)
802{
803 struct sky2_hw *hw = sky2->hw;
804 unsigned port = sky2->port;
805 u16 reg;
806
807 reg = gma_read16(hw, port, GM_GP_CTRL);
808 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
809 gma_write16(hw, port, GM_GP_CTRL, reg);
810}
811
1b537565
SH		 812/* Force a renegotiation */
813static void sky2_phy_reinit(struct sky2_port *sky2)
814{
e07b1aa8 815 spin_lock_bh(&sky2->phy_lock);
1b537565 816 sky2_phy_init(sky2->hw, sky2->port);
38000a94 817 sky2_enable_rx_tx(sky2);
e07b1aa8 818 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 819}
820
e3173832
SH		 821/* Put device in state to listen for Wake On Lan */
822static void sky2_wol_init(struct sky2_port *sky2)
823{
824 struct sky2_hw *hw = sky2->hw;
825 unsigned port = sky2->port;
826 enum flow_control save_mode;
827 u16 ctrl;
e3173832
SH		 828
829 /* Bring hardware out of reset */
830 sky2_write16(hw, B0_CTST, CS_RST_CLR);
831 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
832
833 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
834 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
835
836 /* Force to 10/100
837 * sky2_reset will re-enable on resume
838 */
839 save_mode = sky2->flow_mode;
840 ctrl = sky2->advertising;
841
842 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
843 sky2->flow_mode = FC_NONE;
b96936da
SH		 844
845 spin_lock_bh(&sky2->phy_lock);
846 sky2_phy_power_up(hw, port);
847 sky2_phy_init(hw, port);
848 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 849
850 sky2->flow_mode = save_mode;
851 sky2->advertising = ctrl;
852
853 /* Set GMAC to no flow control and auto update for speed/duplex */
854 gma_write16(hw, port, GM_GP_CTRL,
855 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
856 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
857
858 /* Set WOL address */
859 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
860 sky2->netdev->dev_addr, ETH_ALEN);
861
862 /* Turn on appropriate WOL control bits */
863 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
864 ctrl = 0;
865 if (sky2->wol & WAKE_PHY)
866 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
867 else
868 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
869
870 if (sky2->wol & WAKE_MAGIC)
871 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
872 else
a419aef8 873 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 874
875 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
876 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
877
5f8ae5c5 878 /* Disable PiG firmware */
879 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
880
e3173832
SH		 881 /* block receiver */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 883}
884
69161611
SH		 885static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
886{
05745c4a
SH		 887 struct net_device *dev = hw->dev[port];
888
ed4d4161
SH		 889 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
890 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 891 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 892 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 893 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
894 } else if (dev->mtu > ETH_DATA_LEN) {
895 /* set Tx GMAC FIFO Almost Empty Threshold */
896 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
897 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 898
44dde56d 899 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
900 } else
901 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 902}
903
cd28ab6a
SH		 904static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
905{
906 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
907 u16 reg;
25cccecc 908 u32 rx_reg;
cd28ab6a
SH		 909 int i;
910 const u8 *addr = hw->dev[port]->dev_addr;
911
f350339c
SH		 912 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
913 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 914
915 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
916
4b7c47aa 917 if (hw->chip_id == CHIP_ID_YUKON_XL &&
918 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
919 port == 1) {
cd28ab6a
SH		 920 /* WA DEV_472 -- looks like crossed wires on port 2 */
921 /* clear GMAC 1 Control reset */
922 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
923 do {
924 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
925 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
926 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
927 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
928 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
929 }
930
793b883e 931 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 932
2eaba1a2
SH		 933 /* Enable Transmit FIFO Underrun */
934 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
935
e07b1aa8 936 spin_lock_bh(&sky2->phy_lock);
b96936da 937 sky2_phy_power_up(hw, port);
cd28ab6a 938 sky2_phy_init(hw, port);
e07b1aa8 939 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 940
941 /* MIB clear */
942 reg = gma_read16(hw, port, GM_PHY_ADDR);
943 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
944
43f2f104
SH		 945 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
946 gma_read16(hw, port, i);
cd28ab6a
SH		 947 gma_write16(hw, port, GM_PHY_ADDR, reg);
948
949 /* transmit control */
950 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
951
952 /* receive control reg: unicast + multicast + no FCS */
953 gma_write16(hw, port, GM_RX_CTRL,
793b883e 954 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 955
956 /* transmit flow control */
957 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
958
959 /* transmit parameter */
960 gma_write16(hw, port, GM_TX_PARAM,
961 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
962 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
963 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
964 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
965
966 /* serial mode register */
967 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
8e11680f 968 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
cd28ab6a 969
6b1a3aef 970 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 971 reg |= GM_SMOD_JUMBO_ENA;
972
c1cd0a85 973 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
974 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
975 reg |= GM_NEW_FLOW_CTRL;
976
cd28ab6a
SH		 977 gma_write16(hw, port, GM_SERIAL_MODE, reg);
978
cd28ab6a
SH		 979 /* virtual address for data */
980 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
981
793b883e
SH		 982 /* physical address: used for pause frames */
983 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
984
985 /* ignore counter overflows */
cd28ab6a
SH		 986 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
987 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
988 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
989
990 /* Configure Rx MAC FIFO */
991 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 992 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 993 if (hw->chip_id == CHIP_ID_YUKON_EX ||
994 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 995 rx_reg |= GMF_RX_OVER_ON;
69161611 996
25cccecc 997 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 998
798fdd07
SH		 999 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1000 /* Hardware errata - clear flush mask */
1001 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1002 } else {
1003 /* Flush Rx MAC FIFO on any flow control or error */
1004 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1005 }
cd28ab6a 1006
8df9a876 1007 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 1008 reg = RX_GMF_FL_THR_DEF + 1;
1009 /* Another magic mystery workaround from sk98lin */
1010 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1011 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1012 reg = 0x178;
1013 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 1014
1015 /* Configure Tx MAC FIFO */
1016 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1017 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 1018
25985edc 1019 /* On chips without ram buffer, pause is controlled by MAC level */
39dbd958 1020 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 1021 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 1022 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1023 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 1024 reg = 1568 / 8;
1025 else
1026 reg = 1024 / 8;
1027 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1028 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 1029
69161611 1030 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 1031 }
1032
e970d1f8
SH		 1033 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1034 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1035 /* disable dynamic watermark */
1036 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1037 reg &= ~TX_DYN_WM_ENA;
1038 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1039 }
cd28ab6a
SH		 1040}
1041
67712901
SH		 1042/* Assign Ram Buffer allocation to queue */
1043static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 1044{
67712901
SH		 1045 u32 end;
1046
1047 /* convert from K bytes to qwords used for hw register */
1048 start *= 1024/8;
1049 space *= 1024/8;
1050 end = start + space - 1;
793b883e 1051
cd28ab6a
SH		 1052 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1053 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1054 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1055 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1056 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1057
1058 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 1059 u32 tp = space - space/4;
793b883e 1060
1c28f6ba
SH		 1061 /* On receive queue's set the thresholds
1062 * give receiver priority when > 3/4 full
1063 * send pause when down to 2K
1064 */
1065 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1066 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 1067
1c28f6ba
SH		 1068 tp = space - 2048/8;
1069 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1070 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 1071 } else {
1072 /* Enable store & forward on Tx queue's because
1073 * Tx FIFO is only 1K on Yukon
1074 */
1075 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1076 }
1077
1078 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 1079 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 1080}
1081
cd28ab6a 1082/* Setup Bus Memory Interface */
af4ed7e6 1083static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1084{
1085 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1086 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1087 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1088 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1089}
1090
cd28ab6a
SH		 1091/* Setup prefetch unit registers. This is the interface between
1092 * hardware and driver list elements
1093 */
8cc048e3 1094static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1095 dma_addr_t addr, u32 last)
cd28ab6a 1096{
cd28ab6a
SH		 1097 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1098 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1099 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1100 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1101 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1103
1104 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1105}
1106
9b289c33 1107static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1108{
9b289c33 1109 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1110
ee5f68fe 1111 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1112 le->ctrl = 0;
793b883e
SH		 1113 return le;
1114}
cd28ab6a 1115
88f5f0ca
SH		 1116static void tx_init(struct sky2_port *sky2)
1117{
1118 struct sky2_tx_le *le;
1119
1120 sky2->tx_prod = sky2->tx_cons = 0;
1121 sky2->tx_tcpsum = 0;
1122 sky2->tx_last_mss = 0;
1123
9b289c33 1124 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1125 le->addr = 0;
1126 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1127 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1128}
1129
290d4de5
SH		 1130/* Update chip's next pointer */
1131static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1132{
50432cb5 1133 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1134 wmb();
50432cb5
SH		 1135 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1136
1137 /* Synchronize I/O on since next processor may write to tail */
1138 mmiowb();
cd28ab6a
SH		 1139}
1140
793b883e 1141
cd28ab6a
SH		 1142static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1143{
1144 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1145 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1146 le->ctrl = 0;
cd28ab6a
SH		 1147 return le;
1148}
1149
060b946c 1150static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
39ef110b
MM		 1151{
1152 unsigned size;
1153
1154 /* Space needed for frame data + headers rounded up */
1155 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1156
1157 /* Stopping point for hardware truncation */
1158 return (size - 8) / sizeof(u32);
1159}
1160
060b946c 1161static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
39ef110b
MM		 1162{
1163 struct rx_ring_info *re;
1164 unsigned size;
1165
1166 /* Space needed for frame data + headers rounded up */
1167 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1168
1169 sky2->rx_nfrags = size >> PAGE_SHIFT;
1170 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1171
1172 /* Compute residue after pages */
1173 size -= sky2->rx_nfrags << PAGE_SHIFT;
1174
1175 /* Optimize to handle small packets and headers */
1176 if (size < copybreak)
1177 size = copybreak;
1178 if (size < ETH_HLEN)
1179 size = ETH_HLEN;
1180
1181 return size;
1182}
1183
14d0263f 1184/* Build description to hardware for one receive segment */
060b946c 1185static void sky2_rx_add(struct sky2_port *sky2, u8 op,
14d0263f 1186 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1187{
1188 struct sky2_rx_le *le;
1189
86c6887e 1190 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1191 le = sky2_next_rx(sky2);
86c6887e 1192 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1193 le->opcode = OP_ADDR64 | HW_OWNER;
1194 }
793b883e 1195
cd28ab6a 1196 le = sky2_next_rx(sky2);
d6e74b6b 1197 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1198 le->length = cpu_to_le16(len);
14d0263f 1199 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1200}
1201
14d0263f
SH		 1202/* Build description to hardware for one possibly fragmented skb */
1203static void sky2_rx_submit(struct sky2_port *sky2,
1204 const struct rx_ring_info *re)
1205{
1206 int i;
1207
1208 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1209
1210 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1211 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1212}
1213
1214
454e6cb6 1215static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1216 unsigned size)
1217{
1218 struct sk_buff *skb = re->skb;
1219 int i;
1220
1221 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1222 if (pci_dma_mapping_error(pdev, re->data_addr))
1223 goto mapping_error;
454e6cb6 1224
7cd26ce5 1225 dma_unmap_len_set(re, data_size, size);
14d0263f 1226
3fbd9187 1227 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 1228 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3fbd9187 1229
950a5a4f 1230 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
9e903e08 1231 skb_frag_size(frag),
5d6bcdfe 1232 DMA_FROM_DEVICE);
3fbd9187 1233
5d6bcdfe 1234 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
3fbd9187 1235 goto map_page_error;
1236 }
454e6cb6 1237 return 0;
3fbd9187 1238
1239map_page_error:
1240 while (--i >= 0) {
1241 pci_unmap_page(pdev, re->frag_addr[i],
9e903e08 1242 skb_frag_size(&skb_shinfo(skb)->frags[i]),
3fbd9187 1243 PCI_DMA_FROMDEVICE);
1244 }
1245
7cd26ce5 1246 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
3fbd9187 1247 PCI_DMA_FROMDEVICE);
1248
1249mapping_error:
1250 if (net_ratelimit())
1251 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1252 skb->dev->name);
1253 return -EIO;
14d0263f
SH		 1254}
1255
1256static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1257{
1258 struct sk_buff *skb = re->skb;
1259 int i;
1260
7cd26ce5 1261 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
14d0263f
SH		 1262 PCI_DMA_FROMDEVICE);
1263
1264 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1265 pci_unmap_page(pdev, re->frag_addr[i],
9e903e08 1266 skb_frag_size(&skb_shinfo(skb)->frags[i]),
14d0263f
SH		 1267 PCI_DMA_FROMDEVICE);
1268}
793b883e 1269
cd28ab6a
SH		 1270/* Tell chip where to start receive checksum.
1271 * Actually has two checksums, but set both same to avoid possible byte
1272 * order problems.
1273 */
793b883e 1274static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1275{
ea76e635 1276 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1277
ea76e635
SH		 1278 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1279 le->ctrl = 0;
1280 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1281
ea76e635
SH		 1282 sky2_write32(sky2->hw,
1283 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
f5d64037 1284 (sky2->netdev->features & NETIF_F_RXCSUM)
0ea065e5 1285 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1286}
1287
bf73130d 1288/* Enable/disable receive hash calculation (RSS) */
f5d64037 1289static void rx_set_rss(struct net_device *dev, u32 features)
bf73130d
SH		 1290{
1291 struct sky2_port *sky2 = netdev_priv(dev);
1292 struct sky2_hw *hw = sky2->hw;
1293 int i, nkeys = 4;
1294
1295 /* Supports IPv6 and other modes */
1296 if (hw->flags & SKY2_HW_NEW_LE) {
1297 nkeys = 10;
1298 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1299 }
1300
1301 /* Program RSS initial values */
f5d64037 1302 if (features & NETIF_F_RXHASH) {
bf73130d
SH		 1303 u32 key[nkeys];
1304
1305 get_random_bytes(key, nkeys * sizeof(u32));
1306 for (i = 0; i < nkeys; i++)
1307 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1308 key[i]);
1309
1310 /* Need to turn on (undocumented) flag to make hashing work */
1311 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1312 RX_STFW_ENA);
1313
1314 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1315 BMU_ENA_RX_RSS_HASH);
1316 } else
1317 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1318 BMU_DIS_RX_RSS_HASH);
1319}
1320
6b1a3aef
SH		 1321/*
1322 * The RX Stop command will not work for Yukon-2 if the BMU does not
1323 * reach the end of packet and since we can't make sure that we have
1324 * incoming data, we must reset the BMU while it is not doing a DMA
1325 * transfer. Since it is possible that the RX path is still active,
1326 * the RX RAM buffer will be stopped first, so any possible incoming
1327 * data will not trigger a DMA. After the RAM buffer is stopped, the
1328 * BMU is polled until any DMA in progress is ended and only then it
1329 * will be reset.
1330 */
1331static void sky2_rx_stop(struct sky2_port *sky2)
1332{
1333 struct sky2_hw *hw = sky2->hw;
1334 unsigned rxq = rxqaddr[sky2->port];
1335 int i;
1336
1337 /* disable the RAM Buffer receive queue */
1338 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1339
1340 for (i = 0; i < 0xffff; i++)
1341 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1342 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1343 goto stopped;
1344
ada1db5c 1345 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef
SH		 1346stopped:
1347 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1348
1349 /* reset the Rx prefetch unit */
1350 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1351 mmiowb();
6b1a3aef 1352}
793b883e 1353
d571b694 1354/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1355static void sky2_rx_clean(struct sky2_port *sky2)
1356{
1357 unsigned i;
1358
1359 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1360 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1361 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1362
1363 if (re->skb) {
14d0263f 1364 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1365 kfree_skb(re->skb);
1366 re->skb = NULL;
1367 }
1368 }
1369}
1370
ef743d33
SH		 1371/* Basic MII support */
1372static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1373{
1374 struct mii_ioctl_data *data = if_mii(ifr);
1375 struct sky2_port *sky2 = netdev_priv(dev);
1376 struct sky2_hw *hw = sky2->hw;
1377 int err = -EOPNOTSUPP;
1378
1379 if (!netif_running(dev))
1380 return -ENODEV; /* Phy still in reset */
1381
d89e1343 1382 switch (cmd) {
ef743d33
SH		 1383 case SIOCGMIIPHY:
1384 data->phy_id = PHY_ADDR_MARV;
1385
1386 /* fallthru */
1387 case SIOCGMIIREG: {
1388 u16 val = 0;
91c86df5 1389
e07b1aa8 1390 spin_lock_bh(&sky2->phy_lock);
ef743d33 1391 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1392 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1393
ef743d33
SH		 1394 data->val_out = val;
1395 break;
1396 }
1397
1398 case SIOCSMIIREG:
e07b1aa8 1399 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1400 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1401 data->val_in);
e07b1aa8 1402 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1403 break;
1404 }
1405 return err;
1406}
1407
f5d64037 1408#define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
d494eacd 1409
f5d64037 1410static void sky2_vlan_mode(struct net_device *dev, u32 features)
d494eacd
SH		 1411{
1412 struct sky2_port *sky2 = netdev_priv(dev);
1413 struct sky2_hw *hw = sky2->hw;
1414 u16 port = sky2->port;
1415
f5d64037 1416 if (features & NETIF_F_HW_VLAN_RX)
86aa7785
SH		 1417 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1418 RX_VLAN_STRIP_ON);
1419 else
1420 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1421 RX_VLAN_STRIP_OFF);
d494eacd 1422
f5d64037 1423 if (features & NETIF_F_HW_VLAN_TX) {
86aa7785
SH		 1424 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1425 TX_VLAN_TAG_ON);
f5d64037
MM		 1426
1427 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1428 } else {
86aa7785
SH		 1429 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1430 TX_VLAN_TAG_OFF);
d1f13708 1431
86aa7785 1432 /* Can't do transmit offload of vlan without hw vlan */
f5d64037 1433 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
86aa7785 1434 }
d1f13708 1435}
d1f13708 1436
bd1c6869
SH		 1437/* Amount of required worst case padding in rx buffer */
1438static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1439{
1440 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1441}
1442
82788c7a 1443/*
14d0263f
SH		 1444 * Allocate an skb for receiving. If the MTU is large enough
1445 * make the skb non-linear with a fragment list of pages.
82788c7a 1446 */
68ac3191 1447static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
82788c7a
SH		 1448{
1449 struct sk_buff *skb;
14d0263f 1450 int i;
82788c7a 1451
68ac3191
ED		 1452 skb = __netdev_alloc_skb(sky2->netdev,
1453 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1454 gfp);
bd1c6869
SH		 1455 if (!skb)
1456 goto nomem;
1457
39dbd958 1458 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1459 unsigned char *start;
1460 /*
1461 * Workaround for a bug in FIFO that cause hang
1462 * if the FIFO if the receive buffer is not 64 byte aligned.
1463 * The buffer returned from netdev_alloc_skb is
1464 * aligned except if slab debugging is enabled.
1465 */
f03b8654
SH		 1466 start = PTR_ALIGN(skb->data, 8);
1467 skb_reserve(skb, start - skb->data);
bd1c6869 1468 } else
f03b8654 1469 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1470
1471 for (i = 0; i < sky2->rx_nfrags; i++) {
68ac3191 1472 struct page *page = alloc_page(gfp);
14d0263f
SH		 1473
1474 if (!page)
1475 goto free_partial;
1476 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1477 }
1478
1479 return skb;
14d0263f
SH		 1480free_partial:
1481 kfree_skb(skb);
1482nomem:
1483 return NULL;
82788c7a
SH		 1484}
1485
55c9dd35
SH		 1486static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1487{
1488 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1489}
1490
200ac492
MM		 1491static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1492{
1493 struct sky2_hw *hw = sky2->hw;
1494 unsigned i;
1495
1496 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1497
1498 /* Fill Rx ring */
1499 for (i = 0; i < sky2->rx_pending; i++) {
1500 struct rx_ring_info *re = sky2->rx_ring + i;
1501
68ac3191 1502 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
200ac492
MM		 1503 if (!re->skb)
1504 return -ENOMEM;
1505
1506 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1507 dev_kfree_skb(re->skb);
1508 re->skb = NULL;
1509 return -ENOMEM;
1510 }
1511 }
1512 return 0;
1513}
1514
cd28ab6a 1515/*
200ac492 1516 * Setup receiver buffer pool.
14d0263f
SH		 1517 * Normal case this ends up creating one list element for skb
1518 * in the receive ring. Worst case if using large MTU and each
1519 * allocation falls on a different 64 bit region, that results
1520 * in 6 list elements per ring entry.
1521 * One element is used for checksum enable/disable, and one
1522 * extra to avoid wrap.
cd28ab6a 1523 */
200ac492 1524static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1525{
6b1a3aef 1526 struct sky2_hw *hw = sky2->hw;
14d0263f 1527 struct rx_ring_info *re;
6b1a3aef 1528 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1529 unsigned i, thresh;
cd28ab6a 1530
6b1a3aef 1531 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1532 sky2_qset(hw, rxq);
977bdf06 1533
c3905bc4 1534 /* On PCI express lowering the watermark gives better performance */
1a10ccae 1535 if (pci_is_pcie(hw->pdev))
c3905bc4
SH		 1536 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1537
1538 /* These chips have no ram buffer?
1539 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1540 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1541 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1542 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1543
6b1a3aef
SH		 1544 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1545
ea76e635
SH		 1546 if (!(hw->flags & SKY2_HW_NEW_LE))
1547 rx_set_checksum(sky2);
14d0263f 1548
bf73130d 1549 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
f5d64037 1550 rx_set_rss(sky2->netdev, sky2->netdev->features);
bf73130d 1551
200ac492 1552 /* submit Rx ring */
793b883e 1553 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1554 re = sky2->rx_ring + i;
14d0263f 1555 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1556 }
1557
a1433ac4
SH		 1558 /*
1559 * The receiver hangs if it receives frames larger than the
1560 * packet buffer. As a workaround, truncate oversize frames, but
1561 * the register is limited to 9 bits, so if you do frames > 2052
1562 * you better get the MTU right!
1563 */
39ef110b 1564 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1565 if (thresh > 0x1ff)
1566 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1567 else {
1568 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1569 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1570 }
1571
6b1a3aef 1572 /* Tell chip about available buffers */
55c9dd35 1573 sky2_rx_update(sky2, rxq);
877c8570
SH		 1574
1575 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1576 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1577 /*
1578 * Disable flushing of non ASF packets;
1579 * must be done after initializing the BMUs;
1580 * drivers without ASF support should do this too, otherwise
1581 * it may happen that they cannot run on ASF devices;
1582 * remember that the MAC FIFO isn't reset during initialization.
1583 */
1584 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1585 }
1586
1587 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1588 /* Enable RX Home Address & Routing Header checksum fix */
1589 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1590 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1591
1592 /* Enable TX Home Address & Routing Header checksum fix */
1593 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1594 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1595 }
cd28ab6a
SH		 1596}
1597
90bbebb4
MM		 1598static int sky2_alloc_buffers(struct sky2_port *sky2)
1599{
1600 struct sky2_hw *hw = sky2->hw;
1601
1602 /* must be power of 2 */
1603 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1604 sky2->tx_ring_size *
1605 sizeof(struct sky2_tx_le),
1606 &sky2->tx_le_map);
1607 if (!sky2->tx_le)
1608 goto nomem;
1609
1610 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1611 GFP_KERNEL);
1612 if (!sky2->tx_ring)
1613 goto nomem;
1614
1615 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1616 &sky2->rx_le_map);
1617 if (!sky2->rx_le)
1618 goto nomem;
1619 memset(sky2->rx_le, 0, RX_LE_BYTES);
1620
1621 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1622 GFP_KERNEL);
1623 if (!sky2->rx_ring)
1624 goto nomem;
1625
200ac492 1626 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1627nomem:
1628 return -ENOMEM;
1629}
1630
1631static void sky2_free_buffers(struct sky2_port *sky2)
1632{
1633 struct sky2_hw *hw = sky2->hw;
1634
200ac492
MM		 1635 sky2_rx_clean(sky2);
1636
90bbebb4
MM		 1637 if (sky2->rx_le) {
1638 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1639 sky2->rx_le, sky2->rx_le_map);
1640 sky2->rx_le = NULL;
1641 }
1642 if (sky2->tx_le) {
1643 pci_free_consistent(hw->pdev,
1644 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1645 sky2->tx_le, sky2->tx_le_map);
1646 sky2->tx_le = NULL;
1647 }
1648 kfree(sky2->tx_ring);
1649 kfree(sky2->rx_ring);
1650
1651 sky2->tx_ring = NULL;
1652 sky2->rx_ring = NULL;
1653}
1654
ea0f71e5 1655static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1656{
cd28ab6a
SH		 1657 struct sky2_hw *hw = sky2->hw;
1658 unsigned port = sky2->port;
ea0f71e5
MM		 1659 u32 ramsize;
1660 int cap;
843a46f4 1661 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1662
ea0f71e5
MM		 1663 tx_init(sky2);
1664
ee7abb04
SH		 1665 /*
1666 * On dual port PCI-X card, there is an problem where status
1667 * can be received out of order due to split transactions
843a46f4 1668 */
ee7abb04
SH		 1669 if (otherdev && netif_running(otherdev) &&
1670 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1671 u16 cmd;
1672
b32f40c4 1673 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1674 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1675 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1676 }
cd28ab6a 1677
cd28ab6a
SH		 1678 sky2_mac_init(hw, port);
1679
e0c28116
SH		 1680 /* Register is number of 4K blocks on internal RAM buffer. */
1681 ramsize = sky2_read8(hw, B2_E_0) * 4;
1682 if (ramsize > 0) {
67712901 1683 u32 rxspace;
cd28ab6a 1684
ada1db5c 1685 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1686 if (ramsize < 16)
1687 rxspace = ramsize / 2;
1688 else
1689 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1690
67712901
SH		 1691 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1692 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1693
1694 /* Make sure SyncQ is disabled */
1695 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1696 RB_RST_SET);
1697 }
793b883e 1698
af4ed7e6 1699 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1700
69161611
SH		 1701 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1702 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1703 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1704
977bdf06 1705 /* Set almost empty threshold */
8e95a202
JP		 1706 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1707 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1708 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1709
6b1a3aef 1710 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1711 sky2->tx_ring_size - 1);
cd28ab6a 1712
f5d64037
MM		 1713 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1714 netdev_update_features(sky2->netdev);
d494eacd 1715
200ac492 1716 sky2_rx_start(sky2);
ea0f71e5
MM		 1717}
1718
0bdb0bd0 1719/* Setup device IRQ and enable napi to process */
1720static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1721{
1722 struct pci_dev *pdev = hw->pdev;
1723 int err;
1724
1725 err = request_irq(pdev->irq, sky2_intr,
1726 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1727 name, hw);
1728 if (err)
1729 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1730 else {
1731 napi_enable(&hw->napi);
1732 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1733 sky2_read32(hw, B0_IMSK);
1734 }
1735
1736 return err;
1737}
1738
1739
ea0f71e5
MM		 1740/* Bring up network interface. */
1741static int sky2_up(struct net_device *dev)
1742{
1743 struct sky2_port *sky2 = netdev_priv(dev);
1744 struct sky2_hw *hw = sky2->hw;
1745 unsigned port = sky2->port;
1746 u32 imask;
1747 int err;
1748
1749 netif_carrier_off(dev);
1750
1751 err = sky2_alloc_buffers(sky2);
1752 if (err)
1753 goto err_out;
1754
0bdb0bd0 1755 /* With single port, IRQ is setup when device is brought up */
1756 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1757 goto err_out;
1758
ea0f71e5 1759 sky2_hw_up(sky2);
cd28ab6a 1760
cd28ab6a 1761 /* Enable interrupts from phy/mac for port */
e07b1aa8 1762 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1763 imask |= portirq_msk[port];
e07b1aa8 1764 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1765 sky2_read32(hw, B0_IMSK);
e07b1aa8 1766
6c35abae 1767 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1768
cd28ab6a
SH		 1769 return 0;
1770
1771err_out:
90bbebb4 1772 sky2_free_buffers(sky2);
cd28ab6a
SH		 1773 return err;
1774}
1775
793b883e 1776/* Modular subtraction in ring */
ee5f68fe 1777static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1778{
ee5f68fe 1779 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1780}
cd28ab6a 1781
793b883e
SH		 1782/* Number of list elements available for next tx */
1783static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1784{
ee5f68fe 1785 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1786}
1787
793b883e 1788/* Estimate of number of transmit list elements required */
28bd181a 1789static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1790{
793b883e
SH		 1791 unsigned count;
1792
07e31637
SH		 1793 count = (skb_shinfo(skb)->nr_frags + 1)
1794 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1795
89114afd 1796 if (skb_is_gso(skb))
793b883e 1797 ++count;
07e31637
SH		 1798 else if (sizeof(dma_addr_t) == sizeof(u32))
1799 ++count; /* possible vlan */
793b883e 1800
84fa7933 1801 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1802 ++count;
1803
1804 return count;
cd28ab6a
SH		 1805}
1806
f6815077 1807static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1808{
1809 if (re->flags & TX_MAP_SINGLE)
7cd26ce5
FT		 1810 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1811 dma_unmap_len(re, maplen),
6b84daca
SH		 1812 PCI_DMA_TODEVICE);
1813 else if (re->flags & TX_MAP_PAGE)
7cd26ce5
FT		 1814 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1815 dma_unmap_len(re, maplen),
6b84daca 1816 PCI_DMA_TODEVICE);
f6815077 1817 re->flags = 0;
6b84daca
SH		 1818}
1819
793b883e
SH		 1820/*
1821 * Put one packet in ring for transmit.
1822 * A single packet can generate multiple list elements, and
1823 * the number of ring elements will probably be less than the number
1824 * of list elements used.
1825 */
61357325
SH		 1826static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1827 struct net_device *dev)
cd28ab6a
SH		 1828{
1829 struct sky2_port *sky2 = netdev_priv(dev);
1830 struct sky2_hw *hw = sky2->hw;
d1f13708 1831 struct sky2_tx_le *le = NULL;
6cdbbdf3 1832 struct tx_ring_info *re;
9b289c33 1833 unsigned i, len;
cd28ab6a 1834 dma_addr_t mapping;
5dce95e5
SH		 1835 u32 upper;
1836 u16 slot;
cd28ab6a
SH		 1837 u16 mss;
1838 u8 ctrl;
1839
2bb8c262
SH		 1840 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1841 return NETDEV_TX_BUSY;
cd28ab6a 1842
cd28ab6a
SH		 1843 len = skb_headlen(skb);
1844 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1845
454e6cb6
SH		 1846 if (pci_dma_mapping_error(hw->pdev, mapping))
1847 goto mapping_error;
1848
9b289c33 1849 slot = sky2->tx_prod;
6c35abae
JP		 1850 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1851 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1852
86c6887e 1853 /* Send high bits if needed */
5dce95e5
SH		 1854 upper = upper_32_bits(mapping);
1855 if (upper != sky2->tx_last_upper) {
9b289c33 1856 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1857 le->addr = cpu_to_le32(upper);
1858 sky2->tx_last_upper = upper;
793b883e 1859 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1860 }
cd28ab6a
SH		 1861
1862 /* Check for TCP Segmentation Offload */
7967168c 1863 mss = skb_shinfo(skb)->gso_size;
793b883e 1864 if (mss != 0) {
ea76e635
SH		 1865
1866 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1867 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1868
1869 if (mss != sky2->tx_last_mss) {
9b289c33 1870 le = get_tx_le(sky2, &slot);
69161611 1871 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1872
1873 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1874 le->opcode = OP_MSS | HW_OWNER;
1875 else
1876 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1877 sky2->tx_last_mss = mss;
1878 }
cd28ab6a
SH		 1879 }
1880
cd28ab6a 1881 ctrl = 0;
86aa7785 1882
d1f13708 1883 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
eab6d18d 1884 if (vlan_tx_tag_present(skb)) {
d1f13708 1885 if (!le) {
9b289c33 1886 le = get_tx_le(sky2, &slot);
f65b138c 1887 le->addr = 0;
d1f13708 1888 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1889 } else
1890 le->opcode |= OP_VLAN;
1891 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1892 ctrl |= INS_VLAN;
1893 }
d1f13708
SH		 1894
1895 /* Handle TCP checksum offload */
84fa7933 1896 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1897 /* On Yukon EX (some versions) encoding change. */
ea76e635 1898 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1899 ctrl |= CALSUM; /* auto checksum */
1900 else {
1901 const unsigned offset = skb_transport_offset(skb);
1902 u32 tcpsum;
1903
1904 tcpsum = offset << 16; /* sum start */
1905 tcpsum |= offset + skb->csum_offset; /* sum write */
1906
1907 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1908 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1909 ctrl |= UDPTCP;
1910
1911 if (tcpsum != sky2->tx_tcpsum) {
1912 sky2->tx_tcpsum = tcpsum;
1913
9b289c33 1914 le = get_tx_le(sky2, &slot);
69161611
SH		 1915 le->addr = cpu_to_le32(tcpsum);
1916 le->length = 0; /* initial checksum value */
1917 le->ctrl = 1; /* one packet */
1918 le->opcode = OP_TCPLISW | HW_OWNER;
1919 }
1d179332 1920 }
cd28ab6a
SH		 1921 }
1922
6b84daca
SH		 1923 re = sky2->tx_ring + slot;
1924 re->flags = TX_MAP_SINGLE;
7cd26ce5
FT		 1925 dma_unmap_addr_set(re, mapaddr, mapping);
1926 dma_unmap_len_set(re, maplen, len);
6b84daca 1927
9b289c33 1928 le = get_tx_le(sky2, &slot);
d6e74b6b 1929 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1930 le->length = cpu_to_le16(len);
1931 le->ctrl = ctrl;
793b883e 1932 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1933
cd28ab6a
SH		 1934
1935 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1936 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a 1937
950a5a4f 1938 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
9e903e08 1939 skb_frag_size(frag), DMA_TO_DEVICE);
86c6887e 1940
5d6bcdfe 1941 if (dma_mapping_error(&hw->pdev->dev, mapping))
454e6cb6
SH		 1942 goto mapping_unwind;
1943
5dce95e5
SH		 1944 upper = upper_32_bits(mapping);
1945 if (upper != sky2->tx_last_upper) {
9b289c33 1946 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1947 le->addr = cpu_to_le32(upper);
1948 sky2->tx_last_upper = upper;
793b883e 1949 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1950 }
1951
6b84daca
SH		 1952 re = sky2->tx_ring + slot;
1953 re->flags = TX_MAP_PAGE;
7cd26ce5 1954 dma_unmap_addr_set(re, mapaddr, mapping);
9e903e08 1955 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
6b84daca 1956
9b289c33 1957 le = get_tx_le(sky2, &slot);
d6e74b6b 1958 le->addr = cpu_to_le32(lower_32_bits(mapping));
9e903e08 1959 le->length = cpu_to_le16(skb_frag_size(frag));
cd28ab6a 1960 le->ctrl = ctrl;
793b883e 1961 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1962 }
6cdbbdf3 1963
6b84daca 1964 re->skb = skb;
cd28ab6a
SH		 1965 le->ctrl |= EOP;
1966
9b289c33
MM		 1967 sky2->tx_prod = slot;
1968
97bda706
SH		 1969 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1970 netif_stop_queue(dev);
b19666d9 1971
290d4de5 1972 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1973
cd28ab6a 1974 return NETDEV_TX_OK;
454e6cb6
SH		 1975
1976mapping_unwind:
ee5f68fe 1977 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1978 re = sky2->tx_ring + i;
1979
6b84daca 1980 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1981 }
1982
454e6cb6
SH		 1983mapping_error:
1984 if (net_ratelimit())
1985 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1986 dev_kfree_skb(skb);
1987 return NETDEV_TX_OK;
cd28ab6a
SH		 1988}
1989
cd28ab6a 1990/*
793b883e
SH		 1991 * Free ring elements from starting at tx_cons until "done"
1992 *
481cea4a
SH		 1993 * NB:
1994 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1995 * buffers so make sure not to free skb to early.
481cea4a
SH		 1996 * 2. This may run in parallel start_xmit because the it only
1997 * looks at the tail of the queue of FIFO (tx_cons), not
1998 * the head (tx_prod)
cd28ab6a 1999 */
d11c13e7 2000static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 2001{
d11c13e7 2002 struct net_device *dev = sky2->netdev;
291ea614 2003 unsigned idx;
cd28ab6a 2004
ee5f68fe 2005 BUG_ON(done >= sky2->tx_ring_size);
2224795d 2006
291ea614 2007 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 2008 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 2009 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 2010 struct sk_buff *skb = re->skb;
291ea614 2011
6b84daca 2012 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 2013
6b84daca 2014 if (skb) {
6c35abae
JP		 2015 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2016 "tx done %u\n", idx);
3cf26753 2017
0885a30b 2018 u64_stats_update_begin(&sky2->tx_stats.syncp);
2019 ++sky2->tx_stats.packets;
2020 sky2->tx_stats.bytes += skb->len;
2021 u64_stats_update_end(&sky2->tx_stats.syncp);
bd1c6869 2022
f6815077 2023 re->skb = NULL;
724b6942 2024 dev_kfree_skb_any(skb);
2bf56fe2 2025
ee5f68fe 2026 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 2027 }
793b883e 2028 }
793b883e 2029
291ea614 2030 sky2->tx_cons = idx;
50432cb5 2031 smp_mb();
cd28ab6a
SH		 2032}
2033
264bb4fa 2034static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 2035{
a510996b
MM		 2036 /* Disable Force Sync bit and Enable Alloc bit */
2037 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2038 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2039
2040 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2041 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2042 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2043
2044 /* Reset the PCI FIFO of the async Tx queue */
2045 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2046 BMU_RST_SET | BMU_FIFO_RST);
2047
2048 /* Reset the Tx prefetch units */
2049 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2050 PREF_UNIT_RST_SET);
2051
2052 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2053 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2054}
2055
f2b31cb3 2056static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 2057{
cd28ab6a
SH		 2058 struct sky2_hw *hw = sky2->hw;
2059 unsigned port = sky2->port;
f2b31cb3 2060 u16 ctrl;
cd28ab6a 2061
d104acaf
SH		 2062 /* Force flow control off */
2063 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 2064
cd28ab6a
SH		 2065 /* Stop transmitter */
2066 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2067 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2068
2069 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 2070 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 2071
2072 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 2073 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 2074 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2075
2076 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2077
2078 /* Workaround shared GMAC reset */
8e95a202
JP		 2079 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2080 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 2081 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2082
cd28ab6a 2083 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 2084
6c83504f
SH		 2085 /* Force any delayed status interrrupt and NAPI */
2086 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2087 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2088 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2089 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2090
a947a39d
MM		 2091 sky2_rx_stop(sky2);
2092
0da6d7b3 2093 spin_lock_bh(&sky2->phy_lock);
b96936da 2094 sky2_phy_power_down(hw, port);
0da6d7b3 2095 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 2096
264bb4fa
MM		 2097 sky2_tx_reset(hw, port);
2098
481cea4a
SH		 2099 /* Free any pending frames stuck in HW queue */
2100 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 2101}
2102
2103/* Network shutdown */
2104static int sky2_down(struct net_device *dev)
2105{
2106 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 2107 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 2108
2109 /* Never really got started! */
2110 if (!sky2->tx_le)
2111 return 0;
2112
6c35abae 2113 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 2114
8a0c9228
MM		 2115 /* Disable port IRQ */
2116 sky2_write32(hw, B0_IMSK,
2117 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2118 sky2_read32(hw, B0_IMSK);
2119
0bdb0bd0 2120 if (hw->ports == 1) {
2121 napi_disable(&hw->napi);
2122 free_irq(hw->pdev->irq, hw);
2123 } else {
2124 synchronize_irq(hw->pdev->irq);
2125 napi_synchronize(&hw->napi);
2126 }
8a0c9228 2127
f2b31cb3 2128 sky2_hw_down(sky2);
481cea4a 2129
90bbebb4 2130 sky2_free_buffers(sky2);
1b537565 2131
cd28ab6a
SH		 2132 return 0;
2133}
2134
2135static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2136{
ea76e635 2137 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 2138 return SPEED_1000;
2139
05745c4a
SH		 2140 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2141 if (aux & PHY_M_PS_SPEED_100)
2142 return SPEED_100;
2143 else
2144 return SPEED_10;
2145 }
cd28ab6a
SH		 2146
2147 switch (aux & PHY_M_PS_SPEED_MSK) {
2148 case PHY_M_PS_SPEED_1000:
2149 return SPEED_1000;
2150 case PHY_M_PS_SPEED_100:
2151 return SPEED_100;
2152 default:
2153 return SPEED_10;
2154 }
2155}
2156
2157static void sky2_link_up(struct sky2_port *sky2)
2158{
2159 struct sky2_hw *hw = sky2->hw;
2160 unsigned port = sky2->port;
16ad91e1
SH		 2161 static const char *fc_name[] = {
2162 [FC_NONE] = "none",
2163 [FC_TX] = "tx",
2164 [FC_RX] = "rx",
2165 [FC_BOTH] = "both",
2166 };
cd28ab6a 2167
8e11680f 2168 sky2_set_ipg(sky2);
2169
38000a94 2170 sky2_enable_rx_tx(sky2);
cd28ab6a
SH		 2171
2172 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2173
2174 netif_carrier_on(sky2->netdev);
cd28ab6a 2175
75e80683 2176 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2177
cd28ab6a 2178 /* Turn on link LED */
793b883e 2179 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2180 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2181
6c35abae
JP		 2182 netif_info(sky2, link, sky2->netdev,
2183 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2184 sky2->speed,
2185 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2186 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2187}
2188
2189static void sky2_link_down(struct sky2_port *sky2)
2190{
2191 struct sky2_hw *hw = sky2->hw;
2192 unsigned port = sky2->port;
2193 u16 reg;
2194
2195 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2196
2197 reg = gma_read16(hw, port, GM_GP_CTRL);
2198 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2199 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2200
cd28ab6a 2201 netif_carrier_off(sky2->netdev);
cd28ab6a 2202
809aaaae 2203 /* Turn off link LED */
cd28ab6a
SH		 2204 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2205
6c35abae 2206 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2207
cd28ab6a
SH		 2208 sky2_phy_init(hw, port);
2209}
2210
16ad91e1
SH		 2211static enum flow_control sky2_flow(int rx, int tx)
2212{
2213 if (rx)
2214 return tx ? FC_BOTH : FC_RX;
2215 else
2216 return tx ? FC_TX : FC_NONE;
2217}
2218
793b883e
SH		 2219static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2220{
2221 struct sky2_hw *hw = sky2->hw;
2222 unsigned port = sky2->port;
da4c1ff4 2223 u16 advert, lpa;
793b883e 2224
da4c1ff4 2225 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2226 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2227 if (lpa & PHY_M_AN_RF) {
ada1db5c 2228 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2229 return -1;
2230 }
2231
793b883e 2232 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2233 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2234 return -1;
2235 }
2236
793b883e 2237 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2238 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2239
da4c1ff4
SH		 2240 /* Since the pause result bits seem to in different positions on
2241 * different chips. look at registers.
2242 */
ea76e635 2243 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2244 /* Shift for bits in fiber PHY */
2245 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2246 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2247
2248 if (advert & ADVERTISE_1000XPAUSE)
2249 advert |= ADVERTISE_PAUSE_CAP;
2250 if (advert & ADVERTISE_1000XPSE_ASYM)
2251 advert |= ADVERTISE_PAUSE_ASYM;
2252 if (lpa & LPA_1000XPAUSE)
2253 lpa |= LPA_PAUSE_CAP;
2254 if (lpa & LPA_1000XPAUSE_ASYM)
2255 lpa |= LPA_PAUSE_ASYM;
2256 }
793b883e 2257
da4c1ff4
SH		 2258 sky2->flow_status = FC_NONE;
2259 if (advert & ADVERTISE_PAUSE_CAP) {
2260 if (lpa & LPA_PAUSE_CAP)
2261 sky2->flow_status = FC_BOTH;
2262 else if (advert & ADVERTISE_PAUSE_ASYM)
2263 sky2->flow_status = FC_RX;
2264 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2265 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2266 sky2->flow_status = FC_TX;
2267 }
793b883e 2268
8e95a202
JP		 2269 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2270 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2271 sky2->flow_status = FC_NONE;
2eaba1a2 2272
da4c1ff4 2273 if (sky2->flow_status & FC_TX)
793b883e
SH		 2274 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2275 else
2276 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2277
2278 return 0;
2279}
cd28ab6a 2280
e07b1aa8
SH		 2281/* Interrupt from PHY */
2282static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2283{
e07b1aa8
SH		 2284 struct net_device *dev = hw->dev[port];
2285 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2286 u16 istatus, phystat;
2287
ebc646f6
SH		 2288 if (!netif_running(dev))
2289 return;
2290
e07b1aa8
SH		 2291 spin_lock(&sky2->phy_lock);
2292 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2293 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2294
6c35abae
JP		 2295 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2296 istatus, phystat);
cd28ab6a 2297
0ea065e5 2298 if (istatus & PHY_M_IS_AN_COMPL) {
9badba25 2299 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2300 !netif_carrier_ok(dev))
793b883e
SH		 2301 sky2_link_up(sky2);
2302 goto out;
2303 }
cd28ab6a 2304
793b883e
SH		 2305 if (istatus & PHY_M_IS_LSP_CHANGE)
2306 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2307
793b883e
SH		 2308 if (istatus & PHY_M_IS_DUP_CHANGE)
2309 sky2->duplex =
2310 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2311
793b883e
SH		 2312 if (istatus & PHY_M_IS_LST_CHANGE) {
2313 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2314 sky2_link_up(sky2);
793b883e
SH		 2315 else
2316 sky2_link_down(sky2);
cd28ab6a 2317 }
793b883e 2318out:
e07b1aa8 2319 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2320}
2321
0f5aac70
SH		 2322/* Special quick link interrupt (Yukon-2 Optima only) */
2323static void sky2_qlink_intr(struct sky2_hw *hw)
2324{
2325 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2326 u32 imask;
2327 u16 phy;
2328
2329 /* disable irq */
2330 imask = sky2_read32(hw, B0_IMSK);
2331 imask &= ~Y2_IS_PHY_QLNK;
2332 sky2_write32(hw, B0_IMSK, imask);
2333
2334 /* reset PHY Link Detect */
2335 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2336 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2337 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2338 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2339
2340 sky2_link_up(sky2);
2341}
2342
62335ab0 2343/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2344 * and tx queue is full (stopped).
2345 */
cd28ab6a
SH		 2346static void sky2_tx_timeout(struct net_device *dev)
2347{
2348 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2349 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2350
6c35abae 2351 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2352
ada1db5c
JP		 2353 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2354 sky2->tx_cons, sky2->tx_prod,
2355 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2356 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2357
81906791
SH		 2358 /* can't restart safely under softirq */
2359 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2360}
2361
2362static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2363{
6b1a3aef
SH		 2364 struct sky2_port *sky2 = netdev_priv(dev);
2365 struct sky2_hw *hw = sky2->hw;
b628ed98 2366 unsigned port = sky2->port;
6b1a3aef
SH		 2367 int err;
2368 u16 ctl, mode;
e07b1aa8 2369 u32 imask;
cd28ab6a 2370
44dde56d 2371 /* MTU size outside the spec */
cd28ab6a
SH		 2372 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2373 return -EINVAL;
2374
44dde56d 2375 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2376 if (new_mtu > ETH_DATA_LEN &&
2377 (hw->chip_id == CHIP_ID_YUKON_FE ||
2378 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2379 return -EINVAL;
2380
6b1a3aef
SH		 2381 if (!netif_running(dev)) {
2382 dev->mtu = new_mtu;
f5d64037 2383 netdev_update_features(dev);
6b1a3aef
SH		 2384 return 0;
2385 }
2386
e07b1aa8 2387 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2388 sky2_write32(hw, B0_IMSK, 0);
2389
018d1c66 2390 dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 2391 napi_disable(&hw->napi);
df01093b 2392 netif_tx_disable(dev);
018d1c66 2393
e07b1aa8
SH		 2394 synchronize_irq(hw->pdev->irq);
2395
39dbd958 2396 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2397 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2398
2399 ctl = gma_read16(hw, port, GM_GP_CTRL);
2400 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2401 sky2_rx_stop(sky2);
2402 sky2_rx_clean(sky2);
cd28ab6a
SH		 2403
2404 dev->mtu = new_mtu;
f5d64037 2405 netdev_update_features(dev);
14d0263f 2406
8e11680f 2407 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2408 if (sky2->speed > SPEED_100)
2409 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2410 else
2411 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
6b1a3aef
SH		 2412
2413 if (dev->mtu > ETH_DATA_LEN)
2414 mode |= GM_SMOD_JUMBO_ENA;
2415
b628ed98 2416 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2417
b628ed98 2418 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2419
200ac492
MM		 2420 err = sky2_alloc_rx_skbs(sky2);
2421 if (!err)
2422 sky2_rx_start(sky2);
2423 else
2424 sky2_rx_clean(sky2);
e07b1aa8 2425 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2426
d1d08d12 2427 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2428 napi_enable(&hw->napi);
2429
1b537565
SH		 2430 if (err)
2431 dev_close(dev);
2432 else {
b628ed98 2433 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2434
1b537565
SH		 2435 netif_wake_queue(dev);
2436 }
2437
cd28ab6a
SH		 2438 return err;
2439}
2440
14d0263f
SH		 2441/* For small just reuse existing skb for next receive */
2442static struct sk_buff *receive_copy(struct sky2_port *sky2,
2443 const struct rx_ring_info *re,
2444 unsigned length)
2445{
2446 struct sk_buff *skb;
2447
89d71a66 2448 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2449 if (likely(skb)) {
14d0263f
SH		 2450 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2451 length, PCI_DMA_FROMDEVICE);
d626f62b 2452 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2453 skb->ip_summed = re->skb->ip_summed;
2454 skb->csum = re->skb->csum;
2455 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2456 length, PCI_DMA_FROMDEVICE);
2457 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2458 skb_put(skb, length);
14d0263f
SH		 2459 }
2460 return skb;
2461}
2462
2463/* Adjust length of skb with fragments to match received data */
2464static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2465 unsigned int length)
2466{
2467 int i, num_frags;
2468 unsigned int size;
2469
2470 /* put header into skb */
2471 size = min(length, hdr_space);
2472 skb->tail += size;
2473 skb->len += size;
2474 length -= size;
2475
2476 num_frags = skb_shinfo(skb)->nr_frags;
2477 for (i = 0; i < num_frags; i++) {
2478 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2479
2480 if (length == 0) {
2481 /* don't need this page */
950a5a4f 2482 __skb_frag_unref(frag);
14d0263f
SH		 2483 --skb_shinfo(skb)->nr_frags;
2484 } else {
2485 size = min(length, (unsigned) PAGE_SIZE);
2486
9e903e08 2487 skb_frag_size_set(frag, size);
14d0263f 2488 skb->data_len += size;
7ae60b3f 2489 skb->truesize += PAGE_SIZE;
14d0263f
SH		 2490 skb->len += size;
2491 length -= size;
2492 }
2493 }
2494}
2495
2496/* Normal packet - take skb from ring element and put in a new one */
2497static struct sk_buff *receive_new(struct sky2_port *sky2,
2498 struct rx_ring_info *re,
2499 unsigned int length)
2500{
3fbd9187 2501 struct sk_buff *skb;
2502 struct rx_ring_info nre;
14d0263f
SH		 2503 unsigned hdr_space = sky2->rx_data_size;
2504
68ac3191 2505 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
3fbd9187 2506 if (unlikely(!nre.skb))
2507 goto nobuf;
2508
2509 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2510 goto nomap;
14d0263f
SH		 2511
2512 skb = re->skb;
2513 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2514 prefetch(skb->data);
3fbd9187 2515 *re = nre;
14d0263f
SH		 2516
2517 if (skb_shinfo(skb)->nr_frags)
2518 skb_put_frags(skb, hdr_space, length);
2519 else
489b10c1 2520 skb_put(skb, length);
14d0263f 2521 return skb;
3fbd9187 2522
2523nomap:
2524 dev_kfree_skb(nre.skb);
2525nobuf:
2526 return NULL;
14d0263f
SH		 2527}
2528
cd28ab6a
SH		 2529/*
2530 * Receive one packet.
d571b694 2531 * For larger packets, get new buffer.
cd28ab6a 2532 */
497d7c86 2533static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2534 u16 length, u32 status)
2535{
497d7c86 2536 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2537 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2538 struct sk_buff *skb = NULL;
d6532232
SH		 2539 u16 count = (status & GMR_FS_LEN) >> 16;
2540
86aa7785
SH		 2541 if (status & GMR_FS_VLAN)
2542 count -= VLAN_HLEN; /* Account for vlan tag */
cd28ab6a 2543
6c35abae
JP		 2544 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2545 "rx slot %u status 0x%x len %d\n",
2546 sky2->rx_next, status, length);
cd28ab6a 2547
793b883e 2548 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2549 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2550
3b12e014
SH		 2551 /* This chip has hardware problems that generates bogus status.
2552 * So do only marginal checking and expect higher level protocols
2553 * to handle crap frames.
2554 */
2555 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2556 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2557 length != count)
2558 goto okay;
2559
42eeea01 2560 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2561 goto error;
2562
42eeea01
SH		 2563 if (!(status & GMR_FS_RX_OK))
2564 goto resubmit;
2565
d6532232
SH		 2566 /* if length reported by DMA does not match PHY, packet was truncated */
2567 if (length != count)
0885a30b 2568 goto error;
71749531 2569
3b12e014 2570okay:
14d0263f
SH		 2571 if (length < copybreak)
2572 skb = receive_copy(sky2, re, length);
2573 else
2574 skb = receive_new(sky2, re, length);
90c30335
SH		 2575
2576 dev->stats.rx_dropped += (skb == NULL);
2577
793b883e 2578resubmit:
14d0263f 2579 sky2_rx_submit(sky2, re);
79e57d32 2580
cd28ab6a
SH		 2581 return skb;
2582
2583error:
7138a0f5 2584 ++dev->stats.rx_errors;
6e15b712 2585
6c35abae
JP		 2586 if (net_ratelimit())
2587 netif_info(sky2, rx_err, dev,
2588 "rx error, status 0x%x length %d\n", status, length);
793b883e 2589
793b883e 2590 goto resubmit;
cd28ab6a
SH		 2591}
2592
e07b1aa8
SH		 2593/* Transmit complete */
2594static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2595{
e07b1aa8 2596 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2597
8a0c9228 2598 if (netif_running(dev)) {
e07b1aa8 2599 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2600
2601 /* Wake unless it's detached, and called e.g. from sky2_down() */
2602 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2603 netif_wake_queue(dev);
2604 }
cd28ab6a
SH		 2605}
2606
37e5a243
SH		 2607static inline void sky2_skb_rx(const struct sky2_port *sky2,
2608 u32 status, struct sk_buff *skb)
2609{
86aa7785
SH		 2610 if (status & GMR_FS_VLAN)
2611 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2612
37e5a243
SH		 2613 if (skb->ip_summed == CHECKSUM_NONE)
2614 netif_receive_skb(skb);
2615 else
2616 napi_gro_receive(&sky2->hw->napi, skb);
2617}
2618
bf15fe99
SH		 2619static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2620 unsigned packets, unsigned bytes)
2621{
0885a30b 2622 struct net_device *dev = hw->dev[port];
2623 struct sky2_port *sky2 = netdev_priv(dev);
bf15fe99 2624
0885a30b 2625 if (packets == 0)
2626 return;
2627
2628 u64_stats_update_begin(&sky2->rx_stats.syncp);
2629 sky2->rx_stats.packets += packets;
2630 sky2->rx_stats.bytes += bytes;
2631 u64_stats_update_end(&sky2->rx_stats.syncp);
2632
2633 dev->last_rx = jiffies;
2634 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
bf15fe99
SH		 2635}
2636
375c5688 2637static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2638{
2639 /* If this happens then driver assuming wrong format for chip type */
2640 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2641
2642 /* Both checksum counters are programmed to start at
2643 * the same offset, so unless there is a problem they
2644 * should match. This failure is an early indication that
2645 * hardware receive checksumming won't work.
2646 */
2647 if (likely((u16)(status >> 16) == (u16)status)) {
2648 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2649 skb->ip_summed = CHECKSUM_COMPLETE;
2650 skb->csum = le16_to_cpu(status);
2651 } else {
2652 dev_notice(&sky2->hw->pdev->dev,
2653 "%s: receive checksum problem (status = %#x)\n",
2654 sky2->netdev->name, status);
2655
f5d64037
MM		 2656 /* Disable checksum offload
2657 * It will be reenabled on next ndo_set_features, but if it's
2658 * really broken, will get disabled again
2659 */
2660 sky2->netdev->features &= ~NETIF_F_RXCSUM;
375c5688 2661 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2662 BMU_DIS_RX_CHKSUM);
2663 }
2664}
2665
bf73130d
SH		 2666static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2667{
2668 struct sk_buff *skb;
2669
2670 skb = sky2->rx_ring[sky2->rx_next].skb;
2671 skb->rxhash = le32_to_cpu(status);
2672}
2673
e07b1aa8 2674/* Process status response ring */
26691830 2675static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2676{
e07b1aa8 2677 int work_done = 0;
bf15fe99
SH		 2678 unsigned int total_bytes[2] = { 0 };
2679 unsigned int total_packets[2] = { 0 };
a8fd6266 2680
af2a58ac 2681 rmb();
26691830 2682 do {
55c9dd35 2683 struct sky2_port *sky2;
13210ce5 2684 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2685 unsigned port;
13210ce5 2686 struct net_device *dev;
cd28ab6a 2687 struct sk_buff *skb;
cd28ab6a
SH		 2688 u32 status;
2689 u16 length;
ab5adecb
SH		 2690 u8 opcode = le->opcode;
2691
2692 if (!(opcode & HW_OWNER))
2693 break;
cd28ab6a 2694
efe91932 2695 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
bea86103 2696
ab5adecb 2697 port = le->css & CSS_LINK_BIT;
69161611 2698 dev = hw->dev[port];
13210ce5 2699 sky2 = netdev_priv(dev);
f65b138c
SH		 2700 length = le16_to_cpu(le->length);
2701 status = le32_to_cpu(le->status);
cd28ab6a 2702
ab5adecb
SH		 2703 le->opcode = 0;
2704 switch (opcode & ~HW_OWNER) {
cd28ab6a 2705 case OP_RXSTAT:
bf15fe99
SH		 2706 total_packets[port]++;
2707 total_bytes[port] += length;
90c30335 2708
497d7c86 2709 skb = sky2_receive(dev, length, status);
90c30335 2710 if (!skb)
55c9dd35 2711 break;
13210ce5 2712
69161611 2713 /* This chip reports checksum status differently */
05745c4a 2714 if (hw->flags & SKY2_HW_NEW_LE) {
f5d64037 2715 if ((dev->features & NETIF_F_RXCSUM) &&
69161611
SH		 2716 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2717 (le->css & CSS_TCPUDPCSOK))
2718 skb->ip_summed = CHECKSUM_UNNECESSARY;
2719 else
2720 skb->ip_summed = CHECKSUM_NONE;
2721 }
2722
13210ce5 2723 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2724
37e5a243 2725 sky2_skb_rx(sky2, status, skb);
13210ce5 2726
22e11703 2727 /* Stop after net poll weight */
13210ce5
SH		 2728 if (++work_done >= to_do)
2729 goto exit_loop;
cd28ab6a
SH		 2730 break;
2731
d1f13708
SH		 2732 case OP_RXVLAN:
2733 sky2->rx_tag = length;
2734 break;
2735
2736 case OP_RXCHKSVLAN:
2737 sky2->rx_tag = length;
2738 /* fall through */
cd28ab6a 2739 case OP_RXCHKS:
f5d64037 2740 if (likely(dev->features & NETIF_F_RXCSUM))
375c5688 2741 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2742 break;
2743
bf73130d
SH		 2744 case OP_RSS_HASH:
2745 sky2_rx_hash(sky2, status);
2746 break;
2747
cd28ab6a 2748 case OP_TXINDEXLE:
13b97b74 2749 /* TX index reports status for both ports */
f55925d7 2750 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2751 if (hw->dev[1])
2752 sky2_tx_done(hw->dev[1],
2753 ((status >> 24) & 0xff)
2754 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2755 break;
2756
cd28ab6a
SH		 2757 default:
2758 if (net_ratelimit())
ada1db5c 2759 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2760 }
26691830 2761 } while (hw->st_idx != idx);
cd28ab6a 2762
fe2a24df
SH		 2763 /* Fully processed status ring so clear irq */
2764 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2765
13210ce5 2766exit_loop:
bf15fe99
SH		 2767 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2768 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2769
e07b1aa8 2770 return work_done;
cd28ab6a
SH		 2771}
2772
2773static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2774{
2775 struct net_device *dev = hw->dev[port];
2776
3be92a70 2777 if (net_ratelimit())
ada1db5c 2778 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2779
2780 if (status & Y2_IS_PAR_RD1) {
3be92a70 2781 if (net_ratelimit())
ada1db5c 2782 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2783 /* Clear IRQ */
2784 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2785 }
2786
2787 if (status & Y2_IS_PAR_WR1) {
3be92a70 2788 if (net_ratelimit())
ada1db5c 2789 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2790
2791 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2792 }
2793
2794 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2795 if (net_ratelimit())
ada1db5c 2796 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2797 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2798 }
2799
2800 if (status & Y2_IS_PAR_RX1) {
3be92a70 2801 if (net_ratelimit())
ada1db5c 2802 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2803 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2804 }
2805
2806 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2807 if (net_ratelimit())
ada1db5c 2808 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2809 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2810 }
2811}
2812
2813static void sky2_hw_intr(struct sky2_hw *hw)
2814{
555382cb 2815 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2816 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2817 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2818
2819 status &= hwmsk;
cd28ab6a 2820
793b883e 2821 if (status & Y2_IS_TIST_OV)
cd28ab6a 2822 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2823
2824 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2825 u16 pci_err;
2826
a40ccc68 2827 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2828 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2829 if (net_ratelimit())
555382cb 2830 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2831 pci_err);
cd28ab6a 2832
b32f40c4 2833 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2834 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2835 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2836 }
2837
2838 if (status & Y2_IS_PCI_EXP) {
d571b694 2839 /* PCI-Express uncorrectable Error occurred */
555382cb 2840 u32 err;
cd28ab6a 2841
a40ccc68 2842 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2843 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2844 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2845 0xfffffffful);
3be92a70 2846 if (net_ratelimit())
555382cb 2847 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2848
7782c8c4 2849 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2850 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2851 }
2852
2853 if (status & Y2_HWE_L1_MASK)
2854 sky2_hw_error(hw, 0, status);
2855 status >>= 8;
2856 if (status & Y2_HWE_L1_MASK)
2857 sky2_hw_error(hw, 1, status);
2858}
2859
2860static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2861{
2862 struct net_device *dev = hw->dev[port];
2863 struct sky2_port *sky2 = netdev_priv(dev);
2864 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2865
6c35abae 2866 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2867
a3caeada
SH		 2868 if (status & GM_IS_RX_CO_OV)
2869 gma_read16(hw, port, GM_RX_IRQ_SRC);
2870
2871 if (status & GM_IS_TX_CO_OV)
2872 gma_read16(hw, port, GM_TX_IRQ_SRC);
2873
cd28ab6a 2874 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2875 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2876 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2877 }
2878
2879 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2880 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2881 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2882 }
cd28ab6a
SH		 2883}
2884
40b01727 2885/* This should never happen it is a bug. */
c119731d 2886static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2887{
2888 struct net_device *dev = hw->dev[port];
c119731d 2889 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2890
ada1db5c 2891 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2892 dev->name, (unsigned) q, (unsigned) idx,
2893 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2894
40b01727 2895 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2896}
cd28ab6a 2897
75e80683
SH		 2898static int sky2_rx_hung(struct net_device *dev)
2899{
2900 struct sky2_port *sky2 = netdev_priv(dev);
2901 struct sky2_hw *hw = sky2->hw;
2902 unsigned port = sky2->port;
2903 unsigned rxq = rxqaddr[port];
2904 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2905 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2906 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2907 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2908
2909 /* If idle and MAC or PCI is stuck */
2910 if (sky2->check.last == dev->last_rx &&
2911 ((mac_rp == sky2->check.mac_rp &&
2912 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2913 /* Check if the PCI RX hang */
2914 (fifo_rp == sky2->check.fifo_rp &&
2915 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2916 netdev_printk(KERN_DEBUG, dev,
2917 "hung mac %d:%d fifo %d (%d:%d)\n",
2918 mac_lev, mac_rp, fifo_lev,
2919 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2920 return 1;
2921 } else {
2922 sky2->check.last = dev->last_rx;
2923 sky2->check.mac_rp = mac_rp;
2924 sky2->check.mac_lev = mac_lev;
2925 sky2->check.fifo_rp = fifo_rp;
2926 sky2->check.fifo_lev = fifo_lev;
2927 return 0;
2928 }
2929}
2930
32c2c300 2931static void sky2_watchdog(unsigned long arg)
d27ed387 2932{
01bd7564 2933 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2934
75e80683 2935 /* Check for lost IRQ once a second */
32c2c300 2936 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2937 napi_schedule(&hw->napi);
75e80683
SH		 2938 } else {
2939 int i, active = 0;
2940
2941 for (i = 0; i < hw->ports; i++) {
bea3348e 2942 struct net_device *dev = hw->dev[i];
75e80683
SH		 2943 if (!netif_running(dev))
2944 continue;
2945 ++active;
2946
2947 /* For chips with Rx FIFO, check if stuck */
39dbd958 2948 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2949 sky2_rx_hung(dev)) {
ada1db5c 2950 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2951 schedule_work(&hw->restart_work);
2952 return;
2953 }
2954 }
2955
2956 if (active == 0)
2957 return;
32c2c300 2958 }
01bd7564 2959
75e80683 2960 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2961}
2962
40b01727
SH		 2963/* Hardware/software error handling */
2964static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2965{
40b01727
SH		 2966 if (net_ratelimit())
2967 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2968
1e5f1283
SH		 2969 if (status & Y2_IS_HW_ERR)
2970 sky2_hw_intr(hw);
d257924e 2971
1e5f1283
SH		 2972 if (status & Y2_IS_IRQ_MAC1)
2973 sky2_mac_intr(hw, 0);
cd28ab6a 2974
1e5f1283
SH		 2975 if (status & Y2_IS_IRQ_MAC2)
2976 sky2_mac_intr(hw, 1);
cd28ab6a 2977
1e5f1283 2978 if (status & Y2_IS_CHK_RX1)
c119731d 2979 sky2_le_error(hw, 0, Q_R1);
d257924e 2980
1e5f1283 2981 if (status & Y2_IS_CHK_RX2)
c119731d 2982 sky2_le_error(hw, 1, Q_R2);
d257924e 2983
1e5f1283 2984 if (status & Y2_IS_CHK_TXA1)
c119731d 2985 sky2_le_error(hw, 0, Q_XA1);
d257924e 2986
1e5f1283 2987 if (status & Y2_IS_CHK_TXA2)
c119731d 2988 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2989}
2990
bea3348e 2991static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2992{
bea3348e 2993 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2994 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2995 int work_done = 0;
26691830 2996 u16 idx;
40b01727
SH		 2997
2998 if (unlikely(status & Y2_IS_ERROR))
2999 sky2_err_intr(hw, status);
3000
3001 if (status & Y2_IS_IRQ_PHY1)
3002 sky2_phy_intr(hw, 0);
3003
3004 if (status & Y2_IS_IRQ_PHY2)
3005 sky2_phy_intr(hw, 1);
cd28ab6a 3006
0f5aac70
SH		 3007 if (status & Y2_IS_PHY_QLNK)
3008 sky2_qlink_intr(hw);
3009
26691830
SH		 3010 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3011 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 3012
3013 if (work_done >= work_limit)
26691830
SH		 3014 goto done;
3015 }
6f535763 3016
26691830
SH		 3017 napi_complete(napi);
3018 sky2_read32(hw, B0_Y2_SP_LISR);
3019done:
6f535763 3020
bea3348e 3021 return work_done;
e07b1aa8
SH		 3022}
3023
7d12e780 3024static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 3025{
3026 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 3027 u32 status;
3028
3029 /* Reading this mask interrupts as side effect */
3030 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3031 if (status == 0 || status == ~0)
3032 return IRQ_NONE;
793b883e 3033
e07b1aa8 3034 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 3035
3036 napi_schedule(&hw->napi);
793b883e 3037
cd28ab6a
SH		 3038 return IRQ_HANDLED;
3039}
3040
3041#ifdef CONFIG_NET_POLL_CONTROLLER
3042static void sky2_netpoll(struct net_device *dev)
3043{
3044 struct sky2_port *sky2 = netdev_priv(dev);
3045
bea3348e 3046 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 3047}
3048#endif
3049
3050/* Chip internal frequency for clock calculations */
05745c4a 3051static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 3052{
793b883e 3053 switch (hw->chip_id) {
cd28ab6a 3054 case CHIP_ID_YUKON_EC:
5a5b1ea0 3055 case CHIP_ID_YUKON_EC_U:
93745494 3056 case CHIP_ID_YUKON_EX:
ed4d4161 3057 case CHIP_ID_YUKON_SUPR:
0ce8b98d 3058 case CHIP_ID_YUKON_UL_2:
0f5aac70 3059 case CHIP_ID_YUKON_OPT:
4fb99cd6 3060 case CHIP_ID_YUKON_PRM:
3061 case CHIP_ID_YUKON_OP_2:
05745c4a
SH		 3062 return 125;
3063
cd28ab6a 3064 case CHIP_ID_YUKON_FE:
05745c4a
SH		 3065 return 100;
3066
3067 case CHIP_ID_YUKON_FE_P:
3068 return 50;
3069
3070 case CHIP_ID_YUKON_XL:
3071 return 156;
3072
3073 default:
3074 BUG();
cd28ab6a
SH		 3075 }
3076}
3077
fb17358f 3078static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 3079{
fb17358f 3080 return sky2_mhz(hw) * us;
cd28ab6a
SH		 3081}
3082
fb17358f 3083static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 3084{
fb17358f 3085 return clk / sky2_mhz(hw);
cd28ab6a
SH		 3086}
3087
fb17358f 3088
e3173832 3089static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 3090{
b89165f2 3091 u8 t8;
cd28ab6a 3092
167f53d0 3093 /* Enable all clocks and check for bad PCI access */
b32f40c4 3094 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 3095
cd28ab6a 3096 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 3097
cd28ab6a 3098 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 3099 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3100
060b946c 3101 switch (hw->chip_id) {
ea76e635 3102 case CHIP_ID_YUKON_XL:
39dbd958 3103 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
bf73130d
SH		 3104 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3105 hw->flags |= SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3106 break;
3107
3108 case CHIP_ID_YUKON_EC_U:
3109 hw->flags = SKY2_HW_GIGABIT
3110 | SKY2_HW_NEWER_PHY
3111 | SKY2_HW_ADV_POWER_CTL;
3112 break;
3113
3114 case CHIP_ID_YUKON_EX:
3115 hw->flags = SKY2_HW_GIGABIT
3116 | SKY2_HW_NEWER_PHY
3117 | SKY2_HW_NEW_LE
aa5ca96c 3118 | SKY2_HW_ADV_POWER_CTL
3119 | SKY2_HW_RSS_CHKSUM;
ea76e635
SH		 3120
3121 /* New transmit checksum */
3122 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3123 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3124 break;
3125
3126 case CHIP_ID_YUKON_EC:
3127 /* This rev is really old, and requires untested workarounds */
3128 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3129 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3130 return -EOPNOTSUPP;
3131 }
bf73130d 3132 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3133 break;
3134
3135 case CHIP_ID_YUKON_FE:
bf73130d 3136 hw->flags = SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3137 break;
3138
05745c4a
SH		 3139 case CHIP_ID_YUKON_FE_P:
3140 hw->flags = SKY2_HW_NEWER_PHY
3141 | SKY2_HW_NEW_LE
3142 | SKY2_HW_AUTO_TX_SUM
3143 | SKY2_HW_ADV_POWER_CTL;
86aa7785
SH		 3144
3145 /* The workaround for status conflicts VLAN tag detection. */
3146 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
aa5ca96c 3147 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
05745c4a 3148 break;
ed4d4161
SH		 3149
3150 case CHIP_ID_YUKON_SUPR:
3151 hw->flags = SKY2_HW_GIGABIT
3152 | SKY2_HW_NEWER_PHY
3153 | SKY2_HW_NEW_LE
3154 | SKY2_HW_AUTO_TX_SUM
3155 | SKY2_HW_ADV_POWER_CTL;
aa5ca96c 3156
3157 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3158 hw->flags |= SKY2_HW_RSS_CHKSUM;
ed4d4161
SH		 3159 break;
3160
0ce8b98d 3161 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3162 hw->flags = SKY2_HW_GIGABIT
3163 | SKY2_HW_ADV_POWER_CTL;
3164 break;
3165
0f5aac70 3166 case CHIP_ID_YUKON_OPT:
4fb99cd6 3167 case CHIP_ID_YUKON_PRM:
3168 case CHIP_ID_YUKON_OP_2:
0ce8b98d 3169 hw->flags = SKY2_HW_GIGABIT
b338682d 3170 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3171 | SKY2_HW_ADV_POWER_CTL;
3172 break;
3173
ea76e635 3174 default:
b02a9258
SH		 3175 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3176 hw->chip_id);
cd28ab6a
SH		 3177 return -EOPNOTSUPP;
3178 }
3179
ea76e635
SH		 3180 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3181 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3182 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3183
e3173832
SH		 3184 hw->ports = 1;
3185 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3186 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3187 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3188 ++hw->ports;
3189 }
3190
74a61ebf
MM		 3191 if (sky2_read8(hw, B2_E_0))
3192 hw->flags |= SKY2_HW_RAM_BUFFER;
3193
e3173832
SH		 3194 return 0;
3195}
3196
3197static void sky2_reset(struct sky2_hw *hw)
3198{
555382cb 3199 struct pci_dev *pdev = hw->pdev;
e3173832 3200 u16 status;
1a10ccae 3201 int i;
555382cb 3202 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3203
cd28ab6a 3204 /* disable ASF */
acd12dde 3205 if (hw->chip_id == CHIP_ID_YUKON_EX
3206 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3207 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3208 status = sky2_read16(hw, HCU_CCSR);
3209 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3210 HCU_CCSR_UC_STATE_MSK);
acd12dde 3211 /*
3212 * CPU clock divider shouldn't be used because
3213 * - ASF firmware may malfunction
3214 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3215 */
3216 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3217 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3218 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3219 } else
3220 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3221 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3222
3223 /* do a SW reset */
3224 sky2_write8(hw, B0_CTST, CS_RST_SET);
3225 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3226
ac93a394
SH		 3227 /* allow writes to PCI config */
3228 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3229
cd28ab6a 3230 /* clear PCI errors, if any */
b32f40c4 3231 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3232 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3233 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3234
3235 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3236
1a10ccae 3237 if (pci_is_pcie(pdev)) {
7782c8c4
SH		 3238 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3239 0xfffffffful);
555382cb
SH		 3240
3241 /* If error bit is stuck on ignore it */
3242 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3243 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3244 else
555382cb
SH		 3245 hwe_mask |= Y2_IS_PCI_EXP;
3246 }
cd28ab6a 3247
ae306cca 3248 sky2_power_on(hw);
a40ccc68 3249 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3250
3251 for (i = 0; i < hw->ports; i++) {
3252 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3253 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3254
ed4d4161
SH		 3255 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3256 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3257 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3258 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3259 | GMC_BYP_RETR_ON);
877c8570
SH		 3260
3261 }
3262
3263 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3264 /* enable MACSec clock gating */
3265 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3266 }
3267
4fb99cd6 3268 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3269 hw->chip_id == CHIP_ID_YUKON_PRM ||
3270 hw->chip_id == CHIP_ID_YUKON_OP_2) {
0f5aac70
SH		 3271 u16 reg;
3272 u32 msk;
3273
4fb99cd6 3274 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
0f5aac70
SH		 3275 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3276 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3277
3278 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3279 reg = 10;
4fb99cd6 3280
3281 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3282 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
0f5aac70
SH		 3283 } else {
3284 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3285 reg = 3;
3286 }
3287
3288 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
4fb99cd6 3289 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
0f5aac70
SH		 3290
3291 /* reset PHY Link Detect */
a40ccc68 3292 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3293 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3294
0f5aac70
SH		 3295 /* enable PHY Quick Link */
3296 msk = sky2_read32(hw, B0_IMSK);
3297 msk |= Y2_IS_PHY_QLNK;
3298 sky2_write32(hw, B0_IMSK, msk);
3299
3300 /* check if PSMv2 was running before */
3301 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
1a10ccae 3302 if (reg & PCI_EXP_LNKCTL_ASPMC)
0f5aac70 3303 /* restore the PCIe Link Control register */
1a10ccae
JM		 3304 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3305 reg);
3306
a40ccc68 3307 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3308
3309 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3310 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3311 }
3312
793b883e
SH		 3313 /* Clear I2C IRQ noise */
3314 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3315
3316 /* turn off hardware timer (unused) */
3317 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3318 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3319
69634ee7
SH		 3320 /* Turn off descriptor polling */
3321 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3322
3323 /* Turn off receive timestamp */
3324 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3325 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3326
3327 /* enable the Tx Arbiters */
3328 for (i = 0; i < hw->ports; i++)
3329 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3330
3331 /* Initialize ram interface */
3332 for (i = 0; i < hw->ports; i++) {
793b883e 3333 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3334
3335 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3336 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3337 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3338 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3339 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3340 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3341 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3342 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3343 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3344 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3345 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3346 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3347 }
3348
555382cb 3349 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3350
cd28ab6a 3351 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3352 sky2_gmac_reset(hw, i);
cd28ab6a 3353
efe91932 3354 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
cd28ab6a
SH		 3355 hw->st_idx = 0;
3356
3357 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3358 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3359
3360 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3361 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3362
3363 /* Set the list last index */
efe91932 3364 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
cd28ab6a 3365
290d4de5
SH		 3366 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3367 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3368
290d4de5
SH		 3369 /* set Status-FIFO ISR watermark */
3370 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3371 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3372 else
3373 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3374
290d4de5 3375 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3376 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3377 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3378
793b883e 3379 /* enable status unit */
cd28ab6a
SH		 3380 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3381
3382 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3383 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3384 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3385}
3386
af18d8b8
SH		 3387/* Take device down (offline).
3388 * Equivalent to doing dev_stop() but this does not
25985edc 3389 * inform upper layers of the transition.
af18d8b8
SH		 3390 */
3391static void sky2_detach(struct net_device *dev)
3392{
3393 if (netif_running(dev)) {
c36531b9 3394 netif_tx_lock(dev);
af18d8b8 3395 netif_device_detach(dev); /* stop txq */
c36531b9 3396 netif_tx_unlock(dev);
af18d8b8
SH		 3397 sky2_down(dev);
3398 }
3399}
3400
3401/* Bring device back after doing sky2_detach */
3402static int sky2_reattach(struct net_device *dev)
3403{
3404 int err = 0;
3405
3406 if (netif_running(dev)) {
3407 err = sky2_up(dev);
3408 if (err) {
ada1db5c 3409 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3410 dev_close(dev);
3411 } else {
3412 netif_device_attach(dev);
3413 sky2_set_multicast(dev);
3414 }
3415 }
3416
3417 return err;
3418}
3419
d72ff8fa 3420static void sky2_all_down(struct sky2_hw *hw)
81906791 3421{
af18d8b8 3422 int i;
81906791 3423
d72ff8fa 3424 sky2_read32(hw, B0_IMSK);
8cfcbe99 3425 sky2_write32(hw, B0_IMSK, 0);
93135a3b
MM		 3426 synchronize_irq(hw->pdev->irq);
3427 napi_disable(&hw->napi);
8a0c9228
MM		 3428
3429 for (i = 0; i < hw->ports; i++) {
3430 struct net_device *dev = hw->dev[i];
3431 struct sky2_port *sky2 = netdev_priv(dev);
3432
3433 if (!netif_running(dev))
3434 continue;
3435
3436 netif_carrier_off(dev);
3437 netif_tx_disable(dev);
3438 sky2_hw_down(sky2);
3439 }
d72ff8fa 3440}
8a0c9228 3441
d72ff8fa
MM		 3442static void sky2_all_up(struct sky2_hw *hw)
3443{
3444 u32 imask = Y2_IS_BASE;
3445 int i;
81906791 3446
8a0c9228
MM		 3447 for (i = 0; i < hw->ports; i++) {
3448 struct net_device *dev = hw->dev[i];
3449 struct sky2_port *sky2 = netdev_priv(dev);
3450
3451 if (!netif_running(dev))
3452 continue;
3453
3454 sky2_hw_up(sky2);
37652522 3455 sky2_set_multicast(dev);
d72ff8fa 3456 imask |= portirq_msk[i];
8a0c9228
MM		 3457 netif_wake_queue(dev);
3458 }
3459
3460 sky2_write32(hw, B0_IMSK, imask);
3461 sky2_read32(hw, B0_IMSK);
3462
3463 sky2_read32(hw, B0_Y2_SP_LISR);
3464 napi_enable(&hw->napi);
d72ff8fa
MM		 3465}
3466
3467static void sky2_restart(struct work_struct *work)
3468{
3469 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3470
3471 rtnl_lock();
3472
3473 sky2_all_down(hw);
3474 sky2_reset(hw);
3475 sky2_all_up(hw);
81906791 3476
81906791
SH		 3477 rtnl_unlock();
3478}
3479
e3173832
SH		 3480static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3481{
3482 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3483}
3484
3485static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3486{
3487 const struct sky2_port *sky2 = netdev_priv(dev);
3488
3489 wol->supported = sky2_wol_supported(sky2->hw);
3490 wol->wolopts = sky2->wol;
3491}
3492
3493static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3494{
3495 struct sky2_port *sky2 = netdev_priv(dev);
3496 struct sky2_hw *hw = sky2->hw;
0f333d10
RW		 3497 bool enable_wakeup = false;
3498 int i;
cd28ab6a 3499
8e95a202
JP		 3500 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3501 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3502 return -EOPNOTSUPP;
3503
3504 sky2->wol = wol->wolopts;
0f333d10
RW		 3505
3506 for (i = 0; i < hw->ports; i++) {
3507 struct net_device *dev = hw->dev[i];
3508 struct sky2_port *sky2 = netdev_priv(dev);
3509
3510 if (sky2->wol)
3511 enable_wakeup = true;
3512 }
3513 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3514
cd28ab6a
SH		 3515 return 0;
3516}
3517
28bd181a 3518static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3519{
b89165f2
SH		 3520 if (sky2_is_copper(hw)) {
3521 u32 modes = SUPPORTED_10baseT_Half
3522 | SUPPORTED_10baseT_Full
3523 | SUPPORTED_100baseT_Half
2aca31e7 3524 | SUPPORTED_100baseT_Full;
cd28ab6a 3525
ea76e635 3526 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3527 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3528 | SUPPORTED_1000baseT_Full;
3529 return modes;
cd28ab6a 3530 } else
2aca31e7
SH		 3531 return SUPPORTED_1000baseT_Half
3532 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 3533}
3534
793b883e 3535static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3536{
3537 struct sky2_port *sky2 = netdev_priv(dev);
3538 struct sky2_hw *hw = sky2->hw;
3539
3540 ecmd->transceiver = XCVR_INTERNAL;
3541 ecmd->supported = sky2_supported_modes(hw);
3542 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3543 if (sky2_is_copper(hw)) {
cd28ab6a 3544 ecmd->port = PORT_TP;
70739497 3545 ethtool_cmd_speed_set(ecmd, sky2->speed);
2aca31e7 3546 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
b89165f2 3547 } else {
70739497 3548 ethtool_cmd_speed_set(ecmd, SPEED_1000);
cd28ab6a 3549 ecmd->port = PORT_FIBRE;
2aca31e7 3550 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
b89165f2 3551 }
cd28ab6a
SH		 3552
3553 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3554 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3555 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3556 ecmd->duplex = sky2->duplex;
3557 return 0;
3558}
3559
3560static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3561{
3562 struct sky2_port *sky2 = netdev_priv(dev);
3563 const struct sky2_hw *hw = sky2->hw;
3564 u32 supported = sky2_supported_modes(hw);
3565
3566 if (ecmd->autoneg == AUTONEG_ENABLE) {
2aca31e7
SH		 3567 if (ecmd->advertising & ~supported)
3568 return -EINVAL;
3569
3570 if (sky2_is_copper(hw))
3571 sky2->advertising = ecmd->advertising |
3572 ADVERTISED_TP |
3573 ADVERTISED_Autoneg;
3574 else
3575 sky2->advertising = ecmd->advertising |
3576 ADVERTISED_FIBRE |
3577 ADVERTISED_Autoneg;
3578
0ea065e5 3579 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3580 sky2->duplex = -1;
3581 sky2->speed = -1;
3582 } else {
3583 u32 setting;
25db0338 3584 u32 speed = ethtool_cmd_speed(ecmd);
cd28ab6a 3585
25db0338 3586 switch (speed) {
cd28ab6a
SH		 3587 case SPEED_1000:
3588 if (ecmd->duplex == DUPLEX_FULL)
3589 setting = SUPPORTED_1000baseT_Full;
3590 else if (ecmd->duplex == DUPLEX_HALF)
3591 setting = SUPPORTED_1000baseT_Half;
3592 else
3593 return -EINVAL;
3594 break;
3595 case SPEED_100:
3596 if (ecmd->duplex == DUPLEX_FULL)
3597 setting = SUPPORTED_100baseT_Full;
3598 else if (ecmd->duplex == DUPLEX_HALF)
3599 setting = SUPPORTED_100baseT_Half;
3600 else
3601 return -EINVAL;
3602 break;
3603
3604 case SPEED_10:
3605 if (ecmd->duplex == DUPLEX_FULL)
3606 setting = SUPPORTED_10baseT_Full;
3607 else if (ecmd->duplex == DUPLEX_HALF)
3608 setting = SUPPORTED_10baseT_Half;
3609 else
3610 return -EINVAL;
3611 break;
3612 default:
3613 return -EINVAL;
3614 }
3615
3616 if ((setting & supported) == 0)
3617 return -EINVAL;
3618
25db0338 3619 sky2->speed = speed;
cd28ab6a 3620 sky2->duplex = ecmd->duplex;
0ea065e5 3621 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3622 }
3623
d1b139c0 3624 if (netif_running(dev)) {
1b537565 3625 sky2_phy_reinit(sky2);
d1b139c0
SH		 3626 sky2_set_multicast(dev);
3627 }
cd28ab6a
SH		 3628
3629 return 0;
3630}
3631
3632static void sky2_get_drvinfo(struct net_device *dev,
3633 struct ethtool_drvinfo *info)
3634{
3635 struct sky2_port *sky2 = netdev_priv(dev);
3636
3637 strcpy(info->driver, DRV_NAME);
3638 strcpy(info->version, DRV_VERSION);
3639 strcpy(info->fw_version, "N/A");
3640 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3641}
3642
3643static const struct sky2_stat {
793b883e
SH		 3644 char name[ETH_GSTRING_LEN];
3645 u16 offset;
cd28ab6a
SH		 3646} sky2_stats[] = {
3647 { "tx_bytes", GM_TXO_OK_HI },
3648 { "rx_bytes", GM_RXO_OK_HI },
3649 { "tx_broadcast", GM_TXF_BC_OK },
3650 { "rx_broadcast", GM_RXF_BC_OK },
3651 { "tx_multicast", GM_TXF_MC_OK },
3652 { "rx_multicast", GM_RXF_MC_OK },
3653 { "tx_unicast", GM_TXF_UC_OK },
3654 { "rx_unicast", GM_RXF_UC_OK },
3655 { "tx_mac_pause", GM_TXF_MPAUSE },
3656 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3657 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3658 { "late_collision",GM_TXF_LAT_COL },
3659 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3660 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3661 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3662
d2604540 3663 { "rx_short", GM_RXF_SHT },
cd28ab6a 3664 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3665 { "rx_64_byte_packets", GM_RXF_64B },
3666 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3667 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3668 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3669 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3670 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3671 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3672 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3673 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3674 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3675 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3676
3677 { "tx_64_byte_packets", GM_TXF_64B },
3678 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3679 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3680 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3681 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3682 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3683 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3684 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3685};
3686
cd28ab6a
SH		 3687static u32 sky2_get_msglevel(struct net_device *netdev)
3688{
3689 struct sky2_port *sky2 = netdev_priv(netdev);
3690 return sky2->msg_enable;
3691}
3692
9a7ae0a9
SH		 3693static int sky2_nway_reset(struct net_device *dev)
3694{
3695 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3696
0ea065e5 3697 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3698 return -EINVAL;
3699
1b537565 3700 sky2_phy_reinit(sky2);
d1b139c0 3701 sky2_set_multicast(dev);
9a7ae0a9
SH		 3702
3703 return 0;
3704}
3705
793b883e 3706static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3707{
3708 struct sky2_hw *hw = sky2->hw;
3709 unsigned port = sky2->port;
3710 int i;
3711
0885a30b 3712 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3713 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
cd28ab6a 3714
793b883e 3715 for (i = 2; i < count; i++)
0885a30b 3716 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
cd28ab6a
SH		 3717}
3718
cd28ab6a
SH		 3719static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3720{
3721 struct sky2_port *sky2 = netdev_priv(netdev);
3722 sky2->msg_enable = value;
3723}
3724
b9f2c044 3725static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3726{
b9f2c044
JG		 3727 switch (sset) {
3728 case ETH_SS_STATS:
3729 return ARRAY_SIZE(sky2_stats);
3730 default:
3731 return -EOPNOTSUPP;
3732 }
cd28ab6a
SH		 3733}
3734
3735static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3736 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3737{
3738 struct sky2_port *sky2 = netdev_priv(dev);
3739
793b883e 3740 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3741}
3742
793b883e 3743static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3744{
3745 int i;
3746
3747 switch (stringset) {
3748 case ETH_SS_STATS:
3749 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3750 memcpy(data + i * ETH_GSTRING_LEN,
3751 sky2_stats[i].name, ETH_GSTRING_LEN);
3752 break;
3753 }
3754}
3755
cd28ab6a
SH		 3756static int sky2_set_mac_address(struct net_device *dev, void *p)
3757{
3758 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3759 struct sky2_hw *hw = sky2->hw;
3760 unsigned port = sky2->port;
3761 const struct sockaddr *addr = p;
cd28ab6a
SH		 3762
3763 if (!is_valid_ether_addr(addr->sa_data))
3764 return -EADDRNOTAVAIL;
3765
cd28ab6a 3766 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3767 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3768 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3769 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3770 dev->dev_addr, ETH_ALEN);
1b537565 3771
a8ab1ec0
SH		 3772 /* virtual address for data */
3773 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3774
3775 /* physical address: used for pause frames */
3776 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3777
3778 return 0;
cd28ab6a
SH		 3779}
3780
060b946c 3781static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
a052b52f
SH		 3782{
3783 u32 bit;
3784
3785 bit = ether_crc(ETH_ALEN, addr) & 63;
3786 filter[bit >> 3] |= 1 << (bit & 7);
3787}
3788
cd28ab6a
SH		 3789static void sky2_set_multicast(struct net_device *dev)
3790{
3791 struct sky2_port *sky2 = netdev_priv(dev);
3792 struct sky2_hw *hw = sky2->hw;
3793 unsigned port = sky2->port;
22bedad3 3794 struct netdev_hw_addr *ha;
cd28ab6a
SH		 3795 u16 reg;
3796 u8 filter[8];
a052b52f
SH		 3797 int rx_pause;
3798 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3799
a052b52f 3800 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3801 memset(filter, 0, sizeof(filter));
3802
3803 reg = gma_read16(hw, port, GM_RX_CTRL);
3804 reg |= GM_RXCR_UCF_ENA;
3805
d571b694 3806 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3807 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3808 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3809 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3810 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3811 reg &= ~GM_RXCR_MCF_ENA;
3812 else {
cd28ab6a
SH		 3813 reg |= GM_RXCR_MCF_ENA;
3814
a052b52f
SH		 3815 if (rx_pause)
3816 sky2_add_filter(filter, pause_mc_addr);
3817
22bedad3
JP		 3818 netdev_for_each_mc_addr(ha, dev)
3819 sky2_add_filter(filter, ha->addr);
cd28ab6a
SH		 3820 }
3821
cd28ab6a 3822 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3823 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3824 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3825 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3826 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3827 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3828 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3829 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3830
3831 gma_write16(hw, port, GM_RX_CTRL, reg);
3832}
3833
0885a30b 3834static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3835 struct rtnl_link_stats64 *stats)
3836{
3837 struct sky2_port *sky2 = netdev_priv(dev);
3838 struct sky2_hw *hw = sky2->hw;
3839 unsigned port = sky2->port;
3840 unsigned int start;
3841 u64 _bytes, _packets;
3842
3843 do {
3844 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3845 _bytes = sky2->rx_stats.bytes;
3846 _packets = sky2->rx_stats.packets;
3847 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3848
3849 stats->rx_packets = _packets;
3850 stats->rx_bytes = _bytes;
3851
3852 do {
3853 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3854 _bytes = sky2->tx_stats.bytes;
3855 _packets = sky2->tx_stats.packets;
3856 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3857
3858 stats->tx_packets = _packets;
3859 stats->tx_bytes = _bytes;
3860
3861 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3862 + get_stats32(hw, port, GM_RXF_BC_OK);
3863
3864 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3865
3866 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3867 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3868 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3869 + get_stats32(hw, port, GM_RXE_FRAG);
3870 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3871
3872 stats->rx_dropped = dev->stats.rx_dropped;
3873 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3874 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3875
3876 return stats;
3877}
3878
cd28ab6a
SH		 3879/* Can have one global because blinking is controlled by
3880 * ethtool and that is always under RTNL mutex
3881 */
a84d0a3d 3882static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3883{
a84d0a3d
SH		 3884 struct sky2_hw *hw = sky2->hw;
3885 unsigned port = sky2->port;
793b883e 3886
a84d0a3d
SH		 3887 spin_lock_bh(&sky2->phy_lock);
3888 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3889 hw->chip_id == CHIP_ID_YUKON_EX ||
3890 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3891 u16 pg;
793b883e
SH		 3892 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3893 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3894
a84d0a3d
SH		 3895 switch (mode) {
3896 case MO_LED_OFF:
3897 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3898 PHY_M_LEDC_LOS_CTRL(8) |
3899 PHY_M_LEDC_INIT_CTRL(8) |
3900 PHY_M_LEDC_STA1_CTRL(8) |
3901 PHY_M_LEDC_STA0_CTRL(8));
3902 break;
3903 case MO_LED_ON:
3904 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3905 PHY_M_LEDC_LOS_CTRL(9) |
3906 PHY_M_LEDC_INIT_CTRL(9) |
3907 PHY_M_LEDC_STA1_CTRL(9) |
3908 PHY_M_LEDC_STA0_CTRL(9));
3909 break;
3910 case MO_LED_BLINK:
3911 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3912 PHY_M_LEDC_LOS_CTRL(0xa) |
3913 PHY_M_LEDC_INIT_CTRL(0xa) |
3914 PHY_M_LEDC_STA1_CTRL(0xa) |
3915 PHY_M_LEDC_STA0_CTRL(0xa));
3916 break;
3917 case MO_LED_NORM:
3918 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3919 PHY_M_LEDC_LOS_CTRL(1) |
3920 PHY_M_LEDC_INIT_CTRL(8) |
3921 PHY_M_LEDC_STA1_CTRL(7) |
3922 PHY_M_LEDC_STA0_CTRL(7));
3923 }
793b883e 3924
a84d0a3d
SH		 3925 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3926 } else
7d2e3cb7 3927 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3928 PHY_M_LED_MO_DUP(mode) |
3929 PHY_M_LED_MO_10(mode) |
3930 PHY_M_LED_MO_100(mode) |
3931 PHY_M_LED_MO_1000(mode) |
3932 PHY_M_LED_MO_RX(mode) |
3933 PHY_M_LED_MO_TX(mode));
3934
3935 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3936}
3937
3938/* blink LED's for finding board */
74e532ff 3939static int sky2_set_phys_id(struct net_device *dev,
3940 enum ethtool_phys_id_state state)
cd28ab6a
SH		 3941{
3942 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3943
74e532ff 3944 switch (state) {
3945 case ETHTOOL_ID_ACTIVE:
fce55922 3946 return 1; /* cycle on/off once per second */
74e532ff 3947 case ETHTOOL_ID_INACTIVE:
3948 sky2_led(sky2, MO_LED_NORM);
3949 break;
3950 case ETHTOOL_ID_ON:
a84d0a3d 3951 sky2_led(sky2, MO_LED_ON);
74e532ff 3952 break;
3953 case ETHTOOL_ID_OFF:
a84d0a3d 3954 sky2_led(sky2, MO_LED_OFF);
74e532ff 3955 break;
793b883e 3956 }
cd28ab6a
SH		 3957
3958 return 0;
3959}
3960
3961static void sky2_get_pauseparam(struct net_device *dev,
3962 struct ethtool_pauseparam *ecmd)
3963{
3964 struct sky2_port *sky2 = netdev_priv(dev);
3965
16ad91e1
SH		 3966 switch (sky2->flow_mode) {
3967 case FC_NONE:
3968 ecmd->tx_pause = ecmd->rx_pause = 0;
3969 break;
3970 case FC_TX:
3971 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3972 break;
3973 case FC_RX:
3974 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3975 break;
3976 case FC_BOTH:
3977 ecmd->tx_pause = ecmd->rx_pause = 1;
3978 }
3979
0ea065e5
SH		 3980 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3981 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3982}
3983
3984static int sky2_set_pauseparam(struct net_device *dev,
3985 struct ethtool_pauseparam *ecmd)
3986{
3987 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3988
0ea065e5
SH		 3989 if (ecmd->autoneg == AUTONEG_ENABLE)
3990 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3991 else
3992 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3993
16ad91e1 3994 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3995
16ad91e1
SH		 3996 if (netif_running(dev))
3997 sky2_phy_reinit(sky2);
cd28ab6a 3998
2eaba1a2 3999 return 0;
cd28ab6a
SH		 4000}
4001
fb17358f
SH		 4002static int sky2_get_coalesce(struct net_device *dev,
4003 struct ethtool_coalesce *ecmd)
4004{
4005 struct sky2_port *sky2 = netdev_priv(dev);
4006 struct sky2_hw *hw = sky2->hw;
4007
4008 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4009 ecmd->tx_coalesce_usecs = 0;
4010 else {
4011 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4012 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4013 }
4014 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4015
4016 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4017 ecmd->rx_coalesce_usecs = 0;
4018 else {
4019 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4020 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4021 }
4022 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4023
4024 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4025 ecmd->rx_coalesce_usecs_irq = 0;
4026 else {
4027 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4028 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4029 }
4030
4031 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4032
4033 return 0;
4034}
4035
4036/* Note: this affect both ports */
4037static int sky2_set_coalesce(struct net_device *dev,
4038 struct ethtool_coalesce *ecmd)
4039{
4040 struct sky2_port *sky2 = netdev_priv(dev);
4041 struct sky2_hw *hw = sky2->hw;
77b3d6a2 4042 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 4043
77b3d6a2
SH		 4044 if (ecmd->tx_coalesce_usecs > tmax ||
4045 ecmd->rx_coalesce_usecs > tmax ||
4046 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 4047 return -EINVAL;
4048
ee5f68fe 4049 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 4050 return -EINVAL;
ff81fbbe 4051 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 4052 return -EINVAL;
060b946c 4053 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
fb17358f
SH		 4054 return -EINVAL;
4055
4056 if (ecmd->tx_coalesce_usecs == 0)
4057 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4058 else {
4059 sky2_write32(hw, STAT_TX_TIMER_INI,
4060 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4061 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4062 }
4063 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4064
4065 if (ecmd->rx_coalesce_usecs == 0)
4066 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4067 else {
4068 sky2_write32(hw, STAT_LEV_TIMER_INI,
4069 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4070 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4071 }
4072 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4073
4074 if (ecmd->rx_coalesce_usecs_irq == 0)
4075 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4076 else {
d28d4870 4077 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 4078 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4079 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4080 }
4081 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4082 return 0;
4083}
4084
793b883e
SH		 4085static void sky2_get_ringparam(struct net_device *dev,
4086 struct ethtool_ringparam *ering)
4087{
4088 struct sky2_port *sky2 = netdev_priv(dev);
4089
4090 ering->rx_max_pending = RX_MAX_PENDING;
ee5f68fe 4091 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 4092
4093 ering->rx_pending = sky2->rx_pending;
793b883e
SH		 4094 ering->tx_pending = sky2->tx_pending;
4095}
4096
4097static int sky2_set_ringparam(struct net_device *dev,
4098 struct ethtool_ringparam *ering)
4099{
4100 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 4101
4102 if (ering->rx_pending > RX_MAX_PENDING ||
4103 ering->rx_pending < 8 ||
ee5f68fe
SH		 4104 ering->tx_pending < TX_MIN_PENDING ||
4105 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 4106 return -EINVAL;
4107
af18d8b8 4108 sky2_detach(dev);
793b883e
SH		 4109
4110 sky2->rx_pending = ering->rx_pending;
4111 sky2->tx_pending = ering->tx_pending;
ee5f68fe 4112 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 4113
af18d8b8 4114 return sky2_reattach(dev);
793b883e
SH		 4115}
4116
793b883e
SH		 4117static int sky2_get_regs_len(struct net_device *dev)
4118{
6e4cbb34 4119 return 0x4000;
793b883e
SH		 4120}
4121
c32bbff8
MM		 4122static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4123{
4124 /* This complicated switch statement is to make sure and
4125 * only access regions that are unreserved.
4126 * Some blocks are only valid on dual port cards.
4127 */
4128 switch (b) {
4129 /* second port */
4130 case 5: /* Tx Arbiter 2 */
4131 case 9: /* RX2 */
4132 case 14 ... 15: /* TX2 */
4133 case 17: case 19: /* Ram Buffer 2 */
4134 case 22 ... 23: /* Tx Ram Buffer 2 */
4135 case 25: /* Rx MAC Fifo 1 */
4136 case 27: /* Tx MAC Fifo 2 */
4137 case 31: /* GPHY 2 */
4138 case 40 ... 47: /* Pattern Ram 2 */
4139 case 52: case 54: /* TCP Segmentation 2 */
4140 case 112 ... 116: /* GMAC 2 */
4141 return hw->ports > 1;
4142
4143 case 0: /* Control */
4144 case 2: /* Mac address */
4145 case 4: /* Tx Arbiter 1 */
4146 case 7: /* PCI express reg */
4147 case 8: /* RX1 */
4148 case 12 ... 13: /* TX1 */
4149 case 16: case 18:/* Rx Ram Buffer 1 */
4150 case 20 ... 21: /* Tx Ram Buffer 1 */
4151 case 24: /* Rx MAC Fifo 1 */
4152 case 26: /* Tx MAC Fifo 1 */
4153 case 28 ... 29: /* Descriptor and status unit */
4154 case 30: /* GPHY 1*/
4155 case 32 ... 39: /* Pattern Ram 1 */
4156 case 48: case 50: /* TCP Segmentation 1 */
4157 case 56 ... 60: /* PCI space */
4158 case 80 ... 84: /* GMAC 1 */
4159 return 1;
4160
4161 default:
4162 return 0;
4163 }
4164}
4165
793b883e
SH		 4166/*
4167 * Returns copy of control register region
3ead5db7 4168 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 4169 */
4170static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4171 void *p)
4172{
4173 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 4174 const void __iomem *io = sky2->hw->regs;
295b54c4 4175 unsigned int b;
793b883e
SH		 4176
4177 regs->version = 1;
793b883e 4178
295b54c4 4179 for (b = 0; b < 128; b++) {
c32bbff8
MM		 4180 /* skip poisonous diagnostic ram region in block 3 */
4181 if (b == 3)
295b54c4 4182 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 4183 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 4184 memcpy_fromio(p, io, 128);
c32bbff8 4185 else
295b54c4 4186 memset(p, 0, 128);
3ead5db7 4187
295b54c4
SH		 4188 p += 128;
4189 io += 128;
4190 }
793b883e 4191}
cd28ab6a 4192
f4331a6d
SH		 4193static int sky2_get_eeprom_len(struct net_device *dev)
4194{
4195 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4196 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4197 u16 reg2;
4198
b32f40c4 4199 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4200 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4201}
4202
1413235c 4203static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4204{
1413235c 4205 unsigned long start = jiffies;
f4331a6d 4206
1413235c
SH		 4207 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4208 /* Can take up to 10.6 ms for write */
4209 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4210 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4211 return -ETIMEDOUT;
4212 }
4213 mdelay(1);
4214 }
167f53d0 4215
1413235c
SH		 4216 return 0;
4217}
167f53d0 4218
1413235c
SH		 4219static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4220 u16 offset, size_t length)
4221{
4222 int rc = 0;
4223
4224 while (length > 0) {
4225 u32 val;
4226
4227 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4228 rc = sky2_vpd_wait(hw, cap, 0);
4229 if (rc)
4230 break;
4231
4232 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4233
4234 memcpy(data, &val, min(sizeof(val), length));
4235 offset += sizeof(u32);
4236 data += sizeof(u32);
4237 length -= sizeof(u32);
4238 }
4239
4240 return rc;
f4331a6d
SH		 4241}
4242
1413235c
SH		 4243static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4244 u16 offset, unsigned int length)
f4331a6d 4245{
1413235c
SH		 4246 unsigned int i;
4247 int rc = 0;
4248
4249 for (i = 0; i < length; i += sizeof(u32)) {
4250 u32 val = *(u32 *)(data + i);
4251
4252 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4253 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4254
4255 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4256 if (rc)
4257 break;
4258 }
4259 return rc;
f4331a6d
SH		 4260}
4261
4262static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4263 u8 *data)
4264{
4265 struct sky2_port *sky2 = netdev_priv(dev);
4266 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4267
4268 if (!cap)
4269 return -EINVAL;
4270
4271 eeprom->magic = SKY2_EEPROM_MAGIC;
4272
1413235c 4273 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4274}
4275
4276static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4277 u8 *data)
4278{
4279 struct sky2_port *sky2 = netdev_priv(dev);
4280 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4281
4282 if (!cap)
4283 return -EINVAL;
4284
4285 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4286 return -EINVAL;
4287
1413235c
SH		 4288 /* Partial writes not supported */
4289 if ((eeprom->offset & 3) || (eeprom->len & 3))
4290 return -EINVAL;
f4331a6d 4291
1413235c 4292 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4293}
4294
f5d64037 4295static u32 sky2_fix_features(struct net_device *dev, u32 features)
bf73130d 4296{
f5d64037
MM		 4297 const struct sky2_port *sky2 = netdev_priv(dev);
4298 const struct sky2_hw *hw = sky2->hw;
bf73130d 4299
f5d64037
MM		 4300 /* In order to do Jumbo packets on these chips, need to turn off the
4301 * transmit store/forward. Therefore checksum offload won't work.
4302 */
aa5ca96c 4303 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4304 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
f5d64037 4305 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
aa5ca96c 4306 }
4307
4308 /* Some hardware requires receive checksum for RSS to work. */
4309 if ( (features & NETIF_F_RXHASH) &&
4310 !(features & NETIF_F_RXCSUM) &&
4311 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4312 netdev_info(dev, "receive hashing forces receive checksum\n");
4313 features |= NETIF_F_RXCSUM;
4314 }
86aa7785 4315
f5d64037
MM		 4316 return features;
4317}
86aa7785 4318
f5d64037
MM		 4319static int sky2_set_features(struct net_device *dev, u32 features)
4320{
4321 struct sky2_port *sky2 = netdev_priv(dev);
4322 u32 changed = dev->features ^ features;
86aa7785 4323
f5d64037
MM		 4324 if (changed & NETIF_F_RXCSUM) {
4325 u32 on = features & NETIF_F_RXCSUM;
4326 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4327 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4328 }
bf73130d 4329
f5d64037
MM		 4330 if (changed & NETIF_F_RXHASH)
4331 rx_set_rss(dev, features);
86aa7785 4332
f5d64037
MM		 4333 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4334 sky2_vlan_mode(dev, features);
bf73130d
SH		 4335
4336 return 0;
4337}
f4331a6d 4338
7282d491 4339static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4340 .get_settings = sky2_get_settings,
4341 .set_settings = sky2_set_settings,
4342 .get_drvinfo = sky2_get_drvinfo,
4343 .get_wol = sky2_get_wol,
4344 .set_wol = sky2_set_wol,
4345 .get_msglevel = sky2_get_msglevel,
4346 .set_msglevel = sky2_set_msglevel,
4347 .nway_reset = sky2_nway_reset,
4348 .get_regs_len = sky2_get_regs_len,
4349 .get_regs = sky2_get_regs,
4350 .get_link = ethtool_op_get_link,
4351 .get_eeprom_len = sky2_get_eeprom_len,
4352 .get_eeprom = sky2_get_eeprom,
4353 .set_eeprom = sky2_set_eeprom,
f4331a6d
SH		 4354 .get_strings = sky2_get_strings,
4355 .get_coalesce = sky2_get_coalesce,
4356 .set_coalesce = sky2_set_coalesce,
4357 .get_ringparam = sky2_get_ringparam,
4358 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4359 .get_pauseparam = sky2_get_pauseparam,
4360 .set_pauseparam = sky2_set_pauseparam,
74e532ff 4361 .set_phys_id = sky2_set_phys_id,
b9f2c044 4362 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4363 .get_ethtool_stats = sky2_get_ethtool_stats,
4364};
4365
3cf26753
SH		 4366#ifdef CONFIG_SKY2_DEBUG
4367
4368static struct dentry *sky2_debug;
4369
e4c2abe2
SH		 4370
4371/*
4372 * Read and parse the first part of Vital Product Data
4373 */
4374#define VPD_SIZE 128
4375#define VPD_MAGIC 0x82
4376
4377static const struct vpd_tag {
4378 char tag[2];
4379 char *label;
4380} vpd_tags[] = {
4381 { "PN", "Part Number" },
4382 { "EC", "Engineering Level" },
4383 { "MN", "Manufacturer" },
4384 { "SN", "Serial Number" },
4385 { "YA", "Asset Tag" },
4386 { "VL", "First Error Log Message" },
4387 { "VF", "Second Error Log Message" },
4388 { "VB", "Boot Agent ROM Configuration" },
4389 { "VE", "EFI UNDI Configuration" },
4390};
4391
4392static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4393{
4394 size_t vpd_size;
4395 loff_t offs;
4396 u8 len;
4397 unsigned char *buf;
4398 u16 reg2;
4399
4400 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4401 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4402
4403 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4404 buf = kmalloc(vpd_size, GFP_KERNEL);
4405 if (!buf) {
4406 seq_puts(seq, "no memory!\n");
4407 return;
4408 }
4409
4410 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4411 seq_puts(seq, "VPD read failed\n");
4412 goto out;
4413 }
4414
4415 if (buf[0] != VPD_MAGIC) {
4416 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4417 goto out;
4418 }
4419 len = buf[1];
4420 if (len == 0 || len > vpd_size - 4) {
4421 seq_printf(seq, "Invalid id length: %d\n", len);
4422 goto out;
4423 }
4424
4425 seq_printf(seq, "%.*s\n", len, buf + 3);
4426 offs = len + 3;
4427
4428 while (offs < vpd_size - 4) {
4429 int i;
4430
4431 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4432 break;
4433 len = buf[offs + 2];
4434 if (offs + len + 3 >= vpd_size)
4435 break;
4436
4437 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4438 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4439 seq_printf(seq, " %s: %.*s\n",
4440 vpd_tags[i].label, len, buf + offs + 3);
4441 break;
4442 }
4443 }
4444 offs += len + 3;
4445 }
4446out:
4447 kfree(buf);
4448}
4449
3cf26753
SH		 4450static int sky2_debug_show(struct seq_file *seq, void *v)
4451{
4452 struct net_device *dev = seq->private;
4453 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4454 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4455 unsigned port = sky2->port;
4456 unsigned idx, last;
4457 int sop;
4458
e4c2abe2 4459 sky2_show_vpd(seq, hw);
3cf26753 4460
e4c2abe2 4461 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4462 sky2_read32(hw, B0_ISRC),
4463 sky2_read32(hw, B0_IMSK),
4464 sky2_read32(hw, B0_Y2_SP_ICR));
4465
e4c2abe2
SH		 4466 if (!netif_running(dev)) {
4467 seq_printf(seq, "network not running\n");
4468 return 0;
4469 }
4470
bea3348e 4471 napi_disable(&hw->napi);
3cf26753
SH		 4472 last = sky2_read16(hw, STAT_PUT_IDX);
4473
efe91932 4474 seq_printf(seq, "Status ring %u\n", hw->st_size);
3cf26753
SH		 4475 if (hw->st_idx == last)
4476 seq_puts(seq, "Status ring (empty)\n");
4477 else {
4478 seq_puts(seq, "Status ring\n");
efe91932 4479 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4480 idx = RING_NEXT(idx, hw->st_size)) {
3cf26753
SH		 4481 const struct sky2_status_le *le = hw->st_le + idx;
4482 seq_printf(seq, "[%d] %#x %d %#x\n",
4483 idx, le->opcode, le->length, le->status);
4484 }
4485 seq_puts(seq, "\n");
4486 }
4487
4488 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4489 sky2->tx_cons, sky2->tx_prod,
4490 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4491 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4492
4493 /* Dump contents of tx ring */
4494 sop = 1;
ee5f68fe
SH		 4495 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4496 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4497 const struct sky2_tx_le *le = sky2->tx_le + idx;
4498 u32 a = le32_to_cpu(le->addr);
4499
4500 if (sop)
4501 seq_printf(seq, "%u:", idx);
4502 sop = 0;
4503
060b946c 4504 switch (le->opcode & ~HW_OWNER) {
3cf26753
SH		 4505 case OP_ADDR64:
4506 seq_printf(seq, " %#x:", a);
4507 break;
4508 case OP_LRGLEN:
4509 seq_printf(seq, " mtu=%d", a);
4510 break;
4511 case OP_VLAN:
4512 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4513 break;
4514 case OP_TCPLISW:
4515 seq_printf(seq, " csum=%#x", a);
4516 break;
4517 case OP_LARGESEND:
4518 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4519 break;
4520 case OP_PACKET:
4521 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4522 break;
4523 case OP_BUFFER:
4524 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4525 break;
4526 default:
4527 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4528 a, le16_to_cpu(le->length));
4529 }
4530
4531 if (le->ctrl & EOP) {
4532 seq_putc(seq, '\n');
4533 sop = 1;
4534 }
4535 }
4536
4537 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4538 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4539 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4540 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4541
d1d08d12 4542 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4543 napi_enable(&hw->napi);
3cf26753
SH		 4544 return 0;
4545}
4546
4547static int sky2_debug_open(struct inode *inode, struct file *file)
4548{
4549 return single_open(file, sky2_debug_show, inode->i_private);
4550}
4551
4552static const struct file_operations sky2_debug_fops = {
4553 .owner = THIS_MODULE,
4554 .open = sky2_debug_open,
4555 .read = seq_read,
4556 .llseek = seq_lseek,
4557 .release = single_release,
4558};
4559
4560/*
4561 * Use network device events to create/remove/rename
4562 * debugfs file entries
4563 */
4564static int sky2_device_event(struct notifier_block *unused,
4565 unsigned long event, void *ptr)
4566{
4567 struct net_device *dev = ptr;
5b296bc9 4568 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4569
1436b301 4570 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4571 return NOTIFY_DONE;
3cf26753 4572
060b946c 4573 switch (event) {
5b296bc9
SH		 4574 case NETDEV_CHANGENAME:
4575 if (sky2->debugfs) {
4576 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4577 sky2_debug, dev->name);
4578 }
4579 break;
3cf26753 4580
5b296bc9
SH		 4581 case NETDEV_GOING_DOWN:
4582 if (sky2->debugfs) {
ada1db5c 4583 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4584 debugfs_remove(sky2->debugfs);
4585 sky2->debugfs = NULL;
3cf26753 4586 }
5b296bc9
SH		 4587 break;
4588
4589 case NETDEV_UP:
4590 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4591 sky2_debug, dev,
4592 &sky2_debug_fops);
4593 if (IS_ERR(sky2->debugfs))
4594 sky2->debugfs = NULL;
3cf26753
SH		 4595 }
4596
4597 return NOTIFY_DONE;
4598}
4599
4600static struct notifier_block sky2_notifier = {
4601 .notifier_call = sky2_device_event,
4602};
4603
4604
4605static __init void sky2_debug_init(void)
4606{
4607 struct dentry *ent;
4608
4609 ent = debugfs_create_dir("sky2", NULL);
4610 if (!ent || IS_ERR(ent))
4611 return;
4612
4613 sky2_debug = ent;
4614 register_netdevice_notifier(&sky2_notifier);
4615}
4616
4617static __exit void sky2_debug_cleanup(void)
4618{
4619 if (sky2_debug) {
4620 unregister_netdevice_notifier(&sky2_notifier);
4621 debugfs_remove(sky2_debug);
4622 sky2_debug = NULL;
4623 }
4624}
4625
4626#else
4627#define sky2_debug_init()
4628#define sky2_debug_cleanup()
4629#endif
4630
1436b301
SH		 4631/* Two copies of network device operations to handle special case of
4632 not allowing netpoll on second port */
4633static const struct net_device_ops sky2_netdev_ops[2] = {
4634 {
4635 .ndo_open = sky2_up,
4636 .ndo_stop = sky2_down,
00829823 4637 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4638 .ndo_do_ioctl = sky2_ioctl,
4639 .ndo_validate_addr = eth_validate_addr,
4640 .ndo_set_mac_address = sky2_set_mac_address,
afc4b13d 4641 .ndo_set_rx_mode = sky2_set_multicast,
1436b301 4642 .ndo_change_mtu = sky2_change_mtu,
f5d64037
MM		 4643 .ndo_fix_features = sky2_fix_features,
4644 .ndo_set_features = sky2_set_features,
1436b301 4645 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4646 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4647#ifdef CONFIG_NET_POLL_CONTROLLER
4648 .ndo_poll_controller = sky2_netpoll,
4649#endif
4650 },
4651 {
4652 .ndo_open = sky2_up,
4653 .ndo_stop = sky2_down,
00829823 4654 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4655 .ndo_do_ioctl = sky2_ioctl,
4656 .ndo_validate_addr = eth_validate_addr,
4657 .ndo_set_mac_address = sky2_set_mac_address,
afc4b13d 4658 .ndo_set_rx_mode = sky2_set_multicast,
1436b301 4659 .ndo_change_mtu = sky2_change_mtu,
f5d64037
MM		 4660 .ndo_fix_features = sky2_fix_features,
4661 .ndo_set_features = sky2_set_features,
1436b301 4662 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4663 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4664 },
4665};
3cf26753 4666
cd28ab6a
SH		 4667/* Initialize network device */
4668static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4669 unsigned port,
be63a21c 4670 int highmem, int wol)
cd28ab6a
SH		 4671{
4672 struct sky2_port *sky2;
4673 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4674
4675 if (!dev) {
898eb71c 4676 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4677 return NULL;
4678 }
4679
cd28ab6a 4680 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4681 dev->irq = hw->pdev->irq;
cd28ab6a 4682 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4683 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4684 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4685
4686 sky2 = netdev_priv(dev);
4687 sky2->netdev = dev;
4688 sky2->hw = hw;
4689 sky2->msg_enable = netif_msg_init(debug, default_msg);
4690
cd28ab6a 4691 /* Auto speed and flow control */
0ea065e5
SH		 4692 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4693 if (hw->chip_id != CHIP_ID_YUKON_XL)
f5d64037 4694 dev->hw_features |= NETIF_F_RXCSUM;
0ea065e5 4695
16ad91e1
SH		 4696 sky2->flow_mode = FC_BOTH;
4697
cd28ab6a
SH		 4698 sky2->duplex = -1;
4699 sky2->speed = -1;
4700 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4701 sky2->wol = wol;
75d070c5 4702
e07b1aa8 4703 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4704
793b883e 4705 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4706 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4707 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4708
4709 hw->dev[port] = dev;
4710
4711 sky2->port = port;
4712
f5d64037 4713 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
86aa7785 4714
cd28ab6a
SH		 4715 if (highmem)
4716 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4717
bf73130d
SH		 4718 /* Enable receive hashing unless hardware is known broken */
4719 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
f5d64037
MM		 4720 dev->hw_features |= NETIF_F_RXHASH;
4721
4722 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4723 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4724 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4725 }
bf73130d 4726
f5d64037 4727 dev->features |= dev->hw_features;
d1f13708 4728
cd28ab6a 4729 /* read the mac address */
793b883e 4730 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4731 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4732
cd28ab6a
SH		 4733 return dev;
4734}
4735
28bd181a 4736static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4737{
4738 const struct sky2_port *sky2 = netdev_priv(dev);
4739
6c35abae 4740 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4741}
4742
fb2690a9 4743/* Handle software interrupt used during MSI test */
7d12e780 4744static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4745{
4746 struct sky2_hw *hw = dev_id;
4747 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4748
4749 if (status == 0)
4750 return IRQ_NONE;
4751
4752 if (status & Y2_IS_IRQ_SW) {
ea76e635 4753 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4754 wake_up(&hw->msi_wait);
4755 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4756 }
4757 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4758
4759 return IRQ_HANDLED;
4760}
4761
4762/* Test interrupt path by forcing a a software IRQ */
4763static int __devinit sky2_test_msi(struct sky2_hw *hw)
4764{
4765 struct pci_dev *pdev = hw->pdev;
4766 int err;
4767
060b946c 4768 init_waitqueue_head(&hw->msi_wait);
bb507fe1 4769
fb2690a9
SH		 4770 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4771
b0a20ded 4772 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4773 if (err) {
b02a9258 4774 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4775 return err;
4776 }
4777
fb2690a9 4778 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4779 sky2_read8(hw, B0_CTST);
fb2690a9 4780
ea76e635 4781 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4782
ea76e635 4783 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4784 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4785 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4786 "switching to INTx mode.\n");
fb2690a9
SH		 4787
4788 err = -EOPNOTSUPP;
4789 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4790 }
4791
4792 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4793 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4794
4795 free_irq(pdev->irq, hw);
4796
4797 return err;
4798}
4799
c7127a34
SH		 4800/* This driver supports yukon2 chipset only */
4801static const char *sky2_name(u8 chipid, char *buf, int sz)
4802{
4803 const char *name[] = {
4804 "XL", /* 0xb3 */
4805 "EC Ultra", /* 0xb4 */
4806 "Extreme", /* 0xb5 */
4807 "EC", /* 0xb6 */
4808 "FE", /* 0xb7 */
4809 "FE+", /* 0xb8 */
4810 "Supreme", /* 0xb9 */
0ce8b98d 4811 "UL 2", /* 0xba */
0f5aac70
SH		 4812 "Unknown", /* 0xbb */
4813 "Optima", /* 0xbc */
4fb99cd6 4814 "Optima Prime", /* 0xbd */
4815 "Optima 2", /* 0xbe */
c7127a34
SH		 4816 };
4817
4fb99cd6 4818 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
c7127a34
SH		 4819 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4820 else
4821 snprintf(buf, sz, "(chip %#x)", chipid);
4822 return buf;
4823}
4824
cd28ab6a
SH		 4825static int __devinit sky2_probe(struct pci_dev *pdev,
4826 const struct pci_device_id *ent)
4827{
0bdb0bd0 4828 struct net_device *dev, *dev1;
cd28ab6a 4829 struct sky2_hw *hw;
be63a21c 4830 int err, using_dac = 0, wol_default;
3834507d 4831 u32 reg;
c7127a34 4832 char buf1[16];
cd28ab6a 4833
793b883e
SH		 4834 err = pci_enable_device(pdev);
4835 if (err) {
b02a9258 4836 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4837 goto err_out;
4838 }
4839
6cc90a5a
SH		 4840 /* Get configuration information
4841 * Note: only regular PCI config access once to test for HW issues
4842 * other PCI access through shared memory for speed and to
4843 * avoid MMCONFIG problems.
4844 */
4845 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4846 if (err) {
4847 dev_err(&pdev->dev, "PCI read config failed\n");
4848 goto err_out;
4849 }
4850
4851 if (~reg == 0) {
4852 dev_err(&pdev->dev, "PCI configuration read error\n");
4853 goto err_out;
4854 }
4855
793b883e
SH		 4856 err = pci_request_regions(pdev, DRV_NAME);
4857 if (err) {
b02a9258 4858 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4859 goto err_out_disable;
cd28ab6a
SH		 4860 }
4861
4862 pci_set_master(pdev);
4863
d1f3d4dd 4864 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4865 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4866 using_dac = 1;
6a35528a 4867 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4868 if (err < 0) {
b02a9258
SH		 4869 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4870 "for consistent allocations\n");
d1f3d4dd
SH		 4871 goto err_out_free_regions;
4872 }
d1f3d4dd 4873 } else {
284901a9 4874 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4875 if (err) {
b02a9258 4876 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4877 goto err_out_free_regions;
4878 }
4879 }
d1f3d4dd 4880
3834507d
SH		 4881
4882#ifdef __BIG_ENDIAN
4883 /* The sk98lin vendor driver uses hardware byte swapping but
4884 * this driver uses software swapping.
4885 */
4886 reg &= ~PCI_REV_DESC;
060b946c 4887 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3834507d
SH		 4888 if (err) {
4889 dev_err(&pdev->dev, "PCI write config failed\n");
4890 goto err_out_free_regions;
4891 }
4892#endif
4893
9d731d77 4894 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4895
cd28ab6a 4896 err = -ENOMEM;
66466797
SH		 4897
4898 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4899 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4900 if (!hw) {
b02a9258 4901 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4902 goto err_out_free_regions;
4903 }
4904
cd28ab6a 4905 hw->pdev = pdev;
66466797 4906 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4907
4908 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4909 if (!hw->regs) {
b02a9258 4910 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4911 goto err_out_free_hw;
4912 }
4913
e3173832 4914 err = sky2_init(hw);
cd28ab6a 4915 if (err)
793b883e 4916 goto err_out_iounmap;
cd28ab6a 4917
efe91932 4918 /* ring for status responses */
bf73130d 4919 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
efe91932 4920 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4921 &hw->st_dma);
4922 if (!hw->st_le)
4923 goto err_out_reset;
4924
c844d483
SH		 4925 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4926 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4927
e3173832
SH		 4928 sky2_reset(hw);
4929
be63a21c 4930 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4931 if (!dev) {
4932 err = -ENOMEM;
cd28ab6a 4933 goto err_out_free_pci;
7f60c64b 4934 }
cd28ab6a 4935
9fa1b1f3
SH		 4936 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4937 err = sky2_test_msi(hw);
4938 if (err == -EOPNOTSUPP)
4939 pci_disable_msi(pdev);
4940 else if (err)
4941 goto err_out_free_netdev;
4942 }
4943
793b883e
SH		 4944 err = register_netdev(dev);
4945 if (err) {
b02a9258 4946 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4947 goto err_out_free_netdev;
4948 }
4949
33cb7d33
BP		 4950 netif_carrier_off(dev);
4951
6de16237
SH		 4952 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4953
cd28ab6a
SH		 4954 sky2_show_addr(dev);
4955
7f60c64b 4956 if (hw->ports > 1) {
be63a21c 4957 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
0bdb0bd0 4958 if (!dev1) {
4959 err = -ENOMEM;
4960 goto err_out_unregister;
ca519274 4961 }
0bdb0bd0 4962
4963 err = register_netdev(dev1);
4964 if (err) {
4965 dev_err(&pdev->dev, "cannot register second net device\n");
4966 goto err_out_free_dev1;
4967 }
4968
4969 err = sky2_setup_irq(hw, hw->irq_name);
4970 if (err)
4971 goto err_out_unregister_dev1;
4972
4973 sky2_show_addr(dev1);
cd28ab6a
SH		 4974 }
4975
32c2c300 4976 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4977 INIT_WORK(&hw->restart_work, sky2_restart);
4978
793b883e 4979 pci_set_drvdata(pdev, hw);
1ae861e6 4980 pdev->d3_delay = 150;
793b883e 4981
cd28ab6a
SH		 4982 return 0;
4983
0bdb0bd0 4984err_out_unregister_dev1:
4985 unregister_netdev(dev1);
4986err_out_free_dev1:
4987 free_netdev(dev1);
793b883e 4988err_out_unregister:
ea76e635 4989 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4990 pci_disable_msi(pdev);
793b883e 4991 unregister_netdev(dev);
cd28ab6a
SH		 4992err_out_free_netdev:
4993 free_netdev(dev);
cd28ab6a 4994err_out_free_pci:
efe91932 4995 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4996 hw->st_le, hw->st_dma);
4997err_out_reset:
793b883e 4998 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4999err_out_iounmap:
5000 iounmap(hw->regs);
5001err_out_free_hw:
5002 kfree(hw);
5003err_out_free_regions:
5004 pci_release_regions(pdev);
44a1d2e5 5005err_out_disable:
cd28ab6a 5006 pci_disable_device(pdev);
cd28ab6a 5007err_out:
549a68c3 5008 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 5009 return err;
5010}
5011
5012static void __devexit sky2_remove(struct pci_dev *pdev)
5013{
793b883e 5014 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 5015 int i;
cd28ab6a 5016
793b883e 5017 if (!hw)
cd28ab6a
SH		 5018 return;
5019
32c2c300 5020 del_timer_sync(&hw->watchdog_timer);
6de16237 5021 cancel_work_sync(&hw->restart_work);
d27ed387 5022
b877fe28 5023 for (i = hw->ports-1; i >= 0; --i)
6de16237 5024 unregister_netdev(hw->dev[i]);
81906791 5025
d27ed387 5026 sky2_write32(hw, B0_IMSK, 0);
0bdb0bd0 5027 sky2_read32(hw, B0_IMSK);
cd28ab6a 5028
ae306cca
SH		 5029 sky2_power_aux(hw);
5030
793b883e 5031 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 5032 sky2_read8(hw, B0_CTST);
cd28ab6a 5033
0bdb0bd0 5034 if (hw->ports > 1) {
5035 napi_disable(&hw->napi);
5036 free_irq(pdev->irq, hw);
5037 }
5038
ea76e635 5039 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 5040 pci_disable_msi(pdev);
efe91932 5041 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5042 hw->st_le, hw->st_dma);
cd28ab6a
SH		 5043 pci_release_regions(pdev);
5044 pci_disable_device(pdev);
793b883e 5045
b877fe28 5046 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 5047 free_netdev(hw->dev[i]);
5048
cd28ab6a
SH		 5049 iounmap(hw->regs);
5050 kfree(hw);
5afa0a9c 5051
cd28ab6a
SH		 5052 pci_set_drvdata(pdev, NULL);
5053}
5054
0f333d10 5055static int sky2_suspend(struct device *dev)
cd28ab6a 5056{
0f333d10 5057 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 5058 struct sky2_hw *hw = pci_get_drvdata(pdev);
0f333d10 5059 int i;
cd28ab6a 5060
549a68c3
SH		 5061 if (!hw)
5062 return 0;
5063
063a0b38
SH		 5064 del_timer_sync(&hw->watchdog_timer);
5065 cancel_work_sync(&hw->restart_work);
5066
19720737 5067 rtnl_lock();
3403aca2
MM		 5068
5069 sky2_all_down(hw);
f05267e7 5070 for (i = 0; i < hw->ports; i++) {
cd28ab6a 5071 struct net_device *dev = hw->dev[i];
e3173832 5072 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 5073
e3173832
SH		 5074 if (sky2->wol)
5075 sky2_wol_init(sky2);
cd28ab6a
SH		 5076 }
5077
ae306cca 5078 sky2_power_aux(hw);
19720737 5079 rtnl_unlock();
e3173832 5080
2ccc99b7 5081 return 0;
cd28ab6a
SH		 5082}
5083
94252763 5084#ifdef CONFIG_PM_SLEEP
0f333d10 5085static int sky2_resume(struct device *dev)
cd28ab6a 5086{
0f333d10 5087 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 5088 struct sky2_hw *hw = pci_get_drvdata(pdev);
3403aca2 5089 int err;
cd28ab6a 5090
549a68c3
SH		 5091 if (!hw)
5092 return 0;
5093
1ad5b4a5 5094 /* Re-enable all clocks */
a0db28b8 5095 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5096 if (err) {
5097 dev_err(&pdev->dev, "PCI write config failed\n");
5098 goto out;
5099 }
1ad5b4a5 5100
3403aca2 5101 rtnl_lock();
e3173832 5102 sky2_reset(hw);
3403aca2 5103 sky2_all_up(hw);
af18d8b8 5104 rtnl_unlock();
eb35cf60 5105
ae306cca 5106 return 0;
08c06d8a 5107out:
af18d8b8 5108
b02a9258 5109 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 5110 pci_disable_device(pdev);
08c06d8a 5111 return err;
cd28ab6a 5112}
0f333d10
RW		 5113
5114static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5115#define SKY2_PM_OPS (&sky2_pm_ops)
5116
5117#else
5118
5119#define SKY2_PM_OPS NULL
cd28ab6a
SH		 5120#endif
5121
e3173832
SH		 5122static void sky2_shutdown(struct pci_dev *pdev)
5123{
0f333d10
RW		 5124 sky2_suspend(&pdev->dev);
5125 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5126 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 5127}
5128
cd28ab6a 5129static struct pci_driver sky2_driver = {
793b883e
SH		 5130 .name = DRV_NAME,
5131 .id_table = sky2_id_table,
5132 .probe = sky2_probe,
5133 .remove = __devexit_p(sky2_remove),
e3173832 5134 .shutdown = sky2_shutdown,
0f333d10 5135 .driver.pm = SKY2_PM_OPS,
cd28ab6a
SH		 5136};
5137
5138static int __init sky2_init_module(void)
5139{
ada1db5c 5140 pr_info("driver version " DRV_VERSION "\n");
c844d483 5141
3cf26753 5142 sky2_debug_init();
50241c4c 5143 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 5144}
5145
5146static void __exit sky2_cleanup_module(void)
5147{
5148 pci_unregister_driver(&sky2_driver);
3cf26753 5149 sky2_debug_cleanup();
cd28ab6a
SH		 5150}
5151
5152module_init(sky2_init_module);
5153module_exit(sky2_cleanup_module);
5154
5155MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 5156MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 5157MODULE_LICENSE("GPL");
5f4f9dc1 5158MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)