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KVM: x86: pass host_tsc to read_l1_tsc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
1361b83a 60#include <asm/fpu-internal.h> /* Ugh! */
98918833 61#include <asm/xcr.h>
1d5f066e 62#include <asm/pvclock.h>
217fc9cf 63#include <asm/div64.h>
043405e1 64
313a3dc7 65#define MAX_IO_MSRS 256
890ca9ae 66#define KVM_MAX_MCE_BANKS 32
5854dbca 67#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 68
0f65dd70
AK		 69#define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
1260edbe
LJ		 77static
78u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 79#else
1260edbe 80static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
476bc001
RR		 92static bool ignore_msrs = 0;
93module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
cc578287
ZA		 100/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101static u32 tsc_tolerance_ppm = 250;
102module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
18863bdd
AK		 104#define KVM_NR_SHARED_MSRS 16
105
106struct kvm_shared_msrs_global {
107 int nr;
2bf78fa7 108 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
2bf78fa7
SY		 114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
417bc304 123struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 136 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 144 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 145 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 153 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 155 { "largepages", VM_STAT(lpages) },
417bc304
HB		 156 { NULL }
157};
158
2acf923e
DC		 159u64 __read_mostly host_xcr0;
160
b6785def 161static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 162
8b6e4547
JK		 163static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
2bf78fa7 192 struct kvm_shared_msrs *smsr;
18863bdd
AK		 193 u64 value;
194
2bf78fa7
SY		 195 smsr = &__get_cpu_var(shared_msrs);
196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 226{
227 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
228
2bf78fa7 229 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 230 return;
2bf78fa7
SY		 231 smsr->values[slot].curr = value;
232 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 233 if (!smsr->registered) {
234 smsr->urn.on_user_return = kvm_on_user_return;
235 user_return_notifier_register(&smsr->urn);
236 smsr->registered = true;
237 }
238}
239EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
240
3548bab5
AK		 241static void drop_user_return_notifiers(void *ignore)
242{
243 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
244
245 if (smsr->registered)
246 kvm_on_user_return(&smsr->urn);
247}
248
6866b83e
CO		 249u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
250{
8a5a87d9 251 return vcpu->arch.apic_base;
6866b83e
CO		 252}
253EXPORT_SYMBOL_GPL(kvm_get_apic_base);
254
255void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
256{
257 /* TODO: reserve bits check */
8a5a87d9 258 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
db8fcefa 337void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 338{
db8fcefa
AP		 339 if (err)
340 kvm_inject_gp(vcpu, 0);
341 else
342 kvm_x86_ops->skip_emulated_instruction(vcpu);
343}
344EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 345
6389ee94 346void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 347{
348 ++vcpu->stat.pf_guest;
6389ee94
AK		 349 vcpu->arch.cr2 = fault->address;
350 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 351}
27d6c865 352EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 353
6389ee94 354void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 355{
6389ee94
AK		 356 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
357 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 358 else
6389ee94 359 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 360}
361
3419ffc8
SY		 362void kvm_inject_nmi(struct kvm_vcpu *vcpu)
363{
7460fb4a
AK		 364 atomic_inc(&vcpu->arch.nmi_queued);
365 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 366}
367EXPORT_SYMBOL_GPL(kvm_inject_nmi);
368
298101da
AK		 369void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370{
ce7ddec4 371 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 372}
373EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
374
ce7ddec4
JR		 375void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
376{
377 kvm_multiple_exception(vcpu, nr, true, error_code, true);
378}
379EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
380
0a79b009
AK		 381/*
382 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
383 * a #GP and return false.
384 */
385bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 386{
0a79b009
AK		 387 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
388 return true;
389 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
390 return false;
298101da 391}
0a79b009 392EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 393
ec92fe44
JR		 394/*
395 * This function will be used to read from the physical memory of the currently
396 * running guest. The difference to kvm_read_guest_page is that this function
397 * can read from guest physical or from the guest's guest physical memory.
398 */
399int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
400 gfn_t ngfn, void *data, int offset, int len,
401 u32 access)
402{
403 gfn_t real_gfn;
404 gpa_t ngpa;
405
406 ngpa = gfn_to_gpa(ngfn);
407 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
408 if (real_gfn == UNMAPPED_GVA)
409 return -EFAULT;
410
411 real_gfn = gpa_to_gfn(real_gfn);
412
413 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
414}
415EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
416
3d06b8bf
JR		 417int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
418 void *data, int offset, int len, u32 access)
419{
420 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
421 data, offset, len, access);
422}
423
a03490ed
CO		 424/*
425 * Load the pae pdptrs. Return true is they are all valid.
426 */
ff03a073 427int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 428{
429 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
430 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
431 int i;
432 int ret;
ff03a073 433 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 434
ff03a073
JR		 435 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
436 offset * sizeof(u64), sizeof(pdpte),
437 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 438 if (ret < 0) {
439 ret = 0;
440 goto out;
441 }
442 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 443 if (is_present_gpte(pdpte[i]) &&
20c466b5 444 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 445 ret = 0;
446 goto out;
447 }
448 }
449 ret = 1;
450
ff03a073 451 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_avail);
454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 456out:
a03490ed
CO		 457
458 return ret;
459}
cc4b6871 460EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 461
d835dfec
AK		 462static bool pdptrs_changed(struct kvm_vcpu *vcpu)
463{
ff03a073 464 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 465 bool changed = true;
3d06b8bf
JR		 466 int offset;
467 gfn_t gfn;
d835dfec
AK		 468 int r;
469
470 if (is_long_mode(vcpu) || !is_pae(vcpu))
471 return false;
472
6de4f3ad
AK		 473 if (!test_bit(VCPU_EXREG_PDPTR,
474 (unsigned long *)&vcpu->arch.regs_avail))
475 return true;
476
9f8fe504
AK		 477 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
478 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 479 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
480 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 481 if (r < 0)
482 goto out;
ff03a073 483 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 484out:
d835dfec
AK		 485
486 return changed;
487}
488
49a9b07e 489int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 490{
aad82703
SY		 491 unsigned long old_cr0 = kvm_read_cr0(vcpu);
492 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
493 X86_CR0_CD | X86_CR0_NW;
494
f9a48e6a
AK		 495 cr0 |= X86_CR0_ET;
496
ab344828 497#ifdef CONFIG_X86_64
0f12244f
GN		 498 if (cr0 & 0xffffffff00000000UL)
499 return 1;
ab344828
GN		 500#endif
501
502 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 503
0f12244f
GN		 504 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
505 return 1;
a03490ed 506
0f12244f
GN		 507 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
508 return 1;
a03490ed
CO		 509
510 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
511#ifdef CONFIG_X86_64
f6801dff 512 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 513 int cs_db, cs_l;
514
0f12244f
GN		 515 if (!is_pae(vcpu))
516 return 1;
a03490ed 517 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 518 if (cs_l)
519 return 1;
a03490ed
CO		 520 } else
521#endif
ff03a073 522 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 523 kvm_read_cr3(vcpu)))
0f12244f 524 return 1;
a03490ed
CO		 525 }
526
ad756a16
MJ		 527 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
528 return 1;
529
a03490ed 530 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 531
d170c419 532 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 533 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 534 kvm_async_pf_hash_reset(vcpu);
535 }
e5f3f027 536
aad82703
SY		 537 if ((cr0 ^ old_cr0) & update_bits)
538 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 539 return 0;
540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 542
2d3ad1f4 543void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 544{
49a9b07e 545 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 546}
2d3ad1f4 547EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 548
2acf923e
DC		 549int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
550{
551 u64 xcr0;
552
553 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
554 if (index != XCR_XFEATURE_ENABLED_MASK)
555 return 1;
556 xcr0 = xcr;
557 if (kvm_x86_ops->get_cpl(vcpu) != 0)
558 return 1;
559 if (!(xcr0 & XSTATE_FP))
560 return 1;
561 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
562 return 1;
563 if (xcr0 & ~host_xcr0)
564 return 1;
565 vcpu->arch.xcr0 = xcr0;
566 vcpu->guest_xcr0_loaded = 0;
567 return 0;
568}
569
570int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
571{
572 if (__kvm_set_xcr(vcpu, index, xcr)) {
573 kvm_inject_gp(vcpu, 0);
574 return 1;
575 }
576 return 0;
577}
578EXPORT_SYMBOL_GPL(kvm_set_xcr);
579
a83b29c6 580int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 581{
fc78f519 582 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 583 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
584 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 585 if (cr4 & CR4_RESERVED_BITS)
586 return 1;
a03490ed 587
2acf923e
DC		 588 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
589 return 1;
590
c68b734f
YW		 591 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
592 return 1;
593
74dc2b4f
YW		 594 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
595 return 1;
596
a03490ed 597 if (is_long_mode(vcpu)) {
0f12244f
GN		 598 if (!(cr4 & X86_CR4_PAE))
599 return 1;
a2edf57f
AK		 600 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
601 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 602 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
603 kvm_read_cr3(vcpu)))
0f12244f
GN		 604 return 1;
605
ad756a16
MJ		 606 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
607 if (!guest_cpuid_has_pcid(vcpu))
608 return 1;
609
610 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
611 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
612 return 1;
613 }
614
5e1746d6 615 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 616 return 1;
a03490ed 617
ad756a16
MJ		 618 if (((cr4 ^ old_cr4) & pdptr_bits) ||
619 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 620 kvm_mmu_reset_context(vcpu);
0f12244f 621
2acf923e 622 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 623 kvm_update_cpuid(vcpu);
2acf923e 624
0f12244f
GN		 625 return 0;
626}
2d3ad1f4 627EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 628
2390218b 629int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 630{
9f8fe504 631 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 632 kvm_mmu_sync_roots(vcpu);
d835dfec 633 kvm_mmu_flush_tlb(vcpu);
0f12244f 634 return 0;
d835dfec
AK		 635 }
636
a03490ed 637 if (is_long_mode(vcpu)) {
471842ec 638 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 639 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
640 return 1;
641 } else
642 if (cr3 & CR3_L_MODE_RESERVED_BITS)
643 return 1;
a03490ed
CO		 644 } else {
645 if (is_pae(vcpu)) {
0f12244f
GN		 646 if (cr3 & CR3_PAE_RESERVED_BITS)
647 return 1;
ff03a073
JR		 648 if (is_paging(vcpu) &&
649 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 650 return 1;
a03490ed
CO		 651 }
652 /*
653 * We don't check reserved bits in nonpae mode, because
654 * this isn't enforced, and VMware depends on this.
655 */
656 }
657
a03490ed
CO		 658 /*
659 * Does the new cr3 value map to physical memory? (Note, we
660 * catch an invalid cr3 even in real-mode, because it would
661 * cause trouble later on when we turn on paging anyway.)
662 *
663 * A real CPU would silently accept an invalid cr3 and would
664 * attempt to use it - with largely undefined (and often hard
665 * to debug) behavior on the guest side.
666 */
667 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 668 return 1;
669 vcpu->arch.cr3 = cr3;
aff48baa 670 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 671 vcpu->arch.mmu.new_cr3(vcpu);
672 return 0;
673}
2d3ad1f4 674EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 675
eea1cff9 676int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 677{
0f12244f
GN		 678 if (cr8 & CR8_RESERVED_BITS)
679 return 1;
a03490ed
CO		 680 if (irqchip_in_kernel(vcpu->kvm))
681 kvm_lapic_set_tpr(vcpu, cr8);
682 else
ad312c7c 683 vcpu->arch.cr8 = cr8;
0f12244f
GN		 684 return 0;
685}
2d3ad1f4 686EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 687
2d3ad1f4 688unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 689{
690 if (irqchip_in_kernel(vcpu->kvm))
691 return kvm_lapic_get_cr8(vcpu);
692 else
ad312c7c 693 return vcpu->arch.cr8;
a03490ed 694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 696
c8639010
JK		 697static void kvm_update_dr7(struct kvm_vcpu *vcpu)
698{
699 unsigned long dr7;
700
701 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
702 dr7 = vcpu->arch.guest_debug_dr7;
703 else
704 dr7 = vcpu->arch.dr7;
705 kvm_x86_ops->set_dr7(vcpu, dr7);
706 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
707}
708
338dbc97 709static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 710{
711 switch (dr) {
712 case 0 ... 3:
713 vcpu->arch.db[dr] = val;
714 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
715 vcpu->arch.eff_db[dr] = val;
716 break;
717 case 4:
338dbc97
GN		 718 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
719 return 1; /* #UD */
020df079
GN		 720 /* fall through */
721 case 6:
338dbc97
GN		 722 if (val & 0xffffffff00000000ULL)
723 return -1; /* #GP */
020df079
GN		 724 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
725 break;
726 case 5:
338dbc97
GN		 727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
020df079
GN		 729 /* fall through */
730 default: /* 7 */
338dbc97
GN		 731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
020df079 733 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 734 kvm_update_dr7(vcpu);
020df079
GN		 735 break;
736 }
737
738 return 0;
739}
338dbc97
GN		 740
741int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
742{
743 int res;
744
745 res = __kvm_set_dr(vcpu, dr, val);
746 if (res > 0)
747 kvm_queue_exception(vcpu, UD_VECTOR);
748 else if (res < 0)
749 kvm_inject_gp(vcpu, 0);
750
751 return res;
752}
020df079
GN		 753EXPORT_SYMBOL_GPL(kvm_set_dr);
754
338dbc97 755static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 756{
757 switch (dr) {
758 case 0 ... 3:
759 *val = vcpu->arch.db[dr];
760 break;
761 case 4:
338dbc97 762 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 763 return 1;
020df079
GN		 764 /* fall through */
765 case 6:
766 *val = vcpu->arch.dr6;
767 break;
768 case 5:
338dbc97 769 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 770 return 1;
020df079
GN		 771 /* fall through */
772 default: /* 7 */
773 *val = vcpu->arch.dr7;
774 break;
775 }
776
777 return 0;
778}
338dbc97
GN		 779
780int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
781{
782 if (_kvm_get_dr(vcpu, dr, val)) {
783 kvm_queue_exception(vcpu, UD_VECTOR);
784 return 1;
785 }
786 return 0;
787}
020df079
GN		 788EXPORT_SYMBOL_GPL(kvm_get_dr);
789
022cd0e8
AK		 790bool kvm_rdpmc(struct kvm_vcpu *vcpu)
791{
792 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
793 u64 data;
794 int err;
795
796 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
797 if (err)
798 return err;
799 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
800 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
801 return err;
802}
803EXPORT_SYMBOL_GPL(kvm_rdpmc);
804
043405e1
CO		 805/*
806 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
807 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
808 *
809 * This list is modified at module load time to reflect the
e3267cbb
GC		 810 * capabilities of the host cpu. This capabilities test skips MSRs that are
811 * kvm-specific. Those are put in the beginning of the list.
043405e1 812 */
e3267cbb 813
439793d4 814#define KVM_SAVE_MSRS_BEGIN 10
043405e1 815static u32 msrs_to_save[] = {
e3267cbb 816 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 817 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 818 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 819 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 820 MSR_KVM_PV_EOI_EN,
043405e1 821 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 822 MSR_STAR,
043405e1
CO		 823#ifdef CONFIG_X86_64
824 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
825#endif
e90aa41e 826 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 827};
828
829static unsigned num_msrs_to_save;
830
f1d24831 831static const u32 emulated_msrs[] = {
a3e06bbe 832 MSR_IA32_TSCDEADLINE,
043405e1 833 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 834 MSR_IA32_MCG_STATUS,
835 MSR_IA32_MCG_CTL,
043405e1
CO		 836};
837
b69e8cae 838static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 839{
aad82703
SY		 840 u64 old_efer = vcpu->arch.efer;
841
b69e8cae
RJ		 842 if (efer & efer_reserved_bits)
843 return 1;
15c4a640
CO		 844
845 if (is_paging(vcpu)
b69e8cae
RJ		 846 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
847 return 1;
15c4a640 848
1b2fd70c
AG		 849 if (efer & EFER_FFXSR) {
850 struct kvm_cpuid_entry2 *feat;
851
852 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 853 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
854 return 1;
1b2fd70c
AG		 855 }
856
d8017474
AG		 857 if (efer & EFER_SVME) {
858 struct kvm_cpuid_entry2 *feat;
859
860 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 861 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
862 return 1;
d8017474
AG		 863 }
864
15c4a640 865 efer &= ~EFER_LMA;
f6801dff 866 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 867
a3d204e2
SY		 868 kvm_x86_ops->set_efer(vcpu, efer);
869
9645bb56 870 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 871
aad82703
SY		 872 /* Update reserved bits */
873 if ((efer ^ old_efer) & EFER_NX)
874 kvm_mmu_reset_context(vcpu);
875
b69e8cae 876 return 0;
15c4a640
CO		 877}
878
f2b4b7dd
JR		 879void kvm_enable_efer_bits(u64 mask)
880{
881 efer_reserved_bits &= ~mask;
882}
883EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
884
885
15c4a640
CO		 886/*
887 * Writes msr value into into the appropriate "register".
888 * Returns 0 on success, non-0 otherwise.
889 * Assumes vcpu_load() was already called.
890 */
891int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
892{
893 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
894}
895
313a3dc7
CO		 896/*
897 * Adapt set_msr() to msr_io()'s calling convention
898 */
899static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
900{
901 return kvm_set_msr(vcpu, index, *data);
902}
903
18068523
GOC		 904static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
905{
9ed3c444
AK		 906 int version;
907 int r;
50d0a0f9 908 struct pvclock_wall_clock wc;
923de3cf 909 struct timespec boot;
18068523
GOC		 910
911 if (!wall_clock)
912 return;
913
9ed3c444
AK		 914 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
915 if (r)
916 return;
917
918 if (version & 1)
919 ++version; /* first time write, random junk */
920
921 ++version;
18068523 922
18068523
GOC		 923 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
924
50d0a0f9
GH		 925 /*
926 * The guest calculates current wall clock time by adding
34c238a1 927 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 928 * wall clock specified here. guest system time equals host
929 * system time for us, thus we must fill in host boot time here.
930 */
923de3cf 931 getboottime(&boot);
50d0a0f9 932
4b648665
BR		 933 if (kvm->arch.kvmclock_offset) {
934 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
935 boot = timespec_sub(boot, ts);
936 }
50d0a0f9
GH		 937 wc.sec = boot.tv_sec;
938 wc.nsec = boot.tv_nsec;
939 wc.version = version;
18068523
GOC		 940
941 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
942
943 version++;
944 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 945}
946
50d0a0f9
GH		 947static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
948{
949 uint32_t quotient, remainder;
950
951 /* Don't try to replace with do_div(), this one calculates
952 * "(dividend << 32) / divisor" */
953 __asm__ ( "divl %4"
954 : "=a" (quotient), "=d" (remainder)
955 : "0" (0), "1" (dividend), "r" (divisor) );
956 return quotient;
957}
958
5f4e3f88
ZA		 959static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
960 s8 *pshift, u32 *pmultiplier)
50d0a0f9 961{
5f4e3f88 962 uint64_t scaled64;
50d0a0f9
GH		 963 int32_t shift = 0;
964 uint64_t tps64;
965 uint32_t tps32;
966
5f4e3f88
ZA		 967 tps64 = base_khz * 1000LL;
968 scaled64 = scaled_khz * 1000LL;
50933623 969 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 970 tps64 >>= 1;
971 shift--;
972 }
973
974 tps32 = (uint32_t)tps64;
50933623
JK		 975 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
976 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 977 scaled64 >>= 1;
978 else
979 tps32 <<= 1;
50d0a0f9
GH		 980 shift++;
981 }
982
5f4e3f88
ZA		 983 *pshift = shift;
984 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 985
5f4e3f88
ZA		 986 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
987 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 988}
989
759379dd
ZA		 990static inline u64 get_kernel_ns(void)
991{
992 struct timespec ts;
993
994 WARN_ON(preemptible());
995 ktime_get_ts(&ts);
996 monotonic_to_bootbased(&ts);
997 return timespec_to_ns(&ts);
50d0a0f9
GH		 998}
999
c8076604 1000static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1001unsigned long max_tsc_khz;
c8076604 1002
cc578287 1003static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1004{
cc578287
ZA		 1005 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1006 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1007}
1008
cc578287 1009static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1010{
cc578287
ZA		 1011 u64 v = (u64)khz * (1000000 + ppm);
1012 do_div(v, 1000000);
1013 return v;
1e993611
JR		 1014}
1015
cc578287 1016static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1017{
cc578287
ZA		 1018 u32 thresh_lo, thresh_hi;
1019 int use_scaling = 0;
217fc9cf 1020
c285545f
ZA		 1021 /* Compute a scale to convert nanoseconds in TSC cycles */
1022 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1023 &vcpu->arch.virtual_tsc_shift,
1024 &vcpu->arch.virtual_tsc_mult);
1025 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1026
1027 /*
1028 * Compute the variation in TSC rate which is acceptable
1029 * within the range of tolerance and decide if the
1030 * rate being applied is within that bounds of the hardware
1031 * rate. If so, no scaling or compensation need be done.
1032 */
1033 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1034 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1035 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1036 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1037 use_scaling = 1;
1038 }
1039 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1040}
1041
1042static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1043{
e26101b1 1044 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1045 vcpu->arch.virtual_tsc_mult,
1046 vcpu->arch.virtual_tsc_shift);
e26101b1 1047 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1048 return tsc;
1049}
1050
99e3e30a
ZA		 1051void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1052{
1053 struct kvm *kvm = vcpu->kvm;
f38e098f 1054 u64 offset, ns, elapsed;
99e3e30a 1055 unsigned long flags;
02626b6a 1056 s64 usdiff;
99e3e30a 1057
038f8c11 1058 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1059 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1060 ns = get_kernel_ns();
f38e098f 1061 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1062
1063 /* n.b - signed multiplication and division required */
02626b6a 1064 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1065#ifdef CONFIG_X86_64
02626b6a 1066 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1067#else
1068 /* do_div() only does unsigned */
1069 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1070 : "=A"(usdiff)
1071 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1072#endif
02626b6a
MT		 1073 do_div(elapsed, 1000);
1074 usdiff -= elapsed;
1075 if (usdiff < 0)
1076 usdiff = -usdiff;
f38e098f
ZA		 1077
1078 /*
5d3cb0f6
ZA		 1079 * Special case: TSC write with a small delta (1 second) of virtual
1080 * cycle time against real time is interpreted as an attempt to
1081 * synchronize the CPU.
1082 *
1083 * For a reliable TSC, we can match TSC offsets, and for an unstable
1084 * TSC, we add elapsed time in this computation. We could let the
1085 * compensation code attempt to catch up if we fall behind, but
1086 * it's better to try to match offsets from the beginning.
1087 */
02626b6a 1088 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1089 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1090 if (!check_tsc_unstable()) {
e26101b1 1091 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1092 pr_debug("kvm: matched tsc offset for %llu\n", data);
1093 } else {
857e4099 1094 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1095 data += delta;
1096 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1097 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1098 }
e26101b1
ZA		 1099 } else {
1100 /*
1101 * We split periods of matched TSC writes into generations.
1102 * For each generation, we track the original measured
1103 * nanosecond time, offset, and write, so if TSCs are in
1104 * sync, we can match exact offset, and if not, we can match
4a969980 1105 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1106 *
1107 * These values are tracked in kvm->arch.cur_xxx variables.
1108 */
1109 kvm->arch.cur_tsc_generation++;
1110 kvm->arch.cur_tsc_nsec = ns;
1111 kvm->arch.cur_tsc_write = data;
1112 kvm->arch.cur_tsc_offset = offset;
1113 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1114 kvm->arch.cur_tsc_generation, data);
f38e098f 1115 }
e26101b1
ZA		 1116
1117 /*
1118 * We also track th most recent recorded KHZ, write and time to
1119 * allow the matching interval to be extended at each write.
1120 */
f38e098f
ZA		 1121 kvm->arch.last_tsc_nsec = ns;
1122 kvm->arch.last_tsc_write = data;
5d3cb0f6 1123 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1124
1125 /* Reset of TSC must disable overshoot protection below */
1126 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1127 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1128
1129 /* Keep track of which generation this VCPU has synchronized to */
1130 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1131 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1132 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1133
1134 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1135 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1136}
e26101b1 1137
99e3e30a
ZA		 1138EXPORT_SYMBOL_GPL(kvm_write_tsc);
1139
34c238a1 1140static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1141{
18068523
GOC		 1142 unsigned long flags;
1143 struct kvm_vcpu_arch *vcpu = &v->arch;
1144 void *shared_kaddr;
463656c0 1145 unsigned long this_tsc_khz;
1d5f066e
ZA		 1146 s64 kernel_ns, max_kernel_ns;
1147 u64 tsc_timestamp;
78c0337a 1148 struct pvclock_vcpu_time_info *guest_hv_clock;
51d59c6b 1149 u8 pvclock_flags;
18068523 1150
18068523
GOC		 1151 /* Keep irq disabled to prevent changes to the clock */
1152 local_irq_save(flags);
886b470c 1153 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, native_read_tsc());
759379dd 1154 kernel_ns = get_kernel_ns();
cc578287 1155 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1156 if (unlikely(this_tsc_khz == 0)) {
c285545f 1157 local_irq_restore(flags);
34c238a1 1158 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1159 return 1;
1160 }
18068523 1161
c285545f
ZA		 1162 /*
1163 * We may have to catch up the TSC to match elapsed wall clock
1164 * time for two reasons, even if kvmclock is used.
1165 * 1) CPU could have been running below the maximum TSC rate
1166 * 2) Broken TSC compensation resets the base at each VCPU
1167 * entry to avoid unknown leaps of TSC even when running
1168 * again on the same CPU. This may cause apparent elapsed
1169 * time to disappear, and the guest to stand still or run
1170 * very slowly.
1171 */
1172 if (vcpu->tsc_catchup) {
1173 u64 tsc = compute_guest_tsc(v, kernel_ns);
1174 if (tsc > tsc_timestamp) {
f1e2b260 1175 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1176 tsc_timestamp = tsc;
1177 }
50d0a0f9
GH		 1178 }
1179
18068523
GOC		 1180 local_irq_restore(flags);
1181
c285545f
ZA		 1182 if (!vcpu->time_page)
1183 return 0;
18068523 1184
1d5f066e
ZA		 1185 /*
1186 * Time as measured by the TSC may go backwards when resetting the base
1187 * tsc_timestamp. The reason for this is that the TSC resolution is
1188 * higher than the resolution of the other clock scales. Thus, many
1189 * possible measurments of the TSC correspond to one measurement of any
1190 * other clock, and so a spread of values is possible. This is not a
1191 * problem for the computation of the nanosecond clock; with TSC rates
1192 * around 1GHZ, there can only be a few cycles which correspond to one
1193 * nanosecond value, and any path through this code will inevitably
1194 * take longer than that. However, with the kernel_ns value itself,
1195 * the precision may be much lower, down to HZ granularity. If the
1196 * first sampling of TSC against kernel_ns ends in the low part of the
1197 * range, and the second in the high end of the range, we can get:
1198 *
1199 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1200 *
1201 * As the sampling errors potentially range in the thousands of cycles,
1202 * it is possible such a time value has already been observed by the
1203 * guest. To protect against this, we must compute the system time as
1204 * observed by the guest and ensure the new system time is greater.
1205 */
1206 max_kernel_ns = 0;
b183aa58 1207 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1208 max_kernel_ns = vcpu->last_guest_tsc -
1209 vcpu->hv_clock.tsc_timestamp;
1210 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1211 vcpu->hv_clock.tsc_to_system_mul,
1212 vcpu->hv_clock.tsc_shift);
1213 max_kernel_ns += vcpu->last_kernel_ns;
1214 }
afbcf7ab 1215
e48672fa 1216 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1217 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1218 &vcpu->hv_clock.tsc_shift,
1219 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1220 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1221 }
1222
1d5f066e
ZA		 1223 if (max_kernel_ns > kernel_ns)
1224 kernel_ns = max_kernel_ns;
1225
8cfdc000 1226 /* With all the info we got, fill in the values */
1d5f066e 1227 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1228 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1229 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1230 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1231
371bcf64 1232
18068523
GOC		 1233 /*
1234 * The interface expects us to write an even number signaling that the
1235 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1236 * state, we just increase by 2 at the end.
18068523 1237 */
50d0a0f9 1238 vcpu->hv_clock.version += 2;
18068523 1239
8fd75e12 1240 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523 1241
78c0337a
MT		 1242 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1243
1244 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1245 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1246
1247 if (vcpu->pvclock_set_guest_stopped_request) {
1248 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1249 vcpu->pvclock_set_guest_stopped_request = false;
1250 }
1251
1252 vcpu->hv_clock.flags = pvclock_flags;
1253
18068523 1254 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1255 sizeof(vcpu->hv_clock));
18068523 1256
8fd75e12 1257 kunmap_atomic(shared_kaddr);
18068523
GOC		 1258
1259 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1260 return 0;
c8076604
GH		 1261}
1262
9ba075a6
AK		 1263static bool msr_mtrr_valid(unsigned msr)
1264{
1265 switch (msr) {
1266 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1267 case MSR_MTRRfix64K_00000:
1268 case MSR_MTRRfix16K_80000:
1269 case MSR_MTRRfix16K_A0000:
1270 case MSR_MTRRfix4K_C0000:
1271 case MSR_MTRRfix4K_C8000:
1272 case MSR_MTRRfix4K_D0000:
1273 case MSR_MTRRfix4K_D8000:
1274 case MSR_MTRRfix4K_E0000:
1275 case MSR_MTRRfix4K_E8000:
1276 case MSR_MTRRfix4K_F0000:
1277 case MSR_MTRRfix4K_F8000:
1278 case MSR_MTRRdefType:
1279 case MSR_IA32_CR_PAT:
1280 return true;
1281 case 0x2f8:
1282 return true;
1283 }
1284 return false;
1285}
1286
d6289b93
MT		 1287static bool valid_pat_type(unsigned t)
1288{
1289 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1290}
1291
1292static bool valid_mtrr_type(unsigned t)
1293{
1294 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1295}
1296
1297static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1298{
1299 int i;
1300
1301 if (!msr_mtrr_valid(msr))
1302 return false;
1303
1304 if (msr == MSR_IA32_CR_PAT) {
1305 for (i = 0; i < 8; i++)
1306 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1307 return false;
1308 return true;
1309 } else if (msr == MSR_MTRRdefType) {
1310 if (data & ~0xcff)
1311 return false;
1312 return valid_mtrr_type(data & 0xff);
1313 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1314 for (i = 0; i < 8 ; i++)
1315 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1316 return false;
1317 return true;
1318 }
1319
1320 /* variable MTRRs */
1321 return valid_mtrr_type(data & 0xff);
1322}
1323
9ba075a6
AK		 1324static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1325{
0bed3b56
SY		 1326 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1327
d6289b93 1328 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1329 return 1;
1330
0bed3b56
SY		 1331 if (msr == MSR_MTRRdefType) {
1332 vcpu->arch.mtrr_state.def_type = data;
1333 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1334 } else if (msr == MSR_MTRRfix64K_00000)
1335 p[0] = data;
1336 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1337 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1338 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1339 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1340 else if (msr == MSR_IA32_CR_PAT)
1341 vcpu->arch.pat = data;
1342 else { /* Variable MTRRs */
1343 int idx, is_mtrr_mask;
1344 u64 *pt;
1345
1346 idx = (msr - 0x200) / 2;
1347 is_mtrr_mask = msr - 0x200 - 2 * idx;
1348 if (!is_mtrr_mask)
1349 pt =
1350 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1351 else
1352 pt =
1353 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1354 *pt = data;
1355 }
1356
1357 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1358 return 0;
1359}
15c4a640 1360
890ca9ae 1361static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1362{
890ca9ae
HY		 1363 u64 mcg_cap = vcpu->arch.mcg_cap;
1364 unsigned bank_num = mcg_cap & 0xff;
1365
15c4a640 1366 switch (msr) {
15c4a640 1367 case MSR_IA32_MCG_STATUS:
890ca9ae 1368 vcpu->arch.mcg_status = data;
15c4a640 1369 break;
c7ac679c 1370 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1371 if (!(mcg_cap & MCG_CTL_P))
1372 return 1;
1373 if (data != 0 && data != ~(u64)0)
1374 return -1;
1375 vcpu->arch.mcg_ctl = data;
1376 break;
1377 default:
1378 if (msr >= MSR_IA32_MC0_CTL &&
1379 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1380 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1381 /* only 0 or all 1s can be written to IA32_MCi_CTL
1382 * some Linux kernels though clear bit 10 in bank 4 to
1383 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1384 * this to avoid an uncatched #GP in the guest
1385 */
890ca9ae 1386 if ((offset & 0x3) == 0 &&
114be429 1387 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1388 return -1;
1389 vcpu->arch.mce_banks[offset] = data;
1390 break;
1391 }
1392 return 1;
1393 }
1394 return 0;
1395}
1396
ffde22ac
ES		 1397static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1398{
1399 struct kvm *kvm = vcpu->kvm;
1400 int lm = is_long_mode(vcpu);
1401 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1402 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1403 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1404 : kvm->arch.xen_hvm_config.blob_size_32;
1405 u32 page_num = data & ~PAGE_MASK;
1406 u64 page_addr = data & PAGE_MASK;
1407 u8 *page;
1408 int r;
1409
1410 r = -E2BIG;
1411 if (page_num >= blob_size)
1412 goto out;
1413 r = -ENOMEM;
ff5c2c03
SL		 1414 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1415 if (IS_ERR(page)) {
1416 r = PTR_ERR(page);
ffde22ac 1417 goto out;
ff5c2c03 1418 }
ffde22ac
ES		 1419 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1420 goto out_free;
1421 r = 0;
1422out_free:
1423 kfree(page);
1424out:
1425 return r;
1426}
1427
55cd8e5a
GN		 1428static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1429{
1430 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1431}
1432
1433static bool kvm_hv_msr_partition_wide(u32 msr)
1434{
1435 bool r = false;
1436 switch (msr) {
1437 case HV_X64_MSR_GUEST_OS_ID:
1438 case HV_X64_MSR_HYPERCALL:
1439 r = true;
1440 break;
1441 }
1442
1443 return r;
1444}
1445
1446static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1447{
1448 struct kvm *kvm = vcpu->kvm;
1449
1450 switch (msr) {
1451 case HV_X64_MSR_GUEST_OS_ID:
1452 kvm->arch.hv_guest_os_id = data;
1453 /* setting guest os id to zero disables hypercall page */
1454 if (!kvm->arch.hv_guest_os_id)
1455 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1456 break;
1457 case HV_X64_MSR_HYPERCALL: {
1458 u64 gfn;
1459 unsigned long addr;
1460 u8 instructions[4];
1461
1462 /* if guest os id is not set hypercall should remain disabled */
1463 if (!kvm->arch.hv_guest_os_id)
1464 break;
1465 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1466 kvm->arch.hv_hypercall = data;
1467 break;
1468 }
1469 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1470 addr = gfn_to_hva(kvm, gfn);
1471 if (kvm_is_error_hva(addr))
1472 return 1;
1473 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1474 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1475 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1476 return 1;
1477 kvm->arch.hv_hypercall = data;
1478 break;
1479 }
1480 default:
a737f256
CD		 1481 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1482 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1483 return 1;
1484 }
1485 return 0;
1486}
1487
1488static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1489{
10388a07
GN		 1490 switch (msr) {
1491 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1492 unsigned long addr;
55cd8e5a 1493
10388a07
GN		 1494 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1495 vcpu->arch.hv_vapic = data;
1496 break;
1497 }
1498 addr = gfn_to_hva(vcpu->kvm, data >>
1499 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1500 if (kvm_is_error_hva(addr))
1501 return 1;
8b0cedff 1502 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1503 return 1;
1504 vcpu->arch.hv_vapic = data;
1505 break;
1506 }
1507 case HV_X64_MSR_EOI:
1508 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1509 case HV_X64_MSR_ICR:
1510 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1511 case HV_X64_MSR_TPR:
1512 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1513 default:
a737f256
CD		 1514 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1515 "data 0x%llx\n", msr, data);
10388a07
GN		 1516 return 1;
1517 }
1518
1519 return 0;
55cd8e5a
GN		 1520}
1521
344d9588
GN		 1522static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1523{
1524 gpa_t gpa = data & ~0x3f;
1525
4a969980 1526 /* Bits 2:5 are reserved, Should be zero */
6adba527 1527 if (data & 0x3c)
344d9588
GN		 1528 return 1;
1529
1530 vcpu->arch.apf.msr_val = data;
1531
1532 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1533 kvm_clear_async_pf_completion_queue(vcpu);
1534 kvm_async_pf_hash_reset(vcpu);
1535 return 0;
1536 }
1537
1538 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1539 return 1;
1540
6adba527 1541 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1542 kvm_async_pf_wakeup_all(vcpu);
1543 return 0;
1544}
1545
12f9a48f
GC		 1546static void kvmclock_reset(struct kvm_vcpu *vcpu)
1547{
1548 if (vcpu->arch.time_page) {
1549 kvm_release_page_dirty(vcpu->arch.time_page);
1550 vcpu->arch.time_page = NULL;
1551 }
1552}
1553
c9aaa895
GC		 1554static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1555{
1556 u64 delta;
1557
1558 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1559 return;
1560
1561 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1562 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1563 vcpu->arch.st.accum_steal = delta;
1564}
1565
1566static void record_steal_time(struct kvm_vcpu *vcpu)
1567{
1568 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1569 return;
1570
1571 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1572 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1573 return;
1574
1575 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1576 vcpu->arch.st.steal.version += 2;
1577 vcpu->arch.st.accum_steal = 0;
1578
1579 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1580 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1581}
1582
15c4a640
CO		 1583int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1584{
5753785f
GN		 1585 bool pr = false;
1586
15c4a640 1587 switch (msr) {
15c4a640 1588 case MSR_EFER:
b69e8cae 1589 return set_efer(vcpu, data);
8f1589d9
AP		 1590 case MSR_K7_HWCR:
1591 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1592 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1593 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1594 if (data != 0) {
a737f256
CD		 1595 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1596 data);
8f1589d9
AP		 1597 return 1;
1598 }
15c4a640 1599 break;
f7c6d140
AP		 1600 case MSR_FAM10H_MMIO_CONF_BASE:
1601 if (data != 0) {
a737f256
CD		 1602 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1603 "0x%llx\n", data);
f7c6d140
AP		 1604 return 1;
1605 }
15c4a640 1606 break;
c323c0e5 1607 case MSR_AMD64_NB_CFG:
c7ac679c 1608 break;
b5e2fec0
AG		 1609 case MSR_IA32_DEBUGCTLMSR:
1610 if (!data) {
1611 /* We support the non-activated case already */
1612 break;
1613 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1614 /* Values other than LBR and BTF are vendor-specific,
1615 thus reserved and should throw a #GP */
1616 return 1;
1617 }
a737f256
CD		 1618 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1619 __func__, data);
b5e2fec0 1620 break;
15c4a640
CO		 1621 case MSR_IA32_UCODE_REV:
1622 case MSR_IA32_UCODE_WRITE:
61a6bd67 1623 case MSR_VM_HSAVE_PA:
6098ca93 1624 case MSR_AMD64_PATCH_LOADER:
15c4a640 1625 break;
9ba075a6
AK		 1626 case 0x200 ... 0x2ff:
1627 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1628 case MSR_IA32_APICBASE:
1629 kvm_set_apic_base(vcpu, data);
1630 break;
0105d1a5
GN		 1631 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1632 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1633 case MSR_IA32_TSCDEADLINE:
1634 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1635 break;
15c4a640 1636 case MSR_IA32_MISC_ENABLE:
ad312c7c 1637 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1638 break;
11c6bffa 1639 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1640 case MSR_KVM_WALL_CLOCK:
1641 vcpu->kvm->arch.wall_clock = data;
1642 kvm_write_wall_clock(vcpu->kvm, data);
1643 break;
11c6bffa 1644 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1645 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1646 kvmclock_reset(vcpu);
18068523
GOC		 1647
1648 vcpu->arch.time = data;
c285545f 1649 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1650
1651 /* we verify if the enable bit is set... */
1652 if (!(data & 1))
1653 break;
1654
1655 /* ...but clean it before doing the actual write */
1656 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1657
18068523
GOC		 1658 vcpu->arch.time_page =
1659 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1660
32cad84f 1661 if (is_error_page(vcpu->arch.time_page))
18068523 1662 vcpu->arch.time_page = NULL;
32cad84f 1663
18068523
GOC		 1664 break;
1665 }
344d9588
GN		 1666 case MSR_KVM_ASYNC_PF_EN:
1667 if (kvm_pv_enable_async_pf(vcpu, data))
1668 return 1;
1669 break;
c9aaa895
GC		 1670 case MSR_KVM_STEAL_TIME:
1671
1672 if (unlikely(!sched_info_on()))
1673 return 1;
1674
1675 if (data & KVM_STEAL_RESERVED_MASK)
1676 return 1;
1677
1678 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1679 data & KVM_STEAL_VALID_BITS))
1680 return 1;
1681
1682 vcpu->arch.st.msr_val = data;
1683
1684 if (!(data & KVM_MSR_ENABLED))
1685 break;
1686
1687 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1688
1689 preempt_disable();
1690 accumulate_steal_time(vcpu);
1691 preempt_enable();
1692
1693 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1694
1695 break;
ae7a2a3f
MT		 1696 case MSR_KVM_PV_EOI_EN:
1697 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1698 return 1;
1699 break;
c9aaa895 1700
890ca9ae
HY		 1701 case MSR_IA32_MCG_CTL:
1702 case MSR_IA32_MCG_STATUS:
1703 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1704 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1705
1706 /* Performance counters are not protected by a CPUID bit,
1707 * so we should check all of them in the generic path for the sake of
1708 * cross vendor migration.
1709 * Writing a zero into the event select MSRs disables them,
1710 * which we perfectly emulate ;-). Any other value should be at least
1711 * reported, some guests depend on them.
1712 */
71db6023
AP		 1713 case MSR_K7_EVNTSEL0:
1714 case MSR_K7_EVNTSEL1:
1715 case MSR_K7_EVNTSEL2:
1716 case MSR_K7_EVNTSEL3:
1717 if (data != 0)
a737f256
CD		 1718 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1719 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1720 break;
1721 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1722 * so we ignore writes to make it happy.
1723 */
71db6023
AP		 1724 case MSR_K7_PERFCTR0:
1725 case MSR_K7_PERFCTR1:
1726 case MSR_K7_PERFCTR2:
1727 case MSR_K7_PERFCTR3:
a737f256
CD		 1728 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1729 "0x%x data 0x%llx\n", msr, data);
71db6023 1730 break;
5753785f
GN		 1731 case MSR_P6_PERFCTR0:
1732 case MSR_P6_PERFCTR1:
1733 pr = true;
1734 case MSR_P6_EVNTSEL0:
1735 case MSR_P6_EVNTSEL1:
1736 if (kvm_pmu_msr(vcpu, msr))
1737 return kvm_pmu_set_msr(vcpu, msr, data);
1738
1739 if (pr || data != 0)
a737f256
CD		 1740 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1741 "0x%x data 0x%llx\n", msr, data);
5753785f 1742 break;
84e0cefa
JS		 1743 case MSR_K7_CLK_CTL:
1744 /*
1745 * Ignore all writes to this no longer documented MSR.
1746 * Writes are only relevant for old K7 processors,
1747 * all pre-dating SVM, but a recommended workaround from
4a969980 1748 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 1749 * affected processor models on the command line, hence
1750 * the need to ignore the workaround.
1751 */
1752 break;
55cd8e5a
GN		 1753 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1754 if (kvm_hv_msr_partition_wide(msr)) {
1755 int r;
1756 mutex_lock(&vcpu->kvm->lock);
1757 r = set_msr_hyperv_pw(vcpu, msr, data);
1758 mutex_unlock(&vcpu->kvm->lock);
1759 return r;
1760 } else
1761 return set_msr_hyperv(vcpu, msr, data);
1762 break;
91c9c3ed 1763 case MSR_IA32_BBL_CR_CTL3:
1764 /* Drop writes to this legacy MSR -- see rdmsr
1765 * counterpart for further detail.
1766 */
a737f256 1767 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 1768 break;
2b036c6b
BO		 1769 case MSR_AMD64_OSVW_ID_LENGTH:
1770 if (!guest_cpuid_has_osvw(vcpu))
1771 return 1;
1772 vcpu->arch.osvw.length = data;
1773 break;
1774 case MSR_AMD64_OSVW_STATUS:
1775 if (!guest_cpuid_has_osvw(vcpu))
1776 return 1;
1777 vcpu->arch.osvw.status = data;
1778 break;
15c4a640 1779 default:
ffde22ac
ES		 1780 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1781 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1782 if (kvm_pmu_msr(vcpu, msr))
1783 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 1784 if (!ignore_msrs) {
a737f256
CD		 1785 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1786 msr, data);
ed85c068
AP		 1787 return 1;
1788 } else {
a737f256
CD		 1789 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1790 msr, data);
ed85c068
AP		 1791 break;
1792 }
15c4a640
CO		 1793 }
1794 return 0;
1795}
1796EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1797
1798
1799/*
1800 * Reads an msr value (of 'msr_index') into 'pdata'.
1801 * Returns 0 on success, non-0 otherwise.
1802 * Assumes vcpu_load() was already called.
1803 */
1804int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1805{
1806 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1807}
1808
9ba075a6
AK		 1809static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1810{
0bed3b56
SY		 1811 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1812
9ba075a6
AK		 1813 if (!msr_mtrr_valid(msr))
1814 return 1;
1815
0bed3b56
SY		 1816 if (msr == MSR_MTRRdefType)
1817 *pdata = vcpu->arch.mtrr_state.def_type +
1818 (vcpu->arch.mtrr_state.enabled << 10);
1819 else if (msr == MSR_MTRRfix64K_00000)
1820 *pdata = p[0];
1821 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1822 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1823 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1824 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1825 else if (msr == MSR_IA32_CR_PAT)
1826 *pdata = vcpu->arch.pat;
1827 else { /* Variable MTRRs */
1828 int idx, is_mtrr_mask;
1829 u64 *pt;
1830
1831 idx = (msr - 0x200) / 2;
1832 is_mtrr_mask = msr - 0x200 - 2 * idx;
1833 if (!is_mtrr_mask)
1834 pt =
1835 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1836 else
1837 pt =
1838 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1839 *pdata = *pt;
1840 }
1841
9ba075a6
AK		 1842 return 0;
1843}
1844
890ca9ae 1845static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1846{
1847 u64 data;
890ca9ae
HY		 1848 u64 mcg_cap = vcpu->arch.mcg_cap;
1849 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1850
1851 switch (msr) {
15c4a640
CO		 1852 case MSR_IA32_P5_MC_ADDR:
1853 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1854 data = 0;
1855 break;
15c4a640 1856 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1857 data = vcpu->arch.mcg_cap;
1858 break;
c7ac679c 1859 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1860 if (!(mcg_cap & MCG_CTL_P))
1861 return 1;
1862 data = vcpu->arch.mcg_ctl;
1863 break;
1864 case MSR_IA32_MCG_STATUS:
1865 data = vcpu->arch.mcg_status;
1866 break;
1867 default:
1868 if (msr >= MSR_IA32_MC0_CTL &&
1869 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1870 u32 offset = msr - MSR_IA32_MC0_CTL;
1871 data = vcpu->arch.mce_banks[offset];
1872 break;
1873 }
1874 return 1;
1875 }
1876 *pdata = data;
1877 return 0;
1878}
1879
55cd8e5a
GN		 1880static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1881{
1882 u64 data = 0;
1883 struct kvm *kvm = vcpu->kvm;
1884
1885 switch (msr) {
1886 case HV_X64_MSR_GUEST_OS_ID:
1887 data = kvm->arch.hv_guest_os_id;
1888 break;
1889 case HV_X64_MSR_HYPERCALL:
1890 data = kvm->arch.hv_hypercall;
1891 break;
1892 default:
a737f256 1893 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1894 return 1;
1895 }
1896
1897 *pdata = data;
1898 return 0;
1899}
1900
1901static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1902{
1903 u64 data = 0;
1904
1905 switch (msr) {
1906 case HV_X64_MSR_VP_INDEX: {
1907 int r;
1908 struct kvm_vcpu *v;
1909 kvm_for_each_vcpu(r, v, vcpu->kvm)
1910 if (v == vcpu)
1911 data = r;
1912 break;
1913 }
10388a07
GN		 1914 case HV_X64_MSR_EOI:
1915 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1916 case HV_X64_MSR_ICR:
1917 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1918 case HV_X64_MSR_TPR:
1919 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1920 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1921 data = vcpu->arch.hv_vapic;
1922 break;
55cd8e5a 1923 default:
a737f256 1924 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1925 return 1;
1926 }
1927 *pdata = data;
1928 return 0;
1929}
1930
890ca9ae
HY		 1931int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1932{
1933 u64 data;
1934
1935 switch (msr) {
890ca9ae 1936 case MSR_IA32_PLATFORM_ID:
15c4a640 1937 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1938 case MSR_IA32_DEBUGCTLMSR:
1939 case MSR_IA32_LASTBRANCHFROMIP:
1940 case MSR_IA32_LASTBRANCHTOIP:
1941 case MSR_IA32_LASTINTFROMIP:
1942 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1943 case MSR_K8_SYSCFG:
1944 case MSR_K7_HWCR:
61a6bd67 1945 case MSR_VM_HSAVE_PA:
9e699624 1946 case MSR_K7_EVNTSEL0:
1f3ee616 1947 case MSR_K7_PERFCTR0:
1fdbd48c 1948 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1949 case MSR_AMD64_NB_CFG:
f7c6d140 1950 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1951 data = 0;
1952 break;
5753785f
GN		 1953 case MSR_P6_PERFCTR0:
1954 case MSR_P6_PERFCTR1:
1955 case MSR_P6_EVNTSEL0:
1956 case MSR_P6_EVNTSEL1:
1957 if (kvm_pmu_msr(vcpu, msr))
1958 return kvm_pmu_get_msr(vcpu, msr, pdata);
1959 data = 0;
1960 break;
742bc670
MT		 1961 case MSR_IA32_UCODE_REV:
1962 data = 0x100000000ULL;
1963 break;
9ba075a6
AK		 1964 case MSR_MTRRcap:
1965 data = 0x500 | KVM_NR_VAR_MTRR;
1966 break;
1967 case 0x200 ... 0x2ff:
1968 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1969 case 0xcd: /* fsb frequency */
1970 data = 3;
1971 break;
7b914098
JS		 1972 /*
1973 * MSR_EBC_FREQUENCY_ID
1974 * Conservative value valid for even the basic CPU models.
1975 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1976 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1977 * and 266MHz for model 3, or 4. Set Core Clock
1978 * Frequency to System Bus Frequency Ratio to 1 (bits
1979 * 31:24) even though these are only valid for CPU
1980 * models > 2, however guests may end up dividing or
1981 * multiplying by zero otherwise.
1982 */
1983 case MSR_EBC_FREQUENCY_ID:
1984 data = 1 << 24;
1985 break;
15c4a640
CO		 1986 case MSR_IA32_APICBASE:
1987 data = kvm_get_apic_base(vcpu);
1988 break;
0105d1a5
GN		 1989 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1990 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1991 break;
a3e06bbe
LJ		 1992 case MSR_IA32_TSCDEADLINE:
1993 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1994 break;
15c4a640 1995 case MSR_IA32_MISC_ENABLE:
ad312c7c 1996 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1997 break;
847f0ad8
AG		 1998 case MSR_IA32_PERF_STATUS:
1999 /* TSC increment by tick */
2000 data = 1000ULL;
2001 /* CPU multiplier */
2002 data |= (((uint64_t)4ULL) << 40);
2003 break;
15c4a640 2004 case MSR_EFER:
f6801dff 2005 data = vcpu->arch.efer;
15c4a640 2006 break;
18068523 2007 case MSR_KVM_WALL_CLOCK:
11c6bffa 2008 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2009 data = vcpu->kvm->arch.wall_clock;
2010 break;
2011 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2012 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2013 data = vcpu->arch.time;
2014 break;
344d9588
GN		 2015 case MSR_KVM_ASYNC_PF_EN:
2016 data = vcpu->arch.apf.msr_val;
2017 break;
c9aaa895
GC		 2018 case MSR_KVM_STEAL_TIME:
2019 data = vcpu->arch.st.msr_val;
2020 break;
1d92128f
MT		 2021 case MSR_KVM_PV_EOI_EN:
2022 data = vcpu->arch.pv_eoi.msr_val;
2023 break;
890ca9ae
HY		 2024 case MSR_IA32_P5_MC_ADDR:
2025 case MSR_IA32_P5_MC_TYPE:
2026 case MSR_IA32_MCG_CAP:
2027 case MSR_IA32_MCG_CTL:
2028 case MSR_IA32_MCG_STATUS:
2029 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2030 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2031 case MSR_K7_CLK_CTL:
2032 /*
2033 * Provide expected ramp-up count for K7. All other
2034 * are set to zero, indicating minimum divisors for
2035 * every field.
2036 *
2037 * This prevents guest kernels on AMD host with CPU
2038 * type 6, model 8 and higher from exploding due to
2039 * the rdmsr failing.
2040 */
2041 data = 0x20000000;
2042 break;
55cd8e5a
GN		 2043 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2044 if (kvm_hv_msr_partition_wide(msr)) {
2045 int r;
2046 mutex_lock(&vcpu->kvm->lock);
2047 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2048 mutex_unlock(&vcpu->kvm->lock);
2049 return r;
2050 } else
2051 return get_msr_hyperv(vcpu, msr, pdata);
2052 break;
91c9c3ed 2053 case MSR_IA32_BBL_CR_CTL3:
2054 /* This legacy MSR exists but isn't fully documented in current
2055 * silicon. It is however accessed by winxp in very narrow
2056 * scenarios where it sets bit #19, itself documented as
2057 * a "reserved" bit. Best effort attempt to source coherent
2058 * read data here should the balance of the register be
2059 * interpreted by the guest:
2060 *
2061 * L2 cache control register 3: 64GB range, 256KB size,
2062 * enabled, latency 0x1, configured
2063 */
2064 data = 0xbe702111;
2065 break;
2b036c6b
BO		 2066 case MSR_AMD64_OSVW_ID_LENGTH:
2067 if (!guest_cpuid_has_osvw(vcpu))
2068 return 1;
2069 data = vcpu->arch.osvw.length;
2070 break;
2071 case MSR_AMD64_OSVW_STATUS:
2072 if (!guest_cpuid_has_osvw(vcpu))
2073 return 1;
2074 data = vcpu->arch.osvw.status;
2075 break;
15c4a640 2076 default:
f5132b01
GN		 2077 if (kvm_pmu_msr(vcpu, msr))
2078 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2079 if (!ignore_msrs) {
a737f256 2080 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2081 return 1;
2082 } else {
a737f256 2083 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2084 data = 0;
2085 }
2086 break;
15c4a640
CO		 2087 }
2088 *pdata = data;
2089 return 0;
2090}
2091EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2092
313a3dc7
CO		 2093/*
2094 * Read or write a bunch of msrs. All parameters are kernel addresses.
2095 *
2096 * @return number of msrs set successfully.
2097 */
2098static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2099 struct kvm_msr_entry *entries,
2100 int (*do_msr)(struct kvm_vcpu *vcpu,
2101 unsigned index, u64 *data))
2102{
f656ce01 2103 int i, idx;
313a3dc7 2104
f656ce01 2105 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2106 for (i = 0; i < msrs->nmsrs; ++i)
2107 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2108 break;
f656ce01 2109 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2110
313a3dc7
CO		 2111 return i;
2112}
2113
2114/*
2115 * Read or write a bunch of msrs. Parameters are user addresses.
2116 *
2117 * @return number of msrs set successfully.
2118 */
2119static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2120 int (*do_msr)(struct kvm_vcpu *vcpu,
2121 unsigned index, u64 *data),
2122 int writeback)
2123{
2124 struct kvm_msrs msrs;
2125 struct kvm_msr_entry *entries;
2126 int r, n;
2127 unsigned size;
2128
2129 r = -EFAULT;
2130 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2131 goto out;
2132
2133 r = -E2BIG;
2134 if (msrs.nmsrs >= MAX_IO_MSRS)
2135 goto out;
2136
313a3dc7 2137 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2138 entries = memdup_user(user_msrs->entries, size);
2139 if (IS_ERR(entries)) {
2140 r = PTR_ERR(entries);
313a3dc7 2141 goto out;
ff5c2c03 2142 }
313a3dc7
CO		 2143
2144 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2145 if (r < 0)
2146 goto out_free;
2147
2148 r = -EFAULT;
2149 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2150 goto out_free;
2151
2152 r = n;
2153
2154out_free:
7a73c028 2155 kfree(entries);
313a3dc7
CO		 2156out:
2157 return r;
2158}
2159
018d00d2
ZX		 2160int kvm_dev_ioctl_check_extension(long ext)
2161{
2162 int r;
2163
2164 switch (ext) {
2165 case KVM_CAP_IRQCHIP:
2166 case KVM_CAP_HLT:
2167 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2168 case KVM_CAP_SET_TSS_ADDR:
07716717 2169 case KVM_CAP_EXT_CPUID:
c8076604 2170 case KVM_CAP_CLOCKSOURCE:
7837699f 2171 case KVM_CAP_PIT:
a28e4f5a 2172 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2173 case KVM_CAP_MP_STATE:
ed848624 2174 case KVM_CAP_SYNC_MMU:
a355c85c 2175 case KVM_CAP_USER_NMI:
52d939a0 2176 case KVM_CAP_REINJECT_CONTROL:
4925663a 2177 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2178 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2179 case KVM_CAP_IRQFD:
d34e6b17 2180 case KVM_CAP_IOEVENTFD:
c5ff41ce 2181 case KVM_CAP_PIT2:
e9f42757 2182 case KVM_CAP_PIT_STATE2:
b927a3ce 2183 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2184 case KVM_CAP_XEN_HVM:
afbcf7ab 2185 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2186 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2187 case KVM_CAP_HYPERV:
10388a07 2188 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2189 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2190 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2191 case KVM_CAP_DEBUGREGS:
d2be1651 2192 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2193 case KVM_CAP_XSAVE:
344d9588 2194 case KVM_CAP_ASYNC_PF:
92a1f12d 2195 case KVM_CAP_GET_TSC_KHZ:
07700a94 2196 case KVM_CAP_PCI_2_3:
1c0b28c2 2197 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2198 case KVM_CAP_READONLY_MEM:
7a84428a 2199 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2200 r = 1;
2201 break;
542472b5
LV		 2202 case KVM_CAP_COALESCED_MMIO:
2203 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2204 break;
774ead3a
AK		 2205 case KVM_CAP_VAPIC:
2206 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2207 break;
f725230a 2208 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2209 r = KVM_SOFT_MAX_VCPUS;
2210 break;
2211 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2212 r = KVM_MAX_VCPUS;
2213 break;
a988b910
AK		 2214 case KVM_CAP_NR_MEMSLOTS:
2215 r = KVM_MEMORY_SLOTS;
2216 break;
a68a6a72
MT		 2217 case KVM_CAP_PV_MMU: /* obsolete */
2218 r = 0;
2f333bcb 2219 break;
62c476c7 2220 case KVM_CAP_IOMMU:
a1b60c1c 2221 r = iommu_present(&pci_bus_type);
62c476c7 2222 break;
890ca9ae
HY		 2223 case KVM_CAP_MCE:
2224 r = KVM_MAX_MCE_BANKS;
2225 break;
2d5b5a66
SY		 2226 case KVM_CAP_XCRS:
2227 r = cpu_has_xsave;
2228 break;
92a1f12d
JR		 2229 case KVM_CAP_TSC_CONTROL:
2230 r = kvm_has_tsc_control;
2231 break;
4d25a066
JK		 2232 case KVM_CAP_TSC_DEADLINE_TIMER:
2233 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2234 break;
018d00d2
ZX		 2235 default:
2236 r = 0;
2237 break;
2238 }
2239 return r;
2240
2241}
2242
043405e1
CO		 2243long kvm_arch_dev_ioctl(struct file *filp,
2244 unsigned int ioctl, unsigned long arg)
2245{
2246 void __user *argp = (void __user *)arg;
2247 long r;
2248
2249 switch (ioctl) {
2250 case KVM_GET_MSR_INDEX_LIST: {
2251 struct kvm_msr_list __user *user_msr_list = argp;
2252 struct kvm_msr_list msr_list;
2253 unsigned n;
2254
2255 r = -EFAULT;
2256 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2257 goto out;
2258 n = msr_list.nmsrs;
2259 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2260 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2261 goto out;
2262 r = -E2BIG;
e125e7b6 2263 if (n < msr_list.nmsrs)
043405e1
CO		 2264 goto out;
2265 r = -EFAULT;
2266 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2267 num_msrs_to_save * sizeof(u32)))
2268 goto out;
e125e7b6 2269 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2270 &emulated_msrs,
2271 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2272 goto out;
2273 r = 0;
2274 break;
2275 }
674eea0f
AK		 2276 case KVM_GET_SUPPORTED_CPUID: {
2277 struct kvm_cpuid2 __user *cpuid_arg = argp;
2278 struct kvm_cpuid2 cpuid;
2279
2280 r = -EFAULT;
2281 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2282 goto out;
2283 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2284 cpuid_arg->entries);
674eea0f
AK		 2285 if (r)
2286 goto out;
2287
2288 r = -EFAULT;
2289 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2290 goto out;
2291 r = 0;
2292 break;
2293 }
890ca9ae
HY		 2294 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2295 u64 mce_cap;
2296
2297 mce_cap = KVM_MCE_CAP_SUPPORTED;
2298 r = -EFAULT;
2299 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2300 goto out;
2301 r = 0;
2302 break;
2303 }
043405e1
CO		 2304 default:
2305 r = -EINVAL;
2306 }
2307out:
2308 return r;
2309}
2310
f5f48ee1
SY		 2311static void wbinvd_ipi(void *garbage)
2312{
2313 wbinvd();
2314}
2315
2316static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2317{
2318 return vcpu->kvm->arch.iommu_domain &&
2319 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2320}
2321
313a3dc7
CO		 2322void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2323{
f5f48ee1
SY		 2324 /* Address WBINVD may be executed by guest */
2325 if (need_emulate_wbinvd(vcpu)) {
2326 if (kvm_x86_ops->has_wbinvd_exit())
2327 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2328 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2329 smp_call_function_single(vcpu->cpu,
2330 wbinvd_ipi, NULL, 1);
2331 }
2332
313a3dc7 2333 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2334
0dd6a6ed
ZA		 2335 /* Apply any externally detected TSC adjustments (due to suspend) */
2336 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2337 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2338 vcpu->arch.tsc_offset_adjustment = 0;
2339 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2340 }
8f6055cb 2341
48434c20 2342 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2343 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2344 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2345 if (tsc_delta < 0)
2346 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2347 if (check_tsc_unstable()) {
b183aa58
ZA		 2348 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2349 vcpu->arch.last_guest_tsc);
2350 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2351 vcpu->arch.tsc_catchup = 1;
c285545f 2352 }
1aa8ceef 2353 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2354 if (vcpu->cpu != cpu)
2355 kvm_migrate_timers(vcpu);
e48672fa 2356 vcpu->cpu = cpu;
6b7d7e76 2357 }
c9aaa895
GC		 2358
2359 accumulate_steal_time(vcpu);
2360 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2361}
2362
2363void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2364{
02daab21 2365 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2366 kvm_put_guest_fpu(vcpu);
6f526ec5 2367 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2368}
2369
313a3dc7
CO		 2370static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2371 struct kvm_lapic_state *s)
2372{
ad312c7c 2373 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2374
2375 return 0;
2376}
2377
2378static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2379 struct kvm_lapic_state *s)
2380{
64eb0620 2381 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2382 update_cr8_intercept(vcpu);
313a3dc7
CO		 2383
2384 return 0;
2385}
2386
f77bc6a4
ZX		 2387static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2388 struct kvm_interrupt *irq)
2389{
a50abc3b 2390 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2391 return -EINVAL;
2392 if (irqchip_in_kernel(vcpu->kvm))
2393 return -ENXIO;
f77bc6a4 2394
66fd3f7f 2395 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2396 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2397
f77bc6a4
ZX		 2398 return 0;
2399}
2400
c4abb7c9
JK		 2401static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2402{
c4abb7c9 2403 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2404
2405 return 0;
2406}
2407
b209749f
AK		 2408static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2409 struct kvm_tpr_access_ctl *tac)
2410{
2411 if (tac->flags)
2412 return -EINVAL;
2413 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2414 return 0;
2415}
2416
890ca9ae
HY		 2417static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2418 u64 mcg_cap)
2419{
2420 int r;
2421 unsigned bank_num = mcg_cap & 0xff, bank;
2422
2423 r = -EINVAL;
a9e38c3e 2424 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2425 goto out;
2426 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2427 goto out;
2428 r = 0;
2429 vcpu->arch.mcg_cap = mcg_cap;
2430 /* Init IA32_MCG_CTL to all 1s */
2431 if (mcg_cap & MCG_CTL_P)
2432 vcpu->arch.mcg_ctl = ~(u64)0;
2433 /* Init IA32_MCi_CTL to all 1s */
2434 for (bank = 0; bank < bank_num; bank++)
2435 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2436out:
2437 return r;
2438}
2439
2440static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2441 struct kvm_x86_mce *mce)
2442{
2443 u64 mcg_cap = vcpu->arch.mcg_cap;
2444 unsigned bank_num = mcg_cap & 0xff;
2445 u64 *banks = vcpu->arch.mce_banks;
2446
2447 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2448 return -EINVAL;
2449 /*
2450 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2451 * reporting is disabled
2452 */
2453 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2454 vcpu->arch.mcg_ctl != ~(u64)0)
2455 return 0;
2456 banks += 4 * mce->bank;
2457 /*
2458 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2459 * reporting is disabled for the bank
2460 */
2461 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2462 return 0;
2463 if (mce->status & MCI_STATUS_UC) {
2464 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2465 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2466 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2467 return 0;
2468 }
2469 if (banks[1] & MCI_STATUS_VAL)
2470 mce->status |= MCI_STATUS_OVER;
2471 banks[2] = mce->addr;
2472 banks[3] = mce->misc;
2473 vcpu->arch.mcg_status = mce->mcg_status;
2474 banks[1] = mce->status;
2475 kvm_queue_exception(vcpu, MC_VECTOR);
2476 } else if (!(banks[1] & MCI_STATUS_VAL)
2477 || !(banks[1] & MCI_STATUS_UC)) {
2478 if (banks[1] & MCI_STATUS_VAL)
2479 mce->status |= MCI_STATUS_OVER;
2480 banks[2] = mce->addr;
2481 banks[3] = mce->misc;
2482 banks[1] = mce->status;
2483 } else
2484 banks[1] |= MCI_STATUS_OVER;
2485 return 0;
2486}
2487
3cfc3092
JK		 2488static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2489 struct kvm_vcpu_events *events)
2490{
7460fb4a 2491 process_nmi(vcpu);
03b82a30
JK		 2492 events->exception.injected =
2493 vcpu->arch.exception.pending &&
2494 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2495 events->exception.nr = vcpu->arch.exception.nr;
2496 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2497 events->exception.pad = 0;
3cfc3092
JK		 2498 events->exception.error_code = vcpu->arch.exception.error_code;
2499
03b82a30
JK		 2500 events->interrupt.injected =
2501 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2502 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2503 events->interrupt.soft = 0;
48005f64
JK		 2504 events->interrupt.shadow =
2505 kvm_x86_ops->get_interrupt_shadow(vcpu,
2506 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2507
2508 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2509 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2510 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2511 events->nmi.pad = 0;
3cfc3092
JK		 2512
2513 events->sipi_vector = vcpu->arch.sipi_vector;
2514
dab4b911 2515 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2516 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2517 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2518 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2519}
2520
2521static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2522 struct kvm_vcpu_events *events)
2523{
dab4b911 2524 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2525 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2526 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2527 return -EINVAL;
2528
7460fb4a 2529 process_nmi(vcpu);
3cfc3092
JK		 2530 vcpu->arch.exception.pending = events->exception.injected;
2531 vcpu->arch.exception.nr = events->exception.nr;
2532 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2533 vcpu->arch.exception.error_code = events->exception.error_code;
2534
2535 vcpu->arch.interrupt.pending = events->interrupt.injected;
2536 vcpu->arch.interrupt.nr = events->interrupt.nr;
2537 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2538 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2539 kvm_x86_ops->set_interrupt_shadow(vcpu,
2540 events->interrupt.shadow);
3cfc3092
JK		 2541
2542 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2543 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2544 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2545 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2546
dab4b911
JK		 2547 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2548 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2549
3842d135
AK		 2550 kvm_make_request(KVM_REQ_EVENT, vcpu);
2551
3cfc3092
JK		 2552 return 0;
2553}
2554
a1efbe77
JK		 2555static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2556 struct kvm_debugregs *dbgregs)
2557{
a1efbe77
JK		 2558 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2559 dbgregs->dr6 = vcpu->arch.dr6;
2560 dbgregs->dr7 = vcpu->arch.dr7;
2561 dbgregs->flags = 0;
97e69aa6 2562 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2563}
2564
2565static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2566 struct kvm_debugregs *dbgregs)
2567{
2568 if (dbgregs->flags)
2569 return -EINVAL;
2570
a1efbe77
JK		 2571 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2572 vcpu->arch.dr6 = dbgregs->dr6;
2573 vcpu->arch.dr7 = dbgregs->dr7;
2574
a1efbe77
JK		 2575 return 0;
2576}
2577
2d5b5a66
SY		 2578static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2579 struct kvm_xsave *guest_xsave)
2580{
2581 if (cpu_has_xsave)
2582 memcpy(guest_xsave->region,
2583 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2584 xstate_size);
2d5b5a66
SY		 2585 else {
2586 memcpy(guest_xsave->region,
2587 &vcpu->arch.guest_fpu.state->fxsave,
2588 sizeof(struct i387_fxsave_struct));
2589 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2590 XSTATE_FPSSE;
2591 }
2592}
2593
2594static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2595 struct kvm_xsave *guest_xsave)
2596{
2597 u64 xstate_bv =
2598 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2599
2600 if (cpu_has_xsave)
2601 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2602 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2603 else {
2604 if (xstate_bv & ~XSTATE_FPSSE)
2605 return -EINVAL;
2606 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2607 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2608 }
2609 return 0;
2610}
2611
2612static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2613 struct kvm_xcrs *guest_xcrs)
2614{
2615 if (!cpu_has_xsave) {
2616 guest_xcrs->nr_xcrs = 0;
2617 return;
2618 }
2619
2620 guest_xcrs->nr_xcrs = 1;
2621 guest_xcrs->flags = 0;
2622 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2623 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2624}
2625
2626static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2627 struct kvm_xcrs *guest_xcrs)
2628{
2629 int i, r = 0;
2630
2631 if (!cpu_has_xsave)
2632 return -EINVAL;
2633
2634 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2635 return -EINVAL;
2636
2637 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2638 /* Only support XCR0 currently */
2639 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2640 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2641 guest_xcrs->xcrs[0].value);
2642 break;
2643 }
2644 if (r)
2645 r = -EINVAL;
2646 return r;
2647}
2648
1c0b28c2
EM		 2649/*
2650 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2651 * stopped by the hypervisor. This function will be called from the host only.
2652 * EINVAL is returned when the host attempts to set the flag for a guest that
2653 * does not support pv clocks.
2654 */
2655static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2656{
1c0b28c2
EM		 2657 if (!vcpu->arch.time_page)
2658 return -EINVAL;
51d59c6b 2659 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2660 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2661 return 0;
2662}
2663
313a3dc7
CO		 2664long kvm_arch_vcpu_ioctl(struct file *filp,
2665 unsigned int ioctl, unsigned long arg)
2666{
2667 struct kvm_vcpu *vcpu = filp->private_data;
2668 void __user *argp = (void __user *)arg;
2669 int r;
d1ac91d8
AK		 2670 union {
2671 struct kvm_lapic_state *lapic;
2672 struct kvm_xsave *xsave;
2673 struct kvm_xcrs *xcrs;
2674 void *buffer;
2675 } u;
2676
2677 u.buffer = NULL;
313a3dc7
CO		 2678 switch (ioctl) {
2679 case KVM_GET_LAPIC: {
2204ae3c
MT		 2680 r = -EINVAL;
2681 if (!vcpu->arch.apic)
2682 goto out;
d1ac91d8 2683 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2684
b772ff36 2685 r = -ENOMEM;
d1ac91d8 2686 if (!u.lapic)
b772ff36 2687 goto out;
d1ac91d8 2688 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2689 if (r)
2690 goto out;
2691 r = -EFAULT;
d1ac91d8 2692 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2693 goto out;
2694 r = 0;
2695 break;
2696 }
2697 case KVM_SET_LAPIC: {
2204ae3c
MT		 2698 if (!vcpu->arch.apic)
2699 goto out;
ff5c2c03 2700 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 2701 if (IS_ERR(u.lapic))
2702 return PTR_ERR(u.lapic);
ff5c2c03 2703
d1ac91d8 2704 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2705 break;
2706 }
f77bc6a4
ZX		 2707 case KVM_INTERRUPT: {
2708 struct kvm_interrupt irq;
2709
2710 r = -EFAULT;
2711 if (copy_from_user(&irq, argp, sizeof irq))
2712 goto out;
2713 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 2714 break;
2715 }
c4abb7c9
JK		 2716 case KVM_NMI: {
2717 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 2718 break;
2719 }
313a3dc7
CO		 2720 case KVM_SET_CPUID: {
2721 struct kvm_cpuid __user *cpuid_arg = argp;
2722 struct kvm_cpuid cpuid;
2723
2724 r = -EFAULT;
2725 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2726 goto out;
2727 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 2728 break;
2729 }
07716717
DK		 2730 case KVM_SET_CPUID2: {
2731 struct kvm_cpuid2 __user *cpuid_arg = argp;
2732 struct kvm_cpuid2 cpuid;
2733
2734 r = -EFAULT;
2735 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2736 goto out;
2737 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2738 cpuid_arg->entries);
07716717
DK		 2739 break;
2740 }
2741 case KVM_GET_CPUID2: {
2742 struct kvm_cpuid2 __user *cpuid_arg = argp;
2743 struct kvm_cpuid2 cpuid;
2744
2745 r = -EFAULT;
2746 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2747 goto out;
2748 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2749 cpuid_arg->entries);
07716717
DK		 2750 if (r)
2751 goto out;
2752 r = -EFAULT;
2753 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2754 goto out;
2755 r = 0;
2756 break;
2757 }
313a3dc7
CO		 2758 case KVM_GET_MSRS:
2759 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2760 break;
2761 case KVM_SET_MSRS:
2762 r = msr_io(vcpu, argp, do_set_msr, 0);
2763 break;
b209749f
AK		 2764 case KVM_TPR_ACCESS_REPORTING: {
2765 struct kvm_tpr_access_ctl tac;
2766
2767 r = -EFAULT;
2768 if (copy_from_user(&tac, argp, sizeof tac))
2769 goto out;
2770 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2771 if (r)
2772 goto out;
2773 r = -EFAULT;
2774 if (copy_to_user(argp, &tac, sizeof tac))
2775 goto out;
2776 r = 0;
2777 break;
2778 };
b93463aa
AK		 2779 case KVM_SET_VAPIC_ADDR: {
2780 struct kvm_vapic_addr va;
2781
2782 r = -EINVAL;
2783 if (!irqchip_in_kernel(vcpu->kvm))
2784 goto out;
2785 r = -EFAULT;
2786 if (copy_from_user(&va, argp, sizeof va))
2787 goto out;
2788 r = 0;
2789 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2790 break;
2791 }
890ca9ae
HY		 2792 case KVM_X86_SETUP_MCE: {
2793 u64 mcg_cap;
2794
2795 r = -EFAULT;
2796 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2797 goto out;
2798 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2799 break;
2800 }
2801 case KVM_X86_SET_MCE: {
2802 struct kvm_x86_mce mce;
2803
2804 r = -EFAULT;
2805 if (copy_from_user(&mce, argp, sizeof mce))
2806 goto out;
2807 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2808 break;
2809 }
3cfc3092
JK		 2810 case KVM_GET_VCPU_EVENTS: {
2811 struct kvm_vcpu_events events;
2812
2813 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2814
2815 r = -EFAULT;
2816 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2817 break;
2818 r = 0;
2819 break;
2820 }
2821 case KVM_SET_VCPU_EVENTS: {
2822 struct kvm_vcpu_events events;
2823
2824 r = -EFAULT;
2825 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2826 break;
2827
2828 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2829 break;
2830 }
a1efbe77
JK		 2831 case KVM_GET_DEBUGREGS: {
2832 struct kvm_debugregs dbgregs;
2833
2834 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2835
2836 r = -EFAULT;
2837 if (copy_to_user(argp, &dbgregs,
2838 sizeof(struct kvm_debugregs)))
2839 break;
2840 r = 0;
2841 break;
2842 }
2843 case KVM_SET_DEBUGREGS: {
2844 struct kvm_debugregs dbgregs;
2845
2846 r = -EFAULT;
2847 if (copy_from_user(&dbgregs, argp,
2848 sizeof(struct kvm_debugregs)))
2849 break;
2850
2851 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2852 break;
2853 }
2d5b5a66 2854 case KVM_GET_XSAVE: {
d1ac91d8 2855 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2856 r = -ENOMEM;
d1ac91d8 2857 if (!u.xsave)
2d5b5a66
SY		 2858 break;
2859
d1ac91d8 2860 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2861
2862 r = -EFAULT;
d1ac91d8 2863 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2864 break;
2865 r = 0;
2866 break;
2867 }
2868 case KVM_SET_XSAVE: {
ff5c2c03 2869 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 2870 if (IS_ERR(u.xsave))
2871 return PTR_ERR(u.xsave);
2d5b5a66 2872
d1ac91d8 2873 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2874 break;
2875 }
2876 case KVM_GET_XCRS: {
d1ac91d8 2877 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2878 r = -ENOMEM;
d1ac91d8 2879 if (!u.xcrs)
2d5b5a66
SY		 2880 break;
2881
d1ac91d8 2882 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2883
2884 r = -EFAULT;
d1ac91d8 2885 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2886 sizeof(struct kvm_xcrs)))
2887 break;
2888 r = 0;
2889 break;
2890 }
2891 case KVM_SET_XCRS: {
ff5c2c03 2892 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 2893 if (IS_ERR(u.xcrs))
2894 return PTR_ERR(u.xcrs);
2d5b5a66 2895
d1ac91d8 2896 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2897 break;
2898 }
92a1f12d
JR		 2899 case KVM_SET_TSC_KHZ: {
2900 u32 user_tsc_khz;
2901
2902 r = -EINVAL;
92a1f12d
JR		 2903 user_tsc_khz = (u32)arg;
2904
2905 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2906 goto out;
2907
cc578287
ZA		 2908 if (user_tsc_khz == 0)
2909 user_tsc_khz = tsc_khz;
2910
2911 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2912
2913 r = 0;
2914 goto out;
2915 }
2916 case KVM_GET_TSC_KHZ: {
cc578287 2917 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2918 goto out;
2919 }
1c0b28c2
EM		 2920 case KVM_KVMCLOCK_CTRL: {
2921 r = kvm_set_guest_paused(vcpu);
2922 goto out;
2923 }
313a3dc7
CO		 2924 default:
2925 r = -EINVAL;
2926 }
2927out:
d1ac91d8 2928 kfree(u.buffer);
313a3dc7
CO		 2929 return r;
2930}
2931
5b1c1493
CO		 2932int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2933{
2934 return VM_FAULT_SIGBUS;
2935}
2936
1fe779f8
CO		 2937static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2938{
2939 int ret;
2940
2941 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 2942 return -EINVAL;
1fe779f8
CO		 2943 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2944 return ret;
2945}
2946
b927a3ce
SY		 2947static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2948 u64 ident_addr)
2949{
2950 kvm->arch.ept_identity_map_addr = ident_addr;
2951 return 0;
2952}
2953
1fe779f8
CO		 2954static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2955 u32 kvm_nr_mmu_pages)
2956{
2957 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2958 return -EINVAL;
2959
79fac95e 2960 mutex_lock(&kvm->slots_lock);
7c8a83b7 2961 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2962
2963 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2964 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2965
7c8a83b7 2966 spin_unlock(&kvm->mmu_lock);
79fac95e 2967 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2968 return 0;
2969}
2970
2971static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2972{
39de71ec 2973 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2974}
2975
1fe779f8
CO		 2976static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2977{
2978 int r;
2979
2980 r = 0;
2981 switch (chip->chip_id) {
2982 case KVM_IRQCHIP_PIC_MASTER:
2983 memcpy(&chip->chip.pic,
2984 &pic_irqchip(kvm)->pics[0],
2985 sizeof(struct kvm_pic_state));
2986 break;
2987 case KVM_IRQCHIP_PIC_SLAVE:
2988 memcpy(&chip->chip.pic,
2989 &pic_irqchip(kvm)->pics[1],
2990 sizeof(struct kvm_pic_state));
2991 break;
2992 case KVM_IRQCHIP_IOAPIC:
eba0226b 2993 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2994 break;
2995 default:
2996 r = -EINVAL;
2997 break;
2998 }
2999 return r;
3000}
3001
3002static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3003{
3004 int r;
3005
3006 r = 0;
3007 switch (chip->chip_id) {
3008 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3009 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3010 memcpy(&pic_irqchip(kvm)->pics[0],
3011 &chip->chip.pic,
3012 sizeof(struct kvm_pic_state));
f4f51050 3013 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3014 break;
3015 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3016 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3017 memcpy(&pic_irqchip(kvm)->pics[1],
3018 &chip->chip.pic,
3019 sizeof(struct kvm_pic_state));
f4f51050 3020 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3021 break;
3022 case KVM_IRQCHIP_IOAPIC:
eba0226b 3023 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3024 break;
3025 default:
3026 r = -EINVAL;
3027 break;
3028 }
3029 kvm_pic_update_irq(pic_irqchip(kvm));
3030 return r;
3031}
3032
e0f63cb9
SY		 3033static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3034{
3035 int r = 0;
3036
894a9c55 3037 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3038 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3039 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3040 return r;
3041}
3042
3043static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3044{
3045 int r = 0;
3046
894a9c55 3047 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3048 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3049 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3050 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3051 return r;
3052}
3053
3054static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3055{
3056 int r = 0;
3057
3058 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3059 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3060 sizeof(ps->channels));
3061 ps->flags = kvm->arch.vpit->pit_state.flags;
3062 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3063 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3064 return r;
3065}
3066
3067static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3068{
3069 int r = 0, start = 0;
3070 u32 prev_legacy, cur_legacy;
3071 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3072 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3073 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3074 if (!prev_legacy && cur_legacy)
3075 start = 1;
3076 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3077 sizeof(kvm->arch.vpit->pit_state.channels));
3078 kvm->arch.vpit->pit_state.flags = ps->flags;
3079 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3080 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3081 return r;
3082}
3083
52d939a0
MT		 3084static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3085 struct kvm_reinject_control *control)
3086{
3087 if (!kvm->arch.vpit)
3088 return -ENXIO;
894a9c55 3089 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3090 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3091 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3092 return 0;
3093}
3094
95d4c16c 3095/**
60c34612
TY		 3096 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3097 * @kvm: kvm instance
3098 * @log: slot id and address to which we copy the log
95d4c16c 3099 *
60c34612
TY		 3100 * We need to keep it in mind that VCPU threads can write to the bitmap
3101 * concurrently. So, to avoid losing data, we keep the following order for
3102 * each bit:
95d4c16c 3103 *
60c34612
TY		 3104 * 1. Take a snapshot of the bit and clear it if needed.
3105 * 2. Write protect the corresponding page.
3106 * 3. Flush TLB's if needed.
3107 * 4. Copy the snapshot to the userspace.
95d4c16c 3108 *
60c34612
TY		 3109 * Between 2 and 3, the guest may write to the page using the remaining TLB
3110 * entry. This is not a problem because the page will be reported dirty at
3111 * step 4 using the snapshot taken before and step 3 ensures that successive
3112 * writes will be logged for the next call.
5bb064dc 3113 */
60c34612 3114int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3115{
7850ac54 3116 int r;
5bb064dc 3117 struct kvm_memory_slot *memslot;
60c34612
TY		 3118 unsigned long n, i;
3119 unsigned long *dirty_bitmap;
3120 unsigned long *dirty_bitmap_buffer;
3121 bool is_dirty = false;
5bb064dc 3122
79fac95e 3123 mutex_lock(&kvm->slots_lock);
5bb064dc 3124
b050b015
MT		 3125 r = -EINVAL;
3126 if (log->slot >= KVM_MEMORY_SLOTS)
3127 goto out;
3128
28a37544 3129 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3130
3131 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3132 r = -ENOENT;
60c34612 3133 if (!dirty_bitmap)
b050b015
MT		 3134 goto out;
3135
87bf6e7d 3136 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3137
60c34612
TY		 3138 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3139 memset(dirty_bitmap_buffer, 0, n);
b050b015 3140
60c34612 3141 spin_lock(&kvm->mmu_lock);
b050b015 3142
60c34612
TY		 3143 for (i = 0; i < n / sizeof(long); i++) {
3144 unsigned long mask;
3145 gfn_t offset;
cdfca7b3 3146
60c34612
TY		 3147 if (!dirty_bitmap[i])
3148 continue;
b050b015 3149
60c34612 3150 is_dirty = true;
914ebccd 3151
60c34612
TY		 3152 mask = xchg(&dirty_bitmap[i], 0);
3153 dirty_bitmap_buffer[i] = mask;
edde99ce 3154
60c34612
TY		 3155 offset = i * BITS_PER_LONG;
3156 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3157 }
60c34612
TY		 3158 if (is_dirty)
3159 kvm_flush_remote_tlbs(kvm);
3160
3161 spin_unlock(&kvm->mmu_lock);
3162
3163 r = -EFAULT;
3164 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3165 goto out;
b050b015 3166
5bb064dc
ZX		 3167 r = 0;
3168out:
79fac95e 3169 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3170 return r;
3171}
3172
23d43cf9
CD		 3173int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3174{
3175 if (!irqchip_in_kernel(kvm))
3176 return -ENXIO;
3177
3178 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3179 irq_event->irq, irq_event->level);
3180 return 0;
3181}
3182
1fe779f8
CO		 3183long kvm_arch_vm_ioctl(struct file *filp,
3184 unsigned int ioctl, unsigned long arg)
3185{
3186 struct kvm *kvm = filp->private_data;
3187 void __user *argp = (void __user *)arg;
367e1319 3188 int r = -ENOTTY;
f0d66275
DH		 3189 /*
3190 * This union makes it completely explicit to gcc-3.x
3191 * that these two variables' stack usage should be
3192 * combined, not added together.
3193 */
3194 union {
3195 struct kvm_pit_state ps;
e9f42757 3196 struct kvm_pit_state2 ps2;
c5ff41ce 3197 struct kvm_pit_config pit_config;
f0d66275 3198 } u;
1fe779f8
CO		 3199
3200 switch (ioctl) {
3201 case KVM_SET_TSS_ADDR:
3202 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3203 break;
b927a3ce
SY		 3204 case KVM_SET_IDENTITY_MAP_ADDR: {
3205 u64 ident_addr;
3206
3207 r = -EFAULT;
3208 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3209 goto out;
3210 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3211 break;
3212 }
1fe779f8
CO		 3213 case KVM_SET_NR_MMU_PAGES:
3214 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3215 break;
3216 case KVM_GET_NR_MMU_PAGES:
3217 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3218 break;
3ddea128
MT		 3219 case KVM_CREATE_IRQCHIP: {
3220 struct kvm_pic *vpic;
3221
3222 mutex_lock(&kvm->lock);
3223 r = -EEXIST;
3224 if (kvm->arch.vpic)
3225 goto create_irqchip_unlock;
3e515705
AK		 3226 r = -EINVAL;
3227 if (atomic_read(&kvm->online_vcpus))
3228 goto create_irqchip_unlock;
1fe779f8 3229 r = -ENOMEM;
3ddea128
MT		 3230 vpic = kvm_create_pic(kvm);
3231 if (vpic) {
1fe779f8
CO		 3232 r = kvm_ioapic_init(kvm);
3233 if (r) {
175504cd 3234 mutex_lock(&kvm->slots_lock);
72bb2fcd 3235 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3236 &vpic->dev_master);
3237 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3238 &vpic->dev_slave);
3239 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3240 &vpic->dev_eclr);
175504cd 3241 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3242 kfree(vpic);
3243 goto create_irqchip_unlock;
1fe779f8
CO		 3244 }
3245 } else
3ddea128
MT		 3246 goto create_irqchip_unlock;
3247 smp_wmb();
3248 kvm->arch.vpic = vpic;
3249 smp_wmb();
399ec807
AK		 3250 r = kvm_setup_default_irq_routing(kvm);
3251 if (r) {
175504cd 3252 mutex_lock(&kvm->slots_lock);
3ddea128 3253 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3254 kvm_ioapic_destroy(kvm);
3255 kvm_destroy_pic(kvm);
3ddea128 3256 mutex_unlock(&kvm->irq_lock);
175504cd 3257 mutex_unlock(&kvm->slots_lock);
399ec807 3258 }
3ddea128
MT		 3259 create_irqchip_unlock:
3260 mutex_unlock(&kvm->lock);
1fe779f8 3261 break;
3ddea128 3262 }
7837699f 3263 case KVM_CREATE_PIT:
c5ff41ce
JK		 3264 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3265 goto create_pit;
3266 case KVM_CREATE_PIT2:
3267 r = -EFAULT;
3268 if (copy_from_user(&u.pit_config, argp,
3269 sizeof(struct kvm_pit_config)))
3270 goto out;
3271 create_pit:
79fac95e 3272 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3273 r = -EEXIST;
3274 if (kvm->arch.vpit)
3275 goto create_pit_unlock;
7837699f 3276 r = -ENOMEM;
c5ff41ce 3277 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3278 if (kvm->arch.vpit)
3279 r = 0;
269e05e4 3280 create_pit_unlock:
79fac95e 3281 mutex_unlock(&kvm->slots_lock);
7837699f 3282 break;
1fe779f8
CO		 3283 case KVM_GET_IRQCHIP: {
3284 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3285 struct kvm_irqchip *chip;
1fe779f8 3286
ff5c2c03
SL		 3287 chip = memdup_user(argp, sizeof(*chip));
3288 if (IS_ERR(chip)) {
3289 r = PTR_ERR(chip);
1fe779f8 3290 goto out;
ff5c2c03
SL		 3291 }
3292
1fe779f8
CO		 3293 r = -ENXIO;
3294 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3295 goto get_irqchip_out;
3296 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3297 if (r)
f0d66275 3298 goto get_irqchip_out;
1fe779f8 3299 r = -EFAULT;
f0d66275
DH		 3300 if (copy_to_user(argp, chip, sizeof *chip))
3301 goto get_irqchip_out;
1fe779f8 3302 r = 0;
f0d66275
DH		 3303 get_irqchip_out:
3304 kfree(chip);
1fe779f8
CO		 3305 break;
3306 }
3307 case KVM_SET_IRQCHIP: {
3308 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3309 struct kvm_irqchip *chip;
1fe779f8 3310
ff5c2c03
SL		 3311 chip = memdup_user(argp, sizeof(*chip));
3312 if (IS_ERR(chip)) {
3313 r = PTR_ERR(chip);
1fe779f8 3314 goto out;
ff5c2c03
SL		 3315 }
3316
1fe779f8
CO		 3317 r = -ENXIO;
3318 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3319 goto set_irqchip_out;
3320 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3321 if (r)
f0d66275 3322 goto set_irqchip_out;
1fe779f8 3323 r = 0;
f0d66275
DH		 3324 set_irqchip_out:
3325 kfree(chip);
1fe779f8
CO		 3326 break;
3327 }
e0f63cb9 3328 case KVM_GET_PIT: {
e0f63cb9 3329 r = -EFAULT;
f0d66275 3330 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3331 goto out;
3332 r = -ENXIO;
3333 if (!kvm->arch.vpit)
3334 goto out;
f0d66275 3335 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3336 if (r)
3337 goto out;
3338 r = -EFAULT;
f0d66275 3339 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3340 goto out;
3341 r = 0;
3342 break;
3343 }
3344 case KVM_SET_PIT: {
e0f63cb9 3345 r = -EFAULT;
f0d66275 3346 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3347 goto out;
3348 r = -ENXIO;
3349 if (!kvm->arch.vpit)
3350 goto out;
f0d66275 3351 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3352 break;
3353 }
e9f42757
BK		 3354 case KVM_GET_PIT2: {
3355 r = -ENXIO;
3356 if (!kvm->arch.vpit)
3357 goto out;
3358 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3359 if (r)
3360 goto out;
3361 r = -EFAULT;
3362 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3363 goto out;
3364 r = 0;
3365 break;
3366 }
3367 case KVM_SET_PIT2: {
3368 r = -EFAULT;
3369 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3370 goto out;
3371 r = -ENXIO;
3372 if (!kvm->arch.vpit)
3373 goto out;
3374 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3375 break;
3376 }
52d939a0
MT		 3377 case KVM_REINJECT_CONTROL: {
3378 struct kvm_reinject_control control;
3379 r = -EFAULT;
3380 if (copy_from_user(&control, argp, sizeof(control)))
3381 goto out;
3382 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3383 break;
3384 }
ffde22ac
ES		 3385 case KVM_XEN_HVM_CONFIG: {
3386 r = -EFAULT;
3387 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3388 sizeof(struct kvm_xen_hvm_config)))
3389 goto out;
3390 r = -EINVAL;
3391 if (kvm->arch.xen_hvm_config.flags)
3392 goto out;
3393 r = 0;
3394 break;
3395 }
afbcf7ab 3396 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3397 struct kvm_clock_data user_ns;
3398 u64 now_ns;
3399 s64 delta;
3400
3401 r = -EFAULT;
3402 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3403 goto out;
3404
3405 r = -EINVAL;
3406 if (user_ns.flags)
3407 goto out;
3408
3409 r = 0;
395c6b0a 3410 local_irq_disable();
759379dd 3411 now_ns = get_kernel_ns();
afbcf7ab 3412 delta = user_ns.clock - now_ns;
395c6b0a 3413 local_irq_enable();
afbcf7ab
GC		 3414 kvm->arch.kvmclock_offset = delta;
3415 break;
3416 }
3417 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3418 struct kvm_clock_data user_ns;
3419 u64 now_ns;
3420
395c6b0a 3421 local_irq_disable();
759379dd 3422 now_ns = get_kernel_ns();
afbcf7ab 3423 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3424 local_irq_enable();
afbcf7ab 3425 user_ns.flags = 0;
97e69aa6 3426 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3427
3428 r = -EFAULT;
3429 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3430 goto out;
3431 r = 0;
3432 break;
3433 }
3434
1fe779f8
CO		 3435 default:
3436 ;
3437 }
3438out:
3439 return r;
3440}
3441
a16b043c 3442static void kvm_init_msr_list(void)
043405e1
CO		 3443{
3444 u32 dummy[2];
3445 unsigned i, j;
3446
e3267cbb
GC		 3447 /* skip the first msrs in the list. KVM-specific */
3448 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3449 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3450 continue;
3451 if (j < i)
3452 msrs_to_save[j] = msrs_to_save[i];
3453 j++;
3454 }
3455 num_msrs_to_save = j;
3456}
3457
bda9020e
MT		 3458static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3459 const void *v)
bbd9b64e 3460{
70252a10
AK		 3461 int handled = 0;
3462 int n;
3463
3464 do {
3465 n = min(len, 8);
3466 if (!(vcpu->arch.apic &&
3467 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3468 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3469 break;
3470 handled += n;
3471 addr += n;
3472 len -= n;
3473 v += n;
3474 } while (len);
bbd9b64e 3475
70252a10 3476 return handled;
bbd9b64e
CO		 3477}
3478
bda9020e 3479static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3480{
70252a10
AK		 3481 int handled = 0;
3482 int n;
3483
3484 do {
3485 n = min(len, 8);
3486 if (!(vcpu->arch.apic &&
3487 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3488 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3489 break;
3490 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3491 handled += n;
3492 addr += n;
3493 len -= n;
3494 v += n;
3495 } while (len);
bbd9b64e 3496
70252a10 3497 return handled;
bbd9b64e
CO		 3498}
3499
2dafc6c2
GN		 3500static void kvm_set_segment(struct kvm_vcpu *vcpu,
3501 struct kvm_segment *var, int seg)
3502{
3503 kvm_x86_ops->set_segment(vcpu, var, seg);
3504}
3505
3506void kvm_get_segment(struct kvm_vcpu *vcpu,
3507 struct kvm_segment *var, int seg)
3508{
3509 kvm_x86_ops->get_segment(vcpu, var, seg);
3510}
3511
e459e322 3512gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3513{
3514 gpa_t t_gpa;
ab9ae313 3515 struct x86_exception exception;
02f59dc9
JR		 3516
3517 BUG_ON(!mmu_is_nested(vcpu));
3518
3519 /* NPT walks are always user-walks */
3520 access |= PFERR_USER_MASK;
ab9ae313 3521 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3522
3523 return t_gpa;
3524}
3525
ab9ae313
AK		 3526gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3527 struct x86_exception *exception)
1871c602
GN		 3528{
3529 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3530 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3531}
3532
ab9ae313
AK		 3533 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3534 struct x86_exception *exception)
1871c602
GN		 3535{
3536 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3537 access |= PFERR_FETCH_MASK;
ab9ae313 3538 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3539}
3540
ab9ae313
AK		 3541gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3542 struct x86_exception *exception)
1871c602
GN		 3543{
3544 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3545 access |= PFERR_WRITE_MASK;
ab9ae313 3546 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3547}
3548
3549/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3550gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3551 struct x86_exception *exception)
1871c602 3552{
ab9ae313 3553 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3554}
3555
3556static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3557 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3558 struct x86_exception *exception)
bbd9b64e
CO		 3559{
3560 void *data = val;
10589a46 3561 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3562
3563 while (bytes) {
14dfe855 3564 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3565 exception);
bbd9b64e 3566 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3567 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3568 int ret;
3569
bcc55cba 3570 if (gpa == UNMAPPED_GVA)
ab9ae313 3571 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3572 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3573 if (ret < 0) {
c3cd7ffa 3574 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3575 goto out;
3576 }
bbd9b64e 3577
77c2002e
IE		 3578 bytes -= toread;
3579 data += toread;
3580 addr += toread;
bbd9b64e 3581 }
10589a46 3582out:
10589a46 3583 return r;
bbd9b64e 3584}
77c2002e 3585
1871c602 3586/* used for instruction fetching */
0f65dd70
AK		 3587static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3588 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3589 struct x86_exception *exception)
1871c602 3590{
0f65dd70 3591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3592 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3593
1871c602 3594 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3595 access | PFERR_FETCH_MASK,
3596 exception);
1871c602
GN		 3597}
3598
064aea77 3599int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3600 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3601 struct x86_exception *exception)
1871c602 3602{
0f65dd70 3603 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3604 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3605
1871c602 3606 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3607 exception);
1871c602 3608}
064aea77 3609EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3610
0f65dd70
AK		 3611static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3612 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3613 struct x86_exception *exception)
1871c602 3614{
0f65dd70 3615 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3616 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3617}
3618
6a4d7550 3619int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3620 gva_t addr, void *val,
2dafc6c2 3621 unsigned int bytes,
bcc55cba 3622 struct x86_exception *exception)
77c2002e 3623{
0f65dd70 3624 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3625 void *data = val;
3626 int r = X86EMUL_CONTINUE;
3627
3628 while (bytes) {
14dfe855
JR		 3629 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3630 PFERR_WRITE_MASK,
ab9ae313 3631 exception);
77c2002e
IE		 3632 unsigned offset = addr & (PAGE_SIZE-1);
3633 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3634 int ret;
3635
bcc55cba 3636 if (gpa == UNMAPPED_GVA)
ab9ae313 3637 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3638 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3639 if (ret < 0) {
c3cd7ffa 3640 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3641 goto out;
3642 }
3643
3644 bytes -= towrite;
3645 data += towrite;
3646 addr += towrite;
3647 }
3648out:
3649 return r;
3650}
6a4d7550 3651EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3652
af7cc7d1
XG		 3653static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3654 gpa_t *gpa, struct x86_exception *exception,
3655 bool write)
3656{
97d64b78
AK		 3657 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3658 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3659
97d64b78
AK		 3660 if (vcpu_match_mmio_gva(vcpu, gva)
3661 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3662 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3663 (gva & (PAGE_SIZE - 1));
4f022648 3664 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3665 return 1;
3666 }
3667
af7cc7d1
XG		 3668 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3669
3670 if (*gpa == UNMAPPED_GVA)
3671 return -1;
3672
3673 /* For APIC access vmexit */
3674 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3675 return 1;
3676
4f022648
XG		 3677 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3678 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3679 return 1;
4f022648 3680 }
bebb106a 3681
af7cc7d1
XG		 3682 return 0;
3683}
3684
3200f405 3685int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3686 const void *val, int bytes)
bbd9b64e
CO		 3687{
3688 int ret;
3689
3690 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3691 if (ret < 0)
bbd9b64e 3692 return 0;
f57f2ef5 3693 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3694 return 1;
3695}
3696
77d197b2
XG		 3697struct read_write_emulator_ops {
3698 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3699 int bytes);
3700 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3701 void *val, int bytes);
3702 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3703 int bytes, void *val);
3704 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3705 void *val, int bytes);
3706 bool write;
3707};
3708
3709static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3710{
3711 if (vcpu->mmio_read_completed) {
77d197b2 3712 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3713 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3714 vcpu->mmio_read_completed = 0;
3715 return 1;
3716 }
3717
3718 return 0;
3719}
3720
3721static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3722 void *val, int bytes)
3723{
3724 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3725}
3726
3727static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3728 void *val, int bytes)
3729{
3730 return emulator_write_phys(vcpu, gpa, val, bytes);
3731}
3732
3733static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3734{
3735 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3736 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3737}
3738
3739static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3740 void *val, int bytes)
3741{
3742 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3743 return X86EMUL_IO_NEEDED;
3744}
3745
3746static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3747 void *val, int bytes)
3748{
f78146b0
AK		 3749 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3750
3751 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 3752 return X86EMUL_CONTINUE;
3753}
3754
0fbe9b0b 3755static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 3756 .read_write_prepare = read_prepare,
3757 .read_write_emulate = read_emulate,
3758 .read_write_mmio = vcpu_mmio_read,
3759 .read_write_exit_mmio = read_exit_mmio,
3760};
3761
0fbe9b0b 3762static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 3763 .read_write_emulate = write_emulate,
3764 .read_write_mmio = write_mmio,
3765 .read_write_exit_mmio = write_exit_mmio,
3766 .write = true,
3767};
3768
22388a3c
XG		 3769static int emulator_read_write_onepage(unsigned long addr, void *val,
3770 unsigned int bytes,
3771 struct x86_exception *exception,
3772 struct kvm_vcpu *vcpu,
0fbe9b0b 3773 const struct read_write_emulator_ops *ops)
bbd9b64e 3774{
af7cc7d1
XG		 3775 gpa_t gpa;
3776 int handled, ret;
22388a3c 3777 bool write = ops->write;
f78146b0 3778 struct kvm_mmio_fragment *frag;
10589a46 3779
22388a3c 3780 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3781
af7cc7d1 3782 if (ret < 0)
bbd9b64e 3783 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3784
3785 /* For APIC access vmexit */
af7cc7d1 3786 if (ret)
bbd9b64e
CO		 3787 goto mmio;
3788
22388a3c 3789 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3790 return X86EMUL_CONTINUE;
3791
3792mmio:
3793 /*
3794 * Is this MMIO handled locally?
3795 */
22388a3c 3796 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3797 if (handled == bytes)
bbd9b64e 3798 return X86EMUL_CONTINUE;
bbd9b64e 3799
70252a10
AK		 3800 gpa += handled;
3801 bytes -= handled;
3802 val += handled;
3803
f78146b0
AK		 3804 while (bytes) {
3805 unsigned now = min(bytes, 8U);
bbd9b64e 3806
f78146b0
AK		 3807 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3808 frag->gpa = gpa;
3809 frag->data = val;
3810 frag->len = now;
3811
3812 gpa += now;
3813 val += now;
3814 bytes -= now;
3815 }
3816 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3817}
3818
22388a3c
XG		 3819int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3820 void *val, unsigned int bytes,
3821 struct x86_exception *exception,
0fbe9b0b 3822 const struct read_write_emulator_ops *ops)
bbd9b64e 3823{
0f65dd70 3824 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 3825 gpa_t gpa;
3826 int rc;
3827
3828 if (ops->read_write_prepare &&
3829 ops->read_write_prepare(vcpu, val, bytes))
3830 return X86EMUL_CONTINUE;
3831
3832 vcpu->mmio_nr_fragments = 0;
0f65dd70 3833
bbd9b64e
CO		 3834 /* Crossing a page boundary? */
3835 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 3836 int now;
bbd9b64e
CO		 3837
3838 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3839 rc = emulator_read_write_onepage(addr, val, now, exception,
3840 vcpu, ops);
3841
bbd9b64e
CO		 3842 if (rc != X86EMUL_CONTINUE)
3843 return rc;
3844 addr += now;
3845 val += now;
3846 bytes -= now;
3847 }
22388a3c 3848
f78146b0
AK		 3849 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3850 vcpu, ops);
3851 if (rc != X86EMUL_CONTINUE)
3852 return rc;
3853
3854 if (!vcpu->mmio_nr_fragments)
3855 return rc;
3856
3857 gpa = vcpu->mmio_fragments[0].gpa;
3858
3859 vcpu->mmio_needed = 1;
3860 vcpu->mmio_cur_fragment = 0;
3861
3862 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3863 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3864 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3865 vcpu->run->mmio.phys_addr = gpa;
3866
3867 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 3868}
3869
3870static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3871 unsigned long addr,
3872 void *val,
3873 unsigned int bytes,
3874 struct x86_exception *exception)
3875{
3876 return emulator_read_write(ctxt, addr, val, bytes,
3877 exception, &read_emultor);
3878}
3879
3880int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3881 unsigned long addr,
3882 const void *val,
3883 unsigned int bytes,
3884 struct x86_exception *exception)
3885{
3886 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3887 exception, &write_emultor);
bbd9b64e 3888}
bbd9b64e 3889
daea3e73
AK		 3890#define CMPXCHG_TYPE(t, ptr, old, new) \
3891 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3892
3893#ifdef CONFIG_X86_64
3894# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3895#else
3896# define CMPXCHG64(ptr, old, new) \
9749a6c0 3897 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3898#endif
3899
0f65dd70
AK		 3900static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3901 unsigned long addr,
bbd9b64e
CO		 3902 const void *old,
3903 const void *new,
3904 unsigned int bytes,
0f65dd70 3905 struct x86_exception *exception)
bbd9b64e 3906{
0f65dd70 3907 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3908 gpa_t gpa;
3909 struct page *page;
3910 char *kaddr;
3911 bool exchanged;
2bacc55c 3912
daea3e73
AK		 3913 /* guests cmpxchg8b have to be emulated atomically */
3914 if (bytes > 8 || (bytes & (bytes - 1)))
3915 goto emul_write;
10589a46 3916
daea3e73 3917 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3918
daea3e73
AK		 3919 if (gpa == UNMAPPED_GVA ||
3920 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3921 goto emul_write;
2bacc55c 3922
daea3e73
AK		 3923 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3924 goto emul_write;
72dc67a6 3925
daea3e73 3926 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 3927 if (is_error_page(page))
c19b8bd6 3928 goto emul_write;
72dc67a6 3929
8fd75e12 3930 kaddr = kmap_atomic(page);
daea3e73
AK		 3931 kaddr += offset_in_page(gpa);
3932 switch (bytes) {
3933 case 1:
3934 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3935 break;
3936 case 2:
3937 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3938 break;
3939 case 4:
3940 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3941 break;
3942 case 8:
3943 exchanged = CMPXCHG64(kaddr, old, new);
3944 break;
3945 default:
3946 BUG();
2bacc55c 3947 }
8fd75e12 3948 kunmap_atomic(kaddr);
daea3e73
AK		 3949 kvm_release_page_dirty(page);
3950
3951 if (!exchanged)
3952 return X86EMUL_CMPXCHG_FAILED;
3953
f57f2ef5 3954 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3955
3956 return X86EMUL_CONTINUE;
4a5f48f6 3957
3200f405 3958emul_write:
daea3e73 3959 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3960
0f65dd70 3961 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3962}
3963
cf8f70bf
GN		 3964static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3965{
3966 /* TODO: String I/O for in kernel device */
3967 int r;
3968
3969 if (vcpu->arch.pio.in)
3970 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3971 vcpu->arch.pio.size, pd);
3972 else
3973 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3974 vcpu->arch.pio.port, vcpu->arch.pio.size,
3975 pd);
3976 return r;
3977}
3978
6f6fbe98
XG		 3979static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3980 unsigned short port, void *val,
3981 unsigned int count, bool in)
cf8f70bf 3982{
6f6fbe98 3983 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3984
3985 vcpu->arch.pio.port = port;
6f6fbe98 3986 vcpu->arch.pio.in = in;
7972995b 3987 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3988 vcpu->arch.pio.size = size;
3989
3990 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3991 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3992 return 1;
3993 }
3994
3995 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3996 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3997 vcpu->run->io.size = size;
3998 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3999 vcpu->run->io.count = count;
4000 vcpu->run->io.port = port;
4001
4002 return 0;
4003}
4004
6f6fbe98
XG		 4005static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4006 int size, unsigned short port, void *val,
4007 unsigned int count)
cf8f70bf 4008{
ca1d4a9e 4009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4010 int ret;
ca1d4a9e 4011
6f6fbe98
XG		 4012 if (vcpu->arch.pio.count)
4013 goto data_avail;
cf8f70bf 4014
6f6fbe98
XG		 4015 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4016 if (ret) {
4017data_avail:
4018 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4019 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4020 return 1;
4021 }
4022
cf8f70bf
GN		 4023 return 0;
4024}
4025
6f6fbe98
XG		 4026static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4027 int size, unsigned short port,
4028 const void *val, unsigned int count)
4029{
4030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4031
4032 memcpy(vcpu->arch.pio_data, val, size * count);
4033 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4034}
4035
bbd9b64e
CO		 4036static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4037{
4038 return kvm_x86_ops->get_segment_base(vcpu, seg);
4039}
4040
3cb16fe7 4041static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4042{
3cb16fe7 4043 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4044}
4045
f5f48ee1
SY		 4046int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4047{
4048 if (!need_emulate_wbinvd(vcpu))
4049 return X86EMUL_CONTINUE;
4050
4051 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4052 int cpu = get_cpu();
4053
4054 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4055 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4056 wbinvd_ipi, NULL, 1);
2eec7343 4057 put_cpu();
f5f48ee1 4058 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4059 } else
4060 wbinvd();
f5f48ee1
SY		 4061 return X86EMUL_CONTINUE;
4062}
4063EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4064
bcaf5cc5
AK		 4065static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4066{
4067 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4068}
4069
717746e3 4070int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4071{
717746e3 4072 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4073}
4074
717746e3 4075int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4076{
338dbc97 4077
717746e3 4078 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4079}
4080
52a46617 4081static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4082{
52a46617 4083 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4084}
4085
717746e3 4086static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4087{
717746e3 4088 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4089 unsigned long value;
4090
4091 switch (cr) {
4092 case 0:
4093 value = kvm_read_cr0(vcpu);
4094 break;
4095 case 2:
4096 value = vcpu->arch.cr2;
4097 break;
4098 case 3:
9f8fe504 4099 value = kvm_read_cr3(vcpu);
52a46617
GN		 4100 break;
4101 case 4:
4102 value = kvm_read_cr4(vcpu);
4103 break;
4104 case 8:
4105 value = kvm_get_cr8(vcpu);
4106 break;
4107 default:
a737f256 4108 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4109 return 0;
4110 }
4111
4112 return value;
4113}
4114
717746e3 4115static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4116{
717746e3 4117 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4118 int res = 0;
4119
52a46617
GN		 4120 switch (cr) {
4121 case 0:
49a9b07e 4122 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4123 break;
4124 case 2:
4125 vcpu->arch.cr2 = val;
4126 break;
4127 case 3:
2390218b 4128 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4129 break;
4130 case 4:
a83b29c6 4131 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4132 break;
4133 case 8:
eea1cff9 4134 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4135 break;
4136 default:
a737f256 4137 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4138 res = -1;
52a46617 4139 }
0f12244f
GN		 4140
4141 return res;
52a46617
GN		 4142}
4143
4cee4798
KW		 4144static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4145{
4146 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4147}
4148
717746e3 4149static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4150{
717746e3 4151 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4152}
4153
4bff1e86 4154static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4155{
4bff1e86 4156 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4157}
4158
4bff1e86 4159static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4160{
4bff1e86 4161 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4162}
4163
1ac9d0cf
AK		 4164static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4165{
4166 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4167}
4168
4169static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4170{
4171 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4172}
4173
4bff1e86
AK		 4174static unsigned long emulator_get_cached_segment_base(
4175 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4176{
4bff1e86 4177 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4178}
4179
1aa36616
AK		 4180static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4181 struct desc_struct *desc, u32 *base3,
4182 int seg)
2dafc6c2
GN		 4183{
4184 struct kvm_segment var;
4185
4bff1e86 4186 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4187 *selector = var.selector;
2dafc6c2
GN		 4188
4189 if (var.unusable)
4190 return false;
4191
4192 if (var.g)
4193 var.limit >>= 12;
4194 set_desc_limit(desc, var.limit);
4195 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4196#ifdef CONFIG_X86_64
4197 if (base3)
4198 *base3 = var.base >> 32;
4199#endif
2dafc6c2
GN		 4200 desc->type = var.type;
4201 desc->s = var.s;
4202 desc->dpl = var.dpl;
4203 desc->p = var.present;
4204 desc->avl = var.avl;
4205 desc->l = var.l;
4206 desc->d = var.db;
4207 desc->g = var.g;
4208
4209 return true;
4210}
4211
1aa36616
AK		 4212static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4213 struct desc_struct *desc, u32 base3,
4214 int seg)
2dafc6c2 4215{
4bff1e86 4216 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4217 struct kvm_segment var;
4218
1aa36616 4219 var.selector = selector;
2dafc6c2 4220 var.base = get_desc_base(desc);
5601d05b
GN		 4221#ifdef CONFIG_X86_64
4222 var.base |= ((u64)base3) << 32;
4223#endif
2dafc6c2
GN		 4224 var.limit = get_desc_limit(desc);
4225 if (desc->g)
4226 var.limit = (var.limit << 12) | 0xfff;
4227 var.type = desc->type;
4228 var.present = desc->p;
4229 var.dpl = desc->dpl;
4230 var.db = desc->d;
4231 var.s = desc->s;
4232 var.l = desc->l;
4233 var.g = desc->g;
4234 var.avl = desc->avl;
4235 var.present = desc->p;
4236 var.unusable = !var.present;
4237 var.padding = 0;
4238
4239 kvm_set_segment(vcpu, &var, seg);
4240 return;
4241}
4242
717746e3
AK		 4243static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4244 u32 msr_index, u64 *pdata)
4245{
4246 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4247}
4248
4249static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4250 u32 msr_index, u64 data)
4251{
4252 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4253}
4254
222d21aa
AK		 4255static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4256 u32 pmc, u64 *pdata)
4257{
4258 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4259}
4260
6c3287f7
AK		 4261static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4262{
4263 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4264}
4265
5037f6f3
AK		 4266static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4267{
4268 preempt_disable();
5197b808 4269 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4270 /*
4271 * CR0.TS may reference the host fpu state, not the guest fpu state,
4272 * so it may be clear at this point.
4273 */
4274 clts();
4275}
4276
4277static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4278{
4279 preempt_enable();
4280}
4281
2953538e 4282static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4283 struct x86_instruction_info *info,
c4f035c6
AK		 4284 enum x86_intercept_stage stage)
4285{
2953538e 4286 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4287}
4288
0017f93a 4289static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4290 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4291{
0017f93a 4292 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4293}
4294
dd856efa
AK		 4295static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4296{
4297 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4298}
4299
4300static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4301{
4302 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4303}
4304
0225fb50 4305static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4306 .read_gpr = emulator_read_gpr,
4307 .write_gpr = emulator_write_gpr,
1871c602 4308 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4309 .write_std = kvm_write_guest_virt_system,
1871c602 4310 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4311 .read_emulated = emulator_read_emulated,
4312 .write_emulated = emulator_write_emulated,
4313 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4314 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4315 .pio_in_emulated = emulator_pio_in_emulated,
4316 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4317 .get_segment = emulator_get_segment,
4318 .set_segment = emulator_set_segment,
5951c442 4319 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4320 .get_gdt = emulator_get_gdt,
160ce1f1 4321 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4322 .set_gdt = emulator_set_gdt,
4323 .set_idt = emulator_set_idt,
52a46617
GN		 4324 .get_cr = emulator_get_cr,
4325 .set_cr = emulator_set_cr,
4cee4798 4326 .set_rflags = emulator_set_rflags,
9c537244 4327 .cpl = emulator_get_cpl,
35aa5375
GN		 4328 .get_dr = emulator_get_dr,
4329 .set_dr = emulator_set_dr,
717746e3
AK		 4330 .set_msr = emulator_set_msr,
4331 .get_msr = emulator_get_msr,
222d21aa 4332 .read_pmc = emulator_read_pmc,
6c3287f7 4333 .halt = emulator_halt,
bcaf5cc5 4334 .wbinvd = emulator_wbinvd,
d6aa1000 4335 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4336 .get_fpu = emulator_get_fpu,
4337 .put_fpu = emulator_put_fpu,
c4f035c6 4338 .intercept = emulator_intercept,
bdb42f5a 4339 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4340};
4341
95cb2295
GN		 4342static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4343{
4344 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4345 /*
4346 * an sti; sti; sequence only disable interrupts for the first
4347 * instruction. So, if the last instruction, be it emulated or
4348 * not, left the system with the INT_STI flag enabled, it
4349 * means that the last instruction is an sti. We should not
4350 * leave the flag on in this case. The same goes for mov ss
4351 */
4352 if (!(int_shadow & mask))
4353 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4354}
4355
54b8486f
GN		 4356static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4357{
4358 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4359 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4360 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4361 else if (ctxt->exception.error_code_valid)
4362 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4363 ctxt->exception.error_code);
54b8486f 4364 else
da9cb575 4365 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4366}
4367
dd856efa 4368static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4369{
9dac77fa 4370 memset(&ctxt->twobyte, 0,
dd856efa 4371 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4372
9dac77fa
AK		 4373 ctxt->fetch.start = 0;
4374 ctxt->fetch.end = 0;
4375 ctxt->io_read.pos = 0;
4376 ctxt->io_read.end = 0;
4377 ctxt->mem_read.pos = 0;
4378 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4379}
4380
8ec4722d
MG		 4381static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4382{
adf52235 4383 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4384 int cs_db, cs_l;
4385
8ec4722d
MG		 4386 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4387
adf52235
TY		 4388 ctxt->eflags = kvm_get_rflags(vcpu);
4389 ctxt->eip = kvm_rip_read(vcpu);
4390 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4391 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4392 cs_l ? X86EMUL_MODE_PROT64 :
4393 cs_db ? X86EMUL_MODE_PROT32 :
4394 X86EMUL_MODE_PROT16;
4395 ctxt->guest_mode = is_guest_mode(vcpu);
4396
dd856efa 4397 init_decode_cache(ctxt);
7ae441ea 4398 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4399}
4400
71f9833b 4401int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4402{
9d74191a 4403 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4404 int ret;
4405
4406 init_emulate_ctxt(vcpu);
4407
9dac77fa
AK		 4408 ctxt->op_bytes = 2;
4409 ctxt->ad_bytes = 2;
4410 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4411 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4412
4413 if (ret != X86EMUL_CONTINUE)
4414 return EMULATE_FAIL;
4415
9dac77fa 4416 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4417 kvm_rip_write(vcpu, ctxt->eip);
4418 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4419
4420 if (irq == NMI_VECTOR)
7460fb4a 4421 vcpu->arch.nmi_pending = 0;
63995653
MG		 4422 else
4423 vcpu->arch.interrupt.pending = false;
4424
4425 return EMULATE_DONE;
4426}
4427EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4428
6d77dbfc
GN		 4429static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4430{
fc3a9157
JR		 4431 int r = EMULATE_DONE;
4432
6d77dbfc
GN		 4433 ++vcpu->stat.insn_emulation_fail;
4434 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4435 if (!is_guest_mode(vcpu)) {
4436 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4437 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4438 vcpu->run->internal.ndata = 0;
4439 r = EMULATE_FAIL;
4440 }
6d77dbfc 4441 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4442
4443 return r;
6d77dbfc
GN		 4444}
4445
a6f177ef
GN		 4446static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4447{
4448 gpa_t gpa;
8e3d9d06 4449 pfn_t pfn;
a6f177ef 4450
68be0803
GN		 4451 if (tdp_enabled)
4452 return false;
4453
a6f177ef
GN		 4454 /*
4455 * if emulation was due to access to shadowed page table
4a969980 4456 * and it failed try to unshadow page and re-enter the
a6f177ef
GN		 4457 * guest to let CPU execute the instruction.
4458 */
4459 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4460 return true;
4461
4462 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4463
4464 if (gpa == UNMAPPED_GVA)
4465 return true; /* let cpu generate fault */
4466
8e3d9d06
XG		 4467 /*
4468 * Do not retry the unhandleable instruction if it faults on the
4469 * readonly host memory, otherwise it will goto a infinite loop:
4470 * retry instruction -> write #PF -> emulation fail -> retry
4471 * instruction -> ...
4472 */
4473 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
81c52c56 4474 if (!is_error_noslot_pfn(pfn)) {
8e3d9d06 4475 kvm_release_pfn_clean(pfn);
a6f177ef 4476 return true;
8e3d9d06 4477 }
a6f177ef
GN		 4478
4479 return false;
4480}
4481
1cb3f3ae
XG		 4482static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4483 unsigned long cr2, int emulation_type)
4484{
4485 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4486 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4487
4488 last_retry_eip = vcpu->arch.last_retry_eip;
4489 last_retry_addr = vcpu->arch.last_retry_addr;
4490
4491 /*
4492 * If the emulation is caused by #PF and it is non-page_table
4493 * writing instruction, it means the VM-EXIT is caused by shadow
4494 * page protected, we can zap the shadow page and retry this
4495 * instruction directly.
4496 *
4497 * Note: if the guest uses a non-page-table modifying instruction
4498 * on the PDE that points to the instruction, then we will unmap
4499 * the instruction and go to an infinite loop. So, we cache the
4500 * last retried eip and the last fault address, if we meet the eip
4501 * and the address again, we can break out of the potential infinite
4502 * loop.
4503 */
4504 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4505
4506 if (!(emulation_type & EMULTYPE_RETRY))
4507 return false;
4508
4509 if (x86_page_table_writing_insn(ctxt))
4510 return false;
4511
4512 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4513 return false;
4514
4515 vcpu->arch.last_retry_eip = ctxt->eip;
4516 vcpu->arch.last_retry_addr = cr2;
4517
4518 if (!vcpu->arch.mmu.direct_map)
4519 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4520
4521 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4522
4523 return true;
4524}
4525
716d51ab
GN		 4526static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4527static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4528
51d8b661
AP		 4529int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4530 unsigned long cr2,
dc25e89e
AP		 4531 int emulation_type,
4532 void *insn,
4533 int insn_len)
bbd9b64e 4534{
95cb2295 4535 int r;
9d74191a 4536 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4537 bool writeback = true;
bbd9b64e 4538
26eef70c 4539 kvm_clear_exception_queue(vcpu);
8d7d8102 4540
571008da 4541 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4542 init_emulate_ctxt(vcpu);
9d74191a
TY		 4543 ctxt->interruptibility = 0;
4544 ctxt->have_exception = false;
4545 ctxt->perm_ok = false;
bbd9b64e 4546
9d74191a 4547 ctxt->only_vendor_specific_insn
4005996e
AK		 4548 = emulation_type & EMULTYPE_TRAP_UD;
4549
9d74191a 4550 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4551
e46479f8 4552 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4553 ++vcpu->stat.insn_emulation;
1d2887e2 4554 if (r != EMULATION_OK) {
4005996e
AK		 4555 if (emulation_type & EMULTYPE_TRAP_UD)
4556 return EMULATE_FAIL;
a6f177ef 4557 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4558 return EMULATE_DONE;
6d77dbfc
GN		 4559 if (emulation_type & EMULTYPE_SKIP)
4560 return EMULATE_FAIL;
4561 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4562 }
4563 }
4564
ba8afb6b 4565 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4566 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4567 return EMULATE_DONE;
4568 }
4569
1cb3f3ae
XG		 4570 if (retry_instruction(ctxt, cr2, emulation_type))
4571 return EMULATE_DONE;
4572
7ae441ea 4573 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4574 changes registers values during IO operation */
7ae441ea
GN		 4575 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4576 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4577 emulator_invalidate_register_cache(ctxt);
7ae441ea 4578 }
4d2179e1 4579
5cd21917 4580restart:
9d74191a 4581 r = x86_emulate_insn(ctxt);
bbd9b64e 4582
775fde86
JR		 4583 if (r == EMULATION_INTERCEPTED)
4584 return EMULATE_DONE;
4585
d2ddd1c4 4586 if (r == EMULATION_FAILED) {
a6f177ef 4587 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4588 return EMULATE_DONE;
4589
6d77dbfc 4590 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4591 }
4592
9d74191a 4593 if (ctxt->have_exception) {
54b8486f 4594 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4595 r = EMULATE_DONE;
4596 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4597 if (!vcpu->arch.pio.in)
4598 vcpu->arch.pio.count = 0;
716d51ab 4599 else {
7ae441ea 4600 writeback = false;
716d51ab
GN		 4601 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4602 }
e85d28f8 4603 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4604 } else if (vcpu->mmio_needed) {
4605 if (!vcpu->mmio_is_write)
4606 writeback = false;
e85d28f8 4607 r = EMULATE_DO_MMIO;
716d51ab 4608 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4609 } else if (r == EMULATION_RESTART)
5cd21917 4610 goto restart;
d2ddd1c4
GN		 4611 else
4612 r = EMULATE_DONE;
f850e2e6 4613
7ae441ea 4614 if (writeback) {
9d74191a
TY		 4615 toggle_interruptibility(vcpu, ctxt->interruptibility);
4616 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4617 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4618 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4619 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4620 } else
4621 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4622
4623 return r;
de7d789a 4624}
51d8b661 4625EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4626
cf8f70bf 4627int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4628{
cf8f70bf 4629 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4630 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4631 size, port, &val, 1);
cf8f70bf 4632 /* do not return to emulator after return from userspace */
7972995b 4633 vcpu->arch.pio.count = 0;
de7d789a
CO		 4634 return ret;
4635}
cf8f70bf 4636EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4637
8cfdc000
ZA		 4638static void tsc_bad(void *info)
4639{
0a3aee0d 4640 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4641}
4642
4643static void tsc_khz_changed(void *data)
c8076604 4644{
8cfdc000
ZA		 4645 struct cpufreq_freqs *freq = data;
4646 unsigned long khz = 0;
4647
4648 if (data)
4649 khz = freq->new;
4650 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4651 khz = cpufreq_quick_get(raw_smp_processor_id());
4652 if (!khz)
4653 khz = tsc_khz;
0a3aee0d 4654 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4655}
4656
c8076604
GH		 4657static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4658 void *data)
4659{
4660 struct cpufreq_freqs *freq = data;
4661 struct kvm *kvm;
4662 struct kvm_vcpu *vcpu;
4663 int i, send_ipi = 0;
4664
8cfdc000
ZA		 4665 /*
4666 * We allow guests to temporarily run on slowing clocks,
4667 * provided we notify them after, or to run on accelerating
4668 * clocks, provided we notify them before. Thus time never
4669 * goes backwards.
4670 *
4671 * However, we have a problem. We can't atomically update
4672 * the frequency of a given CPU from this function; it is
4673 * merely a notifier, which can be called from any CPU.
4674 * Changing the TSC frequency at arbitrary points in time
4675 * requires a recomputation of local variables related to
4676 * the TSC for each VCPU. We must flag these local variables
4677 * to be updated and be sure the update takes place with the
4678 * new frequency before any guests proceed.
4679 *
4680 * Unfortunately, the combination of hotplug CPU and frequency
4681 * change creates an intractable locking scenario; the order
4682 * of when these callouts happen is undefined with respect to
4683 * CPU hotplug, and they can race with each other. As such,
4684 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4685 * undefined; you can actually have a CPU frequency change take
4686 * place in between the computation of X and the setting of the
4687 * variable. To protect against this problem, all updates of
4688 * the per_cpu tsc_khz variable are done in an interrupt
4689 * protected IPI, and all callers wishing to update the value
4690 * must wait for a synchronous IPI to complete (which is trivial
4691 * if the caller is on the CPU already). This establishes the
4692 * necessary total order on variable updates.
4693 *
4694 * Note that because a guest time update may take place
4695 * anytime after the setting of the VCPU's request bit, the
4696 * correct TSC value must be set before the request. However,
4697 * to ensure the update actually makes it to any guest which
4698 * starts running in hardware virtualization between the set
4699 * and the acquisition of the spinlock, we must also ping the
4700 * CPU after setting the request bit.
4701 *
4702 */
4703
c8076604
GH		 4704 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4705 return 0;
4706 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4707 return 0;
8cfdc000
ZA		 4708
4709 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4710
e935b837 4711 raw_spin_lock(&kvm_lock);
c8076604 4712 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4713 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4714 if (vcpu->cpu != freq->cpu)
4715 continue;
c285545f 4716 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4717 if (vcpu->cpu != smp_processor_id())
8cfdc000 4718 send_ipi = 1;
c8076604
GH		 4719 }
4720 }
e935b837 4721 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4722
4723 if (freq->old < freq->new && send_ipi) {
4724 /*
4725 * We upscale the frequency. Must make the guest
4726 * doesn't see old kvmclock values while running with
4727 * the new frequency, otherwise we risk the guest sees
4728 * time go backwards.
4729 *
4730 * In case we update the frequency for another cpu
4731 * (which might be in guest context) send an interrupt
4732 * to kick the cpu out of guest context. Next time
4733 * guest context is entered kvmclock will be updated,
4734 * so the guest will not see stale values.
4735 */
8cfdc000 4736 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4737 }
4738 return 0;
4739}
4740
4741static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4742 .notifier_call = kvmclock_cpufreq_notifier
4743};
4744
4745static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4746 unsigned long action, void *hcpu)
4747{
4748 unsigned int cpu = (unsigned long)hcpu;
4749
4750 switch (action) {
4751 case CPU_ONLINE:
4752 case CPU_DOWN_FAILED:
4753 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4754 break;
4755 case CPU_DOWN_PREPARE:
4756 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4757 break;
4758 }
4759 return NOTIFY_OK;
4760}
4761
4762static struct notifier_block kvmclock_cpu_notifier_block = {
4763 .notifier_call = kvmclock_cpu_notifier,
4764 .priority = -INT_MAX
c8076604
GH		 4765};
4766
b820cc0c
ZA		 4767static void kvm_timer_init(void)
4768{
4769 int cpu;
4770
c285545f 4771 max_tsc_khz = tsc_khz;
8cfdc000 4772 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4773 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4774#ifdef CONFIG_CPU_FREQ
4775 struct cpufreq_policy policy;
4776 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4777 cpu = get_cpu();
4778 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4779 if (policy.cpuinfo.max_freq)
4780 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4781 put_cpu();
c285545f 4782#endif
b820cc0c
ZA		 4783 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4784 CPUFREQ_TRANSITION_NOTIFIER);
4785 }
c285545f 4786 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4787 for_each_online_cpu(cpu)
4788 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4789}
4790
ff9d07a0
ZY		 4791static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4792
f5132b01 4793int kvm_is_in_guest(void)
ff9d07a0 4794{
086c9855 4795 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4796}
4797
4798static int kvm_is_user_mode(void)
4799{
4800 int user_mode = 3;
dcf46b94 4801
086c9855
AS		 4802 if (__this_cpu_read(current_vcpu))
4803 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4804
ff9d07a0
ZY		 4805 return user_mode != 0;
4806}
4807
4808static unsigned long kvm_get_guest_ip(void)
4809{
4810 unsigned long ip = 0;
dcf46b94 4811
086c9855
AS		 4812 if (__this_cpu_read(current_vcpu))
4813 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4814
ff9d07a0
ZY		 4815 return ip;
4816}
4817
4818static struct perf_guest_info_callbacks kvm_guest_cbs = {
4819 .is_in_guest = kvm_is_in_guest,
4820 .is_user_mode = kvm_is_user_mode,
4821 .get_guest_ip = kvm_get_guest_ip,
4822};
4823
4824void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4825{
086c9855 4826 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4827}
4828EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4829
4830void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4831{
086c9855 4832 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4833}
4834EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4835
ce88decf
XG		 4836static void kvm_set_mmio_spte_mask(void)
4837{
4838 u64 mask;
4839 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4840
4841 /*
4842 * Set the reserved bits and the present bit of an paging-structure
4843 * entry to generate page fault with PFER.RSV = 1.
4844 */
4845 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4846 mask |= 1ull;
4847
4848#ifdef CONFIG_X86_64
4849 /*
4850 * If reserved bit is not supported, clear the present bit to disable
4851 * mmio page fault.
4852 */
4853 if (maxphyaddr == 52)
4854 mask &= ~1ull;
4855#endif
4856
4857 kvm_mmu_set_mmio_spte_mask(mask);
4858}
4859
f8c16bba 4860int kvm_arch_init(void *opaque)
043405e1 4861{
b820cc0c 4862 int r;
f8c16bba
ZX		 4863 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4864
f8c16bba
ZX		 4865 if (kvm_x86_ops) {
4866 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4867 r = -EEXIST;
4868 goto out;
f8c16bba
ZX		 4869 }
4870
4871 if (!ops->cpu_has_kvm_support()) {
4872 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4873 r = -EOPNOTSUPP;
4874 goto out;
f8c16bba
ZX		 4875 }
4876 if (ops->disabled_by_bios()) {
4877 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4878 r = -EOPNOTSUPP;
4879 goto out;
f8c16bba
ZX		 4880 }
4881
97db56ce
AK		 4882 r = kvm_mmu_module_init();
4883 if (r)
4884 goto out;
4885
ce88decf 4886 kvm_set_mmio_spte_mask();
97db56ce
AK		 4887 kvm_init_msr_list();
4888
f8c16bba 4889 kvm_x86_ops = ops;
7b52345e 4890 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4891 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4892
b820cc0c 4893 kvm_timer_init();
c8076604 4894
ff9d07a0
ZY		 4895 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4896
2acf923e
DC		 4897 if (cpu_has_xsave)
4898 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4899
c5cc421b 4900 kvm_lapic_init();
f8c16bba 4901 return 0;
56c6d28a
ZX		 4902
4903out:
56c6d28a 4904 return r;
043405e1 4905}
8776e519 4906
f8c16bba
ZX		 4907void kvm_arch_exit(void)
4908{
ff9d07a0
ZY		 4909 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4910
888d256e
JK		 4911 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4912 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4913 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4914 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4915 kvm_x86_ops = NULL;
56c6d28a
ZX		 4916 kvm_mmu_module_exit();
4917}
f8c16bba 4918
8776e519
HB		 4919int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4920{
4921 ++vcpu->stat.halt_exits;
4922 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4923 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4924 return 1;
4925 } else {
4926 vcpu->run->exit_reason = KVM_EXIT_HLT;
4927 return 0;
4928 }
4929}
4930EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4931
55cd8e5a
GN		 4932int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4933{
4934 u64 param, ingpa, outgpa, ret;
4935 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4936 bool fast, longmode;
4937 int cs_db, cs_l;
4938
4939 /*
4940 * hypercall generates UD from non zero cpl and real mode
4941 * per HYPER-V spec
4942 */
3eeb3288 4943 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4944 kvm_queue_exception(vcpu, UD_VECTOR);
4945 return 0;
4946 }
4947
4948 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4949 longmode = is_long_mode(vcpu) && cs_l == 1;
4950
4951 if (!longmode) {
ccd46936
GN		 4952 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4953 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4954 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4955 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4956 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4957 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4958 }
4959#ifdef CONFIG_X86_64
4960 else {
4961 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4962 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4963 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4964 }
4965#endif
4966
4967 code = param & 0xffff;
4968 fast = (param >> 16) & 0x1;
4969 rep_cnt = (param >> 32) & 0xfff;
4970 rep_idx = (param >> 48) & 0xfff;
4971
4972 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4973
c25bc163
GN		 4974 switch (code) {
4975 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4976 kvm_vcpu_on_spin(vcpu);
4977 break;
4978 default:
4979 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4980 break;
4981 }
55cd8e5a
GN		 4982
4983 ret = res | (((u64)rep_done & 0xfff) << 32);
4984 if (longmode) {
4985 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4986 } else {
4987 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4988 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4989 }
4990
4991 return 1;
4992}
4993
8776e519
HB		 4994int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4995{
4996 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4997 int r = 1;
8776e519 4998
55cd8e5a
GN		 4999 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5000 return kvm_hv_hypercall(vcpu);
5001
5fdbf976
MT		 5002 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5003 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5004 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5005 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5006 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5007
229456fc 5008 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5009
8776e519
HB		 5010 if (!is_long_mode(vcpu)) {
5011 nr &= 0xFFFFFFFF;
5012 a0 &= 0xFFFFFFFF;
5013 a1 &= 0xFFFFFFFF;
5014 a2 &= 0xFFFFFFFF;
5015 a3 &= 0xFFFFFFFF;
5016 }
5017
07708c4a
JK		 5018 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5019 ret = -KVM_EPERM;
5020 goto out;
5021 }
5022
8776e519 5023 switch (nr) {
b93463aa
AK		 5024 case KVM_HC_VAPIC_POLL_IRQ:
5025 ret = 0;
5026 break;
8776e519
HB		 5027 default:
5028 ret = -KVM_ENOSYS;
5029 break;
5030 }
07708c4a 5031out:
5fdbf976 5032 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5033 ++vcpu->stat.hypercalls;
2f333bcb 5034 return r;
8776e519
HB		 5035}
5036EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5037
b6785def 5038static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5039{
d6aa1000 5040 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5041 char instruction[3];
5fdbf976 5042 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5043
8776e519
HB		 5044 /*
5045 * Blow out the MMU to ensure that no other VCPU has an active mapping
5046 * to ensure that the updated hypercall appears atomically across all
5047 * VCPUs.
5048 */
5049 kvm_mmu_zap_all(vcpu->kvm);
5050
8776e519 5051 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5052
9d74191a 5053 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5054}
5055
b6c7a5dc
HB		 5056/*
5057 * Check if userspace requested an interrupt window, and that the
5058 * interrupt window is open.
5059 *
5060 * No need to exit to userspace if we already have an interrupt queued.
5061 */
851ba692 5062static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5063{
8061823a 5064 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5065 vcpu->run->request_interrupt_window &&
5df56646 5066 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5067}
5068
851ba692 5069static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5070{
851ba692
AK		 5071 struct kvm_run *kvm_run = vcpu->run;
5072
91586a3b 5073 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5074 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5075 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5076 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5077 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5078 else
b6c7a5dc 5079 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5080 kvm_arch_interrupt_allowed(vcpu) &&
5081 !kvm_cpu_has_interrupt(vcpu) &&
5082 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5083}
5084
4484141a 5085static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5086{
5087 struct kvm_lapic *apic = vcpu->arch.apic;
5088 struct page *page;
5089
5090 if (!apic || !apic->vapic_addr)
4484141a 5091 return 0;
b93463aa
AK		 5092
5093 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5094 if (is_error_page(page))
5095 return -EFAULT;
72dc67a6
IE		 5096
5097 vcpu->arch.apic->vapic_page = page;
4484141a 5098 return 0;
b93463aa
AK		 5099}
5100
5101static void vapic_exit(struct kvm_vcpu *vcpu)
5102{
5103 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5104 int idx;
b93463aa
AK		 5105
5106 if (!apic || !apic->vapic_addr)
5107 return;
5108
f656ce01 5109 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5110 kvm_release_page_dirty(apic->vapic_page);
5111 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5112 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5113}
5114
95ba8273
GN		 5115static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5116{
5117 int max_irr, tpr;
5118
5119 if (!kvm_x86_ops->update_cr8_intercept)
5120 return;
5121
88c808fd
AK		 5122 if (!vcpu->arch.apic)
5123 return;
5124
8db3baa2
GN		 5125 if (!vcpu->arch.apic->vapic_addr)
5126 max_irr = kvm_lapic_find_highest_irr(vcpu);
5127 else
5128 max_irr = -1;
95ba8273
GN		 5129
5130 if (max_irr != -1)
5131 max_irr >>= 4;
5132
5133 tpr = kvm_lapic_get_cr8(vcpu);
5134
5135 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5136}
5137
851ba692 5138static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5139{
5140 /* try to reinject previous events if any */
b59bb7bd 5141 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5142 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5143 vcpu->arch.exception.has_error_code,
5144 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5145 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5146 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5147 vcpu->arch.exception.error_code,
5148 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5149 return;
5150 }
5151
95ba8273
GN		 5152 if (vcpu->arch.nmi_injected) {
5153 kvm_x86_ops->set_nmi(vcpu);
5154 return;
5155 }
5156
5157 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5158 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5159 return;
5160 }
5161
5162 /* try to inject new event if pending */
5163 if (vcpu->arch.nmi_pending) {
5164 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5165 --vcpu->arch.nmi_pending;
95ba8273
GN		 5166 vcpu->arch.nmi_injected = true;
5167 kvm_x86_ops->set_nmi(vcpu);
5168 }
5169 } else if (kvm_cpu_has_interrupt(vcpu)) {
5170 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5171 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5172 false);
5173 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5174 }
5175 }
5176}
5177
2acf923e
DC		 5178static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5179{
5180 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5181 !vcpu->guest_xcr0_loaded) {
5182 /* kvm_set_xcr() also depends on this */
5183 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5184 vcpu->guest_xcr0_loaded = 1;
5185 }
5186}
5187
5188static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5189{
5190 if (vcpu->guest_xcr0_loaded) {
5191 if (vcpu->arch.xcr0 != host_xcr0)
5192 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5193 vcpu->guest_xcr0_loaded = 0;
5194 }
5195}
5196
7460fb4a
AK		 5197static void process_nmi(struct kvm_vcpu *vcpu)
5198{
5199 unsigned limit = 2;
5200
5201 /*
5202 * x86 is limited to one NMI running, and one NMI pending after it.
5203 * If an NMI is already in progress, limit further NMIs to just one.
5204 * Otherwise, allow two (and we'll inject the first one immediately).
5205 */
5206 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5207 limit = 1;
5208
5209 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5210 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5211 kvm_make_request(KVM_REQ_EVENT, vcpu);
5212}
5213
851ba692 5214static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5215{
5216 int r;
6a8b1d13 5217 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5218 vcpu->run->request_interrupt_window;
d6185f20 5219 bool req_immediate_exit = 0;
b6c7a5dc 5220
3e007509 5221 if (vcpu->requests) {
a8eeb04a 5222 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5223 kvm_mmu_unload(vcpu);
a8eeb04a 5224 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5225 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5226 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5227 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5228 if (unlikely(r))
5229 goto out;
5230 }
a8eeb04a 5231 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5232 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5233 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5234 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5235 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5236 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5237 r = 0;
5238 goto out;
5239 }
a8eeb04a 5240 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5241 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5242 r = 0;
5243 goto out;
5244 }
a8eeb04a 5245 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5246 vcpu->fpu_active = 0;
5247 kvm_x86_ops->fpu_deactivate(vcpu);
5248 }
af585b92
GN		 5249 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5250 /* Page is swapped out. Do synthetic halt */
5251 vcpu->arch.apf.halted = true;
5252 r = 1;
5253 goto out;
5254 }
c9aaa895
GC		 5255 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5256 record_steal_time(vcpu);
7460fb4a
AK		 5257 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5258 process_nmi(vcpu);
d6185f20
NHE		 5259 req_immediate_exit =
5260 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5261 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5262 kvm_handle_pmu_event(vcpu);
5263 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5264 kvm_deliver_pmi(vcpu);
2f52d58c 5265 }
b93463aa 5266
b463a6f7
AK		 5267 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5268 inject_pending_event(vcpu);
5269
5270 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5271 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5272 kvm_x86_ops->enable_nmi_window(vcpu);
5273 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5274 kvm_x86_ops->enable_irq_window(vcpu);
5275
5276 if (kvm_lapic_enabled(vcpu)) {
5277 update_cr8_intercept(vcpu);
5278 kvm_lapic_sync_to_vapic(vcpu);
5279 }
5280 }
5281
d8368af8
AK		 5282 r = kvm_mmu_reload(vcpu);
5283 if (unlikely(r)) {
d905c069 5284 goto cancel_injection;
d8368af8
AK		 5285 }
5286
b6c7a5dc
HB		 5287 preempt_disable();
5288
5289 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5290 if (vcpu->fpu_active)
5291 kvm_load_guest_fpu(vcpu);
2acf923e 5292 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5293
6b7e2d09
XG		 5294 vcpu->mode = IN_GUEST_MODE;
5295
5296 /* We should set ->mode before check ->requests,
5297 * see the comment in make_all_cpus_request.
5298 */
5299 smp_mb();
b6c7a5dc 5300
d94e1dc9 5301 local_irq_disable();
32f88400 5302
6b7e2d09 5303 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5304 || need_resched() || signal_pending(current)) {
6b7e2d09 5305 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5306 smp_wmb();
6c142801
AK		 5307 local_irq_enable();
5308 preempt_enable();
5309 r = 1;
d905c069 5310 goto cancel_injection;
6c142801
AK		 5311 }
5312
f656ce01 5313 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5314
d6185f20
NHE		 5315 if (req_immediate_exit)
5316 smp_send_reschedule(vcpu->cpu);
5317
b6c7a5dc
HB		 5318 kvm_guest_enter();
5319
42dbaa5a 5320 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5321 set_debugreg(0, 7);
5322 set_debugreg(vcpu->arch.eff_db[0], 0);
5323 set_debugreg(vcpu->arch.eff_db[1], 1);
5324 set_debugreg(vcpu->arch.eff_db[2], 2);
5325 set_debugreg(vcpu->arch.eff_db[3], 3);
5326 }
b6c7a5dc 5327
229456fc 5328 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5329 kvm_x86_ops->run(vcpu);
b6c7a5dc 5330
24f1e32c
FW		 5331 /*
5332 * If the guest has used debug registers, at least dr7
5333 * will be disabled while returning to the host.
5334 * If we don't have active breakpoints in the host, we don't
5335 * care about the messed up debug address registers. But if
5336 * we have some of them active, restore the old state.
5337 */
59d8eb53 5338 if (hw_breakpoint_active())
24f1e32c 5339 hw_breakpoint_restore();
42dbaa5a 5340
886b470c
MT		 5341 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5342 native_read_tsc());
1d5f066e 5343
6b7e2d09 5344 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5345 smp_wmb();
b6c7a5dc
HB		 5346 local_irq_enable();
5347
5348 ++vcpu->stat.exits;
5349
5350 /*
5351 * We must have an instruction between local_irq_enable() and
5352 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5353 * the interrupt shadow. The stat.exits increment will do nicely.
5354 * But we need to prevent reordering, hence this barrier():
5355 */
5356 barrier();
5357
5358 kvm_guest_exit();
5359
5360 preempt_enable();
5361
f656ce01 5362 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5363
b6c7a5dc
HB		 5364 /*
5365 * Profile KVM exit RIPs:
5366 */
5367 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5368 unsigned long rip = kvm_rip_read(vcpu);
5369 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5370 }
5371
cc578287
ZA		 5372 if (unlikely(vcpu->arch.tsc_always_catchup))
5373 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5374
5cfb1d5a
MT		 5375 if (vcpu->arch.apic_attention)
5376 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5377
851ba692 5378 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5379 return r;
5380
5381cancel_injection:
5382 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5383 if (unlikely(vcpu->arch.apic_attention))
5384 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5385out:
5386 return r;
5387}
b6c7a5dc 5388
09cec754 5389
851ba692 5390static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5391{
5392 int r;
f656ce01 5393 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5394
5395 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5396 pr_debug("vcpu %d received sipi with vector # %x\n",
5397 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5398 kvm_lapic_reset(vcpu);
8b6e4547 5399 r = kvm_vcpu_reset(vcpu);
d7690175
MT		 5400 if (r)
5401 return r;
5402 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5403 }
5404
f656ce01 5405 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5406 r = vapic_enter(vcpu);
5407 if (r) {
5408 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5409 return r;
5410 }
d7690175
MT		 5411
5412 r = 1;
5413 while (r > 0) {
af585b92
GN		 5414 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5415 !vcpu->arch.apf.halted)
851ba692 5416 r = vcpu_enter_guest(vcpu);
d7690175 5417 else {
f656ce01 5418 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5419 kvm_vcpu_block(vcpu);
f656ce01 5420 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5421 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5422 {
5423 switch(vcpu->arch.mp_state) {
5424 case KVM_MP_STATE_HALTED:
d7690175 5425 vcpu->arch.mp_state =
09cec754
GN		 5426 KVM_MP_STATE_RUNNABLE;
5427 case KVM_MP_STATE_RUNNABLE:
af585b92 5428 vcpu->arch.apf.halted = false;
09cec754
GN		 5429 break;
5430 case KVM_MP_STATE_SIPI_RECEIVED:
5431 default:
5432 r = -EINTR;
5433 break;
5434 }
5435 }
d7690175
MT		 5436 }
5437
09cec754
GN		 5438 if (r <= 0)
5439 break;
5440
5441 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5442 if (kvm_cpu_has_pending_timer(vcpu))
5443 kvm_inject_pending_timer_irqs(vcpu);
5444
851ba692 5445 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5446 r = -EINTR;
851ba692 5447 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5448 ++vcpu->stat.request_irq_exits;
5449 }
af585b92
GN		 5450
5451 kvm_check_async_pf_completion(vcpu);
5452
09cec754
GN		 5453 if (signal_pending(current)) {
5454 r = -EINTR;
851ba692 5455 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5456 ++vcpu->stat.signal_exits;
5457 }
5458 if (need_resched()) {
f656ce01 5459 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5460 kvm_resched(vcpu);
f656ce01 5461 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5462 }
b6c7a5dc
HB		 5463 }
5464
f656ce01 5465 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5466
b93463aa
AK		 5467 vapic_exit(vcpu);
5468
b6c7a5dc
HB		 5469 return r;
5470}
5471
716d51ab
GN		 5472static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5473{
5474 int r;
5475 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5476 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5477 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5478 if (r != EMULATE_DONE)
5479 return 0;
5480 return 1;
5481}
5482
5483static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5484{
5485 BUG_ON(!vcpu->arch.pio.count);
5486
5487 return complete_emulated_io(vcpu);
5488}
5489
f78146b0
AK		 5490/*
5491 * Implements the following, as a state machine:
5492 *
5493 * read:
5494 * for each fragment
5495 * write gpa, len
5496 * exit
5497 * copy data
5498 * execute insn
5499 *
5500 * write:
5501 * for each fragment
5502 * write gpa, len
5503 * copy data
5504 * exit
5505 */
716d51ab 5506static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5507{
5508 struct kvm_run *run = vcpu->run;
f78146b0 5509 struct kvm_mmio_fragment *frag;
5287f194 5510
716d51ab 5511 BUG_ON(!vcpu->mmio_needed);
5287f194 5512
716d51ab
GN		 5513 /* Complete previous fragment */
5514 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5515 if (!vcpu->mmio_is_write)
5516 memcpy(frag->data, run->mmio.data, frag->len);
5517 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5518 vcpu->mmio_needed = 0;
cef4dea0 5519 if (vcpu->mmio_is_write)
716d51ab
GN		 5520 return 1;
5521 vcpu->mmio_read_completed = 1;
5522 return complete_emulated_io(vcpu);
5523 }
5524 /* Initiate next fragment */
5525 ++frag;
5526 run->exit_reason = KVM_EXIT_MMIO;
5527 run->mmio.phys_addr = frag->gpa;
5528 if (vcpu->mmio_is_write)
5529 memcpy(run->mmio.data, frag->data, frag->len);
5530 run->mmio.len = frag->len;
5531 run->mmio.is_write = vcpu->mmio_is_write;
5532 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5533 return 0;
5287f194
AK		 5534}
5535
716d51ab 5536
b6c7a5dc
HB		 5537int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5538{
5539 int r;
5540 sigset_t sigsaved;
5541
e5c30142
AK		 5542 if (!tsk_used_math(current) && init_fpu(current))
5543 return -ENOMEM;
5544
ac9f6dc0
AK		 5545 if (vcpu->sigset_active)
5546 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5547
a4535290 5548 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5549 kvm_vcpu_block(vcpu);
d7690175 5550 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5551 r = -EAGAIN;
5552 goto out;
b6c7a5dc
HB		 5553 }
5554
b6c7a5dc 5555 /* re-sync apic's tpr */
eea1cff9
AP		 5556 if (!irqchip_in_kernel(vcpu->kvm)) {
5557 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5558 r = -EINVAL;
5559 goto out;
5560 }
5561 }
b6c7a5dc 5562
716d51ab
GN		 5563 if (unlikely(vcpu->arch.complete_userspace_io)) {
5564 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
5565 vcpu->arch.complete_userspace_io = NULL;
5566 r = cui(vcpu);
5567 if (r <= 0)
5568 goto out;
5569 } else
5570 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 5571
851ba692 5572 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5573
5574out:
f1d86e46 5575 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5576 if (vcpu->sigset_active)
5577 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5578
b6c7a5dc
HB		 5579 return r;
5580}
5581
5582int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5583{
7ae441ea
GN		 5584 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5585 /*
5586 * We are here if userspace calls get_regs() in the middle of
5587 * instruction emulation. Registers state needs to be copied
4a969980 5588 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 5589 * that usually, but some bad designed PV devices (vmware
5590 * backdoor interface) need this to work
5591 */
dd856efa 5592 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 5593 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5594 }
5fdbf976
MT		 5595 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5596 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5597 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5598 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5599 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5600 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5601 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5602 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5603#ifdef CONFIG_X86_64
5fdbf976
MT		 5604 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5605 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5606 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5607 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5608 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5609 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5610 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5611 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5612#endif
5613
5fdbf976 5614 regs->rip = kvm_rip_read(vcpu);
91586a3b 5615 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5616
b6c7a5dc
HB		 5617 return 0;
5618}
5619
5620int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5621{
7ae441ea
GN		 5622 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5623 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5624
5fdbf976
MT		 5625 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5626 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5627 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5628 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5629 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5630 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5631 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5632 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5633#ifdef CONFIG_X86_64
5fdbf976
MT		 5634 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5635 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5636 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5637 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5638 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5639 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5640 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5641 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5642#endif
5643
5fdbf976 5644 kvm_rip_write(vcpu, regs->rip);
91586a3b 5645 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5646
b4f14abd
JK		 5647 vcpu->arch.exception.pending = false;
5648
3842d135
AK		 5649 kvm_make_request(KVM_REQ_EVENT, vcpu);
5650
b6c7a5dc
HB		 5651 return 0;
5652}
5653
b6c7a5dc
HB		 5654void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5655{
5656 struct kvm_segment cs;
5657
3e6e0aab 5658 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5659 *db = cs.db;
5660 *l = cs.l;
5661}
5662EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5663
5664int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5665 struct kvm_sregs *sregs)
5666{
89a27f4d 5667 struct desc_ptr dt;
b6c7a5dc 5668
3e6e0aab
GT		 5669 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5670 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5671 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5672 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5673 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5674 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5675
3e6e0aab
GT		 5676 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5677 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5678
5679 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5680 sregs->idt.limit = dt.size;
5681 sregs->idt.base = dt.address;
b6c7a5dc 5682 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5683 sregs->gdt.limit = dt.size;
5684 sregs->gdt.base = dt.address;
b6c7a5dc 5685
4d4ec087 5686 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5687 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5688 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5689 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5690 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5691 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5692 sregs->apic_base = kvm_get_apic_base(vcpu);
5693
923c61bb 5694 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5695
36752c9b 5696 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5697 set_bit(vcpu->arch.interrupt.nr,
5698 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5699
b6c7a5dc
HB		 5700 return 0;
5701}
5702
62d9f0db
MT		 5703int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5704 struct kvm_mp_state *mp_state)
5705{
62d9f0db 5706 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5707 return 0;
5708}
5709
5710int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5711 struct kvm_mp_state *mp_state)
5712{
62d9f0db 5713 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5714 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5715 return 0;
5716}
5717
7f3d35fd
KW		 5718int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5719 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5720{
9d74191a 5721 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5722 int ret;
e01c2426 5723
8ec4722d 5724 init_emulate_ctxt(vcpu);
c697518a 5725
7f3d35fd 5726 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5727 has_error_code, error_code);
c697518a 5728
c697518a 5729 if (ret)
19d04437 5730 return EMULATE_FAIL;
37817f29 5731
9d74191a
TY		 5732 kvm_rip_write(vcpu, ctxt->eip);
5733 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5734 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5735 return EMULATE_DONE;
37817f29
IE		 5736}
5737EXPORT_SYMBOL_GPL(kvm_task_switch);
5738
b6c7a5dc
HB		 5739int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5740 struct kvm_sregs *sregs)
5741{
5742 int mmu_reset_needed = 0;
63f42e02 5743 int pending_vec, max_bits, idx;
89a27f4d 5744 struct desc_ptr dt;
b6c7a5dc 5745
89a27f4d
GN		 5746 dt.size = sregs->idt.limit;
5747 dt.address = sregs->idt.base;
b6c7a5dc 5748 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5749 dt.size = sregs->gdt.limit;
5750 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5751 kvm_x86_ops->set_gdt(vcpu, &dt);
5752
ad312c7c 5753 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5754 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5755 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5756 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5757
2d3ad1f4 5758 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5759
f6801dff 5760 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5761 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5762 kvm_set_apic_base(vcpu, sregs->apic_base);
5763
4d4ec087 5764 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5765 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5766 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5767
fc78f519 5768 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5769 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5770 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5771 kvm_update_cpuid(vcpu);
63f42e02
XG		 5772
5773 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5774 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5775 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5776 mmu_reset_needed = 1;
5777 }
63f42e02 5778 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5779
5780 if (mmu_reset_needed)
5781 kvm_mmu_reset_context(vcpu);
5782
a50abc3b 5783 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 5784 pending_vec = find_first_bit(
5785 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5786 if (pending_vec < max_bits) {
66fd3f7f 5787 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5788 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5789 }
5790
3e6e0aab
GT		 5791 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5792 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5793 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5794 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5795 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5796 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5797
3e6e0aab
GT		 5798 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5799 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5800
5f0269f5
ME		 5801 update_cr8_intercept(vcpu);
5802
9c3e4aab 5803 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5804 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5805 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5806 !is_protmode(vcpu))
9c3e4aab
MT		 5807 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5808
3842d135
AK		 5809 kvm_make_request(KVM_REQ_EVENT, vcpu);
5810
b6c7a5dc
HB		 5811 return 0;
5812}
5813
d0bfb940
JK		 5814int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5815 struct kvm_guest_debug *dbg)
b6c7a5dc 5816{
355be0b9 5817 unsigned long rflags;
ae675ef0 5818 int i, r;
b6c7a5dc 5819
4f926bf2
JK		 5820 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5821 r = -EBUSY;
5822 if (vcpu->arch.exception.pending)
2122ff5e 5823 goto out;
4f926bf2
JK		 5824 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5825 kvm_queue_exception(vcpu, DB_VECTOR);
5826 else
5827 kvm_queue_exception(vcpu, BP_VECTOR);
5828 }
5829
91586a3b
JK		 5830 /*
5831 * Read rflags as long as potentially injected trace flags are still
5832 * filtered out.
5833 */
5834 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5835
5836 vcpu->guest_debug = dbg->control;
5837 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5838 vcpu->guest_debug = 0;
5839
5840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5841 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5842 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 5843 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 5844 } else {
5845 for (i = 0; i < KVM_NR_DB_REGS; i++)
5846 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 5847 }
c8639010 5848 kvm_update_dr7(vcpu);
ae675ef0 5849
f92653ee
JK		 5850 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5851 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5852 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5853
91586a3b
JK		 5854 /*
5855 * Trigger an rflags update that will inject or remove the trace
5856 * flags.
5857 */
5858 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5859
c8639010 5860 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 5861
4f926bf2 5862 r = 0;
d0bfb940 5863
2122ff5e 5864out:
b6c7a5dc
HB		 5865
5866 return r;
5867}
5868
8b006791
ZX		 5869/*
5870 * Translate a guest virtual address to a guest physical address.
5871 */
5872int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5873 struct kvm_translation *tr)
5874{
5875 unsigned long vaddr = tr->linear_address;
5876 gpa_t gpa;
f656ce01 5877 int idx;
8b006791 5878
f656ce01 5879 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5880 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5881 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5882 tr->physical_address = gpa;
5883 tr->valid = gpa != UNMAPPED_GVA;
5884 tr->writeable = 1;
5885 tr->usermode = 0;
8b006791
ZX		 5886
5887 return 0;
5888}
5889
d0752060
HB		 5890int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5891{
98918833
SY		 5892 struct i387_fxsave_struct *fxsave =
5893 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5894
d0752060
HB		 5895 memcpy(fpu->fpr, fxsave->st_space, 128);
5896 fpu->fcw = fxsave->cwd;
5897 fpu->fsw = fxsave->swd;
5898 fpu->ftwx = fxsave->twd;
5899 fpu->last_opcode = fxsave->fop;
5900 fpu->last_ip = fxsave->rip;
5901 fpu->last_dp = fxsave->rdp;
5902 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5903
d0752060
HB		 5904 return 0;
5905}
5906
5907int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5908{
98918833
SY		 5909 struct i387_fxsave_struct *fxsave =
5910 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5911
d0752060
HB		 5912 memcpy(fxsave->st_space, fpu->fpr, 128);
5913 fxsave->cwd = fpu->fcw;
5914 fxsave->swd = fpu->fsw;
5915 fxsave->twd = fpu->ftwx;
5916 fxsave->fop = fpu->last_opcode;
5917 fxsave->rip = fpu->last_ip;
5918 fxsave->rdp = fpu->last_dp;
5919 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5920
d0752060
HB		 5921 return 0;
5922}
5923
10ab25cd 5924int fx_init(struct kvm_vcpu *vcpu)
d0752060 5925{
10ab25cd
JK		 5926 int err;
5927
5928 err = fpu_alloc(&vcpu->arch.guest_fpu);
5929 if (err)
5930 return err;
5931
98918833 5932 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5933
2acf923e
DC		 5934 /*
5935 * Ensure guest xcr0 is valid for loading
5936 */
5937 vcpu->arch.xcr0 = XSTATE_FP;
5938
ad312c7c 5939 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5940
5941 return 0;
d0752060
HB		 5942}
5943EXPORT_SYMBOL_GPL(fx_init);
5944
98918833
SY		 5945static void fx_free(struct kvm_vcpu *vcpu)
5946{
5947 fpu_free(&vcpu->arch.guest_fpu);
5948}
5949
d0752060
HB		 5950void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5951{
2608d7a1 5952 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5953 return;
5954
2acf923e
DC		 5955 /*
5956 * Restore all possible states in the guest,
5957 * and assume host would use all available bits.
5958 * Guest xcr0 would be loaded later.
5959 */
5960 kvm_put_guest_xcr0(vcpu);
d0752060 5961 vcpu->guest_fpu_loaded = 1;
b1a74bf8 5962 __kernel_fpu_begin();
98918833 5963 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5964 trace_kvm_fpu(1);
d0752060 5965}
d0752060
HB		 5966
5967void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5968{
2acf923e
DC		 5969 kvm_put_guest_xcr0(vcpu);
5970
d0752060
HB		 5971 if (!vcpu->guest_fpu_loaded)
5972 return;
5973
5974 vcpu->guest_fpu_loaded = 0;
98918833 5975 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 5976 __kernel_fpu_end();
f096ed85 5977 ++vcpu->stat.fpu_reload;
a8eeb04a 5978 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5979 trace_kvm_fpu(0);
d0752060 5980}
e9b11c17
ZX		 5981
5982void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5983{
12f9a48f 5984 kvmclock_reset(vcpu);
7f1ea208 5985
f5f48ee1 5986 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5987 fx_free(vcpu);
e9b11c17
ZX		 5988 kvm_x86_ops->vcpu_free(vcpu);
5989}
5990
5991struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5992 unsigned int id)
5993{
6755bae8
ZA		 5994 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5995 printk_once(KERN_WARNING
5996 "kvm: SMP vm created on host with unstable TSC; "
5997 "guest TSC will not be reliable\n");
26e5215f
AK		 5998 return kvm_x86_ops->vcpu_create(kvm, id);
5999}
e9b11c17 6000
26e5215f
AK		 6001int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6002{
6003 int r;
e9b11c17 6004
0bed3b56 6005 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6006 r = vcpu_load(vcpu);
6007 if (r)
6008 return r;
8b6e4547 6009 r = kvm_vcpu_reset(vcpu);
e9b11c17
ZX		 6010 if (r == 0)
6011 r = kvm_mmu_setup(vcpu);
6012 vcpu_put(vcpu);
e9b11c17 6013
26e5215f 6014 return r;
e9b11c17
ZX		 6015}
6016
d40ccc62 6017void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6018{
9fc77441 6019 int r;
344d9588
GN		 6020 vcpu->arch.apf.msr_val = 0;
6021
9fc77441
MT		 6022 r = vcpu_load(vcpu);
6023 BUG_ON(r);
e9b11c17
ZX		 6024 kvm_mmu_unload(vcpu);
6025 vcpu_put(vcpu);
6026
98918833 6027 fx_free(vcpu);
e9b11c17
ZX		 6028 kvm_x86_ops->vcpu_free(vcpu);
6029}
6030
8b6e4547 6031static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6032{
7460fb4a
AK		 6033 atomic_set(&vcpu->arch.nmi_queued, 0);
6034 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6035 vcpu->arch.nmi_injected = false;
6036
42dbaa5a
JK		 6037 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6038 vcpu->arch.dr6 = DR6_FIXED_1;
6039 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6040 kvm_update_dr7(vcpu);
42dbaa5a 6041
3842d135 6042 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6043 vcpu->arch.apf.msr_val = 0;
c9aaa895 6044 vcpu->arch.st.msr_val = 0;
3842d135 6045
12f9a48f
GC		 6046 kvmclock_reset(vcpu);
6047
af585b92
GN		 6048 kvm_clear_async_pf_completion_queue(vcpu);
6049 kvm_async_pf_hash_reset(vcpu);
6050 vcpu->arch.apf.halted = false;
3842d135 6051
f5132b01
GN		 6052 kvm_pmu_reset(vcpu);
6053
e9b11c17
ZX		 6054 return kvm_x86_ops->vcpu_reset(vcpu);
6055}
6056
10474ae8 6057int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6058{
ca84d1a2
ZA		 6059 struct kvm *kvm;
6060 struct kvm_vcpu *vcpu;
6061 int i;
0dd6a6ed
ZA		 6062 int ret;
6063 u64 local_tsc;
6064 u64 max_tsc = 0;
6065 bool stable, backwards_tsc = false;
18863bdd
AK		 6066
6067 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6068 ret = kvm_x86_ops->hardware_enable(garbage);
6069 if (ret != 0)
6070 return ret;
6071
6072 local_tsc = native_read_tsc();
6073 stable = !check_tsc_unstable();
6074 list_for_each_entry(kvm, &vm_list, vm_list) {
6075 kvm_for_each_vcpu(i, vcpu, kvm) {
6076 if (!stable && vcpu->cpu == smp_processor_id())
6077 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6078 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6079 backwards_tsc = true;
6080 if (vcpu->arch.last_host_tsc > max_tsc)
6081 max_tsc = vcpu->arch.last_host_tsc;
6082 }
6083 }
6084 }
6085
6086 /*
6087 * Sometimes, even reliable TSCs go backwards. This happens on
6088 * platforms that reset TSC during suspend or hibernate actions, but
6089 * maintain synchronization. We must compensate. Fortunately, we can
6090 * detect that condition here, which happens early in CPU bringup,
6091 * before any KVM threads can be running. Unfortunately, we can't
6092 * bring the TSCs fully up to date with real time, as we aren't yet far
6093 * enough into CPU bringup that we know how much real time has actually
6094 * elapsed; our helper function, get_kernel_ns() will be using boot
6095 * variables that haven't been updated yet.
6096 *
6097 * So we simply find the maximum observed TSC above, then record the
6098 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6099 * the adjustment will be applied. Note that we accumulate
6100 * adjustments, in case multiple suspend cycles happen before some VCPU
6101 * gets a chance to run again. In the event that no KVM threads get a
6102 * chance to run, we will miss the entire elapsed period, as we'll have
6103 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6104 * loose cycle time. This isn't too big a deal, since the loss will be
6105 * uniform across all VCPUs (not to mention the scenario is extremely
6106 * unlikely). It is possible that a second hibernate recovery happens
6107 * much faster than a first, causing the observed TSC here to be
6108 * smaller; this would require additional padding adjustment, which is
6109 * why we set last_host_tsc to the local tsc observed here.
6110 *
6111 * N.B. - this code below runs only on platforms with reliable TSC,
6112 * as that is the only way backwards_tsc is set above. Also note
6113 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6114 * have the same delta_cyc adjustment applied if backwards_tsc
6115 * is detected. Note further, this adjustment is only done once,
6116 * as we reset last_host_tsc on all VCPUs to stop this from being
6117 * called multiple times (one for each physical CPU bringup).
6118 *
4a969980 6119 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6120 * will be compensated by the logic in vcpu_load, which sets the TSC to
6121 * catchup mode. This will catchup all VCPUs to real time, but cannot
6122 * guarantee that they stay in perfect synchronization.
6123 */
6124 if (backwards_tsc) {
6125 u64 delta_cyc = max_tsc - local_tsc;
6126 list_for_each_entry(kvm, &vm_list, vm_list) {
6127 kvm_for_each_vcpu(i, vcpu, kvm) {
6128 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6129 vcpu->arch.last_host_tsc = local_tsc;
6130 }
6131
6132 /*
6133 * We have to disable TSC offset matching.. if you were
6134 * booting a VM while issuing an S4 host suspend....
6135 * you may have some problem. Solving this issue is
6136 * left as an exercise to the reader.
6137 */
6138 kvm->arch.last_tsc_nsec = 0;
6139 kvm->arch.last_tsc_write = 0;
6140 }
6141
6142 }
6143 return 0;
e9b11c17
ZX		 6144}
6145
6146void kvm_arch_hardware_disable(void *garbage)
6147{
6148 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6149 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6150}
6151
6152int kvm_arch_hardware_setup(void)
6153{
6154 return kvm_x86_ops->hardware_setup();
6155}
6156
6157void kvm_arch_hardware_unsetup(void)
6158{
6159 kvm_x86_ops->hardware_unsetup();
6160}
6161
6162void kvm_arch_check_processor_compat(void *rtn)
6163{
6164 kvm_x86_ops->check_processor_compatibility(rtn);
6165}
6166
3e515705
AK		 6167bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6168{
6169 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6170}
6171
54e9818f
GN		 6172struct static_key kvm_no_apic_vcpu __read_mostly;
6173
e9b11c17
ZX		 6174int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6175{
6176 struct page *page;
6177 struct kvm *kvm;
6178 int r;
6179
6180 BUG_ON(vcpu->kvm == NULL);
6181 kvm = vcpu->kvm;
6182
9aabc88f 6183 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6184 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6185 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6186 else
a4535290 6187 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6188
6189 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6190 if (!page) {
6191 r = -ENOMEM;
6192 goto fail;
6193 }
ad312c7c 6194 vcpu->arch.pio_data = page_address(page);
e9b11c17 6195
cc578287 6196 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6197
e9b11c17
ZX		 6198 r = kvm_mmu_create(vcpu);
6199 if (r < 0)
6200 goto fail_free_pio_data;
6201
6202 if (irqchip_in_kernel(kvm)) {
6203 r = kvm_create_lapic(vcpu);
6204 if (r < 0)
6205 goto fail_mmu_destroy;
54e9818f
GN		 6206 } else
6207 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6208
890ca9ae
HY		 6209 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6210 GFP_KERNEL);
6211 if (!vcpu->arch.mce_banks) {
6212 r = -ENOMEM;
443c39bc 6213 goto fail_free_lapic;
890ca9ae
HY		 6214 }
6215 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6216
f5f48ee1
SY		 6217 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6218 goto fail_free_mce_banks;
6219
af585b92 6220 kvm_async_pf_hash_reset(vcpu);
f5132b01 6221 kvm_pmu_init(vcpu);
af585b92 6222
e9b11c17 6223 return 0;
f5f48ee1
SY		 6224fail_free_mce_banks:
6225 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6226fail_free_lapic:
6227 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6228fail_mmu_destroy:
6229 kvm_mmu_destroy(vcpu);
6230fail_free_pio_data:
ad312c7c 6231 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6232fail:
6233 return r;
6234}
6235
6236void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6237{
f656ce01
MT		 6238 int idx;
6239
f5132b01 6240 kvm_pmu_destroy(vcpu);
36cb93fd 6241 kfree(vcpu->arch.mce_banks);
e9b11c17 6242 kvm_free_lapic(vcpu);
f656ce01 6243 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6244 kvm_mmu_destroy(vcpu);
f656ce01 6245 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6246 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6247 if (!irqchip_in_kernel(vcpu->kvm))
6248 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6249}
d19a9cd2 6250
e08b9637 6251int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6252{
e08b9637
CO		 6253 if (type)
6254 return -EINVAL;
6255
f05e70ac 6256 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6257 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6258
5550af4d
SY		 6259 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6260 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6261 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6262 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6263 &kvm->arch.irq_sources_bitmap);
5550af4d 6264
038f8c11 6265 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6266 mutex_init(&kvm->arch.apic_map_lock);
53f658b3 6267
d89f5eff 6268 return 0;
d19a9cd2
ZX		 6269}
6270
6271static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6272{
9fc77441
MT		 6273 int r;
6274 r = vcpu_load(vcpu);
6275 BUG_ON(r);
d19a9cd2
ZX		 6276 kvm_mmu_unload(vcpu);
6277 vcpu_put(vcpu);
6278}
6279
6280static void kvm_free_vcpus(struct kvm *kvm)
6281{
6282 unsigned int i;
988a2cae 6283 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6284
6285 /*
6286 * Unpin any mmu pages first.
6287 */
af585b92
GN		 6288 kvm_for_each_vcpu(i, vcpu, kvm) {
6289 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6290 kvm_unload_vcpu_mmu(vcpu);
af585b92 6291 }
988a2cae
GN		 6292 kvm_for_each_vcpu(i, vcpu, kvm)
6293 kvm_arch_vcpu_free(vcpu);
6294
6295 mutex_lock(&kvm->lock);
6296 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6297 kvm->vcpus[i] = NULL;
d19a9cd2 6298
988a2cae
GN		 6299 atomic_set(&kvm->online_vcpus, 0);
6300 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6301}
6302
ad8ba2cd
SY		 6303void kvm_arch_sync_events(struct kvm *kvm)
6304{
ba4cef31 6305 kvm_free_all_assigned_devices(kvm);
aea924f6 6306 kvm_free_pit(kvm);
ad8ba2cd
SY		 6307}
6308
d19a9cd2
ZX		 6309void kvm_arch_destroy_vm(struct kvm *kvm)
6310{
6eb55818 6311 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6312 kfree(kvm->arch.vpic);
6313 kfree(kvm->arch.vioapic);
d19a9cd2 6314 kvm_free_vcpus(kvm);
3d45830c
AK		 6315 if (kvm->arch.apic_access_page)
6316 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6317 if (kvm->arch.ept_identity_pagetable)
6318 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6319 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6320}
0de10343 6321
db3fe4eb
TY		 6322void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6323 struct kvm_memory_slot *dont)
6324{
6325 int i;
6326
d89cc617
TY		 6327 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6328 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6329 kvm_kvfree(free->arch.rmap[i]);
6330 free->arch.rmap[i] = NULL;
77d11309 6331 }
d89cc617
TY		 6332 if (i == 0)
6333 continue;
6334
6335 if (!dont || free->arch.lpage_info[i - 1] !=
6336 dont->arch.lpage_info[i - 1]) {
6337 kvm_kvfree(free->arch.lpage_info[i - 1]);
6338 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6339 }
6340 }
6341}
6342
6343int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6344{
6345 int i;
6346
d89cc617 6347 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6348 unsigned long ugfn;
6349 int lpages;
d89cc617 6350 int level = i + 1;
db3fe4eb
TY		 6351
6352 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6353 slot->base_gfn, level) + 1;
6354
d89cc617
TY		 6355 slot->arch.rmap[i] =
6356 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6357 if (!slot->arch.rmap[i])
77d11309 6358 goto out_free;
d89cc617
TY		 6359 if (i == 0)
6360 continue;
77d11309 6361
d89cc617
TY		 6362 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6363 sizeof(*slot->arch.lpage_info[i - 1]));
6364 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6365 goto out_free;
6366
6367 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6368 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6369 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6370 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6371 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6372 /*
6373 * If the gfn and userspace address are not aligned wrt each
6374 * other, or if explicitly asked to, disable large page
6375 * support for this slot
6376 */
6377 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6378 !kvm_largepages_enabled()) {
6379 unsigned long j;
6380
6381 for (j = 0; j < lpages; ++j)
d89cc617 6382 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6383 }
6384 }
6385
6386 return 0;
6387
6388out_free:
d89cc617
TY		 6389 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6390 kvm_kvfree(slot->arch.rmap[i]);
6391 slot->arch.rmap[i] = NULL;
6392 if (i == 0)
6393 continue;
6394
6395 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6396 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6397 }
6398 return -ENOMEM;
6399}
6400
f7784b8e
MT		 6401int kvm_arch_prepare_memory_region(struct kvm *kvm,
6402 struct kvm_memory_slot *memslot,
0de10343 6403 struct kvm_memory_slot old,
f7784b8e 6404 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6405 int user_alloc)
6406{
f7784b8e 6407 int npages = memslot->npages;
7ac77099
AK		 6408 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6409
6410 /* Prevent internal slot pages from being moved by fork()/COW. */
6411 if (memslot->id >= KVM_MEMORY_SLOTS)
6412 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6413
6414 /*To keep backward compatibility with older userspace,
4a969980 6415 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6416 */
6417 if (!user_alloc) {
aab2eb7a 6418 if (npages && !old.npages) {
604b38ac
AA		 6419 unsigned long userspace_addr;
6420
6be5ceb0 6421 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6422 npages * PAGE_SIZE,
6423 PROT_READ | PROT_WRITE,
7ac77099 6424 map_flags,
604b38ac 6425 0);
0de10343 6426
604b38ac
AA		 6427 if (IS_ERR((void *)userspace_addr))
6428 return PTR_ERR((void *)userspace_addr);
6429
604b38ac 6430 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6431 }
6432 }
6433
f7784b8e
MT		 6434
6435 return 0;
6436}
6437
6438void kvm_arch_commit_memory_region(struct kvm *kvm,
6439 struct kvm_userspace_memory_region *mem,
6440 struct kvm_memory_slot old,
6441 int user_alloc)
6442{
6443
48c0e4e9 6444 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6445
aab2eb7a 6446 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6447 int ret;
6448
bfce281c 6449 ret = vm_munmap(old.userspace_addr,
f7784b8e 6450 old.npages * PAGE_SIZE);
f7784b8e
MT		 6451 if (ret < 0)
6452 printk(KERN_WARNING
6453 "kvm_vm_ioctl_set_memory_region: "
6454 "failed to munmap memory\n");
6455 }
6456
48c0e4e9
XG		 6457 if (!kvm->arch.n_requested_mmu_pages)
6458 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6459
7c8a83b7 6460 spin_lock(&kvm->mmu_lock);
48c0e4e9 6461 if (nr_mmu_pages)
0de10343 6462 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6463 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6464 spin_unlock(&kvm->mmu_lock);
3b4dc3a0
MT		 6465 /*
6466 * If memory slot is created, or moved, we need to clear all
6467 * mmio sptes.
6468 */
6469 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6470 kvm_mmu_zap_all(kvm);
6471 kvm_reload_remote_mmus(kvm);
6472 }
0de10343 6473}
1d737c8a 6474
2df72e9b 6475void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6476{
6477 kvm_mmu_zap_all(kvm);
8986ecc0 6478 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6479}
6480
2df72e9b
MT		 6481void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6482 struct kvm_memory_slot *slot)
6483{
6484 kvm_arch_flush_shadow_all(kvm);
6485}
6486
1d737c8a
ZX		 6487int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6488{
af585b92
GN		 6489 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6490 !vcpu->arch.apf.halted)
6491 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6492 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6493 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6494 (kvm_arch_interrupt_allowed(vcpu) &&
6495 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6496}
5736199a 6497
b6d33834 6498int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6499{
b6d33834 6500 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6501}
78646121
GN		 6502
6503int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6504{
6505 return kvm_x86_ops->interrupt_allowed(vcpu);
6506}
229456fc 6507
f92653ee
JK		 6508bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6509{
6510 unsigned long current_rip = kvm_rip_read(vcpu) +
6511 get_segment_base(vcpu, VCPU_SREG_CS);
6512
6513 return current_rip == linear_rip;
6514}
6515EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6516
94fe45da
JK		 6517unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6518{
6519 unsigned long rflags;
6520
6521 rflags = kvm_x86_ops->get_rflags(vcpu);
6522 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6523 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6524 return rflags;
6525}
6526EXPORT_SYMBOL_GPL(kvm_get_rflags);
6527
6528void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6529{
6530 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6531 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6532 rflags |= X86_EFLAGS_TF;
94fe45da 6533 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6534 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6535}
6536EXPORT_SYMBOL_GPL(kvm_set_rflags);
6537
56028d08
GN		 6538void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6539{
6540 int r;
6541
fb67e14f 6542 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6543 is_error_page(work->page))
56028d08
GN		 6544 return;
6545
6546 r = kvm_mmu_reload(vcpu);
6547 if (unlikely(r))
6548 return;
6549
fb67e14f
XG		 6550 if (!vcpu->arch.mmu.direct_map &&
6551 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6552 return;
6553
56028d08
GN		 6554 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6555}
6556
af585b92
GN		 6557static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6558{
6559 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6560}
6561
6562static inline u32 kvm_async_pf_next_probe(u32 key)
6563{
6564 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6565}
6566
6567static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6568{
6569 u32 key = kvm_async_pf_hash_fn(gfn);
6570
6571 while (vcpu->arch.apf.gfns[key] != ~0)
6572 key = kvm_async_pf_next_probe(key);
6573
6574 vcpu->arch.apf.gfns[key] = gfn;
6575}
6576
6577static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6578{
6579 int i;
6580 u32 key = kvm_async_pf_hash_fn(gfn);
6581
6582 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6583 (vcpu->arch.apf.gfns[key] != gfn &&
6584 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6585 key = kvm_async_pf_next_probe(key);
6586
6587 return key;
6588}
6589
6590bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6591{
6592 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6593}
6594
6595static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6596{
6597 u32 i, j, k;
6598
6599 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6600 while (true) {
6601 vcpu->arch.apf.gfns[i] = ~0;
6602 do {
6603 j = kvm_async_pf_next_probe(j);
6604 if (vcpu->arch.apf.gfns[j] == ~0)
6605 return;
6606 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6607 /*
6608 * k lies cyclically in ]i,j]
6609 * | i.k.j |
6610 * |....j i.k.| or |.k..j i...|
6611 */
6612 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6613 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6614 i = j;
6615 }
6616}
6617
7c90705b
GN		 6618static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6619{
6620
6621 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6622 sizeof(val));
6623}
6624
af585b92
GN		 6625void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6626 struct kvm_async_pf *work)
6627{
6389ee94
AK		 6628 struct x86_exception fault;
6629
7c90705b 6630 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6631 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6632
6633 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6634 (vcpu->arch.apf.send_user_only &&
6635 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6636 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6637 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6638 fault.vector = PF_VECTOR;
6639 fault.error_code_valid = true;
6640 fault.error_code = 0;
6641 fault.nested_page_fault = false;
6642 fault.address = work->arch.token;
6643 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6644 }
af585b92
GN		 6645}
6646
6647void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6648 struct kvm_async_pf *work)
6649{
6389ee94
AK		 6650 struct x86_exception fault;
6651
7c90705b
GN		 6652 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6653 if (is_error_page(work->page))
6654 work->arch.token = ~0; /* broadcast wakeup */
6655 else
6656 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6657
6658 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6659 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6660 fault.vector = PF_VECTOR;
6661 fault.error_code_valid = true;
6662 fault.error_code = 0;
6663 fault.nested_page_fault = false;
6664 fault.address = work->arch.token;
6665 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6666 }
e6d53e3b 6667 vcpu->arch.apf.halted = false;
a4fa1635 6668 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 6669}
6670
6671bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6672{
6673 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6674 return true;
6675 else
6676 return !kvm_event_needs_reinjection(vcpu) &&
6677 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6678}
6679
229456fc
MT		 6680EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6681EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6682EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6683EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6684EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6685EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6686EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)