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KVM: Don't spam kernel log when injecting exceptions due to bad cr writes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
aec51dc4
AK		 43#include <trace/events/kvm.h>
44#undef TRACE_INCLUDE_FILE
229456fc
MT		 45#define CREATE_TRACE_POINTS
46#include "trace.h"
043405e1 47
24f1e32c 48#include <asm/debugreg.h>
043405e1 49#include <asm/uaccess.h>
d825ed0a 50#include <asm/msr.h>
a5f61300 51#include <asm/desc.h>
0bed3b56 52#include <asm/mtrr.h>
890ca9ae 53#include <asm/mce.h>
043405e1 54
313a3dc7 55#define MAX_IO_MSRS 256
a03490ed
CO		 56#define CR0_RESERVED_BITS \
57 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
58 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
59 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
60#define CR4_RESERVED_BITS \
61 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
62 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
63 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
64 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
65
66#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 67
68#define KVM_MAX_MCE_BANKS 32
69#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
77#else
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
18863bdd
AK		 94#define KVM_NR_SHARED_MSRS 16
95
96struct kvm_shared_msrs_global {
97 int nr;
2bf78fa7 98 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
2bf78fa7
SY		 104 struct kvm_shared_msr_values {
105 u64 host;
106 u64 curr;
107 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
111static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
112
417bc304 113struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 114 { "pf_fixed", VCPU_STAT(pf_fixed) },
115 { "pf_guest", VCPU_STAT(pf_guest) },
116 { "tlb_flush", VCPU_STAT(tlb_flush) },
117 { "invlpg", VCPU_STAT(invlpg) },
118 { "exits", VCPU_STAT(exits) },
119 { "io_exits", VCPU_STAT(io_exits) },
120 { "mmio_exits", VCPU_STAT(mmio_exits) },
121 { "signal_exits", VCPU_STAT(signal_exits) },
122 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 123 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 124 { "halt_exits", VCPU_STAT(halt_exits) },
125 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 126 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 127 { "request_irq", VCPU_STAT(request_irq_exits) },
128 { "irq_exits", VCPU_STAT(irq_exits) },
129 { "host_state_reload", VCPU_STAT(host_state_reload) },
130 { "efer_reload", VCPU_STAT(efer_reload) },
131 { "fpu_reload", VCPU_STAT(fpu_reload) },
132 { "insn_emulation", VCPU_STAT(insn_emulation) },
133 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 134 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 135 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 136 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
137 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
138 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
139 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
140 { "mmu_flooded", VM_STAT(mmu_flooded) },
141 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 142 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 143 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 144 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 145 { "largepages", VM_STAT(lpages) },
417bc304
HB		 146 { NULL }
147};
148
18863bdd
AK		 149static void kvm_on_user_return(struct user_return_notifier *urn)
150{
151 unsigned slot;
18863bdd
AK		 152 struct kvm_shared_msrs *locals
153 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 154 struct kvm_shared_msr_values *values;
18863bdd
AK		 155
156 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 157 values = &locals->values[slot];
158 if (values->host != values->curr) {
159 wrmsrl(shared_msrs_global.msrs[slot], values->host);
160 values->curr = values->host;
18863bdd
AK		 161 }
162 }
163 locals->registered = false;
164 user_return_notifier_unregister(urn);
165}
166
2bf78fa7 167static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 168{
2bf78fa7 169 struct kvm_shared_msrs *smsr;
18863bdd
AK		 170 u64 value;
171
2bf78fa7
SY		 172 smsr = &__get_cpu_var(shared_msrs);
173 /* only read, and nobody should modify it at this time,
174 * so don't need lock */
175 if (slot >= shared_msrs_global.nr) {
176 printk(KERN_ERR "kvm: invalid MSR slot!");
177 return;
178 }
179 rdmsrl_safe(msr, &value);
180 smsr->values[slot].host = value;
181 smsr->values[slot].curr = value;
182}
183
184void kvm_define_shared_msr(unsigned slot, u32 msr)
185{
18863bdd
AK		 186 if (slot >= shared_msrs_global.nr)
187 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 188 shared_msrs_global.msrs[slot] = msr;
189 /* we need ensured the shared_msr_global have been updated */
190 smp_wmb();
18863bdd
AK		 191}
192EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
193
194static void kvm_shared_msr_cpu_online(void)
195{
196 unsigned i;
18863bdd
AK		 197
198 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 199 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 200}
201
d5696725 202void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 203{
204 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
205
2bf78fa7 206 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 207 return;
2bf78fa7
SY		 208 smsr->values[slot].curr = value;
209 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 210 if (!smsr->registered) {
211 smsr->urn.on_user_return = kvm_on_user_return;
212 user_return_notifier_register(&smsr->urn);
213 smsr->registered = true;
214 }
215}
216EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
217
3548bab5
AK		 218static void drop_user_return_notifiers(void *ignore)
219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
222 if (smsr->registered)
223 kvm_on_user_return(&smsr->urn);
224}
225
5fb76f9b
CO		 226unsigned long segment_base(u16 selector)
227{
228 struct descriptor_table gdt;
a5f61300 229 struct desc_struct *d;
5fb76f9b
CO		 230 unsigned long table_base;
231 unsigned long v;
232
233 if (selector == 0)
234 return 0;
235
b792c344 236 kvm_get_gdt(&gdt);
5fb76f9b
CO		 237 table_base = gdt.base;
238
239 if (selector & 4) { /* from ldt */
b792c344 240 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 241
5fb76f9b
CO		 242 table_base = segment_base(ldt_selector);
243 }
a5f61300 244 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 245 v = get_desc_base(d);
5fb76f9b 246#ifdef CONFIG_X86_64
a5f61300
AK		 247 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
248 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 249#endif
250 return v;
251}
252EXPORT_SYMBOL_GPL(segment_base);
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
256 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 257 return vcpu->arch.apic_base;
6866b83e 258 else
ad312c7c 259 return vcpu->arch.apic_base;
6866b83e
CO		 260}
261EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262
263void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
264{
265 /* TODO: reserve bits check */
266 if (irqchip_in_kernel(vcpu->kvm))
267 kvm_lapic_set_base(vcpu, data);
268 else
ad312c7c 269 vcpu->arch.apic_base = data;
6866b83e
CO		 270}
271EXPORT_SYMBOL_GPL(kvm_set_apic_base);
272
3fd28fce
ED		 273#define EXCPT_BENIGN 0
274#define EXCPT_CONTRIBUTORY 1
275#define EXCPT_PF 2
276
277static int exception_class(int vector)
278{
279 switch (vector) {
280 case PF_VECTOR:
281 return EXCPT_PF;
282 case DE_VECTOR:
283 case TS_VECTOR:
284 case NP_VECTOR:
285 case SS_VECTOR:
286 case GP_VECTOR:
287 return EXCPT_CONTRIBUTORY;
288 default:
289 break;
290 }
291 return EXCPT_BENIGN;
292}
293
294static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
295 unsigned nr, bool has_error, u32 error_code)
296{
297 u32 prev_nr;
298 int class1, class2;
299
300 if (!vcpu->arch.exception.pending) {
301 queue:
302 vcpu->arch.exception.pending = true;
303 vcpu->arch.exception.has_error_code = has_error;
304 vcpu->arch.exception.nr = nr;
305 vcpu->arch.exception.error_code = error_code;
306 return;
307 }
308
309 /* to check exception */
310 prev_nr = vcpu->arch.exception.nr;
311 if (prev_nr == DF_VECTOR) {
312 /* triple fault -> shutdown */
313 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
314 return;
315 }
316 class1 = exception_class(prev_nr);
317 class2 = exception_class(nr);
318 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
319 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
320 /* generate double fault per SDM Table 5-5 */
321 vcpu->arch.exception.pending = true;
322 vcpu->arch.exception.has_error_code = true;
323 vcpu->arch.exception.nr = DF_VECTOR;
324 vcpu->arch.exception.error_code = 0;
325 } else
326 /* replace previous exception with a new one in a hope
327 that instruction re-execution will regenerate lost
328 exception */
329 goto queue;
330}
331
298101da
AK		 332void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
333{
3fd28fce 334 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 335}
336EXPORT_SYMBOL_GPL(kvm_queue_exception);
337
c3c91fee
AK		 338void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
339 u32 error_code)
340{
341 ++vcpu->stat.pf_guest;
ad312c7c 342 vcpu->arch.cr2 = addr;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
3419ffc8
SY		 346void kvm_inject_nmi(struct kvm_vcpu *vcpu)
347{
348 vcpu->arch.nmi_pending = 1;
349}
350EXPORT_SYMBOL_GPL(kvm_inject_nmi);
351
298101da
AK		 352void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
353{
3fd28fce 354 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 355}
356EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
357
0a79b009
AK		 358/*
359 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
360 * a #GP and return false.
361 */
362bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 363{
0a79b009
AK		 364 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
365 return true;
366 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
367 return false;
298101da 368}
0a79b009 369EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 370
a03490ed
CO		 371/*
372 * Load the pae pdptrs. Return true is they are all valid.
373 */
374int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
375{
376 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
377 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
378 int i;
379 int ret;
ad312c7c 380 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 381
a03490ed
CO		 382 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
383 offset * sizeof(u64), sizeof(pdpte));
384 if (ret < 0) {
385 ret = 0;
386 goto out;
387 }
388 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 389 if (is_present_gpte(pdpte[i]) &&
20c466b5 390 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 391 ret = 0;
392 goto out;
393 }
394 }
395 ret = 1;
396
ad312c7c 397 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_avail);
400 __set_bit(VCPU_EXREG_PDPTR,
401 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 402out:
a03490ed
CO		 403
404 return ret;
405}
cc4b6871 406EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 407
d835dfec
AK		 408static bool pdptrs_changed(struct kvm_vcpu *vcpu)
409{
ad312c7c 410 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 411 bool changed = true;
412 int r;
413
414 if (is_long_mode(vcpu) || !is_pae(vcpu))
415 return false;
416
6de4f3ad
AK		 417 if (!test_bit(VCPU_EXREG_PDPTR,
418 (unsigned long *)&vcpu->arch.regs_avail))
419 return true;
420
ad312c7c 421 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 422 if (r < 0)
423 goto out;
ad312c7c 424 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 425out:
d835dfec
AK		 426
427 return changed;
428}
429
2d3ad1f4 430void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 431{
f9a48e6a
AK		 432 cr0 |= X86_CR0_ET;
433
ab344828
GN		 434#ifdef CONFIG_X86_64
435 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 442
443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 444 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 445 return;
446 }
447
448 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 449 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 450 return;
451 }
452
453 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
454#ifdef CONFIG_X86_64
f6801dff 455 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 456 int cs_db, cs_l;
457
458 if (!is_pae(vcpu)) {
c1a5d4f9 459 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 460 return;
461 }
462 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
463 if (cs_l) {
c1a5d4f9 464 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 465 return;
466
467 }
468 } else
469#endif
ad312c7c 470 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 471 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 472 return;
473 }
474
475 }
476
477 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 478 vcpu->arch.cr0 = cr0;
a03490ed 479
a03490ed 480 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 481 return;
482}
2d3ad1f4 483EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 484
2d3ad1f4 485void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 486{
4d4ec087 487 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 488}
2d3ad1f4 489EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 490
2d3ad1f4 491void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 492{
fc78f519 493 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 494 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
495
a03490ed 496 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 498 return;
499 }
500
501 if (is_long_mode(vcpu)) {
502 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 504 return;
505 }
a2edf57f
AK		 506 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
507 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 508 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 510 return;
511 }
512
513 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 514 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 515 return;
516 }
517 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 518 vcpu->arch.cr4 = cr4;
5a41accd 519 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 520 kvm_mmu_reset_context(vcpu);
a03490ed 521}
2d3ad1f4 522EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 523
2d3ad1f4 524void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 525{
ad312c7c 526 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 527 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 528 kvm_mmu_flush_tlb(vcpu);
529 return;
530 }
531
a03490ed
CO		 532 if (is_long_mode(vcpu)) {
533 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 534 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 535 return;
536 }
537 } else {
538 if (is_pae(vcpu)) {
539 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 540 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 541 return;
542 }
543 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 544 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 545 return;
546 }
547 }
548 /*
549 * We don't check reserved bits in nonpae mode, because
550 * this isn't enforced, and VMware depends on this.
551 */
552 }
553
a03490ed
CO		 554 /*
555 * Does the new cr3 value map to physical memory? (Note, we
556 * catch an invalid cr3 even in real-mode, because it would
557 * cause trouble later on when we turn on paging anyway.)
558 *
559 * A real CPU would silently accept an invalid cr3 and would
560 * attempt to use it - with largely undefined (and often hard
561 * to debug) behavior on the guest side.
562 */
563 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 564 kvm_inject_gp(vcpu, 0);
a03490ed 565 else {
ad312c7c
ZX		 566 vcpu->arch.cr3 = cr3;
567 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 568 }
a03490ed 569}
2d3ad1f4 570EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 571
2d3ad1f4 572void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 573{
574 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 575 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 576 return;
577 }
578 if (irqchip_in_kernel(vcpu->kvm))
579 kvm_lapic_set_tpr(vcpu, cr8);
580 else
ad312c7c 581 vcpu->arch.cr8 = cr8;
a03490ed 582}
2d3ad1f4 583EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 584
2d3ad1f4 585unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 586{
587 if (irqchip_in_kernel(vcpu->kvm))
588 return kvm_lapic_get_cr8(vcpu);
589 else
ad312c7c 590 return vcpu->arch.cr8;
a03490ed 591}
2d3ad1f4 592EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 593
d8017474
AG		 594static inline u32 bit(int bitno)
595{
596 return 1 << (bitno & 31);
597}
598
043405e1
CO		 599/*
600 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
601 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
602 *
603 * This list is modified at module load time to reflect the
e3267cbb
GC		 604 * capabilities of the host cpu. This capabilities test skips MSRs that are
605 * kvm-specific. Those are put in the beginning of the list.
043405e1 606 */
e3267cbb 607
10388a07 608#define KVM_SAVE_MSRS_BEGIN 5
043405e1 609static u32 msrs_to_save[] = {
e3267cbb 610 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 611 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 612 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 613 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
614 MSR_K6_STAR,
615#ifdef CONFIG_X86_64
616 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
617#endif
e3267cbb 618 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 619};
620
621static unsigned num_msrs_to_save;
622
623static u32 emulated_msrs[] = {
624 MSR_IA32_MISC_ENABLE,
625};
626
15c4a640
CO		 627static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
628{
f2b4b7dd 629 if (efer & efer_reserved_bits) {
c1a5d4f9 630 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 631 return;
632 }
633
634 if (is_paging(vcpu)
f6801dff 635 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 636 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 637 return;
638 }
639
1b2fd70c
AG		 640 if (efer & EFER_FFXSR) {
641 struct kvm_cpuid_entry2 *feat;
642
643 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
644 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 645 kvm_inject_gp(vcpu, 0);
646 return;
647 }
648 }
649
d8017474
AG		 650 if (efer & EFER_SVME) {
651 struct kvm_cpuid_entry2 *feat;
652
653 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
654 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 655 kvm_inject_gp(vcpu, 0);
656 return;
657 }
658 }
659
15c4a640
CO		 660 kvm_x86_ops->set_efer(vcpu, efer);
661
662 efer &= ~EFER_LMA;
f6801dff 663 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 664
f6801dff 665 vcpu->arch.efer = efer;
9645bb56
AK		 666
667 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
668 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 669}
670
f2b4b7dd
JR		 671void kvm_enable_efer_bits(u64 mask)
672{
673 efer_reserved_bits &= ~mask;
674}
675EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
676
677
15c4a640
CO		 678/*
679 * Writes msr value into into the appropriate "register".
680 * Returns 0 on success, non-0 otherwise.
681 * Assumes vcpu_load() was already called.
682 */
683int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
684{
685 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
686}
687
313a3dc7
CO		 688/*
689 * Adapt set_msr() to msr_io()'s calling convention
690 */
691static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
692{
693 return kvm_set_msr(vcpu, index, *data);
694}
695
18068523
GOC		 696static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
697{
698 static int version;
50d0a0f9 699 struct pvclock_wall_clock wc;
923de3cf 700 struct timespec boot;
18068523
GOC		 701
702 if (!wall_clock)
703 return;
704
705 version++;
706
18068523
GOC		 707 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
708
50d0a0f9
GH		 709 /*
710 * The guest calculates current wall clock time by adding
711 * system time (updated by kvm_write_guest_time below) to the
712 * wall clock specified here. guest system time equals host
713 * system time for us, thus we must fill in host boot time here.
714 */
923de3cf 715 getboottime(&boot);
50d0a0f9
GH		 716
717 wc.sec = boot.tv_sec;
718 wc.nsec = boot.tv_nsec;
719 wc.version = version;
18068523
GOC		 720
721 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
722
723 version++;
724 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 725}
726
50d0a0f9
GH		 727static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
728{
729 uint32_t quotient, remainder;
730
731 /* Don't try to replace with do_div(), this one calculates
732 * "(dividend << 32) / divisor" */
733 __asm__ ( "divl %4"
734 : "=a" (quotient), "=d" (remainder)
735 : "0" (0), "1" (dividend), "r" (divisor) );
736 return quotient;
737}
738
739static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
740{
741 uint64_t nsecs = 1000000000LL;
742 int32_t shift = 0;
743 uint64_t tps64;
744 uint32_t tps32;
745
746 tps64 = tsc_khz * 1000LL;
747 while (tps64 > nsecs*2) {
748 tps64 >>= 1;
749 shift--;
750 }
751
752 tps32 = (uint32_t)tps64;
753 while (tps32 <= (uint32_t)nsecs) {
754 tps32 <<= 1;
755 shift++;
756 }
757
758 hv_clock->tsc_shift = shift;
759 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
760
761 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 762 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 763 hv_clock->tsc_to_system_mul);
764}
765
c8076604
GH		 766static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
767
18068523
GOC		 768static void kvm_write_guest_time(struct kvm_vcpu *v)
769{
770 struct timespec ts;
771 unsigned long flags;
772 struct kvm_vcpu_arch *vcpu = &v->arch;
773 void *shared_kaddr;
463656c0 774 unsigned long this_tsc_khz;
18068523
GOC		 775
776 if ((!vcpu->time_page))
777 return;
778
463656c0
AK		 779 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
780 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
781 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
782 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 783 }
463656c0 784 put_cpu_var(cpu_tsc_khz);
50d0a0f9 785
18068523
GOC		 786 /* Keep irq disabled to prevent changes to the clock */
787 local_irq_save(flags);
af24a4e4 788 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 789 ktime_get_ts(&ts);
923de3cf 790 monotonic_to_bootbased(&ts);
18068523
GOC		 791 local_irq_restore(flags);
792
793 /* With all the info we got, fill in the values */
794
795 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 796 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
797
18068523
GOC		 798 /*
799 * The interface expects us to write an even number signaling that the
800 * update is finished. Since the guest won't see the intermediate
50d0a0f9 801 * state, we just increase by 2 at the end.
18068523 802 */
50d0a0f9 803 vcpu->hv_clock.version += 2;
18068523
GOC		 804
805 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
806
807 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 808 sizeof(vcpu->hv_clock));
18068523
GOC		 809
810 kunmap_atomic(shared_kaddr, KM_USER0);
811
812 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
813}
814
c8076604
GH		 815static int kvm_request_guest_time_update(struct kvm_vcpu *v)
816{
817 struct kvm_vcpu_arch *vcpu = &v->arch;
818
819 if (!vcpu->time_page)
820 return 0;
821 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
822 return 1;
823}
824
9ba075a6
AK		 825static bool msr_mtrr_valid(unsigned msr)
826{
827 switch (msr) {
828 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
829 case MSR_MTRRfix64K_00000:
830 case MSR_MTRRfix16K_80000:
831 case MSR_MTRRfix16K_A0000:
832 case MSR_MTRRfix4K_C0000:
833 case MSR_MTRRfix4K_C8000:
834 case MSR_MTRRfix4K_D0000:
835 case MSR_MTRRfix4K_D8000:
836 case MSR_MTRRfix4K_E0000:
837 case MSR_MTRRfix4K_E8000:
838 case MSR_MTRRfix4K_F0000:
839 case MSR_MTRRfix4K_F8000:
840 case MSR_MTRRdefType:
841 case MSR_IA32_CR_PAT:
842 return true;
843 case 0x2f8:
844 return true;
845 }
846 return false;
847}
848
d6289b93
MT		 849static bool valid_pat_type(unsigned t)
850{
851 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
852}
853
854static bool valid_mtrr_type(unsigned t)
855{
856 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
857}
858
859static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
860{
861 int i;
862
863 if (!msr_mtrr_valid(msr))
864 return false;
865
866 if (msr == MSR_IA32_CR_PAT) {
867 for (i = 0; i < 8; i++)
868 if (!valid_pat_type((data >> (i * 8)) & 0xff))
869 return false;
870 return true;
871 } else if (msr == MSR_MTRRdefType) {
872 if (data & ~0xcff)
873 return false;
874 return valid_mtrr_type(data & 0xff);
875 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
876 for (i = 0; i < 8 ; i++)
877 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
878 return false;
879 return true;
880 }
881
882 /* variable MTRRs */
883 return valid_mtrr_type(data & 0xff);
884}
885
9ba075a6
AK		 886static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
887{
0bed3b56
SY		 888 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
889
d6289b93 890 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 891 return 1;
892
0bed3b56
SY		 893 if (msr == MSR_MTRRdefType) {
894 vcpu->arch.mtrr_state.def_type = data;
895 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
896 } else if (msr == MSR_MTRRfix64K_00000)
897 p[0] = data;
898 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
899 p[1 + msr - MSR_MTRRfix16K_80000] = data;
900 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
901 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
902 else if (msr == MSR_IA32_CR_PAT)
903 vcpu->arch.pat = data;
904 else { /* Variable MTRRs */
905 int idx, is_mtrr_mask;
906 u64 *pt;
907
908 idx = (msr - 0x200) / 2;
909 is_mtrr_mask = msr - 0x200 - 2 * idx;
910 if (!is_mtrr_mask)
911 pt =
912 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
913 else
914 pt =
915 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
916 *pt = data;
917 }
918
919 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 920 return 0;
921}
15c4a640 922
890ca9ae 923static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 924{
890ca9ae
HY		 925 u64 mcg_cap = vcpu->arch.mcg_cap;
926 unsigned bank_num = mcg_cap & 0xff;
927
15c4a640 928 switch (msr) {
15c4a640 929 case MSR_IA32_MCG_STATUS:
890ca9ae 930 vcpu->arch.mcg_status = data;
15c4a640 931 break;
c7ac679c 932 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 933 if (!(mcg_cap & MCG_CTL_P))
934 return 1;
935 if (data != 0 && data != ~(u64)0)
936 return -1;
937 vcpu->arch.mcg_ctl = data;
938 break;
939 default:
940 if (msr >= MSR_IA32_MC0_CTL &&
941 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
942 u32 offset = msr - MSR_IA32_MC0_CTL;
943 /* only 0 or all 1s can be written to IA32_MCi_CTL */
944 if ((offset & 0x3) == 0 &&
945 data != 0 && data != ~(u64)0)
946 return -1;
947 vcpu->arch.mce_banks[offset] = data;
948 break;
949 }
950 return 1;
951 }
952 return 0;
953}
954
ffde22ac
ES		 955static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
956{
957 struct kvm *kvm = vcpu->kvm;
958 int lm = is_long_mode(vcpu);
959 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
960 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
961 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
962 : kvm->arch.xen_hvm_config.blob_size_32;
963 u32 page_num = data & ~PAGE_MASK;
964 u64 page_addr = data & PAGE_MASK;
965 u8 *page;
966 int r;
967
968 r = -E2BIG;
969 if (page_num >= blob_size)
970 goto out;
971 r = -ENOMEM;
972 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
973 if (!page)
974 goto out;
975 r = -EFAULT;
976 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
977 goto out_free;
978 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
979 goto out_free;
980 r = 0;
981out_free:
982 kfree(page);
983out:
984 return r;
985}
986
55cd8e5a
GN		 987static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
988{
989 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
990}
991
992static bool kvm_hv_msr_partition_wide(u32 msr)
993{
994 bool r = false;
995 switch (msr) {
996 case HV_X64_MSR_GUEST_OS_ID:
997 case HV_X64_MSR_HYPERCALL:
998 r = true;
999 break;
1000 }
1001
1002 return r;
1003}
1004
1005static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1006{
1007 struct kvm *kvm = vcpu->kvm;
1008
1009 switch (msr) {
1010 case HV_X64_MSR_GUEST_OS_ID:
1011 kvm->arch.hv_guest_os_id = data;
1012 /* setting guest os id to zero disables hypercall page */
1013 if (!kvm->arch.hv_guest_os_id)
1014 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1015 break;
1016 case HV_X64_MSR_HYPERCALL: {
1017 u64 gfn;
1018 unsigned long addr;
1019 u8 instructions[4];
1020
1021 /* if guest os id is not set hypercall should remain disabled */
1022 if (!kvm->arch.hv_guest_os_id)
1023 break;
1024 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1025 kvm->arch.hv_hypercall = data;
1026 break;
1027 }
1028 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1029 addr = gfn_to_hva(kvm, gfn);
1030 if (kvm_is_error_hva(addr))
1031 return 1;
1032 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1033 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1034 if (copy_to_user((void __user *)addr, instructions, 4))
1035 return 1;
1036 kvm->arch.hv_hypercall = data;
1037 break;
1038 }
1039 default:
1040 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1041 "data 0x%llx\n", msr, data);
1042 return 1;
1043 }
1044 return 0;
1045}
1046
1047static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1048{
10388a07
GN		 1049 switch (msr) {
1050 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1051 unsigned long addr;
55cd8e5a 1052
10388a07
GN		 1053 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1054 vcpu->arch.hv_vapic = data;
1055 break;
1056 }
1057 addr = gfn_to_hva(vcpu->kvm, data >>
1058 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1059 if (kvm_is_error_hva(addr))
1060 return 1;
1061 if (clear_user((void __user *)addr, PAGE_SIZE))
1062 return 1;
1063 vcpu->arch.hv_vapic = data;
1064 break;
1065 }
1066 case HV_X64_MSR_EOI:
1067 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1068 case HV_X64_MSR_ICR:
1069 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1070 case HV_X64_MSR_TPR:
1071 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1072 default:
1073 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1074 "data 0x%llx\n", msr, data);
1075 return 1;
1076 }
1077
1078 return 0;
55cd8e5a
GN		 1079}
1080
15c4a640
CO		 1081int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1082{
1083 switch (msr) {
15c4a640
CO		 1084 case MSR_EFER:
1085 set_efer(vcpu, data);
1086 break;
8f1589d9
AP		 1087 case MSR_K7_HWCR:
1088 data &= ~(u64)0x40; /* ignore flush filter disable */
1089 if (data != 0) {
1090 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1091 data);
1092 return 1;
1093 }
15c4a640 1094 break;
f7c6d140
AP		 1095 case MSR_FAM10H_MMIO_CONF_BASE:
1096 if (data != 0) {
1097 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1098 "0x%llx\n", data);
1099 return 1;
1100 }
15c4a640 1101 break;
c323c0e5 1102 case MSR_AMD64_NB_CFG:
c7ac679c 1103 break;
b5e2fec0
AG		 1104 case MSR_IA32_DEBUGCTLMSR:
1105 if (!data) {
1106 /* We support the non-activated case already */
1107 break;
1108 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1109 /* Values other than LBR and BTF are vendor-specific,
1110 thus reserved and should throw a #GP */
1111 return 1;
1112 }
1113 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1114 __func__, data);
1115 break;
15c4a640
CO		 1116 case MSR_IA32_UCODE_REV:
1117 case MSR_IA32_UCODE_WRITE:
61a6bd67 1118 case MSR_VM_HSAVE_PA:
6098ca93 1119 case MSR_AMD64_PATCH_LOADER:
15c4a640 1120 break;
9ba075a6
AK		 1121 case 0x200 ... 0x2ff:
1122 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1123 case MSR_IA32_APICBASE:
1124 kvm_set_apic_base(vcpu, data);
1125 break;
0105d1a5
GN		 1126 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1127 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1128 case MSR_IA32_MISC_ENABLE:
ad312c7c 1129 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1130 break;
18068523
GOC		 1131 case MSR_KVM_WALL_CLOCK:
1132 vcpu->kvm->arch.wall_clock = data;
1133 kvm_write_wall_clock(vcpu->kvm, data);
1134 break;
1135 case MSR_KVM_SYSTEM_TIME: {
1136 if (vcpu->arch.time_page) {
1137 kvm_release_page_dirty(vcpu->arch.time_page);
1138 vcpu->arch.time_page = NULL;
1139 }
1140
1141 vcpu->arch.time = data;
1142
1143 /* we verify if the enable bit is set... */
1144 if (!(data & 1))
1145 break;
1146
1147 /* ...but clean it before doing the actual write */
1148 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1149
18068523
GOC		 1150 vcpu->arch.time_page =
1151 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1152
1153 if (is_error_page(vcpu->arch.time_page)) {
1154 kvm_release_page_clean(vcpu->arch.time_page);
1155 vcpu->arch.time_page = NULL;
1156 }
1157
c8076604 1158 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1159 break;
1160 }
890ca9ae
HY		 1161 case MSR_IA32_MCG_CTL:
1162 case MSR_IA32_MCG_STATUS:
1163 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1164 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1165
1166 /* Performance counters are not protected by a CPUID bit,
1167 * so we should check all of them in the generic path for the sake of
1168 * cross vendor migration.
1169 * Writing a zero into the event select MSRs disables them,
1170 * which we perfectly emulate ;-). Any other value should be at least
1171 * reported, some guests depend on them.
1172 */
1173 case MSR_P6_EVNTSEL0:
1174 case MSR_P6_EVNTSEL1:
1175 case MSR_K7_EVNTSEL0:
1176 case MSR_K7_EVNTSEL1:
1177 case MSR_K7_EVNTSEL2:
1178 case MSR_K7_EVNTSEL3:
1179 if (data != 0)
1180 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1181 "0x%x data 0x%llx\n", msr, data);
1182 break;
1183 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1184 * so we ignore writes to make it happy.
1185 */
1186 case MSR_P6_PERFCTR0:
1187 case MSR_P6_PERFCTR1:
1188 case MSR_K7_PERFCTR0:
1189 case MSR_K7_PERFCTR1:
1190 case MSR_K7_PERFCTR2:
1191 case MSR_K7_PERFCTR3:
1192 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1193 "0x%x data 0x%llx\n", msr, data);
1194 break;
55cd8e5a
GN		 1195 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1196 if (kvm_hv_msr_partition_wide(msr)) {
1197 int r;
1198 mutex_lock(&vcpu->kvm->lock);
1199 r = set_msr_hyperv_pw(vcpu, msr, data);
1200 mutex_unlock(&vcpu->kvm->lock);
1201 return r;
1202 } else
1203 return set_msr_hyperv(vcpu, msr, data);
1204 break;
15c4a640 1205 default:
ffde22ac
ES		 1206 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1207 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1208 if (!ignore_msrs) {
1209 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1210 msr, data);
1211 return 1;
1212 } else {
1213 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1214 msr, data);
1215 break;
1216 }
15c4a640
CO		 1217 }
1218 return 0;
1219}
1220EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1221
1222
1223/*
1224 * Reads an msr value (of 'msr_index') into 'pdata'.
1225 * Returns 0 on success, non-0 otherwise.
1226 * Assumes vcpu_load() was already called.
1227 */
1228int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1229{
1230 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1231}
1232
9ba075a6
AK		 1233static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1234{
0bed3b56
SY		 1235 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1236
9ba075a6
AK		 1237 if (!msr_mtrr_valid(msr))
1238 return 1;
1239
0bed3b56
SY		 1240 if (msr == MSR_MTRRdefType)
1241 *pdata = vcpu->arch.mtrr_state.def_type +
1242 (vcpu->arch.mtrr_state.enabled << 10);
1243 else if (msr == MSR_MTRRfix64K_00000)
1244 *pdata = p[0];
1245 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1246 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1247 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1248 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1249 else if (msr == MSR_IA32_CR_PAT)
1250 *pdata = vcpu->arch.pat;
1251 else { /* Variable MTRRs */
1252 int idx, is_mtrr_mask;
1253 u64 *pt;
1254
1255 idx = (msr - 0x200) / 2;
1256 is_mtrr_mask = msr - 0x200 - 2 * idx;
1257 if (!is_mtrr_mask)
1258 pt =
1259 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1260 else
1261 pt =
1262 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1263 *pdata = *pt;
1264 }
1265
9ba075a6
AK		 1266 return 0;
1267}
1268
890ca9ae 1269static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1270{
1271 u64 data;
890ca9ae
HY		 1272 u64 mcg_cap = vcpu->arch.mcg_cap;
1273 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1274
1275 switch (msr) {
15c4a640
CO		 1276 case MSR_IA32_P5_MC_ADDR:
1277 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1278 data = 0;
1279 break;
15c4a640 1280 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1281 data = vcpu->arch.mcg_cap;
1282 break;
c7ac679c 1283 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1284 if (!(mcg_cap & MCG_CTL_P))
1285 return 1;
1286 data = vcpu->arch.mcg_ctl;
1287 break;
1288 case MSR_IA32_MCG_STATUS:
1289 data = vcpu->arch.mcg_status;
1290 break;
1291 default:
1292 if (msr >= MSR_IA32_MC0_CTL &&
1293 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1294 u32 offset = msr - MSR_IA32_MC0_CTL;
1295 data = vcpu->arch.mce_banks[offset];
1296 break;
1297 }
1298 return 1;
1299 }
1300 *pdata = data;
1301 return 0;
1302}
1303
55cd8e5a
GN		 1304static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1305{
1306 u64 data = 0;
1307 struct kvm *kvm = vcpu->kvm;
1308
1309 switch (msr) {
1310 case HV_X64_MSR_GUEST_OS_ID:
1311 data = kvm->arch.hv_guest_os_id;
1312 break;
1313 case HV_X64_MSR_HYPERCALL:
1314 data = kvm->arch.hv_hypercall;
1315 break;
1316 default:
1317 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1318 return 1;
1319 }
1320
1321 *pdata = data;
1322 return 0;
1323}
1324
1325static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1326{
1327 u64 data = 0;
1328
1329 switch (msr) {
1330 case HV_X64_MSR_VP_INDEX: {
1331 int r;
1332 struct kvm_vcpu *v;
1333 kvm_for_each_vcpu(r, v, vcpu->kvm)
1334 if (v == vcpu)
1335 data = r;
1336 break;
1337 }
10388a07
GN		 1338 case HV_X64_MSR_EOI:
1339 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1340 case HV_X64_MSR_ICR:
1341 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1342 case HV_X64_MSR_TPR:
1343 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1344 default:
1345 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1346 return 1;
1347 }
1348 *pdata = data;
1349 return 0;
1350}
1351
890ca9ae
HY		 1352int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1353{
1354 u64 data;
1355
1356 switch (msr) {
890ca9ae 1357 case MSR_IA32_PLATFORM_ID:
15c4a640 1358 case MSR_IA32_UCODE_REV:
15c4a640 1359 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1360 case MSR_IA32_DEBUGCTLMSR:
1361 case MSR_IA32_LASTBRANCHFROMIP:
1362 case MSR_IA32_LASTBRANCHTOIP:
1363 case MSR_IA32_LASTINTFROMIP:
1364 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1365 case MSR_K8_SYSCFG:
1366 case MSR_K7_HWCR:
61a6bd67 1367 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1368 case MSR_P6_PERFCTR0:
1369 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1370 case MSR_P6_EVNTSEL0:
1371 case MSR_P6_EVNTSEL1:
9e699624 1372 case MSR_K7_EVNTSEL0:
1f3ee616 1373 case MSR_K7_PERFCTR0:
1fdbd48c 1374 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1375 case MSR_AMD64_NB_CFG:
f7c6d140 1376 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1377 data = 0;
1378 break;
9ba075a6
AK		 1379 case MSR_MTRRcap:
1380 data = 0x500 | KVM_NR_VAR_MTRR;
1381 break;
1382 case 0x200 ... 0x2ff:
1383 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1384 case 0xcd: /* fsb frequency */
1385 data = 3;
1386 break;
1387 case MSR_IA32_APICBASE:
1388 data = kvm_get_apic_base(vcpu);
1389 break;
0105d1a5
GN		 1390 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1391 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1392 break;
15c4a640 1393 case MSR_IA32_MISC_ENABLE:
ad312c7c 1394 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1395 break;
847f0ad8
AG		 1396 case MSR_IA32_PERF_STATUS:
1397 /* TSC increment by tick */
1398 data = 1000ULL;
1399 /* CPU multiplier */
1400 data |= (((uint64_t)4ULL) << 40);
1401 break;
15c4a640 1402 case MSR_EFER:
f6801dff 1403 data = vcpu->arch.efer;
15c4a640 1404 break;
18068523
GOC		 1405 case MSR_KVM_WALL_CLOCK:
1406 data = vcpu->kvm->arch.wall_clock;
1407 break;
1408 case MSR_KVM_SYSTEM_TIME:
1409 data = vcpu->arch.time;
1410 break;
890ca9ae
HY		 1411 case MSR_IA32_P5_MC_ADDR:
1412 case MSR_IA32_P5_MC_TYPE:
1413 case MSR_IA32_MCG_CAP:
1414 case MSR_IA32_MCG_CTL:
1415 case MSR_IA32_MCG_STATUS:
1416 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1417 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1418 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1419 if (kvm_hv_msr_partition_wide(msr)) {
1420 int r;
1421 mutex_lock(&vcpu->kvm->lock);
1422 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1423 mutex_unlock(&vcpu->kvm->lock);
1424 return r;
1425 } else
1426 return get_msr_hyperv(vcpu, msr, pdata);
1427 break;
15c4a640 1428 default:
ed85c068
AP		 1429 if (!ignore_msrs) {
1430 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1431 return 1;
1432 } else {
1433 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1434 data = 0;
1435 }
1436 break;
15c4a640
CO		 1437 }
1438 *pdata = data;
1439 return 0;
1440}
1441EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1442
313a3dc7
CO		 1443/*
1444 * Read or write a bunch of msrs. All parameters are kernel addresses.
1445 *
1446 * @return number of msrs set successfully.
1447 */
1448static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1449 struct kvm_msr_entry *entries,
1450 int (*do_msr)(struct kvm_vcpu *vcpu,
1451 unsigned index, u64 *data))
1452{
f656ce01 1453 int i, idx;
313a3dc7
CO		 1454
1455 vcpu_load(vcpu);
1456
f656ce01 1457 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1458 for (i = 0; i < msrs->nmsrs; ++i)
1459 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1460 break;
f656ce01 1461 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1462
1463 vcpu_put(vcpu);
1464
1465 return i;
1466}
1467
1468/*
1469 * Read or write a bunch of msrs. Parameters are user addresses.
1470 *
1471 * @return number of msrs set successfully.
1472 */
1473static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1474 int (*do_msr)(struct kvm_vcpu *vcpu,
1475 unsigned index, u64 *data),
1476 int writeback)
1477{
1478 struct kvm_msrs msrs;
1479 struct kvm_msr_entry *entries;
1480 int r, n;
1481 unsigned size;
1482
1483 r = -EFAULT;
1484 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1485 goto out;
1486
1487 r = -E2BIG;
1488 if (msrs.nmsrs >= MAX_IO_MSRS)
1489 goto out;
1490
1491 r = -ENOMEM;
1492 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1493 entries = vmalloc(size);
1494 if (!entries)
1495 goto out;
1496
1497 r = -EFAULT;
1498 if (copy_from_user(entries, user_msrs->entries, size))
1499 goto out_free;
1500
1501 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1502 if (r < 0)
1503 goto out_free;
1504
1505 r = -EFAULT;
1506 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1507 goto out_free;
1508
1509 r = n;
1510
1511out_free:
1512 vfree(entries);
1513out:
1514 return r;
1515}
1516
018d00d2
ZX		 1517int kvm_dev_ioctl_check_extension(long ext)
1518{
1519 int r;
1520
1521 switch (ext) {
1522 case KVM_CAP_IRQCHIP:
1523 case KVM_CAP_HLT:
1524 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1525 case KVM_CAP_SET_TSS_ADDR:
07716717 1526 case KVM_CAP_EXT_CPUID:
c8076604 1527 case KVM_CAP_CLOCKSOURCE:
7837699f 1528 case KVM_CAP_PIT:
a28e4f5a 1529 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1530 case KVM_CAP_MP_STATE:
ed848624 1531 case KVM_CAP_SYNC_MMU:
52d939a0 1532 case KVM_CAP_REINJECT_CONTROL:
4925663a 1533 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1534 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1535 case KVM_CAP_IRQFD:
d34e6b17 1536 case KVM_CAP_IOEVENTFD:
c5ff41ce 1537 case KVM_CAP_PIT2:
e9f42757 1538 case KVM_CAP_PIT_STATE2:
b927a3ce 1539 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1540 case KVM_CAP_XEN_HVM:
afbcf7ab 1541 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1542 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1543 case KVM_CAP_HYPERV:
10388a07 1544 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1545 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1546 case KVM_CAP_PCI_SEGMENT:
d2be1651 1547 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1548 r = 1;
1549 break;
542472b5
LV		 1550 case KVM_CAP_COALESCED_MMIO:
1551 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1552 break;
774ead3a
AK		 1553 case KVM_CAP_VAPIC:
1554 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1555 break;
f725230a
AK		 1556 case KVM_CAP_NR_VCPUS:
1557 r = KVM_MAX_VCPUS;
1558 break;
a988b910
AK		 1559 case KVM_CAP_NR_MEMSLOTS:
1560 r = KVM_MEMORY_SLOTS;
1561 break;
a68a6a72
MT		 1562 case KVM_CAP_PV_MMU: /* obsolete */
1563 r = 0;
2f333bcb 1564 break;
62c476c7 1565 case KVM_CAP_IOMMU:
19de40a8 1566 r = iommu_found();
62c476c7 1567 break;
890ca9ae
HY		 1568 case KVM_CAP_MCE:
1569 r = KVM_MAX_MCE_BANKS;
1570 break;
018d00d2
ZX		 1571 default:
1572 r = 0;
1573 break;
1574 }
1575 return r;
1576
1577}
1578
043405e1
CO		 1579long kvm_arch_dev_ioctl(struct file *filp,
1580 unsigned int ioctl, unsigned long arg)
1581{
1582 void __user *argp = (void __user *)arg;
1583 long r;
1584
1585 switch (ioctl) {
1586 case KVM_GET_MSR_INDEX_LIST: {
1587 struct kvm_msr_list __user *user_msr_list = argp;
1588 struct kvm_msr_list msr_list;
1589 unsigned n;
1590
1591 r = -EFAULT;
1592 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1593 goto out;
1594 n = msr_list.nmsrs;
1595 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1596 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1597 goto out;
1598 r = -E2BIG;
e125e7b6 1599 if (n < msr_list.nmsrs)
043405e1
CO		 1600 goto out;
1601 r = -EFAULT;
1602 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1603 num_msrs_to_save * sizeof(u32)))
1604 goto out;
e125e7b6 1605 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1606 &emulated_msrs,
1607 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1608 goto out;
1609 r = 0;
1610 break;
1611 }
674eea0f
AK		 1612 case KVM_GET_SUPPORTED_CPUID: {
1613 struct kvm_cpuid2 __user *cpuid_arg = argp;
1614 struct kvm_cpuid2 cpuid;
1615
1616 r = -EFAULT;
1617 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1618 goto out;
1619 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1620 cpuid_arg->entries);
674eea0f
AK		 1621 if (r)
1622 goto out;
1623
1624 r = -EFAULT;
1625 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1626 goto out;
1627 r = 0;
1628 break;
1629 }
890ca9ae
HY		 1630 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1631 u64 mce_cap;
1632
1633 mce_cap = KVM_MCE_CAP_SUPPORTED;
1634 r = -EFAULT;
1635 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1636 goto out;
1637 r = 0;
1638 break;
1639 }
043405e1
CO		 1640 default:
1641 r = -EINVAL;
1642 }
1643out:
1644 return r;
1645}
1646
313a3dc7
CO		 1647void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1648{
1649 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1650 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1651 unsigned long khz = cpufreq_quick_get(cpu);
1652 if (!khz)
1653 khz = tsc_khz;
1654 per_cpu(cpu_tsc_khz, cpu) = khz;
1655 }
c8076604 1656 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1657}
1658
1659void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1660{
9327fd11 1661 kvm_put_guest_fpu(vcpu);
02daab21 1662 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1663}
1664
07716717 1665static int is_efer_nx(void)
313a3dc7 1666{
e286e86e 1667 unsigned long long efer = 0;
313a3dc7 1668
e286e86e 1669 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1670 return efer & EFER_NX;
1671}
1672
1673static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1674{
1675 int i;
1676 struct kvm_cpuid_entry2 *e, *entry;
1677
313a3dc7 1678 entry = NULL;
ad312c7c
ZX		 1679 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1680 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1681 if (e->function == 0x80000001) {
1682 entry = e;
1683 break;
1684 }
1685 }
07716717 1686 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1687 entry->edx &= ~(1 << 20);
1688 printk(KERN_INFO "kvm: guest NX capability removed\n");
1689 }
1690}
1691
07716717 1692/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1693static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1694 struct kvm_cpuid *cpuid,
1695 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1696{
1697 int r, i;
1698 struct kvm_cpuid_entry *cpuid_entries;
1699
1700 r = -E2BIG;
1701 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1702 goto out;
1703 r = -ENOMEM;
1704 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1705 if (!cpuid_entries)
1706 goto out;
1707 r = -EFAULT;
1708 if (copy_from_user(cpuid_entries, entries,
1709 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1710 goto out_free;
1711 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1712 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1713 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1714 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1715 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1716 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1717 vcpu->arch.cpuid_entries[i].index = 0;
1718 vcpu->arch.cpuid_entries[i].flags = 0;
1719 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1720 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1721 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1722 }
1723 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1724 cpuid_fix_nx_cap(vcpu);
1725 r = 0;
fc61b800 1726 kvm_apic_set_version(vcpu);
0e851880 1727 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1728
1729out_free:
1730 vfree(cpuid_entries);
1731out:
1732 return r;
1733}
1734
1735static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1736 struct kvm_cpuid2 *cpuid,
1737 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1738{
1739 int r;
1740
1741 r = -E2BIG;
1742 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1743 goto out;
1744 r = -EFAULT;
ad312c7c 1745 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1746 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1747 goto out;
ad312c7c 1748 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1749 kvm_apic_set_version(vcpu);
0e851880 1750 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1751 return 0;
1752
1753out:
1754 return r;
1755}
1756
07716717 1757static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1758 struct kvm_cpuid2 *cpuid,
1759 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1760{
1761 int r;
1762
1763 r = -E2BIG;
ad312c7c 1764 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1765 goto out;
1766 r = -EFAULT;
ad312c7c 1767 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1768 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1769 goto out;
1770 return 0;
1771
1772out:
ad312c7c 1773 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1774 return r;
1775}
1776
07716717 1777static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1778 u32 index)
07716717
DK		 1779{
1780 entry->function = function;
1781 entry->index = index;
1782 cpuid_count(entry->function, entry->index,
19355475 1783 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1784 entry->flags = 0;
1785}
1786
7faa4ee1
AK		 1787#define F(x) bit(X86_FEATURE_##x)
1788
07716717
DK		 1789static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1790 u32 index, int *nent, int maxnent)
1791{
7faa4ee1 1792 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1793#ifdef CONFIG_X86_64
17cc3935
SY		 1794 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1795 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1796 unsigned f_lm = F(LM);
1797#else
17cc3935 1798 unsigned f_gbpages = 0;
7faa4ee1 1799 unsigned f_lm = 0;
07716717 1800#endif
4e47c7a6 1801 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1802
1803 /* cpuid 1.edx */
1804 const u32 kvm_supported_word0_x86_features =
1805 F(FPU) | F(VME) | F(DE) | F(PSE) |
1806 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1807 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1808 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1809 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1810 0 /* Reserved, DS, ACPI */ | F(MMX) |
1811 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1812 0 /* HTT, TM, Reserved, PBE */;
1813 /* cpuid 0x80000001.edx */
1814 const u32 kvm_supported_word1_x86_features =
1815 F(FPU) | F(VME) | F(DE) | F(PSE) |
1816 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1817 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1818 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1819 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1820 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1821 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1822 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1823 /* cpuid 1.ecx */
1824 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1825 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1826 0 /* DS-CPL, VMX, SMX, EST */ |
1827 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1828 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1829 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1830 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1831 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1832 /* cpuid 0x80000001.ecx */
07716717 1833 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1834 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1835 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1836 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1837 0 /* SKINIT */ | 0 /* WDT */;
07716717 1838
19355475 1839 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1840 get_cpu();
1841 do_cpuid_1_ent(entry, function, index);
1842 ++*nent;
1843
1844 switch (function) {
1845 case 0:
1846 entry->eax = min(entry->eax, (u32)0xb);
1847 break;
1848 case 1:
1849 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1850 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1851 /* we support x2apic emulation even if host does not support
1852 * it since we emulate x2apic in software */
1853 entry->ecx |= F(X2APIC);
07716717
DK		 1854 break;
1855 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1856 * may return different values. This forces us to get_cpu() before
1857 * issuing the first command, and also to emulate this annoying behavior
1858 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1859 case 2: {
1860 int t, times = entry->eax & 0xff;
1861
1862 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1863 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1864 for (t = 1; t < times && *nent < maxnent; ++t) {
1865 do_cpuid_1_ent(&entry[t], function, 0);
1866 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1867 ++*nent;
1868 }
1869 break;
1870 }
1871 /* function 4 and 0xb have additional index. */
1872 case 4: {
14af3f3c 1873 int i, cache_type;
07716717
DK		 1874
1875 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1876 /* read more entries until cache_type is zero */
14af3f3c
HH		 1877 for (i = 1; *nent < maxnent; ++i) {
1878 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1879 if (!cache_type)
1880 break;
14af3f3c
HH		 1881 do_cpuid_1_ent(&entry[i], function, i);
1882 entry[i].flags |=
07716717
DK		 1883 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1884 ++*nent;
1885 }
1886 break;
1887 }
1888 case 0xb: {
14af3f3c 1889 int i, level_type;
07716717
DK		 1890
1891 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1892 /* read more entries until level_type is zero */
14af3f3c 1893 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1894 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1895 if (!level_type)
1896 break;
14af3f3c
HH		 1897 do_cpuid_1_ent(&entry[i], function, i);
1898 entry[i].flags |=
07716717
DK		 1899 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1900 ++*nent;
1901 }
1902 break;
1903 }
1904 case 0x80000000:
1905 entry->eax = min(entry->eax, 0x8000001a);
1906 break;
1907 case 0x80000001:
1908 entry->edx &= kvm_supported_word1_x86_features;
1909 entry->ecx &= kvm_supported_word6_x86_features;
1910 break;
1911 }
1912 put_cpu();
1913}
1914
7faa4ee1
AK		 1915#undef F
1916
674eea0f 1917static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1918 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1919{
1920 struct kvm_cpuid_entry2 *cpuid_entries;
1921 int limit, nent = 0, r = -E2BIG;
1922 u32 func;
1923
1924 if (cpuid->nent < 1)
1925 goto out;
6a544355
AK		 1926 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1927 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1928 r = -ENOMEM;
1929 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1930 if (!cpuid_entries)
1931 goto out;
1932
1933 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1934 limit = cpuid_entries[0].eax;
1935 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1936 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1937 &nent, cpuid->nent);
07716717
DK		 1938 r = -E2BIG;
1939 if (nent >= cpuid->nent)
1940 goto out_free;
1941
1942 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1943 limit = cpuid_entries[nent - 1].eax;
1944 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1945 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1946 &nent, cpuid->nent);
cb007648
MM		 1947 r = -E2BIG;
1948 if (nent >= cpuid->nent)
1949 goto out_free;
1950
07716717
DK		 1951 r = -EFAULT;
1952 if (copy_to_user(entries, cpuid_entries,
19355475 1953 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1954 goto out_free;
1955 cpuid->nent = nent;
1956 r = 0;
1957
1958out_free:
1959 vfree(cpuid_entries);
1960out:
1961 return r;
1962}
1963
313a3dc7
CO		 1964static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1965 struct kvm_lapic_state *s)
1966{
1967 vcpu_load(vcpu);
ad312c7c 1968 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1969 vcpu_put(vcpu);
1970
1971 return 0;
1972}
1973
1974static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1975 struct kvm_lapic_state *s)
1976{
1977 vcpu_load(vcpu);
ad312c7c 1978 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1979 kvm_apic_post_state_restore(vcpu);
cb142eb7 1980 update_cr8_intercept(vcpu);
313a3dc7
CO		 1981 vcpu_put(vcpu);
1982
1983 return 0;
1984}
1985
f77bc6a4
ZX		 1986static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1987 struct kvm_interrupt *irq)
1988{
1989 if (irq->irq < 0 || irq->irq >= 256)
1990 return -EINVAL;
1991 if (irqchip_in_kernel(vcpu->kvm))
1992 return -ENXIO;
1993 vcpu_load(vcpu);
1994
66fd3f7f 1995 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1996
1997 vcpu_put(vcpu);
1998
1999 return 0;
2000}
2001
c4abb7c9
JK		 2002static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2003{
2004 vcpu_load(vcpu);
2005 kvm_inject_nmi(vcpu);
2006 vcpu_put(vcpu);
2007
2008 return 0;
2009}
2010
b209749f
AK		 2011static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2012 struct kvm_tpr_access_ctl *tac)
2013{
2014 if (tac->flags)
2015 return -EINVAL;
2016 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2017 return 0;
2018}
2019
890ca9ae
HY		 2020static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2021 u64 mcg_cap)
2022{
2023 int r;
2024 unsigned bank_num = mcg_cap & 0xff, bank;
2025
2026 r = -EINVAL;
a9e38c3e 2027 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2028 goto out;
2029 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2030 goto out;
2031 r = 0;
2032 vcpu->arch.mcg_cap = mcg_cap;
2033 /* Init IA32_MCG_CTL to all 1s */
2034 if (mcg_cap & MCG_CTL_P)
2035 vcpu->arch.mcg_ctl = ~(u64)0;
2036 /* Init IA32_MCi_CTL to all 1s */
2037 for (bank = 0; bank < bank_num; bank++)
2038 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2039out:
2040 return r;
2041}
2042
2043static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2044 struct kvm_x86_mce *mce)
2045{
2046 u64 mcg_cap = vcpu->arch.mcg_cap;
2047 unsigned bank_num = mcg_cap & 0xff;
2048 u64 *banks = vcpu->arch.mce_banks;
2049
2050 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2051 return -EINVAL;
2052 /*
2053 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2054 * reporting is disabled
2055 */
2056 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2057 vcpu->arch.mcg_ctl != ~(u64)0)
2058 return 0;
2059 banks += 4 * mce->bank;
2060 /*
2061 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2062 * reporting is disabled for the bank
2063 */
2064 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2065 return 0;
2066 if (mce->status & MCI_STATUS_UC) {
2067 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2068 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2069 printk(KERN_DEBUG "kvm: set_mce: "
2070 "injects mce exception while "
2071 "previous one is in progress!\n");
2072 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2073 return 0;
2074 }
2075 if (banks[1] & MCI_STATUS_VAL)
2076 mce->status |= MCI_STATUS_OVER;
2077 banks[2] = mce->addr;
2078 banks[3] = mce->misc;
2079 vcpu->arch.mcg_status = mce->mcg_status;
2080 banks[1] = mce->status;
2081 kvm_queue_exception(vcpu, MC_VECTOR);
2082 } else if (!(banks[1] & MCI_STATUS_VAL)
2083 || !(banks[1] & MCI_STATUS_UC)) {
2084 if (banks[1] & MCI_STATUS_VAL)
2085 mce->status |= MCI_STATUS_OVER;
2086 banks[2] = mce->addr;
2087 banks[3] = mce->misc;
2088 banks[1] = mce->status;
2089 } else
2090 banks[1] |= MCI_STATUS_OVER;
2091 return 0;
2092}
2093
3cfc3092
JK		 2094static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2095 struct kvm_vcpu_events *events)
2096{
2097 vcpu_load(vcpu);
2098
2099 events->exception.injected = vcpu->arch.exception.pending;
2100 events->exception.nr = vcpu->arch.exception.nr;
2101 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2102 events->exception.error_code = vcpu->arch.exception.error_code;
2103
2104 events->interrupt.injected = vcpu->arch.interrupt.pending;
2105 events->interrupt.nr = vcpu->arch.interrupt.nr;
2106 events->interrupt.soft = vcpu->arch.interrupt.soft;
2107
2108 events->nmi.injected = vcpu->arch.nmi_injected;
2109 events->nmi.pending = vcpu->arch.nmi_pending;
2110 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2111
2112 events->sipi_vector = vcpu->arch.sipi_vector;
2113
dab4b911
JK		 2114 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2115 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 2116
2117 vcpu_put(vcpu);
2118}
2119
2120static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2121 struct kvm_vcpu_events *events)
2122{
dab4b911
JK		 2123 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2124 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 2125 return -EINVAL;
2126
2127 vcpu_load(vcpu);
2128
2129 vcpu->arch.exception.pending = events->exception.injected;
2130 vcpu->arch.exception.nr = events->exception.nr;
2131 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2132 vcpu->arch.exception.error_code = events->exception.error_code;
2133
2134 vcpu->arch.interrupt.pending = events->interrupt.injected;
2135 vcpu->arch.interrupt.nr = events->interrupt.nr;
2136 vcpu->arch.interrupt.soft = events->interrupt.soft;
2137 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2138 kvm_pic_clear_isr_ack(vcpu->kvm);
2139
2140 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2141 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2142 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2143 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2144
dab4b911
JK		 2145 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2146 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2147
2148 vcpu_put(vcpu);
2149
2150 return 0;
2151}
2152
313a3dc7
CO		 2153long kvm_arch_vcpu_ioctl(struct file *filp,
2154 unsigned int ioctl, unsigned long arg)
2155{
2156 struct kvm_vcpu *vcpu = filp->private_data;
2157 void __user *argp = (void __user *)arg;
2158 int r;
b772ff36 2159 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2160
2161 switch (ioctl) {
2162 case KVM_GET_LAPIC: {
2204ae3c
MT		 2163 r = -EINVAL;
2164 if (!vcpu->arch.apic)
2165 goto out;
b772ff36 2166 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2167
b772ff36
DH		 2168 r = -ENOMEM;
2169 if (!lapic)
2170 goto out;
2171 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2172 if (r)
2173 goto out;
2174 r = -EFAULT;
b772ff36 2175 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2176 goto out;
2177 r = 0;
2178 break;
2179 }
2180 case KVM_SET_LAPIC: {
2204ae3c
MT		 2181 r = -EINVAL;
2182 if (!vcpu->arch.apic)
2183 goto out;
b772ff36
DH		 2184 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2185 r = -ENOMEM;
2186 if (!lapic)
2187 goto out;
313a3dc7 2188 r = -EFAULT;
b772ff36 2189 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2190 goto out;
b772ff36 2191 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2192 if (r)
2193 goto out;
2194 r = 0;
2195 break;
2196 }
f77bc6a4
ZX		 2197 case KVM_INTERRUPT: {
2198 struct kvm_interrupt irq;
2199
2200 r = -EFAULT;
2201 if (copy_from_user(&irq, argp, sizeof irq))
2202 goto out;
2203 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2204 if (r)
2205 goto out;
2206 r = 0;
2207 break;
2208 }
c4abb7c9
JK		 2209 case KVM_NMI: {
2210 r = kvm_vcpu_ioctl_nmi(vcpu);
2211 if (r)
2212 goto out;
2213 r = 0;
2214 break;
2215 }
313a3dc7
CO		 2216 case KVM_SET_CPUID: {
2217 struct kvm_cpuid __user *cpuid_arg = argp;
2218 struct kvm_cpuid cpuid;
2219
2220 r = -EFAULT;
2221 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2222 goto out;
2223 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2224 if (r)
2225 goto out;
2226 break;
2227 }
07716717
DK		 2228 case KVM_SET_CPUID2: {
2229 struct kvm_cpuid2 __user *cpuid_arg = argp;
2230 struct kvm_cpuid2 cpuid;
2231
2232 r = -EFAULT;
2233 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2234 goto out;
2235 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2236 cpuid_arg->entries);
07716717
DK		 2237 if (r)
2238 goto out;
2239 break;
2240 }
2241 case KVM_GET_CPUID2: {
2242 struct kvm_cpuid2 __user *cpuid_arg = argp;
2243 struct kvm_cpuid2 cpuid;
2244
2245 r = -EFAULT;
2246 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2247 goto out;
2248 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2249 cpuid_arg->entries);
07716717
DK		 2250 if (r)
2251 goto out;
2252 r = -EFAULT;
2253 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2254 goto out;
2255 r = 0;
2256 break;
2257 }
313a3dc7
CO		 2258 case KVM_GET_MSRS:
2259 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2260 break;
2261 case KVM_SET_MSRS:
2262 r = msr_io(vcpu, argp, do_set_msr, 0);
2263 break;
b209749f
AK		 2264 case KVM_TPR_ACCESS_REPORTING: {
2265 struct kvm_tpr_access_ctl tac;
2266
2267 r = -EFAULT;
2268 if (copy_from_user(&tac, argp, sizeof tac))
2269 goto out;
2270 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2271 if (r)
2272 goto out;
2273 r = -EFAULT;
2274 if (copy_to_user(argp, &tac, sizeof tac))
2275 goto out;
2276 r = 0;
2277 break;
2278 };
b93463aa
AK		 2279 case KVM_SET_VAPIC_ADDR: {
2280 struct kvm_vapic_addr va;
2281
2282 r = -EINVAL;
2283 if (!irqchip_in_kernel(vcpu->kvm))
2284 goto out;
2285 r = -EFAULT;
2286 if (copy_from_user(&va, argp, sizeof va))
2287 goto out;
2288 r = 0;
2289 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2290 break;
2291 }
890ca9ae
HY		 2292 case KVM_X86_SETUP_MCE: {
2293 u64 mcg_cap;
2294
2295 r = -EFAULT;
2296 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2297 goto out;
2298 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2299 break;
2300 }
2301 case KVM_X86_SET_MCE: {
2302 struct kvm_x86_mce mce;
2303
2304 r = -EFAULT;
2305 if (copy_from_user(&mce, argp, sizeof mce))
2306 goto out;
2307 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2308 break;
2309 }
3cfc3092
JK		 2310 case KVM_GET_VCPU_EVENTS: {
2311 struct kvm_vcpu_events events;
2312
2313 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2314
2315 r = -EFAULT;
2316 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2317 break;
2318 r = 0;
2319 break;
2320 }
2321 case KVM_SET_VCPU_EVENTS: {
2322 struct kvm_vcpu_events events;
2323
2324 r = -EFAULT;
2325 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2326 break;
2327
2328 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2329 break;
2330 }
313a3dc7
CO		 2331 default:
2332 r = -EINVAL;
2333 }
2334out:
7a6ce84c 2335 kfree(lapic);
313a3dc7
CO		 2336 return r;
2337}
2338
1fe779f8
CO		 2339static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2340{
2341 int ret;
2342
2343 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2344 return -1;
2345 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2346 return ret;
2347}
2348
b927a3ce
SY		 2349static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2350 u64 ident_addr)
2351{
2352 kvm->arch.ept_identity_map_addr = ident_addr;
2353 return 0;
2354}
2355
1fe779f8
CO		 2356static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2357 u32 kvm_nr_mmu_pages)
2358{
2359 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2360 return -EINVAL;
2361
79fac95e 2362 mutex_lock(&kvm->slots_lock);
7c8a83b7 2363 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2364
2365 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2366 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2367
7c8a83b7 2368 spin_unlock(&kvm->mmu_lock);
79fac95e 2369 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2370 return 0;
2371}
2372
2373static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2374{
f05e70ac 2375 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2376}
2377
a983fb23
MT		 2378gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2379{
2380 int i;
2381 struct kvm_mem_alias *alias;
2382 struct kvm_mem_aliases *aliases;
2383
2384 aliases = rcu_dereference(kvm->arch.aliases);
2385
2386 for (i = 0; i < aliases->naliases; ++i) {
2387 alias = &aliases->aliases[i];
2388 if (alias->flags & KVM_ALIAS_INVALID)
2389 continue;
2390 if (gfn >= alias->base_gfn
2391 && gfn < alias->base_gfn + alias->npages)
2392 return alias->target_gfn + gfn - alias->base_gfn;
2393 }
2394 return gfn;
2395}
2396
e9f85cde
ZX		 2397gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2398{
2399 int i;
2400 struct kvm_mem_alias *alias;
a983fb23
MT		 2401 struct kvm_mem_aliases *aliases;
2402
2403 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2404
fef9cce0
MT		 2405 for (i = 0; i < aliases->naliases; ++i) {
2406 alias = &aliases->aliases[i];
e9f85cde
ZX		 2407 if (gfn >= alias->base_gfn
2408 && gfn < alias->base_gfn + alias->npages)
2409 return alias->target_gfn + gfn - alias->base_gfn;
2410 }
2411 return gfn;
2412}
2413
1fe779f8
CO		 2414/*
2415 * Set a new alias region. Aliases map a portion of physical memory into
2416 * another portion. This is useful for memory windows, for example the PC
2417 * VGA region.
2418 */
2419static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2420 struct kvm_memory_alias *alias)
2421{
2422 int r, n;
2423 struct kvm_mem_alias *p;
a983fb23 2424 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2425
2426 r = -EINVAL;
2427 /* General sanity checks */
2428 if (alias->memory_size & (PAGE_SIZE - 1))
2429 goto out;
2430 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2431 goto out;
2432 if (alias->slot >= KVM_ALIAS_SLOTS)
2433 goto out;
2434 if (alias->guest_phys_addr + alias->memory_size
2435 < alias->guest_phys_addr)
2436 goto out;
2437 if (alias->target_phys_addr + alias->memory_size
2438 < alias->target_phys_addr)
2439 goto out;
2440
a983fb23
MT		 2441 r = -ENOMEM;
2442 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2443 if (!aliases)
2444 goto out;
2445
79fac95e 2446 mutex_lock(&kvm->slots_lock);
1fe779f8 2447
a983fb23
MT		 2448 /* invalidate any gfn reference in case of deletion/shrinking */
2449 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2450 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2451 old_aliases = kvm->arch.aliases;
2452 rcu_assign_pointer(kvm->arch.aliases, aliases);
2453 synchronize_srcu_expedited(&kvm->srcu);
2454 kvm_mmu_zap_all(kvm);
2455 kfree(old_aliases);
2456
2457 r = -ENOMEM;
2458 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2459 if (!aliases)
2460 goto out_unlock;
2461
2462 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2463
2464 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2465 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2466 p->npages = alias->memory_size >> PAGE_SHIFT;
2467 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2468 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2469
2470 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2471 if (aliases->aliases[n - 1].npages)
1fe779f8 2472 break;
fef9cce0 2473 aliases->naliases = n;
1fe779f8 2474
a983fb23
MT		 2475 old_aliases = kvm->arch.aliases;
2476 rcu_assign_pointer(kvm->arch.aliases, aliases);
2477 synchronize_srcu_expedited(&kvm->srcu);
2478 kfree(old_aliases);
2479 r = 0;
1fe779f8 2480
a983fb23 2481out_unlock:
79fac95e 2482 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2483out:
2484 return r;
2485}
2486
2487static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2488{
2489 int r;
2490
2491 r = 0;
2492 switch (chip->chip_id) {
2493 case KVM_IRQCHIP_PIC_MASTER:
2494 memcpy(&chip->chip.pic,
2495 &pic_irqchip(kvm)->pics[0],
2496 sizeof(struct kvm_pic_state));
2497 break;
2498 case KVM_IRQCHIP_PIC_SLAVE:
2499 memcpy(&chip->chip.pic,
2500 &pic_irqchip(kvm)->pics[1],
2501 sizeof(struct kvm_pic_state));
2502 break;
2503 case KVM_IRQCHIP_IOAPIC:
eba0226b 2504 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2505 break;
2506 default:
2507 r = -EINVAL;
2508 break;
2509 }
2510 return r;
2511}
2512
2513static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2514{
2515 int r;
2516
2517 r = 0;
2518 switch (chip->chip_id) {
2519 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2520 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2521 memcpy(&pic_irqchip(kvm)->pics[0],
2522 &chip->chip.pic,
2523 sizeof(struct kvm_pic_state));
fa8273e9 2524 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2525 break;
2526 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2527 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2528 memcpy(&pic_irqchip(kvm)->pics[1],
2529 &chip->chip.pic,
2530 sizeof(struct kvm_pic_state));
fa8273e9 2531 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2532 break;
2533 case KVM_IRQCHIP_IOAPIC:
eba0226b 2534 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2535 break;
2536 default:
2537 r = -EINVAL;
2538 break;
2539 }
2540 kvm_pic_update_irq(pic_irqchip(kvm));
2541 return r;
2542}
2543
e0f63cb9
SY		 2544static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2545{
2546 int r = 0;
2547
894a9c55 2548 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2549 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2550 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2551 return r;
2552}
2553
2554static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2555{
2556 int r = 0;
2557
894a9c55 2558 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2559 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2560 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2561 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2562 return r;
2563}
2564
2565static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2566{
2567 int r = 0;
2568
2569 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2570 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2571 sizeof(ps->channels));
2572 ps->flags = kvm->arch.vpit->pit_state.flags;
2573 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2574 return r;
2575}
2576
2577static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2578{
2579 int r = 0, start = 0;
2580 u32 prev_legacy, cur_legacy;
2581 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2582 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2583 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2584 if (!prev_legacy && cur_legacy)
2585 start = 1;
2586 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2587 sizeof(kvm->arch.vpit->pit_state.channels));
2588 kvm->arch.vpit->pit_state.flags = ps->flags;
2589 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2590 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2591 return r;
2592}
2593
52d939a0
MT		 2594static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2595 struct kvm_reinject_control *control)
2596{
2597 if (!kvm->arch.vpit)
2598 return -ENXIO;
894a9c55 2599 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2600 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2601 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2602 return 0;
2603}
2604
5bb064dc
ZX		 2605/*
2606 * Get (and clear) the dirty memory log for a memory slot.
2607 */
2608int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2609 struct kvm_dirty_log *log)
2610{
b050b015 2611 int r, n, i;
5bb064dc 2612 struct kvm_memory_slot *memslot;
b050b015
MT		 2613 unsigned long is_dirty = 0;
2614 unsigned long *dirty_bitmap = NULL;
5bb064dc 2615
79fac95e 2616 mutex_lock(&kvm->slots_lock);
5bb064dc 2617
b050b015
MT		 2618 r = -EINVAL;
2619 if (log->slot >= KVM_MEMORY_SLOTS)
2620 goto out;
2621
2622 memslot = &kvm->memslots->memslots[log->slot];
2623 r = -ENOENT;
2624 if (!memslot->dirty_bitmap)
2625 goto out;
2626
2627 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2628
2629 r = -ENOMEM;
2630 dirty_bitmap = vmalloc(n);
2631 if (!dirty_bitmap)
5bb064dc 2632 goto out;
b050b015
MT		 2633 memset(dirty_bitmap, 0, n);
2634
2635 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2636 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2637
2638 /* If nothing is dirty, don't bother messing with page tables. */
2639 if (is_dirty) {
b050b015
MT		 2640 struct kvm_memslots *slots, *old_slots;
2641
7c8a83b7 2642 spin_lock(&kvm->mmu_lock);
5bb064dc 2643 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2644 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2645
2646 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2647 if (!slots)
2648 goto out_free;
2649
2650 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2651 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2652
2653 old_slots = kvm->memslots;
2654 rcu_assign_pointer(kvm->memslots, slots);
2655 synchronize_srcu_expedited(&kvm->srcu);
2656 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2657 kfree(old_slots);
5bb064dc 2658 }
b050b015 2659
5bb064dc 2660 r = 0;
b050b015
MT		 2661 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2662 r = -EFAULT;
2663out_free:
2664 vfree(dirty_bitmap);
5bb064dc 2665out:
79fac95e 2666 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2667 return r;
2668}
2669
1fe779f8
CO		 2670long kvm_arch_vm_ioctl(struct file *filp,
2671 unsigned int ioctl, unsigned long arg)
2672{
2673 struct kvm *kvm = filp->private_data;
2674 void __user *argp = (void __user *)arg;
367e1319 2675 int r = -ENOTTY;
f0d66275
DH		 2676 /*
2677 * This union makes it completely explicit to gcc-3.x
2678 * that these two variables' stack usage should be
2679 * combined, not added together.
2680 */
2681 union {
2682 struct kvm_pit_state ps;
e9f42757 2683 struct kvm_pit_state2 ps2;
f0d66275 2684 struct kvm_memory_alias alias;
c5ff41ce 2685 struct kvm_pit_config pit_config;
f0d66275 2686 } u;
1fe779f8
CO		 2687
2688 switch (ioctl) {
2689 case KVM_SET_TSS_ADDR:
2690 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2691 if (r < 0)
2692 goto out;
2693 break;
b927a3ce
SY		 2694 case KVM_SET_IDENTITY_MAP_ADDR: {
2695 u64 ident_addr;
2696
2697 r = -EFAULT;
2698 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2699 goto out;
2700 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2701 if (r < 0)
2702 goto out;
2703 break;
2704 }
1fe779f8
CO		 2705 case KVM_SET_MEMORY_REGION: {
2706 struct kvm_memory_region kvm_mem;
2707 struct kvm_userspace_memory_region kvm_userspace_mem;
2708
2709 r = -EFAULT;
2710 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2711 goto out;
2712 kvm_userspace_mem.slot = kvm_mem.slot;
2713 kvm_userspace_mem.flags = kvm_mem.flags;
2714 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2715 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2716 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2717 if (r)
2718 goto out;
2719 break;
2720 }
2721 case KVM_SET_NR_MMU_PAGES:
2722 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2723 if (r)
2724 goto out;
2725 break;
2726 case KVM_GET_NR_MMU_PAGES:
2727 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2728 break;
f0d66275 2729 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2730 r = -EFAULT;
f0d66275 2731 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2732 goto out;
f0d66275 2733 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2734 if (r)
2735 goto out;
2736 break;
3ddea128
MT		 2737 case KVM_CREATE_IRQCHIP: {
2738 struct kvm_pic *vpic;
2739
2740 mutex_lock(&kvm->lock);
2741 r = -EEXIST;
2742 if (kvm->arch.vpic)
2743 goto create_irqchip_unlock;
1fe779f8 2744 r = -ENOMEM;
3ddea128
MT		 2745 vpic = kvm_create_pic(kvm);
2746 if (vpic) {
1fe779f8
CO		 2747 r = kvm_ioapic_init(kvm);
2748 if (r) {
72bb2fcd
WY		 2749 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2750 &vpic->dev);
3ddea128
MT		 2751 kfree(vpic);
2752 goto create_irqchip_unlock;
1fe779f8
CO		 2753 }
2754 } else
3ddea128
MT		 2755 goto create_irqchip_unlock;
2756 smp_wmb();
2757 kvm->arch.vpic = vpic;
2758 smp_wmb();
399ec807
AK		 2759 r = kvm_setup_default_irq_routing(kvm);
2760 if (r) {
3ddea128 2761 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2762 kvm_ioapic_destroy(kvm);
2763 kvm_destroy_pic(kvm);
3ddea128 2764 mutex_unlock(&kvm->irq_lock);
399ec807 2765 }
3ddea128
MT		 2766 create_irqchip_unlock:
2767 mutex_unlock(&kvm->lock);
1fe779f8 2768 break;
3ddea128 2769 }
7837699f 2770 case KVM_CREATE_PIT:
c5ff41ce
JK		 2771 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2772 goto create_pit;
2773 case KVM_CREATE_PIT2:
2774 r = -EFAULT;
2775 if (copy_from_user(&u.pit_config, argp,
2776 sizeof(struct kvm_pit_config)))
2777 goto out;
2778 create_pit:
79fac95e 2779 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2780 r = -EEXIST;
2781 if (kvm->arch.vpit)
2782 goto create_pit_unlock;
7837699f 2783 r = -ENOMEM;
c5ff41ce 2784 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2785 if (kvm->arch.vpit)
2786 r = 0;
269e05e4 2787 create_pit_unlock:
79fac95e 2788 mutex_unlock(&kvm->slots_lock);
7837699f 2789 break;
4925663a 2790 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2791 case KVM_IRQ_LINE: {
2792 struct kvm_irq_level irq_event;
2793
2794 r = -EFAULT;
2795 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2796 goto out;
2797 if (irqchip_in_kernel(kvm)) {
4925663a 2798 __s32 status;
4925663a
GN		 2799 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2800 irq_event.irq, irq_event.level);
4925663a
GN		 2801 if (ioctl == KVM_IRQ_LINE_STATUS) {
2802 irq_event.status = status;
2803 if (copy_to_user(argp, &irq_event,
2804 sizeof irq_event))
2805 goto out;
2806 }
1fe779f8
CO		 2807 r = 0;
2808 }
2809 break;
2810 }
2811 case KVM_GET_IRQCHIP: {
2812 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2813 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2814
f0d66275
DH		 2815 r = -ENOMEM;
2816 if (!chip)
1fe779f8 2817 goto out;
f0d66275
DH		 2818 r = -EFAULT;
2819 if (copy_from_user(chip, argp, sizeof *chip))
2820 goto get_irqchip_out;
1fe779f8
CO		 2821 r = -ENXIO;
2822 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2823 goto get_irqchip_out;
2824 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2825 if (r)
f0d66275 2826 goto get_irqchip_out;
1fe779f8 2827 r = -EFAULT;
f0d66275
DH		 2828 if (copy_to_user(argp, chip, sizeof *chip))
2829 goto get_irqchip_out;
1fe779f8 2830 r = 0;
f0d66275
DH		 2831 get_irqchip_out:
2832 kfree(chip);
2833 if (r)
2834 goto out;
1fe779f8
CO		 2835 break;
2836 }
2837 case KVM_SET_IRQCHIP: {
2838 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2839 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2840
f0d66275
DH		 2841 r = -ENOMEM;
2842 if (!chip)
1fe779f8 2843 goto out;
f0d66275
DH		 2844 r = -EFAULT;
2845 if (copy_from_user(chip, argp, sizeof *chip))
2846 goto set_irqchip_out;
1fe779f8
CO		 2847 r = -ENXIO;
2848 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2849 goto set_irqchip_out;
2850 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2851 if (r)
f0d66275 2852 goto set_irqchip_out;
1fe779f8 2853 r = 0;
f0d66275
DH		 2854 set_irqchip_out:
2855 kfree(chip);
2856 if (r)
2857 goto out;
1fe779f8
CO		 2858 break;
2859 }
e0f63cb9 2860 case KVM_GET_PIT: {
e0f63cb9 2861 r = -EFAULT;
f0d66275 2862 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2863 goto out;
2864 r = -ENXIO;
2865 if (!kvm->arch.vpit)
2866 goto out;
f0d66275 2867 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2868 if (r)
2869 goto out;
2870 r = -EFAULT;
f0d66275 2871 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2872 goto out;
2873 r = 0;
2874 break;
2875 }
2876 case KVM_SET_PIT: {
e0f63cb9 2877 r = -EFAULT;
f0d66275 2878 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2879 goto out;
2880 r = -ENXIO;
2881 if (!kvm->arch.vpit)
2882 goto out;
f0d66275 2883 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2884 if (r)
2885 goto out;
2886 r = 0;
2887 break;
2888 }
e9f42757
BK		 2889 case KVM_GET_PIT2: {
2890 r = -ENXIO;
2891 if (!kvm->arch.vpit)
2892 goto out;
2893 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2894 if (r)
2895 goto out;
2896 r = -EFAULT;
2897 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2898 goto out;
2899 r = 0;
2900 break;
2901 }
2902 case KVM_SET_PIT2: {
2903 r = -EFAULT;
2904 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2905 goto out;
2906 r = -ENXIO;
2907 if (!kvm->arch.vpit)
2908 goto out;
2909 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2910 if (r)
2911 goto out;
2912 r = 0;
2913 break;
2914 }
52d939a0
MT		 2915 case KVM_REINJECT_CONTROL: {
2916 struct kvm_reinject_control control;
2917 r = -EFAULT;
2918 if (copy_from_user(&control, argp, sizeof(control)))
2919 goto out;
2920 r = kvm_vm_ioctl_reinject(kvm, &control);
2921 if (r)
2922 goto out;
2923 r = 0;
2924 break;
2925 }
ffde22ac
ES		 2926 case KVM_XEN_HVM_CONFIG: {
2927 r = -EFAULT;
2928 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2929 sizeof(struct kvm_xen_hvm_config)))
2930 goto out;
2931 r = -EINVAL;
2932 if (kvm->arch.xen_hvm_config.flags)
2933 goto out;
2934 r = 0;
2935 break;
2936 }
afbcf7ab
GC		 2937 case KVM_SET_CLOCK: {
2938 struct timespec now;
2939 struct kvm_clock_data user_ns;
2940 u64 now_ns;
2941 s64 delta;
2942
2943 r = -EFAULT;
2944 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2945 goto out;
2946
2947 r = -EINVAL;
2948 if (user_ns.flags)
2949 goto out;
2950
2951 r = 0;
2952 ktime_get_ts(&now);
2953 now_ns = timespec_to_ns(&now);
2954 delta = user_ns.clock - now_ns;
2955 kvm->arch.kvmclock_offset = delta;
2956 break;
2957 }
2958 case KVM_GET_CLOCK: {
2959 struct timespec now;
2960 struct kvm_clock_data user_ns;
2961 u64 now_ns;
2962
2963 ktime_get_ts(&now);
2964 now_ns = timespec_to_ns(&now);
2965 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2966 user_ns.flags = 0;
2967
2968 r = -EFAULT;
2969 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2970 goto out;
2971 r = 0;
2972 break;
2973 }
2974
1fe779f8
CO		 2975 default:
2976 ;
2977 }
2978out:
2979 return r;
2980}
2981
a16b043c 2982static void kvm_init_msr_list(void)
043405e1
CO		 2983{
2984 u32 dummy[2];
2985 unsigned i, j;
2986
e3267cbb
GC		 2987 /* skip the first msrs in the list. KVM-specific */
2988 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2989 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2990 continue;
2991 if (j < i)
2992 msrs_to_save[j] = msrs_to_save[i];
2993 j++;
2994 }
2995 num_msrs_to_save = j;
2996}
2997
bda9020e
MT		 2998static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2999 const void *v)
bbd9b64e 3000{
bda9020e
MT		 3001 if (vcpu->arch.apic &&
3002 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3003 return 0;
bbd9b64e 3004
e93f8a0f 3005 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3006}
3007
bda9020e 3008static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3009{
bda9020e
MT		 3010 if (vcpu->arch.apic &&
3011 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3012 return 0;
bbd9b64e 3013
e93f8a0f 3014 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3015}
3016
1871c602
GN		 3017gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3018{
3019 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3020 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3021}
3022
3023 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3024{
3025 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3026 access |= PFERR_FETCH_MASK;
3027 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3028}
3029
3030gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3031{
3032 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3033 access |= PFERR_WRITE_MASK;
3034 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3035}
3036
3037/* uses this to access any guest's mapped memory without checking CPL */
3038gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3039{
3040 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3041}
3042
3043static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3044 struct kvm_vcpu *vcpu, u32 access,
3045 u32 *error)
bbd9b64e
CO		 3046{
3047 void *data = val;
10589a46 3048 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3049
3050 while (bytes) {
1871c602 3051 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3052 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3053 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3054 int ret;
3055
10589a46
MT		 3056 if (gpa == UNMAPPED_GVA) {
3057 r = X86EMUL_PROPAGATE_FAULT;
3058 goto out;
3059 }
77c2002e 3060 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3061 if (ret < 0) {
3062 r = X86EMUL_UNHANDLEABLE;
3063 goto out;
3064 }
bbd9b64e 3065
77c2002e
IE		 3066 bytes -= toread;
3067 data += toread;
3068 addr += toread;
bbd9b64e 3069 }
10589a46 3070out:
10589a46 3071 return r;
bbd9b64e 3072}
77c2002e 3073
1871c602
GN		 3074/* used for instruction fetching */
3075static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3076 struct kvm_vcpu *vcpu, u32 *error)
3077{
3078 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3079 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3080 access | PFERR_FETCH_MASK, error);
3081}
3082
3083static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3084 struct kvm_vcpu *vcpu, u32 *error)
3085{
3086 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3087 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3088 error);
3089}
3090
3091static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3092 struct kvm_vcpu *vcpu, u32 *error)
3093{
3094 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3095}
3096
cded19f3 3097static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3098 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3099{
3100 void *data = val;
3101 int r = X86EMUL_CONTINUE;
3102
3103 while (bytes) {
1871c602 3104 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3105 unsigned offset = addr & (PAGE_SIZE-1);
3106 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3107 int ret;
3108
3109 if (gpa == UNMAPPED_GVA) {
3110 r = X86EMUL_PROPAGATE_FAULT;
3111 goto out;
3112 }
3113 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3114 if (ret < 0) {
3115 r = X86EMUL_UNHANDLEABLE;
3116 goto out;
3117 }
3118
3119 bytes -= towrite;
3120 data += towrite;
3121 addr += towrite;
3122 }
3123out:
3124 return r;
3125}
3126
bbd9b64e 3127
bbd9b64e
CO		 3128static int emulator_read_emulated(unsigned long addr,
3129 void *val,
3130 unsigned int bytes,
3131 struct kvm_vcpu *vcpu)
3132{
bbd9b64e 3133 gpa_t gpa;
1871c602 3134 u32 error_code;
bbd9b64e
CO		 3135
3136 if (vcpu->mmio_read_completed) {
3137 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3138 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3139 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3140 vcpu->mmio_read_completed = 0;
3141 return X86EMUL_CONTINUE;
3142 }
3143
1871c602
GN		 3144 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3145
3146 if (gpa == UNMAPPED_GVA) {
3147 kvm_inject_page_fault(vcpu, addr, error_code);
3148 return X86EMUL_PROPAGATE_FAULT;
3149 }
bbd9b64e
CO		 3150
3151 /* For APIC access vmexit */
3152 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3153 goto mmio;
3154
1871c602 3155 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3156 == X86EMUL_CONTINUE)
bbd9b64e 3157 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3158
3159mmio:
3160 /*
3161 * Is this MMIO handled locally?
3162 */
aec51dc4
AK		 3163 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3164 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3165 return X86EMUL_CONTINUE;
3166 }
aec51dc4
AK		 3167
3168 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3169
3170 vcpu->mmio_needed = 1;
3171 vcpu->mmio_phys_addr = gpa;
3172 vcpu->mmio_size = bytes;
3173 vcpu->mmio_is_write = 0;
3174
3175 return X86EMUL_UNHANDLEABLE;
3176}
3177
3200f405 3178int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3179 const void *val, int bytes)
bbd9b64e
CO		 3180{
3181 int ret;
3182
3183 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3184 if (ret < 0)
bbd9b64e 3185 return 0;
ad218f85 3186 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3187 return 1;
3188}
3189
3190static int emulator_write_emulated_onepage(unsigned long addr,
3191 const void *val,
3192 unsigned int bytes,
3193 struct kvm_vcpu *vcpu)
3194{
10589a46 3195 gpa_t gpa;
1871c602 3196 u32 error_code;
10589a46 3197
1871c602 3198 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3199
3200 if (gpa == UNMAPPED_GVA) {
1871c602 3201 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3202 return X86EMUL_PROPAGATE_FAULT;
3203 }
3204
3205 /* For APIC access vmexit */
3206 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3207 goto mmio;
3208
3209 if (emulator_write_phys(vcpu, gpa, val, bytes))
3210 return X86EMUL_CONTINUE;
3211
3212mmio:
aec51dc4 3213 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3214 /*
3215 * Is this MMIO handled locally?
3216 */
bda9020e 3217 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3218 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3219
3220 vcpu->mmio_needed = 1;
3221 vcpu->mmio_phys_addr = gpa;
3222 vcpu->mmio_size = bytes;
3223 vcpu->mmio_is_write = 1;
3224 memcpy(vcpu->mmio_data, val, bytes);
3225
3226 return X86EMUL_CONTINUE;
3227}
3228
3229int emulator_write_emulated(unsigned long addr,
3230 const void *val,
3231 unsigned int bytes,
3232 struct kvm_vcpu *vcpu)
3233{
3234 /* Crossing a page boundary? */
3235 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3236 int rc, now;
3237
3238 now = -addr & ~PAGE_MASK;
3239 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3240 if (rc != X86EMUL_CONTINUE)
3241 return rc;
3242 addr += now;
3243 val += now;
3244 bytes -= now;
3245 }
3246 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3247}
3248EXPORT_SYMBOL_GPL(emulator_write_emulated);
3249
3250static int emulator_cmpxchg_emulated(unsigned long addr,
3251 const void *old,
3252 const void *new,
3253 unsigned int bytes,
3254 struct kvm_vcpu *vcpu)
3255{
9f51e24e 3256 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3257#ifndef CONFIG_X86_64
3258 /* guests cmpxchg8b have to be emulated atomically */
3259 if (bytes == 8) {
10589a46 3260 gpa_t gpa;
2bacc55c 3261 struct page *page;
c0b49b0d 3262 char *kaddr;
2bacc55c
MT		 3263 u64 val;
3264
1871c602 3265 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
10589a46 3266
2bacc55c
MT		 3267 if (gpa == UNMAPPED_GVA ||
3268 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3269 goto emul_write;
3270
3271 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3272 goto emul_write;
3273
3274 val = *(u64 *)new;
72dc67a6 3275
2bacc55c 3276 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3277
c0b49b0d
AM		 3278 kaddr = kmap_atomic(page, KM_USER0);
3279 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3280 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3281 kvm_release_page_dirty(page);
3282 }
3200f405 3283emul_write:
2bacc55c
MT		 3284#endif
3285
bbd9b64e
CO		 3286 return emulator_write_emulated(addr, new, bytes, vcpu);
3287}
3288
3289static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3290{
3291 return kvm_x86_ops->get_segment_base(vcpu, seg);
3292}
3293
3294int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3295{
a7052897 3296 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3297 return X86EMUL_CONTINUE;
3298}
3299
3300int emulate_clts(struct kvm_vcpu *vcpu)
3301{
4d4ec087 3302 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3303 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3304 return X86EMUL_CONTINUE;
3305}
3306
3307int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3308{
c76de350 3309 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3310}
3311
3312int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3313{
3314 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3315
c76de350 3316 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3317}
3318
3319void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3320{
bbd9b64e 3321 u8 opcodes[4];
5fdbf976 3322 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3323 unsigned long rip_linear;
3324
f76c710d 3325 if (!printk_ratelimit())
bbd9b64e
CO		 3326 return;
3327
25be4608
GC		 3328 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3329
1871c602 3330 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3331
3332 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3333 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3334}
3335EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3336
14af3f3c 3337static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3338 .read_std = kvm_read_guest_virt_system,
3339 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3340 .read_emulated = emulator_read_emulated,
3341 .write_emulated = emulator_write_emulated,
3342 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3343};
3344
5fdbf976
MT		 3345static void cache_all_regs(struct kvm_vcpu *vcpu)
3346{
3347 kvm_register_read(vcpu, VCPU_REGS_RAX);
3348 kvm_register_read(vcpu, VCPU_REGS_RSP);
3349 kvm_register_read(vcpu, VCPU_REGS_RIP);
3350 vcpu->arch.regs_dirty = ~0;
3351}
3352
bbd9b64e 3353int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3354 unsigned long cr2,
3355 u16 error_code,
571008da 3356 int emulation_type)
bbd9b64e 3357{
310b5d30 3358 int r, shadow_mask;
571008da 3359 struct decode_cache *c;
851ba692 3360 struct kvm_run *run = vcpu->run;
bbd9b64e 3361
26eef70c 3362 kvm_clear_exception_queue(vcpu);
ad312c7c 3363 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3364 /*
56e82318 3365 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3366 * instead of direct ->regs accesses, can save hundred cycles
3367 * on Intel for instructions that don't read/change RSP, for
3368 * for example.
3369 */
3370 cache_all_regs(vcpu);
bbd9b64e
CO		 3371
3372 vcpu->mmio_is_write = 0;
ad312c7c 3373 vcpu->arch.pio.string = 0;
bbd9b64e 3374
571008da 3375 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3376 int cs_db, cs_l;
3377 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3378
ad312c7c 3379 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3380 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c 3381 vcpu->arch.emulate_ctxt.mode =
a0044755 3382 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3383 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3384 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3385 ? X86EMUL_MODE_PROT64 : cs_db
3386 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3387
ad312c7c 3388 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3389
0cb5762e
AP		 3390 /* Only allow emulation of specific instructions on #UD
3391 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3392 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3393 if (emulation_type & EMULTYPE_TRAP_UD) {
3394 if (!c->twobyte)
3395 return EMULATE_FAIL;
3396 switch (c->b) {
3397 case 0x01: /* VMMCALL */
3398 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3399 return EMULATE_FAIL;
3400 break;
3401 case 0x34: /* sysenter */
3402 case 0x35: /* sysexit */
3403 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3404 return EMULATE_FAIL;
3405 break;
3406 case 0x05: /* syscall */
3407 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3408 return EMULATE_FAIL;
3409 break;
3410 default:
3411 return EMULATE_FAIL;
3412 }
3413
3414 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3415 return EMULATE_FAIL;
3416 }
571008da 3417
f2b5756b 3418 ++vcpu->stat.insn_emulation;
bbd9b64e 3419 if (r) {
f2b5756b 3420 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3421 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3422 return EMULATE_DONE;
3423 return EMULATE_FAIL;
3424 }
3425 }
3426
ba8afb6b
GN		 3427 if (emulation_type & EMULTYPE_SKIP) {
3428 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3429 return EMULATE_DONE;
3430 }
3431
ad312c7c 3432 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3433 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3434
3435 if (r == 0)
3436 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3437
ad312c7c 3438 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3439 return EMULATE_DO_MMIO;
3440
3441 if ((r || vcpu->mmio_is_write) && run) {
3442 run->exit_reason = KVM_EXIT_MMIO;
3443 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3444 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3445 run->mmio.len = vcpu->mmio_size;
3446 run->mmio.is_write = vcpu->mmio_is_write;
3447 }
3448
3449 if (r) {
3450 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3451 return EMULATE_DONE;
3452 if (!vcpu->mmio_needed) {
3453 kvm_report_emulation_failure(vcpu, "mmio");
3454 return EMULATE_FAIL;
3455 }
3456 return EMULATE_DO_MMIO;
3457 }
3458
91586a3b 3459 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3460
3461 if (vcpu->mmio_is_write) {
3462 vcpu->mmio_needed = 0;
3463 return EMULATE_DO_MMIO;
3464 }
3465
3466 return EMULATE_DONE;
3467}
3468EXPORT_SYMBOL_GPL(emulate_instruction);
3469
de7d789a
CO		 3470static int pio_copy_data(struct kvm_vcpu *vcpu)
3471{
ad312c7c 3472 void *p = vcpu->arch.pio_data;
0f346074 3473 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3474 unsigned bytes;
0f346074 3475 int ret;
1871c602 3476 u32 error_code;
de7d789a 3477
ad312c7c
ZX		 3478 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3479 if (vcpu->arch.pio.in)
1871c602 3480 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3481 else
1871c602
GN		 3482 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3483
3484 if (ret == X86EMUL_PROPAGATE_FAULT)
3485 kvm_inject_page_fault(vcpu, q, error_code);
3486
0f346074 3487 return ret;
de7d789a
CO		 3488}
3489
3490int complete_pio(struct kvm_vcpu *vcpu)
3491{
ad312c7c 3492 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3493 long delta;
3494 int r;
5fdbf976 3495 unsigned long val;
de7d789a
CO		 3496
3497 if (!io->string) {
5fdbf976
MT		 3498 if (io->in) {
3499 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3500 memcpy(&val, vcpu->arch.pio_data, io->size);
3501 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3502 }
de7d789a
CO		 3503 } else {
3504 if (io->in) {
3505 r = pio_copy_data(vcpu);
5fdbf976 3506 if (r)
1871c602 3507 goto out;
de7d789a
CO		 3508 }
3509
3510 delta = 1;
3511 if (io->rep) {
3512 delta *= io->cur_count;
3513 /*
3514 * The size of the register should really depend on
3515 * current address size.
3516 */
5fdbf976
MT		 3517 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3518 val -= delta;
3519 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3520 }
3521 if (io->down)
3522 delta = -delta;
3523 delta *= io->size;
5fdbf976
MT		 3524 if (io->in) {
3525 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3526 val += delta;
3527 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3528 } else {
3529 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3530 val += delta;
3531 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3532 }
de7d789a 3533 }
1871c602 3534out:
de7d789a
CO		 3535 io->count -= io->cur_count;
3536 io->cur_count = 0;
3537
3538 return 0;
3539}
3540
bda9020e 3541static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3542{
3543 /* TODO: String I/O for in kernel device */
bda9020e 3544 int r;
de7d789a 3545
ad312c7c 3546 if (vcpu->arch.pio.in)
e93f8a0f 3547 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3548 vcpu->arch.pio.size, pd);
de7d789a 3549 else
e93f8a0f
MT		 3550 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3551 vcpu->arch.pio.port, vcpu->arch.pio.size,
3552 pd);
bda9020e 3553 return r;
de7d789a
CO		 3554}
3555
bda9020e 3556static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3557{
ad312c7c
ZX		 3558 struct kvm_pio_request *io = &vcpu->arch.pio;
3559 void *pd = vcpu->arch.pio_data;
bda9020e 3560 int i, r = 0;
de7d789a 3561
de7d789a 3562 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3563 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3564 io->port, io->size, pd)) {
3565 r = -EOPNOTSUPP;
3566 break;
3567 }
de7d789a
CO		 3568 pd += io->size;
3569 }
bda9020e 3570 return r;
de7d789a
CO		 3571}
3572
851ba692 3573int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3574{
5fdbf976 3575 unsigned long val;
de7d789a 3576
f850e2e6
GN		 3577 trace_kvm_pio(!in, port, size, 1);
3578
de7d789a
CO		 3579 vcpu->run->exit_reason = KVM_EXIT_IO;
3580 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3581 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3582 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3583 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3584 vcpu->run->io.port = vcpu->arch.pio.port = port;
3585 vcpu->arch.pio.in = in;
3586 vcpu->arch.pio.string = 0;
3587 vcpu->arch.pio.down = 0;
ad312c7c 3588 vcpu->arch.pio.rep = 0;
de7d789a 3589
1976d2d2
TY		 3590 if (!vcpu->arch.pio.in) {
3591 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3592 memcpy(vcpu->arch.pio_data, &val, 4);
3593 }
de7d789a 3594
bda9020e 3595 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3596 complete_pio(vcpu);
3597 return 1;
3598 }
3599 return 0;
3600}
3601EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3602
851ba692 3603int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3604 int size, unsigned long count, int down,
3605 gva_t address, int rep, unsigned port)
3606{
3607 unsigned now, in_page;
0f346074 3608 int ret = 0;
de7d789a 3609
f850e2e6
GN		 3610 trace_kvm_pio(!in, port, size, count);
3611
de7d789a
CO		 3612 vcpu->run->exit_reason = KVM_EXIT_IO;
3613 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3614 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3615 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3616 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3617 vcpu->run->io.port = vcpu->arch.pio.port = port;
3618 vcpu->arch.pio.in = in;
3619 vcpu->arch.pio.string = 1;
3620 vcpu->arch.pio.down = down;
ad312c7c 3621 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3622
3623 if (!count) {
3624 kvm_x86_ops->skip_emulated_instruction(vcpu);
3625 return 1;
3626 }
3627
3628 if (!down)
3629 in_page = PAGE_SIZE - offset_in_page(address);
3630 else
3631 in_page = offset_in_page(address) + size;
3632 now = min(count, (unsigned long)in_page / size);
0f346074 3633 if (!now)
de7d789a 3634 now = 1;
de7d789a
CO		 3635 if (down) {
3636 /*
3637 * String I/O in reverse. Yuck. Kill the guest, fix later.
3638 */
3639 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3640 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3641 return 1;
3642 }
3643 vcpu->run->io.count = now;
ad312c7c 3644 vcpu->arch.pio.cur_count = now;
de7d789a 3645
ad312c7c 3646 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3647 kvm_x86_ops->skip_emulated_instruction(vcpu);
3648
0f346074 3649 vcpu->arch.pio.guest_gva = address;
de7d789a 3650
ad312c7c 3651 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3652 /* string PIO write */
3653 ret = pio_copy_data(vcpu);
1871c602 3654 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3655 return 1;
bda9020e 3656 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3657 complete_pio(vcpu);
ad312c7c 3658 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3659 ret = 1;
3660 }
bda9020e
MT		 3661 }
3662 /* no string PIO read support yet */
de7d789a
CO		 3663
3664 return ret;
3665}
3666EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3667
c8076604
GH		 3668static void bounce_off(void *info)
3669{
3670 /* nothing */
3671}
3672
c8076604
GH		 3673static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3674 void *data)
3675{
3676 struct cpufreq_freqs *freq = data;
3677 struct kvm *kvm;
3678 struct kvm_vcpu *vcpu;
3679 int i, send_ipi = 0;
3680
c8076604
GH		 3681 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3682 return 0;
3683 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3684 return 0;
0cca7907 3685 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3686
3687 spin_lock(&kvm_lock);
3688 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3689 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3690 if (vcpu->cpu != freq->cpu)
3691 continue;
3692 if (!kvm_request_guest_time_update(vcpu))
3693 continue;
3694 if (vcpu->cpu != smp_processor_id())
3695 send_ipi++;
3696 }
3697 }
3698 spin_unlock(&kvm_lock);
3699
3700 if (freq->old < freq->new && send_ipi) {
3701 /*
3702 * We upscale the frequency. Must make the guest
3703 * doesn't see old kvmclock values while running with
3704 * the new frequency, otherwise we risk the guest sees
3705 * time go backwards.
3706 *
3707 * In case we update the frequency for another cpu
3708 * (which might be in guest context) send an interrupt
3709 * to kick the cpu out of guest context. Next time
3710 * guest context is entered kvmclock will be updated,
3711 * so the guest will not see stale values.
3712 */
3713 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3714 }
3715 return 0;
3716}
3717
3718static struct notifier_block kvmclock_cpufreq_notifier_block = {
3719 .notifier_call = kvmclock_cpufreq_notifier
3720};
3721
b820cc0c
ZA		 3722static void kvm_timer_init(void)
3723{
3724 int cpu;
3725
b820cc0c 3726 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3727 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3728 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3729 for_each_online_cpu(cpu) {
3730 unsigned long khz = cpufreq_get(cpu);
3731 if (!khz)
3732 khz = tsc_khz;
3733 per_cpu(cpu_tsc_khz, cpu) = khz;
3734 }
0cca7907
ZA		 3735 } else {
3736 for_each_possible_cpu(cpu)
3737 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3738 }
3739}
3740
f8c16bba 3741int kvm_arch_init(void *opaque)
043405e1 3742{
b820cc0c 3743 int r;
f8c16bba
ZX		 3744 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3745
f8c16bba
ZX		 3746 if (kvm_x86_ops) {
3747 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3748 r = -EEXIST;
3749 goto out;
f8c16bba
ZX		 3750 }
3751
3752 if (!ops->cpu_has_kvm_support()) {
3753 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3754 r = -EOPNOTSUPP;
3755 goto out;
f8c16bba
ZX		 3756 }
3757 if (ops->disabled_by_bios()) {
3758 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3759 r = -EOPNOTSUPP;
3760 goto out;
f8c16bba
ZX		 3761 }
3762
97db56ce
AK		 3763 r = kvm_mmu_module_init();
3764 if (r)
3765 goto out;
3766
3767 kvm_init_msr_list();
3768
f8c16bba 3769 kvm_x86_ops = ops;
56c6d28a 3770 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3771 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3772 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3773 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3774
b820cc0c 3775 kvm_timer_init();
c8076604 3776
f8c16bba 3777 return 0;
56c6d28a
ZX		 3778
3779out:
56c6d28a 3780 return r;
043405e1 3781}
8776e519 3782
f8c16bba
ZX		 3783void kvm_arch_exit(void)
3784{
888d256e
JK		 3785 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3786 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3787 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3788 kvm_x86_ops = NULL;
56c6d28a
ZX		 3789 kvm_mmu_module_exit();
3790}
f8c16bba 3791
8776e519
HB		 3792int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3793{
3794 ++vcpu->stat.halt_exits;
3795 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3796 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3797 return 1;
3798 } else {
3799 vcpu->run->exit_reason = KVM_EXIT_HLT;
3800 return 0;
3801 }
3802}
3803EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3804
2f333bcb
MT		 3805static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3806 unsigned long a1)
3807{
3808 if (is_long_mode(vcpu))
3809 return a0;
3810 else
3811 return a0 | ((gpa_t)a1 << 32);
3812}
3813
55cd8e5a
GN		 3814int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3815{
3816 u64 param, ingpa, outgpa, ret;
3817 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3818 bool fast, longmode;
3819 int cs_db, cs_l;
3820
3821 /*
3822 * hypercall generates UD from non zero cpl and real mode
3823 * per HYPER-V spec
3824 */
3eeb3288 3825 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3826 kvm_queue_exception(vcpu, UD_VECTOR);
3827 return 0;
3828 }
3829
3830 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3831 longmode = is_long_mode(vcpu) && cs_l == 1;
3832
3833 if (!longmode) {
ccd46936
GN		 3834 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3835 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3836 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3837 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3838 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3839 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3840 }
3841#ifdef CONFIG_X86_64
3842 else {
3843 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3844 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3845 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3846 }
3847#endif
3848
3849 code = param & 0xffff;
3850 fast = (param >> 16) & 0x1;
3851 rep_cnt = (param >> 32) & 0xfff;
3852 rep_idx = (param >> 48) & 0xfff;
3853
3854 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3855
c25bc163
GN		 3856 switch (code) {
3857 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
3858 kvm_vcpu_on_spin(vcpu);
3859 break;
3860 default:
3861 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3862 break;
3863 }
55cd8e5a
GN		 3864
3865 ret = res | (((u64)rep_done & 0xfff) << 32);
3866 if (longmode) {
3867 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3868 } else {
3869 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3870 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3871 }
3872
3873 return 1;
3874}
3875
8776e519
HB		 3876int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3877{
3878 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3879 int r = 1;
8776e519 3880
55cd8e5a
GN		 3881 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3882 return kvm_hv_hypercall(vcpu);
3883
5fdbf976
MT		 3884 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3885 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3886 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3887 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3888 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3889
229456fc 3890 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3891
8776e519
HB		 3892 if (!is_long_mode(vcpu)) {
3893 nr &= 0xFFFFFFFF;
3894 a0 &= 0xFFFFFFFF;
3895 a1 &= 0xFFFFFFFF;
3896 a2 &= 0xFFFFFFFF;
3897 a3 &= 0xFFFFFFFF;
3898 }
3899
07708c4a
JK		 3900 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3901 ret = -KVM_EPERM;
3902 goto out;
3903 }
3904
8776e519 3905 switch (nr) {
b93463aa
AK		 3906 case KVM_HC_VAPIC_POLL_IRQ:
3907 ret = 0;
3908 break;
2f333bcb
MT		 3909 case KVM_HC_MMU_OP:
3910 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3911 break;
8776e519
HB		 3912 default:
3913 ret = -KVM_ENOSYS;
3914 break;
3915 }
07708c4a 3916out:
5fdbf976 3917 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3918 ++vcpu->stat.hypercalls;
2f333bcb 3919 return r;
8776e519
HB		 3920}
3921EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3922
3923int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3924{
3925 char instruction[3];
5fdbf976 3926 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3927
8776e519
HB		 3928 /*
3929 * Blow out the MMU to ensure that no other VCPU has an active mapping
3930 * to ensure that the updated hypercall appears atomically across all
3931 * VCPUs.
3932 */
3933 kvm_mmu_zap_all(vcpu->kvm);
3934
8776e519 3935 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 3936
7edcface 3937 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 3938}
3939
3940static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3941{
3942 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3943}
3944
3945void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3946{
3947 struct descriptor_table dt = { limit, base };
3948
3949 kvm_x86_ops->set_gdt(vcpu, &dt);
3950}
3951
3952void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3953{
3954 struct descriptor_table dt = { limit, base };
3955
3956 kvm_x86_ops->set_idt(vcpu, &dt);
3957}
3958
3959void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3960 unsigned long *rflags)
3961{
2d3ad1f4 3962 kvm_lmsw(vcpu, msw);
91586a3b 3963 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3964}
3965
3966unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3967{
54e445ca
JR		 3968 unsigned long value;
3969
8776e519
HB		 3970 switch (cr) {
3971 case 0:
4d4ec087 3972 value = kvm_read_cr0(vcpu);
54e445ca 3973 break;
8776e519 3974 case 2:
54e445ca
JR		 3975 value = vcpu->arch.cr2;
3976 break;
8776e519 3977 case 3:
54e445ca
JR		 3978 value = vcpu->arch.cr3;
3979 break;
8776e519 3980 case 4:
fc78f519 3981 value = kvm_read_cr4(vcpu);
54e445ca 3982 break;
152ff9be 3983 case 8:
54e445ca
JR		 3984 value = kvm_get_cr8(vcpu);
3985 break;
8776e519 3986 default:
b8688d51 3987 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3988 return 0;
3989 }
54e445ca
JR		 3990
3991 return value;
8776e519
HB		 3992}
3993
3994void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3995 unsigned long *rflags)
3996{
3997 switch (cr) {
3998 case 0:
4d4ec087 3999 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 4000 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4001 break;
4002 case 2:
ad312c7c 4003 vcpu->arch.cr2 = val;
8776e519
HB		 4004 break;
4005 case 3:
2d3ad1f4 4006 kvm_set_cr3(vcpu, val);
8776e519
HB		 4007 break;
4008 case 4:
fc78f519 4009 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 4010 break;
152ff9be 4011 case 8:
2d3ad1f4 4012 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 4013 break;
8776e519 4014 default:
b8688d51 4015 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4016 }
4017}
4018
07716717
DK		 4019static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4020{
ad312c7c
ZX		 4021 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4022 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4023
4024 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4025 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4026 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4027 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4028 if (ej->function == e->function) {
4029 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4030 return j;
4031 }
4032 }
4033 return 0; /* silence gcc, even though control never reaches here */
4034}
4035
4036/* find an entry with matching function, matching index (if needed), and that
4037 * should be read next (if it's stateful) */
4038static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4039 u32 function, u32 index)
4040{
4041 if (e->function != function)
4042 return 0;
4043 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4044 return 0;
4045 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4046 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4047 return 0;
4048 return 1;
4049}
4050
d8017474
AG		 4051struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4052 u32 function, u32 index)
8776e519
HB		 4053{
4054 int i;
d8017474 4055 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4056
ad312c7c 4057 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4058 struct kvm_cpuid_entry2 *e;
4059
ad312c7c 4060 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4061 if (is_matching_cpuid_entry(e, function, index)) {
4062 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4063 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4064 best = e;
4065 break;
4066 }
4067 /*
4068 * Both basic or both extended?
4069 */
4070 if (((e->function ^ function) & 0x80000000) == 0)
4071 if (!best || e->function > best->function)
4072 best = e;
4073 }
d8017474
AG		 4074 return best;
4075}
0e851880 4076EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4077
82725b20
DE		 4078int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4079{
4080 struct kvm_cpuid_entry2 *best;
4081
4082 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4083 if (best)
4084 return best->eax & 0xff;
4085 return 36;
4086}
4087
d8017474
AG		 4088void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4089{
4090 u32 function, index;
4091 struct kvm_cpuid_entry2 *best;
4092
4093 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4094 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4095 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4096 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4097 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4098 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4099 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4100 if (best) {
5fdbf976
MT		 4101 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4102 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4103 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4104 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4105 }
8776e519 4106 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4107 trace_kvm_cpuid(function,
4108 kvm_register_read(vcpu, VCPU_REGS_RAX),
4109 kvm_register_read(vcpu, VCPU_REGS_RBX),
4110 kvm_register_read(vcpu, VCPU_REGS_RCX),
4111 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4112}
4113EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4114
b6c7a5dc
HB		 4115/*
4116 * Check if userspace requested an interrupt window, and that the
4117 * interrupt window is open.
4118 *
4119 * No need to exit to userspace if we already have an interrupt queued.
4120 */
851ba692 4121static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4122{
8061823a 4123 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4124 vcpu->run->request_interrupt_window &&
5df56646 4125 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4126}
4127
851ba692 4128static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4129{
851ba692
AK		 4130 struct kvm_run *kvm_run = vcpu->run;
4131
91586a3b 4132 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4133 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4134 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4135 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4136 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4137 else
b6c7a5dc 4138 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4139 kvm_arch_interrupt_allowed(vcpu) &&
4140 !kvm_cpu_has_interrupt(vcpu) &&
4141 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4142}
4143
b93463aa
AK		 4144static void vapic_enter(struct kvm_vcpu *vcpu)
4145{
4146 struct kvm_lapic *apic = vcpu->arch.apic;
4147 struct page *page;
4148
4149 if (!apic || !apic->vapic_addr)
4150 return;
4151
4152 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4153
4154 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4155}
4156
4157static void vapic_exit(struct kvm_vcpu *vcpu)
4158{
4159 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4160 int idx;
b93463aa
AK		 4161
4162 if (!apic || !apic->vapic_addr)
4163 return;
4164
f656ce01 4165 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4166 kvm_release_page_dirty(apic->vapic_page);
4167 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4168 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4169}
4170
95ba8273
GN		 4171static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4172{
4173 int max_irr, tpr;
4174
4175 if (!kvm_x86_ops->update_cr8_intercept)
4176 return;
4177
88c808fd
AK		 4178 if (!vcpu->arch.apic)
4179 return;
4180
8db3baa2
GN		 4181 if (!vcpu->arch.apic->vapic_addr)
4182 max_irr = kvm_lapic_find_highest_irr(vcpu);
4183 else
4184 max_irr = -1;
95ba8273
GN		 4185
4186 if (max_irr != -1)
4187 max_irr >>= 4;
4188
4189 tpr = kvm_lapic_get_cr8(vcpu);
4190
4191 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4192}
4193
851ba692 4194static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4195{
4196 /* try to reinject previous events if any */
b59bb7bd
GN		 4197 if (vcpu->arch.exception.pending) {
4198 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4199 vcpu->arch.exception.has_error_code,
4200 vcpu->arch.exception.error_code);
4201 return;
4202 }
4203
95ba8273
GN		 4204 if (vcpu->arch.nmi_injected) {
4205 kvm_x86_ops->set_nmi(vcpu);
4206 return;
4207 }
4208
4209 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4210 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4211 return;
4212 }
4213
4214 /* try to inject new event if pending */
4215 if (vcpu->arch.nmi_pending) {
4216 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4217 vcpu->arch.nmi_pending = false;
4218 vcpu->arch.nmi_injected = true;
4219 kvm_x86_ops->set_nmi(vcpu);
4220 }
4221 } else if (kvm_cpu_has_interrupt(vcpu)) {
4222 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4223 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4224 false);
4225 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4226 }
4227 }
4228}
4229
851ba692 4230static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4231{
4232 int r;
6a8b1d13 4233 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4234 vcpu->run->request_interrupt_window;
b6c7a5dc 4235
2e53d63a
MT		 4236 if (vcpu->requests)
4237 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4238 kvm_mmu_unload(vcpu);
4239
b6c7a5dc
HB		 4240 r = kvm_mmu_reload(vcpu);
4241 if (unlikely(r))
4242 goto out;
4243
2f52d58c
AK		 4244 if (vcpu->requests) {
4245 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4246 __kvm_migrate_timers(vcpu);
c8076604
GH		 4247 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4248 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4249 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4250 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4251 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4252 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4253 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4254 &vcpu->requests)) {
851ba692 4255 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4256 r = 0;
4257 goto out;
4258 }
71c4dfaf 4259 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4260 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4261 r = 0;
4262 goto out;
4263 }
02daab21
AK		 4264 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4265 vcpu->fpu_active = 0;
4266 kvm_x86_ops->fpu_deactivate(vcpu);
4267 }
2f52d58c 4268 }
b93463aa 4269
b6c7a5dc
HB		 4270 preempt_disable();
4271
4272 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4273 if (vcpu->fpu_active)
4274 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4275
4276 local_irq_disable();
4277
32f88400
MT		 4278 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4279 smp_mb__after_clear_bit();
4280
d7690175 4281 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4282 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4283 local_irq_enable();
4284 preempt_enable();
4285 r = 1;
4286 goto out;
4287 }
4288
851ba692 4289 inject_pending_event(vcpu);
b6c7a5dc 4290
6a8b1d13
GN		 4291 /* enable NMI/IRQ window open exits if needed */
4292 if (vcpu->arch.nmi_pending)
4293 kvm_x86_ops->enable_nmi_window(vcpu);
4294 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4295 kvm_x86_ops->enable_irq_window(vcpu);
4296
95ba8273 4297 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4298 update_cr8_intercept(vcpu);
4299 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4300 }
b93463aa 4301
f656ce01 4302 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4303
b6c7a5dc
HB		 4304 kvm_guest_enter();
4305
42dbaa5a 4306 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4307 set_debugreg(0, 7);
4308 set_debugreg(vcpu->arch.eff_db[0], 0);
4309 set_debugreg(vcpu->arch.eff_db[1], 1);
4310 set_debugreg(vcpu->arch.eff_db[2], 2);
4311 set_debugreg(vcpu->arch.eff_db[3], 3);
4312 }
b6c7a5dc 4313
229456fc 4314 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4315 kvm_x86_ops->run(vcpu);
b6c7a5dc 4316
24f1e32c
FW		 4317 /*
4318 * If the guest has used debug registers, at least dr7
4319 * will be disabled while returning to the host.
4320 * If we don't have active breakpoints in the host, we don't
4321 * care about the messed up debug address registers. But if
4322 * we have some of them active, restore the old state.
4323 */
59d8eb53 4324 if (hw_breakpoint_active())
24f1e32c 4325 hw_breakpoint_restore();
42dbaa5a 4326
32f88400 4327 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4328 local_irq_enable();
4329
4330 ++vcpu->stat.exits;
4331
4332 /*
4333 * We must have an instruction between local_irq_enable() and
4334 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4335 * the interrupt shadow. The stat.exits increment will do nicely.
4336 * But we need to prevent reordering, hence this barrier():
4337 */
4338 barrier();
4339
4340 kvm_guest_exit();
4341
4342 preempt_enable();
4343
f656ce01 4344 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4345
b6c7a5dc
HB		 4346 /*
4347 * Profile KVM exit RIPs:
4348 */
4349 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4350 unsigned long rip = kvm_rip_read(vcpu);
4351 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4352 }
4353
298101da 4354
b93463aa
AK		 4355 kvm_lapic_sync_from_vapic(vcpu);
4356
851ba692 4357 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4358out:
4359 return r;
4360}
b6c7a5dc 4361
09cec754 4362
851ba692 4363static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4364{
4365 int r;
f656ce01 4366 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4367
4368 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4369 pr_debug("vcpu %d received sipi with vector # %x\n",
4370 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4371 kvm_lapic_reset(vcpu);
5f179287 4372 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4373 if (r)
4374 return r;
4375 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4376 }
4377
f656ce01 4378 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4379 vapic_enter(vcpu);
4380
4381 r = 1;
4382 while (r > 0) {
af2152f5 4383 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4384 r = vcpu_enter_guest(vcpu);
d7690175 4385 else {
f656ce01 4386 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4387 kvm_vcpu_block(vcpu);
f656ce01 4388 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4389 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4390 {
4391 switch(vcpu->arch.mp_state) {
4392 case KVM_MP_STATE_HALTED:
d7690175 4393 vcpu->arch.mp_state =
09cec754
GN		 4394 KVM_MP_STATE_RUNNABLE;
4395 case KVM_MP_STATE_RUNNABLE:
4396 break;
4397 case KVM_MP_STATE_SIPI_RECEIVED:
4398 default:
4399 r = -EINTR;
4400 break;
4401 }
4402 }
d7690175
MT		 4403 }
4404
09cec754
GN		 4405 if (r <= 0)
4406 break;
4407
4408 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4409 if (kvm_cpu_has_pending_timer(vcpu))
4410 kvm_inject_pending_timer_irqs(vcpu);
4411
851ba692 4412 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4413 r = -EINTR;
851ba692 4414 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4415 ++vcpu->stat.request_irq_exits;
4416 }
4417 if (signal_pending(current)) {
4418 r = -EINTR;
851ba692 4419 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4420 ++vcpu->stat.signal_exits;
4421 }
4422 if (need_resched()) {
f656ce01 4423 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4424 kvm_resched(vcpu);
f656ce01 4425 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4426 }
b6c7a5dc
HB		 4427 }
4428
f656ce01 4429 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4430 post_kvm_run_save(vcpu);
b6c7a5dc 4431
b93463aa
AK		 4432 vapic_exit(vcpu);
4433
b6c7a5dc
HB		 4434 return r;
4435}
4436
4437int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4438{
4439 int r;
4440 sigset_t sigsaved;
4441
4442 vcpu_load(vcpu);
4443
ac9f6dc0
AK		 4444 if (vcpu->sigset_active)
4445 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4446
a4535290 4447 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4448 kvm_vcpu_block(vcpu);
d7690175 4449 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4450 r = -EAGAIN;
4451 goto out;
b6c7a5dc
HB		 4452 }
4453
b6c7a5dc
HB		 4454 /* re-sync apic's tpr */
4455 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4456 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4457
ad312c7c 4458 if (vcpu->arch.pio.cur_count) {
7567cae1 4459 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
b6c7a5dc 4460 r = complete_pio(vcpu);
7567cae1 4461 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4462 if (r)
4463 goto out;
4464 }
b6c7a5dc
HB		 4465 if (vcpu->mmio_needed) {
4466 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4467 vcpu->mmio_read_completed = 1;
4468 vcpu->mmio_needed = 0;
3200f405 4469
f656ce01 4470 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4471 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4472 EMULTYPE_NO_DECODE);
f656ce01 4473 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4474 if (r == EMULATE_DO_MMIO) {
4475 /*
4476 * Read-modify-write. Back to userspace.
4477 */
4478 r = 0;
4479 goto out;
4480 }
4481 }
5fdbf976
MT		 4482 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4483 kvm_register_write(vcpu, VCPU_REGS_RAX,
4484 kvm_run->hypercall.ret);
b6c7a5dc 4485
851ba692 4486 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4487
4488out:
4489 if (vcpu->sigset_active)
4490 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4491
4492 vcpu_put(vcpu);
4493 return r;
4494}
4495
4496int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4497{
4498 vcpu_load(vcpu);
4499
5fdbf976
MT		 4500 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4501 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4502 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4503 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4504 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4505 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4506 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4507 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4508#ifdef CONFIG_X86_64
5fdbf976
MT		 4509 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4510 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4511 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4512 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4513 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4514 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4515 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4516 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4517#endif
4518
5fdbf976 4519 regs->rip = kvm_rip_read(vcpu);
91586a3b 4520 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4521
4522 vcpu_put(vcpu);
4523
4524 return 0;
4525}
4526
4527int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4528{
4529 vcpu_load(vcpu);
4530
5fdbf976
MT		 4531 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4532 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4533 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4534 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4535 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4536 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4537 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4538 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4539#ifdef CONFIG_X86_64
5fdbf976
MT		 4540 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4541 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4542 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4543 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4544 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4545 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4546 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4547 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4548#endif
4549
5fdbf976 4550 kvm_rip_write(vcpu, regs->rip);
91586a3b 4551 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4552
b4f14abd
JK		 4553 vcpu->arch.exception.pending = false;
4554
b6c7a5dc
HB		 4555 vcpu_put(vcpu);
4556
4557 return 0;
4558}
4559
3e6e0aab
GT		 4560void kvm_get_segment(struct kvm_vcpu *vcpu,
4561 struct kvm_segment *var, int seg)
b6c7a5dc 4562{
14af3f3c 4563 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4564}
4565
4566void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4567{
4568 struct kvm_segment cs;
4569
3e6e0aab 4570 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4571 *db = cs.db;
4572 *l = cs.l;
4573}
4574EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4575
4576int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4577 struct kvm_sregs *sregs)
4578{
4579 struct descriptor_table dt;
b6c7a5dc
HB		 4580
4581 vcpu_load(vcpu);
4582
3e6e0aab
GT		 4583 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4584 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4585 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4586 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4587 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4588 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4589
3e6e0aab
GT		 4590 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4591 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4592
4593 kvm_x86_ops->get_idt(vcpu, &dt);
4594 sregs->idt.limit = dt.limit;
4595 sregs->idt.base = dt.base;
4596 kvm_x86_ops->get_gdt(vcpu, &dt);
4597 sregs->gdt.limit = dt.limit;
4598 sregs->gdt.base = dt.base;
4599
4d4ec087 4600 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4601 sregs->cr2 = vcpu->arch.cr2;
4602 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4603 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4604 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4605 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4606 sregs->apic_base = kvm_get_apic_base(vcpu);
4607
923c61bb 4608 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4609
36752c9b 4610 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4611 set_bit(vcpu->arch.interrupt.nr,
4612 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4613
b6c7a5dc
HB		 4614 vcpu_put(vcpu);
4615
4616 return 0;
4617}
4618
62d9f0db
MT		 4619int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4620 struct kvm_mp_state *mp_state)
4621{
4622 vcpu_load(vcpu);
4623 mp_state->mp_state = vcpu->arch.mp_state;
4624 vcpu_put(vcpu);
4625 return 0;
4626}
4627
4628int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4629 struct kvm_mp_state *mp_state)
4630{
4631 vcpu_load(vcpu);
4632 vcpu->arch.mp_state = mp_state->mp_state;
4633 vcpu_put(vcpu);
4634 return 0;
4635}
4636
3e6e0aab 4637static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4638 struct kvm_segment *var, int seg)
4639{
14af3f3c 4640 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4641}
4642
37817f29
IE		 4643static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4644 struct kvm_segment *kvm_desct)
4645{
46a359e7
AM		 4646 kvm_desct->base = get_desc_base(seg_desc);
4647 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4648 if (seg_desc->g) {
4649 kvm_desct->limit <<= 12;
4650 kvm_desct->limit |= 0xfff;
4651 }
37817f29
IE		 4652 kvm_desct->selector = selector;
4653 kvm_desct->type = seg_desc->type;
4654 kvm_desct->present = seg_desc->p;
4655 kvm_desct->dpl = seg_desc->dpl;
4656 kvm_desct->db = seg_desc->d;
4657 kvm_desct->s = seg_desc->s;
4658 kvm_desct->l = seg_desc->l;
4659 kvm_desct->g = seg_desc->g;
4660 kvm_desct->avl = seg_desc->avl;
4661 if (!selector)
4662 kvm_desct->unusable = 1;
4663 else
4664 kvm_desct->unusable = 0;
4665 kvm_desct->padding = 0;
4666}
4667
b8222ad2
AS		 4668static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4669 u16 selector,
4670 struct descriptor_table *dtable)
37817f29
IE		 4671{
4672 if (selector & 1 << 2) {
4673 struct kvm_segment kvm_seg;
4674
3e6e0aab 4675 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4676
4677 if (kvm_seg.unusable)
4678 dtable->limit = 0;
4679 else
4680 dtable->limit = kvm_seg.limit;
4681 dtable->base = kvm_seg.base;
4682 }
4683 else
4684 kvm_x86_ops->get_gdt(vcpu, dtable);
4685}
4686
4687/* allowed just for 8 bytes segments */
4688static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4689 struct desc_struct *seg_desc)
4690{
4691 struct descriptor_table dtable;
4692 u16 index = selector >> 3;
6f550484
TY		 4693 int ret;
4694 u32 err;
4695 gva_t addr;
37817f29 4696
b8222ad2 4697 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4698
4699 if (dtable.limit < index * 8 + 7) {
4700 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4701 return X86EMUL_PROPAGATE_FAULT;
37817f29 4702 }
6f550484
TY		 4703 addr = dtable.base + index * 8;
4704 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4705 vcpu, &err);
4706 if (ret == X86EMUL_PROPAGATE_FAULT)
4707 kvm_inject_page_fault(vcpu, addr, err);
4708
4709 return ret;
37817f29
IE		 4710}
4711
4712/* allowed just for 8 bytes segments */
4713static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4714 struct desc_struct *seg_desc)
4715{
4716 struct descriptor_table dtable;
4717 u16 index = selector >> 3;
4718
b8222ad2 4719 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4720
4721 if (dtable.limit < index * 8 + 7)
4722 return 1;
1871c602
GN		 4723 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
4724}
4725
4726static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4727 struct desc_struct *seg_desc)
4728{
4729 u32 base_addr = get_desc_base(seg_desc);
4730
4731 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4732}
4733
1871c602 4734static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4735 struct desc_struct *seg_desc)
4736{
46a359e7 4737 u32 base_addr = get_desc_base(seg_desc);
37817f29 4738
1871c602 4739 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4740}
4741
37817f29
IE		 4742static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4743{
4744 struct kvm_segment kvm_seg;
4745
3e6e0aab 4746 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4747 return kvm_seg.selector;
4748}
4749
2259e3a7 4750static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4751{
4752 struct kvm_segment segvar = {
4753 .base = selector << 4,
4754 .limit = 0xffff,
4755 .selector = selector,
4756 .type = 3,
4757 .present = 1,
4758 .dpl = 3,
4759 .db = 0,
4760 .s = 1,
4761 .l = 0,
4762 .g = 0,
4763 .avl = 0,
4764 .unusable = 0,
4765 };
4766 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4767 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4768}
4769
c0c7c04b
AL		 4770static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4771{
4772 return (seg != VCPU_SREG_LDTR) &&
4773 (seg != VCPU_SREG_TR) &&
91586a3b 4774 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4775}
4776
c697518a 4777int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4778{
4779 struct kvm_segment kvm_seg;
e01c2426 4780 struct desc_struct seg_desc;
c697518a
GN		 4781 u8 dpl, rpl, cpl;
4782 unsigned err_vec = GP_VECTOR;
4783 u32 err_code = 0;
4784 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4785 int ret;
37817f29 4786
3eeb3288 4787 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4788 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4789
c697518a
GN		 4790 /* NULL selector is not valid for TR, CS and SS */
4791 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4792 && null_selector)
4793 goto exception;
4794
4795 /* TR should be in GDT only */
4796 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4797 goto exception;
4798
4799 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4800 if (ret)
4801 return ret;
4802
e01c2426 4803 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4804
c697518a
GN		 4805 if (null_selector) { /* for NULL selector skip all following checks */
4806 kvm_seg.unusable = 1;
4807 goto load;
4808 }
37817f29 4809
c697518a
GN		 4810 err_code = selector & 0xfffc;
4811 err_vec = GP_VECTOR;
37817f29 4812
c697518a
GN		 4813 /* can't load system descriptor into segment selecor */
4814 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4815 goto exception;
4816
4817 if (!kvm_seg.present) {
4818 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4819 goto exception;
4820 }
4821
4822 rpl = selector & 3;
4823 dpl = kvm_seg.dpl;
4824 cpl = kvm_x86_ops->get_cpl(vcpu);
4825
4826 switch (seg) {
4827 case VCPU_SREG_SS:
4828 /*
4829 * segment is not a writable data segment or segment
4830 * selector's RPL != CPL or segment selector's RPL != CPL
4831 */
4832 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4833 goto exception;
4834 break;
4835 case VCPU_SREG_CS:
4836 if (!(kvm_seg.type & 8))
4837 goto exception;
4838
4839 if (kvm_seg.type & 4) {
4840 /* conforming */
4841 if (dpl > cpl)
4842 goto exception;
4843 } else {
4844 /* nonconforming */
4845 if (rpl > cpl || dpl != cpl)
4846 goto exception;
4847 }
4848 /* CS(RPL) <- CPL */
4849 selector = (selector & 0xfffc) | cpl;
4850 break;
4851 case VCPU_SREG_TR:
4852 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4853 goto exception;
4854 break;
4855 case VCPU_SREG_LDTR:
4856 if (kvm_seg.s || kvm_seg.type != 2)
4857 goto exception;
4858 break;
4859 default: /* DS, ES, FS, or GS */
4860 /*
4861 * segment is not a data or readable code segment or
4862 * ((segment is a data or nonconforming code segment)
4863 * and (both RPL and CPL > DPL))
4864 */
4865 if ((kvm_seg.type & 0xa) == 0x8 ||
4866 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4867 goto exception;
4868 break;
4869 }
4870
4871 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4872 /* mark segment as accessed */
c697518a 4873 kvm_seg.type |= 1;
e01c2426
GN		 4874 seg_desc.type |= 1;
4875 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4876 }
c697518a
GN		 4877load:
4878 kvm_set_segment(vcpu, &kvm_seg, seg);
4879 return X86EMUL_CONTINUE;
4880exception:
4881 kvm_queue_exception_e(vcpu, err_vec, err_code);
4882 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4883}
4884
4885static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4886 struct tss_segment_32 *tss)
4887{
4888 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4889 tss->eip = kvm_rip_read(vcpu);
91586a3b 4890 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4891 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4892 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4893 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4894 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4895 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4896 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4897 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4898 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4899 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4900 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4901 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4902 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4903 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4904 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4905 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4906}
4907
c697518a
GN		 4908static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4909{
4910 struct kvm_segment kvm_seg;
4911 kvm_get_segment(vcpu, &kvm_seg, seg);
4912 kvm_seg.selector = sel;
4913 kvm_set_segment(vcpu, &kvm_seg, seg);
4914}
4915
37817f29
IE		 4916static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4917 struct tss_segment_32 *tss)
4918{
4919 kvm_set_cr3(vcpu, tss->cr3);
4920
5fdbf976 4921 kvm_rip_write(vcpu, tss->eip);
91586a3b 4922 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4923
5fdbf976
MT		 4924 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4925 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4926 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4927 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4928 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4929 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4930 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4931 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4932
c697518a
GN		 4933 /*
4934 * SDM says that segment selectors are loaded before segment
4935 * descriptors
4936 */
4937 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
4938 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
4939 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
4940 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
4941 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
4942 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
4943 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
4944
4945 /*
4946 * Now load segment descriptors. If fault happenes at this stage
4947 * it is handled in a context of new task
4948 */
4949 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 4950 return 1;
4951
c697518a 4952 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 4953 return 1;
4954
c697518a 4955 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 4956 return 1;
4957
c697518a 4958 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 4959 return 1;
4960
c697518a 4961 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 4962 return 1;
4963
c697518a 4964 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 4965 return 1;
4966
c697518a 4967 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 4968 return 1;
4969 return 0;
4970}
4971
4972static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4973 struct tss_segment_16 *tss)
4974{
5fdbf976 4975 tss->ip = kvm_rip_read(vcpu);
91586a3b 4976 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4977 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4978 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4979 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4980 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4981 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4982 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4983 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4984 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4985
4986 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4987 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4988 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4989 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4990 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4991}
4992
4993static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4994 struct tss_segment_16 *tss)
4995{
5fdbf976 4996 kvm_rip_write(vcpu, tss->ip);
91586a3b 4997 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4998 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4999 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5000 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5001 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5002 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5003 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5004 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5005 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5006
c697518a
GN		 5007 /*
5008 * SDM says that segment selectors are loaded before segment
5009 * descriptors
5010 */
5011 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5012 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5013 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5014 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5015 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5016
5017 /*
5018 * Now load segment descriptors. If fault happenes at this stage
5019 * it is handled in a context of new task
5020 */
5021 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5022 return 1;
5023
c697518a 5024 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5025 return 1;
5026
c697518a 5027 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5028 return 1;
5029
c697518a 5030 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5031 return 1;
5032
c697518a 5033 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5034 return 1;
5035 return 0;
5036}
5037
8b2cf73c 5038static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5039 u16 old_tss_sel, u32 old_tss_base,
5040 struct desc_struct *nseg_desc)
37817f29
IE		 5041{
5042 struct tss_segment_16 tss_segment_16;
5043 int ret = 0;
5044
34198bf8
MT		 5045 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5046 sizeof tss_segment_16))
37817f29
IE		 5047 goto out;
5048
5049 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5050
34198bf8
MT		 5051 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5052 sizeof tss_segment_16))
37817f29 5053 goto out;
34198bf8 5054
1871c602 5055 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5056 &tss_segment_16, sizeof tss_segment_16))
5057 goto out;
5058
b237ac37
GN		 5059 if (old_tss_sel != 0xffff) {
5060 tss_segment_16.prev_task_link = old_tss_sel;
5061
5062 if (kvm_write_guest(vcpu->kvm,
1871c602 5063 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5064 &tss_segment_16.prev_task_link,
5065 sizeof tss_segment_16.prev_task_link))
5066 goto out;
5067 }
5068
37817f29
IE		 5069 if (load_state_from_tss16(vcpu, &tss_segment_16))
5070 goto out;
5071
5072 ret = 1;
5073out:
5074 return ret;
5075}
5076
8b2cf73c 5077static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5078 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5079 struct desc_struct *nseg_desc)
5080{
5081 struct tss_segment_32 tss_segment_32;
5082 int ret = 0;
5083
34198bf8
MT		 5084 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5085 sizeof tss_segment_32))
37817f29
IE		 5086 goto out;
5087
5088 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5089
34198bf8
MT		 5090 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5091 sizeof tss_segment_32))
5092 goto out;
5093
1871c602 5094 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5095 &tss_segment_32, sizeof tss_segment_32))
37817f29 5096 goto out;
34198bf8 5097
b237ac37
GN		 5098 if (old_tss_sel != 0xffff) {
5099 tss_segment_32.prev_task_link = old_tss_sel;
5100
5101 if (kvm_write_guest(vcpu->kvm,
1871c602 5102 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5103 &tss_segment_32.prev_task_link,
5104 sizeof tss_segment_32.prev_task_link))
5105 goto out;
5106 }
5107
37817f29
IE		 5108 if (load_state_from_tss32(vcpu, &tss_segment_32))
5109 goto out;
5110
5111 ret = 1;
5112out:
5113 return ret;
5114}
5115
5116int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5117{
5118 struct kvm_segment tr_seg;
5119 struct desc_struct cseg_desc;
5120 struct desc_struct nseg_desc;
5121 int ret = 0;
34198bf8
MT		 5122 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5123 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 5124
1871c602 5125 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5126
34198bf8
MT		 5127 /* FIXME: Handle errors. Failure to read either TSS or their
5128 * descriptors should generate a pagefault.
5129 */
37817f29
IE		 5130 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5131 goto out;
5132
34198bf8 5133 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5134 goto out;
5135
37817f29
IE		 5136 if (reason != TASK_SWITCH_IRET) {
5137 int cpl;
5138
5139 cpl = kvm_x86_ops->get_cpl(vcpu);
5140 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5141 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5142 return 1;
5143 }
5144 }
5145
46a359e7 5146 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 5147 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5148 return 1;
5149 }
5150
5151 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5152 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5153 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5154 }
5155
5156 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5157 u32 eflags = kvm_get_rflags(vcpu);
5158 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5159 }
5160
b237ac37
GN		 5161 /* set back link to prev task only if NT bit is set in eflags
5162 note that old_tss_sel is not used afetr this point */
5163 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5164 old_tss_sel = 0xffff;
5165
37817f29 5166 if (nseg_desc.type & 8)
b237ac37
GN		 5167 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5168 old_tss_base, &nseg_desc);
37817f29 5169 else
b237ac37
GN		 5170 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5171 old_tss_base, &nseg_desc);
37817f29
IE		 5172
5173 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5174 u32 eflags = kvm_get_rflags(vcpu);
5175 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5176 }
5177
5178 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5179 nseg_desc.type |= (1 << 1);
37817f29
IE		 5180 save_guest_segment_descriptor(vcpu, tss_selector,
5181 &nseg_desc);
5182 }
5183
4d4ec087 5184 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5185 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5186 tr_seg.type = 11;
3e6e0aab 5187 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5188out:
37817f29
IE		 5189 return ret;
5190}
5191EXPORT_SYMBOL_GPL(kvm_task_switch);
5192
b6c7a5dc
HB		 5193int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5194 struct kvm_sregs *sregs)
5195{
5196 int mmu_reset_needed = 0;
923c61bb 5197 int pending_vec, max_bits;
b6c7a5dc
HB		 5198 struct descriptor_table dt;
5199
5200 vcpu_load(vcpu);
5201
5202 dt.limit = sregs->idt.limit;
5203 dt.base = sregs->idt.base;
5204 kvm_x86_ops->set_idt(vcpu, &dt);
5205 dt.limit = sregs->gdt.limit;
5206 dt.base = sregs->gdt.base;
5207 kvm_x86_ops->set_gdt(vcpu, &dt);
5208
ad312c7c
ZX		 5209 vcpu->arch.cr2 = sregs->cr2;
5210 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5211 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5212
2d3ad1f4 5213 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5214
f6801dff 5215 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5216 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5217 kvm_set_apic_base(vcpu, sregs->apic_base);
5218
4d4ec087 5219 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5220 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5221 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5222
fc78f519 5223 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5224 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5225 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5226 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5227 mmu_reset_needed = 1;
5228 }
b6c7a5dc
HB		 5229
5230 if (mmu_reset_needed)
5231 kvm_mmu_reset_context(vcpu);
5232
923c61bb
GN		 5233 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5234 pending_vec = find_first_bit(
5235 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5236 if (pending_vec < max_bits) {
66fd3f7f 5237 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5238 pr_debug("Set back pending irq %d\n", pending_vec);
5239 if (irqchip_in_kernel(vcpu->kvm))
5240 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5241 }
5242
3e6e0aab
GT		 5243 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5244 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5245 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5246 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5247 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5248 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5249
3e6e0aab
GT		 5250 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5251 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5252
5f0269f5
ME		 5253 update_cr8_intercept(vcpu);
5254
9c3e4aab 5255 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5256 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5257 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5258 !is_protmode(vcpu))
9c3e4aab
MT		 5259 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5260
b6c7a5dc
HB		 5261 vcpu_put(vcpu);
5262
5263 return 0;
5264}
5265
d0bfb940
JK		 5266int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5267 struct kvm_guest_debug *dbg)
b6c7a5dc 5268{
355be0b9 5269 unsigned long rflags;
ae675ef0 5270 int i, r;
b6c7a5dc
HB		 5271
5272 vcpu_load(vcpu);
5273
4f926bf2
JK		 5274 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5275 r = -EBUSY;
5276 if (vcpu->arch.exception.pending)
5277 goto unlock_out;
5278 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5279 kvm_queue_exception(vcpu, DB_VECTOR);
5280 else
5281 kvm_queue_exception(vcpu, BP_VECTOR);
5282 }
5283
91586a3b
JK		 5284 /*
5285 * Read rflags as long as potentially injected trace flags are still
5286 * filtered out.
5287 */
5288 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5289
5290 vcpu->guest_debug = dbg->control;
5291 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5292 vcpu->guest_debug = 0;
5293
5294 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5295 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5296 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5297 vcpu->arch.switch_db_regs =
5298 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5299 } else {
5300 for (i = 0; i < KVM_NR_DB_REGS; i++)
5301 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5302 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5303 }
5304
94fe45da
JK		 5305 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5306 vcpu->arch.singlestep_cs =
5307 get_segment_selector(vcpu, VCPU_SREG_CS);
5308 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
5309 }
5310
91586a3b
JK		 5311 /*
5312 * Trigger an rflags update that will inject or remove the trace
5313 * flags.
5314 */
5315 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5316
355be0b9 5317 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5318
4f926bf2 5319 r = 0;
d0bfb940 5320
4f926bf2 5321unlock_out:
b6c7a5dc
HB		 5322 vcpu_put(vcpu);
5323
5324 return r;
5325}
5326
d0752060
HB		 5327/*
5328 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5329 * we have asm/x86/processor.h
5330 */
5331struct fxsave {
5332 u16 cwd;
5333 u16 swd;
5334 u16 twd;
5335 u16 fop;
5336 u64 rip;
5337 u64 rdp;
5338 u32 mxcsr;
5339 u32 mxcsr_mask;
5340 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5341#ifdef CONFIG_X86_64
5342 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5343#else
5344 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5345#endif
5346};
5347
8b006791
ZX		 5348/*
5349 * Translate a guest virtual address to a guest physical address.
5350 */
5351int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5352 struct kvm_translation *tr)
5353{
5354 unsigned long vaddr = tr->linear_address;
5355 gpa_t gpa;
f656ce01 5356 int idx;
8b006791
ZX		 5357
5358 vcpu_load(vcpu);
f656ce01 5359 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5360 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5361 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5362 tr->physical_address = gpa;
5363 tr->valid = gpa != UNMAPPED_GVA;
5364 tr->writeable = 1;
5365 tr->usermode = 0;
8b006791
ZX		 5366 vcpu_put(vcpu);
5367
5368 return 0;
5369}
5370
d0752060
HB		 5371int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5372{
ad312c7c 5373 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5374
5375 vcpu_load(vcpu);
5376
5377 memcpy(fpu->fpr, fxsave->st_space, 128);
5378 fpu->fcw = fxsave->cwd;
5379 fpu->fsw = fxsave->swd;
5380 fpu->ftwx = fxsave->twd;
5381 fpu->last_opcode = fxsave->fop;
5382 fpu->last_ip = fxsave->rip;
5383 fpu->last_dp = fxsave->rdp;
5384 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5385
5386 vcpu_put(vcpu);
5387
5388 return 0;
5389}
5390
5391int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5392{
ad312c7c 5393 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5394
5395 vcpu_load(vcpu);
5396
5397 memcpy(fxsave->st_space, fpu->fpr, 128);
5398 fxsave->cwd = fpu->fcw;
5399 fxsave->swd = fpu->fsw;
5400 fxsave->twd = fpu->ftwx;
5401 fxsave->fop = fpu->last_opcode;
5402 fxsave->rip = fpu->last_ip;
5403 fxsave->rdp = fpu->last_dp;
5404 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5405
5406 vcpu_put(vcpu);
5407
5408 return 0;
5409}
5410
5411void fx_init(struct kvm_vcpu *vcpu)
5412{
5413 unsigned after_mxcsr_mask;
5414
bc1a34f1
AA		 5415 /*
5416 * Touch the fpu the first time in non atomic context as if
5417 * this is the first fpu instruction the exception handler
5418 * will fire before the instruction returns and it'll have to
5419 * allocate ram with GFP_KERNEL.
5420 */
5421 if (!used_math())
d6e88aec 5422 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5423
d0752060
HB		 5424 /* Initialize guest FPU by resetting ours and saving into guest's */
5425 preempt_disable();
d6e88aec
AK		 5426 kvm_fx_save(&vcpu->arch.host_fx_image);
5427 kvm_fx_finit();
5428 kvm_fx_save(&vcpu->arch.guest_fx_image);
5429 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5430 preempt_enable();
5431
ad312c7c 5432 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5433 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5434 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5435 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5436 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5437}
5438EXPORT_SYMBOL_GPL(fx_init);
5439
5440void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5441{
2608d7a1 5442 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5443 return;
5444
5445 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5446 kvm_fx_save(&vcpu->arch.host_fx_image);
5447 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5448 trace_kvm_fpu(1);
d0752060 5449}
d0752060
HB		 5450
5451void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5452{
5453 if (!vcpu->guest_fpu_loaded)
5454 return;
5455
5456 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5457 kvm_fx_save(&vcpu->arch.guest_fx_image);
5458 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5459 ++vcpu->stat.fpu_reload;
02daab21 5460 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5461 trace_kvm_fpu(0);
d0752060 5462}
e9b11c17
ZX		 5463
5464void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5465{
7f1ea208
JR		 5466 if (vcpu->arch.time_page) {
5467 kvm_release_page_dirty(vcpu->arch.time_page);
5468 vcpu->arch.time_page = NULL;
5469 }
5470
e9b11c17
ZX		 5471 kvm_x86_ops->vcpu_free(vcpu);
5472}
5473
5474struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5475 unsigned int id)
5476{
26e5215f
AK		 5477 return kvm_x86_ops->vcpu_create(kvm, id);
5478}
e9b11c17 5479
26e5215f
AK		 5480int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5481{
5482 int r;
e9b11c17
ZX		 5483
5484 /* We do fxsave: this must be aligned. */
ad312c7c 5485 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5486
0bed3b56 5487 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5488 vcpu_load(vcpu);
5489 r = kvm_arch_vcpu_reset(vcpu);
5490 if (r == 0)
5491 r = kvm_mmu_setup(vcpu);
5492 vcpu_put(vcpu);
5493 if (r < 0)
5494 goto free_vcpu;
5495
26e5215f 5496 return 0;
e9b11c17
ZX		 5497free_vcpu:
5498 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5499 return r;
e9b11c17
ZX		 5500}
5501
d40ccc62 5502void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5503{
5504 vcpu_load(vcpu);
5505 kvm_mmu_unload(vcpu);
5506 vcpu_put(vcpu);
5507
5508 kvm_x86_ops->vcpu_free(vcpu);
5509}
5510
5511int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5512{
448fa4a9
JK		 5513 vcpu->arch.nmi_pending = false;
5514 vcpu->arch.nmi_injected = false;
5515
42dbaa5a
JK		 5516 vcpu->arch.switch_db_regs = 0;
5517 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5518 vcpu->arch.dr6 = DR6_FIXED_1;
5519 vcpu->arch.dr7 = DR7_FIXED_1;
5520
e9b11c17
ZX		 5521 return kvm_x86_ops->vcpu_reset(vcpu);
5522}
5523
10474ae8 5524int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5525{
0cca7907
ZA		 5526 /*
5527 * Since this may be called from a hotplug notifcation,
5528 * we can't get the CPU frequency directly.
5529 */
5530 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5531 int cpu = raw_smp_processor_id();
5532 per_cpu(cpu_tsc_khz, cpu) = 0;
5533 }
18863bdd
AK		 5534
5535 kvm_shared_msr_cpu_online();
5536
10474ae8 5537 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5538}
5539
5540void kvm_arch_hardware_disable(void *garbage)
5541{
5542 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5543 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5544}
5545
5546int kvm_arch_hardware_setup(void)
5547{
5548 return kvm_x86_ops->hardware_setup();
5549}
5550
5551void kvm_arch_hardware_unsetup(void)
5552{
5553 kvm_x86_ops->hardware_unsetup();
5554}
5555
5556void kvm_arch_check_processor_compat(void *rtn)
5557{
5558 kvm_x86_ops->check_processor_compatibility(rtn);
5559}
5560
5561int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5562{
5563 struct page *page;
5564 struct kvm *kvm;
5565 int r;
5566
5567 BUG_ON(vcpu->kvm == NULL);
5568 kvm = vcpu->kvm;
5569
ad312c7c 5570 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5571 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5572 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5573 else
a4535290 5574 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5575
5576 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5577 if (!page) {
5578 r = -ENOMEM;
5579 goto fail;
5580 }
ad312c7c 5581 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5582
5583 r = kvm_mmu_create(vcpu);
5584 if (r < 0)
5585 goto fail_free_pio_data;
5586
5587 if (irqchip_in_kernel(kvm)) {
5588 r = kvm_create_lapic(vcpu);
5589 if (r < 0)
5590 goto fail_mmu_destroy;
5591 }
5592
890ca9ae
HY		 5593 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5594 GFP_KERNEL);
5595 if (!vcpu->arch.mce_banks) {
5596 r = -ENOMEM;
443c39bc 5597 goto fail_free_lapic;
890ca9ae
HY		 5598 }
5599 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5600
e9b11c17 5601 return 0;
443c39bc
WY		 5602fail_free_lapic:
5603 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5604fail_mmu_destroy:
5605 kvm_mmu_destroy(vcpu);
5606fail_free_pio_data:
ad312c7c 5607 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5608fail:
5609 return r;
5610}
5611
5612void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5613{
f656ce01
MT		 5614 int idx;
5615
36cb93fd 5616 kfree(vcpu->arch.mce_banks);
e9b11c17 5617 kvm_free_lapic(vcpu);
f656ce01 5618 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5619 kvm_mmu_destroy(vcpu);
f656ce01 5620 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5621 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5622}
d19a9cd2
ZX		 5623
5624struct kvm *kvm_arch_create_vm(void)
5625{
5626 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5627
5628 if (!kvm)
5629 return ERR_PTR(-ENOMEM);
5630
fef9cce0
MT		 5631 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5632 if (!kvm->arch.aliases) {
5633 kfree(kvm);
5634 return ERR_PTR(-ENOMEM);
5635 }
5636
f05e70ac 5637 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5638 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5639
5550af4d
SY		 5640 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5641 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5642
53f658b3
MT		 5643 rdtscll(kvm->arch.vm_init_tsc);
5644
d19a9cd2
ZX		 5645 return kvm;
5646}
5647
5648static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5649{
5650 vcpu_load(vcpu);
5651 kvm_mmu_unload(vcpu);
5652 vcpu_put(vcpu);
5653}
5654
5655static void kvm_free_vcpus(struct kvm *kvm)
5656{
5657 unsigned int i;
988a2cae 5658 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5659
5660 /*
5661 * Unpin any mmu pages first.
5662 */
988a2cae
GN		 5663 kvm_for_each_vcpu(i, vcpu, kvm)
5664 kvm_unload_vcpu_mmu(vcpu);
5665 kvm_for_each_vcpu(i, vcpu, kvm)
5666 kvm_arch_vcpu_free(vcpu);
5667
5668 mutex_lock(&kvm->lock);
5669 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5670 kvm->vcpus[i] = NULL;
d19a9cd2 5671
988a2cae
GN		 5672 atomic_set(&kvm->online_vcpus, 0);
5673 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5674}
5675
ad8ba2cd
SY		 5676void kvm_arch_sync_events(struct kvm *kvm)
5677{
ba4cef31 5678 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5679}
5680
d19a9cd2
ZX		 5681void kvm_arch_destroy_vm(struct kvm *kvm)
5682{
6eb55818 5683 kvm_iommu_unmap_guest(kvm);
7837699f 5684 kvm_free_pit(kvm);
d7deeeb0
ZX		 5685 kfree(kvm->arch.vpic);
5686 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5687 kvm_free_vcpus(kvm);
5688 kvm_free_physmem(kvm);
3d45830c
AK		 5689 if (kvm->arch.apic_access_page)
5690 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5691 if (kvm->arch.ept_identity_pagetable)
5692 put_page(kvm->arch.ept_identity_pagetable);
64749204 5693 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5694 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5695 kfree(kvm);
5696}
0de10343 5697
f7784b8e
MT		 5698int kvm_arch_prepare_memory_region(struct kvm *kvm,
5699 struct kvm_memory_slot *memslot,
0de10343 5700 struct kvm_memory_slot old,
f7784b8e 5701 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5702 int user_alloc)
5703{
f7784b8e 5704 int npages = memslot->npages;
0de10343
ZX		 5705
5706 /*To keep backward compatibility with older userspace,
5707 *x86 needs to hanlde !user_alloc case.
5708 */
5709 if (!user_alloc) {
5710 if (npages && !old.rmap) {
604b38ac
AA		 5711 unsigned long userspace_addr;
5712
72dc67a6 5713 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5714 userspace_addr = do_mmap(NULL, 0,
5715 npages * PAGE_SIZE,
5716 PROT_READ | PROT_WRITE,
acee3c04 5717 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5718 0);
72dc67a6 5719 up_write(&current->mm->mmap_sem);
0de10343 5720
604b38ac
AA		 5721 if (IS_ERR((void *)userspace_addr))
5722 return PTR_ERR((void *)userspace_addr);
5723
604b38ac 5724 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5725 }
5726 }
5727
f7784b8e
MT		 5728
5729 return 0;
5730}
5731
5732void kvm_arch_commit_memory_region(struct kvm *kvm,
5733 struct kvm_userspace_memory_region *mem,
5734 struct kvm_memory_slot old,
5735 int user_alloc)
5736{
5737
5738 int npages = mem->memory_size >> PAGE_SHIFT;
5739
5740 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5741 int ret;
5742
5743 down_write(&current->mm->mmap_sem);
5744 ret = do_munmap(current->mm, old.userspace_addr,
5745 old.npages * PAGE_SIZE);
5746 up_write(&current->mm->mmap_sem);
5747 if (ret < 0)
5748 printk(KERN_WARNING
5749 "kvm_vm_ioctl_set_memory_region: "
5750 "failed to munmap memory\n");
5751 }
5752
7c8a83b7 5753 spin_lock(&kvm->mmu_lock);
f05e70ac 5754 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5755 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5756 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5757 }
5758
5759 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5760 spin_unlock(&kvm->mmu_lock);
0de10343 5761}
1d737c8a 5762
34d4cb8f
MT		 5763void kvm_arch_flush_shadow(struct kvm *kvm)
5764{
5765 kvm_mmu_zap_all(kvm);
8986ecc0 5766 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5767}
5768
1d737c8a
ZX		 5769int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5770{
a4535290 5771 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5772 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5773 || vcpu->arch.nmi_pending ||
5774 (kvm_arch_interrupt_allowed(vcpu) &&
5775 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5776}
5736199a 5777
5736199a
ZX		 5778void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5779{
32f88400
MT		 5780 int me;
5781 int cpu = vcpu->cpu;
5736199a
ZX		 5782
5783 if (waitqueue_active(&vcpu->wq)) {
5784 wake_up_interruptible(&vcpu->wq);
5785 ++vcpu->stat.halt_wakeup;
5786 }
32f88400
MT		 5787
5788 me = get_cpu();
5789 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5790 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5791 smp_send_reschedule(cpu);
e9571ed5 5792 put_cpu();
5736199a 5793}
78646121
GN		 5794
5795int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5796{
5797 return kvm_x86_ops->interrupt_allowed(vcpu);
5798}
229456fc 5799
94fe45da
JK		 5800unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5801{
5802 unsigned long rflags;
5803
5804 rflags = kvm_x86_ops->get_rflags(vcpu);
5805 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5806 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5807 return rflags;
5808}
5809EXPORT_SYMBOL_GPL(kvm_get_rflags);
5810
5811void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5812{
5813 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5814 vcpu->arch.singlestep_cs ==
5815 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5816 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5817 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5818 kvm_x86_ops->set_rflags(vcpu, rflags);
5819}
5820EXPORT_SYMBOL_GPL(kvm_set_rflags);
5821
229456fc
MT		 5822EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5823EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5824EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5825EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5826EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5827EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5828EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5829EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5830EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5831EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5832EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
kernel source for telekom puls (alcatel/mediatek)