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KVM: MMU: Make walk_addr_generic capable for two-level walking
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
287 if (!vcpu->arch.exception.pending) {
288 queue:
289 vcpu->arch.exception.pending = true;
290 vcpu->arch.exception.has_error_code = has_error;
291 vcpu->arch.exception.nr = nr;
292 vcpu->arch.exception.error_code = error_code;
3f0fd292 293 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 294 return;
295 }
296
297 /* to check exception */
298 prev_nr = vcpu->arch.exception.nr;
299 if (prev_nr == DF_VECTOR) {
300 /* triple fault -> shutdown */
a8eeb04a 301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 302 return;
303 }
304 class1 = exception_class(prev_nr);
305 class2 = exception_class(nr);
306 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
307 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
308 /* generate double fault per SDM Table 5-5 */
309 vcpu->arch.exception.pending = true;
310 vcpu->arch.exception.has_error_code = true;
311 vcpu->arch.exception.nr = DF_VECTOR;
312 vcpu->arch.exception.error_code = 0;
313 } else
314 /* replace previous exception with a new one in a hope
315 that instruction re-execution will regenerate lost
316 exception */
317 goto queue;
318}
319
298101da
AK		 320void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
321{
ce7ddec4 322 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 323}
324EXPORT_SYMBOL_GPL(kvm_queue_exception);
325
ce7ddec4
JR		 326void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
327{
328 kvm_multiple_exception(vcpu, nr, false, 0, true);
329}
330EXPORT_SYMBOL_GPL(kvm_requeue_exception);
331
8df25a32 332void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 333{
8df25a32
JR		 334 unsigned error_code = vcpu->arch.fault.error_code;
335
c3c91fee 336 ++vcpu->stat.pf_guest;
8df25a32 337 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 338 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
339}
340
3419ffc8
SY		 341void kvm_inject_nmi(struct kvm_vcpu *vcpu)
342{
343 vcpu->arch.nmi_pending = 1;
344}
345EXPORT_SYMBOL_GPL(kvm_inject_nmi);
346
298101da
AK		 347void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
348{
ce7ddec4 349 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 350}
351EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
352
ce7ddec4
JR		 353void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
354{
355 kvm_multiple_exception(vcpu, nr, true, error_code, true);
356}
357EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
358
0a79b009
AK		 359/*
360 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
361 * a #GP and return false.
362 */
363bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 364{
0a79b009
AK		 365 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
366 return true;
367 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
368 return false;
298101da 369}
0a79b009 370EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 371
ec92fe44
JR		 372/*
373 * This function will be used to read from the physical memory of the currently
374 * running guest. The difference to kvm_read_guest_page is that this function
375 * can read from guest physical or from the guest's guest physical memory.
376 */
377int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
378 gfn_t ngfn, void *data, int offset, int len,
379 u32 access)
380{
381 gfn_t real_gfn;
382 gpa_t ngpa;
383
384 ngpa = gfn_to_gpa(ngfn);
385 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
386 if (real_gfn == UNMAPPED_GVA)
387 return -EFAULT;
388
389 real_gfn = gpa_to_gfn(real_gfn);
390
391 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
392}
393EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
394
a03490ed
CO		 395/*
396 * Load the pae pdptrs. Return true is they are all valid.
397 */
398int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
399{
400 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
401 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
402 int i;
403 int ret;
ad312c7c 404 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 405
a03490ed
CO		 406 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
407 offset * sizeof(u64), sizeof(pdpte));
408 if (ret < 0) {
409 ret = 0;
410 goto out;
411 }
412 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 413 if (is_present_gpte(pdpte[i]) &&
20c466b5 414 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 415 ret = 0;
416 goto out;
417 }
418 }
419 ret = 1;
420
ad312c7c 421 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 422 __set_bit(VCPU_EXREG_PDPTR,
423 (unsigned long *)&vcpu->arch.regs_avail);
424 __set_bit(VCPU_EXREG_PDPTR,
425 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 426out:
a03490ed
CO		 427
428 return ret;
429}
cc4b6871 430EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 431
d835dfec
AK		 432static bool pdptrs_changed(struct kvm_vcpu *vcpu)
433{
ad312c7c 434 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 435 bool changed = true;
436 int r;
437
438 if (is_long_mode(vcpu) || !is_pae(vcpu))
439 return false;
440
6de4f3ad
AK		 441 if (!test_bit(VCPU_EXREG_PDPTR,
442 (unsigned long *)&vcpu->arch.regs_avail))
443 return true;
444
ad312c7c 445 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 446 if (r < 0)
447 goto out;
ad312c7c 448 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 449out:
d835dfec
AK		 450
451 return changed;
452}
453
49a9b07e 454int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 455{
aad82703
SY		 456 unsigned long old_cr0 = kvm_read_cr0(vcpu);
457 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
458 X86_CR0_CD | X86_CR0_NW;
459
f9a48e6a
AK		 460 cr0 |= X86_CR0_ET;
461
ab344828 462#ifdef CONFIG_X86_64
0f12244f
GN		 463 if (cr0 & 0xffffffff00000000UL)
464 return 1;
ab344828
GN		 465#endif
466
467 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 468
0f12244f
GN		 469 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
470 return 1;
a03490ed 471
0f12244f
GN		 472 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
473 return 1;
a03490ed
CO		 474
475 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
476#ifdef CONFIG_X86_64
f6801dff 477 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 478 int cs_db, cs_l;
479
0f12244f
GN		 480 if (!is_pae(vcpu))
481 return 1;
a03490ed 482 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 483 if (cs_l)
484 return 1;
a03490ed
CO		 485 } else
486#endif
0f12244f
GN		 487 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
488 return 1;
a03490ed
CO		 489 }
490
491 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 492
aad82703
SY		 493 if ((cr0 ^ old_cr0) & update_bits)
494 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 495 return 0;
496}
2d3ad1f4 497EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 498
2d3ad1f4 499void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 500{
49a9b07e 501 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 502}
2d3ad1f4 503EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 504
2acf923e
DC		 505int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
506{
507 u64 xcr0;
508
509 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
510 if (index != XCR_XFEATURE_ENABLED_MASK)
511 return 1;
512 xcr0 = xcr;
513 if (kvm_x86_ops->get_cpl(vcpu) != 0)
514 return 1;
515 if (!(xcr0 & XSTATE_FP))
516 return 1;
517 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
518 return 1;
519 if (xcr0 & ~host_xcr0)
520 return 1;
521 vcpu->arch.xcr0 = xcr0;
522 vcpu->guest_xcr0_loaded = 0;
523 return 0;
524}
525
526int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
527{
528 if (__kvm_set_xcr(vcpu, index, xcr)) {
529 kvm_inject_gp(vcpu, 0);
530 return 1;
531 }
532 return 0;
533}
534EXPORT_SYMBOL_GPL(kvm_set_xcr);
535
536static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
537{
538 struct kvm_cpuid_entry2 *best;
539
540 best = kvm_find_cpuid_entry(vcpu, 1, 0);
541 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
542}
543
544static void update_cpuid(struct kvm_vcpu *vcpu)
545{
546 struct kvm_cpuid_entry2 *best;
547
548 best = kvm_find_cpuid_entry(vcpu, 1, 0);
549 if (!best)
550 return;
551
552 /* Update OSXSAVE bit */
553 if (cpu_has_xsave && best->function == 0x1) {
554 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
555 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
556 best->ecx |= bit(X86_FEATURE_OSXSAVE);
557 }
558}
559
a83b29c6 560int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 561{
fc78f519 562 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 563 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
564
0f12244f
GN		 565 if (cr4 & CR4_RESERVED_BITS)
566 return 1;
a03490ed 567
2acf923e
DC		 568 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
569 return 1;
570
a03490ed 571 if (is_long_mode(vcpu)) {
0f12244f
GN		 572 if (!(cr4 & X86_CR4_PAE))
573 return 1;
a2edf57f
AK		 574 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
575 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 576 && !load_pdptrs(vcpu, vcpu->arch.cr3))
577 return 1;
578
579 if (cr4 & X86_CR4_VMXE)
580 return 1;
a03490ed 581
a03490ed 582 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 583
aad82703
SY		 584 if ((cr4 ^ old_cr4) & pdptr_bits)
585 kvm_mmu_reset_context(vcpu);
0f12244f 586
2acf923e
DC		 587 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
588 update_cpuid(vcpu);
589
0f12244f
GN		 590 return 0;
591}
2d3ad1f4 592EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 593
2390218b 594int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 595{
ad312c7c 596 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 597 kvm_mmu_sync_roots(vcpu);
d835dfec 598 kvm_mmu_flush_tlb(vcpu);
0f12244f 599 return 0;
d835dfec
AK		 600 }
601
a03490ed 602 if (is_long_mode(vcpu)) {
0f12244f
GN		 603 if (cr3 & CR3_L_MODE_RESERVED_BITS)
604 return 1;
a03490ed
CO		 605 } else {
606 if (is_pae(vcpu)) {
0f12244f
GN		 607 if (cr3 & CR3_PAE_RESERVED_BITS)
608 return 1;
609 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
610 return 1;
a03490ed
CO		 611 }
612 /*
613 * We don't check reserved bits in nonpae mode, because
614 * this isn't enforced, and VMware depends on this.
615 */
616 }
617
a03490ed
CO		 618 /*
619 * Does the new cr3 value map to physical memory? (Note, we
620 * catch an invalid cr3 even in real-mode, because it would
621 * cause trouble later on when we turn on paging anyway.)
622 *
623 * A real CPU would silently accept an invalid cr3 and would
624 * attempt to use it - with largely undefined (and often hard
625 * to debug) behavior on the guest side.
626 */
627 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 628 return 1;
629 vcpu->arch.cr3 = cr3;
630 vcpu->arch.mmu.new_cr3(vcpu);
631 return 0;
632}
2d3ad1f4 633EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 634
0f12244f 635int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 636{
0f12244f
GN		 637 if (cr8 & CR8_RESERVED_BITS)
638 return 1;
a03490ed
CO		 639 if (irqchip_in_kernel(vcpu->kvm))
640 kvm_lapic_set_tpr(vcpu, cr8);
641 else
ad312c7c 642 vcpu->arch.cr8 = cr8;
0f12244f
GN		 643 return 0;
644}
645
646void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
647{
648 if (__kvm_set_cr8(vcpu, cr8))
649 kvm_inject_gp(vcpu, 0);
a03490ed 650}
2d3ad1f4 651EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 652
2d3ad1f4 653unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 654{
655 if (irqchip_in_kernel(vcpu->kvm))
656 return kvm_lapic_get_cr8(vcpu);
657 else
ad312c7c 658 return vcpu->arch.cr8;
a03490ed 659}
2d3ad1f4 660EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 661
338dbc97 662static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 663{
664 switch (dr) {
665 case 0 ... 3:
666 vcpu->arch.db[dr] = val;
667 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
668 vcpu->arch.eff_db[dr] = val;
669 break;
670 case 4:
338dbc97
GN		 671 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
672 return 1; /* #UD */
020df079
GN		 673 /* fall through */
674 case 6:
338dbc97
GN		 675 if (val & 0xffffffff00000000ULL)
676 return -1; /* #GP */
020df079
GN		 677 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
678 break;
679 case 5:
338dbc97
GN		 680 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
681 return 1; /* #UD */
020df079
GN		 682 /* fall through */
683 default: /* 7 */
338dbc97
GN		 684 if (val & 0xffffffff00000000ULL)
685 return -1; /* #GP */
020df079
GN		 686 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
687 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
688 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
689 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
690 }
691 break;
692 }
693
694 return 0;
695}
338dbc97
GN		 696
697int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
698{
699 int res;
700
701 res = __kvm_set_dr(vcpu, dr, val);
702 if (res > 0)
703 kvm_queue_exception(vcpu, UD_VECTOR);
704 else if (res < 0)
705 kvm_inject_gp(vcpu, 0);
706
707 return res;
708}
020df079
GN		 709EXPORT_SYMBOL_GPL(kvm_set_dr);
710
338dbc97 711static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 712{
713 switch (dr) {
714 case 0 ... 3:
715 *val = vcpu->arch.db[dr];
716 break;
717 case 4:
338dbc97 718 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 719 return 1;
020df079
GN		 720 /* fall through */
721 case 6:
722 *val = vcpu->arch.dr6;
723 break;
724 case 5:
338dbc97 725 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 726 return 1;
020df079
GN		 727 /* fall through */
728 default: /* 7 */
729 *val = vcpu->arch.dr7;
730 break;
731 }
732
733 return 0;
734}
338dbc97
GN		 735
736int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
737{
738 if (_kvm_get_dr(vcpu, dr, val)) {
739 kvm_queue_exception(vcpu, UD_VECTOR);
740 return 1;
741 }
742 return 0;
743}
020df079
GN		 744EXPORT_SYMBOL_GPL(kvm_get_dr);
745
043405e1
CO		 746/*
747 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
748 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
749 *
750 * This list is modified at module load time to reflect the
e3267cbb
GC		 751 * capabilities of the host cpu. This capabilities test skips MSRs that are
752 * kvm-specific. Those are put in the beginning of the list.
043405e1 753 */
e3267cbb 754
11c6bffa 755#define KVM_SAVE_MSRS_BEGIN 7
043405e1 756static u32 msrs_to_save[] = {
e3267cbb 757 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 758 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 759 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 760 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 761 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 762 MSR_STAR,
043405e1
CO		 763#ifdef CONFIG_X86_64
764 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
765#endif
e90aa41e 766 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 767};
768
769static unsigned num_msrs_to_save;
770
771static u32 emulated_msrs[] = {
772 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 773 MSR_IA32_MCG_STATUS,
774 MSR_IA32_MCG_CTL,
043405e1
CO		 775};
776
b69e8cae 777static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 778{
aad82703
SY		 779 u64 old_efer = vcpu->arch.efer;
780
b69e8cae
RJ		 781 if (efer & efer_reserved_bits)
782 return 1;
15c4a640
CO		 783
784 if (is_paging(vcpu)
b69e8cae
RJ		 785 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
786 return 1;
15c4a640 787
1b2fd70c
AG		 788 if (efer & EFER_FFXSR) {
789 struct kvm_cpuid_entry2 *feat;
790
791 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 792 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
793 return 1;
1b2fd70c
AG		 794 }
795
d8017474
AG		 796 if (efer & EFER_SVME) {
797 struct kvm_cpuid_entry2 *feat;
798
799 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 800 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
801 return 1;
d8017474
AG		 802 }
803
15c4a640 804 efer &= ~EFER_LMA;
f6801dff 805 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 806
a3d204e2
SY		 807 kvm_x86_ops->set_efer(vcpu, efer);
808
9645bb56
AK		 809 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
810 kvm_mmu_reset_context(vcpu);
b69e8cae 811
aad82703
SY		 812 /* Update reserved bits */
813 if ((efer ^ old_efer) & EFER_NX)
814 kvm_mmu_reset_context(vcpu);
815
b69e8cae 816 return 0;
15c4a640
CO		 817}
818
f2b4b7dd
JR		 819void kvm_enable_efer_bits(u64 mask)
820{
821 efer_reserved_bits &= ~mask;
822}
823EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
824
825
15c4a640
CO		 826/*
827 * Writes msr value into into the appropriate "register".
828 * Returns 0 on success, non-0 otherwise.
829 * Assumes vcpu_load() was already called.
830 */
831int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
832{
833 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
834}
835
313a3dc7
CO		 836/*
837 * Adapt set_msr() to msr_io()'s calling convention
838 */
839static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
840{
841 return kvm_set_msr(vcpu, index, *data);
842}
843
18068523
GOC		 844static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
845{
9ed3c444
AK		 846 int version;
847 int r;
50d0a0f9 848 struct pvclock_wall_clock wc;
923de3cf 849 struct timespec boot;
18068523
GOC		 850
851 if (!wall_clock)
852 return;
853
9ed3c444
AK		 854 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
855 if (r)
856 return;
857
858 if (version & 1)
859 ++version; /* first time write, random junk */
860
861 ++version;
18068523 862
18068523
GOC		 863 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
864
50d0a0f9
GH		 865 /*
866 * The guest calculates current wall clock time by adding
867 * system time (updated by kvm_write_guest_time below) to the
868 * wall clock specified here. guest system time equals host
869 * system time for us, thus we must fill in host boot time here.
870 */
923de3cf 871 getboottime(&boot);
50d0a0f9
GH		 872
873 wc.sec = boot.tv_sec;
874 wc.nsec = boot.tv_nsec;
875 wc.version = version;
18068523
GOC		 876
877 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
878
879 version++;
880 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 881}
882
50d0a0f9
GH		 883static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
884{
885 uint32_t quotient, remainder;
886
887 /* Don't try to replace with do_div(), this one calculates
888 * "(dividend << 32) / divisor" */
889 __asm__ ( "divl %4"
890 : "=a" (quotient), "=d" (remainder)
891 : "0" (0), "1" (dividend), "r" (divisor) );
892 return quotient;
893}
894
895static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
896{
897 uint64_t nsecs = 1000000000LL;
898 int32_t shift = 0;
899 uint64_t tps64;
900 uint32_t tps32;
901
902 tps64 = tsc_khz * 1000LL;
903 while (tps64 > nsecs*2) {
904 tps64 >>= 1;
905 shift--;
906 }
907
908 tps32 = (uint32_t)tps64;
909 while (tps32 <= (uint32_t)nsecs) {
910 tps32 <<= 1;
911 shift++;
912 }
913
914 hv_clock->tsc_shift = shift;
915 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
916
917 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 918 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 919 hv_clock->tsc_to_system_mul);
920}
921
759379dd
ZA		 922static inline u64 get_kernel_ns(void)
923{
924 struct timespec ts;
925
926 WARN_ON(preemptible());
927 ktime_get_ts(&ts);
928 monotonic_to_bootbased(&ts);
929 return timespec_to_ns(&ts);
930}
931
c8076604
GH		 932static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
933
8cfdc000
ZA		 934static inline int kvm_tsc_changes_freq(void)
935{
936 int cpu = get_cpu();
937 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
938 cpufreq_quick_get(cpu) != 0;
939 put_cpu();
940 return ret;
941}
942
759379dd
ZA		 943static inline u64 nsec_to_cycles(u64 nsec)
944{
217fc9cf
AK		 945 u64 ret;
946
759379dd
ZA		 947 WARN_ON(preemptible());
948 if (kvm_tsc_changes_freq())
949 printk_once(KERN_WARNING
950 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 951 ret = nsec * __get_cpu_var(cpu_tsc_khz);
952 do_div(ret, USEC_PER_SEC);
953 return ret;
759379dd
ZA		 954}
955
99e3e30a
ZA		 956void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
957{
958 struct kvm *kvm = vcpu->kvm;
f38e098f 959 u64 offset, ns, elapsed;
99e3e30a 960 unsigned long flags;
46543ba4 961 s64 sdiff;
99e3e30a
ZA		 962
963 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
964 offset = data - native_read_tsc();
759379dd 965 ns = get_kernel_ns();
f38e098f 966 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 967 sdiff = data - kvm->arch.last_tsc_write;
968 if (sdiff < 0)
969 sdiff = -sdiff;
f38e098f
ZA		 970
971 /*
46543ba4 972 * Special case: close write to TSC within 5 seconds of
f38e098f 973 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 974 * The 5 seconds is to accomodate host load / swapping as
975 * well as any reset of TSC during the boot process.
f38e098f
ZA		 976 *
977 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 978 * or make a best guest using elapsed value.
f38e098f 979 */
46543ba4
ZA		 980 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
981 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 982 if (!check_tsc_unstable()) {
983 offset = kvm->arch.last_tsc_offset;
984 pr_debug("kvm: matched tsc offset for %llu\n", data);
985 } else {
759379dd
ZA		 986 u64 delta = nsec_to_cycles(elapsed);
987 offset += delta;
988 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 989 }
990 ns = kvm->arch.last_tsc_nsec;
991 }
992 kvm->arch.last_tsc_nsec = ns;
993 kvm->arch.last_tsc_write = data;
994 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 995 kvm_x86_ops->write_tsc_offset(vcpu, offset);
996 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
997
998 /* Reset of TSC must disable overshoot protection below */
999 vcpu->arch.hv_clock.tsc_timestamp = 0;
1000}
1001EXPORT_SYMBOL_GPL(kvm_write_tsc);
1002
8cfdc000 1003static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 1004{
18068523
GOC		 1005 unsigned long flags;
1006 struct kvm_vcpu_arch *vcpu = &v->arch;
1007 void *shared_kaddr;
463656c0 1008 unsigned long this_tsc_khz;
1d5f066e
ZA		 1009 s64 kernel_ns, max_kernel_ns;
1010 u64 tsc_timestamp;
18068523
GOC		 1011
1012 if ((!vcpu->time_page))
8cfdc000 1013 return 0;
50d0a0f9 1014
18068523
GOC		 1015 /* Keep irq disabled to prevent changes to the clock */
1016 local_irq_save(flags);
1d5f066e 1017 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1018 kernel_ns = get_kernel_ns();
8cfdc000 1019 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 1020 local_irq_restore(flags);
1021
8cfdc000
ZA		 1022 if (unlikely(this_tsc_khz == 0)) {
1023 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1024 return 1;
1025 }
18068523 1026
1d5f066e
ZA		 1027 /*
1028 * Time as measured by the TSC may go backwards when resetting the base
1029 * tsc_timestamp. The reason for this is that the TSC resolution is
1030 * higher than the resolution of the other clock scales. Thus, many
1031 * possible measurments of the TSC correspond to one measurement of any
1032 * other clock, and so a spread of values is possible. This is not a
1033 * problem for the computation of the nanosecond clock; with TSC rates
1034 * around 1GHZ, there can only be a few cycles which correspond to one
1035 * nanosecond value, and any path through this code will inevitably
1036 * take longer than that. However, with the kernel_ns value itself,
1037 * the precision may be much lower, down to HZ granularity. If the
1038 * first sampling of TSC against kernel_ns ends in the low part of the
1039 * range, and the second in the high end of the range, we can get:
1040 *
1041 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1042 *
1043 * As the sampling errors potentially range in the thousands of cycles,
1044 * it is possible such a time value has already been observed by the
1045 * guest. To protect against this, we must compute the system time as
1046 * observed by the guest and ensure the new system time is greater.
1047 */
1048 max_kernel_ns = 0;
1049 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1050 max_kernel_ns = vcpu->last_guest_tsc -
1051 vcpu->hv_clock.tsc_timestamp;
1052 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1053 vcpu->hv_clock.tsc_to_system_mul,
1054 vcpu->hv_clock.tsc_shift);
1055 max_kernel_ns += vcpu->last_kernel_ns;
1056 }
1057
e48672fa 1058 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1059 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1060 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1061 }
1062
1d5f066e
ZA		 1063 if (max_kernel_ns > kernel_ns)
1064 kernel_ns = max_kernel_ns;
1065
8cfdc000 1066 /* With all the info we got, fill in the values */
1d5f066e 1067 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1068 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1069 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1070 vcpu->hv_clock.flags = 0;
1071
18068523
GOC		 1072 /*
1073 * The interface expects us to write an even number signaling that the
1074 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1075 * state, we just increase by 2 at the end.
18068523 1076 */
50d0a0f9 1077 vcpu->hv_clock.version += 2;
18068523
GOC		 1078
1079 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1080
1081 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1082 sizeof(vcpu->hv_clock));
18068523
GOC		 1083
1084 kunmap_atomic(shared_kaddr, KM_USER0);
1085
1086 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1087 return 0;
18068523
GOC		 1088}
1089
c8076604
GH		 1090static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1091{
1092 struct kvm_vcpu_arch *vcpu = &v->arch;
1093
1094 if (!vcpu->time_page)
1095 return 0;
a8eeb04a 1096 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1097 return 1;
1098}
1099
9ba075a6
AK		 1100static bool msr_mtrr_valid(unsigned msr)
1101{
1102 switch (msr) {
1103 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1104 case MSR_MTRRfix64K_00000:
1105 case MSR_MTRRfix16K_80000:
1106 case MSR_MTRRfix16K_A0000:
1107 case MSR_MTRRfix4K_C0000:
1108 case MSR_MTRRfix4K_C8000:
1109 case MSR_MTRRfix4K_D0000:
1110 case MSR_MTRRfix4K_D8000:
1111 case MSR_MTRRfix4K_E0000:
1112 case MSR_MTRRfix4K_E8000:
1113 case MSR_MTRRfix4K_F0000:
1114 case MSR_MTRRfix4K_F8000:
1115 case MSR_MTRRdefType:
1116 case MSR_IA32_CR_PAT:
1117 return true;
1118 case 0x2f8:
1119 return true;
1120 }
1121 return false;
1122}
1123
d6289b93
MT		 1124static bool valid_pat_type(unsigned t)
1125{
1126 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1127}
1128
1129static bool valid_mtrr_type(unsigned t)
1130{
1131 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1132}
1133
1134static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1135{
1136 int i;
1137
1138 if (!msr_mtrr_valid(msr))
1139 return false;
1140
1141 if (msr == MSR_IA32_CR_PAT) {
1142 for (i = 0; i < 8; i++)
1143 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1144 return false;
1145 return true;
1146 } else if (msr == MSR_MTRRdefType) {
1147 if (data & ~0xcff)
1148 return false;
1149 return valid_mtrr_type(data & 0xff);
1150 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1151 for (i = 0; i < 8 ; i++)
1152 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1153 return false;
1154 return true;
1155 }
1156
1157 /* variable MTRRs */
1158 return valid_mtrr_type(data & 0xff);
1159}
1160
9ba075a6
AK		 1161static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1162{
0bed3b56
SY		 1163 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1164
d6289b93 1165 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1166 return 1;
1167
0bed3b56
SY		 1168 if (msr == MSR_MTRRdefType) {
1169 vcpu->arch.mtrr_state.def_type = data;
1170 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1171 } else if (msr == MSR_MTRRfix64K_00000)
1172 p[0] = data;
1173 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1174 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1175 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1176 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1177 else if (msr == MSR_IA32_CR_PAT)
1178 vcpu->arch.pat = data;
1179 else { /* Variable MTRRs */
1180 int idx, is_mtrr_mask;
1181 u64 *pt;
1182
1183 idx = (msr - 0x200) / 2;
1184 is_mtrr_mask = msr - 0x200 - 2 * idx;
1185 if (!is_mtrr_mask)
1186 pt =
1187 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1188 else
1189 pt =
1190 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1191 *pt = data;
1192 }
1193
1194 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1195 return 0;
1196}
15c4a640 1197
890ca9ae 1198static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1199{
890ca9ae
HY		 1200 u64 mcg_cap = vcpu->arch.mcg_cap;
1201 unsigned bank_num = mcg_cap & 0xff;
1202
15c4a640 1203 switch (msr) {
15c4a640 1204 case MSR_IA32_MCG_STATUS:
890ca9ae 1205 vcpu->arch.mcg_status = data;
15c4a640 1206 break;
c7ac679c 1207 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1208 if (!(mcg_cap & MCG_CTL_P))
1209 return 1;
1210 if (data != 0 && data != ~(u64)0)
1211 return -1;
1212 vcpu->arch.mcg_ctl = data;
1213 break;
1214 default:
1215 if (msr >= MSR_IA32_MC0_CTL &&
1216 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1217 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1218 /* only 0 or all 1s can be written to IA32_MCi_CTL
1219 * some Linux kernels though clear bit 10 in bank 4 to
1220 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1221 * this to avoid an uncatched #GP in the guest
1222 */
890ca9ae 1223 if ((offset & 0x3) == 0 &&
114be429 1224 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1225 return -1;
1226 vcpu->arch.mce_banks[offset] = data;
1227 break;
1228 }
1229 return 1;
1230 }
1231 return 0;
1232}
1233
ffde22ac
ES		 1234static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1235{
1236 struct kvm *kvm = vcpu->kvm;
1237 int lm = is_long_mode(vcpu);
1238 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1239 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1240 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1241 : kvm->arch.xen_hvm_config.blob_size_32;
1242 u32 page_num = data & ~PAGE_MASK;
1243 u64 page_addr = data & PAGE_MASK;
1244 u8 *page;
1245 int r;
1246
1247 r = -E2BIG;
1248 if (page_num >= blob_size)
1249 goto out;
1250 r = -ENOMEM;
1251 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1252 if (!page)
1253 goto out;
1254 r = -EFAULT;
1255 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1256 goto out_free;
1257 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1258 goto out_free;
1259 r = 0;
1260out_free:
1261 kfree(page);
1262out:
1263 return r;
1264}
1265
55cd8e5a
GN		 1266static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1267{
1268 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1269}
1270
1271static bool kvm_hv_msr_partition_wide(u32 msr)
1272{
1273 bool r = false;
1274 switch (msr) {
1275 case HV_X64_MSR_GUEST_OS_ID:
1276 case HV_X64_MSR_HYPERCALL:
1277 r = true;
1278 break;
1279 }
1280
1281 return r;
1282}
1283
1284static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1285{
1286 struct kvm *kvm = vcpu->kvm;
1287
1288 switch (msr) {
1289 case HV_X64_MSR_GUEST_OS_ID:
1290 kvm->arch.hv_guest_os_id = data;
1291 /* setting guest os id to zero disables hypercall page */
1292 if (!kvm->arch.hv_guest_os_id)
1293 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1294 break;
1295 case HV_X64_MSR_HYPERCALL: {
1296 u64 gfn;
1297 unsigned long addr;
1298 u8 instructions[4];
1299
1300 /* if guest os id is not set hypercall should remain disabled */
1301 if (!kvm->arch.hv_guest_os_id)
1302 break;
1303 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1304 kvm->arch.hv_hypercall = data;
1305 break;
1306 }
1307 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1308 addr = gfn_to_hva(kvm, gfn);
1309 if (kvm_is_error_hva(addr))
1310 return 1;
1311 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1312 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1313 if (copy_to_user((void __user *)addr, instructions, 4))
1314 return 1;
1315 kvm->arch.hv_hypercall = data;
1316 break;
1317 }
1318 default:
1319 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1320 "data 0x%llx\n", msr, data);
1321 return 1;
1322 }
1323 return 0;
1324}
1325
1326static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1327{
10388a07
GN		 1328 switch (msr) {
1329 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1330 unsigned long addr;
55cd8e5a 1331
10388a07
GN		 1332 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1333 vcpu->arch.hv_vapic = data;
1334 break;
1335 }
1336 addr = gfn_to_hva(vcpu->kvm, data >>
1337 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1338 if (kvm_is_error_hva(addr))
1339 return 1;
1340 if (clear_user((void __user *)addr, PAGE_SIZE))
1341 return 1;
1342 vcpu->arch.hv_vapic = data;
1343 break;
1344 }
1345 case HV_X64_MSR_EOI:
1346 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1347 case HV_X64_MSR_ICR:
1348 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1349 case HV_X64_MSR_TPR:
1350 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1351 default:
1352 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1353 "data 0x%llx\n", msr, data);
1354 return 1;
1355 }
1356
1357 return 0;
55cd8e5a
GN		 1358}
1359
15c4a640
CO		 1360int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1361{
1362 switch (msr) {
15c4a640 1363 case MSR_EFER:
b69e8cae 1364 return set_efer(vcpu, data);
8f1589d9
AP		 1365 case MSR_K7_HWCR:
1366 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1367 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1368 if (data != 0) {
1369 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1370 data);
1371 return 1;
1372 }
15c4a640 1373 break;
f7c6d140
AP		 1374 case MSR_FAM10H_MMIO_CONF_BASE:
1375 if (data != 0) {
1376 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1377 "0x%llx\n", data);
1378 return 1;
1379 }
15c4a640 1380 break;
c323c0e5 1381 case MSR_AMD64_NB_CFG:
c7ac679c 1382 break;
b5e2fec0
AG		 1383 case MSR_IA32_DEBUGCTLMSR:
1384 if (!data) {
1385 /* We support the non-activated case already */
1386 break;
1387 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1388 /* Values other than LBR and BTF are vendor-specific,
1389 thus reserved and should throw a #GP */
1390 return 1;
1391 }
1392 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1393 __func__, data);
1394 break;
15c4a640
CO		 1395 case MSR_IA32_UCODE_REV:
1396 case MSR_IA32_UCODE_WRITE:
61a6bd67 1397 case MSR_VM_HSAVE_PA:
6098ca93 1398 case MSR_AMD64_PATCH_LOADER:
15c4a640 1399 break;
9ba075a6
AK		 1400 case 0x200 ... 0x2ff:
1401 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1402 case MSR_IA32_APICBASE:
1403 kvm_set_apic_base(vcpu, data);
1404 break;
0105d1a5
GN		 1405 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1406 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1407 case MSR_IA32_MISC_ENABLE:
ad312c7c 1408 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1409 break;
11c6bffa 1410 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1411 case MSR_KVM_WALL_CLOCK:
1412 vcpu->kvm->arch.wall_clock = data;
1413 kvm_write_wall_clock(vcpu->kvm, data);
1414 break;
11c6bffa 1415 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1416 case MSR_KVM_SYSTEM_TIME: {
1417 if (vcpu->arch.time_page) {
1418 kvm_release_page_dirty(vcpu->arch.time_page);
1419 vcpu->arch.time_page = NULL;
1420 }
1421
1422 vcpu->arch.time = data;
1423
1424 /* we verify if the enable bit is set... */
1425 if (!(data & 1))
1426 break;
1427
1428 /* ...but clean it before doing the actual write */
1429 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1430
18068523
GOC		 1431 vcpu->arch.time_page =
1432 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1433
1434 if (is_error_page(vcpu->arch.time_page)) {
1435 kvm_release_page_clean(vcpu->arch.time_page);
1436 vcpu->arch.time_page = NULL;
1437 }
1438
c8076604 1439 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1440 break;
1441 }
890ca9ae
HY		 1442 case MSR_IA32_MCG_CTL:
1443 case MSR_IA32_MCG_STATUS:
1444 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1445 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1446
1447 /* Performance counters are not protected by a CPUID bit,
1448 * so we should check all of them in the generic path for the sake of
1449 * cross vendor migration.
1450 * Writing a zero into the event select MSRs disables them,
1451 * which we perfectly emulate ;-). Any other value should be at least
1452 * reported, some guests depend on them.
1453 */
1454 case MSR_P6_EVNTSEL0:
1455 case MSR_P6_EVNTSEL1:
1456 case MSR_K7_EVNTSEL0:
1457 case MSR_K7_EVNTSEL1:
1458 case MSR_K7_EVNTSEL2:
1459 case MSR_K7_EVNTSEL3:
1460 if (data != 0)
1461 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1462 "0x%x data 0x%llx\n", msr, data);
1463 break;
1464 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1465 * so we ignore writes to make it happy.
1466 */
1467 case MSR_P6_PERFCTR0:
1468 case MSR_P6_PERFCTR1:
1469 case MSR_K7_PERFCTR0:
1470 case MSR_K7_PERFCTR1:
1471 case MSR_K7_PERFCTR2:
1472 case MSR_K7_PERFCTR3:
1473 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1474 "0x%x data 0x%llx\n", msr, data);
1475 break;
84e0cefa
JS		 1476 case MSR_K7_CLK_CTL:
1477 /*
1478 * Ignore all writes to this no longer documented MSR.
1479 * Writes are only relevant for old K7 processors,
1480 * all pre-dating SVM, but a recommended workaround from
1481 * AMD for these chips. It is possible to speicify the
1482 * affected processor models on the command line, hence
1483 * the need to ignore the workaround.
1484 */
1485 break;
55cd8e5a
GN		 1486 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1487 if (kvm_hv_msr_partition_wide(msr)) {
1488 int r;
1489 mutex_lock(&vcpu->kvm->lock);
1490 r = set_msr_hyperv_pw(vcpu, msr, data);
1491 mutex_unlock(&vcpu->kvm->lock);
1492 return r;
1493 } else
1494 return set_msr_hyperv(vcpu, msr, data);
1495 break;
15c4a640 1496 default:
ffde22ac
ES		 1497 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1498 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1499 if (!ignore_msrs) {
1500 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1501 msr, data);
1502 return 1;
1503 } else {
1504 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1505 msr, data);
1506 break;
1507 }
15c4a640
CO		 1508 }
1509 return 0;
1510}
1511EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1512
1513
1514/*
1515 * Reads an msr value (of 'msr_index') into 'pdata'.
1516 * Returns 0 on success, non-0 otherwise.
1517 * Assumes vcpu_load() was already called.
1518 */
1519int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1520{
1521 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1522}
1523
9ba075a6
AK		 1524static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1525{
0bed3b56
SY		 1526 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1527
9ba075a6
AK		 1528 if (!msr_mtrr_valid(msr))
1529 return 1;
1530
0bed3b56
SY		 1531 if (msr == MSR_MTRRdefType)
1532 *pdata = vcpu->arch.mtrr_state.def_type +
1533 (vcpu->arch.mtrr_state.enabled << 10);
1534 else if (msr == MSR_MTRRfix64K_00000)
1535 *pdata = p[0];
1536 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1537 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1538 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1539 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1540 else if (msr == MSR_IA32_CR_PAT)
1541 *pdata = vcpu->arch.pat;
1542 else { /* Variable MTRRs */
1543 int idx, is_mtrr_mask;
1544 u64 *pt;
1545
1546 idx = (msr - 0x200) / 2;
1547 is_mtrr_mask = msr - 0x200 - 2 * idx;
1548 if (!is_mtrr_mask)
1549 pt =
1550 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1551 else
1552 pt =
1553 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1554 *pdata = *pt;
1555 }
1556
9ba075a6
AK		 1557 return 0;
1558}
1559
890ca9ae 1560static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1561{
1562 u64 data;
890ca9ae
HY		 1563 u64 mcg_cap = vcpu->arch.mcg_cap;
1564 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1565
1566 switch (msr) {
15c4a640
CO		 1567 case MSR_IA32_P5_MC_ADDR:
1568 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1569 data = 0;
1570 break;
15c4a640 1571 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1572 data = vcpu->arch.mcg_cap;
1573 break;
c7ac679c 1574 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1575 if (!(mcg_cap & MCG_CTL_P))
1576 return 1;
1577 data = vcpu->arch.mcg_ctl;
1578 break;
1579 case MSR_IA32_MCG_STATUS:
1580 data = vcpu->arch.mcg_status;
1581 break;
1582 default:
1583 if (msr >= MSR_IA32_MC0_CTL &&
1584 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1585 u32 offset = msr - MSR_IA32_MC0_CTL;
1586 data = vcpu->arch.mce_banks[offset];
1587 break;
1588 }
1589 return 1;
1590 }
1591 *pdata = data;
1592 return 0;
1593}
1594
55cd8e5a
GN		 1595static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1596{
1597 u64 data = 0;
1598 struct kvm *kvm = vcpu->kvm;
1599
1600 switch (msr) {
1601 case HV_X64_MSR_GUEST_OS_ID:
1602 data = kvm->arch.hv_guest_os_id;
1603 break;
1604 case HV_X64_MSR_HYPERCALL:
1605 data = kvm->arch.hv_hypercall;
1606 break;
1607 default:
1608 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1609 return 1;
1610 }
1611
1612 *pdata = data;
1613 return 0;
1614}
1615
1616static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1617{
1618 u64 data = 0;
1619
1620 switch (msr) {
1621 case HV_X64_MSR_VP_INDEX: {
1622 int r;
1623 struct kvm_vcpu *v;
1624 kvm_for_each_vcpu(r, v, vcpu->kvm)
1625 if (v == vcpu)
1626 data = r;
1627 break;
1628 }
10388a07
GN		 1629 case HV_X64_MSR_EOI:
1630 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1631 case HV_X64_MSR_ICR:
1632 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1633 case HV_X64_MSR_TPR:
1634 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1635 default:
1636 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1637 return 1;
1638 }
1639 *pdata = data;
1640 return 0;
1641}
1642
890ca9ae
HY		 1643int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1644{
1645 u64 data;
1646
1647 switch (msr) {
890ca9ae 1648 case MSR_IA32_PLATFORM_ID:
15c4a640 1649 case MSR_IA32_UCODE_REV:
15c4a640 1650 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1651 case MSR_IA32_DEBUGCTLMSR:
1652 case MSR_IA32_LASTBRANCHFROMIP:
1653 case MSR_IA32_LASTBRANCHTOIP:
1654 case MSR_IA32_LASTINTFROMIP:
1655 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1656 case MSR_K8_SYSCFG:
1657 case MSR_K7_HWCR:
61a6bd67 1658 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1659 case MSR_P6_PERFCTR0:
1660 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1661 case MSR_P6_EVNTSEL0:
1662 case MSR_P6_EVNTSEL1:
9e699624 1663 case MSR_K7_EVNTSEL0:
1f3ee616 1664 case MSR_K7_PERFCTR0:
1fdbd48c 1665 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1666 case MSR_AMD64_NB_CFG:
f7c6d140 1667 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1668 data = 0;
1669 break;
9ba075a6
AK		 1670 case MSR_MTRRcap:
1671 data = 0x500 | KVM_NR_VAR_MTRR;
1672 break;
1673 case 0x200 ... 0x2ff:
1674 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1675 case 0xcd: /* fsb frequency */
1676 data = 3;
1677 break;
7b914098
JS		 1678 /*
1679 * MSR_EBC_FREQUENCY_ID
1680 * Conservative value valid for even the basic CPU models.
1681 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1682 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1683 * and 266MHz for model 3, or 4. Set Core Clock
1684 * Frequency to System Bus Frequency Ratio to 1 (bits
1685 * 31:24) even though these are only valid for CPU
1686 * models > 2, however guests may end up dividing or
1687 * multiplying by zero otherwise.
1688 */
1689 case MSR_EBC_FREQUENCY_ID:
1690 data = 1 << 24;
1691 break;
15c4a640
CO		 1692 case MSR_IA32_APICBASE:
1693 data = kvm_get_apic_base(vcpu);
1694 break;
0105d1a5
GN		 1695 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1696 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1697 break;
15c4a640 1698 case MSR_IA32_MISC_ENABLE:
ad312c7c 1699 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1700 break;
847f0ad8
AG		 1701 case MSR_IA32_PERF_STATUS:
1702 /* TSC increment by tick */
1703 data = 1000ULL;
1704 /* CPU multiplier */
1705 data |= (((uint64_t)4ULL) << 40);
1706 break;
15c4a640 1707 case MSR_EFER:
f6801dff 1708 data = vcpu->arch.efer;
15c4a640 1709 break;
18068523 1710 case MSR_KVM_WALL_CLOCK:
11c6bffa 1711 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1712 data = vcpu->kvm->arch.wall_clock;
1713 break;
1714 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1715 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1716 data = vcpu->arch.time;
1717 break;
890ca9ae
HY		 1718 case MSR_IA32_P5_MC_ADDR:
1719 case MSR_IA32_P5_MC_TYPE:
1720 case MSR_IA32_MCG_CAP:
1721 case MSR_IA32_MCG_CTL:
1722 case MSR_IA32_MCG_STATUS:
1723 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1724 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1725 case MSR_K7_CLK_CTL:
1726 /*
1727 * Provide expected ramp-up count for K7. All other
1728 * are set to zero, indicating minimum divisors for
1729 * every field.
1730 *
1731 * This prevents guest kernels on AMD host with CPU
1732 * type 6, model 8 and higher from exploding due to
1733 * the rdmsr failing.
1734 */
1735 data = 0x20000000;
1736 break;
55cd8e5a
GN		 1737 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1738 if (kvm_hv_msr_partition_wide(msr)) {
1739 int r;
1740 mutex_lock(&vcpu->kvm->lock);
1741 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1742 mutex_unlock(&vcpu->kvm->lock);
1743 return r;
1744 } else
1745 return get_msr_hyperv(vcpu, msr, pdata);
1746 break;
15c4a640 1747 default:
ed85c068
AP		 1748 if (!ignore_msrs) {
1749 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1750 return 1;
1751 } else {
1752 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1753 data = 0;
1754 }
1755 break;
15c4a640
CO		 1756 }
1757 *pdata = data;
1758 return 0;
1759}
1760EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1761
313a3dc7
CO		 1762/*
1763 * Read or write a bunch of msrs. All parameters are kernel addresses.
1764 *
1765 * @return number of msrs set successfully.
1766 */
1767static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1768 struct kvm_msr_entry *entries,
1769 int (*do_msr)(struct kvm_vcpu *vcpu,
1770 unsigned index, u64 *data))
1771{
f656ce01 1772 int i, idx;
313a3dc7 1773
f656ce01 1774 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1775 for (i = 0; i < msrs->nmsrs; ++i)
1776 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1777 break;
f656ce01 1778 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1779
313a3dc7
CO		 1780 return i;
1781}
1782
1783/*
1784 * Read or write a bunch of msrs. Parameters are user addresses.
1785 *
1786 * @return number of msrs set successfully.
1787 */
1788static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1789 int (*do_msr)(struct kvm_vcpu *vcpu,
1790 unsigned index, u64 *data),
1791 int writeback)
1792{
1793 struct kvm_msrs msrs;
1794 struct kvm_msr_entry *entries;
1795 int r, n;
1796 unsigned size;
1797
1798 r = -EFAULT;
1799 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1800 goto out;
1801
1802 r = -E2BIG;
1803 if (msrs.nmsrs >= MAX_IO_MSRS)
1804 goto out;
1805
1806 r = -ENOMEM;
1807 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1808 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1809 if (!entries)
1810 goto out;
1811
1812 r = -EFAULT;
1813 if (copy_from_user(entries, user_msrs->entries, size))
1814 goto out_free;
1815
1816 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1817 if (r < 0)
1818 goto out_free;
1819
1820 r = -EFAULT;
1821 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1822 goto out_free;
1823
1824 r = n;
1825
1826out_free:
7a73c028 1827 kfree(entries);
313a3dc7
CO		 1828out:
1829 return r;
1830}
1831
018d00d2
ZX		 1832int kvm_dev_ioctl_check_extension(long ext)
1833{
1834 int r;
1835
1836 switch (ext) {
1837 case KVM_CAP_IRQCHIP:
1838 case KVM_CAP_HLT:
1839 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1840 case KVM_CAP_SET_TSS_ADDR:
07716717 1841 case KVM_CAP_EXT_CPUID:
c8076604 1842 case KVM_CAP_CLOCKSOURCE:
7837699f 1843 case KVM_CAP_PIT:
a28e4f5a 1844 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1845 case KVM_CAP_MP_STATE:
ed848624 1846 case KVM_CAP_SYNC_MMU:
52d939a0 1847 case KVM_CAP_REINJECT_CONTROL:
4925663a 1848 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1849 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1850 case KVM_CAP_IRQFD:
d34e6b17 1851 case KVM_CAP_IOEVENTFD:
c5ff41ce 1852 case KVM_CAP_PIT2:
e9f42757 1853 case KVM_CAP_PIT_STATE2:
b927a3ce 1854 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1855 case KVM_CAP_XEN_HVM:
afbcf7ab 1856 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1857 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1858 case KVM_CAP_HYPERV:
10388a07 1859 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1860 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1861 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1862 case KVM_CAP_DEBUGREGS:
d2be1651 1863 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1864 case KVM_CAP_XSAVE:
018d00d2
ZX		 1865 r = 1;
1866 break;
542472b5
LV		 1867 case KVM_CAP_COALESCED_MMIO:
1868 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1869 break;
774ead3a
AK		 1870 case KVM_CAP_VAPIC:
1871 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1872 break;
f725230a
AK		 1873 case KVM_CAP_NR_VCPUS:
1874 r = KVM_MAX_VCPUS;
1875 break;
a988b910
AK		 1876 case KVM_CAP_NR_MEMSLOTS:
1877 r = KVM_MEMORY_SLOTS;
1878 break;
a68a6a72
MT		 1879 case KVM_CAP_PV_MMU: /* obsolete */
1880 r = 0;
2f333bcb 1881 break;
62c476c7 1882 case KVM_CAP_IOMMU:
19de40a8 1883 r = iommu_found();
62c476c7 1884 break;
890ca9ae
HY		 1885 case KVM_CAP_MCE:
1886 r = KVM_MAX_MCE_BANKS;
1887 break;
2d5b5a66
SY		 1888 case KVM_CAP_XCRS:
1889 r = cpu_has_xsave;
1890 break;
018d00d2
ZX		 1891 default:
1892 r = 0;
1893 break;
1894 }
1895 return r;
1896
1897}
1898
043405e1
CO		 1899long kvm_arch_dev_ioctl(struct file *filp,
1900 unsigned int ioctl, unsigned long arg)
1901{
1902 void __user *argp = (void __user *)arg;
1903 long r;
1904
1905 switch (ioctl) {
1906 case KVM_GET_MSR_INDEX_LIST: {
1907 struct kvm_msr_list __user *user_msr_list = argp;
1908 struct kvm_msr_list msr_list;
1909 unsigned n;
1910
1911 r = -EFAULT;
1912 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1913 goto out;
1914 n = msr_list.nmsrs;
1915 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1916 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1917 goto out;
1918 r = -E2BIG;
e125e7b6 1919 if (n < msr_list.nmsrs)
043405e1
CO		 1920 goto out;
1921 r = -EFAULT;
1922 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1923 num_msrs_to_save * sizeof(u32)))
1924 goto out;
e125e7b6 1925 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1926 &emulated_msrs,
1927 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1928 goto out;
1929 r = 0;
1930 break;
1931 }
674eea0f
AK		 1932 case KVM_GET_SUPPORTED_CPUID: {
1933 struct kvm_cpuid2 __user *cpuid_arg = argp;
1934 struct kvm_cpuid2 cpuid;
1935
1936 r = -EFAULT;
1937 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1938 goto out;
1939 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1940 cpuid_arg->entries);
674eea0f
AK		 1941 if (r)
1942 goto out;
1943
1944 r = -EFAULT;
1945 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1946 goto out;
1947 r = 0;
1948 break;
1949 }
890ca9ae
HY		 1950 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1951 u64 mce_cap;
1952
1953 mce_cap = KVM_MCE_CAP_SUPPORTED;
1954 r = -EFAULT;
1955 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1956 goto out;
1957 r = 0;
1958 break;
1959 }
043405e1
CO		 1960 default:
1961 r = -EINVAL;
1962 }
1963out:
1964 return r;
1965}
1966
f5f48ee1
SY		 1967static void wbinvd_ipi(void *garbage)
1968{
1969 wbinvd();
1970}
1971
1972static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
1973{
1974 return vcpu->kvm->arch.iommu_domain &&
1975 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
1976}
1977
313a3dc7
CO		 1978void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1979{
f5f48ee1
SY		 1980 /* Address WBINVD may be executed by guest */
1981 if (need_emulate_wbinvd(vcpu)) {
1982 if (kvm_x86_ops->has_wbinvd_exit())
1983 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
1984 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
1985 smp_call_function_single(vcpu->cpu,
1986 wbinvd_ipi, NULL, 1);
1987 }
1988
313a3dc7 1989 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 1990 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 1991 /* Make sure TSC doesn't go backwards */
1992 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
1993 native_read_tsc() - vcpu->arch.last_host_tsc;
1994 if (tsc_delta < 0)
1995 mark_tsc_unstable("KVM discovered backwards TSC");
1996 if (check_tsc_unstable())
1997 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
1998 kvm_migrate_timers(vcpu);
1999 vcpu->cpu = cpu;
2000 }
313a3dc7
CO		 2001}
2002
2003void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2004{
02daab21 2005 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2006 kvm_put_guest_fpu(vcpu);
e48672fa 2007 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2008}
2009
07716717 2010static int is_efer_nx(void)
313a3dc7 2011{
e286e86e 2012 unsigned long long efer = 0;
313a3dc7 2013
e286e86e 2014 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2015 return efer & EFER_NX;
2016}
2017
2018static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2019{
2020 int i;
2021 struct kvm_cpuid_entry2 *e, *entry;
2022
313a3dc7 2023 entry = NULL;
ad312c7c
ZX		 2024 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2025 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2026 if (e->function == 0x80000001) {
2027 entry = e;
2028 break;
2029 }
2030 }
07716717 2031 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2032 entry->edx &= ~(1 << 20);
2033 printk(KERN_INFO "kvm: guest NX capability removed\n");
2034 }
2035}
2036
07716717 2037/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2038static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2039 struct kvm_cpuid *cpuid,
2040 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2041{
2042 int r, i;
2043 struct kvm_cpuid_entry *cpuid_entries;
2044
2045 r = -E2BIG;
2046 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2047 goto out;
2048 r = -ENOMEM;
2049 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2050 if (!cpuid_entries)
2051 goto out;
2052 r = -EFAULT;
2053 if (copy_from_user(cpuid_entries, entries,
2054 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2055 goto out_free;
2056 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2057 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2058 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2059 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2060 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2061 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2062 vcpu->arch.cpuid_entries[i].index = 0;
2063 vcpu->arch.cpuid_entries[i].flags = 0;
2064 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2065 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2066 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2067 }
2068 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2069 cpuid_fix_nx_cap(vcpu);
2070 r = 0;
fc61b800 2071 kvm_apic_set_version(vcpu);
0e851880 2072 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2073 update_cpuid(vcpu);
07716717
DK		 2074
2075out_free:
2076 vfree(cpuid_entries);
2077out:
2078 return r;
2079}
2080
2081static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2082 struct kvm_cpuid2 *cpuid,
2083 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2084{
2085 int r;
2086
2087 r = -E2BIG;
2088 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2089 goto out;
2090 r = -EFAULT;
ad312c7c 2091 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2092 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2093 goto out;
ad312c7c 2094 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2095 kvm_apic_set_version(vcpu);
0e851880 2096 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2097 update_cpuid(vcpu);
313a3dc7
CO		 2098 return 0;
2099
2100out:
2101 return r;
2102}
2103
07716717 2104static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2105 struct kvm_cpuid2 *cpuid,
2106 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2107{
2108 int r;
2109
2110 r = -E2BIG;
ad312c7c 2111 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2112 goto out;
2113 r = -EFAULT;
ad312c7c 2114 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2115 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2116 goto out;
2117 return 0;
2118
2119out:
ad312c7c 2120 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2121 return r;
2122}
2123
07716717 2124static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2125 u32 index)
07716717
DK		 2126{
2127 entry->function = function;
2128 entry->index = index;
2129 cpuid_count(entry->function, entry->index,
19355475 2130 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2131 entry->flags = 0;
2132}
2133
7faa4ee1
AK		 2134#define F(x) bit(X86_FEATURE_##x)
2135
07716717
DK		 2136static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2137 u32 index, int *nent, int maxnent)
2138{
7faa4ee1 2139 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2140#ifdef CONFIG_X86_64
17cc3935
SY		 2141 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2142 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2143 unsigned f_lm = F(LM);
2144#else
17cc3935 2145 unsigned f_gbpages = 0;
7faa4ee1 2146 unsigned f_lm = 0;
07716717 2147#endif
4e47c7a6 2148 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2149
2150 /* cpuid 1.edx */
2151 const u32 kvm_supported_word0_x86_features =
2152 F(FPU) | F(VME) | F(DE) | F(PSE) |
2153 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2154 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2155 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2156 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2157 0 /* Reserved, DS, ACPI */ | F(MMX) |
2158 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2159 0 /* HTT, TM, Reserved, PBE */;
2160 /* cpuid 0x80000001.edx */
2161 const u32 kvm_supported_word1_x86_features =
2162 F(FPU) | F(VME) | F(DE) | F(PSE) |
2163 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2164 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2165 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2166 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2167 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2168 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2169 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2170 /* cpuid 1.ecx */
2171 const u32 kvm_supported_word4_x86_features =
6c3f6041 2172 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2173 0 /* DS-CPL, VMX, SMX, EST */ |
2174 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2175 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2176 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2177 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2178 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2179 /* cpuid 0x80000001.ecx */
07716717 2180 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 2181 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
2182 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2183 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2184 0 /* SKINIT */ | 0 /* WDT */;
07716717 2185
19355475 2186 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2187 get_cpu();
2188 do_cpuid_1_ent(entry, function, index);
2189 ++*nent;
2190
2191 switch (function) {
2192 case 0:
2acf923e 2193 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2194 break;
2195 case 1:
2196 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2197 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2198 /* we support x2apic emulation even if host does not support
2199 * it since we emulate x2apic in software */
2200 entry->ecx |= F(X2APIC);
07716717
DK		 2201 break;
2202 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2203 * may return different values. This forces us to get_cpu() before
2204 * issuing the first command, and also to emulate this annoying behavior
2205 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2206 case 2: {
2207 int t, times = entry->eax & 0xff;
2208
2209 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2210 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2211 for (t = 1; t < times && *nent < maxnent; ++t) {
2212 do_cpuid_1_ent(&entry[t], function, 0);
2213 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2214 ++*nent;
2215 }
2216 break;
2217 }
2218 /* function 4 and 0xb have additional index. */
2219 case 4: {
14af3f3c 2220 int i, cache_type;
07716717
DK		 2221
2222 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2223 /* read more entries until cache_type is zero */
14af3f3c
HH		 2224 for (i = 1; *nent < maxnent; ++i) {
2225 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2226 if (!cache_type)
2227 break;
14af3f3c
HH		 2228 do_cpuid_1_ent(&entry[i], function, i);
2229 entry[i].flags |=
07716717
DK		 2230 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2231 ++*nent;
2232 }
2233 break;
2234 }
2235 case 0xb: {
14af3f3c 2236 int i, level_type;
07716717
DK		 2237
2238 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2239 /* read more entries until level_type is zero */
14af3f3c 2240 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2241 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2242 if (!level_type)
2243 break;
14af3f3c
HH		 2244 do_cpuid_1_ent(&entry[i], function, i);
2245 entry[i].flags |=
07716717
DK		 2246 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2247 ++*nent;
2248 }
2249 break;
2250 }
2acf923e
DC		 2251 case 0xd: {
2252 int i;
2253
2254 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2255 for (i = 1; *nent < maxnent; ++i) {
2256 if (entry[i - 1].eax == 0 && i != 2)
2257 break;
2258 do_cpuid_1_ent(&entry[i], function, i);
2259 entry[i].flags |=
2260 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2261 ++*nent;
2262 }
2263 break;
2264 }
84478c82
GC		 2265 case KVM_CPUID_SIGNATURE: {
2266 char signature[12] = "KVMKVMKVM\0\0";
2267 u32 *sigptr = (u32 *)signature;
2268 entry->eax = 0;
2269 entry->ebx = sigptr[0];
2270 entry->ecx = sigptr[1];
2271 entry->edx = sigptr[2];
2272 break;
2273 }
2274 case KVM_CPUID_FEATURES:
2275 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2276 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2277 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2278 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2279 entry->ebx = 0;
2280 entry->ecx = 0;
2281 entry->edx = 0;
2282 break;
07716717
DK		 2283 case 0x80000000:
2284 entry->eax = min(entry->eax, 0x8000001a);
2285 break;
2286 case 0x80000001:
2287 entry->edx &= kvm_supported_word1_x86_features;
2288 entry->ecx &= kvm_supported_word6_x86_features;
2289 break;
2290 }
d4330ef2
JR		 2291
2292 kvm_x86_ops->set_supported_cpuid(function, entry);
2293
07716717
DK		 2294 put_cpu();
2295}
2296
7faa4ee1
AK		 2297#undef F
2298
674eea0f 2299static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2300 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2301{
2302 struct kvm_cpuid_entry2 *cpuid_entries;
2303 int limit, nent = 0, r = -E2BIG;
2304 u32 func;
2305
2306 if (cpuid->nent < 1)
2307 goto out;
6a544355
AK		 2308 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2309 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2310 r = -ENOMEM;
2311 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2312 if (!cpuid_entries)
2313 goto out;
2314
2315 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2316 limit = cpuid_entries[0].eax;
2317 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2318 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2319 &nent, cpuid->nent);
07716717
DK		 2320 r = -E2BIG;
2321 if (nent >= cpuid->nent)
2322 goto out_free;
2323
2324 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2325 limit = cpuid_entries[nent - 1].eax;
2326 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2327 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2328 &nent, cpuid->nent);
84478c82
GC		 2329
2330
2331
2332 r = -E2BIG;
2333 if (nent >= cpuid->nent)
2334 goto out_free;
2335
2336 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2337 cpuid->nent);
2338
2339 r = -E2BIG;
2340 if (nent >= cpuid->nent)
2341 goto out_free;
2342
2343 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2344 cpuid->nent);
2345
cb007648
MM		 2346 r = -E2BIG;
2347 if (nent >= cpuid->nent)
2348 goto out_free;
2349
07716717
DK		 2350 r = -EFAULT;
2351 if (copy_to_user(entries, cpuid_entries,
19355475 2352 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2353 goto out_free;
2354 cpuid->nent = nent;
2355 r = 0;
2356
2357out_free:
2358 vfree(cpuid_entries);
2359out:
2360 return r;
2361}
2362
313a3dc7
CO		 2363static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2364 struct kvm_lapic_state *s)
2365{
ad312c7c 2366 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2367
2368 return 0;
2369}
2370
2371static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2372 struct kvm_lapic_state *s)
2373{
ad312c7c 2374 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2375 kvm_apic_post_state_restore(vcpu);
cb142eb7 2376 update_cr8_intercept(vcpu);
313a3dc7
CO		 2377
2378 return 0;
2379}
2380
f77bc6a4
ZX		 2381static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2382 struct kvm_interrupt *irq)
2383{
2384 if (irq->irq < 0 || irq->irq >= 256)
2385 return -EINVAL;
2386 if (irqchip_in_kernel(vcpu->kvm))
2387 return -ENXIO;
f77bc6a4 2388
66fd3f7f 2389 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2390
f77bc6a4
ZX		 2391 return 0;
2392}
2393
c4abb7c9
JK		 2394static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2395{
c4abb7c9 2396 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2397
2398 return 0;
2399}
2400
b209749f
AK		 2401static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2402 struct kvm_tpr_access_ctl *tac)
2403{
2404 if (tac->flags)
2405 return -EINVAL;
2406 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2407 return 0;
2408}
2409
890ca9ae
HY		 2410static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2411 u64 mcg_cap)
2412{
2413 int r;
2414 unsigned bank_num = mcg_cap & 0xff, bank;
2415
2416 r = -EINVAL;
a9e38c3e 2417 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2418 goto out;
2419 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2420 goto out;
2421 r = 0;
2422 vcpu->arch.mcg_cap = mcg_cap;
2423 /* Init IA32_MCG_CTL to all 1s */
2424 if (mcg_cap & MCG_CTL_P)
2425 vcpu->arch.mcg_ctl = ~(u64)0;
2426 /* Init IA32_MCi_CTL to all 1s */
2427 for (bank = 0; bank < bank_num; bank++)
2428 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2429out:
2430 return r;
2431}
2432
2433static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2434 struct kvm_x86_mce *mce)
2435{
2436 u64 mcg_cap = vcpu->arch.mcg_cap;
2437 unsigned bank_num = mcg_cap & 0xff;
2438 u64 *banks = vcpu->arch.mce_banks;
2439
2440 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2441 return -EINVAL;
2442 /*
2443 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2444 * reporting is disabled
2445 */
2446 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2447 vcpu->arch.mcg_ctl != ~(u64)0)
2448 return 0;
2449 banks += 4 * mce->bank;
2450 /*
2451 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2452 * reporting is disabled for the bank
2453 */
2454 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2455 return 0;
2456 if (mce->status & MCI_STATUS_UC) {
2457 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2458 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2459 printk(KERN_DEBUG "kvm: set_mce: "
2460 "injects mce exception while "
2461 "previous one is in progress!\n");
a8eeb04a 2462 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2463 return 0;
2464 }
2465 if (banks[1] & MCI_STATUS_VAL)
2466 mce->status |= MCI_STATUS_OVER;
2467 banks[2] = mce->addr;
2468 banks[3] = mce->misc;
2469 vcpu->arch.mcg_status = mce->mcg_status;
2470 banks[1] = mce->status;
2471 kvm_queue_exception(vcpu, MC_VECTOR);
2472 } else if (!(banks[1] & MCI_STATUS_VAL)
2473 || !(banks[1] & MCI_STATUS_UC)) {
2474 if (banks[1] & MCI_STATUS_VAL)
2475 mce->status |= MCI_STATUS_OVER;
2476 banks[2] = mce->addr;
2477 banks[3] = mce->misc;
2478 banks[1] = mce->status;
2479 } else
2480 banks[1] |= MCI_STATUS_OVER;
2481 return 0;
2482}
2483
3cfc3092
JK		 2484static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2485 struct kvm_vcpu_events *events)
2486{
03b82a30
JK		 2487 events->exception.injected =
2488 vcpu->arch.exception.pending &&
2489 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2490 events->exception.nr = vcpu->arch.exception.nr;
2491 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2492 events->exception.error_code = vcpu->arch.exception.error_code;
2493
03b82a30
JK		 2494 events->interrupt.injected =
2495 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2496 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2497 events->interrupt.soft = 0;
48005f64
JK		 2498 events->interrupt.shadow =
2499 kvm_x86_ops->get_interrupt_shadow(vcpu,
2500 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2501
2502 events->nmi.injected = vcpu->arch.nmi_injected;
2503 events->nmi.pending = vcpu->arch.nmi_pending;
2504 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2505
2506 events->sipi_vector = vcpu->arch.sipi_vector;
2507
dab4b911 2508 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2509 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2510 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2511}
2512
2513static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2514 struct kvm_vcpu_events *events)
2515{
dab4b911 2516 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2517 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2518 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2519 return -EINVAL;
2520
3cfc3092
JK		 2521 vcpu->arch.exception.pending = events->exception.injected;
2522 vcpu->arch.exception.nr = events->exception.nr;
2523 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2524 vcpu->arch.exception.error_code = events->exception.error_code;
2525
2526 vcpu->arch.interrupt.pending = events->interrupt.injected;
2527 vcpu->arch.interrupt.nr = events->interrupt.nr;
2528 vcpu->arch.interrupt.soft = events->interrupt.soft;
2529 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2530 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2531 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2532 kvm_x86_ops->set_interrupt_shadow(vcpu,
2533 events->interrupt.shadow);
3cfc3092
JK		 2534
2535 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2536 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2537 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2538 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2539
dab4b911
JK		 2540 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2541 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2542
3cfc3092
JK		 2543 return 0;
2544}
2545
a1efbe77
JK		 2546static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2547 struct kvm_debugregs *dbgregs)
2548{
a1efbe77
JK		 2549 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2550 dbgregs->dr6 = vcpu->arch.dr6;
2551 dbgregs->dr7 = vcpu->arch.dr7;
2552 dbgregs->flags = 0;
a1efbe77
JK		 2553}
2554
2555static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2556 struct kvm_debugregs *dbgregs)
2557{
2558 if (dbgregs->flags)
2559 return -EINVAL;
2560
a1efbe77
JK		 2561 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2562 vcpu->arch.dr6 = dbgregs->dr6;
2563 vcpu->arch.dr7 = dbgregs->dr7;
2564
a1efbe77
JK		 2565 return 0;
2566}
2567
2d5b5a66
SY		 2568static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2569 struct kvm_xsave *guest_xsave)
2570{
2571 if (cpu_has_xsave)
2572 memcpy(guest_xsave->region,
2573 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2574 xstate_size);
2d5b5a66
SY		 2575 else {
2576 memcpy(guest_xsave->region,
2577 &vcpu->arch.guest_fpu.state->fxsave,
2578 sizeof(struct i387_fxsave_struct));
2579 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2580 XSTATE_FPSSE;
2581 }
2582}
2583
2584static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2585 struct kvm_xsave *guest_xsave)
2586{
2587 u64 xstate_bv =
2588 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2589
2590 if (cpu_has_xsave)
2591 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2592 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2593 else {
2594 if (xstate_bv & ~XSTATE_FPSSE)
2595 return -EINVAL;
2596 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2597 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2598 }
2599 return 0;
2600}
2601
2602static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2603 struct kvm_xcrs *guest_xcrs)
2604{
2605 if (!cpu_has_xsave) {
2606 guest_xcrs->nr_xcrs = 0;
2607 return;
2608 }
2609
2610 guest_xcrs->nr_xcrs = 1;
2611 guest_xcrs->flags = 0;
2612 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2613 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2614}
2615
2616static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2617 struct kvm_xcrs *guest_xcrs)
2618{
2619 int i, r = 0;
2620
2621 if (!cpu_has_xsave)
2622 return -EINVAL;
2623
2624 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2625 return -EINVAL;
2626
2627 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2628 /* Only support XCR0 currently */
2629 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2630 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2631 guest_xcrs->xcrs[0].value);
2632 break;
2633 }
2634 if (r)
2635 r = -EINVAL;
2636 return r;
2637}
2638
313a3dc7
CO		 2639long kvm_arch_vcpu_ioctl(struct file *filp,
2640 unsigned int ioctl, unsigned long arg)
2641{
2642 struct kvm_vcpu *vcpu = filp->private_data;
2643 void __user *argp = (void __user *)arg;
2644 int r;
d1ac91d8
AK		 2645 union {
2646 struct kvm_lapic_state *lapic;
2647 struct kvm_xsave *xsave;
2648 struct kvm_xcrs *xcrs;
2649 void *buffer;
2650 } u;
2651
2652 u.buffer = NULL;
313a3dc7
CO		 2653 switch (ioctl) {
2654 case KVM_GET_LAPIC: {
2204ae3c
MT		 2655 r = -EINVAL;
2656 if (!vcpu->arch.apic)
2657 goto out;
d1ac91d8 2658 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2659
b772ff36 2660 r = -ENOMEM;
d1ac91d8 2661 if (!u.lapic)
b772ff36 2662 goto out;
d1ac91d8 2663 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2664 if (r)
2665 goto out;
2666 r = -EFAULT;
d1ac91d8 2667 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2668 goto out;
2669 r = 0;
2670 break;
2671 }
2672 case KVM_SET_LAPIC: {
2204ae3c
MT		 2673 r = -EINVAL;
2674 if (!vcpu->arch.apic)
2675 goto out;
d1ac91d8 2676 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2677 r = -ENOMEM;
d1ac91d8 2678 if (!u.lapic)
b772ff36 2679 goto out;
313a3dc7 2680 r = -EFAULT;
d1ac91d8 2681 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2682 goto out;
d1ac91d8 2683 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2684 if (r)
2685 goto out;
2686 r = 0;
2687 break;
2688 }
f77bc6a4
ZX		 2689 case KVM_INTERRUPT: {
2690 struct kvm_interrupt irq;
2691
2692 r = -EFAULT;
2693 if (copy_from_user(&irq, argp, sizeof irq))
2694 goto out;
2695 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2696 if (r)
2697 goto out;
2698 r = 0;
2699 break;
2700 }
c4abb7c9
JK		 2701 case KVM_NMI: {
2702 r = kvm_vcpu_ioctl_nmi(vcpu);
2703 if (r)
2704 goto out;
2705 r = 0;
2706 break;
2707 }
313a3dc7
CO		 2708 case KVM_SET_CPUID: {
2709 struct kvm_cpuid __user *cpuid_arg = argp;
2710 struct kvm_cpuid cpuid;
2711
2712 r = -EFAULT;
2713 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2714 goto out;
2715 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2716 if (r)
2717 goto out;
2718 break;
2719 }
07716717
DK		 2720 case KVM_SET_CPUID2: {
2721 struct kvm_cpuid2 __user *cpuid_arg = argp;
2722 struct kvm_cpuid2 cpuid;
2723
2724 r = -EFAULT;
2725 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2726 goto out;
2727 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2728 cpuid_arg->entries);
07716717
DK		 2729 if (r)
2730 goto out;
2731 break;
2732 }
2733 case KVM_GET_CPUID2: {
2734 struct kvm_cpuid2 __user *cpuid_arg = argp;
2735 struct kvm_cpuid2 cpuid;
2736
2737 r = -EFAULT;
2738 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2739 goto out;
2740 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2741 cpuid_arg->entries);
07716717
DK		 2742 if (r)
2743 goto out;
2744 r = -EFAULT;
2745 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2746 goto out;
2747 r = 0;
2748 break;
2749 }
313a3dc7
CO		 2750 case KVM_GET_MSRS:
2751 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2752 break;
2753 case KVM_SET_MSRS:
2754 r = msr_io(vcpu, argp, do_set_msr, 0);
2755 break;
b209749f
AK		 2756 case KVM_TPR_ACCESS_REPORTING: {
2757 struct kvm_tpr_access_ctl tac;
2758
2759 r = -EFAULT;
2760 if (copy_from_user(&tac, argp, sizeof tac))
2761 goto out;
2762 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2763 if (r)
2764 goto out;
2765 r = -EFAULT;
2766 if (copy_to_user(argp, &tac, sizeof tac))
2767 goto out;
2768 r = 0;
2769 break;
2770 };
b93463aa
AK		 2771 case KVM_SET_VAPIC_ADDR: {
2772 struct kvm_vapic_addr va;
2773
2774 r = -EINVAL;
2775 if (!irqchip_in_kernel(vcpu->kvm))
2776 goto out;
2777 r = -EFAULT;
2778 if (copy_from_user(&va, argp, sizeof va))
2779 goto out;
2780 r = 0;
2781 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2782 break;
2783 }
890ca9ae
HY		 2784 case KVM_X86_SETUP_MCE: {
2785 u64 mcg_cap;
2786
2787 r = -EFAULT;
2788 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2789 goto out;
2790 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2791 break;
2792 }
2793 case KVM_X86_SET_MCE: {
2794 struct kvm_x86_mce mce;
2795
2796 r = -EFAULT;
2797 if (copy_from_user(&mce, argp, sizeof mce))
2798 goto out;
2799 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2800 break;
2801 }
3cfc3092
JK		 2802 case KVM_GET_VCPU_EVENTS: {
2803 struct kvm_vcpu_events events;
2804
2805 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2806
2807 r = -EFAULT;
2808 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2809 break;
2810 r = 0;
2811 break;
2812 }
2813 case KVM_SET_VCPU_EVENTS: {
2814 struct kvm_vcpu_events events;
2815
2816 r = -EFAULT;
2817 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2818 break;
2819
2820 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2821 break;
2822 }
a1efbe77
JK		 2823 case KVM_GET_DEBUGREGS: {
2824 struct kvm_debugregs dbgregs;
2825
2826 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2827
2828 r = -EFAULT;
2829 if (copy_to_user(argp, &dbgregs,
2830 sizeof(struct kvm_debugregs)))
2831 break;
2832 r = 0;
2833 break;
2834 }
2835 case KVM_SET_DEBUGREGS: {
2836 struct kvm_debugregs dbgregs;
2837
2838 r = -EFAULT;
2839 if (copy_from_user(&dbgregs, argp,
2840 sizeof(struct kvm_debugregs)))
2841 break;
2842
2843 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2844 break;
2845 }
2d5b5a66 2846 case KVM_GET_XSAVE: {
d1ac91d8 2847 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2848 r = -ENOMEM;
d1ac91d8 2849 if (!u.xsave)
2d5b5a66
SY		 2850 break;
2851
d1ac91d8 2852 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2853
2854 r = -EFAULT;
d1ac91d8 2855 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2856 break;
2857 r = 0;
2858 break;
2859 }
2860 case KVM_SET_XSAVE: {
d1ac91d8 2861 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2862 r = -ENOMEM;
d1ac91d8 2863 if (!u.xsave)
2d5b5a66
SY		 2864 break;
2865
2866 r = -EFAULT;
d1ac91d8 2867 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2868 break;
2869
d1ac91d8 2870 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2871 break;
2872 }
2873 case KVM_GET_XCRS: {
d1ac91d8 2874 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2875 r = -ENOMEM;
d1ac91d8 2876 if (!u.xcrs)
2d5b5a66
SY		 2877 break;
2878
d1ac91d8 2879 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2880
2881 r = -EFAULT;
d1ac91d8 2882 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2883 sizeof(struct kvm_xcrs)))
2884 break;
2885 r = 0;
2886 break;
2887 }
2888 case KVM_SET_XCRS: {
d1ac91d8 2889 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2890 r = -ENOMEM;
d1ac91d8 2891 if (!u.xcrs)
2d5b5a66
SY		 2892 break;
2893
2894 r = -EFAULT;
d1ac91d8 2895 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2896 sizeof(struct kvm_xcrs)))
2897 break;
2898
d1ac91d8 2899 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2900 break;
2901 }
313a3dc7
CO		 2902 default:
2903 r = -EINVAL;
2904 }
2905out:
d1ac91d8 2906 kfree(u.buffer);
313a3dc7
CO		 2907 return r;
2908}
2909
1fe779f8
CO		 2910static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2911{
2912 int ret;
2913
2914 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2915 return -1;
2916 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2917 return ret;
2918}
2919
b927a3ce
SY		 2920static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2921 u64 ident_addr)
2922{
2923 kvm->arch.ept_identity_map_addr = ident_addr;
2924 return 0;
2925}
2926
1fe779f8
CO		 2927static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2928 u32 kvm_nr_mmu_pages)
2929{
2930 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2931 return -EINVAL;
2932
79fac95e 2933 mutex_lock(&kvm->slots_lock);
7c8a83b7 2934 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2935
2936 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2937 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2938
7c8a83b7 2939 spin_unlock(&kvm->mmu_lock);
79fac95e 2940 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2941 return 0;
2942}
2943
2944static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2945{
39de71ec 2946 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2947}
2948
1fe779f8
CO		 2949static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2950{
2951 int r;
2952
2953 r = 0;
2954 switch (chip->chip_id) {
2955 case KVM_IRQCHIP_PIC_MASTER:
2956 memcpy(&chip->chip.pic,
2957 &pic_irqchip(kvm)->pics[0],
2958 sizeof(struct kvm_pic_state));
2959 break;
2960 case KVM_IRQCHIP_PIC_SLAVE:
2961 memcpy(&chip->chip.pic,
2962 &pic_irqchip(kvm)->pics[1],
2963 sizeof(struct kvm_pic_state));
2964 break;
2965 case KVM_IRQCHIP_IOAPIC:
eba0226b 2966 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2967 break;
2968 default:
2969 r = -EINVAL;
2970 break;
2971 }
2972 return r;
2973}
2974
2975static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2976{
2977 int r;
2978
2979 r = 0;
2980 switch (chip->chip_id) {
2981 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2982 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2983 memcpy(&pic_irqchip(kvm)->pics[0],
2984 &chip->chip.pic,
2985 sizeof(struct kvm_pic_state));
fa8273e9 2986 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2987 break;
2988 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2989 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2990 memcpy(&pic_irqchip(kvm)->pics[1],
2991 &chip->chip.pic,
2992 sizeof(struct kvm_pic_state));
fa8273e9 2993 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2994 break;
2995 case KVM_IRQCHIP_IOAPIC:
eba0226b 2996 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2997 break;
2998 default:
2999 r = -EINVAL;
3000 break;
3001 }
3002 kvm_pic_update_irq(pic_irqchip(kvm));
3003 return r;
3004}
3005
e0f63cb9
SY		 3006static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3007{
3008 int r = 0;
3009
894a9c55 3010 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3011 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3012 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3013 return r;
3014}
3015
3016static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3017{
3018 int r = 0;
3019
894a9c55 3020 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3021 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3022 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3023 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3024 return r;
3025}
3026
3027static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3028{
3029 int r = 0;
3030
3031 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3032 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3033 sizeof(ps->channels));
3034 ps->flags = kvm->arch.vpit->pit_state.flags;
3035 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3036 return r;
3037}
3038
3039static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3040{
3041 int r = 0, start = 0;
3042 u32 prev_legacy, cur_legacy;
3043 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3044 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3045 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3046 if (!prev_legacy && cur_legacy)
3047 start = 1;
3048 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3049 sizeof(kvm->arch.vpit->pit_state.channels));
3050 kvm->arch.vpit->pit_state.flags = ps->flags;
3051 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3052 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3053 return r;
3054}
3055
52d939a0
MT		 3056static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3057 struct kvm_reinject_control *control)
3058{
3059 if (!kvm->arch.vpit)
3060 return -ENXIO;
894a9c55 3061 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3062 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3063 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3064 return 0;
3065}
3066
5bb064dc
ZX		 3067/*
3068 * Get (and clear) the dirty memory log for a memory slot.
3069 */
3070int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3071 struct kvm_dirty_log *log)
3072{
87bf6e7d 3073 int r, i;
5bb064dc 3074 struct kvm_memory_slot *memslot;
87bf6e7d 3075 unsigned long n;
b050b015 3076 unsigned long is_dirty = 0;
5bb064dc 3077
79fac95e 3078 mutex_lock(&kvm->slots_lock);
5bb064dc 3079
b050b015
MT		 3080 r = -EINVAL;
3081 if (log->slot >= KVM_MEMORY_SLOTS)
3082 goto out;
3083
3084 memslot = &kvm->memslots->memslots[log->slot];
3085 r = -ENOENT;
3086 if (!memslot->dirty_bitmap)
3087 goto out;
3088
87bf6e7d 3089 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3090
b050b015
MT		 3091 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3092 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3093
3094 /* If nothing is dirty, don't bother messing with page tables. */
3095 if (is_dirty) {
b050b015 3096 struct kvm_memslots *slots, *old_slots;
914ebccd 3097 unsigned long *dirty_bitmap;
b050b015 3098
7c8a83b7 3099 spin_lock(&kvm->mmu_lock);
5bb064dc 3100 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3101 spin_unlock(&kvm->mmu_lock);
b050b015 3102
914ebccd
TY		 3103 r = -ENOMEM;
3104 dirty_bitmap = vmalloc(n);
3105 if (!dirty_bitmap)
3106 goto out;
3107 memset(dirty_bitmap, 0, n);
b050b015 3108
914ebccd
TY		 3109 r = -ENOMEM;
3110 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3111 if (!slots) {
3112 vfree(dirty_bitmap);
3113 goto out;
3114 }
b050b015
MT		 3115 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3116 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3117
3118 old_slots = kvm->memslots;
3119 rcu_assign_pointer(kvm->memslots, slots);
3120 synchronize_srcu_expedited(&kvm->srcu);
3121 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3122 kfree(old_slots);
914ebccd
TY		 3123
3124 r = -EFAULT;
3125 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3126 vfree(dirty_bitmap);
3127 goto out;
3128 }
3129 vfree(dirty_bitmap);
3130 } else {
3131 r = -EFAULT;
3132 if (clear_user(log->dirty_bitmap, n))
3133 goto out;
5bb064dc 3134 }
b050b015 3135
5bb064dc
ZX		 3136 r = 0;
3137out:
79fac95e 3138 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3139 return r;
3140}
3141
1fe779f8
CO		 3142long kvm_arch_vm_ioctl(struct file *filp,
3143 unsigned int ioctl, unsigned long arg)
3144{
3145 struct kvm *kvm = filp->private_data;
3146 void __user *argp = (void __user *)arg;
367e1319 3147 int r = -ENOTTY;
f0d66275
DH		 3148 /*
3149 * This union makes it completely explicit to gcc-3.x
3150 * that these two variables' stack usage should be
3151 * combined, not added together.
3152 */
3153 union {
3154 struct kvm_pit_state ps;
e9f42757 3155 struct kvm_pit_state2 ps2;
c5ff41ce 3156 struct kvm_pit_config pit_config;
f0d66275 3157 } u;
1fe779f8
CO		 3158
3159 switch (ioctl) {
3160 case KVM_SET_TSS_ADDR:
3161 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3162 if (r < 0)
3163 goto out;
3164 break;
b927a3ce
SY		 3165 case KVM_SET_IDENTITY_MAP_ADDR: {
3166 u64 ident_addr;
3167
3168 r = -EFAULT;
3169 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3170 goto out;
3171 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3172 if (r < 0)
3173 goto out;
3174 break;
3175 }
1fe779f8
CO		 3176 case KVM_SET_NR_MMU_PAGES:
3177 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3178 if (r)
3179 goto out;
3180 break;
3181 case KVM_GET_NR_MMU_PAGES:
3182 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3183 break;
3ddea128
MT		 3184 case KVM_CREATE_IRQCHIP: {
3185 struct kvm_pic *vpic;
3186
3187 mutex_lock(&kvm->lock);
3188 r = -EEXIST;
3189 if (kvm->arch.vpic)
3190 goto create_irqchip_unlock;
1fe779f8 3191 r = -ENOMEM;
3ddea128
MT		 3192 vpic = kvm_create_pic(kvm);
3193 if (vpic) {
1fe779f8
CO		 3194 r = kvm_ioapic_init(kvm);
3195 if (r) {
72bb2fcd
WY		 3196 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3197 &vpic->dev);
3ddea128
MT		 3198 kfree(vpic);
3199 goto create_irqchip_unlock;
1fe779f8
CO		 3200 }
3201 } else
3ddea128
MT		 3202 goto create_irqchip_unlock;
3203 smp_wmb();
3204 kvm->arch.vpic = vpic;
3205 smp_wmb();
399ec807
AK		 3206 r = kvm_setup_default_irq_routing(kvm);
3207 if (r) {
3ddea128 3208 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3209 kvm_ioapic_destroy(kvm);
3210 kvm_destroy_pic(kvm);
3ddea128 3211 mutex_unlock(&kvm->irq_lock);
399ec807 3212 }
3ddea128
MT		 3213 create_irqchip_unlock:
3214 mutex_unlock(&kvm->lock);
1fe779f8 3215 break;
3ddea128 3216 }
7837699f 3217 case KVM_CREATE_PIT:
c5ff41ce
JK		 3218 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3219 goto create_pit;
3220 case KVM_CREATE_PIT2:
3221 r = -EFAULT;
3222 if (copy_from_user(&u.pit_config, argp,
3223 sizeof(struct kvm_pit_config)))
3224 goto out;
3225 create_pit:
79fac95e 3226 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3227 r = -EEXIST;
3228 if (kvm->arch.vpit)
3229 goto create_pit_unlock;
7837699f 3230 r = -ENOMEM;
c5ff41ce 3231 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3232 if (kvm->arch.vpit)
3233 r = 0;
269e05e4 3234 create_pit_unlock:
79fac95e 3235 mutex_unlock(&kvm->slots_lock);
7837699f 3236 break;
4925663a 3237 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3238 case KVM_IRQ_LINE: {
3239 struct kvm_irq_level irq_event;
3240
3241 r = -EFAULT;
3242 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3243 goto out;
160d2f6c 3244 r = -ENXIO;
1fe779f8 3245 if (irqchip_in_kernel(kvm)) {
4925663a 3246 __s32 status;
4925663a
GN		 3247 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3248 irq_event.irq, irq_event.level);
4925663a 3249 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3250 r = -EFAULT;
4925663a
GN		 3251 irq_event.status = status;
3252 if (copy_to_user(argp, &irq_event,
3253 sizeof irq_event))
3254 goto out;
3255 }
1fe779f8
CO		 3256 r = 0;
3257 }
3258 break;
3259 }
3260 case KVM_GET_IRQCHIP: {
3261 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3262 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3263
f0d66275
DH		 3264 r = -ENOMEM;
3265 if (!chip)
1fe779f8 3266 goto out;
f0d66275
DH		 3267 r = -EFAULT;
3268 if (copy_from_user(chip, argp, sizeof *chip))
3269 goto get_irqchip_out;
1fe779f8
CO		 3270 r = -ENXIO;
3271 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3272 goto get_irqchip_out;
3273 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3274 if (r)
f0d66275 3275 goto get_irqchip_out;
1fe779f8 3276 r = -EFAULT;
f0d66275
DH		 3277 if (copy_to_user(argp, chip, sizeof *chip))
3278 goto get_irqchip_out;
1fe779f8 3279 r = 0;
f0d66275
DH		 3280 get_irqchip_out:
3281 kfree(chip);
3282 if (r)
3283 goto out;
1fe779f8
CO		 3284 break;
3285 }
3286 case KVM_SET_IRQCHIP: {
3287 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3288 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3289
f0d66275
DH		 3290 r = -ENOMEM;
3291 if (!chip)
1fe779f8 3292 goto out;
f0d66275
DH		 3293 r = -EFAULT;
3294 if (copy_from_user(chip, argp, sizeof *chip))
3295 goto set_irqchip_out;
1fe779f8
CO		 3296 r = -ENXIO;
3297 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3298 goto set_irqchip_out;
3299 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3300 if (r)
f0d66275 3301 goto set_irqchip_out;
1fe779f8 3302 r = 0;
f0d66275
DH		 3303 set_irqchip_out:
3304 kfree(chip);
3305 if (r)
3306 goto out;
1fe779f8
CO		 3307 break;
3308 }
e0f63cb9 3309 case KVM_GET_PIT: {
e0f63cb9 3310 r = -EFAULT;
f0d66275 3311 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3312 goto out;
3313 r = -ENXIO;
3314 if (!kvm->arch.vpit)
3315 goto out;
f0d66275 3316 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3317 if (r)
3318 goto out;
3319 r = -EFAULT;
f0d66275 3320 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3321 goto out;
3322 r = 0;
3323 break;
3324 }
3325 case KVM_SET_PIT: {
e0f63cb9 3326 r = -EFAULT;
f0d66275 3327 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3328 goto out;
3329 r = -ENXIO;
3330 if (!kvm->arch.vpit)
3331 goto out;
f0d66275 3332 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3333 if (r)
3334 goto out;
3335 r = 0;
3336 break;
3337 }
e9f42757
BK		 3338 case KVM_GET_PIT2: {
3339 r = -ENXIO;
3340 if (!kvm->arch.vpit)
3341 goto out;
3342 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3343 if (r)
3344 goto out;
3345 r = -EFAULT;
3346 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3347 goto out;
3348 r = 0;
3349 break;
3350 }
3351 case KVM_SET_PIT2: {
3352 r = -EFAULT;
3353 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3354 goto out;
3355 r = -ENXIO;
3356 if (!kvm->arch.vpit)
3357 goto out;
3358 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3359 if (r)
3360 goto out;
3361 r = 0;
3362 break;
3363 }
52d939a0
MT		 3364 case KVM_REINJECT_CONTROL: {
3365 struct kvm_reinject_control control;
3366 r = -EFAULT;
3367 if (copy_from_user(&control, argp, sizeof(control)))
3368 goto out;
3369 r = kvm_vm_ioctl_reinject(kvm, &control);
3370 if (r)
3371 goto out;
3372 r = 0;
3373 break;
3374 }
ffde22ac
ES		 3375 case KVM_XEN_HVM_CONFIG: {
3376 r = -EFAULT;
3377 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3378 sizeof(struct kvm_xen_hvm_config)))
3379 goto out;
3380 r = -EINVAL;
3381 if (kvm->arch.xen_hvm_config.flags)
3382 goto out;
3383 r = 0;
3384 break;
3385 }
afbcf7ab 3386 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3387 struct kvm_clock_data user_ns;
3388 u64 now_ns;
3389 s64 delta;
3390
3391 r = -EFAULT;
3392 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3393 goto out;
3394
3395 r = -EINVAL;
3396 if (user_ns.flags)
3397 goto out;
3398
3399 r = 0;
759379dd 3400 now_ns = get_kernel_ns();
afbcf7ab
GC		 3401 delta = user_ns.clock - now_ns;
3402 kvm->arch.kvmclock_offset = delta;
3403 break;
3404 }
3405 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3406 struct kvm_clock_data user_ns;
3407 u64 now_ns;
3408
759379dd 3409 now_ns = get_kernel_ns();
afbcf7ab
GC		 3410 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3411 user_ns.flags = 0;
3412
3413 r = -EFAULT;
3414 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3415 goto out;
3416 r = 0;
3417 break;
3418 }
3419
1fe779f8
CO		 3420 default:
3421 ;
3422 }
3423out:
3424 return r;
3425}
3426
a16b043c 3427static void kvm_init_msr_list(void)
043405e1
CO		 3428{
3429 u32 dummy[2];
3430 unsigned i, j;
3431
e3267cbb
GC		 3432 /* skip the first msrs in the list. KVM-specific */
3433 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3434 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3435 continue;
3436 if (j < i)
3437 msrs_to_save[j] = msrs_to_save[i];
3438 j++;
3439 }
3440 num_msrs_to_save = j;
3441}
3442
bda9020e
MT		 3443static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3444 const void *v)
bbd9b64e 3445{
bda9020e
MT		 3446 if (vcpu->arch.apic &&
3447 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3448 return 0;
bbd9b64e 3449
e93f8a0f 3450 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3451}
3452
bda9020e 3453static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3454{
bda9020e
MT		 3455 if (vcpu->arch.apic &&
3456 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3457 return 0;
bbd9b64e 3458
e93f8a0f 3459 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3460}
3461
2dafc6c2
GN		 3462static void kvm_set_segment(struct kvm_vcpu *vcpu,
3463 struct kvm_segment *var, int seg)
3464{
3465 kvm_x86_ops->set_segment(vcpu, var, seg);
3466}
3467
3468void kvm_get_segment(struct kvm_vcpu *vcpu,
3469 struct kvm_segment *var, int seg)
3470{
3471 kvm_x86_ops->get_segment(vcpu, var, seg);
3472}
3473
c30a358d
JR		 3474static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3475{
3476 return gpa;
3477}
3478
1871c602
GN		 3479gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3480{
3481 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3482 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3483}
3484
3485 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3486{
3487 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3488 access |= PFERR_FETCH_MASK;
14dfe855 3489 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3490}
3491
3492gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3493{
3494 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3495 access |= PFERR_WRITE_MASK;
14dfe855 3496 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3497}
3498
3499/* uses this to access any guest's mapped memory without checking CPL */
3500gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3501{
14dfe855 3502 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3503}
3504
3505static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3506 struct kvm_vcpu *vcpu, u32 access,
3507 u32 *error)
bbd9b64e
CO		 3508{
3509 void *data = val;
10589a46 3510 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3511
3512 while (bytes) {
14dfe855
JR		 3513 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3514 error);
bbd9b64e 3515 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3516 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3517 int ret;
3518
10589a46
MT		 3519 if (gpa == UNMAPPED_GVA) {
3520 r = X86EMUL_PROPAGATE_FAULT;
3521 goto out;
3522 }
77c2002e 3523 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3524 if (ret < 0) {
c3cd7ffa 3525 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3526 goto out;
3527 }
bbd9b64e 3528
77c2002e
IE		 3529 bytes -= toread;
3530 data += toread;
3531 addr += toread;
bbd9b64e 3532 }
10589a46 3533out:
10589a46 3534 return r;
bbd9b64e 3535}
77c2002e 3536
1871c602
GN		 3537/* used for instruction fetching */
3538static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3539 struct kvm_vcpu *vcpu, u32 *error)
3540{
3541 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3542 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3543 access | PFERR_FETCH_MASK, error);
3544}
3545
3546static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3547 struct kvm_vcpu *vcpu, u32 *error)
3548{
3549 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3550 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3551 error);
3552}
3553
3554static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3555 struct kvm_vcpu *vcpu, u32 *error)
3556{
3557 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3558}
3559
7972995b 3560static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3561 unsigned int bytes,
7972995b 3562 struct kvm_vcpu *vcpu,
2dafc6c2 3563 u32 *error)
77c2002e
IE		 3564{
3565 void *data = val;
3566 int r = X86EMUL_CONTINUE;
3567
3568 while (bytes) {
14dfe855
JR		 3569 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3570 PFERR_WRITE_MASK,
3571 error);
77c2002e
IE		 3572 unsigned offset = addr & (PAGE_SIZE-1);
3573 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3574 int ret;
3575
3576 if (gpa == UNMAPPED_GVA) {
3577 r = X86EMUL_PROPAGATE_FAULT;
3578 goto out;
3579 }
3580 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3581 if (ret < 0) {
c3cd7ffa 3582 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3583 goto out;
3584 }
3585
3586 bytes -= towrite;
3587 data += towrite;
3588 addr += towrite;
3589 }
3590out:
3591 return r;
3592}
3593
bbd9b64e
CO		 3594static int emulator_read_emulated(unsigned long addr,
3595 void *val,
3596 unsigned int bytes,
8fe681e9 3597 unsigned int *error_code,
bbd9b64e
CO		 3598 struct kvm_vcpu *vcpu)
3599{
bbd9b64e
CO		 3600 gpa_t gpa;
3601
3602 if (vcpu->mmio_read_completed) {
3603 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3604 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3605 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3606 vcpu->mmio_read_completed = 0;
3607 return X86EMUL_CONTINUE;
3608 }
3609
8fe681e9 3610 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3611
8fe681e9 3612 if (gpa == UNMAPPED_GVA)
1871c602 3613 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3614
3615 /* For APIC access vmexit */
3616 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3617 goto mmio;
3618
1871c602 3619 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3620 == X86EMUL_CONTINUE)
bbd9b64e 3621 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3622
3623mmio:
3624 /*
3625 * Is this MMIO handled locally?
3626 */
aec51dc4
AK		 3627 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3628 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3629 return X86EMUL_CONTINUE;
3630 }
aec51dc4
AK		 3631
3632 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3633
3634 vcpu->mmio_needed = 1;
411c35b7
GN		 3635 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3636 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3637 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3638 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3639
c3cd7ffa 3640 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3641}
3642
3200f405 3643int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3644 const void *val, int bytes)
bbd9b64e
CO		 3645{
3646 int ret;
3647
3648 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3649 if (ret < 0)
bbd9b64e 3650 return 0;
ad218f85 3651 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3652 return 1;
3653}
3654
3655static int emulator_write_emulated_onepage(unsigned long addr,
3656 const void *val,
3657 unsigned int bytes,
8fe681e9 3658 unsigned int *error_code,
bbd9b64e
CO		 3659 struct kvm_vcpu *vcpu)
3660{
10589a46
MT		 3661 gpa_t gpa;
3662
8fe681e9 3663 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3664
8fe681e9 3665 if (gpa == UNMAPPED_GVA)
bbd9b64e 3666 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3667
3668 /* For APIC access vmexit */
3669 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3670 goto mmio;
3671
3672 if (emulator_write_phys(vcpu, gpa, val, bytes))
3673 return X86EMUL_CONTINUE;
3674
3675mmio:
aec51dc4 3676 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3677 /*
3678 * Is this MMIO handled locally?
3679 */
bda9020e 3680 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3681 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3682
3683 vcpu->mmio_needed = 1;
411c35b7
GN		 3684 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3685 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3686 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3687 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3688 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3689
3690 return X86EMUL_CONTINUE;
3691}
3692
3693int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3694 const void *val,
3695 unsigned int bytes,
8fe681e9 3696 unsigned int *error_code,
8f6abd06 3697 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3698{
3699 /* Crossing a page boundary? */
3700 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3701 int rc, now;
3702
3703 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3704 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3705 vcpu);
bbd9b64e
CO		 3706 if (rc != X86EMUL_CONTINUE)
3707 return rc;
3708 addr += now;
3709 val += now;
3710 bytes -= now;
3711 }
8fe681e9
GN		 3712 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3713 vcpu);
bbd9b64e 3714}
bbd9b64e 3715
daea3e73
AK		 3716#define CMPXCHG_TYPE(t, ptr, old, new) \
3717 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3718
3719#ifdef CONFIG_X86_64
3720# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3721#else
3722# define CMPXCHG64(ptr, old, new) \
9749a6c0 3723 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3724#endif
3725
bbd9b64e
CO		 3726static int emulator_cmpxchg_emulated(unsigned long addr,
3727 const void *old,
3728 const void *new,
3729 unsigned int bytes,
8fe681e9 3730 unsigned int *error_code,
bbd9b64e
CO		 3731 struct kvm_vcpu *vcpu)
3732{
daea3e73
AK		 3733 gpa_t gpa;
3734 struct page *page;
3735 char *kaddr;
3736 bool exchanged;
2bacc55c 3737
daea3e73
AK		 3738 /* guests cmpxchg8b have to be emulated atomically */
3739 if (bytes > 8 || (bytes & (bytes - 1)))
3740 goto emul_write;
10589a46 3741
daea3e73 3742 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3743
daea3e73
AK		 3744 if (gpa == UNMAPPED_GVA ||
3745 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3746 goto emul_write;
2bacc55c 3747
daea3e73
AK		 3748 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3749 goto emul_write;
72dc67a6 3750
daea3e73 3751 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3752 if (is_error_page(page)) {
3753 kvm_release_page_clean(page);
3754 goto emul_write;
3755 }
72dc67a6 3756
daea3e73
AK		 3757 kaddr = kmap_atomic(page, KM_USER0);
3758 kaddr += offset_in_page(gpa);
3759 switch (bytes) {
3760 case 1:
3761 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3762 break;
3763 case 2:
3764 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3765 break;
3766 case 4:
3767 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3768 break;
3769 case 8:
3770 exchanged = CMPXCHG64(kaddr, old, new);
3771 break;
3772 default:
3773 BUG();
2bacc55c 3774 }
daea3e73
AK		 3775 kunmap_atomic(kaddr, KM_USER0);
3776 kvm_release_page_dirty(page);
3777
3778 if (!exchanged)
3779 return X86EMUL_CMPXCHG_FAILED;
3780
8f6abd06
GN		 3781 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3782
3783 return X86EMUL_CONTINUE;
4a5f48f6 3784
3200f405 3785emul_write:
daea3e73 3786 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3787
8fe681e9 3788 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3789}
3790
cf8f70bf
GN		 3791static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3792{
3793 /* TODO: String I/O for in kernel device */
3794 int r;
3795
3796 if (vcpu->arch.pio.in)
3797 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3798 vcpu->arch.pio.size, pd);
3799 else
3800 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3801 vcpu->arch.pio.port, vcpu->arch.pio.size,
3802 pd);
3803 return r;
3804}
3805
3806
3807static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3808 unsigned int count, struct kvm_vcpu *vcpu)
3809{
7972995b 3810 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3811 goto data_avail;
3812
c41a15dd 3813 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3814
3815 vcpu->arch.pio.port = port;
3816 vcpu->arch.pio.in = 1;
7972995b 3817 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3818 vcpu->arch.pio.size = size;
3819
3820 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3821 data_avail:
3822 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3823 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3824 return 1;
3825 }
3826
3827 vcpu->run->exit_reason = KVM_EXIT_IO;
3828 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3829 vcpu->run->io.size = size;
3830 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3831 vcpu->run->io.count = count;
3832 vcpu->run->io.port = port;
3833
3834 return 0;
3835}
3836
3837static int emulator_pio_out_emulated(int size, unsigned short port,
3838 const void *val, unsigned int count,
3839 struct kvm_vcpu *vcpu)
3840{
c41a15dd 3841 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3842
3843 vcpu->arch.pio.port = port;
3844 vcpu->arch.pio.in = 0;
7972995b 3845 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3846 vcpu->arch.pio.size = size;
3847
3848 memcpy(vcpu->arch.pio_data, val, size * count);
3849
3850 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3851 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3852 return 1;
3853 }
3854
3855 vcpu->run->exit_reason = KVM_EXIT_IO;
3856 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3857 vcpu->run->io.size = size;
3858 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3859 vcpu->run->io.count = count;
3860 vcpu->run->io.port = port;
3861
3862 return 0;
3863}
3864
bbd9b64e
CO		 3865static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3866{
3867 return kvm_x86_ops->get_segment_base(vcpu, seg);
3868}
3869
3870int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3871{
a7052897 3872 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3873 return X86EMUL_CONTINUE;
3874}
3875
f5f48ee1
SY		 3876int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3877{
3878 if (!need_emulate_wbinvd(vcpu))
3879 return X86EMUL_CONTINUE;
3880
3881 if (kvm_x86_ops->has_wbinvd_exit()) {
3882 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3883 wbinvd_ipi, NULL, 1);
3884 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3885 }
3886 wbinvd();
3887 return X86EMUL_CONTINUE;
3888}
3889EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3890
bbd9b64e
CO		 3891int emulate_clts(struct kvm_vcpu *vcpu)
3892{
4d4ec087 3893 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3894 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3895 return X86EMUL_CONTINUE;
3896}
3897
35aa5375 3898int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3899{
338dbc97 3900 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3901}
3902
35aa5375 3903int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3904{
338dbc97
GN		 3905
3906 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3907}
3908
52a46617 3909static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3910{
52a46617 3911 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3912}
3913
52a46617 3914static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3915{
52a46617
GN		 3916 unsigned long value;
3917
3918 switch (cr) {
3919 case 0:
3920 value = kvm_read_cr0(vcpu);
3921 break;
3922 case 2:
3923 value = vcpu->arch.cr2;
3924 break;
3925 case 3:
3926 value = vcpu->arch.cr3;
3927 break;
3928 case 4:
3929 value = kvm_read_cr4(vcpu);
3930 break;
3931 case 8:
3932 value = kvm_get_cr8(vcpu);
3933 break;
3934 default:
3935 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3936 return 0;
3937 }
3938
3939 return value;
3940}
3941
0f12244f 3942static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3943{
0f12244f
GN		 3944 int res = 0;
3945
52a46617
GN		 3946 switch (cr) {
3947 case 0:
49a9b07e 3948 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3949 break;
3950 case 2:
3951 vcpu->arch.cr2 = val;
3952 break;
3953 case 3:
2390218b 3954 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3955 break;
3956 case 4:
a83b29c6 3957 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3958 break;
3959 case 8:
0f12244f 3960 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3961 break;
3962 default:
3963 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3964 res = -1;
52a46617 3965 }
0f12244f
GN		 3966
3967 return res;
52a46617
GN		 3968}
3969
9c537244
GN		 3970static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3971{
3972 return kvm_x86_ops->get_cpl(vcpu);
3973}
3974
2dafc6c2
GN		 3975static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3976{
3977 kvm_x86_ops->get_gdt(vcpu, dt);
3978}
3979
160ce1f1
MG		 3980static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3981{
3982 kvm_x86_ops->get_idt(vcpu, dt);
3983}
3984
5951c442
GN		 3985static unsigned long emulator_get_cached_segment_base(int seg,
3986 struct kvm_vcpu *vcpu)
3987{
3988 return get_segment_base(vcpu, seg);
3989}
3990
2dafc6c2
GN		 3991static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3992 struct kvm_vcpu *vcpu)
3993{
3994 struct kvm_segment var;
3995
3996 kvm_get_segment(vcpu, &var, seg);
3997
3998 if (var.unusable)
3999 return false;
4000
4001 if (var.g)
4002 var.limit >>= 12;
4003 set_desc_limit(desc, var.limit);
4004 set_desc_base(desc, (unsigned long)var.base);
4005 desc->type = var.type;
4006 desc->s = var.s;
4007 desc->dpl = var.dpl;
4008 desc->p = var.present;
4009 desc->avl = var.avl;
4010 desc->l = var.l;
4011 desc->d = var.db;
4012 desc->g = var.g;
4013
4014 return true;
4015}
4016
4017static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4018 struct kvm_vcpu *vcpu)
4019{
4020 struct kvm_segment var;
4021
4022 /* needed to preserve selector */
4023 kvm_get_segment(vcpu, &var, seg);
4024
4025 var.base = get_desc_base(desc);
4026 var.limit = get_desc_limit(desc);
4027 if (desc->g)
4028 var.limit = (var.limit << 12) | 0xfff;
4029 var.type = desc->type;
4030 var.present = desc->p;
4031 var.dpl = desc->dpl;
4032 var.db = desc->d;
4033 var.s = desc->s;
4034 var.l = desc->l;
4035 var.g = desc->g;
4036 var.avl = desc->avl;
4037 var.present = desc->p;
4038 var.unusable = !var.present;
4039 var.padding = 0;
4040
4041 kvm_set_segment(vcpu, &var, seg);
4042 return;
4043}
4044
4045static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4046{
4047 struct kvm_segment kvm_seg;
4048
4049 kvm_get_segment(vcpu, &kvm_seg, seg);
4050 return kvm_seg.selector;
4051}
4052
4053static void emulator_set_segment_selector(u16 sel, int seg,
4054 struct kvm_vcpu *vcpu)
4055{
4056 struct kvm_segment kvm_seg;
4057
4058 kvm_get_segment(vcpu, &kvm_seg, seg);
4059 kvm_seg.selector = sel;
4060 kvm_set_segment(vcpu, &kvm_seg, seg);
4061}
4062
14af3f3c 4063static struct x86_emulate_ops emulate_ops = {
1871c602 4064 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4065 .write_std = kvm_write_guest_virt_system,
1871c602 4066 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4067 .read_emulated = emulator_read_emulated,
4068 .write_emulated = emulator_write_emulated,
4069 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4070 .pio_in_emulated = emulator_pio_in_emulated,
4071 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4072 .get_cached_descriptor = emulator_get_cached_descriptor,
4073 .set_cached_descriptor = emulator_set_cached_descriptor,
4074 .get_segment_selector = emulator_get_segment_selector,
4075 .set_segment_selector = emulator_set_segment_selector,
5951c442 4076 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4077 .get_gdt = emulator_get_gdt,
160ce1f1 4078 .get_idt = emulator_get_idt,
52a46617
GN		 4079 .get_cr = emulator_get_cr,
4080 .set_cr = emulator_set_cr,
9c537244 4081 .cpl = emulator_get_cpl,
35aa5375
GN		 4082 .get_dr = emulator_get_dr,
4083 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4084 .set_msr = kvm_set_msr,
4085 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4086};
4087
5fdbf976
MT		 4088static void cache_all_regs(struct kvm_vcpu *vcpu)
4089{
4090 kvm_register_read(vcpu, VCPU_REGS_RAX);
4091 kvm_register_read(vcpu, VCPU_REGS_RSP);
4092 kvm_register_read(vcpu, VCPU_REGS_RIP);
4093 vcpu->arch.regs_dirty = ~0;
4094}
4095
95cb2295
GN		 4096static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4097{
4098 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4099 /*
4100 * an sti; sti; sequence only disable interrupts for the first
4101 * instruction. So, if the last instruction, be it emulated or
4102 * not, left the system with the INT_STI flag enabled, it
4103 * means that the last instruction is an sti. We should not
4104 * leave the flag on in this case. The same goes for mov ss
4105 */
4106 if (!(int_shadow & mask))
4107 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4108}
4109
54b8486f
GN		 4110static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4111{
4112 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4113 if (ctxt->exception == PF_VECTOR)
8df25a32 4114 kvm_inject_page_fault(vcpu);
54b8486f
GN		 4115 else if (ctxt->error_code_valid)
4116 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4117 else
4118 kvm_queue_exception(vcpu, ctxt->exception);
4119}
4120
8ec4722d
MG		 4121static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4122{
4123 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4124 int cs_db, cs_l;
4125
4126 cache_all_regs(vcpu);
4127
4128 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4129
4130 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4131 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4132 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4133 vcpu->arch.emulate_ctxt.mode =
4134 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4135 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4136 ? X86EMUL_MODE_VM86 : cs_l
4137 ? X86EMUL_MODE_PROT64 : cs_db
4138 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4139 memset(c, 0, sizeof(struct decode_cache));
4140 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4141}
4142
6d77dbfc
GN		 4143static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4144{
6d77dbfc
GN		 4145 ++vcpu->stat.insn_emulation_fail;
4146 trace_kvm_emulate_insn_failed(vcpu);
4147 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4148 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4149 vcpu->run->internal.ndata = 0;
4150 kvm_queue_exception(vcpu, UD_VECTOR);
4151 return EMULATE_FAIL;
4152}
4153
a6f177ef
GN		 4154static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4155{
4156 gpa_t gpa;
4157
68be0803
GN		 4158 if (tdp_enabled)
4159 return false;
4160
a6f177ef
GN		 4161 /*
4162 * if emulation was due to access to shadowed page table
4163 * and it failed try to unshadow page and re-entetr the
4164 * guest to let CPU execute the instruction.
4165 */
4166 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4167 return true;
4168
4169 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4170
4171 if (gpa == UNMAPPED_GVA)
4172 return true; /* let cpu generate fault */
4173
4174 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4175 return true;
4176
4177 return false;
4178}
4179
bbd9b64e 4180int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4181 unsigned long cr2,
4182 u16 error_code,
571008da 4183 int emulation_type)
bbd9b64e 4184{
95cb2295 4185 int r;
4d2179e1 4186 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4187
26eef70c 4188 kvm_clear_exception_queue(vcpu);
ad312c7c 4189 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4190 /*
56e82318 4191 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4192 * instead of direct ->regs accesses, can save hundred cycles
4193 * on Intel for instructions that don't read/change RSP, for
4194 * for example.
4195 */
4196 cache_all_regs(vcpu);
bbd9b64e 4197
571008da 4198 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4199 init_emulate_ctxt(vcpu);
95cb2295 4200 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4201 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4202 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4203
9aabc88f 4204 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
e46479f8 4205 trace_kvm_emulate_insn_start(vcpu);
571008da 4206
0cb5762e
AP		 4207 /* Only allow emulation of specific instructions on #UD
4208 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4209 if (emulation_type & EMULTYPE_TRAP_UD) {
4210 if (!c->twobyte)
4211 return EMULATE_FAIL;
4212 switch (c->b) {
4213 case 0x01: /* VMMCALL */
4214 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4215 return EMULATE_FAIL;
4216 break;
4217 case 0x34: /* sysenter */
4218 case 0x35: /* sysexit */
4219 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4220 return EMULATE_FAIL;
4221 break;
4222 case 0x05: /* syscall */
4223 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4224 return EMULATE_FAIL;
4225 break;
4226 default:
4227 return EMULATE_FAIL;
4228 }
4229
4230 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4231 return EMULATE_FAIL;
4232 }
571008da 4233
f2b5756b 4234 ++vcpu->stat.insn_emulation;
bbd9b64e 4235 if (r) {
a6f177ef 4236 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4237 return EMULATE_DONE;
6d77dbfc
GN		 4238 if (emulation_type & EMULTYPE_SKIP)
4239 return EMULATE_FAIL;
4240 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4241 }
4242 }
4243
ba8afb6b
GN		 4244 if (emulation_type & EMULTYPE_SKIP) {
4245 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4246 return EMULATE_DONE;
4247 }
4248
4d2179e1
GN		 4249 /* this is needed for vmware backdor interface to work since it
4250 changes registers values during IO operation */
4251 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4252
5cd21917 4253restart:
9aabc88f 4254 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4255
d2ddd1c4 4256 if (r == EMULATION_FAILED) {
a6f177ef 4257 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4258 return EMULATE_DONE;
4259
6d77dbfc 4260 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4261 }
4262
d2ddd1c4 4263 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4264 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4265 r = EMULATE_DONE;
4266 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4267 if (!vcpu->arch.pio.in)
4268 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4269 r = EMULATE_DO_MMIO;
4270 } else if (vcpu->mmio_needed) {
3457e419
GN		 4271 if (vcpu->mmio_is_write)
4272 vcpu->mmio_needed = 0;
e85d28f8 4273 r = EMULATE_DO_MMIO;
d2ddd1c4 4274 } else if (r == EMULATION_RESTART)
5cd21917 4275 goto restart;
d2ddd1c4
GN		 4276 else
4277 r = EMULATE_DONE;
f850e2e6 4278
e85d28f8
GN		 4279 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4280 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4281 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4282 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4283
4284 return r;
de7d789a 4285}
bbd9b64e 4286EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4287
cf8f70bf 4288int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4289{
cf8f70bf
GN		 4290 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4291 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4292 /* do not return to emulator after return from userspace */
7972995b 4293 vcpu->arch.pio.count = 0;
de7d789a
CO		 4294 return ret;
4295}
cf8f70bf 4296EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4297
8cfdc000
ZA		 4298static void tsc_bad(void *info)
4299{
4300 __get_cpu_var(cpu_tsc_khz) = 0;
4301}
4302
4303static void tsc_khz_changed(void *data)
c8076604 4304{
8cfdc000
ZA		 4305 struct cpufreq_freqs *freq = data;
4306 unsigned long khz = 0;
4307
4308 if (data)
4309 khz = freq->new;
4310 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4311 khz = cpufreq_quick_get(raw_smp_processor_id());
4312 if (!khz)
4313 khz = tsc_khz;
4314 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4315}
4316
c8076604
GH		 4317static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4318 void *data)
4319{
4320 struct cpufreq_freqs *freq = data;
4321 struct kvm *kvm;
4322 struct kvm_vcpu *vcpu;
4323 int i, send_ipi = 0;
4324
8cfdc000
ZA		 4325 /*
4326 * We allow guests to temporarily run on slowing clocks,
4327 * provided we notify them after, or to run on accelerating
4328 * clocks, provided we notify them before. Thus time never
4329 * goes backwards.
4330 *
4331 * However, we have a problem. We can't atomically update
4332 * the frequency of a given CPU from this function; it is
4333 * merely a notifier, which can be called from any CPU.
4334 * Changing the TSC frequency at arbitrary points in time
4335 * requires a recomputation of local variables related to
4336 * the TSC for each VCPU. We must flag these local variables
4337 * to be updated and be sure the update takes place with the
4338 * new frequency before any guests proceed.
4339 *
4340 * Unfortunately, the combination of hotplug CPU and frequency
4341 * change creates an intractable locking scenario; the order
4342 * of when these callouts happen is undefined with respect to
4343 * CPU hotplug, and they can race with each other. As such,
4344 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4345 * undefined; you can actually have a CPU frequency change take
4346 * place in between the computation of X and the setting of the
4347 * variable. To protect against this problem, all updates of
4348 * the per_cpu tsc_khz variable are done in an interrupt
4349 * protected IPI, and all callers wishing to update the value
4350 * must wait for a synchronous IPI to complete (which is trivial
4351 * if the caller is on the CPU already). This establishes the
4352 * necessary total order on variable updates.
4353 *
4354 * Note that because a guest time update may take place
4355 * anytime after the setting of the VCPU's request bit, the
4356 * correct TSC value must be set before the request. However,
4357 * to ensure the update actually makes it to any guest which
4358 * starts running in hardware virtualization between the set
4359 * and the acquisition of the spinlock, we must also ping the
4360 * CPU after setting the request bit.
4361 *
4362 */
4363
c8076604
GH		 4364 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4365 return 0;
4366 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4367 return 0;
8cfdc000
ZA		 4368
4369 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4370
4371 spin_lock(&kvm_lock);
4372 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4373 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4374 if (vcpu->cpu != freq->cpu)
4375 continue;
4376 if (!kvm_request_guest_time_update(vcpu))
4377 continue;
4378 if (vcpu->cpu != smp_processor_id())
8cfdc000 4379 send_ipi = 1;
c8076604
GH		 4380 }
4381 }
4382 spin_unlock(&kvm_lock);
4383
4384 if (freq->old < freq->new && send_ipi) {
4385 /*
4386 * We upscale the frequency. Must make the guest
4387 * doesn't see old kvmclock values while running with
4388 * the new frequency, otherwise we risk the guest sees
4389 * time go backwards.
4390 *
4391 * In case we update the frequency for another cpu
4392 * (which might be in guest context) send an interrupt
4393 * to kick the cpu out of guest context. Next time
4394 * guest context is entered kvmclock will be updated,
4395 * so the guest will not see stale values.
4396 */
8cfdc000 4397 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4398 }
4399 return 0;
4400}
4401
4402static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4403 .notifier_call = kvmclock_cpufreq_notifier
4404};
4405
4406static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4407 unsigned long action, void *hcpu)
4408{
4409 unsigned int cpu = (unsigned long)hcpu;
4410
4411 switch (action) {
4412 case CPU_ONLINE:
4413 case CPU_DOWN_FAILED:
4414 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4415 break;
4416 case CPU_DOWN_PREPARE:
4417 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4418 break;
4419 }
4420 return NOTIFY_OK;
4421}
4422
4423static struct notifier_block kvmclock_cpu_notifier_block = {
4424 .notifier_call = kvmclock_cpu_notifier,
4425 .priority = -INT_MAX
c8076604
GH		 4426};
4427
b820cc0c
ZA		 4428static void kvm_timer_init(void)
4429{
4430 int cpu;
4431
8cfdc000 4432 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4433 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4434 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4435 CPUFREQ_TRANSITION_NOTIFIER);
4436 }
8cfdc000
ZA		 4437 for_each_online_cpu(cpu)
4438 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4439}
4440
ff9d07a0
ZY		 4441static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4442
4443static int kvm_is_in_guest(void)
4444{
4445 return percpu_read(current_vcpu) != NULL;
4446}
4447
4448static int kvm_is_user_mode(void)
4449{
4450 int user_mode = 3;
dcf46b94 4451
ff9d07a0
ZY		 4452 if (percpu_read(current_vcpu))
4453 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4454
ff9d07a0
ZY		 4455 return user_mode != 0;
4456}
4457
4458static unsigned long kvm_get_guest_ip(void)
4459{
4460 unsigned long ip = 0;
dcf46b94 4461
ff9d07a0
ZY		 4462 if (percpu_read(current_vcpu))
4463 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4464
ff9d07a0
ZY		 4465 return ip;
4466}
4467
4468static struct perf_guest_info_callbacks kvm_guest_cbs = {
4469 .is_in_guest = kvm_is_in_guest,
4470 .is_user_mode = kvm_is_user_mode,
4471 .get_guest_ip = kvm_get_guest_ip,
4472};
4473
4474void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4475{
4476 percpu_write(current_vcpu, vcpu);
4477}
4478EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4479
4480void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4481{
4482 percpu_write(current_vcpu, NULL);
4483}
4484EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4485
f8c16bba 4486int kvm_arch_init(void *opaque)
043405e1 4487{
b820cc0c 4488 int r;
f8c16bba
ZX		 4489 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4490
f8c16bba
ZX		 4491 if (kvm_x86_ops) {
4492 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4493 r = -EEXIST;
4494 goto out;
f8c16bba
ZX		 4495 }
4496
4497 if (!ops->cpu_has_kvm_support()) {
4498 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4499 r = -EOPNOTSUPP;
4500 goto out;
f8c16bba
ZX		 4501 }
4502 if (ops->disabled_by_bios()) {
4503 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4504 r = -EOPNOTSUPP;
4505 goto out;
f8c16bba
ZX		 4506 }
4507
97db56ce
AK		 4508 r = kvm_mmu_module_init();
4509 if (r)
4510 goto out;
4511
4512 kvm_init_msr_list();
4513
f8c16bba 4514 kvm_x86_ops = ops;
56c6d28a 4515 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4516 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4517 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4518 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4519
b820cc0c 4520 kvm_timer_init();
c8076604 4521
ff9d07a0
ZY		 4522 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4523
2acf923e
DC		 4524 if (cpu_has_xsave)
4525 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4526
f8c16bba 4527 return 0;
56c6d28a
ZX		 4528
4529out:
56c6d28a 4530 return r;
043405e1 4531}
8776e519 4532
f8c16bba
ZX		 4533void kvm_arch_exit(void)
4534{
ff9d07a0
ZY		 4535 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4536
888d256e
JK		 4537 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4538 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4539 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4540 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4541 kvm_x86_ops = NULL;
56c6d28a
ZX		 4542 kvm_mmu_module_exit();
4543}
f8c16bba 4544
8776e519
HB		 4545int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4546{
4547 ++vcpu->stat.halt_exits;
4548 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4549 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4550 return 1;
4551 } else {
4552 vcpu->run->exit_reason = KVM_EXIT_HLT;
4553 return 0;
4554 }
4555}
4556EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4557
2f333bcb
MT		 4558static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4559 unsigned long a1)
4560{
4561 if (is_long_mode(vcpu))
4562 return a0;
4563 else
4564 return a0 | ((gpa_t)a1 << 32);
4565}
4566
55cd8e5a
GN		 4567int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4568{
4569 u64 param, ingpa, outgpa, ret;
4570 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4571 bool fast, longmode;
4572 int cs_db, cs_l;
4573
4574 /*
4575 * hypercall generates UD from non zero cpl and real mode
4576 * per HYPER-V spec
4577 */
3eeb3288 4578 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4579 kvm_queue_exception(vcpu, UD_VECTOR);
4580 return 0;
4581 }
4582
4583 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4584 longmode = is_long_mode(vcpu) && cs_l == 1;
4585
4586 if (!longmode) {
ccd46936
GN		 4587 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4588 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4589 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4590 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4591 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4592 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4593 }
4594#ifdef CONFIG_X86_64
4595 else {
4596 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4597 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4598 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4599 }
4600#endif
4601
4602 code = param & 0xffff;
4603 fast = (param >> 16) & 0x1;
4604 rep_cnt = (param >> 32) & 0xfff;
4605 rep_idx = (param >> 48) & 0xfff;
4606
4607 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4608
c25bc163
GN		 4609 switch (code) {
4610 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4611 kvm_vcpu_on_spin(vcpu);
4612 break;
4613 default:
4614 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4615 break;
4616 }
55cd8e5a
GN		 4617
4618 ret = res | (((u64)rep_done & 0xfff) << 32);
4619 if (longmode) {
4620 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4621 } else {
4622 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4623 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4624 }
4625
4626 return 1;
4627}
4628
8776e519
HB		 4629int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4630{
4631 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4632 int r = 1;
8776e519 4633
55cd8e5a
GN		 4634 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4635 return kvm_hv_hypercall(vcpu);
4636
5fdbf976
MT		 4637 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4638 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4639 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4640 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4641 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4642
229456fc 4643 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4644
8776e519
HB		 4645 if (!is_long_mode(vcpu)) {
4646 nr &= 0xFFFFFFFF;
4647 a0 &= 0xFFFFFFFF;
4648 a1 &= 0xFFFFFFFF;
4649 a2 &= 0xFFFFFFFF;
4650 a3 &= 0xFFFFFFFF;
4651 }
4652
07708c4a
JK		 4653 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4654 ret = -KVM_EPERM;
4655 goto out;
4656 }
4657
8776e519 4658 switch (nr) {
b93463aa
AK		 4659 case KVM_HC_VAPIC_POLL_IRQ:
4660 ret = 0;
4661 break;
2f333bcb
MT		 4662 case KVM_HC_MMU_OP:
4663 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4664 break;
8776e519
HB		 4665 default:
4666 ret = -KVM_ENOSYS;
4667 break;
4668 }
07708c4a 4669out:
5fdbf976 4670 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4671 ++vcpu->stat.hypercalls;
2f333bcb 4672 return r;
8776e519
HB		 4673}
4674EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4675
4676int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4677{
4678 char instruction[3];
5fdbf976 4679 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4680
8776e519
HB		 4681 /*
4682 * Blow out the MMU to ensure that no other VCPU has an active mapping
4683 * to ensure that the updated hypercall appears atomically across all
4684 * VCPUs.
4685 */
4686 kvm_mmu_zap_all(vcpu->kvm);
4687
8776e519 4688 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4689
8fe681e9 4690 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4691}
4692
8776e519
HB		 4693void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4694{
89a27f4d 4695 struct desc_ptr dt = { limit, base };
8776e519
HB		 4696
4697 kvm_x86_ops->set_gdt(vcpu, &dt);
4698}
4699
4700void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4701{
89a27f4d 4702 struct desc_ptr dt = { limit, base };
8776e519
HB		 4703
4704 kvm_x86_ops->set_idt(vcpu, &dt);
4705}
4706
07716717
DK		 4707static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4708{
ad312c7c
ZX		 4709 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4710 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4711
4712 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4713 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4714 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4715 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4716 if (ej->function == e->function) {
4717 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4718 return j;
4719 }
4720 }
4721 return 0; /* silence gcc, even though control never reaches here */
4722}
4723
4724/* find an entry with matching function, matching index (if needed), and that
4725 * should be read next (if it's stateful) */
4726static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4727 u32 function, u32 index)
4728{
4729 if (e->function != function)
4730 return 0;
4731 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4732 return 0;
4733 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4734 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4735 return 0;
4736 return 1;
4737}
4738
d8017474
AG		 4739struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4740 u32 function, u32 index)
8776e519
HB		 4741{
4742 int i;
d8017474 4743 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4744
ad312c7c 4745 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4746 struct kvm_cpuid_entry2 *e;
4747
ad312c7c 4748 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4749 if (is_matching_cpuid_entry(e, function, index)) {
4750 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4751 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4752 best = e;
4753 break;
4754 }
4755 /*
4756 * Both basic or both extended?
4757 */
4758 if (((e->function ^ function) & 0x80000000) == 0)
4759 if (!best || e->function > best->function)
4760 best = e;
4761 }
d8017474
AG		 4762 return best;
4763}
0e851880 4764EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4765
82725b20
DE		 4766int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4767{
4768 struct kvm_cpuid_entry2 *best;
4769
f7a71197
AK		 4770 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4771 if (!best || best->eax < 0x80000008)
4772 goto not_found;
82725b20
DE		 4773 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4774 if (best)
4775 return best->eax & 0xff;
f7a71197 4776not_found:
82725b20
DE		 4777 return 36;
4778}
4779
d8017474
AG		 4780void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4781{
4782 u32 function, index;
4783 struct kvm_cpuid_entry2 *best;
4784
4785 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4786 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4787 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4788 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4789 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4790 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4791 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4792 if (best) {
5fdbf976
MT		 4793 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4794 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4795 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4796 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4797 }
8776e519 4798 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4799 trace_kvm_cpuid(function,
4800 kvm_register_read(vcpu, VCPU_REGS_RAX),
4801 kvm_register_read(vcpu, VCPU_REGS_RBX),
4802 kvm_register_read(vcpu, VCPU_REGS_RCX),
4803 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4804}
4805EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4806
b6c7a5dc
HB		 4807/*
4808 * Check if userspace requested an interrupt window, and that the
4809 * interrupt window is open.
4810 *
4811 * No need to exit to userspace if we already have an interrupt queued.
4812 */
851ba692 4813static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4814{
8061823a 4815 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4816 vcpu->run->request_interrupt_window &&
5df56646 4817 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4818}
4819
851ba692 4820static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4821{
851ba692
AK		 4822 struct kvm_run *kvm_run = vcpu->run;
4823
91586a3b 4824 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4825 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4826 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4827 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4828 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4829 else
b6c7a5dc 4830 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4831 kvm_arch_interrupt_allowed(vcpu) &&
4832 !kvm_cpu_has_interrupt(vcpu) &&
4833 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4834}
4835
b93463aa
AK		 4836static void vapic_enter(struct kvm_vcpu *vcpu)
4837{
4838 struct kvm_lapic *apic = vcpu->arch.apic;
4839 struct page *page;
4840
4841 if (!apic || !apic->vapic_addr)
4842 return;
4843
4844 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4845
4846 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4847}
4848
4849static void vapic_exit(struct kvm_vcpu *vcpu)
4850{
4851 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4852 int idx;
b93463aa
AK		 4853
4854 if (!apic || !apic->vapic_addr)
4855 return;
4856
f656ce01 4857 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4858 kvm_release_page_dirty(apic->vapic_page);
4859 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4860 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4861}
4862
95ba8273
GN		 4863static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4864{
4865 int max_irr, tpr;
4866
4867 if (!kvm_x86_ops->update_cr8_intercept)
4868 return;
4869
88c808fd
AK		 4870 if (!vcpu->arch.apic)
4871 return;
4872
8db3baa2
GN		 4873 if (!vcpu->arch.apic->vapic_addr)
4874 max_irr = kvm_lapic_find_highest_irr(vcpu);
4875 else
4876 max_irr = -1;
95ba8273
GN		 4877
4878 if (max_irr != -1)
4879 max_irr >>= 4;
4880
4881 tpr = kvm_lapic_get_cr8(vcpu);
4882
4883 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4884}
4885
851ba692 4886static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4887{
4888 /* try to reinject previous events if any */
b59bb7bd 4889 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4890 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4891 vcpu->arch.exception.has_error_code,
4892 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4893 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4894 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4895 vcpu->arch.exception.error_code,
4896 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4897 return;
4898 }
4899
95ba8273
GN		 4900 if (vcpu->arch.nmi_injected) {
4901 kvm_x86_ops->set_nmi(vcpu);
4902 return;
4903 }
4904
4905 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4906 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4907 return;
4908 }
4909
4910 /* try to inject new event if pending */
4911 if (vcpu->arch.nmi_pending) {
4912 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4913 vcpu->arch.nmi_pending = false;
4914 vcpu->arch.nmi_injected = true;
4915 kvm_x86_ops->set_nmi(vcpu);
4916 }
4917 } else if (kvm_cpu_has_interrupt(vcpu)) {
4918 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4919 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4920 false);
4921 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4922 }
4923 }
4924}
4925
2acf923e
DC		 4926static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4927{
4928 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4929 !vcpu->guest_xcr0_loaded) {
4930 /* kvm_set_xcr() also depends on this */
4931 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4932 vcpu->guest_xcr0_loaded = 1;
4933 }
4934}
4935
4936static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4937{
4938 if (vcpu->guest_xcr0_loaded) {
4939 if (vcpu->arch.xcr0 != host_xcr0)
4940 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4941 vcpu->guest_xcr0_loaded = 0;
4942 }
4943}
4944
851ba692 4945static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4946{
4947 int r;
6a8b1d13 4948 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4949 vcpu->run->request_interrupt_window;
b6c7a5dc 4950
3e007509 4951 if (vcpu->requests) {
a8eeb04a 4952 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4953 kvm_mmu_unload(vcpu);
a8eeb04a 4954 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4955 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 4956 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
4957 r = kvm_write_guest_time(vcpu);
4958 if (unlikely(r))
4959 goto out;
4960 }
a8eeb04a 4961 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4962 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4963 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4964 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4965 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4966 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4967 r = 0;
4968 goto out;
4969 }
a8eeb04a 4970 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 4971 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4972 r = 0;
4973 goto out;
4974 }
a8eeb04a 4975 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 4976 vcpu->fpu_active = 0;
4977 kvm_x86_ops->fpu_deactivate(vcpu);
4978 }
2f52d58c 4979 }
b93463aa 4980
3e007509
AK		 4981 r = kvm_mmu_reload(vcpu);
4982 if (unlikely(r))
4983 goto out;
4984
b6c7a5dc
HB		 4985 preempt_disable();
4986
4987 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4988 if (vcpu->fpu_active)
4989 kvm_load_guest_fpu(vcpu);
2acf923e 4990 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4991
d94e1dc9
AK		 4992 atomic_set(&vcpu->guest_mode, 1);
4993 smp_wmb();
b6c7a5dc 4994
d94e1dc9 4995 local_irq_disable();
32f88400 4996
d94e1dc9
AK		 4997 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4998 || need_resched() || signal_pending(current)) {
4999 atomic_set(&vcpu->guest_mode, 0);
5000 smp_wmb();
6c142801
AK		 5001 local_irq_enable();
5002 preempt_enable();
5003 r = 1;
5004 goto out;
5005 }
5006
851ba692 5007 inject_pending_event(vcpu);
b6c7a5dc 5008
6a8b1d13
GN		 5009 /* enable NMI/IRQ window open exits if needed */
5010 if (vcpu->arch.nmi_pending)
5011 kvm_x86_ops->enable_nmi_window(vcpu);
5012 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5013 kvm_x86_ops->enable_irq_window(vcpu);
5014
95ba8273 5015 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 5016 update_cr8_intercept(vcpu);
5017 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 5018 }
b93463aa 5019
f656ce01 5020 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5021
b6c7a5dc
HB		 5022 kvm_guest_enter();
5023
42dbaa5a 5024 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5025 set_debugreg(0, 7);
5026 set_debugreg(vcpu->arch.eff_db[0], 0);
5027 set_debugreg(vcpu->arch.eff_db[1], 1);
5028 set_debugreg(vcpu->arch.eff_db[2], 2);
5029 set_debugreg(vcpu->arch.eff_db[3], 3);
5030 }
b6c7a5dc 5031
229456fc 5032 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5033 kvm_x86_ops->run(vcpu);
b6c7a5dc 5034
24f1e32c
FW		 5035 /*
5036 * If the guest has used debug registers, at least dr7
5037 * will be disabled while returning to the host.
5038 * If we don't have active breakpoints in the host, we don't
5039 * care about the messed up debug address registers. But if
5040 * we have some of them active, restore the old state.
5041 */
59d8eb53 5042 if (hw_breakpoint_active())
24f1e32c 5043 hw_breakpoint_restore();
42dbaa5a 5044
1d5f066e
ZA		 5045 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5046
d94e1dc9
AK		 5047 atomic_set(&vcpu->guest_mode, 0);
5048 smp_wmb();
b6c7a5dc
HB		 5049 local_irq_enable();
5050
5051 ++vcpu->stat.exits;
5052
5053 /*
5054 * We must have an instruction between local_irq_enable() and
5055 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5056 * the interrupt shadow. The stat.exits increment will do nicely.
5057 * But we need to prevent reordering, hence this barrier():
5058 */
5059 barrier();
5060
5061 kvm_guest_exit();
5062
5063 preempt_enable();
5064
f656ce01 5065 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5066
b6c7a5dc
HB		 5067 /*
5068 * Profile KVM exit RIPs:
5069 */
5070 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5071 unsigned long rip = kvm_rip_read(vcpu);
5072 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5073 }
5074
298101da 5075
b93463aa
AK		 5076 kvm_lapic_sync_from_vapic(vcpu);
5077
851ba692 5078 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5079out:
5080 return r;
5081}
b6c7a5dc 5082
09cec754 5083
851ba692 5084static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5085{
5086 int r;
f656ce01 5087 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5088
5089 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5090 pr_debug("vcpu %d received sipi with vector # %x\n",
5091 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5092 kvm_lapic_reset(vcpu);
5f179287 5093 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5094 if (r)
5095 return r;
5096 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5097 }
5098
f656ce01 5099 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5100 vapic_enter(vcpu);
5101
5102 r = 1;
5103 while (r > 0) {
af2152f5 5104 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5105 r = vcpu_enter_guest(vcpu);
d7690175 5106 else {
f656ce01 5107 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5108 kvm_vcpu_block(vcpu);
f656ce01 5109 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5110 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5111 {
5112 switch(vcpu->arch.mp_state) {
5113 case KVM_MP_STATE_HALTED:
d7690175 5114 vcpu->arch.mp_state =
09cec754
GN		 5115 KVM_MP_STATE_RUNNABLE;
5116 case KVM_MP_STATE_RUNNABLE:
5117 break;
5118 case KVM_MP_STATE_SIPI_RECEIVED:
5119 default:
5120 r = -EINTR;
5121 break;
5122 }
5123 }
d7690175
MT		 5124 }
5125
09cec754
GN		 5126 if (r <= 0)
5127 break;
5128
5129 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5130 if (kvm_cpu_has_pending_timer(vcpu))
5131 kvm_inject_pending_timer_irqs(vcpu);
5132
851ba692 5133 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5134 r = -EINTR;
851ba692 5135 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5136 ++vcpu->stat.request_irq_exits;
5137 }
5138 if (signal_pending(current)) {
5139 r = -EINTR;
851ba692 5140 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5141 ++vcpu->stat.signal_exits;
5142 }
5143 if (need_resched()) {
f656ce01 5144 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5145 kvm_resched(vcpu);
f656ce01 5146 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5147 }
b6c7a5dc
HB		 5148 }
5149
f656ce01 5150 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5151
b93463aa
AK		 5152 vapic_exit(vcpu);
5153
b6c7a5dc
HB		 5154 return r;
5155}
5156
5157int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5158{
5159 int r;
5160 sigset_t sigsaved;
5161
ac9f6dc0
AK		 5162 if (vcpu->sigset_active)
5163 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5164
a4535290 5165 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5166 kvm_vcpu_block(vcpu);
d7690175 5167 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5168 r = -EAGAIN;
5169 goto out;
b6c7a5dc
HB		 5170 }
5171
b6c7a5dc
HB		 5172 /* re-sync apic's tpr */
5173 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5174 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5175
d2ddd1c4 5176 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5177 if (vcpu->mmio_needed) {
5178 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5179 vcpu->mmio_read_completed = 1;
5180 vcpu->mmio_needed = 0;
b6c7a5dc 5181 }
f656ce01 5182 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5183 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5184 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5185 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5186 r = 0;
5187 goto out;
5188 }
5189 }
5fdbf976
MT		 5190 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5191 kvm_register_write(vcpu, VCPU_REGS_RAX,
5192 kvm_run->hypercall.ret);
b6c7a5dc 5193
851ba692 5194 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5195
5196out:
f1d86e46 5197 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5198 if (vcpu->sigset_active)
5199 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5200
b6c7a5dc
HB		 5201 return r;
5202}
5203
5204int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5205{
5fdbf976
MT		 5206 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5207 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5208 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5209 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5210 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5211 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5212 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5213 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5214#ifdef CONFIG_X86_64
5fdbf976
MT		 5215 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5216 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5217 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5218 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5219 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5220 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5221 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5222 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5223#endif
5224
5fdbf976 5225 regs->rip = kvm_rip_read(vcpu);
91586a3b 5226 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5227
b6c7a5dc
HB		 5228 return 0;
5229}
5230
5231int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5232{
5fdbf976
MT		 5233 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5234 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5235 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5236 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5237 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5238 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5239 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5240 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5241#ifdef CONFIG_X86_64
5fdbf976
MT		 5242 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5243 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5244 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5245 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5246 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5247 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5248 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5249 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5250#endif
5251
5fdbf976 5252 kvm_rip_write(vcpu, regs->rip);
91586a3b 5253 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5254
b4f14abd
JK		 5255 vcpu->arch.exception.pending = false;
5256
b6c7a5dc
HB		 5257 return 0;
5258}
5259
b6c7a5dc
HB		 5260void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5261{
5262 struct kvm_segment cs;
5263
3e6e0aab 5264 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5265 *db = cs.db;
5266 *l = cs.l;
5267}
5268EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5269
5270int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5271 struct kvm_sregs *sregs)
5272{
89a27f4d 5273 struct desc_ptr dt;
b6c7a5dc 5274
3e6e0aab
GT		 5275 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5276 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5277 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5278 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5279 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5280 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5281
3e6e0aab
GT		 5282 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5283 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5284
5285 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5286 sregs->idt.limit = dt.size;
5287 sregs->idt.base = dt.address;
b6c7a5dc 5288 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5289 sregs->gdt.limit = dt.size;
5290 sregs->gdt.base = dt.address;
b6c7a5dc 5291
4d4ec087 5292 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5293 sregs->cr2 = vcpu->arch.cr2;
5294 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5295 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5296 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5297 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5298 sregs->apic_base = kvm_get_apic_base(vcpu);
5299
923c61bb 5300 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5301
36752c9b 5302 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5303 set_bit(vcpu->arch.interrupt.nr,
5304 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5305
b6c7a5dc
HB		 5306 return 0;
5307}
5308
62d9f0db
MT		 5309int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5310 struct kvm_mp_state *mp_state)
5311{
62d9f0db 5312 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5313 return 0;
5314}
5315
5316int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5317 struct kvm_mp_state *mp_state)
5318{
62d9f0db 5319 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5320 return 0;
5321}
5322
e269fb21
JK		 5323int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5324 bool has_error_code, u32 error_code)
b6c7a5dc 5325{
4d2179e1 5326 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5327 int ret;
e01c2426 5328
8ec4722d 5329 init_emulate_ctxt(vcpu);
c697518a 5330
9aabc88f 5331 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5332 tss_selector, reason, has_error_code,
5333 error_code);
c697518a 5334
c697518a 5335 if (ret)
19d04437 5336 return EMULATE_FAIL;
37817f29 5337
4d2179e1 5338 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5339 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5340 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5341 return EMULATE_DONE;
37817f29
IE		 5342}
5343EXPORT_SYMBOL_GPL(kvm_task_switch);
5344
b6c7a5dc
HB		 5345int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5346 struct kvm_sregs *sregs)
5347{
5348 int mmu_reset_needed = 0;
923c61bb 5349 int pending_vec, max_bits;
89a27f4d 5350 struct desc_ptr dt;
b6c7a5dc 5351
89a27f4d
GN		 5352 dt.size = sregs->idt.limit;
5353 dt.address = sregs->idt.base;
b6c7a5dc 5354 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5355 dt.size = sregs->gdt.limit;
5356 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5357 kvm_x86_ops->set_gdt(vcpu, &dt);
5358
ad312c7c
ZX		 5359 vcpu->arch.cr2 = sregs->cr2;
5360 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5361 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5362
2d3ad1f4 5363 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5364
f6801dff 5365 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5366 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5367 kvm_set_apic_base(vcpu, sregs->apic_base);
5368
4d4ec087 5369 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5370 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5371 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5372
fc78f519 5373 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5374 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5375 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5376 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5377 mmu_reset_needed = 1;
5378 }
b6c7a5dc
HB		 5379
5380 if (mmu_reset_needed)
5381 kvm_mmu_reset_context(vcpu);
5382
923c61bb
GN		 5383 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5384 pending_vec = find_first_bit(
5385 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5386 if (pending_vec < max_bits) {
66fd3f7f 5387 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5388 pr_debug("Set back pending irq %d\n", pending_vec);
5389 if (irqchip_in_kernel(vcpu->kvm))
5390 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5391 }
5392
3e6e0aab
GT		 5393 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5394 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5395 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5396 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5397 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5398 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5399
3e6e0aab
GT		 5400 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5401 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5402
5f0269f5
ME		 5403 update_cr8_intercept(vcpu);
5404
9c3e4aab 5405 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5406 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5407 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5408 !is_protmode(vcpu))
9c3e4aab
MT		 5409 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5410
b6c7a5dc
HB		 5411 return 0;
5412}
5413
d0bfb940
JK		 5414int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5415 struct kvm_guest_debug *dbg)
b6c7a5dc 5416{
355be0b9 5417 unsigned long rflags;
ae675ef0 5418 int i, r;
b6c7a5dc 5419
4f926bf2
JK		 5420 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5421 r = -EBUSY;
5422 if (vcpu->arch.exception.pending)
2122ff5e 5423 goto out;
4f926bf2
JK		 5424 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5425 kvm_queue_exception(vcpu, DB_VECTOR);
5426 else
5427 kvm_queue_exception(vcpu, BP_VECTOR);
5428 }
5429
91586a3b
JK		 5430 /*
5431 * Read rflags as long as potentially injected trace flags are still
5432 * filtered out.
5433 */
5434 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5435
5436 vcpu->guest_debug = dbg->control;
5437 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5438 vcpu->guest_debug = 0;
5439
5440 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5441 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5442 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5443 vcpu->arch.switch_db_regs =
5444 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5445 } else {
5446 for (i = 0; i < KVM_NR_DB_REGS; i++)
5447 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5448 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5449 }
5450
f92653ee
JK		 5451 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5452 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5453 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5454
91586a3b
JK		 5455 /*
5456 * Trigger an rflags update that will inject or remove the trace
5457 * flags.
5458 */
5459 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5460
355be0b9 5461 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5462
4f926bf2 5463 r = 0;
d0bfb940 5464
2122ff5e 5465out:
b6c7a5dc
HB		 5466
5467 return r;
5468}
5469
8b006791
ZX		 5470/*
5471 * Translate a guest virtual address to a guest physical address.
5472 */
5473int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5474 struct kvm_translation *tr)
5475{
5476 unsigned long vaddr = tr->linear_address;
5477 gpa_t gpa;
f656ce01 5478 int idx;
8b006791 5479
f656ce01 5480 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5481 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5482 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5483 tr->physical_address = gpa;
5484 tr->valid = gpa != UNMAPPED_GVA;
5485 tr->writeable = 1;
5486 tr->usermode = 0;
8b006791
ZX		 5487
5488 return 0;
5489}
5490
d0752060
HB		 5491int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5492{
98918833
SY		 5493 struct i387_fxsave_struct *fxsave =
5494 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5495
d0752060
HB		 5496 memcpy(fpu->fpr, fxsave->st_space, 128);
5497 fpu->fcw = fxsave->cwd;
5498 fpu->fsw = fxsave->swd;
5499 fpu->ftwx = fxsave->twd;
5500 fpu->last_opcode = fxsave->fop;
5501 fpu->last_ip = fxsave->rip;
5502 fpu->last_dp = fxsave->rdp;
5503 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5504
d0752060
HB		 5505 return 0;
5506}
5507
5508int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5509{
98918833
SY		 5510 struct i387_fxsave_struct *fxsave =
5511 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5512
d0752060
HB		 5513 memcpy(fxsave->st_space, fpu->fpr, 128);
5514 fxsave->cwd = fpu->fcw;
5515 fxsave->swd = fpu->fsw;
5516 fxsave->twd = fpu->ftwx;
5517 fxsave->fop = fpu->last_opcode;
5518 fxsave->rip = fpu->last_ip;
5519 fxsave->rdp = fpu->last_dp;
5520 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5521
d0752060
HB		 5522 return 0;
5523}
5524
10ab25cd 5525int fx_init(struct kvm_vcpu *vcpu)
d0752060 5526{
10ab25cd
JK		 5527 int err;
5528
5529 err = fpu_alloc(&vcpu->arch.guest_fpu);
5530 if (err)
5531 return err;
5532
98918833 5533 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5534
2acf923e
DC		 5535 /*
5536 * Ensure guest xcr0 is valid for loading
5537 */
5538 vcpu->arch.xcr0 = XSTATE_FP;
5539
ad312c7c 5540 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5541
5542 return 0;
d0752060
HB		 5543}
5544EXPORT_SYMBOL_GPL(fx_init);
5545
98918833
SY		 5546static void fx_free(struct kvm_vcpu *vcpu)
5547{
5548 fpu_free(&vcpu->arch.guest_fpu);
5549}
5550
d0752060
HB		 5551void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5552{
2608d7a1 5553 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5554 return;
5555
2acf923e
DC		 5556 /*
5557 * Restore all possible states in the guest,
5558 * and assume host would use all available bits.
5559 * Guest xcr0 would be loaded later.
5560 */
5561 kvm_put_guest_xcr0(vcpu);
d0752060 5562 vcpu->guest_fpu_loaded = 1;
7cf30855 5563 unlazy_fpu(current);
98918833 5564 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5565 trace_kvm_fpu(1);
d0752060 5566}
d0752060
HB		 5567
5568void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5569{
2acf923e
DC		 5570 kvm_put_guest_xcr0(vcpu);
5571
d0752060
HB		 5572 if (!vcpu->guest_fpu_loaded)
5573 return;
5574
5575 vcpu->guest_fpu_loaded = 0;
98918833 5576 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5577 ++vcpu->stat.fpu_reload;
a8eeb04a 5578 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5579 trace_kvm_fpu(0);
d0752060 5580}
e9b11c17
ZX		 5581
5582void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5583{
7f1ea208
JR		 5584 if (vcpu->arch.time_page) {
5585 kvm_release_page_dirty(vcpu->arch.time_page);
5586 vcpu->arch.time_page = NULL;
5587 }
5588
f5f48ee1 5589 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5590 fx_free(vcpu);
e9b11c17
ZX		 5591 kvm_x86_ops->vcpu_free(vcpu);
5592}
5593
5594struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5595 unsigned int id)
5596{
6755bae8
ZA		 5597 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5598 printk_once(KERN_WARNING
5599 "kvm: SMP vm created on host with unstable TSC; "
5600 "guest TSC will not be reliable\n");
26e5215f
AK		 5601 return kvm_x86_ops->vcpu_create(kvm, id);
5602}
e9b11c17 5603
26e5215f
AK		 5604int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5605{
5606 int r;
e9b11c17 5607
0bed3b56 5608 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5609 vcpu_load(vcpu);
5610 r = kvm_arch_vcpu_reset(vcpu);
5611 if (r == 0)
5612 r = kvm_mmu_setup(vcpu);
5613 vcpu_put(vcpu);
5614 if (r < 0)
5615 goto free_vcpu;
5616
26e5215f 5617 return 0;
e9b11c17
ZX		 5618free_vcpu:
5619 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5620 return r;
e9b11c17
ZX		 5621}
5622
d40ccc62 5623void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5624{
5625 vcpu_load(vcpu);
5626 kvm_mmu_unload(vcpu);
5627 vcpu_put(vcpu);
5628
98918833 5629 fx_free(vcpu);
e9b11c17
ZX		 5630 kvm_x86_ops->vcpu_free(vcpu);
5631}
5632
5633int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5634{
448fa4a9
JK		 5635 vcpu->arch.nmi_pending = false;
5636 vcpu->arch.nmi_injected = false;
5637
42dbaa5a
JK		 5638 vcpu->arch.switch_db_regs = 0;
5639 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5640 vcpu->arch.dr6 = DR6_FIXED_1;
5641 vcpu->arch.dr7 = DR7_FIXED_1;
5642
e9b11c17
ZX		 5643 return kvm_x86_ops->vcpu_reset(vcpu);
5644}
5645
10474ae8 5646int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5647{
ca84d1a2
ZA		 5648 struct kvm *kvm;
5649 struct kvm_vcpu *vcpu;
5650 int i;
5651
18863bdd 5652 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5653 list_for_each_entry(kvm, &vm_list, vm_list)
5654 kvm_for_each_vcpu(i, vcpu, kvm)
5655 if (vcpu->cpu == smp_processor_id())
5656 kvm_request_guest_time_update(vcpu);
10474ae8 5657 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5658}
5659
5660void kvm_arch_hardware_disable(void *garbage)
5661{
5662 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5663 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5664}
5665
5666int kvm_arch_hardware_setup(void)
5667{
5668 return kvm_x86_ops->hardware_setup();
5669}
5670
5671void kvm_arch_hardware_unsetup(void)
5672{
5673 kvm_x86_ops->hardware_unsetup();
5674}
5675
5676void kvm_arch_check_processor_compat(void *rtn)
5677{
5678 kvm_x86_ops->check_processor_compatibility(rtn);
5679}
5680
5681int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5682{
5683 struct page *page;
5684 struct kvm *kvm;
5685 int r;
5686
5687 BUG_ON(vcpu->kvm == NULL);
5688 kvm = vcpu->kvm;
5689
9aabc88f 5690 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5691 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5692 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5693 vcpu->arch.mmu.translate_gpa = translate_gpa;
c5af89b6 5694 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5695 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5696 else
a4535290 5697 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5698
5699 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5700 if (!page) {
5701 r = -ENOMEM;
5702 goto fail;
5703 }
ad312c7c 5704 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5705
5706 r = kvm_mmu_create(vcpu);
5707 if (r < 0)
5708 goto fail_free_pio_data;
5709
5710 if (irqchip_in_kernel(kvm)) {
5711 r = kvm_create_lapic(vcpu);
5712 if (r < 0)
5713 goto fail_mmu_destroy;
5714 }
5715
890ca9ae
HY		 5716 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5717 GFP_KERNEL);
5718 if (!vcpu->arch.mce_banks) {
5719 r = -ENOMEM;
443c39bc 5720 goto fail_free_lapic;
890ca9ae
HY		 5721 }
5722 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5723
f5f48ee1
SY		 5724 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5725 goto fail_free_mce_banks;
5726
e9b11c17 5727 return 0;
f5f48ee1
SY		 5728fail_free_mce_banks:
5729 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5730fail_free_lapic:
5731 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5732fail_mmu_destroy:
5733 kvm_mmu_destroy(vcpu);
5734fail_free_pio_data:
ad312c7c 5735 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5736fail:
5737 return r;
5738}
5739
5740void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5741{
f656ce01
MT		 5742 int idx;
5743
36cb93fd 5744 kfree(vcpu->arch.mce_banks);
e9b11c17 5745 kvm_free_lapic(vcpu);
f656ce01 5746 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5747 kvm_mmu_destroy(vcpu);
f656ce01 5748 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5749 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5750}
d19a9cd2
ZX		 5751
5752struct kvm *kvm_arch_create_vm(void)
5753{
5754 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5755
5756 if (!kvm)
5757 return ERR_PTR(-ENOMEM);
5758
f05e70ac 5759 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5760 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5761
5550af4d
SY		 5762 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5763 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5764
99e3e30a
ZA		 5765 spin_lock_init(&kvm->arch.tsc_write_lock);
5766
d19a9cd2
ZX		 5767 return kvm;
5768}
5769
5770static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5771{
5772 vcpu_load(vcpu);
5773 kvm_mmu_unload(vcpu);
5774 vcpu_put(vcpu);
5775}
5776
5777static void kvm_free_vcpus(struct kvm *kvm)
5778{
5779 unsigned int i;
988a2cae 5780 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5781
5782 /*
5783 * Unpin any mmu pages first.
5784 */
988a2cae
GN		 5785 kvm_for_each_vcpu(i, vcpu, kvm)
5786 kvm_unload_vcpu_mmu(vcpu);
5787 kvm_for_each_vcpu(i, vcpu, kvm)
5788 kvm_arch_vcpu_free(vcpu);
5789
5790 mutex_lock(&kvm->lock);
5791 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5792 kvm->vcpus[i] = NULL;
d19a9cd2 5793
988a2cae
GN		 5794 atomic_set(&kvm->online_vcpus, 0);
5795 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5796}
5797
ad8ba2cd
SY		 5798void kvm_arch_sync_events(struct kvm *kvm)
5799{
ba4cef31 5800 kvm_free_all_assigned_devices(kvm);
aea924f6 5801 kvm_free_pit(kvm);
ad8ba2cd
SY		 5802}
5803
d19a9cd2
ZX		 5804void kvm_arch_destroy_vm(struct kvm *kvm)
5805{
6eb55818 5806 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5807 kfree(kvm->arch.vpic);
5808 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5809 kvm_free_vcpus(kvm);
5810 kvm_free_physmem(kvm);
3d45830c
AK		 5811 if (kvm->arch.apic_access_page)
5812 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5813 if (kvm->arch.ept_identity_pagetable)
5814 put_page(kvm->arch.ept_identity_pagetable);
64749204 5815 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5816 kfree(kvm);
5817}
0de10343 5818
f7784b8e
MT		 5819int kvm_arch_prepare_memory_region(struct kvm *kvm,
5820 struct kvm_memory_slot *memslot,
0de10343 5821 struct kvm_memory_slot old,
f7784b8e 5822 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5823 int user_alloc)
5824{
f7784b8e 5825 int npages = memslot->npages;
7ac77099
AK		 5826 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5827
5828 /* Prevent internal slot pages from being moved by fork()/COW. */
5829 if (memslot->id >= KVM_MEMORY_SLOTS)
5830 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5831
5832 /*To keep backward compatibility with older userspace,
5833 *x86 needs to hanlde !user_alloc case.
5834 */
5835 if (!user_alloc) {
5836 if (npages && !old.rmap) {
604b38ac
AA		 5837 unsigned long userspace_addr;
5838
72dc67a6 5839 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5840 userspace_addr = do_mmap(NULL, 0,
5841 npages * PAGE_SIZE,
5842 PROT_READ | PROT_WRITE,
7ac77099 5843 map_flags,
604b38ac 5844 0);
72dc67a6 5845 up_write(&current->mm->mmap_sem);
0de10343 5846
604b38ac
AA		 5847 if (IS_ERR((void *)userspace_addr))
5848 return PTR_ERR((void *)userspace_addr);
5849
604b38ac 5850 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5851 }
5852 }
5853
f7784b8e
MT		 5854
5855 return 0;
5856}
5857
5858void kvm_arch_commit_memory_region(struct kvm *kvm,
5859 struct kvm_userspace_memory_region *mem,
5860 struct kvm_memory_slot old,
5861 int user_alloc)
5862{
5863
5864 int npages = mem->memory_size >> PAGE_SHIFT;
5865
5866 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5867 int ret;
5868
5869 down_write(&current->mm->mmap_sem);
5870 ret = do_munmap(current->mm, old.userspace_addr,
5871 old.npages * PAGE_SIZE);
5872 up_write(&current->mm->mmap_sem);
5873 if (ret < 0)
5874 printk(KERN_WARNING
5875 "kvm_vm_ioctl_set_memory_region: "
5876 "failed to munmap memory\n");
5877 }
5878
7c8a83b7 5879 spin_lock(&kvm->mmu_lock);
f05e70ac 5880 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5881 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5882 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5883 }
5884
5885 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5886 spin_unlock(&kvm->mmu_lock);
0de10343 5887}
1d737c8a 5888
34d4cb8f
MT		 5889void kvm_arch_flush_shadow(struct kvm *kvm)
5890{
5891 kvm_mmu_zap_all(kvm);
8986ecc0 5892 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5893}
5894
1d737c8a
ZX		 5895int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5896{
a4535290 5897 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5898 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5899 || vcpu->arch.nmi_pending ||
5900 (kvm_arch_interrupt_allowed(vcpu) &&
5901 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5902}
5736199a 5903
5736199a
ZX		 5904void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5905{
32f88400
MT		 5906 int me;
5907 int cpu = vcpu->cpu;
5736199a
ZX		 5908
5909 if (waitqueue_active(&vcpu->wq)) {
5910 wake_up_interruptible(&vcpu->wq);
5911 ++vcpu->stat.halt_wakeup;
5912 }
32f88400
MT		 5913
5914 me = get_cpu();
5915 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5916 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5917 smp_send_reschedule(cpu);
e9571ed5 5918 put_cpu();
5736199a 5919}
78646121
GN		 5920
5921int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5922{
5923 return kvm_x86_ops->interrupt_allowed(vcpu);
5924}
229456fc 5925
f92653ee
JK		 5926bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5927{
5928 unsigned long current_rip = kvm_rip_read(vcpu) +
5929 get_segment_base(vcpu, VCPU_SREG_CS);
5930
5931 return current_rip == linear_rip;
5932}
5933EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5934
94fe45da
JK		 5935unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5936{
5937 unsigned long rflags;
5938
5939 rflags = kvm_x86_ops->get_rflags(vcpu);
5940 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5941 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5942 return rflags;
5943}
5944EXPORT_SYMBOL_GPL(kvm_get_rflags);
5945
5946void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5947{
5948 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5949 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5950 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5951 kvm_x86_ops->set_rflags(vcpu, rflags);
5952}
5953EXPORT_SYMBOL_GPL(kvm_set_rflags);
5954
229456fc
MT		 5955EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5956EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5957EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5958EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5959EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5960EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5961EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5962EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5963EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5964EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5965EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5966EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)