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vmstat: User per cpu atomics to avoid interrupt disable / enable
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
5854dbca 76#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
3842d135
AK		 287 kvm_make_request(KVM_REQ_EVENT, vcpu);
288
3fd28fce
ED		 289 if (!vcpu->arch.exception.pending) {
290 queue:
291 vcpu->arch.exception.pending = true;
292 vcpu->arch.exception.has_error_code = has_error;
293 vcpu->arch.exception.nr = nr;
294 vcpu->arch.exception.error_code = error_code;
3f0fd292 295 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 296 return;
297 }
298
299 /* to check exception */
300 prev_nr = vcpu->arch.exception.nr;
301 if (prev_nr == DF_VECTOR) {
302 /* triple fault -> shutdown */
a8eeb04a 303 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 304 return;
305 }
306 class1 = exception_class(prev_nr);
307 class2 = exception_class(nr);
308 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
309 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
310 /* generate double fault per SDM Table 5-5 */
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = true;
313 vcpu->arch.exception.nr = DF_VECTOR;
314 vcpu->arch.exception.error_code = 0;
315 } else
316 /* replace previous exception with a new one in a hope
317 that instruction re-execution will regenerate lost
318 exception */
319 goto queue;
320}
321
298101da
AK		 322void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
323{
ce7ddec4 324 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 325}
326EXPORT_SYMBOL_GPL(kvm_queue_exception);
327
ce7ddec4
JR		 328void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
330 kvm_multiple_exception(vcpu, nr, false, 0, true);
331}
332EXPORT_SYMBOL_GPL(kvm_requeue_exception);
333
8df25a32 334void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 335{
8df25a32
JR		 336 unsigned error_code = vcpu->arch.fault.error_code;
337
c3c91fee 338 ++vcpu->stat.pf_guest;
8df25a32 339 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 340 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
341}
342
d4f8cf66
JR		 343void kvm_propagate_fault(struct kvm_vcpu *vcpu)
344{
0959ffac 345 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 346 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
347 else
348 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 349
350 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 351}
352
3419ffc8
SY		 353void kvm_inject_nmi(struct kvm_vcpu *vcpu)
354{
3842d135 355 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 356 vcpu->arch.nmi_pending = 1;
357}
358EXPORT_SYMBOL_GPL(kvm_inject_nmi);
359
298101da
AK		 360void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
361{
ce7ddec4 362 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 363}
364EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
365
ce7ddec4
JR		 366void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
367{
368 kvm_multiple_exception(vcpu, nr, true, error_code, true);
369}
370EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
371
0a79b009
AK		 372/*
373 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
374 * a #GP and return false.
375 */
376bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 377{
0a79b009
AK		 378 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
379 return true;
380 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
381 return false;
298101da 382}
0a79b009 383EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 384
ec92fe44
JR		 385/*
386 * This function will be used to read from the physical memory of the currently
387 * running guest. The difference to kvm_read_guest_page is that this function
388 * can read from guest physical or from the guest's guest physical memory.
389 */
390int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
391 gfn_t ngfn, void *data, int offset, int len,
392 u32 access)
393{
394 gfn_t real_gfn;
395 gpa_t ngpa;
396
397 ngpa = gfn_to_gpa(ngfn);
398 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
399 if (real_gfn == UNMAPPED_GVA)
400 return -EFAULT;
401
402 real_gfn = gpa_to_gfn(real_gfn);
403
404 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
405}
406EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
407
3d06b8bf
JR		 408int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
409 void *data, int offset, int len, u32 access)
410{
411 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
412 data, offset, len, access);
413}
414
a03490ed
CO		 415/*
416 * Load the pae pdptrs. Return true is they are all valid.
417 */
ff03a073 418int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 419{
420 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
421 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
422 int i;
423 int ret;
ff03a073 424 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 425
ff03a073
JR		 426 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
427 offset * sizeof(u64), sizeof(pdpte),
428 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 429 if (ret < 0) {
430 ret = 0;
431 goto out;
432 }
433 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 434 if (is_present_gpte(pdpte[i]) &&
20c466b5 435 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 436 ret = 0;
437 goto out;
438 }
439 }
440 ret = 1;
441
ff03a073 442 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 443 __set_bit(VCPU_EXREG_PDPTR,
444 (unsigned long *)&vcpu->arch.regs_avail);
445 __set_bit(VCPU_EXREG_PDPTR,
446 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 447out:
a03490ed
CO		 448
449 return ret;
450}
cc4b6871 451EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 452
d835dfec
AK		 453static bool pdptrs_changed(struct kvm_vcpu *vcpu)
454{
ff03a073 455 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 456 bool changed = true;
3d06b8bf
JR		 457 int offset;
458 gfn_t gfn;
d835dfec
AK		 459 int r;
460
461 if (is_long_mode(vcpu) || !is_pae(vcpu))
462 return false;
463
6de4f3ad
AK		 464 if (!test_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail))
466 return true;
467
3d06b8bf
JR		 468 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
469 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
470 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
471 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 472 if (r < 0)
473 goto out;
ff03a073 474 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 475out:
d835dfec
AK		 476
477 return changed;
478}
479
49a9b07e 480int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 481{
aad82703
SY		 482 unsigned long old_cr0 = kvm_read_cr0(vcpu);
483 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
484 X86_CR0_CD | X86_CR0_NW;
485
f9a48e6a
AK		 486 cr0 |= X86_CR0_ET;
487
ab344828 488#ifdef CONFIG_X86_64
0f12244f
GN		 489 if (cr0 & 0xffffffff00000000UL)
490 return 1;
ab344828
GN		 491#endif
492
493 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 494
0f12244f
GN		 495 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
496 return 1;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
499 return 1;
a03490ed
CO		 500
501 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
502#ifdef CONFIG_X86_64
f6801dff 503 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 504 int cs_db, cs_l;
505
0f12244f
GN		 506 if (!is_pae(vcpu))
507 return 1;
a03490ed 508 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 509 if (cs_l)
510 return 1;
a03490ed
CO		 511 } else
512#endif
ff03a073
JR		 513 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
514 vcpu->arch.cr3))
0f12244f 515 return 1;
a03490ed
CO		 516 }
517
518 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 519
aad82703
SY		 520 if ((cr0 ^ old_cr0) & update_bits)
521 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 522 return 0;
523}
2d3ad1f4 524EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 525
2d3ad1f4 526void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 527{
49a9b07e 528 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 531
2acf923e
DC		 532int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
533{
534 u64 xcr0;
535
536 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
537 if (index != XCR_XFEATURE_ENABLED_MASK)
538 return 1;
539 xcr0 = xcr;
540 if (kvm_x86_ops->get_cpl(vcpu) != 0)
541 return 1;
542 if (!(xcr0 & XSTATE_FP))
543 return 1;
544 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
545 return 1;
546 if (xcr0 & ~host_xcr0)
547 return 1;
548 vcpu->arch.xcr0 = xcr0;
549 vcpu->guest_xcr0_loaded = 0;
550 return 0;
551}
552
553int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 if (__kvm_set_xcr(vcpu, index, xcr)) {
556 kvm_inject_gp(vcpu, 0);
557 return 1;
558 }
559 return 0;
560}
561EXPORT_SYMBOL_GPL(kvm_set_xcr);
562
563static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
564{
565 struct kvm_cpuid_entry2 *best;
566
567 best = kvm_find_cpuid_entry(vcpu, 1, 0);
568 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
569}
570
571static void update_cpuid(struct kvm_vcpu *vcpu)
572{
573 struct kvm_cpuid_entry2 *best;
574
575 best = kvm_find_cpuid_entry(vcpu, 1, 0);
576 if (!best)
577 return;
578
579 /* Update OSXSAVE bit */
580 if (cpu_has_xsave && best->function == 0x1) {
581 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
582 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
583 best->ecx |= bit(X86_FEATURE_OSXSAVE);
584 }
585}
586
a83b29c6 587int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 588{
fc78f519 589 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 590 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
591
0f12244f
GN		 592 if (cr4 & CR4_RESERVED_BITS)
593 return 1;
a03490ed 594
2acf923e
DC		 595 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
596 return 1;
597
a03490ed 598 if (is_long_mode(vcpu)) {
0f12244f
GN		 599 if (!(cr4 & X86_CR4_PAE))
600 return 1;
a2edf57f
AK		 601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 604 return 1;
605
606 if (cr4 & X86_CR4_VMXE)
607 return 1;
a03490ed 608
a03490ed 609 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 610
aad82703
SY		 611 if ((cr4 ^ old_cr4) & pdptr_bits)
612 kvm_mmu_reset_context(vcpu);
0f12244f 613
2acf923e
DC		 614 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
615 update_cpuid(vcpu);
616
0f12244f
GN		 617 return 0;
618}
2d3ad1f4 619EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 620
2390218b 621int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 622{
ad312c7c 623 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 624 kvm_mmu_sync_roots(vcpu);
d835dfec 625 kvm_mmu_flush_tlb(vcpu);
0f12244f 626 return 0;
d835dfec
AK		 627 }
628
a03490ed 629 if (is_long_mode(vcpu)) {
0f12244f
GN		 630 if (cr3 & CR3_L_MODE_RESERVED_BITS)
631 return 1;
a03490ed
CO		 632 } else {
633 if (is_pae(vcpu)) {
0f12244f
GN		 634 if (cr3 & CR3_PAE_RESERVED_BITS)
635 return 1;
ff03a073
JR		 636 if (is_paging(vcpu) &&
637 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 638 return 1;
a03490ed
CO		 639 }
640 /*
641 * We don't check reserved bits in nonpae mode, because
642 * this isn't enforced, and VMware depends on this.
643 */
644 }
645
a03490ed
CO		 646 /*
647 * Does the new cr3 value map to physical memory? (Note, we
648 * catch an invalid cr3 even in real-mode, because it would
649 * cause trouble later on when we turn on paging anyway.)
650 *
651 * A real CPU would silently accept an invalid cr3 and would
652 * attempt to use it - with largely undefined (and often hard
653 * to debug) behavior on the guest side.
654 */
655 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 656 return 1;
657 vcpu->arch.cr3 = cr3;
658 vcpu->arch.mmu.new_cr3(vcpu);
659 return 0;
660}
2d3ad1f4 661EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 662
0f12244f 663int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 664{
0f12244f
GN		 665 if (cr8 & CR8_RESERVED_BITS)
666 return 1;
a03490ed
CO		 667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
669 else
ad312c7c 670 vcpu->arch.cr8 = cr8;
0f12244f
GN		 671 return 0;
672}
673
674void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675{
676 if (__kvm_set_cr8(vcpu, cr8))
677 kvm_inject_gp(vcpu, 0);
a03490ed 678}
2d3ad1f4 679EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 680
2d3ad1f4 681unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 682{
683 if (irqchip_in_kernel(vcpu->kvm))
684 return kvm_lapic_get_cr8(vcpu);
685 else
ad312c7c 686 return vcpu->arch.cr8;
a03490ed 687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 689
338dbc97 690static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 691{
692 switch (dr) {
693 case 0 ... 3:
694 vcpu->arch.db[dr] = val;
695 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
696 vcpu->arch.eff_db[dr] = val;
697 break;
698 case 4:
338dbc97
GN		 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
700 return 1; /* #UD */
020df079
GN		 701 /* fall through */
702 case 6:
338dbc97
GN		 703 if (val & 0xffffffff00000000ULL)
704 return -1; /* #GP */
020df079
GN		 705 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
706 break;
707 case 5:
338dbc97
GN		 708 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
709 return 1; /* #UD */
020df079
GN		 710 /* fall through */
711 default: /* 7 */
338dbc97
GN		 712 if (val & 0xffffffff00000000ULL)
713 return -1; /* #GP */
020df079
GN		 714 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
715 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
716 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
717 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
718 }
719 break;
720 }
721
722 return 0;
723}
338dbc97
GN		 724
725int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
726{
727 int res;
728
729 res = __kvm_set_dr(vcpu, dr, val);
730 if (res > 0)
731 kvm_queue_exception(vcpu, UD_VECTOR);
732 else if (res < 0)
733 kvm_inject_gp(vcpu, 0);
734
735 return res;
736}
020df079
GN		 737EXPORT_SYMBOL_GPL(kvm_set_dr);
738
338dbc97 739static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 740{
741 switch (dr) {
742 case 0 ... 3:
743 *val = vcpu->arch.db[dr];
744 break;
745 case 4:
338dbc97 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 747 return 1;
020df079
GN		 748 /* fall through */
749 case 6:
750 *val = vcpu->arch.dr6;
751 break;
752 case 5:
338dbc97 753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 754 return 1;
020df079
GN		 755 /* fall through */
756 default: /* 7 */
757 *val = vcpu->arch.dr7;
758 break;
759 }
760
761 return 0;
762}
338dbc97
GN		 763
764int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
765{
766 if (_kvm_get_dr(vcpu, dr, val)) {
767 kvm_queue_exception(vcpu, UD_VECTOR);
768 return 1;
769 }
770 return 0;
771}
020df079
GN		 772EXPORT_SYMBOL_GPL(kvm_get_dr);
773
043405e1
CO		 774/*
775 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
776 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
777 *
778 * This list is modified at module load time to reflect the
e3267cbb
GC		 779 * capabilities of the host cpu. This capabilities test skips MSRs that are
780 * kvm-specific. Those are put in the beginning of the list.
043405e1 781 */
e3267cbb 782
11c6bffa 783#define KVM_SAVE_MSRS_BEGIN 7
043405e1 784static u32 msrs_to_save[] = {
e3267cbb 785 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 786 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 787 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 788 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 789 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 790 MSR_STAR,
043405e1
CO		 791#ifdef CONFIG_X86_64
792 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
793#endif
e90aa41e 794 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 795};
796
797static unsigned num_msrs_to_save;
798
799static u32 emulated_msrs[] = {
800 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 801 MSR_IA32_MCG_STATUS,
802 MSR_IA32_MCG_CTL,
043405e1
CO		 803};
804
b69e8cae 805static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 806{
aad82703
SY		 807 u64 old_efer = vcpu->arch.efer;
808
b69e8cae
RJ		 809 if (efer & efer_reserved_bits)
810 return 1;
15c4a640
CO		 811
812 if (is_paging(vcpu)
b69e8cae
RJ		 813 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
814 return 1;
15c4a640 815
1b2fd70c
AG		 816 if (efer & EFER_FFXSR) {
817 struct kvm_cpuid_entry2 *feat;
818
819 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 820 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
821 return 1;
1b2fd70c
AG		 822 }
823
d8017474
AG		 824 if (efer & EFER_SVME) {
825 struct kvm_cpuid_entry2 *feat;
826
827 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 828 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
829 return 1;
d8017474
AG		 830 }
831
15c4a640 832 efer &= ~EFER_LMA;
f6801dff 833 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 834
a3d204e2
SY		 835 kvm_x86_ops->set_efer(vcpu, efer);
836
9645bb56
AK		 837 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
838 kvm_mmu_reset_context(vcpu);
b69e8cae 839
aad82703
SY		 840 /* Update reserved bits */
841 if ((efer ^ old_efer) & EFER_NX)
842 kvm_mmu_reset_context(vcpu);
843
b69e8cae 844 return 0;
15c4a640
CO		 845}
846
f2b4b7dd
JR		 847void kvm_enable_efer_bits(u64 mask)
848{
849 efer_reserved_bits &= ~mask;
850}
851EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
852
853
15c4a640
CO		 854/*
855 * Writes msr value into into the appropriate "register".
856 * Returns 0 on success, non-0 otherwise.
857 * Assumes vcpu_load() was already called.
858 */
859int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
860{
861 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
862}
863
313a3dc7
CO		 864/*
865 * Adapt set_msr() to msr_io()'s calling convention
866 */
867static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
868{
869 return kvm_set_msr(vcpu, index, *data);
870}
871
18068523
GOC		 872static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
873{
9ed3c444
AK		 874 int version;
875 int r;
50d0a0f9 876 struct pvclock_wall_clock wc;
923de3cf 877 struct timespec boot;
18068523
GOC		 878
879 if (!wall_clock)
880 return;
881
9ed3c444
AK		 882 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
883 if (r)
884 return;
885
886 if (version & 1)
887 ++version; /* first time write, random junk */
888
889 ++version;
18068523 890
18068523
GOC		 891 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
892
50d0a0f9
GH		 893 /*
894 * The guest calculates current wall clock time by adding
34c238a1 895 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 896 * wall clock specified here. guest system time equals host
897 * system time for us, thus we must fill in host boot time here.
898 */
923de3cf 899 getboottime(&boot);
50d0a0f9
GH		 900
901 wc.sec = boot.tv_sec;
902 wc.nsec = boot.tv_nsec;
903 wc.version = version;
18068523
GOC		 904
905 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
906
907 version++;
908 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 909}
910
50d0a0f9
GH		 911static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
912{
913 uint32_t quotient, remainder;
914
915 /* Don't try to replace with do_div(), this one calculates
916 * "(dividend << 32) / divisor" */
917 __asm__ ( "divl %4"
918 : "=a" (quotient), "=d" (remainder)
919 : "0" (0), "1" (dividend), "r" (divisor) );
920 return quotient;
921}
922
5f4e3f88
ZA		 923static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
924 s8 *pshift, u32 *pmultiplier)
50d0a0f9 925{
5f4e3f88 926 uint64_t scaled64;
50d0a0f9
GH		 927 int32_t shift = 0;
928 uint64_t tps64;
929 uint32_t tps32;
930
5f4e3f88
ZA		 931 tps64 = base_khz * 1000LL;
932 scaled64 = scaled_khz * 1000LL;
50933623 933 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 934 tps64 >>= 1;
935 shift--;
936 }
937
938 tps32 = (uint32_t)tps64;
50933623
JK		 939 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
940 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 941 scaled64 >>= 1;
942 else
943 tps32 <<= 1;
50d0a0f9
GH		 944 shift++;
945 }
946
5f4e3f88
ZA		 947 *pshift = shift;
948 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 949
5f4e3f88
ZA		 950 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
951 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 952}
953
759379dd
ZA		 954static inline u64 get_kernel_ns(void)
955{
956 struct timespec ts;
957
958 WARN_ON(preemptible());
959 ktime_get_ts(&ts);
960 monotonic_to_bootbased(&ts);
961 return timespec_to_ns(&ts);
50d0a0f9
GH		 962}
963
c8076604 964static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 965unsigned long max_tsc_khz;
c8076604 966
8cfdc000
ZA		 967static inline int kvm_tsc_changes_freq(void)
968{
969 int cpu = get_cpu();
970 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
971 cpufreq_quick_get(cpu) != 0;
972 put_cpu();
973 return ret;
974}
975
759379dd
ZA		 976static inline u64 nsec_to_cycles(u64 nsec)
977{
217fc9cf
AK		 978 u64 ret;
979
759379dd
ZA		 980 WARN_ON(preemptible());
981 if (kvm_tsc_changes_freq())
982 printk_once(KERN_WARNING
983 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 984 ret = nsec * __get_cpu_var(cpu_tsc_khz);
985 do_div(ret, USEC_PER_SEC);
986 return ret;
759379dd
ZA		 987}
988
c285545f
ZA		 989static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
990{
991 /* Compute a scale to convert nanoseconds in TSC cycles */
992 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
993 &kvm->arch.virtual_tsc_shift,
994 &kvm->arch.virtual_tsc_mult);
995 kvm->arch.virtual_tsc_khz = this_tsc_khz;
996}
997
998static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
999{
1000 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1001 vcpu->kvm->arch.virtual_tsc_mult,
1002 vcpu->kvm->arch.virtual_tsc_shift);
1003 tsc += vcpu->arch.last_tsc_write;
1004 return tsc;
1005}
1006
99e3e30a
ZA		 1007void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1008{
1009 struct kvm *kvm = vcpu->kvm;
f38e098f 1010 u64 offset, ns, elapsed;
99e3e30a 1011 unsigned long flags;
46543ba4 1012 s64 sdiff;
99e3e30a
ZA		 1013
1014 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1015 offset = data - native_read_tsc();
759379dd 1016 ns = get_kernel_ns();
f38e098f 1017 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1018 sdiff = data - kvm->arch.last_tsc_write;
1019 if (sdiff < 0)
1020 sdiff = -sdiff;
f38e098f
ZA		 1021
1022 /*
46543ba4 1023 * Special case: close write to TSC within 5 seconds of
f38e098f 1024 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1025 * The 5 seconds is to accomodate host load / swapping as
1026 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1027 *
1028 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1029 * or make a best guest using elapsed value.
f38e098f 1030 */
46543ba4
ZA		 1031 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1032 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1033 if (!check_tsc_unstable()) {
1034 offset = kvm->arch.last_tsc_offset;
1035 pr_debug("kvm: matched tsc offset for %llu\n", data);
1036 } else {
759379dd
ZA		 1037 u64 delta = nsec_to_cycles(elapsed);
1038 offset += delta;
1039 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1040 }
1041 ns = kvm->arch.last_tsc_nsec;
1042 }
1043 kvm->arch.last_tsc_nsec = ns;
1044 kvm->arch.last_tsc_write = data;
1045 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1046 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1047 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1048
1049 /* Reset of TSC must disable overshoot protection below */
1050 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1051 vcpu->arch.last_tsc_write = data;
1052 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1053}
1054EXPORT_SYMBOL_GPL(kvm_write_tsc);
1055
34c238a1 1056static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1057{
18068523
GOC		 1058 unsigned long flags;
1059 struct kvm_vcpu_arch *vcpu = &v->arch;
1060 void *shared_kaddr;
463656c0 1061 unsigned long this_tsc_khz;
1d5f066e
ZA		 1062 s64 kernel_ns, max_kernel_ns;
1063 u64 tsc_timestamp;
18068523 1064
18068523
GOC		 1065 /* Keep irq disabled to prevent changes to the clock */
1066 local_irq_save(flags);
1d5f066e 1067 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1068 kernel_ns = get_kernel_ns();
8cfdc000 1069 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1070
8cfdc000 1071 if (unlikely(this_tsc_khz == 0)) {
c285545f 1072 local_irq_restore(flags);
34c238a1 1073 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1074 return 1;
1075 }
18068523 1076
c285545f
ZA		 1077 /*
1078 * We may have to catch up the TSC to match elapsed wall clock
1079 * time for two reasons, even if kvmclock is used.
1080 * 1) CPU could have been running below the maximum TSC rate
1081 * 2) Broken TSC compensation resets the base at each VCPU
1082 * entry to avoid unknown leaps of TSC even when running
1083 * again on the same CPU. This may cause apparent elapsed
1084 * time to disappear, and the guest to stand still or run
1085 * very slowly.
1086 */
1087 if (vcpu->tsc_catchup) {
1088 u64 tsc = compute_guest_tsc(v, kernel_ns);
1089 if (tsc > tsc_timestamp) {
1090 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1091 tsc_timestamp = tsc;
1092 }
50d0a0f9
GH		 1093 }
1094
18068523
GOC		 1095 local_irq_restore(flags);
1096
c285545f
ZA		 1097 if (!vcpu->time_page)
1098 return 0;
18068523 1099
1d5f066e
ZA		 1100 /*
1101 * Time as measured by the TSC may go backwards when resetting the base
1102 * tsc_timestamp. The reason for this is that the TSC resolution is
1103 * higher than the resolution of the other clock scales. Thus, many
1104 * possible measurments of the TSC correspond to one measurement of any
1105 * other clock, and so a spread of values is possible. This is not a
1106 * problem for the computation of the nanosecond clock; with TSC rates
1107 * around 1GHZ, there can only be a few cycles which correspond to one
1108 * nanosecond value, and any path through this code will inevitably
1109 * take longer than that. However, with the kernel_ns value itself,
1110 * the precision may be much lower, down to HZ granularity. If the
1111 * first sampling of TSC against kernel_ns ends in the low part of the
1112 * range, and the second in the high end of the range, we can get:
1113 *
1114 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1115 *
1116 * As the sampling errors potentially range in the thousands of cycles,
1117 * it is possible such a time value has already been observed by the
1118 * guest. To protect against this, we must compute the system time as
1119 * observed by the guest and ensure the new system time is greater.
1120 */
1121 max_kernel_ns = 0;
1122 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1123 max_kernel_ns = vcpu->last_guest_tsc -
1124 vcpu->hv_clock.tsc_timestamp;
1125 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1126 vcpu->hv_clock.tsc_to_system_mul,
1127 vcpu->hv_clock.tsc_shift);
1128 max_kernel_ns += vcpu->last_kernel_ns;
1129 }
afbcf7ab 1130
e48672fa 1131 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1132 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1133 &vcpu->hv_clock.tsc_shift,
1134 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1135 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1136 }
1137
1d5f066e
ZA		 1138 if (max_kernel_ns > kernel_ns)
1139 kernel_ns = max_kernel_ns;
1140
8cfdc000 1141 /* With all the info we got, fill in the values */
1d5f066e 1142 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1143 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1144 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1145 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1146 vcpu->hv_clock.flags = 0;
1147
18068523
GOC		 1148 /*
1149 * The interface expects us to write an even number signaling that the
1150 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1151 * state, we just increase by 2 at the end.
18068523 1152 */
50d0a0f9 1153 vcpu->hv_clock.version += 2;
18068523
GOC		 1154
1155 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1156
1157 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1158 sizeof(vcpu->hv_clock));
18068523
GOC		 1159
1160 kunmap_atomic(shared_kaddr, KM_USER0);
1161
1162 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1163 return 0;
c8076604
GH		 1164}
1165
9ba075a6
AK		 1166static bool msr_mtrr_valid(unsigned msr)
1167{
1168 switch (msr) {
1169 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1170 case MSR_MTRRfix64K_00000:
1171 case MSR_MTRRfix16K_80000:
1172 case MSR_MTRRfix16K_A0000:
1173 case MSR_MTRRfix4K_C0000:
1174 case MSR_MTRRfix4K_C8000:
1175 case MSR_MTRRfix4K_D0000:
1176 case MSR_MTRRfix4K_D8000:
1177 case MSR_MTRRfix4K_E0000:
1178 case MSR_MTRRfix4K_E8000:
1179 case MSR_MTRRfix4K_F0000:
1180 case MSR_MTRRfix4K_F8000:
1181 case MSR_MTRRdefType:
1182 case MSR_IA32_CR_PAT:
1183 return true;
1184 case 0x2f8:
1185 return true;
1186 }
1187 return false;
1188}
1189
d6289b93
MT		 1190static bool valid_pat_type(unsigned t)
1191{
1192 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1193}
1194
1195static bool valid_mtrr_type(unsigned t)
1196{
1197 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1198}
1199
1200static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1201{
1202 int i;
1203
1204 if (!msr_mtrr_valid(msr))
1205 return false;
1206
1207 if (msr == MSR_IA32_CR_PAT) {
1208 for (i = 0; i < 8; i++)
1209 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1210 return false;
1211 return true;
1212 } else if (msr == MSR_MTRRdefType) {
1213 if (data & ~0xcff)
1214 return false;
1215 return valid_mtrr_type(data & 0xff);
1216 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1217 for (i = 0; i < 8 ; i++)
1218 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1219 return false;
1220 return true;
1221 }
1222
1223 /* variable MTRRs */
1224 return valid_mtrr_type(data & 0xff);
1225}
1226
9ba075a6
AK		 1227static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1228{
0bed3b56
SY		 1229 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1230
d6289b93 1231 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1232 return 1;
1233
0bed3b56
SY		 1234 if (msr == MSR_MTRRdefType) {
1235 vcpu->arch.mtrr_state.def_type = data;
1236 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1237 } else if (msr == MSR_MTRRfix64K_00000)
1238 p[0] = data;
1239 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1240 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1241 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1242 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1243 else if (msr == MSR_IA32_CR_PAT)
1244 vcpu->arch.pat = data;
1245 else { /* Variable MTRRs */
1246 int idx, is_mtrr_mask;
1247 u64 *pt;
1248
1249 idx = (msr - 0x200) / 2;
1250 is_mtrr_mask = msr - 0x200 - 2 * idx;
1251 if (!is_mtrr_mask)
1252 pt =
1253 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1254 else
1255 pt =
1256 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1257 *pt = data;
1258 }
1259
1260 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1261 return 0;
1262}
15c4a640 1263
890ca9ae 1264static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1265{
890ca9ae
HY		 1266 u64 mcg_cap = vcpu->arch.mcg_cap;
1267 unsigned bank_num = mcg_cap & 0xff;
1268
15c4a640 1269 switch (msr) {
15c4a640 1270 case MSR_IA32_MCG_STATUS:
890ca9ae 1271 vcpu->arch.mcg_status = data;
15c4a640 1272 break;
c7ac679c 1273 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1274 if (!(mcg_cap & MCG_CTL_P))
1275 return 1;
1276 if (data != 0 && data != ~(u64)0)
1277 return -1;
1278 vcpu->arch.mcg_ctl = data;
1279 break;
1280 default:
1281 if (msr >= MSR_IA32_MC0_CTL &&
1282 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1283 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1284 /* only 0 or all 1s can be written to IA32_MCi_CTL
1285 * some Linux kernels though clear bit 10 in bank 4 to
1286 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1287 * this to avoid an uncatched #GP in the guest
1288 */
890ca9ae 1289 if ((offset & 0x3) == 0 &&
114be429 1290 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1291 return -1;
1292 vcpu->arch.mce_banks[offset] = data;
1293 break;
1294 }
1295 return 1;
1296 }
1297 return 0;
1298}
1299
ffde22ac
ES		 1300static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1301{
1302 struct kvm *kvm = vcpu->kvm;
1303 int lm = is_long_mode(vcpu);
1304 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1305 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1306 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1307 : kvm->arch.xen_hvm_config.blob_size_32;
1308 u32 page_num = data & ~PAGE_MASK;
1309 u64 page_addr = data & PAGE_MASK;
1310 u8 *page;
1311 int r;
1312
1313 r = -E2BIG;
1314 if (page_num >= blob_size)
1315 goto out;
1316 r = -ENOMEM;
1317 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1318 if (!page)
1319 goto out;
1320 r = -EFAULT;
1321 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1322 goto out_free;
1323 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1324 goto out_free;
1325 r = 0;
1326out_free:
1327 kfree(page);
1328out:
1329 return r;
1330}
1331
55cd8e5a
GN		 1332static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1333{
1334 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1335}
1336
1337static bool kvm_hv_msr_partition_wide(u32 msr)
1338{
1339 bool r = false;
1340 switch (msr) {
1341 case HV_X64_MSR_GUEST_OS_ID:
1342 case HV_X64_MSR_HYPERCALL:
1343 r = true;
1344 break;
1345 }
1346
1347 return r;
1348}
1349
1350static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1351{
1352 struct kvm *kvm = vcpu->kvm;
1353
1354 switch (msr) {
1355 case HV_X64_MSR_GUEST_OS_ID:
1356 kvm->arch.hv_guest_os_id = data;
1357 /* setting guest os id to zero disables hypercall page */
1358 if (!kvm->arch.hv_guest_os_id)
1359 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1360 break;
1361 case HV_X64_MSR_HYPERCALL: {
1362 u64 gfn;
1363 unsigned long addr;
1364 u8 instructions[4];
1365
1366 /* if guest os id is not set hypercall should remain disabled */
1367 if (!kvm->arch.hv_guest_os_id)
1368 break;
1369 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1370 kvm->arch.hv_hypercall = data;
1371 break;
1372 }
1373 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1374 addr = gfn_to_hva(kvm, gfn);
1375 if (kvm_is_error_hva(addr))
1376 return 1;
1377 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1378 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1379 if (copy_to_user((void __user *)addr, instructions, 4))
1380 return 1;
1381 kvm->arch.hv_hypercall = data;
1382 break;
1383 }
1384 default:
1385 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1386 "data 0x%llx\n", msr, data);
1387 return 1;
1388 }
1389 return 0;
1390}
1391
1392static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1393{
10388a07
GN		 1394 switch (msr) {
1395 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1396 unsigned long addr;
55cd8e5a 1397
10388a07
GN		 1398 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1399 vcpu->arch.hv_vapic = data;
1400 break;
1401 }
1402 addr = gfn_to_hva(vcpu->kvm, data >>
1403 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1404 if (kvm_is_error_hva(addr))
1405 return 1;
1406 if (clear_user((void __user *)addr, PAGE_SIZE))
1407 return 1;
1408 vcpu->arch.hv_vapic = data;
1409 break;
1410 }
1411 case HV_X64_MSR_EOI:
1412 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1413 case HV_X64_MSR_ICR:
1414 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1415 case HV_X64_MSR_TPR:
1416 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1417 default:
1418 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1419 "data 0x%llx\n", msr, data);
1420 return 1;
1421 }
1422
1423 return 0;
55cd8e5a
GN		 1424}
1425
15c4a640
CO		 1426int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1427{
1428 switch (msr) {
15c4a640 1429 case MSR_EFER:
b69e8cae 1430 return set_efer(vcpu, data);
8f1589d9
AP		 1431 case MSR_K7_HWCR:
1432 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1433 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1434 if (data != 0) {
1435 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1436 data);
1437 return 1;
1438 }
15c4a640 1439 break;
f7c6d140
AP		 1440 case MSR_FAM10H_MMIO_CONF_BASE:
1441 if (data != 0) {
1442 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1443 "0x%llx\n", data);
1444 return 1;
1445 }
15c4a640 1446 break;
c323c0e5 1447 case MSR_AMD64_NB_CFG:
c7ac679c 1448 break;
b5e2fec0
AG		 1449 case MSR_IA32_DEBUGCTLMSR:
1450 if (!data) {
1451 /* We support the non-activated case already */
1452 break;
1453 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1454 /* Values other than LBR and BTF are vendor-specific,
1455 thus reserved and should throw a #GP */
1456 return 1;
1457 }
1458 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1459 __func__, data);
1460 break;
15c4a640
CO		 1461 case MSR_IA32_UCODE_REV:
1462 case MSR_IA32_UCODE_WRITE:
61a6bd67 1463 case MSR_VM_HSAVE_PA:
6098ca93 1464 case MSR_AMD64_PATCH_LOADER:
15c4a640 1465 break;
9ba075a6
AK		 1466 case 0x200 ... 0x2ff:
1467 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1468 case MSR_IA32_APICBASE:
1469 kvm_set_apic_base(vcpu, data);
1470 break;
0105d1a5
GN		 1471 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1472 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1473 case MSR_IA32_MISC_ENABLE:
ad312c7c 1474 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1475 break;
11c6bffa 1476 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1477 case MSR_KVM_WALL_CLOCK:
1478 vcpu->kvm->arch.wall_clock = data;
1479 kvm_write_wall_clock(vcpu->kvm, data);
1480 break;
11c6bffa 1481 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1482 case MSR_KVM_SYSTEM_TIME: {
1483 if (vcpu->arch.time_page) {
1484 kvm_release_page_dirty(vcpu->arch.time_page);
1485 vcpu->arch.time_page = NULL;
1486 }
1487
1488 vcpu->arch.time = data;
c285545f 1489 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1490
1491 /* we verify if the enable bit is set... */
1492 if (!(data & 1))
1493 break;
1494
1495 /* ...but clean it before doing the actual write */
1496 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1497
18068523
GOC		 1498 vcpu->arch.time_page =
1499 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1500
1501 if (is_error_page(vcpu->arch.time_page)) {
1502 kvm_release_page_clean(vcpu->arch.time_page);
1503 vcpu->arch.time_page = NULL;
1504 }
18068523
GOC		 1505 break;
1506 }
890ca9ae
HY		 1507 case MSR_IA32_MCG_CTL:
1508 case MSR_IA32_MCG_STATUS:
1509 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1510 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1511
1512 /* Performance counters are not protected by a CPUID bit,
1513 * so we should check all of them in the generic path for the sake of
1514 * cross vendor migration.
1515 * Writing a zero into the event select MSRs disables them,
1516 * which we perfectly emulate ;-). Any other value should be at least
1517 * reported, some guests depend on them.
1518 */
1519 case MSR_P6_EVNTSEL0:
1520 case MSR_P6_EVNTSEL1:
1521 case MSR_K7_EVNTSEL0:
1522 case MSR_K7_EVNTSEL1:
1523 case MSR_K7_EVNTSEL2:
1524 case MSR_K7_EVNTSEL3:
1525 if (data != 0)
1526 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1527 "0x%x data 0x%llx\n", msr, data);
1528 break;
1529 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1530 * so we ignore writes to make it happy.
1531 */
1532 case MSR_P6_PERFCTR0:
1533 case MSR_P6_PERFCTR1:
1534 case MSR_K7_PERFCTR0:
1535 case MSR_K7_PERFCTR1:
1536 case MSR_K7_PERFCTR2:
1537 case MSR_K7_PERFCTR3:
1538 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1539 "0x%x data 0x%llx\n", msr, data);
1540 break;
84e0cefa
JS		 1541 case MSR_K7_CLK_CTL:
1542 /*
1543 * Ignore all writes to this no longer documented MSR.
1544 * Writes are only relevant for old K7 processors,
1545 * all pre-dating SVM, but a recommended workaround from
1546 * AMD for these chips. It is possible to speicify the
1547 * affected processor models on the command line, hence
1548 * the need to ignore the workaround.
1549 */
1550 break;
55cd8e5a
GN		 1551 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1552 if (kvm_hv_msr_partition_wide(msr)) {
1553 int r;
1554 mutex_lock(&vcpu->kvm->lock);
1555 r = set_msr_hyperv_pw(vcpu, msr, data);
1556 mutex_unlock(&vcpu->kvm->lock);
1557 return r;
1558 } else
1559 return set_msr_hyperv(vcpu, msr, data);
1560 break;
15c4a640 1561 default:
ffde22ac
ES		 1562 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1563 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1564 if (!ignore_msrs) {
1565 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1566 msr, data);
1567 return 1;
1568 } else {
1569 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1570 msr, data);
1571 break;
1572 }
15c4a640
CO		 1573 }
1574 return 0;
1575}
1576EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1577
1578
1579/*
1580 * Reads an msr value (of 'msr_index') into 'pdata'.
1581 * Returns 0 on success, non-0 otherwise.
1582 * Assumes vcpu_load() was already called.
1583 */
1584int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1585{
1586 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1587}
1588
9ba075a6
AK		 1589static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1590{
0bed3b56
SY		 1591 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1592
9ba075a6
AK		 1593 if (!msr_mtrr_valid(msr))
1594 return 1;
1595
0bed3b56
SY		 1596 if (msr == MSR_MTRRdefType)
1597 *pdata = vcpu->arch.mtrr_state.def_type +
1598 (vcpu->arch.mtrr_state.enabled << 10);
1599 else if (msr == MSR_MTRRfix64K_00000)
1600 *pdata = p[0];
1601 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1602 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1603 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1604 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1605 else if (msr == MSR_IA32_CR_PAT)
1606 *pdata = vcpu->arch.pat;
1607 else { /* Variable MTRRs */
1608 int idx, is_mtrr_mask;
1609 u64 *pt;
1610
1611 idx = (msr - 0x200) / 2;
1612 is_mtrr_mask = msr - 0x200 - 2 * idx;
1613 if (!is_mtrr_mask)
1614 pt =
1615 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1616 else
1617 pt =
1618 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1619 *pdata = *pt;
1620 }
1621
9ba075a6
AK		 1622 return 0;
1623}
1624
890ca9ae 1625static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1626{
1627 u64 data;
890ca9ae
HY		 1628 u64 mcg_cap = vcpu->arch.mcg_cap;
1629 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1630
1631 switch (msr) {
15c4a640
CO		 1632 case MSR_IA32_P5_MC_ADDR:
1633 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1634 data = 0;
1635 break;
15c4a640 1636 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1637 data = vcpu->arch.mcg_cap;
1638 break;
c7ac679c 1639 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1640 if (!(mcg_cap & MCG_CTL_P))
1641 return 1;
1642 data = vcpu->arch.mcg_ctl;
1643 break;
1644 case MSR_IA32_MCG_STATUS:
1645 data = vcpu->arch.mcg_status;
1646 break;
1647 default:
1648 if (msr >= MSR_IA32_MC0_CTL &&
1649 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1650 u32 offset = msr - MSR_IA32_MC0_CTL;
1651 data = vcpu->arch.mce_banks[offset];
1652 break;
1653 }
1654 return 1;
1655 }
1656 *pdata = data;
1657 return 0;
1658}
1659
55cd8e5a
GN		 1660static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1661{
1662 u64 data = 0;
1663 struct kvm *kvm = vcpu->kvm;
1664
1665 switch (msr) {
1666 case HV_X64_MSR_GUEST_OS_ID:
1667 data = kvm->arch.hv_guest_os_id;
1668 break;
1669 case HV_X64_MSR_HYPERCALL:
1670 data = kvm->arch.hv_hypercall;
1671 break;
1672 default:
1673 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1674 return 1;
1675 }
1676
1677 *pdata = data;
1678 return 0;
1679}
1680
1681static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1682{
1683 u64 data = 0;
1684
1685 switch (msr) {
1686 case HV_X64_MSR_VP_INDEX: {
1687 int r;
1688 struct kvm_vcpu *v;
1689 kvm_for_each_vcpu(r, v, vcpu->kvm)
1690 if (v == vcpu)
1691 data = r;
1692 break;
1693 }
10388a07
GN		 1694 case HV_X64_MSR_EOI:
1695 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1696 case HV_X64_MSR_ICR:
1697 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1698 case HV_X64_MSR_TPR:
1699 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1700 default:
1701 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1702 return 1;
1703 }
1704 *pdata = data;
1705 return 0;
1706}
1707
890ca9ae
HY		 1708int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1709{
1710 u64 data;
1711
1712 switch (msr) {
890ca9ae 1713 case MSR_IA32_PLATFORM_ID:
15c4a640 1714 case MSR_IA32_UCODE_REV:
15c4a640 1715 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1716 case MSR_IA32_DEBUGCTLMSR:
1717 case MSR_IA32_LASTBRANCHFROMIP:
1718 case MSR_IA32_LASTBRANCHTOIP:
1719 case MSR_IA32_LASTINTFROMIP:
1720 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1721 case MSR_K8_SYSCFG:
1722 case MSR_K7_HWCR:
61a6bd67 1723 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1724 case MSR_P6_PERFCTR0:
1725 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1726 case MSR_P6_EVNTSEL0:
1727 case MSR_P6_EVNTSEL1:
9e699624 1728 case MSR_K7_EVNTSEL0:
1f3ee616 1729 case MSR_K7_PERFCTR0:
1fdbd48c 1730 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1731 case MSR_AMD64_NB_CFG:
f7c6d140 1732 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1733 data = 0;
1734 break;
9ba075a6
AK		 1735 case MSR_MTRRcap:
1736 data = 0x500 | KVM_NR_VAR_MTRR;
1737 break;
1738 case 0x200 ... 0x2ff:
1739 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1740 case 0xcd: /* fsb frequency */
1741 data = 3;
1742 break;
7b914098
JS		 1743 /*
1744 * MSR_EBC_FREQUENCY_ID
1745 * Conservative value valid for even the basic CPU models.
1746 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1747 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1748 * and 266MHz for model 3, or 4. Set Core Clock
1749 * Frequency to System Bus Frequency Ratio to 1 (bits
1750 * 31:24) even though these are only valid for CPU
1751 * models > 2, however guests may end up dividing or
1752 * multiplying by zero otherwise.
1753 */
1754 case MSR_EBC_FREQUENCY_ID:
1755 data = 1 << 24;
1756 break;
15c4a640
CO		 1757 case MSR_IA32_APICBASE:
1758 data = kvm_get_apic_base(vcpu);
1759 break;
0105d1a5
GN		 1760 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1761 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1762 break;
15c4a640 1763 case MSR_IA32_MISC_ENABLE:
ad312c7c 1764 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1765 break;
847f0ad8
AG		 1766 case MSR_IA32_PERF_STATUS:
1767 /* TSC increment by tick */
1768 data = 1000ULL;
1769 /* CPU multiplier */
1770 data |= (((uint64_t)4ULL) << 40);
1771 break;
15c4a640 1772 case MSR_EFER:
f6801dff 1773 data = vcpu->arch.efer;
15c4a640 1774 break;
18068523 1775 case MSR_KVM_WALL_CLOCK:
11c6bffa 1776 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1777 data = vcpu->kvm->arch.wall_clock;
1778 break;
1779 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1780 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1781 data = vcpu->arch.time;
1782 break;
890ca9ae
HY		 1783 case MSR_IA32_P5_MC_ADDR:
1784 case MSR_IA32_P5_MC_TYPE:
1785 case MSR_IA32_MCG_CAP:
1786 case MSR_IA32_MCG_CTL:
1787 case MSR_IA32_MCG_STATUS:
1788 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1789 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1790 case MSR_K7_CLK_CTL:
1791 /*
1792 * Provide expected ramp-up count for K7. All other
1793 * are set to zero, indicating minimum divisors for
1794 * every field.
1795 *
1796 * This prevents guest kernels on AMD host with CPU
1797 * type 6, model 8 and higher from exploding due to
1798 * the rdmsr failing.
1799 */
1800 data = 0x20000000;
1801 break;
55cd8e5a
GN		 1802 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1803 if (kvm_hv_msr_partition_wide(msr)) {
1804 int r;
1805 mutex_lock(&vcpu->kvm->lock);
1806 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1807 mutex_unlock(&vcpu->kvm->lock);
1808 return r;
1809 } else
1810 return get_msr_hyperv(vcpu, msr, pdata);
1811 break;
15c4a640 1812 default:
ed85c068
AP		 1813 if (!ignore_msrs) {
1814 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1815 return 1;
1816 } else {
1817 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1818 data = 0;
1819 }
1820 break;
15c4a640
CO		 1821 }
1822 *pdata = data;
1823 return 0;
1824}
1825EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1826
313a3dc7
CO		 1827/*
1828 * Read or write a bunch of msrs. All parameters are kernel addresses.
1829 *
1830 * @return number of msrs set successfully.
1831 */
1832static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1833 struct kvm_msr_entry *entries,
1834 int (*do_msr)(struct kvm_vcpu *vcpu,
1835 unsigned index, u64 *data))
1836{
f656ce01 1837 int i, idx;
313a3dc7 1838
f656ce01 1839 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1840 for (i = 0; i < msrs->nmsrs; ++i)
1841 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1842 break;
f656ce01 1843 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1844
313a3dc7
CO		 1845 return i;
1846}
1847
1848/*
1849 * Read or write a bunch of msrs. Parameters are user addresses.
1850 *
1851 * @return number of msrs set successfully.
1852 */
1853static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1854 int (*do_msr)(struct kvm_vcpu *vcpu,
1855 unsigned index, u64 *data),
1856 int writeback)
1857{
1858 struct kvm_msrs msrs;
1859 struct kvm_msr_entry *entries;
1860 int r, n;
1861 unsigned size;
1862
1863 r = -EFAULT;
1864 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1865 goto out;
1866
1867 r = -E2BIG;
1868 if (msrs.nmsrs >= MAX_IO_MSRS)
1869 goto out;
1870
1871 r = -ENOMEM;
1872 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1873 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1874 if (!entries)
1875 goto out;
1876
1877 r = -EFAULT;
1878 if (copy_from_user(entries, user_msrs->entries, size))
1879 goto out_free;
1880
1881 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1882 if (r < 0)
1883 goto out_free;
1884
1885 r = -EFAULT;
1886 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1887 goto out_free;
1888
1889 r = n;
1890
1891out_free:
7a73c028 1892 kfree(entries);
313a3dc7
CO		 1893out:
1894 return r;
1895}
1896
018d00d2
ZX		 1897int kvm_dev_ioctl_check_extension(long ext)
1898{
1899 int r;
1900
1901 switch (ext) {
1902 case KVM_CAP_IRQCHIP:
1903 case KVM_CAP_HLT:
1904 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1905 case KVM_CAP_SET_TSS_ADDR:
07716717 1906 case KVM_CAP_EXT_CPUID:
c8076604 1907 case KVM_CAP_CLOCKSOURCE:
7837699f 1908 case KVM_CAP_PIT:
a28e4f5a 1909 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1910 case KVM_CAP_MP_STATE:
ed848624 1911 case KVM_CAP_SYNC_MMU:
52d939a0 1912 case KVM_CAP_REINJECT_CONTROL:
4925663a 1913 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1914 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1915 case KVM_CAP_IRQFD:
d34e6b17 1916 case KVM_CAP_IOEVENTFD:
c5ff41ce 1917 case KVM_CAP_PIT2:
e9f42757 1918 case KVM_CAP_PIT_STATE2:
b927a3ce 1919 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1920 case KVM_CAP_XEN_HVM:
afbcf7ab 1921 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1922 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1923 case KVM_CAP_HYPERV:
10388a07 1924 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1925 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1926 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1927 case KVM_CAP_DEBUGREGS:
d2be1651 1928 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1929 case KVM_CAP_XSAVE:
018d00d2
ZX		 1930 r = 1;
1931 break;
542472b5
LV		 1932 case KVM_CAP_COALESCED_MMIO:
1933 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1934 break;
774ead3a
AK		 1935 case KVM_CAP_VAPIC:
1936 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1937 break;
f725230a
AK		 1938 case KVM_CAP_NR_VCPUS:
1939 r = KVM_MAX_VCPUS;
1940 break;
a988b910
AK		 1941 case KVM_CAP_NR_MEMSLOTS:
1942 r = KVM_MEMORY_SLOTS;
1943 break;
a68a6a72
MT		 1944 case KVM_CAP_PV_MMU: /* obsolete */
1945 r = 0;
2f333bcb 1946 break;
62c476c7 1947 case KVM_CAP_IOMMU:
19de40a8 1948 r = iommu_found();
62c476c7 1949 break;
890ca9ae
HY		 1950 case KVM_CAP_MCE:
1951 r = KVM_MAX_MCE_BANKS;
1952 break;
2d5b5a66
SY		 1953 case KVM_CAP_XCRS:
1954 r = cpu_has_xsave;
1955 break;
018d00d2
ZX		 1956 default:
1957 r = 0;
1958 break;
1959 }
1960 return r;
1961
1962}
1963
043405e1
CO		 1964long kvm_arch_dev_ioctl(struct file *filp,
1965 unsigned int ioctl, unsigned long arg)
1966{
1967 void __user *argp = (void __user *)arg;
1968 long r;
1969
1970 switch (ioctl) {
1971 case KVM_GET_MSR_INDEX_LIST: {
1972 struct kvm_msr_list __user *user_msr_list = argp;
1973 struct kvm_msr_list msr_list;
1974 unsigned n;
1975
1976 r = -EFAULT;
1977 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1978 goto out;
1979 n = msr_list.nmsrs;
1980 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1981 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1982 goto out;
1983 r = -E2BIG;
e125e7b6 1984 if (n < msr_list.nmsrs)
043405e1
CO		 1985 goto out;
1986 r = -EFAULT;
1987 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1988 num_msrs_to_save * sizeof(u32)))
1989 goto out;
e125e7b6 1990 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1991 &emulated_msrs,
1992 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1993 goto out;
1994 r = 0;
1995 break;
1996 }
674eea0f
AK		 1997 case KVM_GET_SUPPORTED_CPUID: {
1998 struct kvm_cpuid2 __user *cpuid_arg = argp;
1999 struct kvm_cpuid2 cpuid;
2000
2001 r = -EFAULT;
2002 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2003 goto out;
2004 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2005 cpuid_arg->entries);
674eea0f
AK		 2006 if (r)
2007 goto out;
2008
2009 r = -EFAULT;
2010 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2011 goto out;
2012 r = 0;
2013 break;
2014 }
890ca9ae
HY		 2015 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2016 u64 mce_cap;
2017
2018 mce_cap = KVM_MCE_CAP_SUPPORTED;
2019 r = -EFAULT;
2020 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2021 goto out;
2022 r = 0;
2023 break;
2024 }
043405e1
CO		 2025 default:
2026 r = -EINVAL;
2027 }
2028out:
2029 return r;
2030}
2031
f5f48ee1
SY		 2032static void wbinvd_ipi(void *garbage)
2033{
2034 wbinvd();
2035}
2036
2037static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2038{
2039 return vcpu->kvm->arch.iommu_domain &&
2040 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2041}
2042
313a3dc7
CO		 2043void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2044{
f5f48ee1
SY		 2045 /* Address WBINVD may be executed by guest */
2046 if (need_emulate_wbinvd(vcpu)) {
2047 if (kvm_x86_ops->has_wbinvd_exit())
2048 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2049 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2050 smp_call_function_single(vcpu->cpu,
2051 wbinvd_ipi, NULL, 1);
2052 }
2053
313a3dc7 2054 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2055 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2056 /* Make sure TSC doesn't go backwards */
2057 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2058 native_read_tsc() - vcpu->arch.last_host_tsc;
2059 if (tsc_delta < 0)
2060 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2061 if (check_tsc_unstable()) {
e48672fa 2062 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2063 vcpu->arch.tsc_catchup = 1;
2064 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2065 }
2066 if (vcpu->cpu != cpu)
2067 kvm_migrate_timers(vcpu);
e48672fa 2068 vcpu->cpu = cpu;
6b7d7e76 2069 }
313a3dc7
CO		 2070}
2071
2072void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2073{
02daab21 2074 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2075 kvm_put_guest_fpu(vcpu);
e48672fa 2076 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2077}
2078
07716717 2079static int is_efer_nx(void)
313a3dc7 2080{
e286e86e 2081 unsigned long long efer = 0;
313a3dc7 2082
e286e86e 2083 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2084 return efer & EFER_NX;
2085}
2086
2087static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2088{
2089 int i;
2090 struct kvm_cpuid_entry2 *e, *entry;
2091
313a3dc7 2092 entry = NULL;
ad312c7c
ZX		 2093 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2094 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2095 if (e->function == 0x80000001) {
2096 entry = e;
2097 break;
2098 }
2099 }
07716717 2100 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2101 entry->edx &= ~(1 << 20);
2102 printk(KERN_INFO "kvm: guest NX capability removed\n");
2103 }
2104}
2105
07716717 2106/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2107static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2108 struct kvm_cpuid *cpuid,
2109 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2110{
2111 int r, i;
2112 struct kvm_cpuid_entry *cpuid_entries;
2113
2114 r = -E2BIG;
2115 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2116 goto out;
2117 r = -ENOMEM;
2118 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2119 if (!cpuid_entries)
2120 goto out;
2121 r = -EFAULT;
2122 if (copy_from_user(cpuid_entries, entries,
2123 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2124 goto out_free;
2125 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2126 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2127 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2128 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2129 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2130 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2131 vcpu->arch.cpuid_entries[i].index = 0;
2132 vcpu->arch.cpuid_entries[i].flags = 0;
2133 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2134 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2135 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2136 }
2137 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2138 cpuid_fix_nx_cap(vcpu);
2139 r = 0;
fc61b800 2140 kvm_apic_set_version(vcpu);
0e851880 2141 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2142 update_cpuid(vcpu);
07716717
DK		 2143
2144out_free:
2145 vfree(cpuid_entries);
2146out:
2147 return r;
2148}
2149
2150static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2151 struct kvm_cpuid2 *cpuid,
2152 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2153{
2154 int r;
2155
2156 r = -E2BIG;
2157 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2158 goto out;
2159 r = -EFAULT;
ad312c7c 2160 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2161 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2162 goto out;
ad312c7c 2163 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2164 kvm_apic_set_version(vcpu);
0e851880 2165 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2166 update_cpuid(vcpu);
313a3dc7
CO		 2167 return 0;
2168
2169out:
2170 return r;
2171}
2172
07716717 2173static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2174 struct kvm_cpuid2 *cpuid,
2175 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2176{
2177 int r;
2178
2179 r = -E2BIG;
ad312c7c 2180 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2181 goto out;
2182 r = -EFAULT;
ad312c7c 2183 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2184 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2185 goto out;
2186 return 0;
2187
2188out:
ad312c7c 2189 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2190 return r;
2191}
2192
07716717 2193static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2194 u32 index)
07716717
DK		 2195{
2196 entry->function = function;
2197 entry->index = index;
2198 cpuid_count(entry->function, entry->index,
19355475 2199 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2200 entry->flags = 0;
2201}
2202
7faa4ee1
AK		 2203#define F(x) bit(X86_FEATURE_##x)
2204
07716717
DK		 2205static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2206 u32 index, int *nent, int maxnent)
2207{
7faa4ee1 2208 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2209#ifdef CONFIG_X86_64
17cc3935
SY		 2210 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2211 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2212 unsigned f_lm = F(LM);
2213#else
17cc3935 2214 unsigned f_gbpages = 0;
7faa4ee1 2215 unsigned f_lm = 0;
07716717 2216#endif
4e47c7a6 2217 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2218
2219 /* cpuid 1.edx */
2220 const u32 kvm_supported_word0_x86_features =
2221 F(FPU) | F(VME) | F(DE) | F(PSE) |
2222 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2223 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2224 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2225 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2226 0 /* Reserved, DS, ACPI */ | F(MMX) |
2227 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2228 0 /* HTT, TM, Reserved, PBE */;
2229 /* cpuid 0x80000001.edx */
2230 const u32 kvm_supported_word1_x86_features =
2231 F(FPU) | F(VME) | F(DE) | F(PSE) |
2232 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2233 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2234 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2235 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2236 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2237 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2238 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2239 /* cpuid 1.ecx */
2240 const u32 kvm_supported_word4_x86_features =
6c3f6041 2241 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2242 0 /* DS-CPL, VMX, SMX, EST */ |
2243 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2244 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2245 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2246 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2247 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2248 F(F16C);
7faa4ee1 2249 /* cpuid 0x80000001.ecx */
07716717 2250 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2251 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2252 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2253 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2254 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2255
19355475 2256 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2257 get_cpu();
2258 do_cpuid_1_ent(entry, function, index);
2259 ++*nent;
2260
2261 switch (function) {
2262 case 0:
2acf923e 2263 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2264 break;
2265 case 1:
2266 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2267 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2268 /* we support x2apic emulation even if host does not support
2269 * it since we emulate x2apic in software */
2270 entry->ecx |= F(X2APIC);
07716717
DK		 2271 break;
2272 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2273 * may return different values. This forces us to get_cpu() before
2274 * issuing the first command, and also to emulate this annoying behavior
2275 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2276 case 2: {
2277 int t, times = entry->eax & 0xff;
2278
2279 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2280 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2281 for (t = 1; t < times && *nent < maxnent; ++t) {
2282 do_cpuid_1_ent(&entry[t], function, 0);
2283 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2284 ++*nent;
2285 }
2286 break;
2287 }
2288 /* function 4 and 0xb have additional index. */
2289 case 4: {
14af3f3c 2290 int i, cache_type;
07716717
DK		 2291
2292 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2293 /* read more entries until cache_type is zero */
14af3f3c
HH		 2294 for (i = 1; *nent < maxnent; ++i) {
2295 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2296 if (!cache_type)
2297 break;
14af3f3c
HH		 2298 do_cpuid_1_ent(&entry[i], function, i);
2299 entry[i].flags |=
07716717
DK		 2300 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2301 ++*nent;
2302 }
2303 break;
2304 }
2305 case 0xb: {
14af3f3c 2306 int i, level_type;
07716717
DK		 2307
2308 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2309 /* read more entries until level_type is zero */
14af3f3c 2310 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2311 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2312 if (!level_type)
2313 break;
14af3f3c
HH		 2314 do_cpuid_1_ent(&entry[i], function, i);
2315 entry[i].flags |=
07716717
DK		 2316 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2317 ++*nent;
2318 }
2319 break;
2320 }
2acf923e
DC		 2321 case 0xd: {
2322 int i;
2323
2324 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2325 for (i = 1; *nent < maxnent; ++i) {
2326 if (entry[i - 1].eax == 0 && i != 2)
2327 break;
2328 do_cpuid_1_ent(&entry[i], function, i);
2329 entry[i].flags |=
2330 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2331 ++*nent;
2332 }
2333 break;
2334 }
84478c82
GC		 2335 case KVM_CPUID_SIGNATURE: {
2336 char signature[12] = "KVMKVMKVM\0\0";
2337 u32 *sigptr = (u32 *)signature;
2338 entry->eax = 0;
2339 entry->ebx = sigptr[0];
2340 entry->ecx = sigptr[1];
2341 entry->edx = sigptr[2];
2342 break;
2343 }
2344 case KVM_CPUID_FEATURES:
2345 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2346 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2347 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2348 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2349 entry->ebx = 0;
2350 entry->ecx = 0;
2351 entry->edx = 0;
2352 break;
07716717
DK		 2353 case 0x80000000:
2354 entry->eax = min(entry->eax, 0x8000001a);
2355 break;
2356 case 0x80000001:
2357 entry->edx &= kvm_supported_word1_x86_features;
2358 entry->ecx &= kvm_supported_word6_x86_features;
2359 break;
2360 }
d4330ef2
JR		 2361
2362 kvm_x86_ops->set_supported_cpuid(function, entry);
2363
07716717
DK		 2364 put_cpu();
2365}
2366
7faa4ee1
AK		 2367#undef F
2368
674eea0f 2369static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2370 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2371{
2372 struct kvm_cpuid_entry2 *cpuid_entries;
2373 int limit, nent = 0, r = -E2BIG;
2374 u32 func;
2375
2376 if (cpuid->nent < 1)
2377 goto out;
6a544355
AK		 2378 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2379 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2380 r = -ENOMEM;
2381 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2382 if (!cpuid_entries)
2383 goto out;
2384
2385 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2386 limit = cpuid_entries[0].eax;
2387 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2388 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2389 &nent, cpuid->nent);
07716717
DK		 2390 r = -E2BIG;
2391 if (nent >= cpuid->nent)
2392 goto out_free;
2393
2394 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2395 limit = cpuid_entries[nent - 1].eax;
2396 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2397 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2398 &nent, cpuid->nent);
84478c82
GC		 2399
2400
2401
2402 r = -E2BIG;
2403 if (nent >= cpuid->nent)
2404 goto out_free;
2405
2406 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2407 cpuid->nent);
2408
2409 r = -E2BIG;
2410 if (nent >= cpuid->nent)
2411 goto out_free;
2412
2413 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2414 cpuid->nent);
2415
cb007648
MM		 2416 r = -E2BIG;
2417 if (nent >= cpuid->nent)
2418 goto out_free;
2419
07716717
DK		 2420 r = -EFAULT;
2421 if (copy_to_user(entries, cpuid_entries,
19355475 2422 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2423 goto out_free;
2424 cpuid->nent = nent;
2425 r = 0;
2426
2427out_free:
2428 vfree(cpuid_entries);
2429out:
2430 return r;
2431}
2432
313a3dc7
CO		 2433static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2434 struct kvm_lapic_state *s)
2435{
ad312c7c 2436 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2437
2438 return 0;
2439}
2440
2441static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2442 struct kvm_lapic_state *s)
2443{
ad312c7c 2444 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2445 kvm_apic_post_state_restore(vcpu);
cb142eb7 2446 update_cr8_intercept(vcpu);
313a3dc7
CO		 2447
2448 return 0;
2449}
2450
f77bc6a4
ZX		 2451static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2452 struct kvm_interrupt *irq)
2453{
2454 if (irq->irq < 0 || irq->irq >= 256)
2455 return -EINVAL;
2456 if (irqchip_in_kernel(vcpu->kvm))
2457 return -ENXIO;
f77bc6a4 2458
66fd3f7f 2459 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2460 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2461
f77bc6a4
ZX		 2462 return 0;
2463}
2464
c4abb7c9
JK		 2465static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2466{
c4abb7c9 2467 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2468
2469 return 0;
2470}
2471
b209749f
AK		 2472static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2473 struct kvm_tpr_access_ctl *tac)
2474{
2475 if (tac->flags)
2476 return -EINVAL;
2477 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2478 return 0;
2479}
2480
890ca9ae
HY		 2481static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2482 u64 mcg_cap)
2483{
2484 int r;
2485 unsigned bank_num = mcg_cap & 0xff, bank;
2486
2487 r = -EINVAL;
a9e38c3e 2488 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2489 goto out;
2490 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2491 goto out;
2492 r = 0;
2493 vcpu->arch.mcg_cap = mcg_cap;
2494 /* Init IA32_MCG_CTL to all 1s */
2495 if (mcg_cap & MCG_CTL_P)
2496 vcpu->arch.mcg_ctl = ~(u64)0;
2497 /* Init IA32_MCi_CTL to all 1s */
2498 for (bank = 0; bank < bank_num; bank++)
2499 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2500out:
2501 return r;
2502}
2503
2504static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2505 struct kvm_x86_mce *mce)
2506{
2507 u64 mcg_cap = vcpu->arch.mcg_cap;
2508 unsigned bank_num = mcg_cap & 0xff;
2509 u64 *banks = vcpu->arch.mce_banks;
2510
2511 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2512 return -EINVAL;
2513 /*
2514 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2515 * reporting is disabled
2516 */
2517 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2518 vcpu->arch.mcg_ctl != ~(u64)0)
2519 return 0;
2520 banks += 4 * mce->bank;
2521 /*
2522 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2523 * reporting is disabled for the bank
2524 */
2525 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2526 return 0;
2527 if (mce->status & MCI_STATUS_UC) {
2528 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2529 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2530 printk(KERN_DEBUG "kvm: set_mce: "
2531 "injects mce exception while "
2532 "previous one is in progress!\n");
a8eeb04a 2533 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2534 return 0;
2535 }
2536 if (banks[1] & MCI_STATUS_VAL)
2537 mce->status |= MCI_STATUS_OVER;
2538 banks[2] = mce->addr;
2539 banks[3] = mce->misc;
2540 vcpu->arch.mcg_status = mce->mcg_status;
2541 banks[1] = mce->status;
2542 kvm_queue_exception(vcpu, MC_VECTOR);
2543 } else if (!(banks[1] & MCI_STATUS_VAL)
2544 || !(banks[1] & MCI_STATUS_UC)) {
2545 if (banks[1] & MCI_STATUS_VAL)
2546 mce->status |= MCI_STATUS_OVER;
2547 banks[2] = mce->addr;
2548 banks[3] = mce->misc;
2549 banks[1] = mce->status;
2550 } else
2551 banks[1] |= MCI_STATUS_OVER;
2552 return 0;
2553}
2554
3cfc3092
JK		 2555static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2556 struct kvm_vcpu_events *events)
2557{
03b82a30
JK		 2558 events->exception.injected =
2559 vcpu->arch.exception.pending &&
2560 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2561 events->exception.nr = vcpu->arch.exception.nr;
2562 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2563 events->exception.pad = 0;
3cfc3092
JK		 2564 events->exception.error_code = vcpu->arch.exception.error_code;
2565
03b82a30
JK		 2566 events->interrupt.injected =
2567 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2568 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2569 events->interrupt.soft = 0;
48005f64
JK		 2570 events->interrupt.shadow =
2571 kvm_x86_ops->get_interrupt_shadow(vcpu,
2572 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2573
2574 events->nmi.injected = vcpu->arch.nmi_injected;
2575 events->nmi.pending = vcpu->arch.nmi_pending;
2576 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2577 events->nmi.pad = 0;
3cfc3092
JK		 2578
2579 events->sipi_vector = vcpu->arch.sipi_vector;
2580
dab4b911 2581 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2582 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2583 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2584 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2585}
2586
2587static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2588 struct kvm_vcpu_events *events)
2589{
dab4b911 2590 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2591 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2592 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2593 return -EINVAL;
2594
3cfc3092
JK		 2595 vcpu->arch.exception.pending = events->exception.injected;
2596 vcpu->arch.exception.nr = events->exception.nr;
2597 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2598 vcpu->arch.exception.error_code = events->exception.error_code;
2599
2600 vcpu->arch.interrupt.pending = events->interrupt.injected;
2601 vcpu->arch.interrupt.nr = events->interrupt.nr;
2602 vcpu->arch.interrupt.soft = events->interrupt.soft;
2603 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2604 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2605 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2606 kvm_x86_ops->set_interrupt_shadow(vcpu,
2607 events->interrupt.shadow);
3cfc3092
JK		 2608
2609 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2610 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2611 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2612 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2613
dab4b911
JK		 2614 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2615 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2616
3842d135
AK		 2617 kvm_make_request(KVM_REQ_EVENT, vcpu);
2618
3cfc3092
JK		 2619 return 0;
2620}
2621
a1efbe77
JK		 2622static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2623 struct kvm_debugregs *dbgregs)
2624{
a1efbe77
JK		 2625 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2626 dbgregs->dr6 = vcpu->arch.dr6;
2627 dbgregs->dr7 = vcpu->arch.dr7;
2628 dbgregs->flags = 0;
97e69aa6 2629 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2630}
2631
2632static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2633 struct kvm_debugregs *dbgregs)
2634{
2635 if (dbgregs->flags)
2636 return -EINVAL;
2637
a1efbe77
JK		 2638 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2639 vcpu->arch.dr6 = dbgregs->dr6;
2640 vcpu->arch.dr7 = dbgregs->dr7;
2641
a1efbe77
JK		 2642 return 0;
2643}
2644
2d5b5a66
SY		 2645static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2646 struct kvm_xsave *guest_xsave)
2647{
2648 if (cpu_has_xsave)
2649 memcpy(guest_xsave->region,
2650 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2651 xstate_size);
2d5b5a66
SY		 2652 else {
2653 memcpy(guest_xsave->region,
2654 &vcpu->arch.guest_fpu.state->fxsave,
2655 sizeof(struct i387_fxsave_struct));
2656 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2657 XSTATE_FPSSE;
2658 }
2659}
2660
2661static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2662 struct kvm_xsave *guest_xsave)
2663{
2664 u64 xstate_bv =
2665 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2666
2667 if (cpu_has_xsave)
2668 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2669 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2670 else {
2671 if (xstate_bv & ~XSTATE_FPSSE)
2672 return -EINVAL;
2673 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2674 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2675 }
2676 return 0;
2677}
2678
2679static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2680 struct kvm_xcrs *guest_xcrs)
2681{
2682 if (!cpu_has_xsave) {
2683 guest_xcrs->nr_xcrs = 0;
2684 return;
2685 }
2686
2687 guest_xcrs->nr_xcrs = 1;
2688 guest_xcrs->flags = 0;
2689 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2690 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2691}
2692
2693static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2694 struct kvm_xcrs *guest_xcrs)
2695{
2696 int i, r = 0;
2697
2698 if (!cpu_has_xsave)
2699 return -EINVAL;
2700
2701 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2702 return -EINVAL;
2703
2704 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2705 /* Only support XCR0 currently */
2706 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2707 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2708 guest_xcrs->xcrs[0].value);
2709 break;
2710 }
2711 if (r)
2712 r = -EINVAL;
2713 return r;
2714}
2715
313a3dc7
CO		 2716long kvm_arch_vcpu_ioctl(struct file *filp,
2717 unsigned int ioctl, unsigned long arg)
2718{
2719 struct kvm_vcpu *vcpu = filp->private_data;
2720 void __user *argp = (void __user *)arg;
2721 int r;
d1ac91d8
AK		 2722 union {
2723 struct kvm_lapic_state *lapic;
2724 struct kvm_xsave *xsave;
2725 struct kvm_xcrs *xcrs;
2726 void *buffer;
2727 } u;
2728
2729 u.buffer = NULL;
313a3dc7
CO		 2730 switch (ioctl) {
2731 case KVM_GET_LAPIC: {
2204ae3c
MT		 2732 r = -EINVAL;
2733 if (!vcpu->arch.apic)
2734 goto out;
d1ac91d8 2735 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2736
b772ff36 2737 r = -ENOMEM;
d1ac91d8 2738 if (!u.lapic)
b772ff36 2739 goto out;
d1ac91d8 2740 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2741 if (r)
2742 goto out;
2743 r = -EFAULT;
d1ac91d8 2744 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2745 goto out;
2746 r = 0;
2747 break;
2748 }
2749 case KVM_SET_LAPIC: {
2204ae3c
MT		 2750 r = -EINVAL;
2751 if (!vcpu->arch.apic)
2752 goto out;
d1ac91d8 2753 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2754 r = -ENOMEM;
d1ac91d8 2755 if (!u.lapic)
b772ff36 2756 goto out;
313a3dc7 2757 r = -EFAULT;
d1ac91d8 2758 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2759 goto out;
d1ac91d8 2760 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2761 if (r)
2762 goto out;
2763 r = 0;
2764 break;
2765 }
f77bc6a4
ZX		 2766 case KVM_INTERRUPT: {
2767 struct kvm_interrupt irq;
2768
2769 r = -EFAULT;
2770 if (copy_from_user(&irq, argp, sizeof irq))
2771 goto out;
2772 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2773 if (r)
2774 goto out;
2775 r = 0;
2776 break;
2777 }
c4abb7c9
JK		 2778 case KVM_NMI: {
2779 r = kvm_vcpu_ioctl_nmi(vcpu);
2780 if (r)
2781 goto out;
2782 r = 0;
2783 break;
2784 }
313a3dc7
CO		 2785 case KVM_SET_CPUID: {
2786 struct kvm_cpuid __user *cpuid_arg = argp;
2787 struct kvm_cpuid cpuid;
2788
2789 r = -EFAULT;
2790 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2791 goto out;
2792 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2793 if (r)
2794 goto out;
2795 break;
2796 }
07716717
DK		 2797 case KVM_SET_CPUID2: {
2798 struct kvm_cpuid2 __user *cpuid_arg = argp;
2799 struct kvm_cpuid2 cpuid;
2800
2801 r = -EFAULT;
2802 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2803 goto out;
2804 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2805 cpuid_arg->entries);
07716717
DK		 2806 if (r)
2807 goto out;
2808 break;
2809 }
2810 case KVM_GET_CPUID2: {
2811 struct kvm_cpuid2 __user *cpuid_arg = argp;
2812 struct kvm_cpuid2 cpuid;
2813
2814 r = -EFAULT;
2815 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2816 goto out;
2817 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2818 cpuid_arg->entries);
07716717
DK		 2819 if (r)
2820 goto out;
2821 r = -EFAULT;
2822 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2823 goto out;
2824 r = 0;
2825 break;
2826 }
313a3dc7
CO		 2827 case KVM_GET_MSRS:
2828 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2829 break;
2830 case KVM_SET_MSRS:
2831 r = msr_io(vcpu, argp, do_set_msr, 0);
2832 break;
b209749f
AK		 2833 case KVM_TPR_ACCESS_REPORTING: {
2834 struct kvm_tpr_access_ctl tac;
2835
2836 r = -EFAULT;
2837 if (copy_from_user(&tac, argp, sizeof tac))
2838 goto out;
2839 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2840 if (r)
2841 goto out;
2842 r = -EFAULT;
2843 if (copy_to_user(argp, &tac, sizeof tac))
2844 goto out;
2845 r = 0;
2846 break;
2847 };
b93463aa
AK		 2848 case KVM_SET_VAPIC_ADDR: {
2849 struct kvm_vapic_addr va;
2850
2851 r = -EINVAL;
2852 if (!irqchip_in_kernel(vcpu->kvm))
2853 goto out;
2854 r = -EFAULT;
2855 if (copy_from_user(&va, argp, sizeof va))
2856 goto out;
2857 r = 0;
2858 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2859 break;
2860 }
890ca9ae
HY		 2861 case KVM_X86_SETUP_MCE: {
2862 u64 mcg_cap;
2863
2864 r = -EFAULT;
2865 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2866 goto out;
2867 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2868 break;
2869 }
2870 case KVM_X86_SET_MCE: {
2871 struct kvm_x86_mce mce;
2872
2873 r = -EFAULT;
2874 if (copy_from_user(&mce, argp, sizeof mce))
2875 goto out;
2876 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2877 break;
2878 }
3cfc3092
JK		 2879 case KVM_GET_VCPU_EVENTS: {
2880 struct kvm_vcpu_events events;
2881
2882 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2883
2884 r = -EFAULT;
2885 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2886 break;
2887 r = 0;
2888 break;
2889 }
2890 case KVM_SET_VCPU_EVENTS: {
2891 struct kvm_vcpu_events events;
2892
2893 r = -EFAULT;
2894 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2895 break;
2896
2897 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2898 break;
2899 }
a1efbe77
JK		 2900 case KVM_GET_DEBUGREGS: {
2901 struct kvm_debugregs dbgregs;
2902
2903 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2904
2905 r = -EFAULT;
2906 if (copy_to_user(argp, &dbgregs,
2907 sizeof(struct kvm_debugregs)))
2908 break;
2909 r = 0;
2910 break;
2911 }
2912 case KVM_SET_DEBUGREGS: {
2913 struct kvm_debugregs dbgregs;
2914
2915 r = -EFAULT;
2916 if (copy_from_user(&dbgregs, argp,
2917 sizeof(struct kvm_debugregs)))
2918 break;
2919
2920 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2921 break;
2922 }
2d5b5a66 2923 case KVM_GET_XSAVE: {
d1ac91d8 2924 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2925 r = -ENOMEM;
d1ac91d8 2926 if (!u.xsave)
2d5b5a66
SY		 2927 break;
2928
d1ac91d8 2929 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2930
2931 r = -EFAULT;
d1ac91d8 2932 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2933 break;
2934 r = 0;
2935 break;
2936 }
2937 case KVM_SET_XSAVE: {
d1ac91d8 2938 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2939 r = -ENOMEM;
d1ac91d8 2940 if (!u.xsave)
2d5b5a66
SY		 2941 break;
2942
2943 r = -EFAULT;
d1ac91d8 2944 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2945 break;
2946
d1ac91d8 2947 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2948 break;
2949 }
2950 case KVM_GET_XCRS: {
d1ac91d8 2951 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2952 r = -ENOMEM;
d1ac91d8 2953 if (!u.xcrs)
2d5b5a66
SY		 2954 break;
2955
d1ac91d8 2956 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2957
2958 r = -EFAULT;
d1ac91d8 2959 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2960 sizeof(struct kvm_xcrs)))
2961 break;
2962 r = 0;
2963 break;
2964 }
2965 case KVM_SET_XCRS: {
d1ac91d8 2966 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2967 r = -ENOMEM;
d1ac91d8 2968 if (!u.xcrs)
2d5b5a66
SY		 2969 break;
2970
2971 r = -EFAULT;
d1ac91d8 2972 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2973 sizeof(struct kvm_xcrs)))
2974 break;
2975
d1ac91d8 2976 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2977 break;
2978 }
313a3dc7
CO		 2979 default:
2980 r = -EINVAL;
2981 }
2982out:
d1ac91d8 2983 kfree(u.buffer);
313a3dc7
CO		 2984 return r;
2985}
2986
1fe779f8
CO		 2987static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2988{
2989 int ret;
2990
2991 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2992 return -1;
2993 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2994 return ret;
2995}
2996
b927a3ce
SY		 2997static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2998 u64 ident_addr)
2999{
3000 kvm->arch.ept_identity_map_addr = ident_addr;
3001 return 0;
3002}
3003
1fe779f8
CO		 3004static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3005 u32 kvm_nr_mmu_pages)
3006{
3007 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3008 return -EINVAL;
3009
79fac95e 3010 mutex_lock(&kvm->slots_lock);
7c8a83b7 3011 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3012
3013 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3014 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3015
7c8a83b7 3016 spin_unlock(&kvm->mmu_lock);
79fac95e 3017 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3018 return 0;
3019}
3020
3021static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3022{
39de71ec 3023 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3024}
3025
1fe779f8
CO		 3026static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3027{
3028 int r;
3029
3030 r = 0;
3031 switch (chip->chip_id) {
3032 case KVM_IRQCHIP_PIC_MASTER:
3033 memcpy(&chip->chip.pic,
3034 &pic_irqchip(kvm)->pics[0],
3035 sizeof(struct kvm_pic_state));
3036 break;
3037 case KVM_IRQCHIP_PIC_SLAVE:
3038 memcpy(&chip->chip.pic,
3039 &pic_irqchip(kvm)->pics[1],
3040 sizeof(struct kvm_pic_state));
3041 break;
3042 case KVM_IRQCHIP_IOAPIC:
eba0226b 3043 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3044 break;
3045 default:
3046 r = -EINVAL;
3047 break;
3048 }
3049 return r;
3050}
3051
3052static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3053{
3054 int r;
3055
3056 r = 0;
3057 switch (chip->chip_id) {
3058 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3059 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3060 memcpy(&pic_irqchip(kvm)->pics[0],
3061 &chip->chip.pic,
3062 sizeof(struct kvm_pic_state));
f4f51050 3063 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3064 break;
3065 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3066 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3067 memcpy(&pic_irqchip(kvm)->pics[1],
3068 &chip->chip.pic,
3069 sizeof(struct kvm_pic_state));
f4f51050 3070 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3071 break;
3072 case KVM_IRQCHIP_IOAPIC:
eba0226b 3073 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3074 break;
3075 default:
3076 r = -EINVAL;
3077 break;
3078 }
3079 kvm_pic_update_irq(pic_irqchip(kvm));
3080 return r;
3081}
3082
e0f63cb9
SY		 3083static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3084{
3085 int r = 0;
3086
894a9c55 3087 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3088 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3089 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3090 return r;
3091}
3092
3093static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3094{
3095 int r = 0;
3096
894a9c55 3097 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3098 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3099 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3100 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3101 return r;
3102}
3103
3104static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3105{
3106 int r = 0;
3107
3108 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3109 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3110 sizeof(ps->channels));
3111 ps->flags = kvm->arch.vpit->pit_state.flags;
3112 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3113 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3114 return r;
3115}
3116
3117static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3118{
3119 int r = 0, start = 0;
3120 u32 prev_legacy, cur_legacy;
3121 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3122 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3123 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3124 if (!prev_legacy && cur_legacy)
3125 start = 1;
3126 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3127 sizeof(kvm->arch.vpit->pit_state.channels));
3128 kvm->arch.vpit->pit_state.flags = ps->flags;
3129 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3130 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3131 return r;
3132}
3133
52d939a0
MT		 3134static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3135 struct kvm_reinject_control *control)
3136{
3137 if (!kvm->arch.vpit)
3138 return -ENXIO;
894a9c55 3139 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3140 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3141 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3142 return 0;
3143}
3144
5bb064dc
ZX		 3145/*
3146 * Get (and clear) the dirty memory log for a memory slot.
3147 */
3148int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3149 struct kvm_dirty_log *log)
3150{
87bf6e7d 3151 int r, i;
5bb064dc 3152 struct kvm_memory_slot *memslot;
87bf6e7d 3153 unsigned long n;
b050b015 3154 unsigned long is_dirty = 0;
5bb064dc 3155
79fac95e 3156 mutex_lock(&kvm->slots_lock);
5bb064dc 3157
b050b015
MT		 3158 r = -EINVAL;
3159 if (log->slot >= KVM_MEMORY_SLOTS)
3160 goto out;
3161
3162 memslot = &kvm->memslots->memslots[log->slot];
3163 r = -ENOENT;
3164 if (!memslot->dirty_bitmap)
3165 goto out;
3166
87bf6e7d 3167 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3168
b050b015
MT		 3169 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3170 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3171
3172 /* If nothing is dirty, don't bother messing with page tables. */
3173 if (is_dirty) {
b050b015 3174 struct kvm_memslots *slots, *old_slots;
914ebccd 3175 unsigned long *dirty_bitmap;
b050b015 3176
914ebccd
TY		 3177 r = -ENOMEM;
3178 dirty_bitmap = vmalloc(n);
3179 if (!dirty_bitmap)
3180 goto out;
3181 memset(dirty_bitmap, 0, n);
b050b015 3182
914ebccd
TY		 3183 r = -ENOMEM;
3184 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3185 if (!slots) {
3186 vfree(dirty_bitmap);
3187 goto out;
3188 }
b050b015
MT		 3189 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3190 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3191
3192 old_slots = kvm->memslots;
3193 rcu_assign_pointer(kvm->memslots, slots);
3194 synchronize_srcu_expedited(&kvm->srcu);
3195 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3196 kfree(old_slots);
914ebccd 3197
edde99ce
MT		 3198 spin_lock(&kvm->mmu_lock);
3199 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3200 spin_unlock(&kvm->mmu_lock);
3201
914ebccd
TY		 3202 r = -EFAULT;
3203 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3204 vfree(dirty_bitmap);
3205 goto out;
3206 }
3207 vfree(dirty_bitmap);
3208 } else {
3209 r = -EFAULT;
3210 if (clear_user(log->dirty_bitmap, n))
3211 goto out;
5bb064dc 3212 }
b050b015 3213
5bb064dc
ZX		 3214 r = 0;
3215out:
79fac95e 3216 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3217 return r;
3218}
3219
1fe779f8
CO		 3220long kvm_arch_vm_ioctl(struct file *filp,
3221 unsigned int ioctl, unsigned long arg)
3222{
3223 struct kvm *kvm = filp->private_data;
3224 void __user *argp = (void __user *)arg;
367e1319 3225 int r = -ENOTTY;
f0d66275
DH		 3226 /*
3227 * This union makes it completely explicit to gcc-3.x
3228 * that these two variables' stack usage should be
3229 * combined, not added together.
3230 */
3231 union {
3232 struct kvm_pit_state ps;
e9f42757 3233 struct kvm_pit_state2 ps2;
c5ff41ce 3234 struct kvm_pit_config pit_config;
f0d66275 3235 } u;
1fe779f8
CO		 3236
3237 switch (ioctl) {
3238 case KVM_SET_TSS_ADDR:
3239 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3240 if (r < 0)
3241 goto out;
3242 break;
b927a3ce
SY		 3243 case KVM_SET_IDENTITY_MAP_ADDR: {
3244 u64 ident_addr;
3245
3246 r = -EFAULT;
3247 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3248 goto out;
3249 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3250 if (r < 0)
3251 goto out;
3252 break;
3253 }
1fe779f8
CO		 3254 case KVM_SET_NR_MMU_PAGES:
3255 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3256 if (r)
3257 goto out;
3258 break;
3259 case KVM_GET_NR_MMU_PAGES:
3260 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3261 break;
3ddea128
MT		 3262 case KVM_CREATE_IRQCHIP: {
3263 struct kvm_pic *vpic;
3264
3265 mutex_lock(&kvm->lock);
3266 r = -EEXIST;
3267 if (kvm->arch.vpic)
3268 goto create_irqchip_unlock;
1fe779f8 3269 r = -ENOMEM;
3ddea128
MT		 3270 vpic = kvm_create_pic(kvm);
3271 if (vpic) {
1fe779f8
CO		 3272 r = kvm_ioapic_init(kvm);
3273 if (r) {
72bb2fcd
WY		 3274 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3275 &vpic->dev);
3ddea128
MT		 3276 kfree(vpic);
3277 goto create_irqchip_unlock;
1fe779f8
CO		 3278 }
3279 } else
3ddea128
MT		 3280 goto create_irqchip_unlock;
3281 smp_wmb();
3282 kvm->arch.vpic = vpic;
3283 smp_wmb();
399ec807
AK		 3284 r = kvm_setup_default_irq_routing(kvm);
3285 if (r) {
3ddea128 3286 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3287 kvm_ioapic_destroy(kvm);
3288 kvm_destroy_pic(kvm);
3ddea128 3289 mutex_unlock(&kvm->irq_lock);
399ec807 3290 }
3ddea128
MT		 3291 create_irqchip_unlock:
3292 mutex_unlock(&kvm->lock);
1fe779f8 3293 break;
3ddea128 3294 }
7837699f 3295 case KVM_CREATE_PIT:
c5ff41ce
JK		 3296 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3297 goto create_pit;
3298 case KVM_CREATE_PIT2:
3299 r = -EFAULT;
3300 if (copy_from_user(&u.pit_config, argp,
3301 sizeof(struct kvm_pit_config)))
3302 goto out;
3303 create_pit:
79fac95e 3304 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3305 r = -EEXIST;
3306 if (kvm->arch.vpit)
3307 goto create_pit_unlock;
7837699f 3308 r = -ENOMEM;
c5ff41ce 3309 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3310 if (kvm->arch.vpit)
3311 r = 0;
269e05e4 3312 create_pit_unlock:
79fac95e 3313 mutex_unlock(&kvm->slots_lock);
7837699f 3314 break;
4925663a 3315 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3316 case KVM_IRQ_LINE: {
3317 struct kvm_irq_level irq_event;
3318
3319 r = -EFAULT;
3320 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3321 goto out;
160d2f6c 3322 r = -ENXIO;
1fe779f8 3323 if (irqchip_in_kernel(kvm)) {
4925663a 3324 __s32 status;
4925663a
GN		 3325 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3326 irq_event.irq, irq_event.level);
4925663a 3327 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3328 r = -EFAULT;
4925663a
GN		 3329 irq_event.status = status;
3330 if (copy_to_user(argp, &irq_event,
3331 sizeof irq_event))
3332 goto out;
3333 }
1fe779f8
CO		 3334 r = 0;
3335 }
3336 break;
3337 }
3338 case KVM_GET_IRQCHIP: {
3339 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3340 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3341
f0d66275
DH		 3342 r = -ENOMEM;
3343 if (!chip)
1fe779f8 3344 goto out;
f0d66275
DH		 3345 r = -EFAULT;
3346 if (copy_from_user(chip, argp, sizeof *chip))
3347 goto get_irqchip_out;
1fe779f8
CO		 3348 r = -ENXIO;
3349 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3350 goto get_irqchip_out;
3351 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3352 if (r)
f0d66275 3353 goto get_irqchip_out;
1fe779f8 3354 r = -EFAULT;
f0d66275
DH		 3355 if (copy_to_user(argp, chip, sizeof *chip))
3356 goto get_irqchip_out;
1fe779f8 3357 r = 0;
f0d66275
DH		 3358 get_irqchip_out:
3359 kfree(chip);
3360 if (r)
3361 goto out;
1fe779f8
CO		 3362 break;
3363 }
3364 case KVM_SET_IRQCHIP: {
3365 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3366 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3367
f0d66275
DH		 3368 r = -ENOMEM;
3369 if (!chip)
1fe779f8 3370 goto out;
f0d66275
DH		 3371 r = -EFAULT;
3372 if (copy_from_user(chip, argp, sizeof *chip))
3373 goto set_irqchip_out;
1fe779f8
CO		 3374 r = -ENXIO;
3375 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3376 goto set_irqchip_out;
3377 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3378 if (r)
f0d66275 3379 goto set_irqchip_out;
1fe779f8 3380 r = 0;
f0d66275
DH		 3381 set_irqchip_out:
3382 kfree(chip);
3383 if (r)
3384 goto out;
1fe779f8
CO		 3385 break;
3386 }
e0f63cb9 3387 case KVM_GET_PIT: {
e0f63cb9 3388 r = -EFAULT;
f0d66275 3389 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3390 goto out;
3391 r = -ENXIO;
3392 if (!kvm->arch.vpit)
3393 goto out;
f0d66275 3394 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3395 if (r)
3396 goto out;
3397 r = -EFAULT;
f0d66275 3398 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3399 goto out;
3400 r = 0;
3401 break;
3402 }
3403 case KVM_SET_PIT: {
e0f63cb9 3404 r = -EFAULT;
f0d66275 3405 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3406 goto out;
3407 r = -ENXIO;
3408 if (!kvm->arch.vpit)
3409 goto out;
f0d66275 3410 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3411 if (r)
3412 goto out;
3413 r = 0;
3414 break;
3415 }
e9f42757
BK		 3416 case KVM_GET_PIT2: {
3417 r = -ENXIO;
3418 if (!kvm->arch.vpit)
3419 goto out;
3420 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3421 if (r)
3422 goto out;
3423 r = -EFAULT;
3424 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3425 goto out;
3426 r = 0;
3427 break;
3428 }
3429 case KVM_SET_PIT2: {
3430 r = -EFAULT;
3431 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3432 goto out;
3433 r = -ENXIO;
3434 if (!kvm->arch.vpit)
3435 goto out;
3436 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3437 if (r)
3438 goto out;
3439 r = 0;
3440 break;
3441 }
52d939a0
MT		 3442 case KVM_REINJECT_CONTROL: {
3443 struct kvm_reinject_control control;
3444 r = -EFAULT;
3445 if (copy_from_user(&control, argp, sizeof(control)))
3446 goto out;
3447 r = kvm_vm_ioctl_reinject(kvm, &control);
3448 if (r)
3449 goto out;
3450 r = 0;
3451 break;
3452 }
ffde22ac
ES		 3453 case KVM_XEN_HVM_CONFIG: {
3454 r = -EFAULT;
3455 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3456 sizeof(struct kvm_xen_hvm_config)))
3457 goto out;
3458 r = -EINVAL;
3459 if (kvm->arch.xen_hvm_config.flags)
3460 goto out;
3461 r = 0;
3462 break;
3463 }
afbcf7ab 3464 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3465 struct kvm_clock_data user_ns;
3466 u64 now_ns;
3467 s64 delta;
3468
3469 r = -EFAULT;
3470 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3471 goto out;
3472
3473 r = -EINVAL;
3474 if (user_ns.flags)
3475 goto out;
3476
3477 r = 0;
395c6b0a 3478 local_irq_disable();
759379dd 3479 now_ns = get_kernel_ns();
afbcf7ab 3480 delta = user_ns.clock - now_ns;
395c6b0a 3481 local_irq_enable();
afbcf7ab
GC		 3482 kvm->arch.kvmclock_offset = delta;
3483 break;
3484 }
3485 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3486 struct kvm_clock_data user_ns;
3487 u64 now_ns;
3488
395c6b0a 3489 local_irq_disable();
759379dd 3490 now_ns = get_kernel_ns();
afbcf7ab 3491 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3492 local_irq_enable();
afbcf7ab 3493 user_ns.flags = 0;
97e69aa6 3494 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3495
3496 r = -EFAULT;
3497 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3498 goto out;
3499 r = 0;
3500 break;
3501 }
3502
1fe779f8
CO		 3503 default:
3504 ;
3505 }
3506out:
3507 return r;
3508}
3509
a16b043c 3510static void kvm_init_msr_list(void)
043405e1
CO		 3511{
3512 u32 dummy[2];
3513 unsigned i, j;
3514
e3267cbb
GC		 3515 /* skip the first msrs in the list. KVM-specific */
3516 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3517 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3518 continue;
3519 if (j < i)
3520 msrs_to_save[j] = msrs_to_save[i];
3521 j++;
3522 }
3523 num_msrs_to_save = j;
3524}
3525
bda9020e
MT		 3526static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3527 const void *v)
bbd9b64e 3528{
bda9020e
MT		 3529 if (vcpu->arch.apic &&
3530 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3531 return 0;
bbd9b64e 3532
e93f8a0f 3533 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3534}
3535
bda9020e 3536static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3537{
bda9020e
MT		 3538 if (vcpu->arch.apic &&
3539 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3540 return 0;
bbd9b64e 3541
e93f8a0f 3542 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3543}
3544
2dafc6c2
GN		 3545static void kvm_set_segment(struct kvm_vcpu *vcpu,
3546 struct kvm_segment *var, int seg)
3547{
3548 kvm_x86_ops->set_segment(vcpu, var, seg);
3549}
3550
3551void kvm_get_segment(struct kvm_vcpu *vcpu,
3552 struct kvm_segment *var, int seg)
3553{
3554 kvm_x86_ops->get_segment(vcpu, var, seg);
3555}
3556
c30a358d
JR		 3557static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3558{
3559 return gpa;
3560}
3561
02f59dc9
JR		 3562static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3563{
3564 gpa_t t_gpa;
3565 u32 error;
3566
3567 BUG_ON(!mmu_is_nested(vcpu));
3568
3569 /* NPT walks are always user-walks */
3570 access |= PFERR_USER_MASK;
3571 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3572 if (t_gpa == UNMAPPED_GVA)
0959ffac 3573 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3574
3575 return t_gpa;
3576}
3577
1871c602
GN		 3578gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3579{
3580 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3581 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3582}
3583
3584 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3585{
3586 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3587 access |= PFERR_FETCH_MASK;
14dfe855 3588 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3589}
3590
3591gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3592{
3593 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3594 access |= PFERR_WRITE_MASK;
14dfe855 3595 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3596}
3597
3598/* uses this to access any guest's mapped memory without checking CPL */
3599gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3600{
14dfe855 3601 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3602}
3603
3604static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3605 struct kvm_vcpu *vcpu, u32 access,
3606 u32 *error)
bbd9b64e
CO		 3607{
3608 void *data = val;
10589a46 3609 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3610
3611 while (bytes) {
14dfe855
JR		 3612 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3613 error);
bbd9b64e 3614 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3615 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3616 int ret;
3617
10589a46
MT		 3618 if (gpa == UNMAPPED_GVA) {
3619 r = X86EMUL_PROPAGATE_FAULT;
3620 goto out;
3621 }
77c2002e 3622 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3623 if (ret < 0) {
c3cd7ffa 3624 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3625 goto out;
3626 }
bbd9b64e 3627
77c2002e
IE		 3628 bytes -= toread;
3629 data += toread;
3630 addr += toread;
bbd9b64e 3631 }
10589a46 3632out:
10589a46 3633 return r;
bbd9b64e 3634}
77c2002e 3635
1871c602
GN		 3636/* used for instruction fetching */
3637static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3638 struct kvm_vcpu *vcpu, u32 *error)
3639{
3640 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3641 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3642 access | PFERR_FETCH_MASK, error);
3643}
3644
3645static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3646 struct kvm_vcpu *vcpu, u32 *error)
3647{
3648 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3649 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3650 error);
3651}
3652
3653static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3654 struct kvm_vcpu *vcpu, u32 *error)
3655{
3656 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3657}
3658
7972995b 3659static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3660 unsigned int bytes,
7972995b 3661 struct kvm_vcpu *vcpu,
2dafc6c2 3662 u32 *error)
77c2002e
IE		 3663{
3664 void *data = val;
3665 int r = X86EMUL_CONTINUE;
3666
3667 while (bytes) {
14dfe855
JR		 3668 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3669 PFERR_WRITE_MASK,
3670 error);
77c2002e
IE		 3671 unsigned offset = addr & (PAGE_SIZE-1);
3672 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3673 int ret;
3674
3675 if (gpa == UNMAPPED_GVA) {
3676 r = X86EMUL_PROPAGATE_FAULT;
3677 goto out;
3678 }
3679 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3680 if (ret < 0) {
c3cd7ffa 3681 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3682 goto out;
3683 }
3684
3685 bytes -= towrite;
3686 data += towrite;
3687 addr += towrite;
3688 }
3689out:
3690 return r;
3691}
3692
bbd9b64e
CO		 3693static int emulator_read_emulated(unsigned long addr,
3694 void *val,
3695 unsigned int bytes,
8fe681e9 3696 unsigned int *error_code,
bbd9b64e
CO		 3697 struct kvm_vcpu *vcpu)
3698{
bbd9b64e
CO		 3699 gpa_t gpa;
3700
3701 if (vcpu->mmio_read_completed) {
3702 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3703 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3704 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3705 vcpu->mmio_read_completed = 0;
3706 return X86EMUL_CONTINUE;
3707 }
3708
8fe681e9 3709 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3710
8fe681e9 3711 if (gpa == UNMAPPED_GVA)
1871c602 3712 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3713
3714 /* For APIC access vmexit */
3715 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3716 goto mmio;
3717
1871c602 3718 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3719 == X86EMUL_CONTINUE)
bbd9b64e 3720 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3721
3722mmio:
3723 /*
3724 * Is this MMIO handled locally?
3725 */
aec51dc4
AK		 3726 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3727 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3728 return X86EMUL_CONTINUE;
3729 }
aec51dc4
AK		 3730
3731 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3732
3733 vcpu->mmio_needed = 1;
411c35b7
GN		 3734 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3735 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3736 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3737 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3738
c3cd7ffa 3739 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3740}
3741
3200f405 3742int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3743 const void *val, int bytes)
bbd9b64e
CO		 3744{
3745 int ret;
3746
3747 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3748 if (ret < 0)
bbd9b64e 3749 return 0;
ad218f85 3750 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3751 return 1;
3752}
3753
3754static int emulator_write_emulated_onepage(unsigned long addr,
3755 const void *val,
3756 unsigned int bytes,
8fe681e9 3757 unsigned int *error_code,
bbd9b64e
CO		 3758 struct kvm_vcpu *vcpu)
3759{
10589a46
MT		 3760 gpa_t gpa;
3761
8fe681e9 3762 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3763
8fe681e9 3764 if (gpa == UNMAPPED_GVA)
bbd9b64e 3765 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3766
3767 /* For APIC access vmexit */
3768 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3769 goto mmio;
3770
3771 if (emulator_write_phys(vcpu, gpa, val, bytes))
3772 return X86EMUL_CONTINUE;
3773
3774mmio:
aec51dc4 3775 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3776 /*
3777 * Is this MMIO handled locally?
3778 */
bda9020e 3779 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3780 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3781
3782 vcpu->mmio_needed = 1;
411c35b7
GN		 3783 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3784 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3785 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3786 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3787 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3788
3789 return X86EMUL_CONTINUE;
3790}
3791
3792int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3793 const void *val,
3794 unsigned int bytes,
8fe681e9 3795 unsigned int *error_code,
8f6abd06 3796 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3797{
3798 /* Crossing a page boundary? */
3799 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3800 int rc, now;
3801
3802 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3803 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3804 vcpu);
bbd9b64e
CO		 3805 if (rc != X86EMUL_CONTINUE)
3806 return rc;
3807 addr += now;
3808 val += now;
3809 bytes -= now;
3810 }
8fe681e9
GN		 3811 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3812 vcpu);
bbd9b64e 3813}
bbd9b64e 3814
daea3e73
AK		 3815#define CMPXCHG_TYPE(t, ptr, old, new) \
3816 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3817
3818#ifdef CONFIG_X86_64
3819# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3820#else
3821# define CMPXCHG64(ptr, old, new) \
9749a6c0 3822 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3823#endif
3824
bbd9b64e
CO		 3825static int emulator_cmpxchg_emulated(unsigned long addr,
3826 const void *old,
3827 const void *new,
3828 unsigned int bytes,
8fe681e9 3829 unsigned int *error_code,
bbd9b64e
CO		 3830 struct kvm_vcpu *vcpu)
3831{
daea3e73
AK		 3832 gpa_t gpa;
3833 struct page *page;
3834 char *kaddr;
3835 bool exchanged;
2bacc55c 3836
daea3e73
AK		 3837 /* guests cmpxchg8b have to be emulated atomically */
3838 if (bytes > 8 || (bytes & (bytes - 1)))
3839 goto emul_write;
10589a46 3840
daea3e73 3841 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3842
daea3e73
AK		 3843 if (gpa == UNMAPPED_GVA ||
3844 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3845 goto emul_write;
2bacc55c 3846
daea3e73
AK		 3847 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3848 goto emul_write;
72dc67a6 3849
daea3e73 3850 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3851 if (is_error_page(page)) {
3852 kvm_release_page_clean(page);
3853 goto emul_write;
3854 }
72dc67a6 3855
daea3e73
AK		 3856 kaddr = kmap_atomic(page, KM_USER0);
3857 kaddr += offset_in_page(gpa);
3858 switch (bytes) {
3859 case 1:
3860 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3861 break;
3862 case 2:
3863 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3864 break;
3865 case 4:
3866 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3867 break;
3868 case 8:
3869 exchanged = CMPXCHG64(kaddr, old, new);
3870 break;
3871 default:
3872 BUG();
2bacc55c 3873 }
daea3e73
AK		 3874 kunmap_atomic(kaddr, KM_USER0);
3875 kvm_release_page_dirty(page);
3876
3877 if (!exchanged)
3878 return X86EMUL_CMPXCHG_FAILED;
3879
8f6abd06
GN		 3880 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3881
3882 return X86EMUL_CONTINUE;
4a5f48f6 3883
3200f405 3884emul_write:
daea3e73 3885 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3886
8fe681e9 3887 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3888}
3889
cf8f70bf
GN		 3890static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3891{
3892 /* TODO: String I/O for in kernel device */
3893 int r;
3894
3895 if (vcpu->arch.pio.in)
3896 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3897 vcpu->arch.pio.size, pd);
3898 else
3899 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3900 vcpu->arch.pio.port, vcpu->arch.pio.size,
3901 pd);
3902 return r;
3903}
3904
3905
3906static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3907 unsigned int count, struct kvm_vcpu *vcpu)
3908{
7972995b 3909 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3910 goto data_avail;
3911
c41a15dd 3912 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3913
3914 vcpu->arch.pio.port = port;
3915 vcpu->arch.pio.in = 1;
7972995b 3916 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3917 vcpu->arch.pio.size = size;
3918
3919 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3920 data_avail:
3921 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3922 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3923 return 1;
3924 }
3925
3926 vcpu->run->exit_reason = KVM_EXIT_IO;
3927 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3928 vcpu->run->io.size = size;
3929 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3930 vcpu->run->io.count = count;
3931 vcpu->run->io.port = port;
3932
3933 return 0;
3934}
3935
3936static int emulator_pio_out_emulated(int size, unsigned short port,
3937 const void *val, unsigned int count,
3938 struct kvm_vcpu *vcpu)
3939{
c41a15dd 3940 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3941
3942 vcpu->arch.pio.port = port;
3943 vcpu->arch.pio.in = 0;
7972995b 3944 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3945 vcpu->arch.pio.size = size;
3946
3947 memcpy(vcpu->arch.pio_data, val, size * count);
3948
3949 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3950 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3951 return 1;
3952 }
3953
3954 vcpu->run->exit_reason = KVM_EXIT_IO;
3955 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3956 vcpu->run->io.size = size;
3957 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3958 vcpu->run->io.count = count;
3959 vcpu->run->io.port = port;
3960
3961 return 0;
3962}
3963
bbd9b64e
CO		 3964static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3965{
3966 return kvm_x86_ops->get_segment_base(vcpu, seg);
3967}
3968
3969int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3970{
a7052897 3971 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3972 return X86EMUL_CONTINUE;
3973}
3974
f5f48ee1
SY		 3975int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3976{
3977 if (!need_emulate_wbinvd(vcpu))
3978 return X86EMUL_CONTINUE;
3979
3980 if (kvm_x86_ops->has_wbinvd_exit()) {
453d9c57 3981 preempt_disable();
f5f48ee1
SY		 3982 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3983 wbinvd_ipi, NULL, 1);
453d9c57 3984 preempt_enable();
f5f48ee1
SY		 3985 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3986 }
3987 wbinvd();
3988 return X86EMUL_CONTINUE;
3989}
3990EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3991
bbd9b64e
CO		 3992int emulate_clts(struct kvm_vcpu *vcpu)
3993{
4d4ec087 3994 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3995 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3996 return X86EMUL_CONTINUE;
3997}
3998
35aa5375 3999int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4000{
338dbc97 4001 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4002}
4003
35aa5375 4004int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4005{
338dbc97
GN		 4006
4007 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4008}
4009
52a46617 4010static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4011{
52a46617 4012 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4013}
4014
52a46617 4015static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4016{
52a46617
GN		 4017 unsigned long value;
4018
4019 switch (cr) {
4020 case 0:
4021 value = kvm_read_cr0(vcpu);
4022 break;
4023 case 2:
4024 value = vcpu->arch.cr2;
4025 break;
4026 case 3:
4027 value = vcpu->arch.cr3;
4028 break;
4029 case 4:
4030 value = kvm_read_cr4(vcpu);
4031 break;
4032 case 8:
4033 value = kvm_get_cr8(vcpu);
4034 break;
4035 default:
4036 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4037 return 0;
4038 }
4039
4040 return value;
4041}
4042
0f12244f 4043static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4044{
0f12244f
GN		 4045 int res = 0;
4046
52a46617
GN		 4047 switch (cr) {
4048 case 0:
49a9b07e 4049 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4050 break;
4051 case 2:
4052 vcpu->arch.cr2 = val;
4053 break;
4054 case 3:
2390218b 4055 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4056 break;
4057 case 4:
a83b29c6 4058 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4059 break;
4060 case 8:
0f12244f 4061 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4062 break;
4063 default:
4064 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4065 res = -1;
52a46617 4066 }
0f12244f
GN		 4067
4068 return res;
52a46617
GN		 4069}
4070
9c537244
GN		 4071static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4072{
4073 return kvm_x86_ops->get_cpl(vcpu);
4074}
4075
2dafc6c2
GN		 4076static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4077{
4078 kvm_x86_ops->get_gdt(vcpu, dt);
4079}
4080
160ce1f1
MG		 4081static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4082{
4083 kvm_x86_ops->get_idt(vcpu, dt);
4084}
4085
5951c442
GN		 4086static unsigned long emulator_get_cached_segment_base(int seg,
4087 struct kvm_vcpu *vcpu)
4088{
4089 return get_segment_base(vcpu, seg);
4090}
4091
2dafc6c2
GN		 4092static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4093 struct kvm_vcpu *vcpu)
4094{
4095 struct kvm_segment var;
4096
4097 kvm_get_segment(vcpu, &var, seg);
4098
4099 if (var.unusable)
4100 return false;
4101
4102 if (var.g)
4103 var.limit >>= 12;
4104 set_desc_limit(desc, var.limit);
4105 set_desc_base(desc, (unsigned long)var.base);
4106 desc->type = var.type;
4107 desc->s = var.s;
4108 desc->dpl = var.dpl;
4109 desc->p = var.present;
4110 desc->avl = var.avl;
4111 desc->l = var.l;
4112 desc->d = var.db;
4113 desc->g = var.g;
4114
4115 return true;
4116}
4117
4118static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4119 struct kvm_vcpu *vcpu)
4120{
4121 struct kvm_segment var;
4122
4123 /* needed to preserve selector */
4124 kvm_get_segment(vcpu, &var, seg);
4125
4126 var.base = get_desc_base(desc);
4127 var.limit = get_desc_limit(desc);
4128 if (desc->g)
4129 var.limit = (var.limit << 12) | 0xfff;
4130 var.type = desc->type;
4131 var.present = desc->p;
4132 var.dpl = desc->dpl;
4133 var.db = desc->d;
4134 var.s = desc->s;
4135 var.l = desc->l;
4136 var.g = desc->g;
4137 var.avl = desc->avl;
4138 var.present = desc->p;
4139 var.unusable = !var.present;
4140 var.padding = 0;
4141
4142 kvm_set_segment(vcpu, &var, seg);
4143 return;
4144}
4145
4146static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4147{
4148 struct kvm_segment kvm_seg;
4149
4150 kvm_get_segment(vcpu, &kvm_seg, seg);
4151 return kvm_seg.selector;
4152}
4153
4154static void emulator_set_segment_selector(u16 sel, int seg,
4155 struct kvm_vcpu *vcpu)
4156{
4157 struct kvm_segment kvm_seg;
4158
4159 kvm_get_segment(vcpu, &kvm_seg, seg);
4160 kvm_seg.selector = sel;
4161 kvm_set_segment(vcpu, &kvm_seg, seg);
4162}
4163
14af3f3c 4164static struct x86_emulate_ops emulate_ops = {
1871c602 4165 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4166 .write_std = kvm_write_guest_virt_system,
1871c602 4167 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4168 .read_emulated = emulator_read_emulated,
4169 .write_emulated = emulator_write_emulated,
4170 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4171 .pio_in_emulated = emulator_pio_in_emulated,
4172 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4173 .get_cached_descriptor = emulator_get_cached_descriptor,
4174 .set_cached_descriptor = emulator_set_cached_descriptor,
4175 .get_segment_selector = emulator_get_segment_selector,
4176 .set_segment_selector = emulator_set_segment_selector,
5951c442 4177 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4178 .get_gdt = emulator_get_gdt,
160ce1f1 4179 .get_idt = emulator_get_idt,
52a46617
GN		 4180 .get_cr = emulator_get_cr,
4181 .set_cr = emulator_set_cr,
9c537244 4182 .cpl = emulator_get_cpl,
35aa5375
GN		 4183 .get_dr = emulator_get_dr,
4184 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4185 .set_msr = kvm_set_msr,
4186 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4187};
4188
5fdbf976
MT		 4189static void cache_all_regs(struct kvm_vcpu *vcpu)
4190{
4191 kvm_register_read(vcpu, VCPU_REGS_RAX);
4192 kvm_register_read(vcpu, VCPU_REGS_RSP);
4193 kvm_register_read(vcpu, VCPU_REGS_RIP);
4194 vcpu->arch.regs_dirty = ~0;
4195}
4196
95cb2295
GN		 4197static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4198{
4199 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4200 /*
4201 * an sti; sti; sequence only disable interrupts for the first
4202 * instruction. So, if the last instruction, be it emulated or
4203 * not, left the system with the INT_STI flag enabled, it
4204 * means that the last instruction is an sti. We should not
4205 * leave the flag on in this case. The same goes for mov ss
4206 */
4207 if (!(int_shadow & mask))
4208 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4209}
4210
54b8486f
GN		 4211static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4212{
4213 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4214 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4215 kvm_propagate_fault(vcpu);
54b8486f
GN		 4216 else if (ctxt->error_code_valid)
4217 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4218 else
4219 kvm_queue_exception(vcpu, ctxt->exception);
4220}
4221
8ec4722d
MG		 4222static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4223{
4224 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4225 int cs_db, cs_l;
4226
4227 cache_all_regs(vcpu);
4228
4229 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4230
4231 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4232 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4233 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4234 vcpu->arch.emulate_ctxt.mode =
4235 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4236 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4237 ? X86EMUL_MODE_VM86 : cs_l
4238 ? X86EMUL_MODE_PROT64 : cs_db
4239 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4240 memset(c, 0, sizeof(struct decode_cache));
4241 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4242}
4243
63995653
MG		 4244int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4245{
4246 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4247 int ret;
4248
4249 init_emulate_ctxt(vcpu);
4250
4251 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4252 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4253 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4254 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4255
4256 if (ret != X86EMUL_CONTINUE)
4257 return EMULATE_FAIL;
4258
4259 vcpu->arch.emulate_ctxt.eip = c->eip;
4260 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4261 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4262 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4263
4264 if (irq == NMI_VECTOR)
4265 vcpu->arch.nmi_pending = false;
4266 else
4267 vcpu->arch.interrupt.pending = false;
4268
4269 return EMULATE_DONE;
4270}
4271EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4272
6d77dbfc
GN		 4273static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4274{
6d77dbfc
GN		 4275 ++vcpu->stat.insn_emulation_fail;
4276 trace_kvm_emulate_insn_failed(vcpu);
4277 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4278 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4279 vcpu->run->internal.ndata = 0;
4280 kvm_queue_exception(vcpu, UD_VECTOR);
4281 return EMULATE_FAIL;
4282}
4283
a6f177ef
GN		 4284static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4285{
4286 gpa_t gpa;
4287
68be0803
GN		 4288 if (tdp_enabled)
4289 return false;
4290
a6f177ef
GN		 4291 /*
4292 * if emulation was due to access to shadowed page table
4293 * and it failed try to unshadow page and re-entetr the
4294 * guest to let CPU execute the instruction.
4295 */
4296 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4297 return true;
4298
4299 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4300
4301 if (gpa == UNMAPPED_GVA)
4302 return true; /* let cpu generate fault */
4303
4304 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4305 return true;
4306
4307 return false;
4308}
4309
bbd9b64e 4310int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4311 unsigned long cr2,
4312 u16 error_code,
571008da 4313 int emulation_type)
bbd9b64e 4314{
95cb2295 4315 int r;
4d2179e1 4316 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4317
26eef70c 4318 kvm_clear_exception_queue(vcpu);
ad312c7c 4319 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4320 /*
56e82318 4321 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4322 * instead of direct ->regs accesses, can save hundred cycles
4323 * on Intel for instructions that don't read/change RSP, for
4324 * for example.
4325 */
4326 cache_all_regs(vcpu);
bbd9b64e 4327
571008da 4328 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4329 init_emulate_ctxt(vcpu);
95cb2295 4330 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4331 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4332 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4333
9aabc88f 4334 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4335 if (r == X86EMUL_PROPAGATE_FAULT)
4336 goto done;
bbd9b64e 4337
e46479f8 4338 trace_kvm_emulate_insn_start(vcpu);
571008da 4339
0cb5762e
AP		 4340 /* Only allow emulation of specific instructions on #UD
4341 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4342 if (emulation_type & EMULTYPE_TRAP_UD) {
4343 if (!c->twobyte)
4344 return EMULATE_FAIL;
4345 switch (c->b) {
4346 case 0x01: /* VMMCALL */
4347 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4348 return EMULATE_FAIL;
4349 break;
4350 case 0x34: /* sysenter */
4351 case 0x35: /* sysexit */
4352 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4353 return EMULATE_FAIL;
4354 break;
4355 case 0x05: /* syscall */
4356 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4357 return EMULATE_FAIL;
4358 break;
4359 default:
4360 return EMULATE_FAIL;
4361 }
4362
4363 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4364 return EMULATE_FAIL;
4365 }
571008da 4366
f2b5756b 4367 ++vcpu->stat.insn_emulation;
bbd9b64e 4368 if (r) {
a6f177ef 4369 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4370 return EMULATE_DONE;
6d77dbfc
GN		 4371 if (emulation_type & EMULTYPE_SKIP)
4372 return EMULATE_FAIL;
4373 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4374 }
4375 }
4376
ba8afb6b
GN		 4377 if (emulation_type & EMULTYPE_SKIP) {
4378 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4379 return EMULATE_DONE;
4380 }
4381
4d2179e1
GN		 4382 /* this is needed for vmware backdor interface to work since it
4383 changes registers values during IO operation */
4384 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4385
5cd21917 4386restart:
9aabc88f 4387 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4388
d2ddd1c4 4389 if (r == EMULATION_FAILED) {
a6f177ef 4390 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4391 return EMULATE_DONE;
4392
6d77dbfc 4393 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4394 }
4395
d47f00a6 4396done:
54b8486f
GN		 4397 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4398 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4399 r = EMULATE_DONE;
4400 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4401 if (!vcpu->arch.pio.in)
4402 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4403 r = EMULATE_DO_MMIO;
4404 } else if (vcpu->mmio_needed) {
3457e419
GN		 4405 if (vcpu->mmio_is_write)
4406 vcpu->mmio_needed = 0;
e85d28f8 4407 r = EMULATE_DO_MMIO;
d2ddd1c4 4408 } else if (r == EMULATION_RESTART)
5cd21917 4409 goto restart;
d2ddd1c4
GN		 4410 else
4411 r = EMULATE_DONE;
f850e2e6 4412
e85d28f8
GN		 4413 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4414 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4415 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4416 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4417 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4418
4419 return r;
de7d789a 4420}
bbd9b64e 4421EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4422
cf8f70bf 4423int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4424{
cf8f70bf
GN		 4425 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4426 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4427 /* do not return to emulator after return from userspace */
7972995b 4428 vcpu->arch.pio.count = 0;
de7d789a
CO		 4429 return ret;
4430}
cf8f70bf 4431EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4432
8cfdc000
ZA		 4433static void tsc_bad(void *info)
4434{
4435 __get_cpu_var(cpu_tsc_khz) = 0;
4436}
4437
4438static void tsc_khz_changed(void *data)
c8076604 4439{
8cfdc000
ZA		 4440 struct cpufreq_freqs *freq = data;
4441 unsigned long khz = 0;
4442
4443 if (data)
4444 khz = freq->new;
4445 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4446 khz = cpufreq_quick_get(raw_smp_processor_id());
4447 if (!khz)
4448 khz = tsc_khz;
4449 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4450}
4451
c8076604
GH		 4452static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4453 void *data)
4454{
4455 struct cpufreq_freqs *freq = data;
4456 struct kvm *kvm;
4457 struct kvm_vcpu *vcpu;
4458 int i, send_ipi = 0;
4459
8cfdc000
ZA		 4460 /*
4461 * We allow guests to temporarily run on slowing clocks,
4462 * provided we notify them after, or to run on accelerating
4463 * clocks, provided we notify them before. Thus time never
4464 * goes backwards.
4465 *
4466 * However, we have a problem. We can't atomically update
4467 * the frequency of a given CPU from this function; it is
4468 * merely a notifier, which can be called from any CPU.
4469 * Changing the TSC frequency at arbitrary points in time
4470 * requires a recomputation of local variables related to
4471 * the TSC for each VCPU. We must flag these local variables
4472 * to be updated and be sure the update takes place with the
4473 * new frequency before any guests proceed.
4474 *
4475 * Unfortunately, the combination of hotplug CPU and frequency
4476 * change creates an intractable locking scenario; the order
4477 * of when these callouts happen is undefined with respect to
4478 * CPU hotplug, and they can race with each other. As such,
4479 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4480 * undefined; you can actually have a CPU frequency change take
4481 * place in between the computation of X and the setting of the
4482 * variable. To protect against this problem, all updates of
4483 * the per_cpu tsc_khz variable are done in an interrupt
4484 * protected IPI, and all callers wishing to update the value
4485 * must wait for a synchronous IPI to complete (which is trivial
4486 * if the caller is on the CPU already). This establishes the
4487 * necessary total order on variable updates.
4488 *
4489 * Note that because a guest time update may take place
4490 * anytime after the setting of the VCPU's request bit, the
4491 * correct TSC value must be set before the request. However,
4492 * to ensure the update actually makes it to any guest which
4493 * starts running in hardware virtualization between the set
4494 * and the acquisition of the spinlock, we must also ping the
4495 * CPU after setting the request bit.
4496 *
4497 */
4498
c8076604
GH		 4499 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4500 return 0;
4501 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4502 return 0;
8cfdc000
ZA		 4503
4504 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4505
4506 spin_lock(&kvm_lock);
4507 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4508 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4509 if (vcpu->cpu != freq->cpu)
4510 continue;
c285545f 4511 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4512 if (vcpu->cpu != smp_processor_id())
8cfdc000 4513 send_ipi = 1;
c8076604
GH		 4514 }
4515 }
4516 spin_unlock(&kvm_lock);
4517
4518 if (freq->old < freq->new && send_ipi) {
4519 /*
4520 * We upscale the frequency. Must make the guest
4521 * doesn't see old kvmclock values while running with
4522 * the new frequency, otherwise we risk the guest sees
4523 * time go backwards.
4524 *
4525 * In case we update the frequency for another cpu
4526 * (which might be in guest context) send an interrupt
4527 * to kick the cpu out of guest context. Next time
4528 * guest context is entered kvmclock will be updated,
4529 * so the guest will not see stale values.
4530 */
8cfdc000 4531 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4532 }
4533 return 0;
4534}
4535
4536static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4537 .notifier_call = kvmclock_cpufreq_notifier
4538};
4539
4540static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4541 unsigned long action, void *hcpu)
4542{
4543 unsigned int cpu = (unsigned long)hcpu;
4544
4545 switch (action) {
4546 case CPU_ONLINE:
4547 case CPU_DOWN_FAILED:
4548 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4549 break;
4550 case CPU_DOWN_PREPARE:
4551 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4552 break;
4553 }
4554 return NOTIFY_OK;
4555}
4556
4557static struct notifier_block kvmclock_cpu_notifier_block = {
4558 .notifier_call = kvmclock_cpu_notifier,
4559 .priority = -INT_MAX
c8076604
GH		 4560};
4561
b820cc0c
ZA		 4562static void kvm_timer_init(void)
4563{
4564 int cpu;
4565
c285545f 4566 max_tsc_khz = tsc_khz;
8cfdc000 4567 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4568 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4569#ifdef CONFIG_CPU_FREQ
4570 struct cpufreq_policy policy;
4571 memset(&policy, 0, sizeof(policy));
4572 cpufreq_get_policy(&policy, get_cpu());
4573 if (policy.cpuinfo.max_freq)
4574 max_tsc_khz = policy.cpuinfo.max_freq;
4575#endif
b820cc0c
ZA		 4576 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4577 CPUFREQ_TRANSITION_NOTIFIER);
4578 }
c285545f 4579 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4580 for_each_online_cpu(cpu)
4581 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4582}
4583
ff9d07a0
ZY		 4584static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4585
4586static int kvm_is_in_guest(void)
4587{
4588 return percpu_read(current_vcpu) != NULL;
4589}
4590
4591static int kvm_is_user_mode(void)
4592{
4593 int user_mode = 3;
dcf46b94 4594
ff9d07a0
ZY		 4595 if (percpu_read(current_vcpu))
4596 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4597
ff9d07a0
ZY		 4598 return user_mode != 0;
4599}
4600
4601static unsigned long kvm_get_guest_ip(void)
4602{
4603 unsigned long ip = 0;
dcf46b94 4604
ff9d07a0
ZY		 4605 if (percpu_read(current_vcpu))
4606 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4607
ff9d07a0
ZY		 4608 return ip;
4609}
4610
4611static struct perf_guest_info_callbacks kvm_guest_cbs = {
4612 .is_in_guest = kvm_is_in_guest,
4613 .is_user_mode = kvm_is_user_mode,
4614 .get_guest_ip = kvm_get_guest_ip,
4615};
4616
4617void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4618{
4619 percpu_write(current_vcpu, vcpu);
4620}
4621EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4622
4623void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4624{
4625 percpu_write(current_vcpu, NULL);
4626}
4627EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4628
f8c16bba 4629int kvm_arch_init(void *opaque)
043405e1 4630{
b820cc0c 4631 int r;
f8c16bba
ZX		 4632 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4633
f8c16bba
ZX		 4634 if (kvm_x86_ops) {
4635 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4636 r = -EEXIST;
4637 goto out;
f8c16bba
ZX		 4638 }
4639
4640 if (!ops->cpu_has_kvm_support()) {
4641 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4642 r = -EOPNOTSUPP;
4643 goto out;
f8c16bba
ZX		 4644 }
4645 if (ops->disabled_by_bios()) {
4646 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4647 r = -EOPNOTSUPP;
4648 goto out;
f8c16bba
ZX		 4649 }
4650
97db56ce
AK		 4651 r = kvm_mmu_module_init();
4652 if (r)
4653 goto out;
4654
4655 kvm_init_msr_list();
4656
f8c16bba 4657 kvm_x86_ops = ops;
56c6d28a 4658 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4659 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4660 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4661 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4662
b820cc0c 4663 kvm_timer_init();
c8076604 4664
ff9d07a0
ZY		 4665 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4666
2acf923e
DC		 4667 if (cpu_has_xsave)
4668 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4669
f8c16bba 4670 return 0;
56c6d28a
ZX		 4671
4672out:
56c6d28a 4673 return r;
043405e1 4674}
8776e519 4675
f8c16bba
ZX		 4676void kvm_arch_exit(void)
4677{
ff9d07a0
ZY		 4678 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4679
888d256e
JK		 4680 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4681 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4682 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4683 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4684 kvm_x86_ops = NULL;
56c6d28a
ZX		 4685 kvm_mmu_module_exit();
4686}
f8c16bba 4687
8776e519
HB		 4688int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4689{
4690 ++vcpu->stat.halt_exits;
4691 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4692 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4693 return 1;
4694 } else {
4695 vcpu->run->exit_reason = KVM_EXIT_HLT;
4696 return 0;
4697 }
4698}
4699EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4700
2f333bcb
MT		 4701static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4702 unsigned long a1)
4703{
4704 if (is_long_mode(vcpu))
4705 return a0;
4706 else
4707 return a0 | ((gpa_t)a1 << 32);
4708}
4709
55cd8e5a
GN		 4710int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4711{
4712 u64 param, ingpa, outgpa, ret;
4713 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4714 bool fast, longmode;
4715 int cs_db, cs_l;
4716
4717 /*
4718 * hypercall generates UD from non zero cpl and real mode
4719 * per HYPER-V spec
4720 */
3eeb3288 4721 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4722 kvm_queue_exception(vcpu, UD_VECTOR);
4723 return 0;
4724 }
4725
4726 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4727 longmode = is_long_mode(vcpu) && cs_l == 1;
4728
4729 if (!longmode) {
ccd46936
GN		 4730 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4731 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4732 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4733 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4734 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4735 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4736 }
4737#ifdef CONFIG_X86_64
4738 else {
4739 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4740 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4741 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4742 }
4743#endif
4744
4745 code = param & 0xffff;
4746 fast = (param >> 16) & 0x1;
4747 rep_cnt = (param >> 32) & 0xfff;
4748 rep_idx = (param >> 48) & 0xfff;
4749
4750 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4751
c25bc163
GN		 4752 switch (code) {
4753 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4754 kvm_vcpu_on_spin(vcpu);
4755 break;
4756 default:
4757 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4758 break;
4759 }
55cd8e5a
GN		 4760
4761 ret = res | (((u64)rep_done & 0xfff) << 32);
4762 if (longmode) {
4763 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4764 } else {
4765 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4766 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4767 }
4768
4769 return 1;
4770}
4771
8776e519
HB		 4772int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4773{
4774 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4775 int r = 1;
8776e519 4776
55cd8e5a
GN		 4777 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4778 return kvm_hv_hypercall(vcpu);
4779
5fdbf976
MT		 4780 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4781 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4782 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4783 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4784 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4785
229456fc 4786 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4787
8776e519
HB		 4788 if (!is_long_mode(vcpu)) {
4789 nr &= 0xFFFFFFFF;
4790 a0 &= 0xFFFFFFFF;
4791 a1 &= 0xFFFFFFFF;
4792 a2 &= 0xFFFFFFFF;
4793 a3 &= 0xFFFFFFFF;
4794 }
4795
07708c4a
JK		 4796 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4797 ret = -KVM_EPERM;
4798 goto out;
4799 }
4800
8776e519 4801 switch (nr) {
b93463aa
AK		 4802 case KVM_HC_VAPIC_POLL_IRQ:
4803 ret = 0;
4804 break;
2f333bcb
MT		 4805 case KVM_HC_MMU_OP:
4806 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4807 break;
8776e519
HB		 4808 default:
4809 ret = -KVM_ENOSYS;
4810 break;
4811 }
07708c4a 4812out:
5fdbf976 4813 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4814 ++vcpu->stat.hypercalls;
2f333bcb 4815 return r;
8776e519
HB		 4816}
4817EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4818
4819int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4820{
4821 char instruction[3];
5fdbf976 4822 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4823
8776e519
HB		 4824 /*
4825 * Blow out the MMU to ensure that no other VCPU has an active mapping
4826 * to ensure that the updated hypercall appears atomically across all
4827 * VCPUs.
4828 */
4829 kvm_mmu_zap_all(vcpu->kvm);
4830
8776e519 4831 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4832
8fe681e9 4833 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4834}
4835
8776e519
HB		 4836void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4837{
89a27f4d 4838 struct desc_ptr dt = { limit, base };
8776e519
HB		 4839
4840 kvm_x86_ops->set_gdt(vcpu, &dt);
4841}
4842
4843void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4844{
89a27f4d 4845 struct desc_ptr dt = { limit, base };
8776e519
HB		 4846
4847 kvm_x86_ops->set_idt(vcpu, &dt);
4848}
4849
07716717
DK		 4850static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4851{
ad312c7c
ZX		 4852 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4853 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4854
4855 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4856 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4857 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4858 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4859 if (ej->function == e->function) {
4860 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4861 return j;
4862 }
4863 }
4864 return 0; /* silence gcc, even though control never reaches here */
4865}
4866
4867/* find an entry with matching function, matching index (if needed), and that
4868 * should be read next (if it's stateful) */
4869static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4870 u32 function, u32 index)
4871{
4872 if (e->function != function)
4873 return 0;
4874 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4875 return 0;
4876 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4877 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4878 return 0;
4879 return 1;
4880}
4881
d8017474
AG		 4882struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4883 u32 function, u32 index)
8776e519
HB		 4884{
4885 int i;
d8017474 4886 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4887
ad312c7c 4888 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4889 struct kvm_cpuid_entry2 *e;
4890
ad312c7c 4891 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4892 if (is_matching_cpuid_entry(e, function, index)) {
4893 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4894 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4895 best = e;
4896 break;
4897 }
4898 /*
4899 * Both basic or both extended?
4900 */
4901 if (((e->function ^ function) & 0x80000000) == 0)
4902 if (!best || e->function > best->function)
4903 best = e;
4904 }
d8017474
AG		 4905 return best;
4906}
0e851880 4907EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4908
82725b20
DE		 4909int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4910{
4911 struct kvm_cpuid_entry2 *best;
4912
f7a71197
AK		 4913 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4914 if (!best || best->eax < 0x80000008)
4915 goto not_found;
82725b20
DE		 4916 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4917 if (best)
4918 return best->eax & 0xff;
f7a71197 4919not_found:
82725b20
DE		 4920 return 36;
4921}
4922
d8017474
AG		 4923void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4924{
4925 u32 function, index;
4926 struct kvm_cpuid_entry2 *best;
4927
4928 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4929 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4930 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4931 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4932 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4933 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4934 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4935 if (best) {
5fdbf976
MT		 4936 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4937 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4938 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4939 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4940 }
8776e519 4941 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4942 trace_kvm_cpuid(function,
4943 kvm_register_read(vcpu, VCPU_REGS_RAX),
4944 kvm_register_read(vcpu, VCPU_REGS_RBX),
4945 kvm_register_read(vcpu, VCPU_REGS_RCX),
4946 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4947}
4948EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4949
b6c7a5dc
HB		 4950/*
4951 * Check if userspace requested an interrupt window, and that the
4952 * interrupt window is open.
4953 *
4954 * No need to exit to userspace if we already have an interrupt queued.
4955 */
851ba692 4956static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4957{
8061823a 4958 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4959 vcpu->run->request_interrupt_window &&
5df56646 4960 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4961}
4962
851ba692 4963static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4964{
851ba692
AK		 4965 struct kvm_run *kvm_run = vcpu->run;
4966
91586a3b 4967 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4968 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4969 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4970 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4971 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4972 else
b6c7a5dc 4973 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4974 kvm_arch_interrupt_allowed(vcpu) &&
4975 !kvm_cpu_has_interrupt(vcpu) &&
4976 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4977}
4978
b93463aa
AK		 4979static void vapic_enter(struct kvm_vcpu *vcpu)
4980{
4981 struct kvm_lapic *apic = vcpu->arch.apic;
4982 struct page *page;
4983
4984 if (!apic || !apic->vapic_addr)
4985 return;
4986
4987 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4988
4989 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4990}
4991
4992static void vapic_exit(struct kvm_vcpu *vcpu)
4993{
4994 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4995 int idx;
b93463aa
AK		 4996
4997 if (!apic || !apic->vapic_addr)
4998 return;
4999
f656ce01 5000 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5001 kvm_release_page_dirty(apic->vapic_page);
5002 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5003 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5004}
5005
95ba8273
GN		 5006static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5007{
5008 int max_irr, tpr;
5009
5010 if (!kvm_x86_ops->update_cr8_intercept)
5011 return;
5012
88c808fd
AK		 5013 if (!vcpu->arch.apic)
5014 return;
5015
8db3baa2
GN		 5016 if (!vcpu->arch.apic->vapic_addr)
5017 max_irr = kvm_lapic_find_highest_irr(vcpu);
5018 else
5019 max_irr = -1;
95ba8273
GN		 5020
5021 if (max_irr != -1)
5022 max_irr >>= 4;
5023
5024 tpr = kvm_lapic_get_cr8(vcpu);
5025
5026 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5027}
5028
851ba692 5029static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5030{
5031 /* try to reinject previous events if any */
b59bb7bd 5032 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5033 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5034 vcpu->arch.exception.has_error_code,
5035 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5036 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5037 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5038 vcpu->arch.exception.error_code,
5039 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5040 return;
5041 }
5042
95ba8273
GN		 5043 if (vcpu->arch.nmi_injected) {
5044 kvm_x86_ops->set_nmi(vcpu);
5045 return;
5046 }
5047
5048 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5049 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5050 return;
5051 }
5052
5053 /* try to inject new event if pending */
5054 if (vcpu->arch.nmi_pending) {
5055 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5056 vcpu->arch.nmi_pending = false;
5057 vcpu->arch.nmi_injected = true;
5058 kvm_x86_ops->set_nmi(vcpu);
5059 }
5060 } else if (kvm_cpu_has_interrupt(vcpu)) {
5061 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5062 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5063 false);
5064 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5065 }
5066 }
5067}
5068
2acf923e
DC		 5069static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5070{
5071 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5072 !vcpu->guest_xcr0_loaded) {
5073 /* kvm_set_xcr() also depends on this */
5074 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5075 vcpu->guest_xcr0_loaded = 1;
5076 }
5077}
5078
5079static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5080{
5081 if (vcpu->guest_xcr0_loaded) {
5082 if (vcpu->arch.xcr0 != host_xcr0)
5083 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5084 vcpu->guest_xcr0_loaded = 0;
5085 }
5086}
5087
851ba692 5088static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5089{
5090 int r;
6a8b1d13 5091 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5092 vcpu->run->request_interrupt_window;
b6c7a5dc 5093
3e007509 5094 if (vcpu->requests) {
a8eeb04a 5095 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5096 kvm_mmu_unload(vcpu);
a8eeb04a 5097 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5098 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5099 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5100 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5101 if (unlikely(r))
5102 goto out;
5103 }
a8eeb04a 5104 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5105 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5106 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5107 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5108 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5109 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5110 r = 0;
5111 goto out;
5112 }
a8eeb04a 5113 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5114 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5115 r = 0;
5116 goto out;
5117 }
a8eeb04a 5118 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5119 vcpu->fpu_active = 0;
5120 kvm_x86_ops->fpu_deactivate(vcpu);
5121 }
2f52d58c 5122 }
b93463aa 5123
3e007509
AK		 5124 r = kvm_mmu_reload(vcpu);
5125 if (unlikely(r))
5126 goto out;
5127
b463a6f7
AK		 5128 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5129 inject_pending_event(vcpu);
5130
5131 /* enable NMI/IRQ window open exits if needed */
5132 if (vcpu->arch.nmi_pending)
5133 kvm_x86_ops->enable_nmi_window(vcpu);
5134 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5135 kvm_x86_ops->enable_irq_window(vcpu);
5136
5137 if (kvm_lapic_enabled(vcpu)) {
5138 update_cr8_intercept(vcpu);
5139 kvm_lapic_sync_to_vapic(vcpu);
5140 }
5141 }
5142
b6c7a5dc
HB		 5143 preempt_disable();
5144
5145 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5146 if (vcpu->fpu_active)
5147 kvm_load_guest_fpu(vcpu);
2acf923e 5148 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5149
d94e1dc9
AK		 5150 atomic_set(&vcpu->guest_mode, 1);
5151 smp_wmb();
b6c7a5dc 5152
d94e1dc9 5153 local_irq_disable();
32f88400 5154
d94e1dc9
AK		 5155 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5156 || need_resched() || signal_pending(current)) {
5157 atomic_set(&vcpu->guest_mode, 0);
5158 smp_wmb();
6c142801
AK		 5159 local_irq_enable();
5160 preempt_enable();
b463a6f7 5161 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5162 r = 1;
5163 goto out;
5164 }
5165
f656ce01 5166 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5167
b6c7a5dc
HB		 5168 kvm_guest_enter();
5169
42dbaa5a 5170 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5171 set_debugreg(0, 7);
5172 set_debugreg(vcpu->arch.eff_db[0], 0);
5173 set_debugreg(vcpu->arch.eff_db[1], 1);
5174 set_debugreg(vcpu->arch.eff_db[2], 2);
5175 set_debugreg(vcpu->arch.eff_db[3], 3);
5176 }
b6c7a5dc 5177
229456fc 5178 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5179 kvm_x86_ops->run(vcpu);
b6c7a5dc 5180
24f1e32c
FW		 5181 /*
5182 * If the guest has used debug registers, at least dr7
5183 * will be disabled while returning to the host.
5184 * If we don't have active breakpoints in the host, we don't
5185 * care about the messed up debug address registers. But if
5186 * we have some of them active, restore the old state.
5187 */
59d8eb53 5188 if (hw_breakpoint_active())
24f1e32c 5189 hw_breakpoint_restore();
42dbaa5a 5190
1d5f066e
ZA		 5191 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5192
d94e1dc9
AK		 5193 atomic_set(&vcpu->guest_mode, 0);
5194 smp_wmb();
b6c7a5dc
HB		 5195 local_irq_enable();
5196
5197 ++vcpu->stat.exits;
5198
5199 /*
5200 * We must have an instruction between local_irq_enable() and
5201 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5202 * the interrupt shadow. The stat.exits increment will do nicely.
5203 * But we need to prevent reordering, hence this barrier():
5204 */
5205 barrier();
5206
5207 kvm_guest_exit();
5208
5209 preempt_enable();
5210
f656ce01 5211 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5212
b6c7a5dc
HB		 5213 /*
5214 * Profile KVM exit RIPs:
5215 */
5216 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5217 unsigned long rip = kvm_rip_read(vcpu);
5218 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5219 }
5220
298101da 5221
b93463aa
AK		 5222 kvm_lapic_sync_from_vapic(vcpu);
5223
851ba692 5224 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5225out:
5226 return r;
5227}
b6c7a5dc 5228
09cec754 5229
851ba692 5230static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5231{
5232 int r;
f656ce01 5233 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5234
5235 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5236 pr_debug("vcpu %d received sipi with vector # %x\n",
5237 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5238 kvm_lapic_reset(vcpu);
5f179287 5239 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5240 if (r)
5241 return r;
5242 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5243 }
5244
f656ce01 5245 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5246 vapic_enter(vcpu);
5247
5248 r = 1;
5249 while (r > 0) {
af2152f5 5250 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5251 r = vcpu_enter_guest(vcpu);
d7690175 5252 else {
f656ce01 5253 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5254 kvm_vcpu_block(vcpu);
f656ce01 5255 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5256 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5257 {
5258 switch(vcpu->arch.mp_state) {
5259 case KVM_MP_STATE_HALTED:
d7690175 5260 vcpu->arch.mp_state =
09cec754
GN		 5261 KVM_MP_STATE_RUNNABLE;
5262 case KVM_MP_STATE_RUNNABLE:
5263 break;
5264 case KVM_MP_STATE_SIPI_RECEIVED:
5265 default:
5266 r = -EINTR;
5267 break;
5268 }
5269 }
d7690175
MT		 5270 }
5271
09cec754
GN		 5272 if (r <= 0)
5273 break;
5274
5275 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5276 if (kvm_cpu_has_pending_timer(vcpu))
5277 kvm_inject_pending_timer_irqs(vcpu);
5278
851ba692 5279 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5280 r = -EINTR;
851ba692 5281 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5282 ++vcpu->stat.request_irq_exits;
5283 }
5284 if (signal_pending(current)) {
5285 r = -EINTR;
851ba692 5286 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5287 ++vcpu->stat.signal_exits;
5288 }
5289 if (need_resched()) {
f656ce01 5290 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5291 kvm_resched(vcpu);
f656ce01 5292 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5293 }
b6c7a5dc
HB		 5294 }
5295
f656ce01 5296 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5297
b93463aa
AK		 5298 vapic_exit(vcpu);
5299
b6c7a5dc
HB		 5300 return r;
5301}
5302
5303int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5304{
5305 int r;
5306 sigset_t sigsaved;
5307
ac9f6dc0
AK		 5308 if (vcpu->sigset_active)
5309 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5310
a4535290 5311 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5312 kvm_vcpu_block(vcpu);
d7690175 5313 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5314 r = -EAGAIN;
5315 goto out;
b6c7a5dc
HB		 5316 }
5317
b6c7a5dc
HB		 5318 /* re-sync apic's tpr */
5319 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5320 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5321
d2ddd1c4 5322 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5323 if (vcpu->mmio_needed) {
5324 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5325 vcpu->mmio_read_completed = 1;
5326 vcpu->mmio_needed = 0;
b6c7a5dc 5327 }
f656ce01 5328 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5329 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5330 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5331 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5332 r = 0;
5333 goto out;
5334 }
5335 }
5fdbf976
MT		 5336 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5337 kvm_register_write(vcpu, VCPU_REGS_RAX,
5338 kvm_run->hypercall.ret);
b6c7a5dc 5339
851ba692 5340 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5341
5342out:
f1d86e46 5343 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5344 if (vcpu->sigset_active)
5345 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5346
b6c7a5dc
HB		 5347 return r;
5348}
5349
5350int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5351{
5fdbf976
MT		 5352 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5353 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5354 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5355 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5356 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5357 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5358 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5359 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5360#ifdef CONFIG_X86_64
5fdbf976
MT		 5361 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5362 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5363 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5364 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5365 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5366 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5367 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5368 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5369#endif
5370
5fdbf976 5371 regs->rip = kvm_rip_read(vcpu);
91586a3b 5372 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5373
b6c7a5dc
HB		 5374 return 0;
5375}
5376
5377int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5378{
5fdbf976
MT		 5379 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5380 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5381 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5382 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5383 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5384 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5385 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5386 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5387#ifdef CONFIG_X86_64
5fdbf976
MT		 5388 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5389 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5390 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5391 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5392 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5393 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5394 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5395 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5396#endif
5397
5fdbf976 5398 kvm_rip_write(vcpu, regs->rip);
91586a3b 5399 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5400
b4f14abd
JK		 5401 vcpu->arch.exception.pending = false;
5402
3842d135
AK		 5403 kvm_make_request(KVM_REQ_EVENT, vcpu);
5404
b6c7a5dc
HB		 5405 return 0;
5406}
5407
b6c7a5dc
HB		 5408void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5409{
5410 struct kvm_segment cs;
5411
3e6e0aab 5412 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5413 *db = cs.db;
5414 *l = cs.l;
5415}
5416EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5417
5418int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5419 struct kvm_sregs *sregs)
5420{
89a27f4d 5421 struct desc_ptr dt;
b6c7a5dc 5422
3e6e0aab
GT		 5423 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5424 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5425 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5426 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5427 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5428 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5429
3e6e0aab
GT		 5430 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5431 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5432
5433 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5434 sregs->idt.limit = dt.size;
5435 sregs->idt.base = dt.address;
b6c7a5dc 5436 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5437 sregs->gdt.limit = dt.size;
5438 sregs->gdt.base = dt.address;
b6c7a5dc 5439
4d4ec087 5440 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5441 sregs->cr2 = vcpu->arch.cr2;
5442 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5443 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5444 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5445 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5446 sregs->apic_base = kvm_get_apic_base(vcpu);
5447
923c61bb 5448 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5449
36752c9b 5450 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5451 set_bit(vcpu->arch.interrupt.nr,
5452 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5453
b6c7a5dc
HB		 5454 return 0;
5455}
5456
62d9f0db
MT		 5457int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5458 struct kvm_mp_state *mp_state)
5459{
62d9f0db 5460 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5461 return 0;
5462}
5463
5464int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5465 struct kvm_mp_state *mp_state)
5466{
62d9f0db 5467 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5468 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5469 return 0;
5470}
5471
e269fb21
JK		 5472int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5473 bool has_error_code, u32 error_code)
b6c7a5dc 5474{
4d2179e1 5475 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5476 int ret;
e01c2426 5477
8ec4722d 5478 init_emulate_ctxt(vcpu);
c697518a 5479
9aabc88f 5480 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5481 tss_selector, reason, has_error_code,
5482 error_code);
c697518a 5483
c697518a 5484 if (ret)
19d04437 5485 return EMULATE_FAIL;
37817f29 5486
4d2179e1 5487 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5488 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5489 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5490 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5491 return EMULATE_DONE;
37817f29
IE		 5492}
5493EXPORT_SYMBOL_GPL(kvm_task_switch);
5494
b6c7a5dc
HB		 5495int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5496 struct kvm_sregs *sregs)
5497{
5498 int mmu_reset_needed = 0;
923c61bb 5499 int pending_vec, max_bits;
89a27f4d 5500 struct desc_ptr dt;
b6c7a5dc 5501
89a27f4d
GN		 5502 dt.size = sregs->idt.limit;
5503 dt.address = sregs->idt.base;
b6c7a5dc 5504 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5505 dt.size = sregs->gdt.limit;
5506 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5507 kvm_x86_ops->set_gdt(vcpu, &dt);
5508
ad312c7c
ZX		 5509 vcpu->arch.cr2 = sregs->cr2;
5510 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5511 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5512
2d3ad1f4 5513 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5514
f6801dff 5515 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5516 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5517 kvm_set_apic_base(vcpu, sregs->apic_base);
5518
4d4ec087 5519 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5520 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5521 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5522
fc78f519 5523 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5524 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5525 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5526 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5527 mmu_reset_needed = 1;
5528 }
b6c7a5dc
HB		 5529
5530 if (mmu_reset_needed)
5531 kvm_mmu_reset_context(vcpu);
5532
923c61bb
GN		 5533 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5534 pending_vec = find_first_bit(
5535 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5536 if (pending_vec < max_bits) {
66fd3f7f 5537 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5538 pr_debug("Set back pending irq %d\n", pending_vec);
5539 if (irqchip_in_kernel(vcpu->kvm))
5540 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5541 }
5542
3e6e0aab
GT		 5543 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5544 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5545 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5546 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5547 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5548 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5549
3e6e0aab
GT		 5550 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5551 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5552
5f0269f5
ME		 5553 update_cr8_intercept(vcpu);
5554
9c3e4aab 5555 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5556 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5557 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5558 !is_protmode(vcpu))
9c3e4aab
MT		 5559 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5560
3842d135
AK		 5561 kvm_make_request(KVM_REQ_EVENT, vcpu);
5562
b6c7a5dc
HB		 5563 return 0;
5564}
5565
d0bfb940
JK		 5566int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5567 struct kvm_guest_debug *dbg)
b6c7a5dc 5568{
355be0b9 5569 unsigned long rflags;
ae675ef0 5570 int i, r;
b6c7a5dc 5571
4f926bf2
JK		 5572 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5573 r = -EBUSY;
5574 if (vcpu->arch.exception.pending)
2122ff5e 5575 goto out;
4f926bf2
JK		 5576 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5577 kvm_queue_exception(vcpu, DB_VECTOR);
5578 else
5579 kvm_queue_exception(vcpu, BP_VECTOR);
5580 }
5581
91586a3b
JK		 5582 /*
5583 * Read rflags as long as potentially injected trace flags are still
5584 * filtered out.
5585 */
5586 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5587
5588 vcpu->guest_debug = dbg->control;
5589 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5590 vcpu->guest_debug = 0;
5591
5592 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5593 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5594 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5595 vcpu->arch.switch_db_regs =
5596 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5597 } else {
5598 for (i = 0; i < KVM_NR_DB_REGS; i++)
5599 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5600 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5601 }
5602
f92653ee
JK		 5603 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5604 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5605 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5606
91586a3b
JK		 5607 /*
5608 * Trigger an rflags update that will inject or remove the trace
5609 * flags.
5610 */
5611 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5612
355be0b9 5613 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5614
4f926bf2 5615 r = 0;
d0bfb940 5616
2122ff5e 5617out:
b6c7a5dc
HB		 5618
5619 return r;
5620}
5621
8b006791
ZX		 5622/*
5623 * Translate a guest virtual address to a guest physical address.
5624 */
5625int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5626 struct kvm_translation *tr)
5627{
5628 unsigned long vaddr = tr->linear_address;
5629 gpa_t gpa;
f656ce01 5630 int idx;
8b006791 5631
f656ce01 5632 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5633 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5634 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5635 tr->physical_address = gpa;
5636 tr->valid = gpa != UNMAPPED_GVA;
5637 tr->writeable = 1;
5638 tr->usermode = 0;
8b006791
ZX		 5639
5640 return 0;
5641}
5642
d0752060
HB		 5643int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5644{
98918833
SY		 5645 struct i387_fxsave_struct *fxsave =
5646 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5647
d0752060
HB		 5648 memcpy(fpu->fpr, fxsave->st_space, 128);
5649 fpu->fcw = fxsave->cwd;
5650 fpu->fsw = fxsave->swd;
5651 fpu->ftwx = fxsave->twd;
5652 fpu->last_opcode = fxsave->fop;
5653 fpu->last_ip = fxsave->rip;
5654 fpu->last_dp = fxsave->rdp;
5655 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5656
d0752060
HB		 5657 return 0;
5658}
5659
5660int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5661{
98918833
SY		 5662 struct i387_fxsave_struct *fxsave =
5663 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5664
d0752060
HB		 5665 memcpy(fxsave->st_space, fpu->fpr, 128);
5666 fxsave->cwd = fpu->fcw;
5667 fxsave->swd = fpu->fsw;
5668 fxsave->twd = fpu->ftwx;
5669 fxsave->fop = fpu->last_opcode;
5670 fxsave->rip = fpu->last_ip;
5671 fxsave->rdp = fpu->last_dp;
5672 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5673
d0752060
HB		 5674 return 0;
5675}
5676
10ab25cd 5677int fx_init(struct kvm_vcpu *vcpu)
d0752060 5678{
10ab25cd
JK		 5679 int err;
5680
5681 err = fpu_alloc(&vcpu->arch.guest_fpu);
5682 if (err)
5683 return err;
5684
98918833 5685 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5686
2acf923e
DC		 5687 /*
5688 * Ensure guest xcr0 is valid for loading
5689 */
5690 vcpu->arch.xcr0 = XSTATE_FP;
5691
ad312c7c 5692 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5693
5694 return 0;
d0752060
HB		 5695}
5696EXPORT_SYMBOL_GPL(fx_init);
5697
98918833
SY		 5698static void fx_free(struct kvm_vcpu *vcpu)
5699{
5700 fpu_free(&vcpu->arch.guest_fpu);
5701}
5702
d0752060
HB		 5703void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5704{
2608d7a1 5705 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5706 return;
5707
2acf923e
DC		 5708 /*
5709 * Restore all possible states in the guest,
5710 * and assume host would use all available bits.
5711 * Guest xcr0 would be loaded later.
5712 */
5713 kvm_put_guest_xcr0(vcpu);
d0752060 5714 vcpu->guest_fpu_loaded = 1;
7cf30855 5715 unlazy_fpu(current);
98918833 5716 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5717 trace_kvm_fpu(1);
d0752060 5718}
d0752060
HB		 5719
5720void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5721{
2acf923e
DC		 5722 kvm_put_guest_xcr0(vcpu);
5723
d0752060
HB		 5724 if (!vcpu->guest_fpu_loaded)
5725 return;
5726
5727 vcpu->guest_fpu_loaded = 0;
98918833 5728 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5729 ++vcpu->stat.fpu_reload;
a8eeb04a 5730 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5731 trace_kvm_fpu(0);
d0752060 5732}
e9b11c17
ZX		 5733
5734void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5735{
7f1ea208
JR		 5736 if (vcpu->arch.time_page) {
5737 kvm_release_page_dirty(vcpu->arch.time_page);
5738 vcpu->arch.time_page = NULL;
5739 }
5740
f5f48ee1 5741 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5742 fx_free(vcpu);
e9b11c17
ZX		 5743 kvm_x86_ops->vcpu_free(vcpu);
5744}
5745
5746struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5747 unsigned int id)
5748{
6755bae8
ZA		 5749 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5750 printk_once(KERN_WARNING
5751 "kvm: SMP vm created on host with unstable TSC; "
5752 "guest TSC will not be reliable\n");
26e5215f
AK		 5753 return kvm_x86_ops->vcpu_create(kvm, id);
5754}
e9b11c17 5755
26e5215f
AK		 5756int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5757{
5758 int r;
e9b11c17 5759
0bed3b56 5760 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5761 vcpu_load(vcpu);
5762 r = kvm_arch_vcpu_reset(vcpu);
5763 if (r == 0)
5764 r = kvm_mmu_setup(vcpu);
5765 vcpu_put(vcpu);
5766 if (r < 0)
5767 goto free_vcpu;
5768
26e5215f 5769 return 0;
e9b11c17
ZX		 5770free_vcpu:
5771 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5772 return r;
e9b11c17
ZX		 5773}
5774
d40ccc62 5775void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5776{
5777 vcpu_load(vcpu);
5778 kvm_mmu_unload(vcpu);
5779 vcpu_put(vcpu);
5780
98918833 5781 fx_free(vcpu);
e9b11c17
ZX		 5782 kvm_x86_ops->vcpu_free(vcpu);
5783}
5784
5785int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5786{
448fa4a9
JK		 5787 vcpu->arch.nmi_pending = false;
5788 vcpu->arch.nmi_injected = false;
5789
42dbaa5a
JK		 5790 vcpu->arch.switch_db_regs = 0;
5791 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5792 vcpu->arch.dr6 = DR6_FIXED_1;
5793 vcpu->arch.dr7 = DR7_FIXED_1;
5794
3842d135
AK		 5795 kvm_make_request(KVM_REQ_EVENT, vcpu);
5796
e9b11c17
ZX		 5797 return kvm_x86_ops->vcpu_reset(vcpu);
5798}
5799
10474ae8 5800int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5801{
ca84d1a2
ZA		 5802 struct kvm *kvm;
5803 struct kvm_vcpu *vcpu;
5804 int i;
18863bdd
AK		 5805
5806 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5807 list_for_each_entry(kvm, &vm_list, vm_list)
5808 kvm_for_each_vcpu(i, vcpu, kvm)
5809 if (vcpu->cpu == smp_processor_id())
c285545f 5810 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5811 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5812}
5813
5814void kvm_arch_hardware_disable(void *garbage)
5815{
5816 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5817 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5818}
5819
5820int kvm_arch_hardware_setup(void)
5821{
5822 return kvm_x86_ops->hardware_setup();
5823}
5824
5825void kvm_arch_hardware_unsetup(void)
5826{
5827 kvm_x86_ops->hardware_unsetup();
5828}
5829
5830void kvm_arch_check_processor_compat(void *rtn)
5831{
5832 kvm_x86_ops->check_processor_compatibility(rtn);
5833}
5834
5835int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5836{
5837 struct page *page;
5838 struct kvm *kvm;
5839 int r;
5840
5841 BUG_ON(vcpu->kvm == NULL);
5842 kvm = vcpu->kvm;
5843
9aabc88f 5844 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5845 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5846 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5847 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5848 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5849 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5850 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5851 else
a4535290 5852 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5853
5854 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5855 if (!page) {
5856 r = -ENOMEM;
5857 goto fail;
5858 }
ad312c7c 5859 vcpu->arch.pio_data = page_address(page);
e9b11c17 5860
c285545f
ZA		 5861 if (!kvm->arch.virtual_tsc_khz)
5862 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5863
e9b11c17
ZX		 5864 r = kvm_mmu_create(vcpu);
5865 if (r < 0)
5866 goto fail_free_pio_data;
5867
5868 if (irqchip_in_kernel(kvm)) {
5869 r = kvm_create_lapic(vcpu);
5870 if (r < 0)
5871 goto fail_mmu_destroy;
5872 }
5873
890ca9ae
HY		 5874 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5875 GFP_KERNEL);
5876 if (!vcpu->arch.mce_banks) {
5877 r = -ENOMEM;
443c39bc 5878 goto fail_free_lapic;
890ca9ae
HY		 5879 }
5880 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5881
f5f48ee1
SY		 5882 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5883 goto fail_free_mce_banks;
5884
e9b11c17 5885 return 0;
f5f48ee1
SY		 5886fail_free_mce_banks:
5887 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5888fail_free_lapic:
5889 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5890fail_mmu_destroy:
5891 kvm_mmu_destroy(vcpu);
5892fail_free_pio_data:
ad312c7c 5893 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5894fail:
5895 return r;
5896}
5897
5898void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5899{
f656ce01
MT		 5900 int idx;
5901
36cb93fd 5902 kfree(vcpu->arch.mce_banks);
e9b11c17 5903 kvm_free_lapic(vcpu);
f656ce01 5904 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5905 kvm_mmu_destroy(vcpu);
f656ce01 5906 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5907 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5908}
d19a9cd2
ZX		 5909
5910struct kvm *kvm_arch_create_vm(void)
5911{
5912 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5913
5914 if (!kvm)
5915 return ERR_PTR(-ENOMEM);
5916
f05e70ac 5917 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5918 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5919
5550af4d
SY		 5920 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5921 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5922
99e3e30a 5923 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5924
d19a9cd2
ZX		 5925 return kvm;
5926}
5927
5928static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5929{
5930 vcpu_load(vcpu);
5931 kvm_mmu_unload(vcpu);
5932 vcpu_put(vcpu);
5933}
5934
5935static void kvm_free_vcpus(struct kvm *kvm)
5936{
5937 unsigned int i;
988a2cae 5938 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5939
5940 /*
5941 * Unpin any mmu pages first.
5942 */
988a2cae
GN		 5943 kvm_for_each_vcpu(i, vcpu, kvm)
5944 kvm_unload_vcpu_mmu(vcpu);
5945 kvm_for_each_vcpu(i, vcpu, kvm)
5946 kvm_arch_vcpu_free(vcpu);
5947
5948 mutex_lock(&kvm->lock);
5949 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5950 kvm->vcpus[i] = NULL;
d19a9cd2 5951
988a2cae
GN		 5952 atomic_set(&kvm->online_vcpus, 0);
5953 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5954}
5955
ad8ba2cd
SY		 5956void kvm_arch_sync_events(struct kvm *kvm)
5957{
ba4cef31 5958 kvm_free_all_assigned_devices(kvm);
aea924f6 5959 kvm_free_pit(kvm);
ad8ba2cd
SY		 5960}
5961
d19a9cd2
ZX		 5962void kvm_arch_destroy_vm(struct kvm *kvm)
5963{
6eb55818 5964 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5965 kfree(kvm->arch.vpic);
5966 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5967 kvm_free_vcpus(kvm);
5968 kvm_free_physmem(kvm);
3d45830c
AK		 5969 if (kvm->arch.apic_access_page)
5970 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5971 if (kvm->arch.ept_identity_pagetable)
5972 put_page(kvm->arch.ept_identity_pagetable);
64749204 5973 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5974 kfree(kvm);
5975}
0de10343 5976
f7784b8e
MT		 5977int kvm_arch_prepare_memory_region(struct kvm *kvm,
5978 struct kvm_memory_slot *memslot,
0de10343 5979 struct kvm_memory_slot old,
f7784b8e 5980 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5981 int user_alloc)
5982{
f7784b8e 5983 int npages = memslot->npages;
7ac77099
AK		 5984 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5985
5986 /* Prevent internal slot pages from being moved by fork()/COW. */
5987 if (memslot->id >= KVM_MEMORY_SLOTS)
5988 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5989
5990 /*To keep backward compatibility with older userspace,
5991 *x86 needs to hanlde !user_alloc case.
5992 */
5993 if (!user_alloc) {
5994 if (npages && !old.rmap) {
604b38ac
AA		 5995 unsigned long userspace_addr;
5996
72dc67a6 5997 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5998 userspace_addr = do_mmap(NULL, 0,
5999 npages * PAGE_SIZE,
6000 PROT_READ | PROT_WRITE,
7ac77099 6001 map_flags,
604b38ac 6002 0);
72dc67a6 6003 up_write(&current->mm->mmap_sem);
0de10343 6004
604b38ac
AA		 6005 if (IS_ERR((void *)userspace_addr))
6006 return PTR_ERR((void *)userspace_addr);
6007
604b38ac 6008 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6009 }
6010 }
6011
f7784b8e
MT		 6012
6013 return 0;
6014}
6015
6016void kvm_arch_commit_memory_region(struct kvm *kvm,
6017 struct kvm_userspace_memory_region *mem,
6018 struct kvm_memory_slot old,
6019 int user_alloc)
6020{
6021
6022 int npages = mem->memory_size >> PAGE_SHIFT;
6023
6024 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6025 int ret;
6026
6027 down_write(&current->mm->mmap_sem);
6028 ret = do_munmap(current->mm, old.userspace_addr,
6029 old.npages * PAGE_SIZE);
6030 up_write(&current->mm->mmap_sem);
6031 if (ret < 0)
6032 printk(KERN_WARNING
6033 "kvm_vm_ioctl_set_memory_region: "
6034 "failed to munmap memory\n");
6035 }
6036
7c8a83b7 6037 spin_lock(&kvm->mmu_lock);
f05e70ac 6038 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6039 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6040 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6041 }
6042
6043 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6044 spin_unlock(&kvm->mmu_lock);
0de10343 6045}
1d737c8a 6046
34d4cb8f
MT		 6047void kvm_arch_flush_shadow(struct kvm *kvm)
6048{
6049 kvm_mmu_zap_all(kvm);
8986ecc0 6050 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6051}
6052
1d737c8a
ZX		 6053int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6054{
a4535290 6055 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 6056 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6057 || vcpu->arch.nmi_pending ||
6058 (kvm_arch_interrupt_allowed(vcpu) &&
6059 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6060}
5736199a 6061
5736199a
ZX		 6062void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6063{
32f88400
MT		 6064 int me;
6065 int cpu = vcpu->cpu;
5736199a
ZX		 6066
6067 if (waitqueue_active(&vcpu->wq)) {
6068 wake_up_interruptible(&vcpu->wq);
6069 ++vcpu->stat.halt_wakeup;
6070 }
32f88400
MT		 6071
6072 me = get_cpu();
6073 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6074 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6075 smp_send_reschedule(cpu);
e9571ed5 6076 put_cpu();
5736199a 6077}
78646121
GN		 6078
6079int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6080{
6081 return kvm_x86_ops->interrupt_allowed(vcpu);
6082}
229456fc 6083
f92653ee
JK		 6084bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6085{
6086 unsigned long current_rip = kvm_rip_read(vcpu) +
6087 get_segment_base(vcpu, VCPU_SREG_CS);
6088
6089 return current_rip == linear_rip;
6090}
6091EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6092
94fe45da
JK		 6093unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6094{
6095 unsigned long rflags;
6096
6097 rflags = kvm_x86_ops->get_rflags(vcpu);
6098 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6099 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6100 return rflags;
6101}
6102EXPORT_SYMBOL_GPL(kvm_get_rflags);
6103
6104void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6105{
6106 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6107 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6108 rflags |= X86_EFLAGS_TF;
94fe45da 6109 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6110 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6111}
6112EXPORT_SYMBOL_GPL(kvm_set_rflags);
6113
229456fc
MT		 6114EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6115EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6116EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6117EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6118EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6119EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6120EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6121EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6122EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6123EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6124EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6125EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)